projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| fa590c22 MC |
1 | /* Driver for Realtek PCI-Express card reader |
| 2 | * Header file | |
| 3 | * | |
| 4 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify it | |
| 7 | * under the terms of the GNU General Public License as published by the | |
| 8 | * Free Software Foundation; either version 2, or (at your option) any | |
| 9 | * later version. | |
| 10 | * | |
| 11 | * This program is distributed in the hope that it will be useful, but | |
| 12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 14 | * General Public License for more details. | |
| 15 | * | |
| 16 | * You should have received a copy of the GNU General Public License along | |
| 17 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
| 18 | * | |
| 19 | * Author: | |
| 20 | * Wei WANG (wei_wang@realsil.com.cn) | |
| 21 | * Micky Ching (micky_ching@realsil.com.cn) | |
| 22 | */ | |
| 23 | ||
| 24 | #ifndef __REALTEK_RTSX_CHIP_H | |
| 25 | #define __REALTEK_RTSX_CHIP_H | |
| 26 | ||
| 27 | #include "rtsx.h" | |
| 28 | ||
| 29 | #define SUPPORT_CPRM | |
| 30 | #define SUPPORT_OCP | |
| 31 | #define SUPPORT_SDIO_ASPM | |
| 32 | #define SUPPORT_MAGIC_GATE | |
| 33 | #define SUPPORT_MSXC | |
| 34 | #define SUPPORT_SD_LOCK | |
| 35 | /* Hardware switch bus_ctl and cd_ctl automatically */ | |
| 36 | #define HW_AUTO_SWITCH_SD_BUS | |
| 37 | /* Enable hardware interrupt write clear */ | |
| 38 | #define HW_INT_WRITE_CLR | |
| 39 | /* #define LED_AUTO_BLINK */ | |
| 40 | /* #define DISABLE_CARD_INT */ | |
| 41 | ||
| 42 | #ifdef SUPPORT_MAGIC_GATE | |
| 43 | /* Using NORMAL_WRITE instead of AUTO_WRITE to set ICV */ | |
| 44 | #define MG_SET_ICV_SLOW | |
| 45 | /* HW may miss ERR/CMDNK signal when sampling INT status. */ | |
| 46 | #define MS_SAMPLE_INT_ERR | |
| e89ac165 SP |
47 | /* |
| 48 | * HW DO NOT support Wait_INT function | |
| 49 | * during READ_BYTES transfer mode | |
| 50 | */ | |
| fa590c22 MC |
51 | #define READ_BYTES_WAIT_INT |
| 52 | #endif | |
| 53 | ||
| 54 | #ifdef SUPPORT_MSXC | |
| 55 | #define XC_POWERCLASS | |
| 56 | #define SUPPORT_PCGL_1P18 | |
| 57 | #endif | |
| 58 | ||
| 59 | #ifndef LED_AUTO_BLINK | |
| 60 | #define REGULAR_BLINK | |
| 61 | #endif | |
| 62 | ||
| 63 | #define LED_BLINK_SPEED 5 | |
| 64 | #define LED_TOGGLE_INTERVAL 6 | |
| 65 | #define GPIO_TOGGLE_THRESHOLD 1024 | |
| 66 | #define LED_GPIO 0 | |
| 67 | ||
| 68 | #define POLLING_INTERVAL 30 | |
| 69 | ||
| 70 | #define TRACE_ITEM_CNT 64 | |
| 71 | ||
| 72 | #ifndef STATUS_SUCCESS | |
| 73 | #define STATUS_SUCCESS 0 | |
| 74 | #endif | |
| 75 | #ifndef STATUS_FAIL | |
| 76 | #define STATUS_FAIL 1 | |
| 77 | #endif | |
| 78 | #ifndef STATUS_TIMEDOUT | |
| 79 | #define STATUS_TIMEDOUT 2 | |
| 80 | #endif | |
| 81 | #ifndef STATUS_NOMEM | |
| 82 | #define STATUS_NOMEM 3 | |
| 83 | #endif | |
| 84 | #ifndef STATUS_READ_FAIL | |
| 85 | #define STATUS_READ_FAIL 4 | |
| 86 | #endif | |
| 87 | #ifndef STATUS_WRITE_FAIL | |
| 88 | #define STATUS_WRITE_FAIL 5 | |
| 89 | #endif | |
| 90 | #ifndef STATUS_ERROR | |
| 91 | #define STATUS_ERROR 10 | |
| 92 | #endif | |
| 93 | ||
| 94 | #define PM_S1 1 | |
| 95 | #define PM_S3 3 | |
| 96 | ||
| 97 | /* | |
| 98 | * Transport return codes | |
| 99 | */ | |
| 100 | ||
| 101 | #define TRANSPORT_GOOD 0 /* Transport good, command good */ | |
| 102 | #define TRANSPORT_FAILED 1 /* Transport good, command failed */ | |
| 103 | #define TRANSPORT_NO_SENSE 2 /* Command failed, no auto-sense */ | |
| 104 | #define TRANSPORT_ERROR 3 /* Transport bad (i.e. device dead) */ | |
| 105 | ||
| e89ac165 SP |
106 | /* |
| 107 | * Start-Stop-Unit | |
| 108 | */ | |
| fa590c22 MC |
109 | #define STOP_MEDIUM 0x00 /* access disable */ |
| 110 | #define MAKE_MEDIUM_READY 0x01 /* access enable */ | |
| 111 | #define UNLOAD_MEDIUM 0x02 /* unload */ | |
| 112 | #define LOAD_MEDIUM 0x03 /* load */ | |
| 113 | ||
| e89ac165 SP |
114 | /* |
| 115 | * STANDARD_INQUIRY | |
| 116 | */ | |
| fa590c22 MC |
117 | #define QULIFIRE 0x00 |
| 118 | #define AENC_FNC 0x00 | |
| 119 | #define TRML_IOP 0x00 | |
| 120 | #define REL_ADR 0x00 | |
| 121 | #define WBUS_32 0x00 | |
| 122 | #define WBUS_16 0x00 | |
| 123 | #define SYNC 0x00 | |
| 124 | #define LINKED 0x00 | |
| 125 | #define CMD_QUE 0x00 | |
| 126 | #define SFT_RE 0x00 | |
| 127 | ||
| 128 | #define VEN_ID_LEN 8 /* Vendor ID Length */ | |
| 129 | #define PRDCT_ID_LEN 16 /* Product ID Length */ | |
| 130 | #define PRDCT_REV_LEN 4 /* Product LOT Length */ | |
| 131 | ||
| 132 | /* Dynamic flag definitions: used in set_bit() etc. */ | |
| e89ac165 SP |
133 | #define RTSX_FLIDX_TRANS_ACTIVE 18 /* 0x00040000 transfer is active */ |
| 134 | #define RTSX_FLIDX_ABORTING 20 /* 0x00100000 abort is in progress */ | |
| 135 | #define RTSX_FLIDX_DISCONNECTING 21 /* 0x00200000 disconnect in progress */ | |
| 136 | ||
| fa590c22 MC |
137 | #define ABORTING_OR_DISCONNECTING ((1UL << US_FLIDX_ABORTING) | \ |
| 138 | (1UL << US_FLIDX_DISCONNECTING)) | |
| e89ac165 SP |
139 | |
| 140 | #define RTSX_FLIDX_RESETTING 22 /* 0x00400000 device reset in progress */ | |
| 141 | #define RTSX_FLIDX_TIMED_OUT 23 /* 0x00800000 SCSI midlayer timed out */ | |
| fa590c22 MC |
142 | |
| 143 | #define DRCT_ACCESS_DEV 0x00 /* Direct Access Device */ | |
| 144 | #define RMB_DISC 0x80 /* The Device is Removable */ | |
| 145 | #define ANSI_SCSI2 0x02 /* Based on ANSI-SCSI2 */ | |
| 146 | ||
| 147 | #define SCSI 0x00 /* Interface ID */ | |
| 148 | ||
| 149 | #define WRITE_PROTECTED_MEDIA 0x07 | |
| 150 | ||
| 151 | /*---- sense key ----*/ | |
| 152 | #define ILI 0x20 /* ILI bit is on */ | |
| 153 | ||
| 154 | #define NO_SENSE 0x00 /* not exist sense key */ | |
| 155 | #define RECOVER_ERR 0x01 /* Target/Logical unit is recoverd */ | |
| 156 | #define NOT_READY 0x02 /* Logical unit is not ready */ | |
| 157 | #define MEDIA_ERR 0x03 /* medium/data error */ | |
| 158 | #define HARDWARE_ERR 0x04 /* hardware error */ | |
| 159 | #define ILGAL_REQ 0x05 /* CDB/parameter/identify msg error */ | |
| 160 | #define UNIT_ATTENTION 0x06 /* unit attention condition occur */ | |
| 161 | #define DAT_PRTCT 0x07 /* read/write is desable */ | |
| 162 | #define BLNC_CHK 0x08 /* find blank/DOF in read */ | |
| 163 | /* write to unblank area */ | |
| 164 | #define CPY_ABRT 0x0a /* Copy/Compare/Copy&Verify illgal */ | |
| 165 | #define ABRT_CMD 0x0b /* Target make the command in error */ | |
| 166 | #define EQUAL 0x0c /* Search Data end with Equal */ | |
| 167 | #define VLM_OVRFLW 0x0d /* Some data are left in buffer */ | |
| 168 | #define MISCMP 0x0e /* find inequality */ | |
| 169 | ||
| 170 | #define READ_ERR -1 | |
| 171 | #define WRITE_ERR -2 | |
| 172 | ||
| 173 | #define FIRST_RESET 0x01 | |
| 174 | #define USED_EXIST 0x02 | |
| 175 | ||
| e89ac165 SP |
176 | /* |
| 177 | * SENSE_DATA | |
| 178 | */ | |
| fa590c22 MC |
179 | /*---- valid ----*/ |
| 180 | #define SENSE_VALID 0x80 /* Sense data is valid as SCSI2 */ | |
| 181 | #define SENSE_INVALID 0x00 /* Sense data is invalid as SCSI2 */ | |
| 182 | ||
| 183 | /*---- error code ----*/ | |
| 184 | #define CUR_ERR 0x70 /* current error */ | |
| 185 | #define DEF_ERR 0x71 /* specific command error */ | |
| 186 | ||
| 187 | /*---- sense key Information ----*/ | |
| 188 | #define SNSKEYINFO_LEN 3 /* length of sense key information */ | |
| 189 | ||
| 190 | #define SKSV 0x80 | |
| 191 | #define CDB_ILLEGAL 0x40 | |
| 192 | #define DAT_ILLEGAL 0x00 | |
| 193 | #define BPV 0x08 | |
| 194 | #define BIT_ILLEGAL0 0 /* bit0 is illegal */ | |
| 195 | #define BIT_ILLEGAL1 1 /* bit1 is illegal */ | |
| 196 | #define BIT_ILLEGAL2 2 /* bit2 is illegal */ | |
| 197 | #define BIT_ILLEGAL3 3 /* bit3 is illegal */ | |
| 198 | #define BIT_ILLEGAL4 4 /* bit4 is illegal */ | |
| 199 | #define BIT_ILLEGAL5 5 /* bit5 is illegal */ | |
| 200 | #define BIT_ILLEGAL6 6 /* bit6 is illegal */ | |
| 201 | #define BIT_ILLEGAL7 7 /* bit7 is illegal */ | |
| 202 | ||
| 203 | /*---- ASC ----*/ | |
| 204 | #define ASC_NO_INFO 0x00 | |
| 205 | #define ASC_MISCMP 0x1d | |
| 206 | #define ASC_INVLD_CDB 0x24 | |
| 207 | #define ASC_INVLD_PARA 0x26 | |
| 208 | #define ASC_LU_NOT_READY 0x04 | |
| 209 | #define ASC_WRITE_ERR 0x0c | |
| 210 | #define ASC_READ_ERR 0x11 | |
| 211 | #define ASC_LOAD_EJCT_ERR 0x53 | |
| 212 | #define ASC_MEDIA_NOT_PRESENT 0x3A | |
| 213 | #define ASC_MEDIA_CHANGED 0x28 | |
| 214 | #define ASC_MEDIA_IN_PROCESS 0x04 | |
| 215 | #define ASC_WRITE_PROTECT 0x27 | |
| 216 | #define ASC_LUN_NOT_SUPPORTED 0x25 | |
| 217 | ||
| 218 | /*---- ASQC ----*/ | |
| 219 | #define ASCQ_NO_INFO 0x00 | |
| 220 | #define ASCQ_MEDIA_IN_PROCESS 0x01 | |
| 221 | #define ASCQ_MISCMP 0x00 | |
| 222 | #define ASCQ_INVLD_CDB 0x00 | |
| 223 | #define ASCQ_INVLD_PARA 0x02 | |
| 224 | #define ASCQ_LU_NOT_READY 0x02 | |
| 225 | #define ASCQ_WRITE_ERR 0x02 | |
| 226 | #define ASCQ_READ_ERR 0x00 | |
| 227 | #define ASCQ_LOAD_EJCT_ERR 0x00 | |
| 228 | #define ASCQ_WRITE_PROTECT 0x00 | |
| 229 | ||
| fa590c22 MC |
230 | struct sense_data_t { |
| 231 | unsigned char err_code; /* error code */ | |
| 232 | /* bit7 : valid */ | |
| 233 | /* (1 : SCSI2) */ | |
| 234 | /* (0 : Vendor * specific) */ | |
| 235 | /* bit6-0 : error * code */ | |
| 236 | /* (0x70 : current * error) */ | |
| 237 | /* (0x71 : specific command error) */ | |
| 238 | unsigned char seg_no; /* segment No. */ | |
| 239 | unsigned char sense_key; /* byte5 : ILI */ | |
| 240 | /* bit3-0 : sense key */ | |
| 241 | unsigned char info[4]; /* information */ | |
| 242 | unsigned char ad_sense_len; /* additional sense data length */ | |
| 243 | unsigned char cmd_info[4]; /* command specific information */ | |
| 244 | unsigned char asc; /* ASC */ | |
| 245 | unsigned char ascq; /* ASCQ */ | |
| 246 | unsigned char rfu; /* FRU */ | |
| 247 | unsigned char sns_key_info[3];/* sense key specific information */ | |
| 248 | }; | |
| 249 | ||
| 250 | /* PCI Operation Register Address */ | |
| 251 | #define RTSX_HCBAR 0x00 | |
| 252 | #define RTSX_HCBCTLR 0x04 | |
| 253 | #define RTSX_HDBAR 0x08 | |
| 254 | #define RTSX_HDBCTLR 0x0C | |
| 255 | #define RTSX_HAIMR 0x10 | |
| 256 | #define RTSX_BIPR 0x14 | |
| 257 | #define RTSX_BIER 0x18 | |
| 258 | ||
| 259 | /* Host command buffer control register */ | |
| 260 | #define STOP_CMD (0x01 << 28) | |
| 261 | ||
| 262 | /* Host data buffer control register */ | |
| 263 | #define SDMA_MODE 0x00 | |
| 264 | #define ADMA_MODE (0x02 << 26) | |
| 265 | #define STOP_DMA (0x01 << 28) | |
| 266 | #define TRIG_DMA (0x01 << 31) | |
| 267 | ||
| 268 | /* Bus interrupt pending register */ | |
| eceef9a3 RS |
269 | #define CMD_DONE_INT BIT(31) |
| 270 | #define DATA_DONE_INT BIT(30) | |
| 271 | #define TRANS_OK_INT BIT(29) | |
| 272 | #define TRANS_FAIL_INT BIT(28) | |
| 273 | #define XD_INT BIT(27) | |
| 274 | #define MS_INT BIT(26) | |
| 275 | #define SD_INT BIT(25) | |
| 276 | #define GPIO0_INT BIT(24) | |
| 277 | #define OC_INT BIT(23) | |
| 278 | #define SD_WRITE_PROTECT BIT(19) | |
| 279 | #define XD_EXIST BIT(18) | |
| 280 | #define MS_EXIST BIT(17) | |
| 281 | #define SD_EXIST BIT(16) | |
| fa590c22 | 282 | #define DELINK_INT GPIO0_INT |
| eceef9a3 RS |
283 | #define MS_OC_INT BIT(23) |
| 284 | #define SD_OC_INT BIT(22) | |
| fa590c22 MC |
285 | |
| 286 | #define CARD_INT (XD_INT | MS_INT | SD_INT) | |
| 287 | #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT) | |
| 288 | #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | CARD_INT | GPIO0_INT | OC_INT) | |
| 289 | ||
| 290 | #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST) | |
| 291 | ||
| 292 | /* Bus interrupt enable register */ | |
| 293 | #define CMD_DONE_INT_EN (1 << 31) | |
| 294 | #define DATA_DONE_INT_EN (1 << 30) | |
| 295 | #define TRANS_OK_INT_EN (1 << 29) | |
| 296 | #define TRANS_FAIL_INT_EN (1 << 28) | |
| 297 | #define XD_INT_EN (1 << 27) | |
| 298 | #define MS_INT_EN (1 << 26) | |
| 299 | #define SD_INT_EN (1 << 25) | |
| 300 | #define GPIO0_INT_EN (1 << 24) | |
| 301 | #define OC_INT_EN (1 << 23) | |
| 302 | #define DELINK_INT_EN GPIO0_INT_EN | |
| 303 | #define MS_OC_INT_EN (1 << 23) | |
| 304 | #define SD_OC_INT_EN (1 << 22) | |
| 305 | ||
| fa590c22 MC |
306 | #define READ_REG_CMD 0 |
| 307 | #define WRITE_REG_CMD 1 | |
| 308 | #define CHECK_REG_CMD 2 | |
| 309 | ||
| 310 | #define HOST_TO_DEVICE 0 | |
| 311 | #define DEVICE_TO_HOST 1 | |
| 312 | ||
| fa590c22 MC |
313 | #define RTSX_RESV_BUF_LEN 4096 |
| 314 | #define HOST_CMDS_BUF_LEN 1024 | |
| 315 | #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN) | |
| 316 | ||
| 317 | #define SD_NR 2 | |
| 318 | #define MS_NR 3 | |
| 319 | #define XD_NR 4 | |
| 320 | #define SPI_NR 7 | |
| 321 | #define SD_CARD (1 << SD_NR) | |
| 322 | #define MS_CARD (1 << MS_NR) | |
| 323 | #define XD_CARD (1 << XD_NR) | |
| 324 | #define SPI_CARD (1 << SPI_NR) | |
| 325 | ||
| 326 | #define MAX_ALLOWED_LUN_CNT 8 | |
| 327 | ||
| 328 | #define XD_FREE_TABLE_CNT 1200 | |
| 329 | #define MS_FREE_TABLE_CNT 512 | |
| 330 | ||
| fa590c22 MC |
331 | /* Bit Operation */ |
| 332 | #define SET_BIT(data, idx) ((data) |= 1 << (idx)) | |
| 333 | #define CLR_BIT(data, idx) ((data) &= ~(1 << (idx))) | |
| 334 | #define CHK_BIT(data, idx) ((data) & (1 << (idx))) | |
| 335 | ||
| 336 | /* SG descriptor */ | |
| 337 | #define SG_INT 0x04 | |
| 338 | #define SG_END 0x02 | |
| 339 | #define SG_VALID 0x01 | |
| 340 | ||
| 341 | #define SG_NO_OP 0x00 | |
| 342 | #define SG_TRANS_DATA (0x02 << 4) | |
| 343 | #define SG_LINK_DESC (0x03 << 4) | |
| 344 | ||
| 345 | struct rtsx_chip; | |
| 346 | ||
| 347 | typedef int (*card_rw_func)(struct scsi_cmnd *srb, struct rtsx_chip *chip, | |
| 348 | u32 sec_addr, u16 sec_cnt); | |
| 349 | ||
| 350 | /* Supported Clock */ | |
| 351 | enum card_clock {CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60, | |
| 352 | CLK_80, CLK_100, CLK_120, CLK_150, CLK_200}; | |
| 353 | ||
| 354 | enum RTSX_STAT {RTSX_STAT_INIT, RTSX_STAT_IDLE, RTSX_STAT_RUN, RTSX_STAT_SS, | |
| 355 | RTSX_STAT_DELINK, RTSX_STAT_SUSPEND, | |
| 356 | RTSX_STAT_ABORT, RTSX_STAT_DISCONNECT}; | |
| 357 | enum IC_VER {IC_VER_AB, IC_VER_C = 2, IC_VER_D = 3}; | |
| 358 | ||
| 359 | #define MAX_RESET_CNT 3 | |
| 360 | ||
| 361 | /* For MS Card */ | |
| 362 | #define MAX_DEFECTIVE_BLOCK 10 | |
| 363 | ||
| 364 | struct zone_entry { | |
| 365 | u16 *l2p_table; | |
| 366 | u16 *free_table; | |
| 367 | u16 defect_list[MAX_DEFECTIVE_BLOCK]; /* For MS card only */ | |
| 368 | int set_index; | |
| 369 | int get_index; | |
| 370 | int unused_blk_cnt; | |
| 371 | int disable_count; | |
| 372 | /* To indicate whether the L2P table of this zone has been built. */ | |
| 373 | int build_flag; | |
| 374 | }; | |
| 375 | ||
| 376 | #define TYPE_SD 0x0000 | |
| 377 | #define TYPE_MMC 0x0001 | |
| 378 | ||
| 379 | /* TYPE_SD */ | |
| 380 | #define SD_HS 0x0100 | |
| 381 | #define SD_SDR50 0x0200 | |
| 382 | #define SD_DDR50 0x0400 | |
| 383 | #define SD_SDR104 0x0800 | |
| 384 | #define SD_HCXC 0x1000 | |
| 385 | ||
| 386 | /* TYPE_MMC */ | |
| 387 | #define MMC_26M 0x0100 | |
| 388 | #define MMC_52M 0x0200 | |
| 389 | #define MMC_4BIT 0x0400 | |
| 390 | #define MMC_8BIT 0x0800 | |
| 391 | #define MMC_SECTOR_MODE 0x1000 | |
| 392 | #define MMC_DDR52 0x2000 | |
| 393 | ||
| 394 | /* SD card */ | |
| 395 | #define CHK_SD(sd_card) (((sd_card)->sd_type & 0xFF) == TYPE_SD) | |
| 396 | #define CHK_SD_HS(sd_card) (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HS)) | |
| 397 | #define CHK_SD_SDR50(sd_card) (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR50)) | |
| 398 | #define CHK_SD_DDR50(sd_card) (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_DDR50)) | |
| 399 | #define CHK_SD_SDR104(sd_card) (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_SDR104)) | |
| 400 | #define CHK_SD_HCXC(sd_card) (CHK_SD(sd_card) && ((sd_card)->sd_type & SD_HCXC)) | |
| 401 | #define CHK_SD_HC(sd_card) (CHK_SD_HCXC(sd_card) && ((sd_card)->capacity <= 0x4000000)) | |
| 402 | #define CHK_SD_XC(sd_card) (CHK_SD_HCXC(sd_card) && ((sd_card)->capacity > 0x4000000)) | |
| 403 | #define CHK_SD30_SPEED(sd_card) (CHK_SD_SDR50(sd_card) || CHK_SD_DDR50(sd_card) || CHK_SD_SDR104(sd_card)) | |
| 404 | ||
| 405 | #define SET_SD(sd_card) ((sd_card)->sd_type = TYPE_SD) | |
| 406 | #define SET_SD_HS(sd_card) ((sd_card)->sd_type |= SD_HS) | |
| 407 | #define SET_SD_SDR50(sd_card) ((sd_card)->sd_type |= SD_SDR50) | |
| 408 | #define SET_SD_DDR50(sd_card) ((sd_card)->sd_type |= SD_DDR50) | |
| 409 | #define SET_SD_SDR104(sd_card) ((sd_card)->sd_type |= SD_SDR104) | |
| 410 | #define SET_SD_HCXC(sd_card) ((sd_card)->sd_type |= SD_HCXC) | |
| 411 | ||
| 412 | #define CLR_SD_HS(sd_card) ((sd_card)->sd_type &= ~SD_HS) | |
| 413 | #define CLR_SD_SDR50(sd_card) ((sd_card)->sd_type &= ~SD_SDR50) | |
| 414 | #define CLR_SD_DDR50(sd_card) ((sd_card)->sd_type &= ~SD_DDR50) | |
| 415 | #define CLR_SD_SDR104(sd_card) ((sd_card)->sd_type &= ~SD_SDR104) | |
| 416 | #define CLR_SD_HCXC(sd_card) ((sd_card)->sd_type &= ~SD_HCXC) | |
| 417 | ||
| 418 | /* MMC card */ | |
| 419 | #define CHK_MMC(sd_card) (((sd_card)->sd_type & 0xFF) == TYPE_MMC) | |
| 420 | #define CHK_MMC_26M(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_26M)) | |
| 421 | #define CHK_MMC_52M(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_52M)) | |
| 422 | #define CHK_MMC_4BIT(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_4BIT)) | |
| 423 | #define CHK_MMC_8BIT(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_8BIT)) | |
| 424 | #define CHK_MMC_SECTOR_MODE(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_SECTOR_MODE)) | |
| 425 | #define CHK_MMC_DDR52(sd_card) (CHK_MMC(sd_card) && ((sd_card)->sd_type & MMC_DDR52)) | |
| 426 | ||
| 427 | #define SET_MMC(sd_card) ((sd_card)->sd_type = TYPE_MMC) | |
| 428 | #define SET_MMC_26M(sd_card) ((sd_card)->sd_type |= MMC_26M) | |
| 429 | #define SET_MMC_52M(sd_card) ((sd_card)->sd_type |= MMC_52M) | |
| 430 | #define SET_MMC_4BIT(sd_card) ((sd_card)->sd_type |= MMC_4BIT) | |
| 431 | #define SET_MMC_8BIT(sd_card) ((sd_card)->sd_type |= MMC_8BIT) | |
| 432 | #define SET_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type |= MMC_SECTOR_MODE) | |
| 433 | #define SET_MMC_DDR52(sd_card) ((sd_card)->sd_type |= MMC_DDR52) | |
| 434 | ||
| 435 | #define CLR_MMC_26M(sd_card) ((sd_card)->sd_type &= ~MMC_26M) | |
| 436 | #define CLR_MMC_52M(sd_card) ((sd_card)->sd_type &= ~MMC_52M) | |
| 437 | #define CLR_MMC_4BIT(sd_card) ((sd_card)->sd_type &= ~MMC_4BIT) | |
| 438 | #define CLR_MMC_8BIT(sd_card) ((sd_card)->sd_type &= ~MMC_8BIT) | |
| 439 | #define CLR_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type &= ~MMC_SECTOR_MODE) | |
| 440 | #define CLR_MMC_DDR52(sd_card) ((sd_card)->sd_type &= ~MMC_DDR52) | |
| 441 | ||
| 442 | #define CHK_MMC_HS(sd_card) (CHK_MMC_52M(sd_card) && CHK_MMC_26M(sd_card)) | |
| 443 | #define CLR_MMC_HS(sd_card) \ | |
| 444 | do { \ | |
| 445 | CLR_MMC_DDR52(sd_card); \ | |
| 446 | CLR_MMC_52M(sd_card); \ | |
| 447 | CLR_MMC_26M(sd_card); \ | |
| 448 | } while (0) | |
| 449 | ||
| 450 | #define SD_SUPPORT_CLASS_TEN 0x01 | |
| 451 | #define SD_SUPPORT_1V8 0x02 | |
| 452 | ||
| 453 | #define SD_SET_CLASS_TEN(sd_card) ((sd_card)->sd_setting |= SD_SUPPORT_CLASS_TEN) | |
| 454 | #define SD_CHK_CLASS_TEN(sd_card) ((sd_card)->sd_setting & SD_SUPPORT_CLASS_TEN) | |
| 455 | #define SD_CLR_CLASS_TEN(sd_card) ((sd_card)->sd_setting &= ~SD_SUPPORT_CLASS_TEN) | |
| 456 | #define SD_SET_1V8(sd_card) ((sd_card)->sd_setting |= SD_SUPPORT_1V8) | |
| 457 | #define SD_CHK_1V8(sd_card) ((sd_card)->sd_setting & SD_SUPPORT_1V8) | |
| 458 | #define SD_CLR_1V8(sd_card) ((sd_card)->sd_setting &= ~SD_SUPPORT_1V8) | |
| 459 | ||
| 460 | struct sd_info { | |
| 461 | u16 sd_type; | |
| 462 | u8 err_code; | |
| 463 | u8 sd_data_buf_ready; | |
| 464 | u32 sd_addr; | |
| 465 | u32 capacity; | |
| 466 | ||
| 467 | u8 raw_csd[16]; | |
| 468 | u8 raw_scr[8]; | |
| 469 | ||
| 470 | /* Sequential RW */ | |
| 471 | int seq_mode; | |
| 472 | enum dma_data_direction pre_dir; | |
| 473 | u32 pre_sec_addr; | |
| 474 | u16 pre_sec_cnt; | |
| 475 | ||
| 476 | int cleanup_counter; | |
| 477 | ||
| 478 | int sd_clock; | |
| 479 | ||
| 480 | int mmc_dont_switch_bus; | |
| 481 | ||
| 482 | #ifdef SUPPORT_CPRM | |
| 483 | int sd_pass_thru_en; | |
| 484 | int pre_cmd_err; | |
| 485 | u8 last_rsp_type; | |
| 486 | u8 rsp[17]; | |
| 487 | #endif | |
| 488 | ||
| 489 | u8 func_group1_mask; | |
| 490 | u8 func_group2_mask; | |
| 491 | u8 func_group3_mask; | |
| 492 | u8 func_group4_mask; | |
| 493 | ||
| 494 | u8 sd_switch_fail; | |
| 495 | u8 sd_read_phase; | |
| 496 | ||
| 497 | #ifdef SUPPORT_SD_LOCK | |
| 498 | u8 sd_lock_status; | |
| 499 | u8 sd_erase_status; | |
| 500 | u8 sd_lock_notify; | |
| 501 | #endif | |
| 502 | int need_retune; | |
| 503 | }; | |
| 504 | ||
| 505 | struct xd_delay_write_tag { | |
| 506 | u32 old_phyblock; | |
| 507 | u32 new_phyblock; | |
| 508 | u32 logblock; | |
| 509 | u8 pageoff; | |
| 510 | u8 delay_write_flag; | |
| 511 | }; | |
| 512 | ||
| 513 | struct xd_info { | |
| 514 | u8 maker_code; | |
| 515 | u8 device_code; | |
| 516 | u8 block_shift; | |
| 517 | u8 page_off; | |
| 518 | u8 addr_cycle; | |
| 519 | u16 cis_block; | |
| 520 | u8 multi_flag; | |
| 521 | u8 err_code; | |
| 522 | u32 capacity; | |
| 523 | ||
| 524 | struct zone_entry *zone; | |
| 525 | int zone_cnt; | |
| 526 | ||
| 527 | struct xd_delay_write_tag delay_write; | |
| 528 | int cleanup_counter; | |
| 529 | ||
| 530 | int xd_clock; | |
| 531 | }; | |
| 532 | ||
| 533 | #define MODE_512_SEQ 0x01 | |
| 534 | #define MODE_2K_SEQ 0x02 | |
| 535 | ||
| 536 | #define TYPE_MS 0x0000 | |
| 537 | #define TYPE_MSPRO 0x0001 | |
| 538 | ||
| 539 | #define MS_4BIT 0x0100 | |
| 540 | #define MS_8BIT 0x0200 | |
| 541 | #define MS_HG 0x0400 | |
| 542 | #define MS_XC 0x0800 | |
| 543 | ||
| 544 | #define HG8BIT (MS_HG | MS_8BIT) | |
| 545 | ||
| 546 | #define CHK_MSPRO(ms_card) (((ms_card)->ms_type & 0xFF) == TYPE_MSPRO) | |
| 547 | #define CHK_HG8BIT(ms_card) (CHK_MSPRO(ms_card) && (((ms_card)->ms_type & HG8BIT) == HG8BIT)) | |
| 548 | #define CHK_MSXC(ms_card) (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_XC)) | |
| 549 | #define CHK_MSHG(ms_card) (CHK_MSPRO(ms_card) && ((ms_card)->ms_type & MS_HG)) | |
| 550 | ||
| 551 | #define CHK_MS8BIT(ms_card) (((ms_card)->ms_type & MS_8BIT)) | |
| 552 | #define CHK_MS4BIT(ms_card) (((ms_card)->ms_type & MS_4BIT)) | |
| 553 | ||
| 554 | struct ms_delay_write_tag { | |
| 555 | u16 old_phyblock; | |
| 556 | u16 new_phyblock; | |
| 557 | u16 logblock; | |
| 558 | u8 pageoff; | |
| 559 | u8 delay_write_flag; | |
| 560 | }; | |
| 561 | ||
| 562 | struct ms_info { | |
| 563 | u16 ms_type; | |
| 564 | u8 block_shift; | |
| 565 | u8 page_off; | |
| 566 | u16 total_block; | |
| 567 | u16 boot_block; | |
| 568 | u32 capacity; | |
| 569 | ||
| 570 | u8 check_ms_flow; | |
| 571 | u8 switch_8bit_fail; | |
| 572 | u8 err_code; | |
| 573 | ||
| 574 | struct zone_entry *segment; | |
| 575 | int segment_cnt; | |
| 576 | ||
| 577 | int pro_under_formatting; | |
| 578 | int format_status; | |
| 579 | u16 progress; | |
| 580 | u8 raw_sys_info[96]; | |
| 581 | #ifdef SUPPORT_PCGL_1P18 | |
| 582 | u8 raw_model_name[48]; | |
| 583 | #endif | |
| 584 | ||
| 585 | u8 multi_flag; | |
| 586 | ||
| 587 | /* Sequential RW */ | |
| 588 | u8 seq_mode; | |
| 589 | enum dma_data_direction pre_dir; | |
| 590 | u32 pre_sec_addr; | |
| 591 | u16 pre_sec_cnt; | |
| 592 | u32 total_sec_cnt; | |
| 593 | ||
| 594 | struct ms_delay_write_tag delay_write; | |
| 595 | ||
| 596 | int cleanup_counter; | |
| 597 | ||
| 598 | int ms_clock; | |
| 599 | ||
| 600 | #ifdef SUPPORT_MAGIC_GATE | |
| 601 | u8 magic_gate_id[16]; | |
| 602 | u8 mg_entry_num; | |
| 603 | int mg_auth; /* flag to indicate authentication process */ | |
| 604 | #endif | |
| 605 | }; | |
| 606 | ||
| 607 | struct spi_info { | |
| 608 | u8 use_clk; | |
| 609 | u8 write_en; | |
| 610 | u16 clk_div; | |
| 611 | u8 err_code; | |
| 612 | ||
| 613 | int spi_clock; | |
| 614 | }; | |
| 615 | ||
| fa590c22 MC |
616 | #ifdef _MSG_TRACE |
| 617 | struct trace_msg_t { | |
| 618 | u16 line; | |
| 619 | #define MSG_FUNC_LEN 64 | |
| 620 | char func[MSG_FUNC_LEN]; | |
| 621 | #define MSG_FILE_LEN 32 | |
| 622 | char file[MSG_FILE_LEN]; | |
| 623 | #define TIME_VAL_LEN 16 | |
| 624 | u8 timeval_buf[TIME_VAL_LEN]; | |
| 625 | u8 valid; | |
| 626 | }; | |
| 627 | #endif | |
| 628 | ||
| 629 | /************/ | |
| 630 | /* LUN mode */ | |
| 631 | /************/ | |
| 632 | /* Single LUN, support xD/SD/MS */ | |
| 633 | #define DEFAULT_SINGLE 0 | |
| 634 | /* 2 LUN mode, support SD/MS */ | |
| 635 | #define SD_MS_2LUN 1 | |
| 636 | /* Single LUN, but only support SD/MS, for Barossa LQFP */ | |
| 637 | #define SD_MS_1LUN 2 | |
| 638 | ||
| 639 | #define LAST_LUN_MODE 2 | |
| 640 | ||
| 641 | /* Barossa package */ | |
| 642 | #define QFN 0 | |
| 643 | #define LQFP 1 | |
| 644 | ||
| 645 | /******************/ | |
| 646 | /* sd_ctl bit map */ | |
| 647 | /******************/ | |
| 648 | /* SD push point control, bit 0, 1 */ | |
| 649 | #define SD_PUSH_POINT_CTL_MASK 0x03 | |
| 650 | #define SD_PUSH_POINT_DELAY 0x01 | |
| 651 | #define SD_PUSH_POINT_AUTO 0x02 | |
| 652 | /* SD sample point control, bit 2, 3 */ | |
| 653 | #define SD_SAMPLE_POINT_CTL_MASK 0x0C | |
| 654 | #define SD_SAMPLE_POINT_DELAY 0x04 | |
| 655 | #define SD_SAMPLE_POINT_AUTO 0x08 | |
| 656 | /* SD DDR Tx phase set by user, bit 4 */ | |
| 657 | #define SD_DDR_TX_PHASE_SET_BY_USER 0x10 | |
| 658 | /* MMC DDR Tx phase set by user, bit 5 */ | |
| 659 | #define MMC_DDR_TX_PHASE_SET_BY_USER 0x20 | |
| 660 | /* Support MMC DDR mode, bit 6 */ | |
| 661 | #define SUPPORT_MMC_DDR_MODE 0x40 | |
| 662 | /* Reset MMC at first */ | |
| 663 | #define RESET_MMC_FIRST 0x80 | |
| 664 | ||
| 665 | #define SEQ_START_CRITERIA 0x20 | |
| 666 | ||
| 667 | /* MS Power Class En */ | |
| 668 | #define POWER_CLASS_2_EN 0x02 | |
| 669 | #define POWER_CLASS_1_EN 0x01 | |
| 670 | ||
| 671 | #define MAX_SHOW_CNT 10 | |
| 672 | #define MAX_RESET_CNT 3 | |
| 673 | ||
| 674 | #define SDIO_EXIST 0x01 | |
| 675 | #define SDIO_IGNORED 0x02 | |
| 676 | ||
| 677 | #define CHK_SDIO_EXIST(chip) ((chip)->sdio_func_exist & SDIO_EXIST) | |
| 678 | #define SET_SDIO_EXIST(chip) ((chip)->sdio_func_exist |= SDIO_EXIST) | |
| 679 | #define CLR_SDIO_EXIST(chip) ((chip)->sdio_func_exist &= ~SDIO_EXIST) | |
| 680 | ||
| 681 | #define CHK_SDIO_IGNORED(chip) ((chip)->sdio_func_exist & SDIO_IGNORED) | |
| 682 | #define SET_SDIO_IGNORED(chip) ((chip)->sdio_func_exist |= SDIO_IGNORED) | |
| 683 | #define CLR_SDIO_IGNORED(chip) ((chip)->sdio_func_exist &= ~SDIO_IGNORED) | |
| 684 | ||
| 685 | struct rtsx_chip { | |
| 8e7e0a96 | 686 | struct rtsx_dev *rtsx; |
| fa590c22 MC |
687 | |
| 688 | u32 int_reg; /* Bus interrupt pending register */ | |
| 689 | char max_lun; | |
| 690 | void *context; | |
| 691 | ||
| 692 | void *host_cmds_ptr; /* host commands buffer pointer */ | |
| 693 | dma_addr_t host_cmds_addr; | |
| 694 | int ci; /* Command Index */ | |
| 695 | ||
| 696 | void *host_sg_tbl_ptr; /* SG descriptor table */ | |
| 697 | dma_addr_t host_sg_tbl_addr; | |
| 698 | int sgi; /* SG entry index */ | |
| 699 | ||
| 700 | struct scsi_cmnd *srb; /* current srb */ | |
| 701 | struct sense_data_t sense_buffer[MAX_ALLOWED_LUN_CNT]; | |
| 702 | ||
| 703 | int cur_clk; /* current card clock */ | |
| 704 | ||
| 705 | /* Current accessed card */ | |
| 706 | int cur_card; | |
| 707 | ||
| 708 | unsigned long need_release; /* need release bit map */ | |
| e89ac165 SP |
709 | unsigned long need_reset; /* need reset bit map */ |
| 710 | /* | |
| 711 | * Flag to indicate that this card is just resumed from SS state, | |
| fa590c22 MC |
712 | * and need released before being resetted |
| 713 | */ | |
| 714 | unsigned long need_reinit; | |
| 715 | ||
| 716 | int rw_need_retry; | |
| 717 | ||
| 718 | #ifdef SUPPORT_OCP | |
| 719 | u32 ocp_int; | |
| 720 | u8 ocp_stat; | |
| 721 | #endif | |
| 722 | ||
| 723 | u8 card_exist; /* card exist bit map (physical exist) */ | |
| 724 | u8 card_ready; /* card ready bit map (reset successfully) */ | |
| 725 | u8 card_fail; /* card reset fail bit map */ | |
| 726 | u8 card_ejected; /* card ejected bit map */ | |
| 727 | u8 card_wp; /* card write protected bit map */ | |
| 728 | ||
| e89ac165 SP |
729 | u8 lun_mc; /* |
| 730 | * flag to indicate whether to answer | |
| 731 | * MediaChange | |
| 732 | */ | |
| fa590c22 MC |
733 | |
| 734 | #ifndef LED_AUTO_BLINK | |
| 735 | int led_toggle_counter; | |
| 736 | #endif | |
| 737 | ||
| 738 | int sd_reset_counter; | |
| 739 | int xd_reset_counter; | |
| 740 | int ms_reset_counter; | |
| 741 | ||
| 742 | /* card bus width */ | |
| 743 | u8 card_bus_width[MAX_ALLOWED_LUN_CNT]; | |
| 744 | /* card capacity */ | |
| 745 | u32 capacity[MAX_ALLOWED_LUN_CNT]; | |
| 746 | /* read/write card function pointer */ | |
| 747 | card_rw_func rw_card[MAX_ALLOWED_LUN_CNT]; | |
| 748 | /* read/write capacity, used for GPIO Toggle */ | |
| 749 | u32 rw_cap[MAX_ALLOWED_LUN_CNT]; | |
| 750 | /* card to lun mapping table */ | |
| 751 | u8 card2lun[32]; | |
| 752 | /* lun to card mapping table */ | |
| 753 | u8 lun2card[MAX_ALLOWED_LUN_CNT]; | |
| 754 | ||
| 755 | int rw_fail_cnt[MAX_ALLOWED_LUN_CNT]; | |
| 756 | ||
| 757 | int sd_show_cnt; | |
| 758 | int xd_show_cnt; | |
| 759 | int ms_show_cnt; | |
| 760 | ||
| 761 | /* card information */ | |
| 762 | struct sd_info sd_card; | |
| 763 | struct xd_info xd_card; | |
| 764 | struct ms_info ms_card; | |
| 765 | ||
| 766 | struct spi_info spi; | |
| 767 | ||
| 768 | #ifdef _MSG_TRACE | |
| 769 | struct trace_msg_t trace_msg[TRACE_ITEM_CNT]; | |
| 770 | int msg_idx; | |
| 771 | #endif | |
| 772 | ||
| 773 | int auto_delink_cnt; | |
| 774 | int auto_delink_allowed; | |
| 775 | ||
| 776 | int aspm_enabled; | |
| 777 | ||
| 778 | int sdio_aspm; | |
| 779 | int sdio_idle; | |
| 780 | int sdio_counter; | |
| 781 | u8 sdio_raw_data[12]; | |
| 782 | ||
| 783 | u8 sd_io; | |
| 784 | u8 sd_int; | |
| 785 | ||
| 786 | u8 rtsx_flag; | |
| 787 | ||
| 788 | int ss_counter; | |
| 789 | int idle_counter; | |
| 790 | enum RTSX_STAT rtsx_stat; | |
| 791 | ||
| 792 | u16 vendor_id; | |
| 793 | u16 product_id; | |
| 794 | u8 ic_version; | |
| 795 | ||
| 796 | int driver_first_load; | |
| 797 | ||
| 798 | #ifdef HW_AUTO_SWITCH_SD_BUS | |
| 799 | int sdio_in_charge; | |
| 800 | #endif | |
| 801 | ||
| 802 | u8 aspm_level[2]; | |
| 803 | ||
| 804 | int chip_insert_with_sdio; | |
| 805 | ||
| 806 | /* Options */ | |
| 807 | ||
| 808 | int adma_mode; | |
| 809 | ||
| 810 | int auto_delink_en; | |
| 811 | int ss_en; | |
| 812 | u8 lun_mode; | |
| 813 | u8 aspm_l0s_l1_en; | |
| 814 | ||
| 815 | int power_down_in_ss; | |
| 816 | ||
| 817 | int sdr104_en; | |
| 818 | int ddr50_en; | |
| 819 | int sdr50_en; | |
| 820 | ||
| 821 | int baro_pkg; | |
| 822 | ||
| 823 | int asic_code; | |
| 824 | int phy_debug_mode; | |
| 825 | int hw_bypass_sd; | |
| 826 | int sdio_func_exist; | |
| 827 | int aux_pwr_exist; | |
| 828 | u8 ms_power_class_en; | |
| 829 | ||
| 830 | int mspro_formatter_enable; | |
| 831 | ||
| 832 | int remote_wakeup_en; | |
| 833 | ||
| 834 | int ignore_sd; | |
| 835 | int use_hw_setting; | |
| 836 | ||
| 837 | int ss_idle_period; | |
| 838 | ||
| 839 | int dynamic_aspm; | |
| 840 | ||
| 841 | int fpga_sd_sdr104_clk; | |
| 842 | int fpga_sd_ddr50_clk; | |
| 843 | int fpga_sd_sdr50_clk; | |
| 844 | int fpga_sd_hs_clk; | |
| 845 | int fpga_mmc_52m_clk; | |
| 846 | int fpga_ms_hg_clk; | |
| 847 | int fpga_ms_4bit_clk; | |
| 848 | int fpga_ms_1bit_clk; | |
| 849 | ||
| 850 | int asic_sd_sdr104_clk; | |
| 851 | int asic_sd_ddr50_clk; | |
| 852 | int asic_sd_sdr50_clk; | |
| 853 | int asic_sd_hs_clk; | |
| 854 | int asic_mmc_52m_clk; | |
| 855 | int asic_ms_hg_clk; | |
| 856 | int asic_ms_4bit_clk; | |
| 857 | int asic_ms_1bit_clk; | |
| 858 | ||
| 859 | u8 ssc_depth_sd_sdr104; | |
| 860 | u8 ssc_depth_sd_ddr50; | |
| 861 | u8 ssc_depth_sd_sdr50; | |
| 862 | u8 ssc_depth_sd_hs; | |
| 863 | u8 ssc_depth_mmc_52m; | |
| 864 | u8 ssc_depth_ms_hg; | |
| 865 | u8 ssc_depth_ms_4bit; | |
| 866 | u8 ssc_depth_low_speed; | |
| 867 | ||
| 868 | u8 card_drive_sel; | |
| 869 | u8 sd30_drive_sel_1v8; | |
| 870 | u8 sd30_drive_sel_3v3; | |
| 871 | ||
| 872 | u8 sd_400mA_ocp_thd; | |
| 873 | u8 sd_800mA_ocp_thd; | |
| 874 | u8 ms_ocp_thd; | |
| 875 | ||
| 876 | int ssc_en; | |
| 877 | int msi_en; | |
| 878 | ||
| 879 | int xd_timeout; | |
| 880 | int sd_timeout; | |
| 881 | int ms_timeout; | |
| 882 | int mspro_timeout; | |
| 883 | ||
| 884 | int auto_power_down; | |
| 885 | ||
| 886 | int sd_ddr_tx_phase; | |
| 887 | int mmc_ddr_tx_phase; | |
| 888 | int sd_default_tx_phase; | |
| 889 | int sd_default_rx_phase; | |
| 890 | ||
| 891 | int pmos_pwr_on_interval; | |
| 892 | int sd_voltage_switch_delay; | |
| 893 | int s3_pwr_off_delay; | |
| 894 | ||
| 895 | int force_clkreq_0; | |
| 896 | int ft2_fast_mode; | |
| 897 | ||
| 898 | int do_delink_before_power_down; | |
| 899 | int polling_config; | |
| 900 | int sdio_retry_cnt; | |
| 901 | ||
| 902 | int delink_stage1_step; | |
| 903 | int delink_stage2_step; | |
| 904 | int delink_stage3_step; | |
| 905 | ||
| 906 | int auto_delink_in_L1; | |
| 907 | int hp_watch_bios_hotplug; | |
| 908 | int support_ms_8bit; | |
| 909 | ||
| 910 | u8 blink_led; | |
| 911 | u8 phy_voltage; | |
| 912 | u8 max_payload; | |
| 913 | ||
| 914 | u32 sd_speed_prior; | |
| 915 | u32 sd_current_prior; | |
| 916 | u32 sd_ctl; | |
| 917 | }; | |
| 918 | ||
| bf6c0d11 FF |
919 | static inline struct device *rtsx_dev(const struct rtsx_chip *chip) |
| 920 | { | |
| 921 | return &chip->rtsx->pci->dev; | |
| 922 | } | |
| 923 | ||
| fa590c22 MC |
924 | #define rtsx_set_stat(chip, stat) \ |
| 925 | do { \ | |
| 926 | if ((stat) != RTSX_STAT_IDLE) { \ | |
| 927 | (chip)->idle_counter = 0; \ | |
| 928 | } \ | |
| 929 | (chip)->rtsx_stat = (enum RTSX_STAT)(stat); \ | |
| 930 | } while (0) | |
| 931 | #define rtsx_get_stat(chip) ((chip)->rtsx_stat) | |
| 932 | #define rtsx_chk_stat(chip, stat) ((chip)->rtsx_stat == (stat)) | |
| 933 | ||
| 934 | #define RTSX_SET_DELINK(chip) ((chip)->rtsx_flag |= 0x01) | |
| 935 | #define RTSX_CLR_DELINK(chip) ((chip)->rtsx_flag &= 0xFE) | |
| 936 | #define RTSX_TST_DELINK(chip) ((chip)->rtsx_flag & 0x01) | |
| 937 | ||
| 938 | #define CHECK_PID(chip, pid) ((chip)->product_id == (pid)) | |
| 939 | #define CHECK_BARO_PKG(chip, pkg) ((chip)->baro_pkg == (pkg)) | |
| 940 | #define CHECK_LUN_MODE(chip, mode) ((chip)->lun_mode == (mode)) | |
| 941 | ||
| 942 | /* Power down control */ | |
| 943 | #define SSC_PDCTL 0x01 | |
| 944 | #define OC_PDCTL 0x02 | |
| 945 | ||
| 946 | int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl); | |
| 947 | int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl); | |
| 948 | ||
| fa590c22 MC |
949 | void rtsx_enable_card_int(struct rtsx_chip *chip); |
| 950 | void rtsx_enable_bus_int(struct rtsx_chip *chip); | |
| 951 | void rtsx_disable_bus_int(struct rtsx_chip *chip); | |
| 952 | int rtsx_reset_chip(struct rtsx_chip *chip); | |
| 953 | int rtsx_init_chip(struct rtsx_chip *chip); | |
| 954 | void rtsx_release_chip(struct rtsx_chip *chip); | |
| 955 | void rtsx_polling_func(struct rtsx_chip *chip); | |
| fa590c22 MC |
956 | void rtsx_stop_cmd(struct rtsx_chip *chip, int card); |
| 957 | int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data); | |
| 958 | int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data); | |
| 959 | int rtsx_write_cfg_dw(struct rtsx_chip *chip, | |
| 960 | u8 func_no, u16 addr, u32 mask, u32 val); | |
| 961 | int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val); | |
| 962 | int rtsx_write_cfg_seq(struct rtsx_chip *chip, | |
| 963 | u8 func, u16 addr, u8 *buf, int len); | |
| 964 | int rtsx_read_cfg_seq(struct rtsx_chip *chip, | |
| 965 | u8 func, u16 addr, u8 *buf, int len); | |
| 966 | int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val); | |
| 967 | int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val); | |
| 968 | int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val); | |
| 969 | int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val); | |
| 970 | int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); | |
| 971 | int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); | |
| fa590c22 MC |
972 | void rtsx_enter_ss(struct rtsx_chip *chip); |
| 973 | void rtsx_exit_ss(struct rtsx_chip *chip); | |
| 974 | int rtsx_pre_handle_interrupt(struct rtsx_chip *chip); | |
| 975 | void rtsx_enter_L1(struct rtsx_chip *chip); | |
| 976 | void rtsx_exit_L1(struct rtsx_chip *chip); | |
| 977 | void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat); | |
| 978 | void rtsx_enable_aspm(struct rtsx_chip *chip); | |
| 979 | void rtsx_disable_aspm(struct rtsx_chip *chip); | |
| 980 | int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); | |
| 981 | int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); | |
| 982 | int rtsx_check_chip_exist(struct rtsx_chip *chip); | |
| 983 | ||
| fa590c22 | 984 | #endif /* __REALTEK_RTSX_CHIP_H */ |