]>
Commit | Line | Data |
---|---|---|
fa590c22 MC |
1 | /* Driver for Realtek PCI-Express card reader |
2 | * | |
3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2, or (at your option) any | |
8 | * later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: | |
19 | * Wei WANG (wei_wang@realsil.com.cn) | |
20 | * Micky Ching (micky_ching@realsil.com.cn) | |
21 | */ | |
22 | ||
23 | #include <linux/blkdev.h> | |
24 | #include <linux/kthread.h> | |
25 | #include <linux/sched.h> | |
26 | ||
27 | #include "rtsx.h" | |
fa590c22 MC |
28 | #include "spi.h" |
29 | ||
30 | static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code) | |
31 | { | |
32 | struct spi_info *spi = &(chip->spi); | |
33 | ||
34 | spi->err_code = err_code; | |
35 | } | |
36 | ||
37 | static int spi_init(struct rtsx_chip *chip) | |
38 | { | |
8ee775f9 JP |
39 | int retval; |
40 | ||
41 | retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, | |
9afccdfe SP |
42 | CS_POLARITY_LOW | DTO_MSB_FIRST |
43 | | SPI_MASTER | SPI_MODE0 | SPI_AUTO); | |
8ee775f9 JP |
44 | if (retval) { |
45 | rtsx_trace(chip); | |
46 | return retval; | |
47 | } | |
48 | retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, | |
49 | SAMPLE_DELAY_HALF); | |
50 | if (retval) { | |
51 | rtsx_trace(chip); | |
52 | return retval; | |
53 | } | |
fa590c22 MC |
54 | |
55 | return STATUS_SUCCESS; | |
56 | } | |
57 | ||
58 | static int spi_set_init_para(struct rtsx_chip *chip) | |
59 | { | |
60 | struct spi_info *spi = &(chip->spi); | |
61 | int retval; | |
62 | ||
8ee775f9 JP |
63 | retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, |
64 | (u8)(spi->clk_div >> 8)); | |
65 | if (retval) { | |
66 | rtsx_trace(chip); | |
67 | return retval; | |
68 | } | |
69 | retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, | |
70 | (u8)(spi->clk_div)); | |
71 | if (retval) { | |
72 | rtsx_trace(chip); | |
73 | return retval; | |
74 | } | |
fa590c22 MC |
75 | |
76 | retval = switch_clock(chip, spi->spi_clock); | |
031366ea JP |
77 | if (retval != STATUS_SUCCESS) { |
78 | rtsx_trace(chip); | |
79 | return STATUS_FAIL; | |
80 | } | |
fa590c22 MC |
81 | |
82 | retval = select_card(chip, SPI_CARD); | |
031366ea JP |
83 | if (retval != STATUS_SUCCESS) { |
84 | rtsx_trace(chip); | |
85 | return STATUS_FAIL; | |
86 | } | |
fa590c22 | 87 | |
8ee775f9 JP |
88 | retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, |
89 | SPI_CLK_EN); | |
90 | if (retval) { | |
91 | rtsx_trace(chip); | |
92 | return retval; | |
93 | } | |
94 | retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, | |
95 | SPI_OUTPUT_EN); | |
96 | if (retval) { | |
97 | rtsx_trace(chip); | |
98 | return retval; | |
99 | } | |
fa590c22 MC |
100 | |
101 | wait_timeout(10); | |
102 | ||
103 | retval = spi_init(chip); | |
031366ea JP |
104 | if (retval != STATUS_SUCCESS) { |
105 | rtsx_trace(chip); | |
106 | return STATUS_FAIL; | |
107 | } | |
fa590c22 MC |
108 | |
109 | return STATUS_SUCCESS; | |
110 | } | |
111 | ||
112 | static int sf_polling_status(struct rtsx_chip *chip, int msec) | |
113 | { | |
114 | int retval; | |
115 | ||
116 | rtsx_init_cmd(chip); | |
117 | ||
118 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR); | |
119 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
120 | SPI_TRANSFER0_START | SPI_POLLING_MODE0); | |
121 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
122 | SPI_TRANSFER0_END); | |
123 | ||
124 | retval = rtsx_send_cmd(chip, 0, msec); | |
125 | if (retval < 0) { | |
126 | rtsx_clear_spi_error(chip); | |
127 | spi_set_err_code(chip, SPI_BUSY_ERR); | |
031366ea JP |
128 | rtsx_trace(chip); |
129 | return STATUS_FAIL; | |
fa590c22 MC |
130 | } |
131 | ||
132 | return STATUS_SUCCESS; | |
133 | } | |
134 | ||
135 | static int sf_enable_write(struct rtsx_chip *chip, u8 ins) | |
136 | { | |
137 | struct spi_info *spi = &(chip->spi); | |
138 | int retval; | |
139 | ||
140 | if (!spi->write_en) | |
141 | return STATUS_SUCCESS; | |
142 | ||
143 | rtsx_init_cmd(chip); | |
144 | ||
145 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); | |
146 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, | |
147 | SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); | |
148 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
149 | SPI_TRANSFER0_START | SPI_C_MODE0); | |
150 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
151 | SPI_TRANSFER0_END); | |
152 | ||
153 | retval = rtsx_send_cmd(chip, 0, 100); | |
154 | if (retval < 0) { | |
155 | rtsx_clear_spi_error(chip); | |
156 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
157 | rtsx_trace(chip); |
158 | return STATUS_FAIL; | |
fa590c22 MC |
159 | } |
160 | ||
161 | return STATUS_SUCCESS; | |
162 | } | |
163 | ||
164 | static int sf_disable_write(struct rtsx_chip *chip, u8 ins) | |
165 | { | |
166 | struct spi_info *spi = &(chip->spi); | |
167 | int retval; | |
168 | ||
169 | if (!spi->write_en) | |
170 | return STATUS_SUCCESS; | |
171 | ||
172 | rtsx_init_cmd(chip); | |
173 | ||
174 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); | |
175 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, | |
176 | SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); | |
177 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
178 | SPI_TRANSFER0_START | SPI_C_MODE0); | |
179 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
180 | SPI_TRANSFER0_END); | |
181 | ||
182 | retval = rtsx_send_cmd(chip, 0, 100); | |
183 | if (retval < 0) { | |
184 | rtsx_clear_spi_error(chip); | |
185 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
186 | rtsx_trace(chip); |
187 | return STATUS_FAIL; | |
fa590c22 MC |
188 | } |
189 | ||
190 | return STATUS_SUCCESS; | |
191 | } | |
192 | ||
193 | static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr, | |
194 | u16 len) | |
195 | { | |
196 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); | |
197 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, | |
198 | SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); | |
199 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len); | |
200 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8)); | |
201 | if (addr_mode) { | |
202 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); | |
203 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, | |
204 | (u8)(addr >> 8)); | |
205 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, | |
206 | (u8)(addr >> 16)); | |
207 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
208 | SPI_TRANSFER0_START | SPI_CADO_MODE0); | |
209 | } else { | |
210 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
211 | SPI_TRANSFER0_START | SPI_CDO_MODE0); | |
212 | } | |
213 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
214 | SPI_TRANSFER0_END); | |
215 | } | |
216 | ||
217 | static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr) | |
218 | { | |
219 | int retval; | |
220 | ||
221 | rtsx_init_cmd(chip); | |
222 | ||
223 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); | |
224 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, | |
225 | SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); | |
226 | if (addr_mode) { | |
227 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); | |
228 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, | |
229 | (u8)(addr >> 8)); | |
230 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, | |
231 | (u8)(addr >> 16)); | |
232 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
233 | SPI_TRANSFER0_START | SPI_CA_MODE0); | |
234 | } else { | |
235 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
236 | SPI_TRANSFER0_START | SPI_C_MODE0); | |
237 | } | |
238 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
239 | SPI_TRANSFER0_END); | |
240 | ||
241 | retval = rtsx_send_cmd(chip, 0, 100); | |
242 | if (retval < 0) { | |
243 | rtsx_clear_spi_error(chip); | |
244 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
245 | rtsx_trace(chip); |
246 | return STATUS_FAIL; | |
fa590c22 MC |
247 | } |
248 | ||
249 | return STATUS_SUCCESS; | |
250 | } | |
251 | ||
252 | static int spi_init_eeprom(struct rtsx_chip *chip) | |
253 | { | |
254 | int retval; | |
255 | int clk; | |
256 | ||
257 | if (chip->asic_code) | |
258 | clk = 30; | |
259 | else | |
260 | clk = CLK_30; | |
261 | ||
8ee775f9 JP |
262 | retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00); |
263 | if (retval) { | |
264 | rtsx_trace(chip); | |
265 | return retval; | |
266 | } | |
267 | retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27); | |
268 | if (retval) { | |
269 | rtsx_trace(chip); | |
270 | return retval; | |
271 | } | |
fa590c22 MC |
272 | |
273 | retval = switch_clock(chip, clk); | |
031366ea JP |
274 | if (retval != STATUS_SUCCESS) { |
275 | rtsx_trace(chip); | |
276 | return STATUS_FAIL; | |
277 | } | |
fa590c22 MC |
278 | |
279 | retval = select_card(chip, SPI_CARD); | |
031366ea JP |
280 | if (retval != STATUS_SUCCESS) { |
281 | rtsx_trace(chip); | |
282 | return STATUS_FAIL; | |
283 | } | |
fa590c22 | 284 | |
8ee775f9 JP |
285 | retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, |
286 | SPI_CLK_EN); | |
287 | if (retval) { | |
288 | rtsx_trace(chip); | |
289 | return retval; | |
290 | } | |
291 | retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, | |
292 | SPI_OUTPUT_EN); | |
293 | if (retval) { | |
294 | rtsx_trace(chip); | |
295 | return retval; | |
296 | } | |
fa590c22 MC |
297 | |
298 | wait_timeout(10); | |
299 | ||
8ee775f9 JP |
300 | retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, |
301 | CS_POLARITY_HIGH | SPI_EEPROM_AUTO); | |
302 | if (retval) { | |
303 | rtsx_trace(chip); | |
304 | return retval; | |
305 | } | |
306 | retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, | |
307 | SAMPLE_DELAY_HALF); | |
308 | if (retval) { | |
309 | rtsx_trace(chip); | |
310 | return retval; | |
311 | } | |
fa590c22 MC |
312 | |
313 | return STATUS_SUCCESS; | |
314 | } | |
315 | ||
316 | static int spi_eeprom_program_enable(struct rtsx_chip *chip) | |
317 | { | |
318 | int retval; | |
319 | ||
320 | rtsx_init_cmd(chip); | |
321 | ||
322 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86); | |
323 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13); | |
324 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
325 | SPI_TRANSFER0_START | SPI_CA_MODE0); | |
326 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
327 | SPI_TRANSFER0_END); | |
328 | ||
329 | retval = rtsx_send_cmd(chip, 0, 100); | |
031366ea JP |
330 | if (retval < 0) { |
331 | rtsx_trace(chip); | |
332 | return STATUS_FAIL; | |
333 | } | |
fa590c22 MC |
334 | |
335 | return STATUS_SUCCESS; | |
336 | } | |
337 | ||
338 | int spi_erase_eeprom_chip(struct rtsx_chip *chip) | |
339 | { | |
340 | int retval; | |
341 | ||
342 | retval = spi_init_eeprom(chip); | |
031366ea JP |
343 | if (retval != STATUS_SUCCESS) { |
344 | rtsx_trace(chip); | |
345 | return STATUS_FAIL; | |
346 | } | |
fa590c22 MC |
347 | |
348 | retval = spi_eeprom_program_enable(chip); | |
031366ea JP |
349 | if (retval != STATUS_SUCCESS) { |
350 | rtsx_trace(chip); | |
351 | return STATUS_FAIL; | |
352 | } | |
fa590c22 MC |
353 | |
354 | rtsx_init_cmd(chip); | |
355 | ||
356 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); | |
357 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); | |
358 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12); | |
359 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84); | |
360 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
361 | SPI_TRANSFER0_START | SPI_CA_MODE0); | |
362 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
363 | SPI_TRANSFER0_END); | |
364 | ||
365 | retval = rtsx_send_cmd(chip, 0, 100); | |
031366ea JP |
366 | if (retval < 0) { |
367 | rtsx_trace(chip); | |
368 | return STATUS_FAIL; | |
369 | } | |
fa590c22 | 370 | |
8ee775f9 JP |
371 | retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); |
372 | if (retval) { | |
373 | rtsx_trace(chip); | |
374 | return retval; | |
375 | } | |
fa590c22 MC |
376 | |
377 | return STATUS_SUCCESS; | |
378 | } | |
379 | ||
380 | int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr) | |
381 | { | |
382 | int retval; | |
383 | ||
384 | retval = spi_init_eeprom(chip); | |
031366ea JP |
385 | if (retval != STATUS_SUCCESS) { |
386 | rtsx_trace(chip); | |
387 | return STATUS_FAIL; | |
388 | } | |
fa590c22 MC |
389 | |
390 | retval = spi_eeprom_program_enable(chip); | |
031366ea JP |
391 | if (retval != STATUS_SUCCESS) { |
392 | rtsx_trace(chip); | |
393 | return STATUS_FAIL; | |
394 | } | |
fa590c22 MC |
395 | |
396 | rtsx_init_cmd(chip); | |
397 | ||
398 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); | |
399 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); | |
400 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07); | |
401 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); | |
402 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8)); | |
403 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46); | |
404 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
405 | SPI_TRANSFER0_START | SPI_CA_MODE0); | |
406 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
407 | SPI_TRANSFER0_END); | |
408 | ||
409 | retval = rtsx_send_cmd(chip, 0, 100); | |
031366ea JP |
410 | if (retval < 0) { |
411 | rtsx_trace(chip); | |
412 | return STATUS_FAIL; | |
413 | } | |
fa590c22 | 414 | |
8ee775f9 JP |
415 | retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); |
416 | if (retval) { | |
417 | rtsx_trace(chip); | |
418 | return retval; | |
419 | } | |
fa590c22 MC |
420 | |
421 | return STATUS_SUCCESS; | |
422 | } | |
423 | ||
fa590c22 MC |
424 | int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val) |
425 | { | |
426 | int retval; | |
427 | u8 data; | |
428 | ||
429 | retval = spi_init_eeprom(chip); | |
031366ea JP |
430 | if (retval != STATUS_SUCCESS) { |
431 | rtsx_trace(chip); | |
432 | return STATUS_FAIL; | |
433 | } | |
fa590c22 MC |
434 | |
435 | rtsx_init_cmd(chip); | |
436 | ||
437 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); | |
438 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); | |
439 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06); | |
440 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); | |
441 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8)); | |
442 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46); | |
443 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1); | |
444 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
445 | SPI_TRANSFER0_START | SPI_CADI_MODE0); | |
446 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
447 | SPI_TRANSFER0_END); | |
448 | ||
449 | retval = rtsx_send_cmd(chip, 0, 100); | |
031366ea JP |
450 | if (retval < 0) { |
451 | rtsx_trace(chip); | |
452 | return STATUS_FAIL; | |
453 | } | |
fa590c22 MC |
454 | |
455 | wait_timeout(5); | |
8ee775f9 JP |
456 | retval = rtsx_read_register(chip, SPI_DATA, &data); |
457 | if (retval) { | |
458 | rtsx_trace(chip); | |
459 | return retval; | |
460 | } | |
fa590c22 MC |
461 | |
462 | if (val) | |
463 | *val = data; | |
464 | ||
8ee775f9 JP |
465 | retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); |
466 | if (retval) { | |
467 | rtsx_trace(chip); | |
468 | return retval; | |
469 | } | |
fa590c22 MC |
470 | |
471 | return STATUS_SUCCESS; | |
472 | } | |
473 | ||
474 | int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val) | |
475 | { | |
476 | int retval; | |
477 | ||
478 | retval = spi_init_eeprom(chip); | |
031366ea JP |
479 | if (retval != STATUS_SUCCESS) { |
480 | rtsx_trace(chip); | |
481 | return STATUS_FAIL; | |
482 | } | |
fa590c22 MC |
483 | |
484 | retval = spi_eeprom_program_enable(chip); | |
031366ea JP |
485 | if (retval != STATUS_SUCCESS) { |
486 | rtsx_trace(chip); | |
487 | return STATUS_FAIL; | |
488 | } | |
fa590c22 MC |
489 | |
490 | rtsx_init_cmd(chip); | |
491 | ||
492 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); | |
493 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); | |
494 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05); | |
495 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val); | |
496 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr); | |
497 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8)); | |
498 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E); | |
499 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
500 | SPI_TRANSFER0_START | SPI_CA_MODE0); | |
501 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
502 | SPI_TRANSFER0_END); | |
503 | ||
504 | retval = rtsx_send_cmd(chip, 0, 100); | |
031366ea JP |
505 | if (retval < 0) { |
506 | rtsx_trace(chip); | |
507 | return STATUS_FAIL; | |
508 | } | |
fa590c22 | 509 | |
8ee775f9 JP |
510 | retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); |
511 | if (retval) { | |
512 | rtsx_trace(chip); | |
513 | return retval; | |
514 | } | |
fa590c22 MC |
515 | |
516 | return STATUS_SUCCESS; | |
517 | } | |
518 | ||
fa590c22 MC |
519 | int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) |
520 | { | |
521 | struct spi_info *spi = &(chip->spi); | |
522 | ||
bf6c0d11 FF |
523 | dev_dbg(rtsx_dev(chip), "spi_get_status: err_code = 0x%x\n", |
524 | spi->err_code); | |
fa590c22 MC |
525 | rtsx_stor_set_xfer_buf(&(spi->err_code), |
526 | min_t(int, scsi_bufflen(srb), 1), srb); | |
527 | scsi_set_resid(srb, scsi_bufflen(srb) - 1); | |
528 | ||
529 | return STATUS_SUCCESS; | |
530 | } | |
531 | ||
532 | int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
533 | { | |
534 | struct spi_info *spi = &(chip->spi); | |
535 | ||
536 | spi_set_err_code(chip, SPI_NO_ERR); | |
537 | ||
538 | if (chip->asic_code) | |
539 | spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9]; | |
540 | else | |
541 | spi->spi_clock = srb->cmnd[3]; | |
542 | ||
543 | spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5]; | |
544 | spi->write_en = srb->cmnd[6]; | |
545 | ||
bf6c0d11 FF |
546 | dev_dbg(rtsx_dev(chip), "spi_set_parameter: spi_clock = %d, clk_div = %d, write_en = %d\n", |
547 | spi->spi_clock, spi->clk_div, spi->write_en); | |
fa590c22 MC |
548 | |
549 | return STATUS_SUCCESS; | |
550 | } | |
551 | ||
552 | int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
553 | { | |
554 | int retval; | |
555 | u16 len; | |
556 | u8 *buf; | |
557 | ||
558 | spi_set_err_code(chip, SPI_NO_ERR); | |
559 | ||
560 | len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; | |
561 | if (len > 512) { | |
562 | spi_set_err_code(chip, SPI_INVALID_COMMAND); | |
031366ea JP |
563 | rtsx_trace(chip); |
564 | return STATUS_FAIL; | |
fa590c22 MC |
565 | } |
566 | ||
567 | retval = spi_set_init_para(chip); | |
568 | if (retval != STATUS_SUCCESS) { | |
569 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
570 | rtsx_trace(chip); |
571 | return STATUS_FAIL; | |
fa590c22 MC |
572 | } |
573 | ||
574 | rtsx_init_cmd(chip); | |
575 | ||
576 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, | |
577 | PINGPONG_BUFFER); | |
578 | ||
579 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]); | |
580 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]); | |
581 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]); | |
582 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]); | |
583 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, | |
584 | SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); | |
585 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]); | |
586 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]); | |
587 | ||
588 | if (len == 0) { | |
589 | if (srb->cmnd[9]) { | |
590 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, | |
591 | 0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0); | |
592 | } else { | |
593 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, | |
594 | 0xFF, SPI_TRANSFER0_START | SPI_C_MODE0); | |
595 | } | |
596 | } else { | |
597 | if (srb->cmnd[9]) { | |
598 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
599 | SPI_TRANSFER0_START | SPI_CADI_MODE0); | |
600 | } else { | |
601 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
602 | SPI_TRANSFER0_START | SPI_CDI_MODE0); | |
603 | } | |
604 | } | |
605 | ||
606 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
607 | SPI_TRANSFER0_END); | |
608 | ||
609 | retval = rtsx_send_cmd(chip, 0, 100); | |
610 | if (retval < 0) { | |
611 | rtsx_clear_spi_error(chip); | |
612 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
613 | rtsx_trace(chip); |
614 | return STATUS_FAIL; | |
fa590c22 MC |
615 | } |
616 | ||
617 | if (len) { | |
618 | buf = kmalloc(len, GFP_KERNEL); | |
031366ea JP |
619 | if (!buf) { |
620 | rtsx_trace(chip); | |
621 | return STATUS_ERROR; | |
622 | } | |
fa590c22 MC |
623 | |
624 | retval = rtsx_read_ppbuf(chip, buf, len); | |
625 | if (retval != STATUS_SUCCESS) { | |
626 | spi_set_err_code(chip, SPI_READ_ERR); | |
627 | kfree(buf); | |
031366ea JP |
628 | rtsx_trace(chip); |
629 | return STATUS_FAIL; | |
fa590c22 MC |
630 | } |
631 | ||
632 | rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb); | |
633 | scsi_set_resid(srb, 0); | |
634 | ||
635 | kfree(buf); | |
636 | } | |
637 | ||
638 | return STATUS_SUCCESS; | |
639 | } | |
640 | ||
641 | int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
642 | { | |
643 | int retval; | |
644 | unsigned int index = 0, offset = 0; | |
645 | u8 ins, slow_read; | |
646 | u32 addr; | |
647 | u16 len; | |
648 | u8 *buf; | |
649 | ||
650 | spi_set_err_code(chip, SPI_NO_ERR); | |
651 | ||
652 | ins = srb->cmnd[3]; | |
653 | addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) | |
654 | << 8) | srb->cmnd[6]; | |
655 | len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; | |
656 | slow_read = srb->cmnd[9]; | |
657 | ||
658 | retval = spi_set_init_para(chip); | |
659 | if (retval != STATUS_SUCCESS) { | |
660 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
661 | rtsx_trace(chip); |
662 | return STATUS_FAIL; | |
fa590c22 MC |
663 | } |
664 | ||
665 | buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL); | |
7586170c | 666 | if (!buf) { |
031366ea JP |
667 | rtsx_trace(chip); |
668 | return STATUS_ERROR; | |
669 | } | |
fa590c22 MC |
670 | |
671 | while (len) { | |
672 | u16 pagelen = SF_PAGE_LEN - (u8)addr; | |
673 | ||
674 | if (pagelen > len) | |
675 | pagelen = len; | |
676 | ||
677 | rtsx_init_cmd(chip); | |
678 | ||
679 | trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256); | |
680 | ||
681 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); | |
682 | ||
683 | if (slow_read) { | |
684 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, | |
685 | (u8)addr); | |
686 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, | |
687 | (u8)(addr >> 8)); | |
688 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, | |
689 | (u8)(addr >> 16)); | |
690 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, | |
691 | SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); | |
692 | } else { | |
693 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, | |
694 | (u8)addr); | |
695 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, | |
696 | (u8)(addr >> 8)); | |
697 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF, | |
698 | (u8)(addr >> 16)); | |
699 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, | |
700 | SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32); | |
701 | } | |
702 | ||
703 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, | |
704 | (u8)(pagelen >> 8)); | |
705 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, | |
706 | (u8)pagelen); | |
707 | ||
708 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
709 | SPI_TRANSFER0_START | SPI_CADI_MODE0); | |
710 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, | |
711 | SPI_TRANSFER0_END, SPI_TRANSFER0_END); | |
712 | ||
713 | rtsx_send_cmd_no_wait(chip); | |
714 | ||
715 | retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, | |
716 | DMA_FROM_DEVICE, 10000); | |
717 | if (retval < 0) { | |
718 | kfree(buf); | |
719 | rtsx_clear_spi_error(chip); | |
720 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
721 | rtsx_trace(chip); |
722 | return STATUS_FAIL; | |
fa590c22 MC |
723 | } |
724 | ||
725 | rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset, | |
726 | TO_XFER_BUF); | |
727 | ||
728 | addr += pagelen; | |
729 | len -= pagelen; | |
730 | } | |
731 | ||
732 | scsi_set_resid(srb, 0); | |
733 | kfree(buf); | |
734 | ||
735 | return STATUS_SUCCESS; | |
736 | } | |
737 | ||
738 | int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
739 | { | |
740 | int retval; | |
741 | u8 ins, program_mode; | |
742 | u32 addr; | |
743 | u16 len; | |
744 | u8 *buf; | |
745 | unsigned int index = 0, offset = 0; | |
746 | ||
747 | spi_set_err_code(chip, SPI_NO_ERR); | |
748 | ||
749 | ins = srb->cmnd[3]; | |
750 | addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) | |
751 | << 8) | srb->cmnd[6]; | |
752 | len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; | |
753 | program_mode = srb->cmnd[9]; | |
754 | ||
755 | retval = spi_set_init_para(chip); | |
756 | if (retval != STATUS_SUCCESS) { | |
757 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
758 | rtsx_trace(chip); |
759 | return STATUS_FAIL; | |
fa590c22 MC |
760 | } |
761 | ||
762 | if (program_mode == BYTE_PROGRAM) { | |
763 | buf = kmalloc(4, GFP_KERNEL); | |
031366ea JP |
764 | if (!buf) { |
765 | rtsx_trace(chip); | |
766 | return STATUS_ERROR; | |
767 | } | |
fa590c22 MC |
768 | |
769 | while (len) { | |
770 | retval = sf_enable_write(chip, SPI_WREN); | |
771 | if (retval != STATUS_SUCCESS) { | |
772 | kfree(buf); | |
031366ea JP |
773 | rtsx_trace(chip); |
774 | return STATUS_FAIL; | |
fa590c22 MC |
775 | } |
776 | ||
777 | rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, | |
778 | FROM_XFER_BUF); | |
779 | ||
780 | rtsx_init_cmd(chip); | |
781 | ||
782 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, | |
783 | 0x01, PINGPONG_BUFFER); | |
784 | rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, | |
785 | buf[0]); | |
786 | sf_program(chip, ins, 1, addr, 1); | |
787 | ||
788 | retval = rtsx_send_cmd(chip, 0, 100); | |
789 | if (retval < 0) { | |
790 | kfree(buf); | |
791 | rtsx_clear_spi_error(chip); | |
792 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
793 | rtsx_trace(chip); |
794 | return STATUS_FAIL; | |
fa590c22 MC |
795 | } |
796 | ||
797 | retval = sf_polling_status(chip, 100); | |
798 | if (retval != STATUS_SUCCESS) { | |
799 | kfree(buf); | |
031366ea JP |
800 | rtsx_trace(chip); |
801 | return STATUS_FAIL; | |
fa590c22 MC |
802 | } |
803 | ||
804 | addr++; | |
805 | len--; | |
806 | } | |
807 | ||
808 | kfree(buf); | |
809 | ||
810 | } else if (program_mode == AAI_PROGRAM) { | |
811 | int first_byte = 1; | |
812 | ||
813 | retval = sf_enable_write(chip, SPI_WREN); | |
031366ea JP |
814 | if (retval != STATUS_SUCCESS) { |
815 | rtsx_trace(chip); | |
816 | return STATUS_FAIL; | |
817 | } | |
fa590c22 MC |
818 | |
819 | buf = kmalloc(4, GFP_KERNEL); | |
031366ea JP |
820 | if (!buf) { |
821 | rtsx_trace(chip); | |
822 | return STATUS_ERROR; | |
823 | } | |
fa590c22 MC |
824 | |
825 | while (len) { | |
826 | rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, | |
827 | FROM_XFER_BUF); | |
828 | ||
829 | rtsx_init_cmd(chip); | |
830 | ||
831 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, | |
832 | 0x01, PINGPONG_BUFFER); | |
833 | rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, | |
834 | buf[0]); | |
835 | if (first_byte) { | |
836 | sf_program(chip, ins, 1, addr, 1); | |
837 | first_byte = 0; | |
838 | } else { | |
839 | sf_program(chip, ins, 0, 0, 1); | |
840 | } | |
841 | ||
842 | retval = rtsx_send_cmd(chip, 0, 100); | |
843 | if (retval < 0) { | |
844 | kfree(buf); | |
845 | rtsx_clear_spi_error(chip); | |
846 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
847 | rtsx_trace(chip); |
848 | return STATUS_FAIL; | |
fa590c22 MC |
849 | } |
850 | ||
851 | retval = sf_polling_status(chip, 100); | |
852 | if (retval != STATUS_SUCCESS) { | |
853 | kfree(buf); | |
031366ea JP |
854 | rtsx_trace(chip); |
855 | return STATUS_FAIL; | |
fa590c22 MC |
856 | } |
857 | ||
858 | len--; | |
859 | } | |
860 | ||
861 | kfree(buf); | |
862 | ||
863 | retval = sf_disable_write(chip, SPI_WRDI); | |
031366ea JP |
864 | if (retval != STATUS_SUCCESS) { |
865 | rtsx_trace(chip); | |
866 | return STATUS_FAIL; | |
867 | } | |
fa590c22 MC |
868 | |
869 | retval = sf_polling_status(chip, 100); | |
031366ea JP |
870 | if (retval != STATUS_SUCCESS) { |
871 | rtsx_trace(chip); | |
872 | return STATUS_FAIL; | |
873 | } | |
fa590c22 MC |
874 | } else if (program_mode == PAGE_PROGRAM) { |
875 | buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL); | |
031366ea JP |
876 | if (!buf) { |
877 | rtsx_trace(chip); | |
878 | return STATUS_NOMEM; | |
879 | } | |
fa590c22 MC |
880 | |
881 | while (len) { | |
882 | u16 pagelen = SF_PAGE_LEN - (u8)addr; | |
883 | ||
884 | if (pagelen > len) | |
885 | pagelen = len; | |
886 | ||
887 | retval = sf_enable_write(chip, SPI_WREN); | |
888 | if (retval != STATUS_SUCCESS) { | |
889 | kfree(buf); | |
031366ea JP |
890 | rtsx_trace(chip); |
891 | return STATUS_FAIL; | |
fa590c22 MC |
892 | } |
893 | ||
894 | rtsx_init_cmd(chip); | |
895 | ||
896 | trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256); | |
897 | sf_program(chip, ins, 1, addr, pagelen); | |
898 | ||
899 | rtsx_send_cmd_no_wait(chip); | |
900 | ||
901 | rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, | |
902 | &offset, FROM_XFER_BUF); | |
903 | ||
904 | retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, | |
905 | DMA_TO_DEVICE, 100); | |
906 | if (retval < 0) { | |
907 | kfree(buf); | |
908 | rtsx_clear_spi_error(chip); | |
909 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
910 | rtsx_trace(chip); |
911 | return STATUS_FAIL; | |
fa590c22 MC |
912 | } |
913 | ||
914 | retval = sf_polling_status(chip, 100); | |
915 | if (retval != STATUS_SUCCESS) { | |
916 | kfree(buf); | |
031366ea JP |
917 | rtsx_trace(chip); |
918 | return STATUS_FAIL; | |
fa590c22 MC |
919 | } |
920 | ||
921 | addr += pagelen; | |
922 | len -= pagelen; | |
923 | } | |
924 | ||
925 | kfree(buf); | |
926 | } else { | |
927 | spi_set_err_code(chip, SPI_INVALID_COMMAND); | |
031366ea JP |
928 | rtsx_trace(chip); |
929 | return STATUS_FAIL; | |
fa590c22 MC |
930 | } |
931 | ||
932 | return STATUS_SUCCESS; | |
933 | } | |
934 | ||
935 | int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
936 | { | |
937 | int retval; | |
938 | u8 ins, erase_mode; | |
939 | u32 addr; | |
940 | ||
941 | spi_set_err_code(chip, SPI_NO_ERR); | |
942 | ||
943 | ins = srb->cmnd[3]; | |
944 | addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) | |
945 | << 8) | srb->cmnd[6]; | |
946 | erase_mode = srb->cmnd[9]; | |
947 | ||
948 | retval = spi_set_init_para(chip); | |
949 | if (retval != STATUS_SUCCESS) { | |
950 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
951 | rtsx_trace(chip); |
952 | return STATUS_FAIL; | |
fa590c22 MC |
953 | } |
954 | ||
955 | if (erase_mode == PAGE_ERASE) { | |
956 | retval = sf_enable_write(chip, SPI_WREN); | |
031366ea JP |
957 | if (retval != STATUS_SUCCESS) { |
958 | rtsx_trace(chip); | |
959 | return STATUS_FAIL; | |
960 | } | |
fa590c22 MC |
961 | |
962 | retval = sf_erase(chip, ins, 1, addr); | |
031366ea JP |
963 | if (retval != STATUS_SUCCESS) { |
964 | rtsx_trace(chip); | |
965 | return STATUS_FAIL; | |
966 | } | |
fa590c22 MC |
967 | } else if (erase_mode == CHIP_ERASE) { |
968 | retval = sf_enable_write(chip, SPI_WREN); | |
031366ea JP |
969 | if (retval != STATUS_SUCCESS) { |
970 | rtsx_trace(chip); | |
971 | return STATUS_FAIL; | |
972 | } | |
fa590c22 MC |
973 | |
974 | retval = sf_erase(chip, ins, 0, 0); | |
031366ea JP |
975 | if (retval != STATUS_SUCCESS) { |
976 | rtsx_trace(chip); | |
977 | return STATUS_FAIL; | |
978 | } | |
fa590c22 MC |
979 | } else { |
980 | spi_set_err_code(chip, SPI_INVALID_COMMAND); | |
031366ea JP |
981 | rtsx_trace(chip); |
982 | return STATUS_FAIL; | |
fa590c22 MC |
983 | } |
984 | ||
985 | return STATUS_SUCCESS; | |
986 | } | |
987 | ||
988 | int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) | |
989 | { | |
990 | int retval; | |
991 | u8 ins, status, ewsr; | |
992 | ||
993 | ins = srb->cmnd[3]; | |
994 | status = srb->cmnd[4]; | |
995 | ewsr = srb->cmnd[5]; | |
996 | ||
997 | retval = spi_set_init_para(chip); | |
998 | if (retval != STATUS_SUCCESS) { | |
999 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
1000 | rtsx_trace(chip); |
1001 | return STATUS_FAIL; | |
fa590c22 MC |
1002 | } |
1003 | ||
1004 | retval = sf_enable_write(chip, ewsr); | |
031366ea JP |
1005 | if (retval != STATUS_SUCCESS) { |
1006 | rtsx_trace(chip); | |
1007 | return STATUS_FAIL; | |
1008 | } | |
fa590c22 MC |
1009 | |
1010 | rtsx_init_cmd(chip); | |
1011 | ||
1012 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, | |
1013 | PINGPONG_BUFFER); | |
1014 | ||
1015 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); | |
1016 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, | |
1017 | SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); | |
1018 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0); | |
1019 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1); | |
1020 | rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status); | |
1021 | rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, | |
1022 | SPI_TRANSFER0_START | SPI_CDO_MODE0); | |
1023 | rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, | |
1024 | SPI_TRANSFER0_END); | |
1025 | ||
1026 | retval = rtsx_send_cmd(chip, 0, 100); | |
1027 | if (retval != STATUS_SUCCESS) { | |
1028 | rtsx_clear_spi_error(chip); | |
1029 | spi_set_err_code(chip, SPI_HW_ERR); | |
031366ea JP |
1030 | rtsx_trace(chip); |
1031 | return STATUS_FAIL; | |
fa590c22 MC |
1032 | } |
1033 | ||
1034 | return STATUS_SUCCESS; | |
1035 | } |