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fa590c22 MC |
1 | /* Driver for Realtek PCI-Express card reader |
2 | * | |
3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2, or (at your option) any | |
8 | * later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: | |
19 | * Wei WANG (wei_wang@realsil.com.cn) | |
20 | * Micky Ching (micky_ching@realsil.com.cn) | |
21 | */ | |
22 | ||
23 | #include <linux/blkdev.h> | |
24 | #include <linux/kthread.h> | |
25 | #include <linux/sched.h> | |
26 | #include <linux/vmalloc.h> | |
27 | ||
28 | #include "rtsx.h" | |
29 | #include "rtsx_transport.h" | |
30 | #include "rtsx_scsi.h" | |
31 | #include "rtsx_card.h" | |
32 | #include "xd.h" | |
33 | ||
34 | static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no); | |
35 | static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, | |
36 | u8 start_page, u8 end_page); | |
37 | ||
38 | static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code) | |
39 | { | |
14c42c79 | 40 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
41 | |
42 | xd_card->err_code = err_code; | |
43 | } | |
44 | ||
45 | static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code) | |
46 | { | |
14c42c79 | 47 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
48 | |
49 | return (xd_card->err_code == err_code); | |
50 | } | |
51 | ||
52 | static int xd_set_init_para(struct rtsx_chip *chip) | |
53 | { | |
14c42c79 | 54 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
55 | int retval; |
56 | ||
57 | if (chip->asic_code) | |
58 | xd_card->xd_clock = 47; | |
59 | else | |
60 | xd_card->xd_clock = CLK_50; | |
61 | ||
62 | retval = switch_clock(chip, xd_card->xd_clock); | |
031366ea JP |
63 | if (retval != STATUS_SUCCESS) { |
64 | rtsx_trace(chip); | |
65 | return STATUS_FAIL; | |
66 | } | |
fa590c22 MC |
67 | |
68 | return STATUS_SUCCESS; | |
69 | } | |
70 | ||
71 | static int xd_switch_clock(struct rtsx_chip *chip) | |
72 | { | |
14c42c79 | 73 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
74 | int retval; |
75 | ||
76 | retval = select_card(chip, XD_CARD); | |
031366ea JP |
77 | if (retval != STATUS_SUCCESS) { |
78 | rtsx_trace(chip); | |
79 | return STATUS_FAIL; | |
80 | } | |
fa590c22 MC |
81 | |
82 | retval = switch_clock(chip, xd_card->xd_clock); | |
031366ea JP |
83 | if (retval != STATUS_SUCCESS) { |
84 | rtsx_trace(chip); | |
85 | return STATUS_FAIL; | |
86 | } | |
fa590c22 MC |
87 | |
88 | return STATUS_SUCCESS; | |
89 | } | |
90 | ||
91 | static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len) | |
92 | { | |
93 | int retval, i; | |
94 | u8 *ptr; | |
95 | ||
96 | rtsx_init_cmd(chip); | |
97 | ||
98 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd); | |
99 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, | |
dd67ec81 | 100 | XD_TRANSFER_START | XD_READ_ID); |
fa590c22 | 101 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, |
dd67ec81 | 102 | XD_TRANSFER_END); |
fa590c22 MC |
103 | |
104 | for (i = 0; i < 4; i++) | |
105 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0); | |
106 | ||
107 | retval = rtsx_send_cmd(chip, XD_CARD, 20); | |
031366ea JP |
108 | if (retval < 0) { |
109 | rtsx_trace(chip); | |
110 | return STATUS_FAIL; | |
111 | } | |
fa590c22 MC |
112 | |
113 | ptr = rtsx_get_cmd_data(chip) + 1; | |
114 | if (id_buf && buf_len) { | |
115 | if (buf_len > 4) | |
116 | buf_len = 4; | |
117 | memcpy(id_buf, ptr, buf_len); | |
118 | } | |
119 | ||
120 | return STATUS_SUCCESS; | |
121 | } | |
122 | ||
123 | static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode) | |
124 | { | |
14c42c79 | 125 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
126 | |
127 | switch (mode) { | |
128 | case XD_RW_ADDR: | |
129 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0); | |
130 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr); | |
131 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, | |
dd67ec81 | 132 | 0xFF, (u8)(addr >> 8)); |
fa590c22 | 133 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, |
dd67ec81 | 134 | 0xFF, (u8)(addr >> 16)); |
fa590c22 | 135 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, |
dd67ec81 WP |
136 | xd_card->addr_cycle | |
137 | XD_CALC_ECC | | |
138 | XD_BA_NO_TRANSFORM); | |
fa590c22 MC |
139 | break; |
140 | ||
141 | case XD_ERASE_ADDR: | |
142 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr); | |
143 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, | |
dd67ec81 | 144 | 0xFF, (u8)(addr >> 8)); |
fa590c22 | 145 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, |
dd67ec81 | 146 | 0xFF, (u8)(addr >> 16)); |
fa590c22 | 147 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, |
dd67ec81 | 148 | (xd_card->addr_cycle - 1) | XD_CALC_ECC | |
fa590c22 MC |
149 | XD_BA_NO_TRANSFORM); |
150 | break; | |
151 | ||
152 | default: | |
153 | break; | |
154 | } | |
155 | } | |
156 | ||
157 | static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr, | |
dd67ec81 | 158 | u8 *buf, int buf_len) |
fa590c22 MC |
159 | { |
160 | int retval, i; | |
161 | ||
162 | rtsx_init_cmd(chip); | |
163 | ||
164 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); | |
165 | ||
166 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, | |
dd67ec81 | 167 | 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT); |
fa590c22 | 168 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
dd67ec81 | 169 | XD_TRANSFER_END, XD_TRANSFER_END); |
fa590c22 MC |
170 | |
171 | for (i = 0; i < 6; i++) | |
172 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i), | |
dd67ec81 | 173 | 0, 0); |
fa590c22 MC |
174 | for (i = 0; i < 4; i++) |
175 | rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i), | |
dd67ec81 | 176 | 0, 0); |
fa590c22 MC |
177 | rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0); |
178 | ||
179 | retval = rtsx_send_cmd(chip, XD_CARD, 500); | |
031366ea JP |
180 | if (retval < 0) { |
181 | rtsx_trace(chip); | |
182 | return STATUS_FAIL; | |
183 | } | |
fa590c22 MC |
184 | |
185 | if (buf && buf_len) { | |
186 | u8 *ptr = rtsx_get_cmd_data(chip) + 1; | |
187 | ||
188 | if (buf_len > 11) | |
189 | buf_len = 11; | |
190 | memcpy(buf, ptr, buf_len); | |
191 | } | |
192 | ||
193 | return STATUS_SUCCESS; | |
194 | } | |
195 | ||
196 | static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset, | |
dd67ec81 | 197 | u8 *buf, int buf_len) |
fa590c22 MC |
198 | { |
199 | int retval, i; | |
200 | ||
031366ea JP |
201 | if (!buf || (buf_len < 0)) { |
202 | rtsx_trace(chip); | |
203 | return STATUS_FAIL; | |
204 | } | |
fa590c22 MC |
205 | |
206 | rtsx_init_cmd(chip); | |
207 | ||
208 | for (i = 0; i < buf_len; i++) | |
209 | rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, | |
dd67ec81 | 210 | 0, 0); |
fa590c22 MC |
211 | |
212 | retval = rtsx_send_cmd(chip, 0, 250); | |
213 | if (retval < 0) { | |
214 | rtsx_clear_xd_error(chip); | |
031366ea JP |
215 | rtsx_trace(chip); |
216 | return STATUS_FAIL; | |
fa590c22 MC |
217 | } |
218 | ||
219 | memcpy(buf, rtsx_get_cmd_data(chip), buf_len); | |
220 | ||
221 | return STATUS_SUCCESS; | |
222 | } | |
223 | ||
224 | static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, | |
dd67ec81 | 225 | int buf_len) |
fa590c22 MC |
226 | { |
227 | int retval; | |
228 | u8 reg; | |
229 | ||
031366ea JP |
230 | if (!buf || (buf_len < 10)) { |
231 | rtsx_trace(chip); | |
232 | return STATUS_FAIL; | |
233 | } | |
fa590c22 MC |
234 | |
235 | rtsx_init_cmd(chip); | |
236 | ||
237 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); | |
238 | ||
239 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, | |
dd67ec81 | 240 | 0x01, PINGPONG_BUFFER); |
fa590c22 MC |
241 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); |
242 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, | |
dd67ec81 | 243 | XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS); |
fa590c22 MC |
244 | |
245 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, | |
dd67ec81 | 246 | XD_TRANSFER_START | XD_READ_PAGES); |
fa590c22 | 247 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, |
dd67ec81 | 248 | XD_TRANSFER_END); |
fa590c22 MC |
249 | |
250 | retval = rtsx_send_cmd(chip, XD_CARD, 250); | |
251 | if (retval == -ETIMEDOUT) { | |
252 | rtsx_clear_xd_error(chip); | |
031366ea JP |
253 | rtsx_trace(chip); |
254 | return STATUS_FAIL; | |
fa590c22 MC |
255 | } |
256 | ||
8ee775f9 JP |
257 | retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®); |
258 | if (retval) { | |
259 | rtsx_trace(chip); | |
260 | return retval; | |
261 | } | |
fa590c22 MC |
262 | if (reg != XD_GPG) { |
263 | rtsx_clear_xd_error(chip); | |
031366ea JP |
264 | rtsx_trace(chip); |
265 | return STATUS_FAIL; | |
fa590c22 MC |
266 | } |
267 | ||
8ee775f9 JP |
268 | retval = rtsx_read_register(chip, XD_CTL, ®); |
269 | if (retval) { | |
270 | rtsx_trace(chip); | |
271 | return retval; | |
272 | } | |
fa590c22 MC |
273 | if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) { |
274 | retval = xd_read_data_from_ppb(chip, 0, buf, buf_len); | |
031366ea JP |
275 | if (retval != STATUS_SUCCESS) { |
276 | rtsx_trace(chip); | |
277 | return STATUS_FAIL; | |
278 | } | |
fa590c22 MC |
279 | if (reg & XD_ECC1_ERROR) { |
280 | u8 ecc_bit, ecc_byte; | |
281 | ||
8ee775f9 JP |
282 | retval = rtsx_read_register(chip, XD_ECC_BIT1, |
283 | &ecc_bit); | |
284 | if (retval) { | |
285 | rtsx_trace(chip); | |
286 | return retval; | |
287 | } | |
288 | retval = rtsx_read_register(chip, XD_ECC_BYTE1, | |
289 | &ecc_byte); | |
290 | if (retval) { | |
291 | rtsx_trace(chip); | |
292 | return retval; | |
293 | } | |
fa590c22 | 294 | |
bf6c0d11 | 295 | dev_dbg(rtsx_dev(chip), "ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n", |
fa590c22 MC |
296 | ecc_bit, ecc_byte); |
297 | if (ecc_byte < buf_len) { | |
bf6c0d11 | 298 | dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n", |
fa590c22 MC |
299 | buf[ecc_byte]); |
300 | buf[ecc_byte] ^= (1 << ecc_bit); | |
bf6c0d11 | 301 | dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n", |
fa590c22 MC |
302 | buf[ecc_byte]); |
303 | } | |
304 | } | |
305 | } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) { | |
306 | rtsx_clear_xd_error(chip); | |
307 | ||
308 | retval = xd_read_data_from_ppb(chip, 256, buf, buf_len); | |
031366ea JP |
309 | if (retval != STATUS_SUCCESS) { |
310 | rtsx_trace(chip); | |
311 | return STATUS_FAIL; | |
312 | } | |
fa590c22 MC |
313 | if (reg & XD_ECC2_ERROR) { |
314 | u8 ecc_bit, ecc_byte; | |
315 | ||
8ee775f9 JP |
316 | retval = rtsx_read_register(chip, XD_ECC_BIT2, |
317 | &ecc_bit); | |
318 | if (retval) { | |
319 | rtsx_trace(chip); | |
320 | return retval; | |
321 | } | |
322 | retval = rtsx_read_register(chip, XD_ECC_BYTE2, | |
323 | &ecc_byte); | |
324 | if (retval) { | |
325 | rtsx_trace(chip); | |
326 | return retval; | |
327 | } | |
fa590c22 | 328 | |
bf6c0d11 | 329 | dev_dbg(rtsx_dev(chip), "ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n", |
fa590c22 MC |
330 | ecc_bit, ecc_byte); |
331 | if (ecc_byte < buf_len) { | |
bf6c0d11 | 332 | dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n", |
fa590c22 MC |
333 | buf[ecc_byte]); |
334 | buf[ecc_byte] ^= (1 << ecc_bit); | |
bf6c0d11 | 335 | dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n", |
fa590c22 MC |
336 | buf[ecc_byte]); |
337 | } | |
338 | } | |
339 | } else { | |
340 | rtsx_clear_xd_error(chip); | |
031366ea JP |
341 | rtsx_trace(chip); |
342 | return STATUS_FAIL; | |
fa590c22 MC |
343 | } |
344 | ||
345 | return STATUS_SUCCESS; | |
346 | } | |
347 | ||
348 | static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip) | |
349 | { | |
350 | if (CHECK_PID(chip, 0x5208)) { | |
351 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, | |
dd67ec81 | 352 | XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); |
fa590c22 | 353 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, |
dd67ec81 | 354 | XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); |
fa590c22 | 355 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, |
dd67ec81 | 356 | XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); |
fa590c22 | 357 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, |
dd67ec81 | 358 | XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD); |
fa590c22 | 359 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, |
dd67ec81 | 360 | MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); |
fa590c22 | 361 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, |
dd67ec81 | 362 | MS_D5_PD | MS_D4_PD); |
fa590c22 MC |
363 | } else if (CHECK_PID(chip, 0x5288)) { |
364 | if (CHECK_BARO_PKG(chip, QFN)) { | |
365 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, | |
dd67ec81 | 366 | 0xFF, 0x55); |
fa590c22 | 367 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, |
dd67ec81 | 368 | 0xFF, 0x55); |
fa590c22 | 369 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, |
dd67ec81 | 370 | 0xFF, 0x4B); |
fa590c22 | 371 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, |
dd67ec81 | 372 | 0xFF, 0x69); |
fa590c22 MC |
373 | } |
374 | } | |
375 | } | |
376 | ||
377 | static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip) | |
378 | { | |
379 | if (CHECK_BARO_PKG(chip, QFN)) { | |
380 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55); | |
381 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55); | |
382 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B); | |
383 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55); | |
384 | } | |
385 | } | |
386 | ||
387 | static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip) | |
388 | { | |
389 | if (CHECK_PID(chip, 0x5208)) { | |
390 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, | |
dd67ec81 | 391 | XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); |
fa590c22 | 392 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, |
dd67ec81 | 393 | XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); |
fa590c22 | 394 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, |
dd67ec81 | 395 | XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU); |
fa590c22 | 396 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, |
dd67ec81 | 397 | XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD); |
fa590c22 | 398 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, |
dd67ec81 | 399 | MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); |
fa590c22 | 400 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, |
dd67ec81 | 401 | MS_D5_PD | MS_D4_PD); |
fa590c22 MC |
402 | } else if (CHECK_PID(chip, 0x5288)) { |
403 | if (CHECK_BARO_PKG(chip, QFN)) { | |
404 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, | |
dd67ec81 | 405 | 0xFF, 0x55); |
fa590c22 | 406 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, |
dd67ec81 | 407 | 0xFF, 0x55); |
fa590c22 | 408 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, |
dd67ec81 | 409 | 0xFF, 0x53); |
fa590c22 | 410 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, |
dd67ec81 | 411 | 0xFF, 0xA9); |
fa590c22 MC |
412 | } |
413 | } | |
414 | } | |
415 | ||
416 | static int xd_pull_ctl_disable(struct rtsx_chip *chip) | |
417 | { | |
8ee775f9 JP |
418 | int retval; |
419 | ||
fa590c22 | 420 | if (CHECK_PID(chip, 0x5208)) { |
8ee775f9 | 421 | retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, |
dd67ec81 WP |
422 | XD_D3_PD | |
423 | XD_D2_PD | | |
424 | XD_D1_PD | | |
425 | XD_D0_PD); | |
8ee775f9 JP |
426 | if (retval) { |
427 | rtsx_trace(chip); | |
428 | return retval; | |
429 | } | |
430 | retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, | |
dd67ec81 WP |
431 | XD_D7_PD | |
432 | XD_D6_PD | | |
433 | XD_D5_PD | | |
434 | XD_D4_PD); | |
8ee775f9 JP |
435 | if (retval) { |
436 | rtsx_trace(chip); | |
437 | return retval; | |
438 | } | |
439 | retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, | |
dd67ec81 WP |
440 | XD_WP_PD | |
441 | XD_CE_PD | | |
442 | XD_CLE_PD | | |
443 | XD_CD_PU); | |
8ee775f9 JP |
444 | if (retval) { |
445 | rtsx_trace(chip); | |
446 | return retval; | |
447 | } | |
448 | retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, | |
dd67ec81 WP |
449 | XD_RDY_PD | |
450 | XD_WE_PD | | |
451 | XD_RE_PD | | |
452 | XD_ALE_PD); | |
8ee775f9 JP |
453 | if (retval) { |
454 | rtsx_trace(chip); | |
455 | return retval; | |
456 | } | |
457 | retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, | |
dd67ec81 WP |
458 | MS_INS_PU | |
459 | SD_WP_PD | | |
460 | SD_CD_PU | | |
461 | SD_CMD_PD); | |
8ee775f9 JP |
462 | if (retval) { |
463 | rtsx_trace(chip); | |
464 | return retval; | |
465 | } | |
466 | retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, | |
467 | MS_D5_PD | MS_D4_PD); | |
468 | if (retval) { | |
469 | rtsx_trace(chip); | |
470 | return retval; | |
471 | } | |
fa590c22 MC |
472 | } else if (CHECK_PID(chip, 0x5288)) { |
473 | if (CHECK_BARO_PKG(chip, QFN)) { | |
8ee775f9 JP |
474 | retval = rtsx_write_register(chip, CARD_PULL_CTL1, |
475 | 0xFF, 0x55); | |
476 | if (retval) { | |
477 | rtsx_trace(chip); | |
478 | return retval; | |
479 | } | |
480 | retval = rtsx_write_register(chip, CARD_PULL_CTL2, | |
481 | 0xFF, 0x55); | |
482 | if (retval) { | |
483 | rtsx_trace(chip); | |
484 | return retval; | |
485 | } | |
486 | retval = rtsx_write_register(chip, CARD_PULL_CTL3, | |
487 | 0xFF, 0x4B); | |
488 | if (retval) { | |
489 | rtsx_trace(chip); | |
490 | return retval; | |
491 | } | |
492 | retval = rtsx_write_register(chip, CARD_PULL_CTL4, | |
493 | 0xFF, 0x69); | |
494 | if (retval) { | |
495 | rtsx_trace(chip); | |
496 | return retval; | |
497 | } | |
fa590c22 MC |
498 | } |
499 | } | |
500 | ||
501 | return STATUS_SUCCESS; | |
502 | } | |
503 | ||
504 | static int reset_xd(struct rtsx_chip *chip) | |
505 | { | |
14c42c79 | 506 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
507 | int retval, i, j; |
508 | u8 *ptr, id_buf[4], redunt[11]; | |
509 | ||
510 | retval = select_card(chip, XD_CARD); | |
031366ea JP |
511 | if (retval != STATUS_SUCCESS) { |
512 | rtsx_trace(chip); | |
513 | return STATUS_FAIL; | |
514 | } | |
fa590c22 MC |
515 | |
516 | rtsx_init_cmd(chip); | |
517 | ||
518 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF, | |
dd67ec81 | 519 | XD_PGSTS_NOT_FF); |
fa590c22 MC |
520 | if (chip->asic_code) { |
521 | if (!CHECK_PID(chip, 0x5288)) | |
522 | xd_fill_pull_ctl_disable(chip); | |
523 | else | |
524 | xd_fill_pull_ctl_stage1_barossa(chip); | |
525 | } else { | |
526 | rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, | |
dd67ec81 WP |
527 | (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | |
528 | 0x20); | |
fa590c22 MC |
529 | } |
530 | ||
531 | if (!chip->ft2_fast_mode) | |
532 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT, | |
dd67ec81 | 533 | XD_NO_AUTO_PWR_OFF, 0); |
fa590c22 MC |
534 | |
535 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0); | |
536 | ||
537 | retval = rtsx_send_cmd(chip, XD_CARD, 100); | |
031366ea JP |
538 | if (retval < 0) { |
539 | rtsx_trace(chip); | |
540 | return STATUS_FAIL; | |
541 | } | |
fa590c22 MC |
542 | |
543 | if (!chip->ft2_fast_mode) { | |
544 | retval = card_power_off(chip, XD_CARD); | |
031366ea JP |
545 | if (retval != STATUS_SUCCESS) { |
546 | rtsx_trace(chip); | |
547 | return STATUS_FAIL; | |
548 | } | |
fa590c22 MC |
549 | |
550 | wait_timeout(250); | |
551 | ||
552 | rtsx_init_cmd(chip); | |
553 | ||
554 | if (chip->asic_code) { | |
555 | xd_fill_pull_ctl_enable(chip); | |
556 | } else { | |
557 | rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, | |
dd67ec81 WP |
558 | (FPGA_XD_PULL_CTL_EN1 & |
559 | FPGA_XD_PULL_CTL_EN2) | | |
560 | 0x20); | |
fa590c22 MC |
561 | } |
562 | ||
563 | retval = rtsx_send_cmd(chip, XD_CARD, 100); | |
031366ea JP |
564 | if (retval < 0) { |
565 | rtsx_trace(chip); | |
566 | return STATUS_FAIL; | |
567 | } | |
fa590c22 MC |
568 | |
569 | retval = card_power_on(chip, XD_CARD); | |
031366ea JP |
570 | if (retval != STATUS_SUCCESS) { |
571 | rtsx_trace(chip); | |
572 | return STATUS_FAIL; | |
573 | } | |
fa590c22 MC |
574 | |
575 | #ifdef SUPPORT_OCP | |
576 | wait_timeout(50); | |
577 | if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { | |
bf6c0d11 | 578 | dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", |
fa590c22 | 579 | chip->ocp_stat); |
031366ea JP |
580 | rtsx_trace(chip); |
581 | return STATUS_FAIL; | |
fa590c22 MC |
582 | } |
583 | #endif | |
584 | } | |
585 | ||
586 | rtsx_init_cmd(chip); | |
587 | ||
588 | if (chip->ft2_fast_mode) { | |
589 | if (chip->asic_code) { | |
590 | xd_fill_pull_ctl_enable(chip); | |
591 | } else { | |
592 | rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, | |
dd67ec81 WP |
593 | (FPGA_XD_PULL_CTL_EN1 & |
594 | FPGA_XD_PULL_CTL_EN2) | | |
595 | 0x20); | |
fa590c22 MC |
596 | } |
597 | } | |
598 | ||
599 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN); | |
600 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN); | |
601 | ||
602 | retval = rtsx_send_cmd(chip, XD_CARD, 100); | |
031366ea JP |
603 | if (retval < 0) { |
604 | rtsx_trace(chip); | |
605 | return STATUS_FAIL; | |
606 | } | |
fa590c22 MC |
607 | |
608 | if (!chip->ft2_fast_mode) | |
609 | wait_timeout(200); | |
610 | ||
611 | retval = xd_set_init_para(chip); | |
031366ea JP |
612 | if (retval != STATUS_SUCCESS) { |
613 | rtsx_trace(chip); | |
614 | return STATUS_FAIL; | |
615 | } | |
fa590c22 MC |
616 | |
617 | /* Read ID to check if the timing setting is right */ | |
618 | for (i = 0; i < 4; i++) { | |
619 | rtsx_init_cmd(chip); | |
620 | ||
621 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF, | |
dd67ec81 WP |
622 | XD_TIME_SETUP_STEP * 3 + |
623 | XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i); | |
fa590c22 | 624 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF, |
dd67ec81 WP |
625 | XD_TIME_SETUP_STEP * 3 + |
626 | XD_TIME_RW_STEP * (4 + i) + | |
627 | XD_TIME_RWN_STEP * (3 + i)); | |
fa590c22 MC |
628 | |
629 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, | |
dd67ec81 | 630 | XD_TRANSFER_START | XD_RESET); |
fa590c22 | 631 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
dd67ec81 | 632 | XD_TRANSFER_END, XD_TRANSFER_END); |
fa590c22 MC |
633 | |
634 | rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); | |
635 | rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); | |
636 | ||
637 | retval = rtsx_send_cmd(chip, XD_CARD, 100); | |
031366ea JP |
638 | if (retval < 0) { |
639 | rtsx_trace(chip); | |
640 | return STATUS_FAIL; | |
641 | } | |
fa590c22 MC |
642 | |
643 | ptr = rtsx_get_cmd_data(chip) + 1; | |
644 | ||
bf6c0d11 FF |
645 | dev_dbg(rtsx_dev(chip), "XD_DAT: 0x%x, XD_CTL: 0x%x\n", |
646 | ptr[0], ptr[1]); | |
fa590c22 MC |
647 | |
648 | if (((ptr[0] & READY_FLAG) != READY_STATE) || | |
dd67ec81 | 649 | !(ptr[1] & XD_RDY)) |
fa590c22 MC |
650 | continue; |
651 | ||
652 | retval = xd_read_id(chip, READ_ID, id_buf, 4); | |
031366ea JP |
653 | if (retval != STATUS_SUCCESS) { |
654 | rtsx_trace(chip); | |
655 | return STATUS_FAIL; | |
656 | } | |
fa590c22 | 657 | |
bf6c0d11 | 658 | dev_dbg(rtsx_dev(chip), "READ_ID: 0x%x 0x%x 0x%x 0x%x\n", |
fa590c22 MC |
659 | id_buf[0], id_buf[1], id_buf[2], id_buf[3]); |
660 | ||
661 | xd_card->device_code = id_buf[1]; | |
662 | ||
663 | /* Check if the xD card is supported */ | |
664 | switch (xd_card->device_code) { | |
665 | case XD_4M_X8_512_1: | |
666 | case XD_4M_X8_512_2: | |
667 | xd_card->block_shift = 4; | |
668 | xd_card->page_off = 0x0F; | |
669 | xd_card->addr_cycle = 3; | |
670 | xd_card->zone_cnt = 1; | |
671 | xd_card->capacity = 8000; | |
672 | XD_SET_4MB(xd_card); | |
673 | break; | |
674 | case XD_8M_X8_512: | |
675 | xd_card->block_shift = 4; | |
676 | xd_card->page_off = 0x0F; | |
677 | xd_card->addr_cycle = 3; | |
678 | xd_card->zone_cnt = 1; | |
679 | xd_card->capacity = 16000; | |
680 | break; | |
681 | case XD_16M_X8_512: | |
682 | XD_PAGE_512(xd_card); | |
683 | xd_card->addr_cycle = 3; | |
684 | xd_card->zone_cnt = 1; | |
685 | xd_card->capacity = 32000; | |
686 | break; | |
687 | case XD_32M_X8_512: | |
688 | XD_PAGE_512(xd_card); | |
689 | xd_card->addr_cycle = 3; | |
690 | xd_card->zone_cnt = 2; | |
691 | xd_card->capacity = 64000; | |
692 | break; | |
693 | case XD_64M_X8_512: | |
694 | XD_PAGE_512(xd_card); | |
695 | xd_card->addr_cycle = 4; | |
696 | xd_card->zone_cnt = 4; | |
697 | xd_card->capacity = 128000; | |
698 | break; | |
699 | case XD_128M_X8_512: | |
700 | XD_PAGE_512(xd_card); | |
701 | xd_card->addr_cycle = 4; | |
702 | xd_card->zone_cnt = 8; | |
703 | xd_card->capacity = 256000; | |
704 | break; | |
705 | case XD_256M_X8_512: | |
706 | XD_PAGE_512(xd_card); | |
707 | xd_card->addr_cycle = 4; | |
708 | xd_card->zone_cnt = 16; | |
709 | xd_card->capacity = 512000; | |
710 | break; | |
711 | case XD_512M_X8: | |
712 | XD_PAGE_512(xd_card); | |
713 | xd_card->addr_cycle = 4; | |
714 | xd_card->zone_cnt = 32; | |
715 | xd_card->capacity = 1024000; | |
716 | break; | |
717 | case xD_1G_X8_512: | |
718 | XD_PAGE_512(xd_card); | |
719 | xd_card->addr_cycle = 4; | |
720 | xd_card->zone_cnt = 64; | |
721 | xd_card->capacity = 2048000; | |
722 | break; | |
723 | case xD_2G_X8_512: | |
724 | XD_PAGE_512(xd_card); | |
725 | xd_card->addr_cycle = 4; | |
726 | xd_card->zone_cnt = 128; | |
727 | xd_card->capacity = 4096000; | |
728 | break; | |
729 | default: | |
730 | continue; | |
731 | } | |
732 | ||
733 | /* Confirm timing setting */ | |
734 | for (j = 0; j < 10; j++) { | |
735 | retval = xd_read_id(chip, READ_ID, id_buf, 4); | |
031366ea JP |
736 | if (retval != STATUS_SUCCESS) { |
737 | rtsx_trace(chip); | |
738 | return STATUS_FAIL; | |
739 | } | |
fa590c22 MC |
740 | |
741 | if (id_buf[1] != xd_card->device_code) | |
742 | break; | |
743 | } | |
744 | ||
745 | if (j == 10) | |
746 | break; | |
747 | } | |
748 | ||
749 | if (i == 4) { | |
750 | xd_card->block_shift = 0; | |
751 | xd_card->page_off = 0; | |
752 | xd_card->addr_cycle = 0; | |
753 | xd_card->capacity = 0; | |
754 | ||
031366ea JP |
755 | rtsx_trace(chip); |
756 | return STATUS_FAIL; | |
fa590c22 MC |
757 | } |
758 | ||
759 | retval = xd_read_id(chip, READ_xD_ID, id_buf, 4); | |
031366ea JP |
760 | if (retval != STATUS_SUCCESS) { |
761 | rtsx_trace(chip); | |
762 | return STATUS_FAIL; | |
763 | } | |
bf6c0d11 FF |
764 | dev_dbg(rtsx_dev(chip), "READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n", |
765 | id_buf[0], id_buf[1], id_buf[2], id_buf[3]); | |
031366ea JP |
766 | if (id_buf[2] != XD_ID_CODE) { |
767 | rtsx_trace(chip); | |
768 | return STATUS_FAIL; | |
769 | } | |
fa590c22 MC |
770 | |
771 | /* Search CIS block */ | |
772 | for (i = 0; i < 24; i++) { | |
773 | u32 page_addr; | |
774 | ||
031366ea JP |
775 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { |
776 | rtsx_trace(chip); | |
777 | return STATUS_FAIL; | |
778 | } | |
fa590c22 MC |
779 | |
780 | page_addr = (u32)i << xd_card->block_shift; | |
781 | ||
782 | for (j = 0; j < 3; j++) { | |
783 | retval = xd_read_redundant(chip, page_addr, redunt, 11); | |
784 | if (retval == STATUS_SUCCESS) | |
785 | break; | |
786 | } | |
787 | if (j == 3) | |
788 | continue; | |
789 | ||
790 | if (redunt[BLOCK_STATUS] != XD_GBLK) | |
791 | continue; | |
792 | ||
793 | j = 0; | |
794 | if (redunt[PAGE_STATUS] != XD_GPG) { | |
795 | for (j = 1; j <= 8; j++) { | |
796 | retval = xd_read_redundant(chip, page_addr + j, | |
dd67ec81 | 797 | redunt, 11); |
fa590c22 MC |
798 | if (retval == STATUS_SUCCESS) { |
799 | if (redunt[PAGE_STATUS] == XD_GPG) | |
800 | break; | |
801 | } | |
802 | } | |
803 | ||
804 | if (j == 9) | |
805 | break; | |
806 | } | |
807 | ||
808 | /* Check CIS data */ | |
809 | if ((redunt[BLOCK_STATUS] == XD_GBLK) && | |
dd67ec81 | 810 | (redunt[PARITY] & XD_BA1_ALL0)) { |
fa590c22 MC |
811 | u8 buf[10]; |
812 | ||
813 | page_addr += j; | |
814 | ||
815 | retval = xd_read_cis(chip, page_addr, buf, 10); | |
031366ea JP |
816 | if (retval != STATUS_SUCCESS) { |
817 | rtsx_trace(chip); | |
818 | return STATUS_FAIL; | |
819 | } | |
fa590c22 MC |
820 | |
821 | if ((buf[0] == 0x01) && (buf[1] == 0x03) && | |
d5549720 WP |
822 | (buf[2] == 0xD9) && |
823 | (buf[3] == 0x01) && (buf[4] == 0xFF) && | |
824 | (buf[5] == 0x18) && (buf[6] == 0x02) && | |
825 | (buf[7] == 0xDF) && (buf[8] == 0x01) && | |
826 | (buf[9] == 0x20)) { | |
fa590c22 MC |
827 | xd_card->cis_block = (u16)i; |
828 | } | |
829 | } | |
830 | ||
831 | break; | |
832 | } | |
833 | ||
bf6c0d11 | 834 | dev_dbg(rtsx_dev(chip), "CIS block: 0x%x\n", xd_card->cis_block); |
031366ea JP |
835 | if (xd_card->cis_block == 0xFFFF) { |
836 | rtsx_trace(chip); | |
837 | return STATUS_FAIL; | |
838 | } | |
fa590c22 MC |
839 | |
840 | chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity; | |
841 | ||
842 | return STATUS_SUCCESS; | |
843 | } | |
844 | ||
845 | static int xd_check_data_blank(u8 *redunt) | |
846 | { | |
847 | int i; | |
848 | ||
849 | for (i = 0; i < 6; i++) { | |
850 | if (redunt[PAGE_STATUS + i] != 0xFF) | |
851 | return 0; | |
852 | } | |
853 | ||
854 | if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) | |
855 | != (XD_ECC1_ALL1 | XD_ECC2_ALL1)) | |
856 | return 0; | |
857 | ||
fa590c22 MC |
858 | for (i = 0; i < 4; i++) { |
859 | if (redunt[RESERVED0 + i] != 0xFF) | |
860 | return 0; | |
861 | } | |
862 | ||
863 | return 1; | |
864 | } | |
865 | ||
866 | static u16 xd_load_log_block_addr(u8 *redunt) | |
867 | { | |
868 | u16 addr = 0xFFFF; | |
869 | ||
870 | if (redunt[PARITY] & XD_BA1_BA2_EQL) | |
871 | addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | | |
872 | redunt[BLOCK_ADDR1_L]; | |
873 | else if (redunt[PARITY] & XD_BA1_VALID) | |
874 | addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | | |
875 | redunt[BLOCK_ADDR1_L]; | |
876 | else if (redunt[PARITY] & XD_BA2_VALID) | |
877 | addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) | | |
878 | redunt[BLOCK_ADDR2_L]; | |
879 | ||
880 | return addr; | |
881 | } | |
882 | ||
883 | static int xd_init_l2p_tbl(struct rtsx_chip *chip) | |
884 | { | |
14c42c79 | 885 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
886 | int size, i; |
887 | ||
bf6c0d11 FF |
888 | dev_dbg(rtsx_dev(chip), "xd_init_l2p_tbl: zone_cnt = %d\n", |
889 | xd_card->zone_cnt); | |
fa590c22 | 890 | |
031366ea JP |
891 | if (xd_card->zone_cnt < 1) { |
892 | rtsx_trace(chip); | |
893 | return STATUS_FAIL; | |
894 | } | |
fa590c22 MC |
895 | |
896 | size = xd_card->zone_cnt * sizeof(struct zone_entry); | |
bf6c0d11 | 897 | dev_dbg(rtsx_dev(chip), "Buffer size for l2p table is %d\n", size); |
fa590c22 MC |
898 | |
899 | xd_card->zone = vmalloc(size); | |
031366ea JP |
900 | if (!xd_card->zone) { |
901 | rtsx_trace(chip); | |
902 | return STATUS_ERROR; | |
903 | } | |
fa590c22 MC |
904 | |
905 | for (i = 0; i < xd_card->zone_cnt; i++) { | |
906 | xd_card->zone[i].build_flag = 0; | |
907 | xd_card->zone[i].l2p_table = NULL; | |
908 | xd_card->zone[i].free_table = NULL; | |
909 | xd_card->zone[i].get_index = 0; | |
910 | xd_card->zone[i].set_index = 0; | |
911 | xd_card->zone[i].unused_blk_cnt = 0; | |
912 | } | |
913 | ||
914 | return STATUS_SUCCESS; | |
915 | } | |
916 | ||
917 | static inline void free_zone(struct zone_entry *zone) | |
918 | { | |
fa590c22 MC |
919 | if (!zone) |
920 | return; | |
921 | ||
922 | zone->build_flag = 0; | |
923 | zone->set_index = 0; | |
924 | zone->get_index = 0; | |
925 | zone->unused_blk_cnt = 0; | |
b242d05f BS |
926 | vfree(zone->l2p_table); |
927 | zone->l2p_table = NULL; | |
928 | vfree(zone->free_table); | |
929 | zone->free_table = NULL; | |
fa590c22 MC |
930 | } |
931 | ||
932 | static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk) | |
933 | { | |
14c42c79 | 934 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
935 | struct zone_entry *zone; |
936 | int zone_no; | |
937 | ||
938 | zone_no = (int)phy_blk >> 10; | |
939 | if (zone_no >= xd_card->zone_cnt) { | |
bf6c0d11 | 940 | dev_dbg(rtsx_dev(chip), "Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n", |
fa590c22 MC |
941 | zone_no, xd_card->zone_cnt); |
942 | return; | |
943 | } | |
14c42c79 | 944 | zone = &xd_card->zone[zone_no]; |
fa590c22 | 945 | |
daaca111 | 946 | if (!zone->free_table) { |
fa590c22 MC |
947 | if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS) |
948 | return; | |
949 | } | |
950 | ||
d5549720 WP |
951 | if ((zone->set_index >= XD_FREE_TABLE_CNT) || |
952 | (zone->set_index < 0)) { | |
fa590c22 | 953 | free_zone(zone); |
bf6c0d11 | 954 | dev_dbg(rtsx_dev(chip), "Set unused block fail, invalid set_index\n"); |
fa590c22 MC |
955 | return; |
956 | } | |
957 | ||
bf6c0d11 FF |
958 | dev_dbg(rtsx_dev(chip), "Set unused block to index %d\n", |
959 | zone->set_index); | |
fa590c22 | 960 | |
7c7f2361 | 961 | zone->free_table[zone->set_index++] = (u16)(phy_blk & 0x3ff); |
fa590c22 MC |
962 | if (zone->set_index >= XD_FREE_TABLE_CNT) |
963 | zone->set_index = 0; | |
964 | zone->unused_blk_cnt++; | |
965 | } | |
966 | ||
967 | static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no) | |
968 | { | |
14c42c79 | 969 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
970 | struct zone_entry *zone; |
971 | u32 phy_blk; | |
972 | ||
973 | if (zone_no >= xd_card->zone_cnt) { | |
bf6c0d11 | 974 | dev_dbg(rtsx_dev(chip), "Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n", |
fa590c22 MC |
975 | zone_no, xd_card->zone_cnt); |
976 | return BLK_NOT_FOUND; | |
977 | } | |
14c42c79 | 978 | zone = &xd_card->zone[zone_no]; |
fa590c22 MC |
979 | |
980 | if ((zone->unused_blk_cnt == 0) || | |
dd67ec81 | 981 | (zone->set_index == zone->get_index)) { |
fa590c22 | 982 | free_zone(zone); |
bf6c0d11 | 983 | dev_dbg(rtsx_dev(chip), "Get unused block fail, no unused block available\n"); |
fa590c22 MC |
984 | return BLK_NOT_FOUND; |
985 | } | |
986 | if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) { | |
987 | free_zone(zone); | |
bf6c0d11 | 988 | dev_dbg(rtsx_dev(chip), "Get unused block fail, invalid get_index\n"); |
fa590c22 MC |
989 | return BLK_NOT_FOUND; |
990 | } | |
991 | ||
bf6c0d11 FF |
992 | dev_dbg(rtsx_dev(chip), "Get unused block from index %d\n", |
993 | zone->get_index); | |
fa590c22 MC |
994 | |
995 | phy_blk = zone->free_table[zone->get_index]; | |
996 | zone->free_table[zone->get_index++] = 0xFFFF; | |
997 | if (zone->get_index >= XD_FREE_TABLE_CNT) | |
998 | zone->get_index = 0; | |
999 | zone->unused_blk_cnt--; | |
1000 | ||
1001 | phy_blk += ((u32)(zone_no) << 10); | |
1002 | return phy_blk; | |
1003 | } | |
1004 | ||
1005 | static void xd_set_l2p_tbl(struct rtsx_chip *chip, | |
dd67ec81 | 1006 | int zone_no, u16 log_off, u16 phy_off) |
fa590c22 | 1007 | { |
14c42c79 | 1008 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1009 | struct zone_entry *zone; |
1010 | ||
14c42c79 | 1011 | zone = &xd_card->zone[zone_no]; |
fa590c22 MC |
1012 | zone->l2p_table[log_off] = phy_off; |
1013 | } | |
1014 | ||
1015 | static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off) | |
1016 | { | |
14c42c79 | 1017 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1018 | struct zone_entry *zone; |
1019 | int retval; | |
1020 | ||
14c42c79 | 1021 | zone = &xd_card->zone[zone_no]; |
fa590c22 MC |
1022 | if (zone->l2p_table[log_off] == 0xFFFF) { |
1023 | u32 phy_blk = 0; | |
1024 | int i; | |
1025 | ||
1026 | #ifdef XD_DELAY_WRITE | |
1027 | retval = xd_delay_write(chip); | |
1028 | if (retval != STATUS_SUCCESS) { | |
bf6c0d11 | 1029 | dev_dbg(rtsx_dev(chip), "In xd_get_l2p_tbl, delay write fail!\n"); |
fa590c22 MC |
1030 | return BLK_NOT_FOUND; |
1031 | } | |
1032 | #endif | |
1033 | ||
1034 | if (zone->unused_blk_cnt <= 0) { | |
bf6c0d11 | 1035 | dev_dbg(rtsx_dev(chip), "No unused block!\n"); |
fa590c22 MC |
1036 | return BLK_NOT_FOUND; |
1037 | } | |
1038 | ||
1039 | for (i = 0; i < zone->unused_blk_cnt; i++) { | |
1040 | phy_blk = xd_get_unused_block(chip, zone_no); | |
1041 | if (phy_blk == BLK_NOT_FOUND) { | |
bf6c0d11 | 1042 | dev_dbg(rtsx_dev(chip), "No unused block available!\n"); |
fa590c22 MC |
1043 | return BLK_NOT_FOUND; |
1044 | } | |
1045 | ||
1046 | retval = xd_init_page(chip, phy_blk, log_off, | |
dd67ec81 | 1047 | 0, xd_card->page_off + 1); |
fa590c22 MC |
1048 | if (retval == STATUS_SUCCESS) |
1049 | break; | |
1050 | } | |
1051 | if (i >= zone->unused_blk_cnt) { | |
bf6c0d11 | 1052 | dev_dbg(rtsx_dev(chip), "No good unused block available!\n"); |
fa590c22 MC |
1053 | return BLK_NOT_FOUND; |
1054 | } | |
1055 | ||
1056 | xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF)); | |
1057 | return phy_blk; | |
1058 | } | |
1059 | ||
1060 | return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10); | |
1061 | } | |
1062 | ||
1063 | int reset_xd_card(struct rtsx_chip *chip) | |
1064 | { | |
14c42c79 | 1065 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1066 | int retval; |
1067 | ||
1068 | memset(xd_card, 0, sizeof(struct xd_info)); | |
1069 | ||
1070 | xd_card->block_shift = 0; | |
1071 | xd_card->page_off = 0; | |
1072 | xd_card->addr_cycle = 0; | |
1073 | xd_card->capacity = 0; | |
1074 | xd_card->zone_cnt = 0; | |
1075 | xd_card->cis_block = 0xFFFF; | |
1076 | xd_card->delay_write.delay_write_flag = 0; | |
1077 | ||
1078 | retval = enable_card_clock(chip, XD_CARD); | |
031366ea JP |
1079 | if (retval != STATUS_SUCCESS) { |
1080 | rtsx_trace(chip); | |
1081 | return STATUS_FAIL; | |
1082 | } | |
fa590c22 MC |
1083 | |
1084 | retval = reset_xd(chip); | |
031366ea JP |
1085 | if (retval != STATUS_SUCCESS) { |
1086 | rtsx_trace(chip); | |
1087 | return STATUS_FAIL; | |
1088 | } | |
fa590c22 MC |
1089 | |
1090 | retval = xd_init_l2p_tbl(chip); | |
031366ea JP |
1091 | if (retval != STATUS_SUCCESS) { |
1092 | rtsx_trace(chip); | |
1093 | return STATUS_FAIL; | |
1094 | } | |
fa590c22 MC |
1095 | |
1096 | return STATUS_SUCCESS; | |
1097 | } | |
1098 | ||
1099 | static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk) | |
1100 | { | |
14c42c79 | 1101 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1102 | int retval; |
1103 | u32 page_addr; | |
1104 | u8 reg = 0; | |
1105 | ||
bf6c0d11 | 1106 | dev_dbg(rtsx_dev(chip), "mark block 0x%x as bad block\n", phy_blk); |
fa590c22 | 1107 | |
031366ea JP |
1108 | if (phy_blk == BLK_NOT_FOUND) { |
1109 | rtsx_trace(chip); | |
1110 | return STATUS_FAIL; | |
1111 | } | |
fa590c22 MC |
1112 | |
1113 | rtsx_init_cmd(chip); | |
1114 | ||
1115 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG); | |
1116 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK); | |
1117 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF); | |
1118 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF); | |
1119 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF); | |
1120 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF); | |
1121 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF); | |
1122 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF); | |
1123 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF); | |
1124 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF); | |
1125 | ||
1126 | page_addr = phy_blk << xd_card->block_shift; | |
1127 | ||
1128 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); | |
1129 | ||
1130 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, | |
dd67ec81 | 1131 | xd_card->page_off + 1); |
fa590c22 MC |
1132 | |
1133 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, | |
dd67ec81 | 1134 | XD_TRANSFER_START | XD_WRITE_REDUNDANT); |
fa590c22 | 1135 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
dd67ec81 | 1136 | XD_TRANSFER_END, XD_TRANSFER_END); |
fa590c22 MC |
1137 | |
1138 | retval = rtsx_send_cmd(chip, XD_CARD, 500); | |
1139 | if (retval < 0) { | |
1140 | rtsx_clear_xd_error(chip); | |
1141 | rtsx_read_register(chip, XD_DAT, ®); | |
1142 | if (reg & PROGRAM_ERROR) | |
1143 | xd_set_err_code(chip, XD_PRG_ERROR); | |
1144 | else | |
1145 | xd_set_err_code(chip, XD_TO_ERROR); | |
031366ea JP |
1146 | rtsx_trace(chip); |
1147 | return STATUS_FAIL; | |
fa590c22 MC |
1148 | } |
1149 | ||
1150 | return STATUS_SUCCESS; | |
1151 | } | |
1152 | ||
1153 | static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, | |
1154 | u16 logoff, u8 start_page, u8 end_page) | |
1155 | { | |
14c42c79 | 1156 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1157 | int retval; |
1158 | u32 page_addr; | |
1159 | u8 reg = 0; | |
1160 | ||
bf6c0d11 | 1161 | dev_dbg(rtsx_dev(chip), "Init block 0x%x\n", phy_blk); |
fa590c22 | 1162 | |
031366ea JP |
1163 | if (start_page > end_page) { |
1164 | rtsx_trace(chip); | |
1165 | return STATUS_FAIL; | |
1166 | } | |
1167 | if (phy_blk == BLK_NOT_FOUND) { | |
1168 | rtsx_trace(chip); | |
1169 | return STATUS_FAIL; | |
1170 | } | |
fa590c22 MC |
1171 | |
1172 | rtsx_init_cmd(chip); | |
1173 | ||
1174 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF); | |
1175 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF); | |
1176 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, | |
dd67ec81 | 1177 | 0xFF, (u8)(logoff >> 8)); |
fa590c22 MC |
1178 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff); |
1179 | ||
1180 | page_addr = (phy_blk << xd_card->block_shift) + start_page; | |
1181 | ||
1182 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); | |
1183 | ||
1184 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, | |
dd67ec81 | 1185 | XD_BA_TRANSFORM, XD_BA_TRANSFORM); |
fa590c22 MC |
1186 | |
1187 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, | |
dd67ec81 | 1188 | 0xFF, (end_page - start_page)); |
fa590c22 MC |
1189 | |
1190 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, | |
dd67ec81 | 1191 | 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT); |
fa590c22 | 1192 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
dd67ec81 | 1193 | XD_TRANSFER_END, XD_TRANSFER_END); |
fa590c22 MC |
1194 | |
1195 | retval = rtsx_send_cmd(chip, XD_CARD, 500); | |
1196 | if (retval < 0) { | |
1197 | rtsx_clear_xd_error(chip); | |
1198 | rtsx_read_register(chip, XD_DAT, ®); | |
1199 | if (reg & PROGRAM_ERROR) { | |
1200 | xd_mark_bad_block(chip, phy_blk); | |
1201 | xd_set_err_code(chip, XD_PRG_ERROR); | |
1202 | } else { | |
1203 | xd_set_err_code(chip, XD_TO_ERROR); | |
1204 | } | |
031366ea JP |
1205 | rtsx_trace(chip); |
1206 | return STATUS_FAIL; | |
fa590c22 MC |
1207 | } |
1208 | ||
1209 | return STATUS_SUCCESS; | |
1210 | } | |
1211 | ||
1212 | static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, | |
1213 | u8 start_page, u8 end_page) | |
1214 | { | |
14c42c79 | 1215 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1216 | u32 old_page, new_page; |
1217 | u8 i, reg = 0; | |
1218 | int retval; | |
1219 | ||
bf6c0d11 | 1220 | dev_dbg(rtsx_dev(chip), "Copy page from block 0x%x to block 0x%x\n", |
fa590c22 MC |
1221 | old_blk, new_blk); |
1222 | ||
031366ea JP |
1223 | if (start_page > end_page) { |
1224 | rtsx_trace(chip); | |
1225 | return STATUS_FAIL; | |
1226 | } | |
fa590c22 | 1227 | |
031366ea JP |
1228 | if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) { |
1229 | rtsx_trace(chip); | |
1230 | return STATUS_FAIL; | |
1231 | } | |
fa590c22 MC |
1232 | |
1233 | old_page = (old_blk << xd_card->block_shift) + start_page; | |
1234 | new_page = (new_blk << xd_card->block_shift) + start_page; | |
1235 | ||
1236 | XD_CLR_BAD_NEWBLK(xd_card); | |
1237 | ||
8ee775f9 JP |
1238 | retval = rtsx_write_register(chip, CARD_DATA_SOURCE, 0x01, |
1239 | PINGPONG_BUFFER); | |
1240 | if (retval) { | |
1241 | rtsx_trace(chip); | |
1242 | return retval; | |
1243 | } | |
fa590c22 MC |
1244 | |
1245 | for (i = start_page; i < end_page; i++) { | |
1246 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { | |
1247 | rtsx_clear_xd_error(chip); | |
1248 | xd_set_err_code(chip, XD_NO_CARD); | |
031366ea JP |
1249 | rtsx_trace(chip); |
1250 | return STATUS_FAIL; | |
fa590c22 MC |
1251 | } |
1252 | ||
1253 | rtsx_init_cmd(chip); | |
1254 | ||
1255 | xd_assign_phy_addr(chip, old_page, XD_RW_ADDR); | |
1256 | ||
1257 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); | |
1258 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, | |
dd67ec81 | 1259 | XD_AUTO_CHK_DATA_STATUS, 0); |
fa590c22 | 1260 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, |
dd67ec81 | 1261 | XD_TRANSFER_START | XD_READ_PAGES); |
fa590c22 | 1262 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
dd67ec81 | 1263 | XD_TRANSFER_END, XD_TRANSFER_END); |
fa590c22 MC |
1264 | |
1265 | retval = rtsx_send_cmd(chip, XD_CARD, 500); | |
1266 | if (retval < 0) { | |
1267 | rtsx_clear_xd_error(chip); | |
1268 | reg = 0; | |
1269 | rtsx_read_register(chip, XD_CTL, ®); | |
1270 | if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) { | |
1271 | wait_timeout(100); | |
1272 | ||
1273 | if (detect_card_cd(chip, | |
dd67ec81 | 1274 | XD_CARD) != STATUS_SUCCESS) { |
fa590c22 | 1275 | xd_set_err_code(chip, XD_NO_CARD); |
031366ea JP |
1276 | rtsx_trace(chip); |
1277 | return STATUS_FAIL; | |
fa590c22 MC |
1278 | } |
1279 | ||
1280 | if (((reg & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) == | |
d5549720 WP |
1281 | (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) || |
1282 | ((reg & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) == | |
fa590c22 MC |
1283 | (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) { |
1284 | rtsx_write_register(chip, | |
dd67ec81 WP |
1285 | XD_PAGE_STATUS, |
1286 | 0xFF, | |
1287 | XD_BPG); | |
fa590c22 | 1288 | rtsx_write_register(chip, |
dd67ec81 WP |
1289 | XD_BLOCK_STATUS, |
1290 | 0xFF, | |
1291 | XD_GBLK); | |
fa590c22 | 1292 | XD_SET_BAD_OLDBLK(xd_card); |
bf6c0d11 FF |
1293 | dev_dbg(rtsx_dev(chip), "old block 0x%x ecc error\n", |
1294 | old_blk); | |
fa590c22 MC |
1295 | } |
1296 | } else { | |
1297 | xd_set_err_code(chip, XD_TO_ERROR); | |
031366ea JP |
1298 | rtsx_trace(chip); |
1299 | return STATUS_FAIL; | |
fa590c22 MC |
1300 | } |
1301 | } | |
1302 | ||
1303 | if (XD_CHK_BAD_OLDBLK(xd_card)) | |
1304 | rtsx_clear_xd_error(chip); | |
1305 | ||
1306 | rtsx_init_cmd(chip); | |
1307 | ||
1308 | xd_assign_phy_addr(chip, new_page, XD_RW_ADDR); | |
1309 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); | |
1310 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, | |
1311 | XD_TRANSFER_START | XD_WRITE_PAGES); | |
1312 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, | |
dd67ec81 | 1313 | XD_TRANSFER_END, XD_TRANSFER_END); |
fa590c22 MC |
1314 | |
1315 | retval = rtsx_send_cmd(chip, XD_CARD, 300); | |
1316 | if (retval < 0) { | |
1317 | rtsx_clear_xd_error(chip); | |
1318 | reg = 0; | |
1319 | rtsx_read_register(chip, XD_DAT, ®); | |
1320 | if (reg & PROGRAM_ERROR) { | |
1321 | xd_mark_bad_block(chip, new_blk); | |
1322 | xd_set_err_code(chip, XD_PRG_ERROR); | |
1323 | XD_SET_BAD_NEWBLK(xd_card); | |
1324 | } else { | |
1325 | xd_set_err_code(chip, XD_TO_ERROR); | |
1326 | } | |
031366ea JP |
1327 | rtsx_trace(chip); |
1328 | return STATUS_FAIL; | |
fa590c22 MC |
1329 | } |
1330 | ||
1331 | old_page++; | |
1332 | new_page++; | |
1333 | } | |
1334 | ||
1335 | return STATUS_SUCCESS; | |
1336 | } | |
1337 | ||
1338 | static int xd_reset_cmd(struct rtsx_chip *chip) | |
1339 | { | |
1340 | int retval; | |
1341 | u8 *ptr; | |
1342 | ||
1343 | rtsx_init_cmd(chip); | |
1344 | ||
1345 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, | |
dd67ec81 | 1346 | 0xFF, XD_TRANSFER_START | XD_RESET); |
fa590c22 | 1347 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
dd67ec81 | 1348 | XD_TRANSFER_END, XD_TRANSFER_END); |
fa590c22 MC |
1349 | rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); |
1350 | rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); | |
1351 | ||
1352 | retval = rtsx_send_cmd(chip, XD_CARD, 100); | |
031366ea JP |
1353 | if (retval < 0) { |
1354 | rtsx_trace(chip); | |
1355 | return STATUS_FAIL; | |
1356 | } | |
fa590c22 MC |
1357 | |
1358 | ptr = rtsx_get_cmd_data(chip) + 1; | |
1359 | if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY)) | |
1360 | return STATUS_SUCCESS; | |
1361 | ||
031366ea JP |
1362 | rtsx_trace(chip); |
1363 | return STATUS_FAIL; | |
fa590c22 MC |
1364 | } |
1365 | ||
1366 | static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk) | |
1367 | { | |
14c42c79 | 1368 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1369 | u32 page_addr; |
1370 | u8 reg = 0, *ptr; | |
1371 | int i, retval; | |
1372 | ||
031366ea JP |
1373 | if (phy_blk == BLK_NOT_FOUND) { |
1374 | rtsx_trace(chip); | |
1375 | return STATUS_FAIL; | |
1376 | } | |
fa590c22 MC |
1377 | |
1378 | page_addr = phy_blk << xd_card->block_shift; | |
1379 | ||
1380 | for (i = 0; i < 3; i++) { | |
1381 | rtsx_init_cmd(chip); | |
1382 | ||
1383 | xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR); | |
1384 | ||
1385 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, | |
dd67ec81 | 1386 | XD_TRANSFER_START | XD_ERASE); |
fa590c22 | 1387 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
dd67ec81 | 1388 | XD_TRANSFER_END, XD_TRANSFER_END); |
fa590c22 MC |
1389 | rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); |
1390 | ||
1391 | retval = rtsx_send_cmd(chip, XD_CARD, 250); | |
1392 | if (retval < 0) { | |
1393 | rtsx_clear_xd_error(chip); | |
1394 | rtsx_read_register(chip, XD_DAT, ®); | |
1395 | if (reg & PROGRAM_ERROR) { | |
1396 | xd_mark_bad_block(chip, phy_blk); | |
1397 | xd_set_err_code(chip, XD_PRG_ERROR); | |
031366ea JP |
1398 | rtsx_trace(chip); |
1399 | return STATUS_FAIL; | |
fa590c22 | 1400 | } |
98f196af | 1401 | xd_set_err_code(chip, XD_ERASE_FAIL); |
fa590c22 | 1402 | retval = xd_reset_cmd(chip); |
031366ea JP |
1403 | if (retval != STATUS_SUCCESS) { |
1404 | rtsx_trace(chip); | |
1405 | return STATUS_FAIL; | |
1406 | } | |
fa590c22 MC |
1407 | continue; |
1408 | } | |
1409 | ||
1410 | ptr = rtsx_get_cmd_data(chip) + 1; | |
1411 | if (*ptr & PROGRAM_ERROR) { | |
1412 | xd_mark_bad_block(chip, phy_blk); | |
1413 | xd_set_err_code(chip, XD_PRG_ERROR); | |
031366ea JP |
1414 | rtsx_trace(chip); |
1415 | return STATUS_FAIL; | |
fa590c22 MC |
1416 | } |
1417 | ||
1418 | return STATUS_SUCCESS; | |
1419 | } | |
1420 | ||
1421 | xd_mark_bad_block(chip, phy_blk); | |
1422 | xd_set_err_code(chip, XD_ERASE_FAIL); | |
031366ea JP |
1423 | rtsx_trace(chip); |
1424 | return STATUS_FAIL; | |
fa590c22 MC |
1425 | } |
1426 | ||
fa590c22 MC |
1427 | static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) |
1428 | { | |
14c42c79 | 1429 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1430 | struct zone_entry *zone; |
1431 | int retval; | |
1432 | u32 start, end, i; | |
1433 | u16 max_logoff, cur_fst_page_logoff; | |
1434 | u16 cur_lst_page_logoff, ent_lst_page_logoff; | |
1435 | u8 redunt[11]; | |
1436 | ||
bf6c0d11 | 1437 | dev_dbg(rtsx_dev(chip), "xd_build_l2p_tbl: %d\n", zone_no); |
fa590c22 | 1438 | |
daaca111 | 1439 | if (!xd_card->zone) { |
fa590c22 MC |
1440 | retval = xd_init_l2p_tbl(chip); |
1441 | if (retval != STATUS_SUCCESS) | |
1442 | return retval; | |
1443 | } | |
1444 | ||
1445 | if (xd_card->zone[zone_no].build_flag) { | |
bf6c0d11 FF |
1446 | dev_dbg(rtsx_dev(chip), "l2p table of zone %d has been built\n", |
1447 | zone_no); | |
fa590c22 MC |
1448 | return STATUS_SUCCESS; |
1449 | } | |
1450 | ||
14c42c79 | 1451 | zone = &xd_card->zone[zone_no]; |
fa590c22 | 1452 | |
daaca111 | 1453 | if (!zone->l2p_table) { |
fa590c22 | 1454 | zone->l2p_table = vmalloc(2000); |
7586170c | 1455 | if (!zone->l2p_table) { |
031366ea | 1456 | rtsx_trace(chip); |
40eeb862 | 1457 | goto build_fail; |
031366ea | 1458 | } |
fa590c22 MC |
1459 | } |
1460 | memset((u8 *)(zone->l2p_table), 0xff, 2000); | |
1461 | ||
daaca111 | 1462 | if (!zone->free_table) { |
fa590c22 | 1463 | zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2); |
7586170c | 1464 | if (!zone->free_table) { |
031366ea | 1465 | rtsx_trace(chip); |
40eeb862 | 1466 | goto build_fail; |
031366ea | 1467 | } |
fa590c22 MC |
1468 | } |
1469 | memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2); | |
1470 | ||
1471 | if (zone_no == 0) { | |
1472 | if (xd_card->cis_block == 0xFFFF) | |
1473 | start = 0; | |
1474 | else | |
1475 | start = xd_card->cis_block + 1; | |
1476 | if (XD_CHK_4MB(xd_card)) { | |
1477 | end = 0x200; | |
1478 | max_logoff = 499; | |
1479 | } else { | |
1480 | end = 0x400; | |
1481 | max_logoff = 999; | |
1482 | } | |
1483 | } else { | |
1484 | start = (u32)(zone_no) << 10; | |
1485 | end = (u32)(zone_no + 1) << 10; | |
1486 | max_logoff = 999; | |
1487 | } | |
1488 | ||
bf6c0d11 FF |
1489 | dev_dbg(rtsx_dev(chip), "start block 0x%x, end block 0x%x\n", |
1490 | start, end); | |
fa590c22 | 1491 | |
6d2117f1 WP |
1492 | zone->set_index = 0; |
1493 | zone->get_index = 0; | |
fa590c22 MC |
1494 | zone->unused_blk_cnt = 0; |
1495 | ||
1496 | for (i = start; i < end; i++) { | |
1497 | u32 page_addr = i << xd_card->block_shift; | |
1498 | u32 phy_block; | |
1499 | ||
1500 | retval = xd_read_redundant(chip, page_addr, redunt, 11); | |
1501 | if (retval != STATUS_SUCCESS) | |
1502 | continue; | |
1503 | ||
1504 | if (redunt[BLOCK_STATUS] != 0xFF) { | |
bf6c0d11 | 1505 | dev_dbg(rtsx_dev(chip), "bad block\n"); |
fa590c22 MC |
1506 | continue; |
1507 | } | |
1508 | ||
1509 | if (xd_check_data_blank(redunt)) { | |
bf6c0d11 | 1510 | dev_dbg(rtsx_dev(chip), "blank block\n"); |
fa590c22 MC |
1511 | xd_set_unused_block(chip, i); |
1512 | continue; | |
1513 | } | |
1514 | ||
1515 | cur_fst_page_logoff = xd_load_log_block_addr(redunt); | |
1516 | if ((cur_fst_page_logoff == 0xFFFF) || | |
dd67ec81 | 1517 | (cur_fst_page_logoff > max_logoff)) { |
fa590c22 MC |
1518 | retval = xd_erase_block(chip, i); |
1519 | if (retval == STATUS_SUCCESS) | |
1520 | xd_set_unused_block(chip, i); | |
1521 | continue; | |
1522 | } | |
1523 | ||
1524 | if ((zone_no == 0) && (cur_fst_page_logoff == 0) && | |
dd67ec81 | 1525 | (redunt[PAGE_STATUS] != XD_GPG)) |
fa590c22 MC |
1526 | XD_SET_MBR_FAIL(xd_card); |
1527 | ||
1528 | if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) { | |
1529 | zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF); | |
1530 | continue; | |
1531 | } | |
1532 | ||
1533 | phy_block = zone->l2p_table[cur_fst_page_logoff] + | |
1534 | ((u32)((zone_no) << 10)); | |
1535 | ||
1536 | page_addr = ((i + 1) << xd_card->block_shift) - 1; | |
1537 | ||
1538 | retval = xd_read_redundant(chip, page_addr, redunt, 11); | |
1539 | if (retval != STATUS_SUCCESS) | |
1540 | continue; | |
1541 | ||
1542 | cur_lst_page_logoff = xd_load_log_block_addr(redunt); | |
1543 | if (cur_lst_page_logoff == cur_fst_page_logoff) { | |
1544 | int m; | |
1545 | ||
1546 | page_addr = ((phy_block + 1) << | |
1547 | xd_card->block_shift) - 1; | |
1548 | ||
1549 | for (m = 0; m < 3; m++) { | |
1550 | retval = xd_read_redundant(chip, page_addr, | |
dd67ec81 | 1551 | redunt, 11); |
fa590c22 MC |
1552 | if (retval == STATUS_SUCCESS) |
1553 | break; | |
1554 | } | |
1555 | ||
1556 | if (m == 3) { | |
1557 | zone->l2p_table[cur_fst_page_logoff] = | |
1558 | (u16)(i & 0x3FF); | |
1559 | retval = xd_erase_block(chip, phy_block); | |
1560 | if (retval == STATUS_SUCCESS) | |
1561 | xd_set_unused_block(chip, phy_block); | |
1562 | continue; | |
1563 | } | |
1564 | ||
1565 | ent_lst_page_logoff = xd_load_log_block_addr(redunt); | |
1566 | if (ent_lst_page_logoff != cur_fst_page_logoff) { | |
1567 | zone->l2p_table[cur_fst_page_logoff] = | |
1568 | (u16)(i & 0x3FF); | |
1569 | retval = xd_erase_block(chip, phy_block); | |
1570 | if (retval == STATUS_SUCCESS) | |
1571 | xd_set_unused_block(chip, phy_block); | |
1572 | continue; | |
1573 | } else { | |
1574 | retval = xd_erase_block(chip, i); | |
1575 | if (retval == STATUS_SUCCESS) | |
1576 | xd_set_unused_block(chip, i); | |
1577 | } | |
1578 | } else { | |
1579 | retval = xd_erase_block(chip, i); | |
1580 | if (retval == STATUS_SUCCESS) | |
1581 | xd_set_unused_block(chip, i); | |
1582 | } | |
1583 | } | |
1584 | ||
1585 | if (XD_CHK_4MB(xd_card)) | |
1586 | end = 500; | |
1587 | else | |
1588 | end = 1000; | |
1589 | ||
1590 | i = 0; | |
1591 | for (start = 0; start < end; start++) { | |
1592 | if (zone->l2p_table[start] == 0xFFFF) | |
1593 | i++; | |
1594 | } | |
1595 | ||
bf6c0d11 FF |
1596 | dev_dbg(rtsx_dev(chip), "Block count %d, invalid L2P entry %d\n", |
1597 | end, i); | |
1598 | dev_dbg(rtsx_dev(chip), "Total unused block: %d\n", | |
1599 | zone->unused_blk_cnt); | |
fa590c22 MC |
1600 | |
1601 | if ((zone->unused_blk_cnt - i) < 1) | |
1602 | chip->card_wp |= XD_CARD; | |
1603 | ||
1604 | zone->build_flag = 1; | |
1605 | ||
1606 | return STATUS_SUCCESS; | |
1607 | ||
40eeb862 | 1608 | build_fail: |
b242d05f BS |
1609 | vfree(zone->l2p_table); |
1610 | zone->l2p_table = NULL; | |
1611 | vfree(zone->free_table); | |
1612 | zone->free_table = NULL; | |
fa590c22 MC |
1613 | |
1614 | return STATUS_FAIL; | |
1615 | } | |
1616 | ||
1617 | static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd) | |
1618 | { | |
1619 | int retval; | |
1620 | ||
1621 | rtsx_init_cmd(chip); | |
1622 | ||
1623 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd); | |
1624 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, | |
dd67ec81 | 1625 | XD_TRANSFER_START | XD_SET_CMD); |
fa590c22 | 1626 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
dd67ec81 | 1627 | XD_TRANSFER_END, XD_TRANSFER_END); |
fa590c22 MC |
1628 | |
1629 | retval = rtsx_send_cmd(chip, XD_CARD, 200); | |
031366ea JP |
1630 | if (retval < 0) { |
1631 | rtsx_trace(chip); | |
1632 | return STATUS_FAIL; | |
1633 | } | |
fa590c22 MC |
1634 | |
1635 | return STATUS_SUCCESS; | |
1636 | } | |
1637 | ||
1638 | static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk, | |
dd67ec81 WP |
1639 | u32 log_blk, u8 start_page, u8 end_page, |
1640 | u8 *buf, unsigned int *index, | |
1641 | unsigned int *offset) | |
fa590c22 | 1642 | { |
14c42c79 | 1643 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1644 | u32 page_addr, new_blk; |
1645 | u16 log_off; | |
1646 | u8 reg_val, page_cnt; | |
1647 | int zone_no, retval, i; | |
1648 | ||
e453eecb | 1649 | if (start_page > end_page) |
40eeb862 | 1650 | goto status_fail; |
fa590c22 MC |
1651 | |
1652 | page_cnt = end_page - start_page; | |
1653 | zone_no = (int)(log_blk / 1000); | |
1654 | log_off = (u16)(log_blk % 1000); | |
1655 | ||
1656 | if ((phy_blk & 0x3FF) == 0x3FF) { | |
1657 | for (i = 0; i < 256; i++) { | |
1658 | page_addr = ((u32)i) << xd_card->block_shift; | |
1659 | ||
1660 | retval = xd_read_redundant(chip, page_addr, NULL, 0); | |
1661 | if (retval == STATUS_SUCCESS) | |
1662 | break; | |
1663 | ||
1664 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { | |
1665 | xd_set_err_code(chip, XD_NO_CARD); | |
40eeb862 | 1666 | goto status_fail; |
fa590c22 MC |
1667 | } |
1668 | } | |
1669 | } | |
1670 | ||
1671 | page_addr = (phy_blk << xd_card->block_shift) + start_page; | |
1672 | ||
1673 | rtsx_init_cmd(chip); | |
1674 | ||
1675 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); | |
1676 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE); | |
1677 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); | |
1678 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt); | |
1679 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, | |
dd67ec81 | 1680 | XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS); |
fa590c22 MC |
1681 | |
1682 | trans_dma_enable(chip->srb->sc_data_direction, chip, | |
dd67ec81 | 1683 | page_cnt * 512, DMA_512); |
fa590c22 MC |
1684 | |
1685 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, | |
dd67ec81 | 1686 | XD_TRANSFER_START | XD_READ_PAGES); |
fa590c22 | 1687 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
dd67ec81 WP |
1688 | XD_TRANSFER_END | XD_PPB_EMPTY, |
1689 | XD_TRANSFER_END | XD_PPB_EMPTY); | |
fa590c22 MC |
1690 | |
1691 | rtsx_send_cmd_no_wait(chip); | |
1692 | ||
1693 | retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, | |
dd67ec81 WP |
1694 | scsi_sg_count(chip->srb), |
1695 | index, offset, DMA_FROM_DEVICE, | |
1696 | chip->xd_timeout); | |
fa590c22 MC |
1697 | if (retval < 0) { |
1698 | rtsx_clear_xd_error(chip); | |
1699 | ||
1700 | if (retval == -ETIMEDOUT) { | |
1701 | xd_set_err_code(chip, XD_TO_ERROR); | |
40eeb862 | 1702 | goto status_fail; |
fa590c22 | 1703 | } else { |
031366ea | 1704 | rtsx_trace(chip); |
40eeb862 | 1705 | goto fail; |
fa590c22 MC |
1706 | } |
1707 | } | |
1708 | ||
1709 | return STATUS_SUCCESS; | |
1710 | ||
40eeb862 | 1711 | fail: |
8ee775f9 JP |
1712 | retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®_val); |
1713 | if (retval) { | |
1714 | rtsx_trace(chip); | |
1715 | return retval; | |
1716 | } | |
fa590c22 MC |
1717 | |
1718 | if (reg_val != XD_GPG) | |
1719 | xd_set_err_code(chip, XD_PRG_ERROR); | |
1720 | ||
8ee775f9 JP |
1721 | retval = rtsx_read_register(chip, XD_CTL, ®_val); |
1722 | if (retval) { | |
1723 | rtsx_trace(chip); | |
1724 | return retval; | |
1725 | } | |
fa590c22 | 1726 | |
d5549720 WP |
1727 | if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) == |
1728 | (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) || | |
1729 | ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) == | |
1730 | (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) { | |
fa590c22 MC |
1731 | wait_timeout(100); |
1732 | ||
1733 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { | |
1734 | xd_set_err_code(chip, XD_NO_CARD); | |
40eeb862 | 1735 | goto status_fail; |
fa590c22 MC |
1736 | } |
1737 | ||
1738 | xd_set_err_code(chip, XD_ECC_ERROR); | |
1739 | ||
1740 | new_blk = xd_get_unused_block(chip, zone_no); | |
1741 | if (new_blk == NO_NEW_BLK) { | |
1742 | XD_CLR_BAD_OLDBLK(xd_card); | |
40eeb862 | 1743 | goto status_fail; |
fa590c22 MC |
1744 | } |
1745 | ||
1746 | retval = xd_copy_page(chip, phy_blk, new_blk, 0, | |
dd67ec81 | 1747 | xd_card->page_off + 1); |
fa590c22 MC |
1748 | if (retval != STATUS_SUCCESS) { |
1749 | if (!XD_CHK_BAD_NEWBLK(xd_card)) { | |
1750 | retval = xd_erase_block(chip, new_blk); | |
1751 | if (retval == STATUS_SUCCESS) | |
1752 | xd_set_unused_block(chip, new_blk); | |
1753 | } else { | |
1754 | XD_CLR_BAD_NEWBLK(xd_card); | |
1755 | } | |
1756 | XD_CLR_BAD_OLDBLK(xd_card); | |
40eeb862 | 1757 | goto status_fail; |
fa590c22 MC |
1758 | } |
1759 | xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); | |
1760 | xd_erase_block(chip, phy_blk); | |
1761 | xd_mark_bad_block(chip, phy_blk); | |
1762 | XD_CLR_BAD_OLDBLK(xd_card); | |
1763 | } | |
1764 | ||
40eeb862 | 1765 | status_fail: |
031366ea JP |
1766 | rtsx_trace(chip); |
1767 | return STATUS_FAIL; | |
fa590c22 MC |
1768 | } |
1769 | ||
1770 | static int xd_finish_write(struct rtsx_chip *chip, | |
dd67ec81 | 1771 | u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off) |
fa590c22 | 1772 | { |
14c42c79 | 1773 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1774 | int retval, zone_no; |
1775 | u16 log_off; | |
1776 | ||
bf6c0d11 FF |
1777 | dev_dbg(rtsx_dev(chip), "xd_finish_write, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", |
1778 | old_blk, new_blk, log_blk); | |
fa590c22 | 1779 | |
031366ea JP |
1780 | if (page_off > xd_card->page_off) { |
1781 | rtsx_trace(chip); | |
1782 | return STATUS_FAIL; | |
1783 | } | |
fa590c22 MC |
1784 | |
1785 | zone_no = (int)(log_blk / 1000); | |
1786 | log_off = (u16)(log_blk % 1000); | |
1787 | ||
1788 | if (old_blk == BLK_NOT_FOUND) { | |
1789 | retval = xd_init_page(chip, new_blk, log_off, | |
dd67ec81 | 1790 | page_off, xd_card->page_off + 1); |
fa590c22 MC |
1791 | if (retval != STATUS_SUCCESS) { |
1792 | retval = xd_erase_block(chip, new_blk); | |
1793 | if (retval == STATUS_SUCCESS) | |
1794 | xd_set_unused_block(chip, new_blk); | |
031366ea JP |
1795 | rtsx_trace(chip); |
1796 | return STATUS_FAIL; | |
fa590c22 MC |
1797 | } |
1798 | } else { | |
1799 | retval = xd_copy_page(chip, old_blk, new_blk, | |
dd67ec81 | 1800 | page_off, xd_card->page_off + 1); |
fa590c22 MC |
1801 | if (retval != STATUS_SUCCESS) { |
1802 | if (!XD_CHK_BAD_NEWBLK(xd_card)) { | |
1803 | retval = xd_erase_block(chip, new_blk); | |
1804 | if (retval == STATUS_SUCCESS) | |
1805 | xd_set_unused_block(chip, new_blk); | |
1806 | } | |
1807 | XD_CLR_BAD_NEWBLK(xd_card); | |
031366ea JP |
1808 | rtsx_trace(chip); |
1809 | return STATUS_FAIL; | |
fa590c22 MC |
1810 | } |
1811 | ||
1812 | retval = xd_erase_block(chip, old_blk); | |
1813 | if (retval == STATUS_SUCCESS) { | |
1814 | if (XD_CHK_BAD_OLDBLK(xd_card)) { | |
1815 | xd_mark_bad_block(chip, old_blk); | |
1816 | XD_CLR_BAD_OLDBLK(xd_card); | |
1817 | } else { | |
1818 | xd_set_unused_block(chip, old_blk); | |
1819 | } | |
1820 | } else { | |
1821 | xd_set_err_code(chip, XD_NO_ERROR); | |
1822 | XD_CLR_BAD_OLDBLK(xd_card); | |
1823 | } | |
1824 | } | |
1825 | ||
1826 | xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); | |
1827 | ||
1828 | return STATUS_SUCCESS; | |
1829 | } | |
1830 | ||
1831 | static int xd_prepare_write(struct rtsx_chip *chip, | |
dd67ec81 | 1832 | u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off) |
fa590c22 MC |
1833 | { |
1834 | int retval; | |
1835 | ||
bf6c0d11 | 1836 | dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n", |
fa590c22 MC |
1837 | __func__, old_blk, new_blk, log_blk, (int)page_off); |
1838 | ||
1839 | if (page_off) { | |
1840 | retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off); | |
031366ea JP |
1841 | if (retval != STATUS_SUCCESS) { |
1842 | rtsx_trace(chip); | |
1843 | return STATUS_FAIL; | |
1844 | } | |
fa590c22 MC |
1845 | } |
1846 | ||
1847 | return STATUS_SUCCESS; | |
1848 | } | |
1849 | ||
fa590c22 | 1850 | static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk, |
dd67ec81 WP |
1851 | u32 new_blk, u32 log_blk, u8 start_page, |
1852 | u8 end_page, u8 *buf, unsigned int *index, | |
1853 | unsigned int *offset) | |
fa590c22 | 1854 | { |
14c42c79 | 1855 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1856 | u32 page_addr; |
1857 | int zone_no, retval; | |
1858 | u16 log_off; | |
1859 | u8 page_cnt, reg_val; | |
1860 | ||
bf6c0d11 FF |
1861 | dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", |
1862 | __func__, old_blk, new_blk, log_blk); | |
fa590c22 | 1863 | |
e453eecb | 1864 | if (start_page > end_page) |
40eeb862 | 1865 | goto status_fail; |
fa590c22 MC |
1866 | |
1867 | page_cnt = end_page - start_page; | |
1868 | zone_no = (int)(log_blk / 1000); | |
1869 | log_off = (u16)(log_blk % 1000); | |
1870 | ||
1871 | page_addr = (new_blk << xd_card->block_shift) + start_page; | |
1872 | ||
1873 | retval = xd_send_cmd(chip, READ1_1); | |
e453eecb | 1874 | if (retval != STATUS_SUCCESS) |
40eeb862 | 1875 | goto status_fail; |
fa590c22 MC |
1876 | |
1877 | rtsx_init_cmd(chip); | |
1878 | ||
1879 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, | |
dd67ec81 | 1880 | 0xFF, (u8)(log_off >> 8)); |
fa590c22 MC |
1881 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off); |
1882 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK); | |
1883 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG); | |
1884 | ||
1885 | xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); | |
1886 | ||
1887 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM, | |
dd67ec81 | 1888 | XD_BA_TRANSFORM); |
fa590c22 MC |
1889 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt); |
1890 | rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); | |
1891 | ||
1892 | trans_dma_enable(chip->srb->sc_data_direction, chip, | |
dd67ec81 | 1893 | page_cnt * 512, DMA_512); |
fa590c22 MC |
1894 | |
1895 | rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, | |
dd67ec81 | 1896 | 0xFF, XD_TRANSFER_START | XD_WRITE_PAGES); |
fa590c22 | 1897 | rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, |
dd67ec81 | 1898 | XD_TRANSFER_END, XD_TRANSFER_END); |
fa590c22 MC |
1899 | |
1900 | rtsx_send_cmd_no_wait(chip); | |
1901 | ||
1902 | retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, | |
dd67ec81 WP |
1903 | scsi_sg_count(chip->srb), |
1904 | index, offset, DMA_TO_DEVICE, chip->xd_timeout); | |
fa590c22 MC |
1905 | if (retval < 0) { |
1906 | rtsx_clear_xd_error(chip); | |
1907 | ||
1908 | if (retval == -ETIMEDOUT) { | |
1909 | xd_set_err_code(chip, XD_TO_ERROR); | |
40eeb862 | 1910 | goto status_fail; |
fa590c22 | 1911 | } else { |
031366ea | 1912 | rtsx_trace(chip); |
40eeb862 | 1913 | goto fail; |
fa590c22 MC |
1914 | } |
1915 | } | |
1916 | ||
1917 | if (end_page == (xd_card->page_off + 1)) { | |
1918 | xd_card->delay_write.delay_write_flag = 0; | |
1919 | ||
1920 | if (old_blk != BLK_NOT_FOUND) { | |
1921 | retval = xd_erase_block(chip, old_blk); | |
1922 | if (retval == STATUS_SUCCESS) { | |
1923 | if (XD_CHK_BAD_OLDBLK(xd_card)) { | |
1924 | xd_mark_bad_block(chip, old_blk); | |
1925 | XD_CLR_BAD_OLDBLK(xd_card); | |
1926 | } else { | |
1927 | xd_set_unused_block(chip, old_blk); | |
1928 | } | |
1929 | } else { | |
1930 | xd_set_err_code(chip, XD_NO_ERROR); | |
1931 | XD_CLR_BAD_OLDBLK(xd_card); | |
1932 | } | |
1933 | } | |
1934 | xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); | |
1935 | } | |
1936 | ||
1937 | return STATUS_SUCCESS; | |
1938 | ||
40eeb862 | 1939 | fail: |
8ee775f9 JP |
1940 | retval = rtsx_read_register(chip, XD_DAT, ®_val); |
1941 | if (retval) { | |
1942 | rtsx_trace(chip); | |
1943 | return retval; | |
1944 | } | |
fa590c22 MC |
1945 | if (reg_val & PROGRAM_ERROR) { |
1946 | xd_set_err_code(chip, XD_PRG_ERROR); | |
1947 | xd_mark_bad_block(chip, new_blk); | |
1948 | } | |
1949 | ||
40eeb862 | 1950 | status_fail: |
031366ea JP |
1951 | rtsx_trace(chip); |
1952 | return STATUS_FAIL; | |
fa590c22 MC |
1953 | } |
1954 | ||
1955 | #ifdef XD_DELAY_WRITE | |
1956 | int xd_delay_write(struct rtsx_chip *chip) | |
1957 | { | |
14c42c79 WP |
1958 | struct xd_info *xd_card = &chip->xd_card; |
1959 | struct xd_delay_write_tag *delay_write = &xd_card->delay_write; | |
fa590c22 MC |
1960 | int retval; |
1961 | ||
1962 | if (delay_write->delay_write_flag) { | |
bf6c0d11 | 1963 | dev_dbg(rtsx_dev(chip), "xd_delay_write\n"); |
fa590c22 | 1964 | retval = xd_switch_clock(chip); |
031366ea JP |
1965 | if (retval != STATUS_SUCCESS) { |
1966 | rtsx_trace(chip); | |
1967 | return STATUS_FAIL; | |
1968 | } | |
fa590c22 MC |
1969 | |
1970 | delay_write->delay_write_flag = 0; | |
1971 | retval = xd_finish_write(chip, | |
dd67ec81 WP |
1972 | delay_write->old_phyblock, |
1973 | delay_write->new_phyblock, | |
1974 | delay_write->logblock, | |
1975 | delay_write->pageoff); | |
031366ea JP |
1976 | if (retval != STATUS_SUCCESS) { |
1977 | rtsx_trace(chip); | |
1978 | return STATUS_FAIL; | |
1979 | } | |
fa590c22 MC |
1980 | } |
1981 | ||
1982 | return STATUS_SUCCESS; | |
1983 | } | |
1984 | #endif | |
1985 | ||
1986 | int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, | |
dd67ec81 | 1987 | u32 start_sector, u16 sector_cnt) |
fa590c22 | 1988 | { |
14c42c79 | 1989 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
1990 | unsigned int lun = SCSI_LUN(srb); |
1991 | #ifdef XD_DELAY_WRITE | |
14c42c79 | 1992 | struct xd_delay_write_tag *delay_write = &xd_card->delay_write; |
fa590c22 MC |
1993 | #endif |
1994 | int retval, zone_no; | |
1995 | unsigned int index = 0, offset = 0; | |
1996 | u32 log_blk, old_blk = 0, new_blk = 0; | |
1997 | u16 log_off, total_sec_cnt = sector_cnt; | |
1998 | u8 start_page, end_page = 0, page_cnt; | |
1999 | u8 *ptr; | |
2000 | ||
2001 | xd_set_err_code(chip, XD_NO_ERROR); | |
2002 | ||
2003 | xd_card->cleanup_counter = 0; | |
2004 | ||
bf6c0d11 FF |
2005 | dev_dbg(rtsx_dev(chip), "xd_rw: scsi_sg_count = %d\n", |
2006 | scsi_sg_count(srb)); | |
fa590c22 MC |
2007 | |
2008 | ptr = (u8 *)scsi_sglist(srb); | |
2009 | ||
2010 | retval = xd_switch_clock(chip); | |
031366ea JP |
2011 | if (retval != STATUS_SUCCESS) { |
2012 | rtsx_trace(chip); | |
2013 | return STATUS_FAIL; | |
2014 | } | |
fa590c22 | 2015 | |
fa590c22 MC |
2016 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { |
2017 | chip->card_fail |= XD_CARD; | |
2018 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); | |
031366ea JP |
2019 | rtsx_trace(chip); |
2020 | return STATUS_FAIL; | |
fa590c22 MC |
2021 | } |
2022 | ||
2023 | log_blk = start_sector >> xd_card->block_shift; | |
2024 | start_page = (u8)start_sector & xd_card->page_off; | |
2025 | zone_no = (int)(log_blk / 1000); | |
2026 | log_off = (u16)(log_blk % 1000); | |
2027 | ||
2028 | if (xd_card->zone[zone_no].build_flag == 0) { | |
2029 | retval = xd_build_l2p_tbl(chip, zone_no); | |
2030 | if (retval != STATUS_SUCCESS) { | |
2031 | chip->card_fail |= XD_CARD; | |
2032 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); | |
031366ea JP |
2033 | rtsx_trace(chip); |
2034 | return STATUS_FAIL; | |
fa590c22 MC |
2035 | } |
2036 | } | |
2037 | ||
2038 | if (srb->sc_data_direction == DMA_TO_DEVICE) { | |
2039 | #ifdef XD_DELAY_WRITE | |
2040 | if (delay_write->delay_write_flag && | |
dd67ec81 WP |
2041 | (delay_write->logblock == log_blk) && |
2042 | (start_page > delay_write->pageoff)) { | |
fa590c22 MC |
2043 | delay_write->delay_write_flag = 0; |
2044 | if (delay_write->old_phyblock != BLK_NOT_FOUND) { | |
2045 | retval = xd_copy_page(chip, | |
dd67ec81 WP |
2046 | delay_write->old_phyblock, |
2047 | delay_write->new_phyblock, | |
2048 | delay_write->pageoff, | |
2049 | start_page); | |
fa590c22 MC |
2050 | if (retval != STATUS_SUCCESS) { |
2051 | set_sense_type(chip, lun, | |
dd67ec81 | 2052 | SENSE_TYPE_MEDIA_WRITE_ERR); |
031366ea JP |
2053 | rtsx_trace(chip); |
2054 | return STATUS_FAIL; | |
fa590c22 MC |
2055 | } |
2056 | } | |
2057 | old_blk = delay_write->old_phyblock; | |
2058 | new_blk = delay_write->new_phyblock; | |
2059 | } else if (delay_write->delay_write_flag && | |
2060 | (delay_write->logblock == log_blk) && | |
2061 | (start_page == delay_write->pageoff)) { | |
2062 | delay_write->delay_write_flag = 0; | |
2063 | old_blk = delay_write->old_phyblock; | |
2064 | new_blk = delay_write->new_phyblock; | |
2065 | } else { | |
2066 | retval = xd_delay_write(chip); | |
2067 | if (retval != STATUS_SUCCESS) { | |
2068 | set_sense_type(chip, lun, | |
dd67ec81 | 2069 | SENSE_TYPE_MEDIA_WRITE_ERR); |
031366ea JP |
2070 | rtsx_trace(chip); |
2071 | return STATUS_FAIL; | |
fa590c22 MC |
2072 | } |
2073 | #endif | |
2074 | old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); | |
2075 | new_blk = xd_get_unused_block(chip, zone_no); | |
2076 | if ((old_blk == BLK_NOT_FOUND) || | |
dd67ec81 | 2077 | (new_blk == BLK_NOT_FOUND)) { |
fa590c22 | 2078 | set_sense_type(chip, lun, |
dd67ec81 | 2079 | SENSE_TYPE_MEDIA_WRITE_ERR); |
031366ea JP |
2080 | rtsx_trace(chip); |
2081 | return STATUS_FAIL; | |
fa590c22 MC |
2082 | } |
2083 | ||
2084 | retval = xd_prepare_write(chip, old_blk, new_blk, | |
dd67ec81 | 2085 | log_blk, start_page); |
fa590c22 MC |
2086 | if (retval != STATUS_SUCCESS) { |
2087 | if (detect_card_cd(chip, XD_CARD) != | |
2088 | STATUS_SUCCESS) { | |
2089 | set_sense_type(chip, lun, | |
dd67ec81 | 2090 | SENSE_TYPE_MEDIA_NOT_PRESENT); |
031366ea JP |
2091 | rtsx_trace(chip); |
2092 | return STATUS_FAIL; | |
fa590c22 MC |
2093 | } |
2094 | set_sense_type(chip, lun, | |
dd67ec81 | 2095 | SENSE_TYPE_MEDIA_WRITE_ERR); |
031366ea JP |
2096 | rtsx_trace(chip); |
2097 | return STATUS_FAIL; | |
fa590c22 MC |
2098 | } |
2099 | #ifdef XD_DELAY_WRITE | |
2100 | } | |
2101 | #endif | |
2102 | } else { | |
2103 | #ifdef XD_DELAY_WRITE | |
2104 | retval = xd_delay_write(chip); | |
2105 | if (retval != STATUS_SUCCESS) { | |
2106 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { | |
2107 | set_sense_type(chip, lun, | |
dd67ec81 | 2108 | SENSE_TYPE_MEDIA_NOT_PRESENT); |
031366ea JP |
2109 | rtsx_trace(chip); |
2110 | return STATUS_FAIL; | |
fa590c22 MC |
2111 | } |
2112 | set_sense_type(chip, lun, | |
dd67ec81 | 2113 | SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); |
031366ea JP |
2114 | rtsx_trace(chip); |
2115 | return STATUS_FAIL; | |
fa590c22 MC |
2116 | } |
2117 | #endif | |
2118 | ||
2119 | old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); | |
2120 | if (old_blk == BLK_NOT_FOUND) { | |
2121 | set_sense_type(chip, lun, | |
dd67ec81 | 2122 | SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); |
031366ea JP |
2123 | rtsx_trace(chip); |
2124 | return STATUS_FAIL; | |
fa590c22 MC |
2125 | } |
2126 | } | |
2127 | ||
bf6c0d11 | 2128 | dev_dbg(rtsx_dev(chip), "old_blk = 0x%x\n", old_blk); |
fa590c22 MC |
2129 | |
2130 | while (total_sec_cnt) { | |
2131 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { | |
2132 | chip->card_fail |= XD_CARD; | |
2133 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); | |
031366ea JP |
2134 | rtsx_trace(chip); |
2135 | return STATUS_FAIL; | |
fa590c22 MC |
2136 | } |
2137 | ||
2138 | if ((start_page + total_sec_cnt) > (xd_card->page_off + 1)) | |
2139 | end_page = xd_card->page_off + 1; | |
2140 | else | |
2141 | end_page = start_page + (u8)total_sec_cnt; | |
2142 | ||
2143 | page_cnt = end_page - start_page; | |
2144 | if (srb->sc_data_direction == DMA_FROM_DEVICE) { | |
2145 | retval = xd_read_multiple_pages(chip, old_blk, log_blk, | |
dd67ec81 WP |
2146 | start_page, end_page, |
2147 | ptr, &index, &offset); | |
fa590c22 MC |
2148 | if (retval != STATUS_SUCCESS) { |
2149 | set_sense_type(chip, lun, | |
dd67ec81 | 2150 | SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); |
031366ea JP |
2151 | rtsx_trace(chip); |
2152 | return STATUS_FAIL; | |
fa590c22 MC |
2153 | } |
2154 | } else { | |
2155 | retval = xd_write_multiple_pages(chip, old_blk, | |
dd67ec81 WP |
2156 | new_blk, log_blk, |
2157 | start_page, end_page, | |
2158 | ptr, &index, &offset); | |
fa590c22 MC |
2159 | if (retval != STATUS_SUCCESS) { |
2160 | set_sense_type(chip, lun, | |
dd67ec81 | 2161 | SENSE_TYPE_MEDIA_WRITE_ERR); |
031366ea JP |
2162 | rtsx_trace(chip); |
2163 | return STATUS_FAIL; | |
fa590c22 MC |
2164 | } |
2165 | } | |
2166 | ||
2167 | total_sec_cnt -= page_cnt; | |
2168 | if (scsi_sg_count(srb) == 0) | |
2169 | ptr += page_cnt * 512; | |
2170 | ||
2171 | if (total_sec_cnt == 0) | |
2172 | break; | |
2173 | ||
2174 | log_blk++; | |
2175 | zone_no = (int)(log_blk / 1000); | |
2176 | log_off = (u16)(log_blk % 1000); | |
2177 | ||
2178 | if (xd_card->zone[zone_no].build_flag == 0) { | |
2179 | retval = xd_build_l2p_tbl(chip, zone_no); | |
2180 | if (retval != STATUS_SUCCESS) { | |
2181 | chip->card_fail |= XD_CARD; | |
2182 | set_sense_type(chip, lun, | |
dd67ec81 | 2183 | SENSE_TYPE_MEDIA_NOT_PRESENT); |
031366ea JP |
2184 | rtsx_trace(chip); |
2185 | return STATUS_FAIL; | |
fa590c22 MC |
2186 | } |
2187 | } | |
2188 | ||
2189 | old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); | |
2190 | if (old_blk == BLK_NOT_FOUND) { | |
2191 | if (srb->sc_data_direction == DMA_FROM_DEVICE) | |
2192 | set_sense_type(chip, lun, | |
dd67ec81 | 2193 | SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); |
fa590c22 MC |
2194 | else |
2195 | set_sense_type(chip, lun, | |
dd67ec81 | 2196 | SENSE_TYPE_MEDIA_WRITE_ERR); |
fa590c22 | 2197 | |
031366ea JP |
2198 | rtsx_trace(chip); |
2199 | return STATUS_FAIL; | |
fa590c22 MC |
2200 | } |
2201 | ||
2202 | if (srb->sc_data_direction == DMA_TO_DEVICE) { | |
2203 | new_blk = xd_get_unused_block(chip, zone_no); | |
2204 | if (new_blk == BLK_NOT_FOUND) { | |
2205 | set_sense_type(chip, lun, | |
dd67ec81 | 2206 | SENSE_TYPE_MEDIA_WRITE_ERR); |
031366ea JP |
2207 | rtsx_trace(chip); |
2208 | return STATUS_FAIL; | |
fa590c22 MC |
2209 | } |
2210 | } | |
2211 | ||
2212 | start_page = 0; | |
2213 | } | |
2214 | ||
2215 | if ((srb->sc_data_direction == DMA_TO_DEVICE) && | |
dd67ec81 | 2216 | (end_page != (xd_card->page_off + 1))) { |
fa590c22 MC |
2217 | #ifdef XD_DELAY_WRITE |
2218 | delay_write->delay_write_flag = 1; | |
2219 | delay_write->old_phyblock = old_blk; | |
2220 | delay_write->new_phyblock = new_blk; | |
2221 | delay_write->logblock = log_blk; | |
2222 | delay_write->pageoff = end_page; | |
2223 | #else | |
2224 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { | |
2225 | chip->card_fail |= XD_CARD; | |
2226 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); | |
031366ea JP |
2227 | rtsx_trace(chip); |
2228 | return STATUS_FAIL; | |
fa590c22 MC |
2229 | } |
2230 | ||
2231 | retval = xd_finish_write(chip, old_blk, new_blk, | |
dd67ec81 | 2232 | log_blk, end_page); |
fa590c22 MC |
2233 | if (retval != STATUS_SUCCESS) { |
2234 | if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { | |
2235 | set_sense_type(chip, lun, | |
dd67ec81 | 2236 | SENSE_TYPE_MEDIA_NOT_PRESENT); |
031366ea JP |
2237 | rtsx_trace(chip); |
2238 | return STATUS_FAIL; | |
fa590c22 MC |
2239 | } |
2240 | set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); | |
031366ea JP |
2241 | rtsx_trace(chip); |
2242 | return STATUS_FAIL; | |
fa590c22 MC |
2243 | } |
2244 | #endif | |
2245 | } | |
2246 | ||
2247 | scsi_set_resid(srb, 0); | |
2248 | ||
2249 | return STATUS_SUCCESS; | |
2250 | } | |
2251 | ||
2252 | void xd_free_l2p_tbl(struct rtsx_chip *chip) | |
2253 | { | |
14c42c79 | 2254 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
2255 | int i = 0; |
2256 | ||
daaca111 | 2257 | if (xd_card->zone) { |
fa590c22 | 2258 | for (i = 0; i < xd_card->zone_cnt; i++) { |
b242d05f BS |
2259 | vfree(xd_card->zone[i].l2p_table); |
2260 | xd_card->zone[i].l2p_table = NULL; | |
2261 | vfree(xd_card->zone[i].free_table); | |
2262 | xd_card->zone[i].free_table = NULL; | |
fa590c22 MC |
2263 | } |
2264 | vfree(xd_card->zone); | |
2265 | xd_card->zone = NULL; | |
2266 | } | |
2267 | } | |
2268 | ||
2269 | void xd_cleanup_work(struct rtsx_chip *chip) | |
2270 | { | |
2271 | #ifdef XD_DELAY_WRITE | |
14c42c79 | 2272 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
2273 | |
2274 | if (xd_card->delay_write.delay_write_flag) { | |
bf6c0d11 | 2275 | dev_dbg(rtsx_dev(chip), "xD: delay write\n"); |
fa590c22 MC |
2276 | xd_delay_write(chip); |
2277 | xd_card->cleanup_counter = 0; | |
2278 | } | |
2279 | #endif | |
2280 | } | |
2281 | ||
2282 | int xd_power_off_card3v3(struct rtsx_chip *chip) | |
2283 | { | |
2284 | int retval; | |
2285 | ||
2286 | retval = disable_card_clock(chip, XD_CARD); | |
031366ea JP |
2287 | if (retval != STATUS_SUCCESS) { |
2288 | rtsx_trace(chip); | |
2289 | return STATUS_FAIL; | |
2290 | } | |
fa590c22 | 2291 | |
8ee775f9 JP |
2292 | retval = rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); |
2293 | if (retval) { | |
2294 | rtsx_trace(chip); | |
2295 | return retval; | |
2296 | } | |
fa590c22 MC |
2297 | |
2298 | if (!chip->ft2_fast_mode) { | |
2299 | retval = card_power_off(chip, XD_CARD); | |
031366ea JP |
2300 | if (retval != STATUS_SUCCESS) { |
2301 | rtsx_trace(chip); | |
2302 | return STATUS_FAIL; | |
2303 | } | |
fa590c22 MC |
2304 | |
2305 | wait_timeout(50); | |
2306 | } | |
2307 | ||
2308 | if (chip->asic_code) { | |
2309 | retval = xd_pull_ctl_disable(chip); | |
031366ea JP |
2310 | if (retval != STATUS_SUCCESS) { |
2311 | rtsx_trace(chip); | |
2312 | return STATUS_FAIL; | |
2313 | } | |
fa590c22 | 2314 | } else { |
8ee775f9 JP |
2315 | retval = rtsx_write_register(chip, FPGA_PULL_CTL, 0xFF, 0xDF); |
2316 | if (retval) { | |
2317 | rtsx_trace(chip); | |
2318 | return retval; | |
2319 | } | |
fa590c22 MC |
2320 | } |
2321 | ||
2322 | return STATUS_SUCCESS; | |
2323 | } | |
2324 | ||
2325 | int release_xd_card(struct rtsx_chip *chip) | |
2326 | { | |
14c42c79 | 2327 | struct xd_info *xd_card = &chip->xd_card; |
fa590c22 MC |
2328 | int retval; |
2329 | ||
fa590c22 MC |
2330 | chip->card_ready &= ~XD_CARD; |
2331 | chip->card_fail &= ~XD_CARD; | |
2332 | chip->card_wp &= ~XD_CARD; | |
2333 | ||
2334 | xd_card->delay_write.delay_write_flag = 0; | |
2335 | ||
2336 | xd_free_l2p_tbl(chip); | |
2337 | ||
2338 | retval = xd_power_off_card3v3(chip); | |
031366ea JP |
2339 | if (retval != STATUS_SUCCESS) { |
2340 | rtsx_trace(chip); | |
2341 | return STATUS_FAIL; | |
2342 | } | |
fa590c22 MC |
2343 | |
2344 | return STATUS_SUCCESS; | |
2345 | } |