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Staging: silicom: checkpatch.pl cleanup: pretty pointers
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7040e556
D		 1/******************************************************************************/
2/* */
3/* Bypass Control utility, Copyright (c) 2005-20011 Silicom */
4/* */
5/* This program is free software; you can redistribute it and/or modify */
6/* it under the terms of the GNU General Public License as published by */
7/* the Free Software Foundation, located in the file LICENSE. */
8/* Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. */
9/* */
10/* */
11/******************************************************************************/
12#include <linux/version.h>
7040e556
D		 13
14#include <linux/kernel.h> /* We're doing kernel work */
15#include <linux/module.h> /* Specifically, a module */
16#include <linux/fs.h>
17#include <linux/pci.h>
18#include <linux/delay.h>
19#include <linux/netdevice.h>
20#include <linux/rtnetlink.h>
21#include <linux/rcupdate.h>
22#include <linux/etherdevice.h>
23
86bc9ebb 24#include <linux/uaccess.h> /* for get_user and put_user */
7040e556
D		 25#include <linux/sched.h>
26#include <linux/ethtool.h>
27#include <linux/proc_fs.h>
28
29#include "bp_ioctl.h"
30#include "bp_mod.h"
31#include "bypass.h"
32#include "libbp_sd.h"
33
34#define SUCCESS 0
35#define BP_MOD_VER "9.0.4"
36#define BP_MOD_DESCR "Silicom Bypass-SD Control driver"
37#define BP_SYNC_FLAG 1
38
39static int Device_Open = 0;
40static int major_num = 0;
41
42MODULE_AUTHOR("Anna Lukin, annal@silicom.co.il");
43MODULE_LICENSE("GPL");
44MODULE_DESCRIPTION(BP_MOD_DESCR);
45MODULE_VERSION(BP_MOD_VER);
46spinlock_t bpvm_lock;
47
48#define lock_bpctl() \
49if (down_interruptible(&bpctl_sema)) { \
50 return -ERESTARTSYS; \
51} \
52
53#define unlock_bpctl() \
54 up(&bpctl_sema);
55
56/* Media Types */
57typedef enum {
58 bp_copper = 0,
59 bp_fiber,
60 bp_cx4,
61 bp_none,
62} bp_media_type;
63
64struct pfs_unit_sd {
65 struct proc_dir_entry *proc_entry;
66 char proc_name[32];
67};
68
69struct bypass_pfs_sd {
70 char dir_name[32];
71 struct proc_dir_entry *bypass_entry;
72 struct pfs_unit_sd bypass_info;
73 struct pfs_unit_sd bypass_slave;
74 struct pfs_unit_sd bypass_caps;
75 struct pfs_unit_sd wd_set_caps;
76 struct pfs_unit_sd bypass;
77 struct pfs_unit_sd bypass_change;
78 struct pfs_unit_sd bypass_wd;
79 struct pfs_unit_sd wd_expire_time;
80 struct pfs_unit_sd reset_bypass_wd;
81 struct pfs_unit_sd dis_bypass;
82 struct pfs_unit_sd bypass_pwup;
83 struct pfs_unit_sd bypass_pwoff;
84 struct pfs_unit_sd std_nic;
85 struct pfs_unit_sd tap;
86 struct pfs_unit_sd dis_tap;
87 struct pfs_unit_sd tap_pwup;
88 struct pfs_unit_sd tap_change;
89 struct pfs_unit_sd wd_exp_mode;
90 struct pfs_unit_sd wd_autoreset;
91 struct pfs_unit_sd tpl;
92
93};
94
95typedef struct _bpctl_dev {
96 char *name;
97 char *desc;
98 struct pci_dev *pdev; /* PCI device */
99 struct net_device *ndev; /* net device */
100 unsigned long mem_map;
101 uint8_t bus;
102 uint8_t slot;
103 uint8_t func;
104 u_int32_t device;
105 u_int32_t vendor;
106 u_int32_t subvendor;
107 u_int32_t subdevice;
108 int ifindex;
109 uint32_t bp_caps;
110 uint32_t bp_caps_ex;
111 uint8_t bp_fw_ver;
112 int bp_ext_ver;
113 int wdt_status;
114 unsigned long bypass_wdt_on_time;
115 uint32_t bypass_timer_interval;
116 struct timer_list bp_timer;
117 uint32_t reset_time;
118 uint8_t bp_status_un;
119 atomic_t wdt_busy;
120 bp_media_type media_type;
121 int bp_tpl_flag;
122 struct timer_list bp_tpl_timer;
123 spinlock_t bypass_wr_lock;
124 int bp_10g;
125 int bp_10gb;
126 int bp_fiber5;
127 int bp_10g9;
128 int bp_i80;
129 int bp_540;
130
131// selftest stanza
01448bbb
DC		 132 int (*hard_start_xmit_save) (struct sk_buff *skb,
133 struct net_device *dev);
7040e556
D		 134 const struct net_device_ops *old_ops;
135 struct net_device_ops new_ops;
136 int bp_self_test_flag;
137 char *bp_tx_data;
138// end selftest stanza
139//
140 struct bypass_pfs_sd bypass_pfs_set;
141
142} bpctl_dev_t;
143
144static bpctl_dev_t *bpctl_dev_arr;
145
146static struct semaphore bpctl_sema;
147static int device_num = 0;
148
149static int get_dev_idx(int ifindex);
01448bbb
DC		 150static bpctl_dev_t *get_master_port_fn(bpctl_dev_t *pbpctl_dev);
151static int disc_status(bpctl_dev_t *pbpctl_dev);
152static int bypass_status(bpctl_dev_t *pbpctl_dev);
153static int wdt_timer(bpctl_dev_t *pbpctl_dev, int *time_left);
154static bpctl_dev_t *get_status_port_fn(bpctl_dev_t *pbpctl_dev);
7040e556
D		 155static void if_scan_init(void);
156
01448bbb
DC		 157int bypass_proc_create_dev_sd(bpctl_dev_t *pbp_device_block);
158int bypass_proc_remove_dev_sd(bpctl_dev_t *pbp_device_block);
7040e556
D		 159int bp_proc_create(void);
160
01448bbb 161int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
7040e556
D		 162int get_dev_idx_bsf(int bus, int slot, int func);
163
164static unsigned long str_to_hex(char *p);
165static int bp_device_event(struct notifier_block *unused,
166 unsigned long event, void *ptr)
167{
168 struct net_device *dev = ptr;
169 static bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
170 int dev_num = 0, ret = 0, ret_d = 0, time_left = 0;
171 //printk("BP_PROC_SUPPORT event =%d %s %d\n", event,dev->name, dev->ifindex );
172 //return NOTIFY_DONE;
173 if (!dev)
174 return NOTIFY_DONE;
175 if (event == NETDEV_REGISTER) {
176 {
177 struct ethtool_drvinfo drvinfo;
178 // char *str=NULL;
179 char cbuf[32];
180 char *buf = NULL;
181 char res[10];
182 int i = 0, ifindex, idx_dev = 0;
183 int bus = 0, slot = 0, func = 0;
184 ifindex = dev->ifindex;
185
186 memset(res, 0, 10);
187 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
188
189 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
190 memset(&drvinfo, 0, sizeof(drvinfo));
191 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
192 } else
193 return NOTIFY_DONE;
194 if (!drvinfo.bus_info)
195 return NOTIFY_DONE;
196 if (!strcmp(drvinfo.bus_info, "N/A"))
197 return NOTIFY_DONE;
198 memcpy(&cbuf, drvinfo.bus_info, 32);
199 buf = &cbuf[0];
200
201 // while(*buf++){
202
203 /*if(*buf==':'){
204 buf++;
205 break;
206 } */
207 //}
208 while (*buf++ != ':') ;
209 for (i = 0; i < 10; i++, buf++) {
210 if (*buf == ':')
211 break;
212 res[i] = *buf;
213
214 }
215 buf++;
216 bus = str_to_hex(res);
217 memset(res, 0, 10);
218
219 for (i = 0; i < 10; i++, buf++) {
220 if (*buf == '.')
221 break;
222 res[i] = *buf;
223
224 }
225 buf++;
226 slot = str_to_hex(res);
227 func = str_to_hex(buf);
228 idx_dev = get_dev_idx_bsf(bus, slot, func);
229
230 if (idx_dev != -1) {
231
232 bpctl_dev_arr[idx_dev].ifindex = ifindex;
233 bpctl_dev_arr[idx_dev].ndev = dev;
234
235 bypass_proc_remove_dev_sd(&bpctl_dev_arr
236 [idx_dev]);
237 bypass_proc_create_dev_sd(&bpctl_dev_arr
238 [idx_dev]);
239
240 }
241
242 }
243 return NOTIFY_DONE;
244
245 }
246 if (event == NETDEV_UNREGISTER) {
247 int idx_dev = 0;
248 //if_scan();
249 for (idx_dev = 0;
250 ((bpctl_dev_arr[idx_dev].pdev != NULL)
251 && (idx_dev < device_num)); idx_dev++) {
252 if (bpctl_dev_arr[idx_dev].ndev == dev) {
253 bypass_proc_remove_dev_sd(&bpctl_dev_arr
254 [idx_dev]);
255 bpctl_dev_arr[idx_dev].ndev = NULL;
256
257 return NOTIFY_DONE;
258
259 }
260
261 }
262 return NOTIFY_DONE;
263 }
264 if (event == NETDEV_CHANGENAME) {
265 int idx_dev = 0;
266 //if_scan();
267 for (idx_dev = 0;
268 ((bpctl_dev_arr[idx_dev].pdev != NULL)
269 && (idx_dev < device_num)); idx_dev++) {
270 if (bpctl_dev_arr[idx_dev].ndev == dev) {
271 bypass_proc_remove_dev_sd(&bpctl_dev_arr
272 [idx_dev]);
273 bypass_proc_create_dev_sd(&bpctl_dev_arr
274 [idx_dev]);
275
276 return NOTIFY_DONE;
277
278 }
279
280 }
281 return NOTIFY_DONE;
282
283 }
284 //return NOTIFY_DONE;
285
286 switch (event) {
287
288 case NETDEV_CHANGE:{
289 if (netif_carrier_ok(dev))
290 return NOTIFY_DONE;
291
292 //if_scan();
293 if (((dev_num = get_dev_idx(dev->ifindex)) == -1) ||
294 (!(pbpctl_dev = &bpctl_dev_arr[dev_num])))
295 return NOTIFY_DONE;
296
297 if ((is_bypass_fn(pbpctl_dev)) == 1)
298 pbpctl_dev_m = pbpctl_dev;
299 else
300 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
301 if (!pbpctl_dev_m)
302 return NOTIFY_DONE;
303 ret = bypass_status(pbpctl_dev_m);
304 if (ret == 1)
305 printk("bpmod: %s is in the Bypass mode now",
306 dev->name);
307 ret_d = disc_status(pbpctl_dev_m);
308 if (ret_d == 1)
309 printk
310 ("bpmod: %s is in the Disconnect mode now",
311 dev->name);
312 if (ret || ret_d) {
313 wdt_timer(pbpctl_dev_m, &time_left);
314 if (time_left == -1)
315 printk("; WDT has expired");
316 printk(".\n");
317
318 }
319 return NOTIFY_DONE;
320
321 }
322
323 default:
324 return NOTIFY_DONE;
325
326 }
327 return NOTIFY_DONE;
328
329}
330
331static struct notifier_block bp_notifier_block = {
332 .notifier_call = bp_device_event,
333};
334
335static int device_open(struct inode *inode, struct file *file)
336{
337#ifdef DEBUG
338 printk("device_open(%p)\n", file);
339#endif
340 Device_Open++;
341/*
342* Initialize the message
343*/
344 return SUCCESS;
345}
346
347static int device_release(struct inode *inode, struct file *file)
348{
349#ifdef DEBUG
350 printk("device_release(%p,%p)\n", inode, file);
351#endif
352 Device_Open--;
353 return SUCCESS;
354}
355
01448bbb
DC		 356int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
357int wdt_time_left(bpctl_dev_t *pbpctl_dev);
7040e556 358
01448bbb 359static void write_pulse(bpctl_dev_t *pbpctl_dev,
7040e556
D		 360 unsigned int ctrl_ext,
361 unsigned char value, unsigned char len)
362{
363 unsigned char ctrl_val = 0;
364 unsigned int i = len;
365 unsigned int ctrl = 0;
366 bpctl_dev_t *pbpctl_dev_c = NULL;
367
368 if (pbpctl_dev->bp_i80)
369 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
370 if (pbpctl_dev->bp_540)
371 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
372
373 if (pbpctl_dev->bp_10g9) {
374 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
375 return;
376 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
377 }
378
379 while (i--) {
380 ctrl_val = (value >> i) & 0x1;
381 if (ctrl_val) {
382 if (pbpctl_dev->bp_10g9) {
383
384 /* To start management : MCLK 1, MDIO 1, output */
385 /* DATA 1 CLK 1 */
386 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
387 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
388 ctrl_ext |
389 BP10G_MDIO_DATA_OUT9);
390 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
391 (ctrl | BP10G_MCLK_DATA_OUT9 |
392 BP10G_MCLK_DIR_OUT9));
393
394 } else if (pbpctl_dev->bp_fiber5) {
395 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
396 BPCTLI_CTRL_EXT_MCLK_DIR5
397 |
398 BPCTLI_CTRL_EXT_MDIO_DIR5
399 |
400 BPCTLI_CTRL_EXT_MDIO_DATA5
401 |
402 BPCTLI_CTRL_EXT_MCLK_DATA5));
403
404 } else if (pbpctl_dev->bp_i80) {
405 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
406 BPCTLI_CTRL_EXT_MDIO_DIR80
407 |
408 BPCTLI_CTRL_EXT_MDIO_DATA80));
409
410 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, (ctrl |
411 BPCTLI_CTRL_EXT_MCLK_DIR80
412 |
413 BPCTLI_CTRL_EXT_MCLK_DATA80));
414
415 } else if (pbpctl_dev->bp_540) {
416 BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl |
417 BP540_MDIO_DIR
418 |
419 BP540_MDIO_DATA
420 |
421 BP540_MCLK_DIR
422 |
423 BP540_MCLK_DATA));
424
425 } else if (pbpctl_dev->bp_10gb) {
426 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
427 (ctrl_ext | BP10GB_MDIO_SET |
428 BP10GB_MCLK_SET) &
429 ~(BP10GB_MCLK_DIR |
430 BP10GB_MDIO_DIR |
431 BP10GB_MDIO_CLR |
432 BP10GB_MCLK_CLR));
433
434 } else if (!pbpctl_dev->bp_10g)
435 /* To start management : MCLK 1, MDIO 1, output */
436 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
437 (ctrl_ext |
438 BPCTLI_CTRL_EXT_MCLK_DIR |
439 BPCTLI_CTRL_EXT_MDIO_DIR |
440 BPCTLI_CTRL_EXT_MDIO_DATA |
441 BPCTLI_CTRL_EXT_MCLK_DATA));
442 else {
443
444/* To start management : MCLK 1, MDIO 1, output*/
445 //writel((0x2|0x8), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
446 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
447 (ctrl_ext | BP10G_MCLK_DATA_OUT
448 | BP10G_MDIO_DATA_OUT));
449 //BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl | BP10G_MDIO_DATA | BP10G_MDIO_DIR));
450
451 }
452
453 usec_delay(PULSE_TIME);
454 if (pbpctl_dev->bp_10g9) {
455
456 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~(BP10G_MCLK_DATA_OUT9))); */
457 /* DATA 1 CLK 0 */
458 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
459 ctrl_ext |
460 BP10G_MDIO_DATA_OUT9);
461 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
462 (ctrl | BP10G_MCLK_DIR_OUT9) &
463 ~BP10G_MCLK_DATA_OUT9);
464
465 } else if (pbpctl_dev->bp_fiber5) {
466 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
467 ((ctrl_ext |
468 BPCTLI_CTRL_EXT_MCLK_DIR5 |
469 BPCTLI_CTRL_EXT_MDIO_DIR5 |
470 BPCTLI_CTRL_EXT_MDIO_DATA5)
471 &
472 ~
473 (BPCTLI_CTRL_EXT_MCLK_DATA5)));
474
475 } else if (pbpctl_dev->bp_i80) {
476 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
477 BPCTLI_CTRL_EXT_MDIO_DIR80
478 |
479 BPCTLI_CTRL_EXT_MDIO_DATA80));
480 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
481 ((ctrl |
482 BPCTLI_CTRL_EXT_MCLK_DIR80)
483 &
484 ~
485 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
486
487 } else if (pbpctl_dev->bp_540) {
488 BP10G_WRITE_REG(pbpctl_dev, ESDP,
489 (ctrl | BP540_MDIO_DIR |
490 BP540_MDIO_DATA |
491 BP540_MCLK_DIR) &
492 ~(BP540_MCLK_DATA));
493
494 } else if (pbpctl_dev->bp_10gb) {
495
496 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
497 (ctrl_ext | BP10GB_MDIO_SET |
498 BP10GB_MCLK_CLR) &
499 ~(BP10GB_MCLK_DIR |
500 BP10GB_MDIO_DIR |
501 BP10GB_MDIO_CLR |
502 BP10GB_MCLK_SET));
503
504 } else if (!pbpctl_dev->bp_10g)
505
506 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
507 ((ctrl_ext |
508 BPCTLI_CTRL_EXT_MCLK_DIR |
509 BPCTLI_CTRL_EXT_MDIO_DIR |
510 BPCTLI_CTRL_EXT_MDIO_DATA)
511 &
512 ~
513 (BPCTLI_CTRL_EXT_MCLK_DATA)));
514 else {
515
516 //writel((0x2), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
517 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
518 ((ctrl_ext |
519 BP10G_MDIO_DATA_OUT) &
520 ~(BP10G_MCLK_DATA_OUT)));
521 // BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl |BP10G_MDIO_DIR|BP10G_MDIO_DATA));
522 }
523
524 usec_delay(PULSE_TIME);
525
526 } else {
527 if (pbpctl_dev->bp_10g9) {
528 /* DATA 0 CLK 1 */
529 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
530 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
531 (ctrl_ext &
532 ~BP10G_MDIO_DATA_OUT9));
533 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
534 (ctrl | BP10G_MCLK_DATA_OUT9 |
535 BP10G_MCLK_DIR_OUT9));
536
537 } else if (pbpctl_dev->bp_fiber5) {
538 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
539 ((ctrl_ext |
540 BPCTLI_CTRL_EXT_MCLK_DIR5 |
541 BPCTLI_CTRL_EXT_MDIO_DIR5 |
542 BPCTLI_CTRL_EXT_MCLK_DATA5)
543 &
544 ~
545 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
546
547 } else if (pbpctl_dev->bp_i80) {
548 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
549 ((ctrl_ext |
550 BPCTLI_CTRL_EXT_MDIO_DIR80)
551 &
552 ~
553 (BPCTLI_CTRL_EXT_MDIO_DATA80)));
554 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
555 (ctrl |
556 BPCTLI_CTRL_EXT_MCLK_DIR80 |
557 BPCTLI_CTRL_EXT_MCLK_DATA80));
558
559 } else if (pbpctl_dev->bp_540) {
560 BP10G_WRITE_REG(pbpctl_dev, ESDP,
561 ((ctrl | BP540_MCLK_DIR |
562 BP540_MCLK_DATA |
563 BP540_MDIO_DIR) &
564 ~(BP540_MDIO_DATA)));
565
566 } else if (pbpctl_dev->bp_10gb) {
567 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
568 (ctrl_ext | BP10GB_MDIO_CLR |
569 BP10GB_MCLK_SET) &
570 ~(BP10GB_MCLK_DIR |
571 BP10GB_MDIO_DIR |
572 BP10GB_MDIO_SET |
573 BP10GB_MCLK_CLR));
574
575 } else if (!pbpctl_dev->bp_10g)
576
577 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
578 ((ctrl_ext |
579 BPCTLI_CTRL_EXT_MCLK_DIR |
580 BPCTLI_CTRL_EXT_MDIO_DIR |
581 BPCTLI_CTRL_EXT_MCLK_DATA)
582 &
583 ~
584 (BPCTLI_CTRL_EXT_MDIO_DATA)));
585 else {
586
587 // writel((0x8), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
588 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
589 ((ctrl_ext |
590 BP10G_MCLK_DATA_OUT) &
591 ~BP10G_MDIO_DATA_OUT));
592 // BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |BP10G_MDIO_DIR)&~BP10G_MDIO_DATA));
593
594 }
595 usec_delay(PULSE_TIME);
596 if (pbpctl_dev->bp_10g9) {
597 /* DATA 0 CLK 0 */
598 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
599 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
600 (ctrl_ext &
601 ~BP10G_MDIO_DATA_OUT9));
602 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
603 ((ctrl | BP10G_MCLK_DIR_OUT9) &
604 ~(BP10G_MCLK_DATA_OUT9)));
605
606 } else if (pbpctl_dev->bp_fiber5) {
607 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
608 ((ctrl_ext |
609 BPCTLI_CTRL_EXT_MCLK_DIR5 |
610 BPCTLI_CTRL_EXT_MDIO_DIR5)
611 &
612 ~(BPCTLI_CTRL_EXT_MCLK_DATA5
613 |
614 BPCTLI_CTRL_EXT_MDIO_DATA5)));
615
616 } else if (pbpctl_dev->bp_i80) {
617 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
618 ((ctrl_ext |
619 BPCTLI_CTRL_EXT_MDIO_DIR80)
620 &
621 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
622 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
623 ((ctrl |
624 BPCTLI_CTRL_EXT_MCLK_DIR80)
625 &
626 ~
627 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
628
629 } else if (pbpctl_dev->bp_540) {
630 BP10G_WRITE_REG(pbpctl_dev, ESDP,
631 ((ctrl | BP540_MCLK_DIR |
632 BP540_MDIO_DIR) &
633 ~(BP540_MDIO_DATA |
634 BP540_MCLK_DATA)));
635 } else if (pbpctl_dev->bp_10gb) {
636
637 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
638 (ctrl_ext | BP10GB_MDIO_CLR |
639 BP10GB_MCLK_CLR) &
640 ~(BP10GB_MCLK_DIR |
641 BP10GB_MDIO_DIR |
642 BP10GB_MDIO_SET |
643 BP10GB_MCLK_SET));
644
645 } else if (!pbpctl_dev->bp_10g)
646 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
647 ((ctrl_ext |
648 BPCTLI_CTRL_EXT_MCLK_DIR |
649 BPCTLI_CTRL_EXT_MDIO_DIR) &
650 ~(BPCTLI_CTRL_EXT_MCLK_DATA
651 |
652 BPCTLI_CTRL_EXT_MDIO_DATA)));
653 else {
654
655 //writel((0x0), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
656 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
657 (ctrl_ext &
658 ~(BP10G_MCLK_DATA_OUT |
659 BP10G_MDIO_DATA_OUT)));
660 //BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |BP10G_MDIO_DIR)&~BP10G_MDIO_DATA));
661 }
662
663 usec_delay(PULSE_TIME);
664 }
665
666 }
667}
668
01448bbb 669static int read_pulse(bpctl_dev_t *pbpctl_dev, unsigned int ctrl_ext,
7040e556
D		 670 unsigned char len)
671{
672 unsigned char ctrl_val = 0;
673 unsigned int i = len;
674 unsigned int ctrl = 0;
675 bpctl_dev_t *pbpctl_dev_c = NULL;
676
677 if (pbpctl_dev->bp_i80)
678 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
679 if (pbpctl_dev->bp_540)
680 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
681 if (pbpctl_dev->bp_10g9) {
682 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
683 return -1;
684 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
685 }
686
687 //ctrl_ext=BP10G_READ_REG(pbpctl_dev,EODSDP);
688
689 while (i--) {
690 if (pbpctl_dev->bp_10g9) {
691 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~BP10G_MCLK_DATA_OUT9)); */
692 /* DATA ? CLK 0 */
693 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
694 ((ctrl | BP10G_MCLK_DIR_OUT9) &
695 ~(BP10G_MCLK_DATA_OUT9)));
696
697 } else if (pbpctl_dev->bp_fiber5) {
698 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
699 BPCTLI_CTRL_EXT_MCLK_DIR5)
700 &
701 ~
702 (BPCTLI_CTRL_EXT_MDIO_DIR5
703 |
704 BPCTLI_CTRL_EXT_MCLK_DATA5)));
705
706 } else if (pbpctl_dev->bp_i80) {
707 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
708 (ctrl_ext &
709 ~BPCTLI_CTRL_EXT_MDIO_DIR80));
710 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
711 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80)
712 & ~(BPCTLI_CTRL_EXT_MCLK_DATA80)));
713
714 } else if (pbpctl_dev->bp_540) {
715 BP10G_WRITE_REG(pbpctl_dev, ESDP,
716 ((ctrl | BP540_MCLK_DIR) &
717 ~(BP540_MDIO_DIR | BP540_MCLK_DATA)));
718
719 } else if (pbpctl_dev->bp_10gb) {
720
721 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
722 (ctrl_ext | BP10GB_MDIO_DIR |
723 BP10GB_MCLK_CLR) & ~(BP10GB_MCLK_DIR |
724 BP10GB_MDIO_CLR |
725 BP10GB_MDIO_SET |
726 BP10GB_MCLK_SET));
727
728 } else if (!pbpctl_dev->bp_10g)
729 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
730 BPCTLI_CTRL_EXT_MCLK_DIR)
731 &
732 ~
733 (BPCTLI_CTRL_EXT_MDIO_DIR
734 |
735 BPCTLI_CTRL_EXT_MCLK_DATA)));
736 else {
737
738 // writel(( 0/*0x1*/), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
739 BP10G_WRITE_REG(pbpctl_dev, EODSDP, ((ctrl_ext | BP10G_MDIO_DATA_OUT) & ~BP10G_MCLK_DATA_OUT)); /* ? */
740 // printk("0x28=0x%x\n",BP10G_READ_REG(pbpctl_dev,EODSDP););
741 //BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl &~BP10G_MDIO_DIR));
742
743 }
744
745 usec_delay(PULSE_TIME);
746 if (pbpctl_dev->bp_10g9) {
747 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
748 /* DATA ? CLK 1 */
749 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
750 (ctrl | BP10G_MCLK_DATA_OUT9 |
751 BP10G_MCLK_DIR_OUT9));
752
753 } else if (pbpctl_dev->bp_fiber5) {
754 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
755 BPCTLI_CTRL_EXT_MCLK_DIR5
756 |
757 BPCTLI_CTRL_EXT_MCLK_DATA5)
758 &
759 ~
760 (BPCTLI_CTRL_EXT_MDIO_DIR5)));
761
762 } else if (pbpctl_dev->bp_i80) {
763 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
764 (ctrl_ext &
765 ~(BPCTLI_CTRL_EXT_MDIO_DIR80)));
766 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
767 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
768 BPCTLI_CTRL_EXT_MCLK_DATA80));
769
770 } else if (pbpctl_dev->bp_540) {
771 BP10G_WRITE_REG(pbpctl_dev, ESDP,
772 ((ctrl | BP540_MCLK_DIR |
773 BP540_MCLK_DATA) &
774 ~(BP540_MDIO_DIR)));
775
776 } else if (pbpctl_dev->bp_10gb) {
777 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
778 (ctrl_ext | BP10GB_MDIO_DIR |
779 BP10GB_MCLK_SET) & ~(BP10GB_MCLK_DIR |
780 BP10GB_MDIO_CLR |
781 BP10GB_MDIO_SET |
782 BP10GB_MCLK_CLR));
783
784 } else if (!pbpctl_dev->bp_10g)
785 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
786 BPCTLI_CTRL_EXT_MCLK_DIR
787 |
788 BPCTLI_CTRL_EXT_MCLK_DATA)
789 &
790 ~
791 (BPCTLI_CTRL_EXT_MDIO_DIR)));
792 else {
793
794 // writel((0x8 /*|0x1*/ ), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
795 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
796 (ctrl_ext | BP10G_MCLK_DATA_OUT |
797 BP10G_MDIO_DATA_OUT));
798 //BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl &~BP10G_MDIO_DIR));
799
800 }
801 if (pbpctl_dev->bp_10g9) {
802 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
803
804 } else if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_i80)) {
805 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
806 } else if (pbpctl_dev->bp_540) {
807 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
808 } else if (pbpctl_dev->bp_10gb)
809 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
810
811 else if (!pbpctl_dev->bp_10g)
812 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
813 else
814 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
815 //ctrl_ext =readl((void *)((pbpctl_dev)->mem_map) + 0x28);
816
817 usec_delay(PULSE_TIME);
818 if (pbpctl_dev->bp_10g9) {
819 if (ctrl_ext & BP10G_MDIO_DATA_IN9)
820 ctrl_val |= 1 << i;
821
822 } else if (pbpctl_dev->bp_fiber5) {
823 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA5)
824 ctrl_val |= 1 << i;
825 } else if (pbpctl_dev->bp_i80) {
826 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA80)
827 ctrl_val |= 1 << i;
828 } else if (pbpctl_dev->bp_540) {
829 if (ctrl_ext & BP540_MDIO_DATA)
830 ctrl_val |= 1 << i;
831 } else if (pbpctl_dev->bp_10gb) {
832 if (ctrl_ext & BP10GB_MDIO_DATA)
833 ctrl_val |= 1 << i;
834
835 } else if (!pbpctl_dev->bp_10g) {
836
837 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA)
838 ctrl_val |= 1 << i;
839 } else {
840
841 if (ctrl_ext & BP10G_MDIO_DATA_IN)
842 ctrl_val |= 1 << i;
843 }
844
845 }
846
847 return ctrl_val;
848}
849
01448bbb 850static void write_reg(bpctl_dev_t *pbpctl_dev, unsigned char value,
7040e556
D		 851 unsigned char addr)
852{
853 uint32_t ctrl_ext = 0, ctrl = 0;
854 bpctl_dev_t *pbpctl_dev_c = NULL;
855 unsigned long flags;
856 if (pbpctl_dev->bp_10g9) {
857 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
858 return;
859 }
860 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
861 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER))
862 wdt_time_left(pbpctl_dev);
863
864#ifdef BP_SYNC_FLAG
865 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
866#else
867 atomic_set(&pbpctl_dev->wdt_busy, 1);
868#endif
869 if (pbpctl_dev->bp_10g9) {
870
871 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
872 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
873 /* DATA 0 CLK 0 */
874 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
875 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
876 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
877 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
878 ((ctrl | BP10G_MCLK_DIR_OUT9) &
879 ~(BP10G_MCLK_DATA_OUT9)));
880
881 } else if (pbpctl_dev->bp_fiber5) {
882 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
883 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
884 BPCTLI_CTRL_EXT_MCLK_DIR5
885 |
886 BPCTLI_CTRL_EXT_MDIO_DIR5)
887 &
888 ~
889 (BPCTLI_CTRL_EXT_MDIO_DATA5
890 |
891 BPCTLI_CTRL_EXT_MCLK_DATA5)));
892 } else if (pbpctl_dev->bp_i80) {
893 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
894 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
895 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
896 BPCTLI_CTRL_EXT_MDIO_DIR80)
897 &
898 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
899 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
900 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
901 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
902
903 } else if (pbpctl_dev->bp_540) {
904 ctrl = ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
905 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
906 BP540_MDIO_DIR |
907 BP540_MCLK_DIR) &
908 ~(BP540_MDIO_DATA |
909 BP540_MCLK_DATA)));
910
911 } else if (pbpctl_dev->bp_10gb) {
912 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
913
914 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
915 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
916 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
917 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
918
919 } else if (!pbpctl_dev->bp_10g) {
920
921 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
922 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
923 BPCTLI_CTRL_EXT_MCLK_DIR
924 |
925 BPCTLI_CTRL_EXT_MDIO_DIR)
926 &
927 ~
928 (BPCTLI_CTRL_EXT_MDIO_DATA
929 |
930 BPCTLI_CTRL_EXT_MCLK_DATA)));
931 } else {
932 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
933 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
934 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
935 (ctrl_ext &
936 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
937 //BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |BP10G_MDIO_DIR)&~BP10G_MDIO_DATA));
938 //writel((0x0), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
939 }
940 usec_delay(CMND_INTERVAL);
941
942 /*send sync cmd */
943 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
944 /*send wr cmd */
945 write_pulse(pbpctl_dev, ctrl_ext, WR_CMD_VAL, WR_CMD_LEN);
946 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
947
948 /*write data */
949 write_pulse(pbpctl_dev, ctrl_ext, value, WR_DATA_LEN);
950 if (pbpctl_dev->bp_10g9) {
951 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
952 /* DATA 0 CLK 0 */
953 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
954 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
955 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
956 ((ctrl | BP10G_MCLK_DIR_OUT9) &
957 ~(BP10G_MCLK_DATA_OUT9)));
958
959 } else if (pbpctl_dev->bp_fiber5) {
960 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
961 BPCTLI_CTRL_EXT_MCLK_DIR5
962 |
963 BPCTLI_CTRL_EXT_MDIO_DIR5)
964 &
965 ~
966 (BPCTLI_CTRL_EXT_MDIO_DATA5
967 |
968 BPCTLI_CTRL_EXT_MCLK_DATA5)));
969 } else if (pbpctl_dev->bp_i80) {
970 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
971 BPCTLI_CTRL_EXT_MDIO_DIR80)
972 &
973 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
974 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
975 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
976 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
977 } else if (pbpctl_dev->bp_540) {
978 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
979 BP540_MDIO_DIR |
980 BP540_MCLK_DIR) &
981 ~(BP540_MDIO_DATA |
982 BP540_MCLK_DATA)));
983 } else if (pbpctl_dev->bp_10gb) {
984 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
985 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
986 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
987 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
988
989 } else if (!pbpctl_dev->bp_10g)
990
991 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
992 BPCTLI_CTRL_EXT_MCLK_DIR
993 |
994 BPCTLI_CTRL_EXT_MDIO_DIR)
995 &
996 ~
997 (BPCTLI_CTRL_EXT_MDIO_DATA
998 |
999 BPCTLI_CTRL_EXT_MCLK_DATA)));
1000 else {
1001 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1002 (ctrl_ext &
1003 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1004 // BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |BP10G_MDIO_DIR)&~BP10G_MDIO_DATA));
1005
1006 // writel((0x0), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
1007 }
1008
1009 usec_delay(CMND_INTERVAL * 4);
1010
1011 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
1012 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER) && (addr == CMND_REG_ADDR))
1013 pbpctl_dev->bypass_wdt_on_time = jiffies;
1014#ifdef BP_SYNC_FLAG
1015 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1016#else
1017 atomic_set(&pbpctl_dev->wdt_busy, 0);
1018#endif
1019
1020}
1021
01448bbb 1022static void write_data(bpctl_dev_t *pbpctl_dev, unsigned char value)
7040e556
D		 1023{
1024 write_reg(pbpctl_dev, value, CMND_REG_ADDR);
1025}
1026
01448bbb 1027static int read_reg(bpctl_dev_t *pbpctl_dev, unsigned char addr)
7040e556
D		 1028{
1029 uint32_t ctrl_ext = 0, ctrl = 0, ctrl_value = 0;
1030 bpctl_dev_t *pbpctl_dev_c = NULL;
1031
1032#ifdef BP_SYNC_FLAG
1033 unsigned long flags;
1034 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1035#else
1036 atomic_set(&pbpctl_dev->wdt_busy, 1);
1037#endif
1038 if (pbpctl_dev->bp_10g9) {
1039 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
1040 return -1;
1041 }
1042
1043 if (pbpctl_dev->bp_10g9) {
1044 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1045 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1046
1047 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1048 /* DATA 0 CLK 0 */
1049 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1050 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1051 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1052 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1053 ~(BP10G_MCLK_DATA_OUT9)));
1054
1055 } else if (pbpctl_dev->bp_fiber5) {
1056 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1057
1058 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1059 BPCTLI_CTRL_EXT_MCLK_DIR5
1060 |
1061 BPCTLI_CTRL_EXT_MDIO_DIR5)
1062 &
1063 ~
1064 (BPCTLI_CTRL_EXT_MDIO_DATA5
1065 |
1066 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1067 } else if (pbpctl_dev->bp_i80) {
1068 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1069 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1070
1071 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1072 BPCTLI_CTRL_EXT_MDIO_DIR80)
1073 &
1074 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1075 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1076 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1077 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1078 } else if (pbpctl_dev->bp_540) {
1079 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
1080 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1081
1082 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1083 BP540_MDIO_DIR) &
1084 ~(BP540_MDIO_DATA |
1085 BP540_MCLK_DATA)));
1086 } else if (pbpctl_dev->bp_10gb) {
1087 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1088
1089 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1090 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1091 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1092 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1093#if 0
1094
1095 /*BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, (ctrl_ext | BP10GB_MCLK_DIR | BP10GB_MDIO_DIR|
1096 BP10GB_MCLK_CLR|BP10GB_MDIO_CLR));
1097 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1098 printk("1reg=%x\n", ctrl_ext); */
1099
1100 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, ((ctrl_ext |
1101 BP10GB_MCLK_SET |
1102 BP10GB_MDIO_CLR))
1103 & ~(BP10GB_MCLK_CLR | BP10GB_MDIO_SET |
1104 BP10GB_MCLK_DIR | BP10GB_MDIO_DIR));
1105
1106 /* bnx2x_set_spio(pbpctl_dev, 5, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1107 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1108 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_INPUT_HI_Z); */
1109
1110 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1111
1112 //printk("2reg=%x\n", ctrl_ext);
1113
1114#ifdef BP_SYNC_FLAG
1115 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1116#else
1117 atomic_set(&pbpctl_dev->wdt_busy, 0);
1118#endif
1119
1120 return 0;
1121
1122#endif
1123
1124 } else if (!pbpctl_dev->bp_10g) {
1125
1126 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1127
1128 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1129 BPCTLI_CTRL_EXT_MCLK_DIR
1130 |
1131 BPCTLI_CTRL_EXT_MDIO_DIR)
1132 &
1133 ~
1134 (BPCTLI_CTRL_EXT_MDIO_DATA
1135 |
1136 BPCTLI_CTRL_EXT_MCLK_DATA)));
1137 } else {
1138
1139 // writel((0x0), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
1140 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1141 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1142 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1143 (ctrl_ext &
1144 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1145 //BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |BP10G_MDIO_DIR)&~BP10G_MDIO_DATA));
1146
1147 }
1148
1149 usec_delay(CMND_INTERVAL);
1150
1151 /*send sync cmd */
1152 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
1153 /*send rd cmd */
1154 write_pulse(pbpctl_dev, ctrl_ext, RD_CMD_VAL, RD_CMD_LEN);
1155 /*send addr */
1156 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
1157 /*read data */
1158 /* zero */
1159 if (pbpctl_dev->bp_10g9) {
1160 /* DATA 0 CLK 1 */
1161 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
1162 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1163 (ctrl_ext | BP10G_MDIO_DATA_OUT9));
1164 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1165 (ctrl | BP10G_MCLK_DATA_OUT9 |
1166 BP10G_MCLK_DIR_OUT9));
1167
1168 } else if (pbpctl_dev->bp_fiber5) {
1169 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1170 BPCTLI_CTRL_EXT_MCLK_DIR5
1171 |
1172 BPCTLI_CTRL_EXT_MCLK_DATA5)
1173 &
1174 ~
1175 (BPCTLI_CTRL_EXT_MDIO_DIR5
1176 |
1177 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1178
1179 } else if (pbpctl_dev->bp_i80) {
1180 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
1181 (ctrl_ext &
1182 ~(BPCTLI_CTRL_EXT_MDIO_DATA80 |
1183 BPCTLI_CTRL_EXT_MDIO_DIR80)));
1184 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1185 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1186 BPCTLI_CTRL_EXT_MCLK_DATA80));
1187
1188 } else if (pbpctl_dev->bp_540) {
1189 BP10G_WRITE_REG(pbpctl_dev, ESDP,
1190 (((ctrl | BP540_MDIO_DIR | BP540_MCLK_DIR |
1191 BP540_MCLK_DATA) & ~BP540_MDIO_DATA)));
1192
1193 } else if (pbpctl_dev->bp_10gb) {
1194
1195 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1196 (ctrl_ext | BP10GB_MDIO_DIR | BP10GB_MCLK_SET)
1197 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_SET |
1198 BP10GB_MDIO_CLR | BP10GB_MCLK_CLR));
1199
1200 } else if (!pbpctl_dev->bp_10g)
1201 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1202 BPCTLI_CTRL_EXT_MCLK_DIR
1203 |
1204 BPCTLI_CTRL_EXT_MCLK_DATA)
1205 &
1206 ~
1207 (BPCTLI_CTRL_EXT_MDIO_DIR
1208 |
1209 BPCTLI_CTRL_EXT_MDIO_DATA)));
1210 else {
1211
1212 // writel((0x8), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
1213 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1214 (ctrl_ext | BP10G_MCLK_DATA_OUT |
1215 BP10G_MDIO_DATA_OUT));
1216
1217 // BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl &~(BP10G_MDIO_DATA|BP10G_MDIO_DIR)));
1218
1219 }
1220 usec_delay(PULSE_TIME);
1221
1222 ctrl_value = read_pulse(pbpctl_dev, ctrl_ext, RD_DATA_LEN);
1223
1224 if (pbpctl_dev->bp_10g9) {
1225 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1226 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1227
1228 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1229 /* DATA 0 CLK 0 */
1230 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1231 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1232 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1233 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1234 ~(BP10G_MCLK_DATA_OUT9)));
1235
1236 } else if (pbpctl_dev->bp_fiber5) {
1237 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1238 BPCTLI_CTRL_EXT_MCLK_DIR5
1239 |
1240 BPCTLI_CTRL_EXT_MDIO_DIR5)
1241 &
1242 ~
1243 (BPCTLI_CTRL_EXT_MDIO_DATA5
1244 |
1245 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1246 } else if (pbpctl_dev->bp_i80) {
1247 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1248 BPCTLI_CTRL_EXT_MDIO_DIR80)
1249 &
1250 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1251 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1252 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1253 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1254
1255 } else if (pbpctl_dev->bp_540) {
1256 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1257 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1258 BP540_MDIO_DIR) &
1259 ~(BP540_MDIO_DATA |
1260 BP540_MCLK_DATA)));
1261
1262 } else if (pbpctl_dev->bp_10gb) {
1263 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1264 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1265 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1266 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1267 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1268
1269 } else if (!pbpctl_dev->bp_10g) {
1270 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1271 BPCTLI_CTRL_EXT_MCLK_DIR
1272 |
1273 BPCTLI_CTRL_EXT_MDIO_DIR)
1274 &
1275 ~
1276 (BPCTLI_CTRL_EXT_MDIO_DATA
1277 |
1278 BPCTLI_CTRL_EXT_MCLK_DATA)));
1279 } else {
1280
1281 //writel((0x0), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
1282 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1283 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1284 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1285 (ctrl_ext &
1286 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1287 //BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |BP10G_MDIO_DIR)&~BP10G_MDIO_DATA));
1288
1289 }
1290
1291 usec_delay(CMND_INTERVAL * 4);
1292#ifdef BP_SYNC_FLAG
1293 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1294#else
1295 atomic_set(&pbpctl_dev->wdt_busy, 0);
1296#endif
1297
1298 return ctrl_value;
1299}
1300
01448bbb 1301static int wdt_pulse(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1302{
1303 uint32_t ctrl_ext = 0, ctrl = 0;
1304 bpctl_dev_t *pbpctl_dev_c = NULL;
1305
1306#ifdef BP_SYNC_FLAG
1307 unsigned long flags;
1308
1309 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1310#else
1311
1312 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1313 return -1;
1314#endif
1315 if (pbpctl_dev->bp_10g9) {
1316 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
1317 return -1;
1318 }
1319
1320 if (pbpctl_dev->bp_10g9) {
1321 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1322 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1323
1324 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1325 /* DATA 0 CLK 0 */
1326 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1327 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1328 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1329 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1330 ~(BP10G_MCLK_DATA_OUT9)));
1331
1332 } else if (pbpctl_dev->bp_fiber5) {
1333 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1334 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1335 BPCTLI_CTRL_EXT_MCLK_DIR5
1336 |
1337 BPCTLI_CTRL_EXT_MDIO_DIR5)
1338 &
1339 ~
1340 (BPCTLI_CTRL_EXT_MDIO_DATA5
1341 |
1342 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1343 } else if (pbpctl_dev->bp_i80) {
1344 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1345 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1346 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1347 BPCTLI_CTRL_EXT_MDIO_DIR80)
1348 &
1349 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1350 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1351 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1352 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1353 } else if (pbpctl_dev->bp_540) {
1354 ctrl_ext = ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1355 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1356 BP540_MDIO_DIR) &
1357 ~(BP540_MDIO_DATA |
1358 BP540_MCLK_DATA)));
1359 } else if (pbpctl_dev->bp_10gb) {
1360 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1361 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1362 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1363 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1364 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1365
1366 } else if (!pbpctl_dev->bp_10g) {
1367
1368 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1369 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1370 BPCTLI_CTRL_EXT_MCLK_DIR
1371 |
1372 BPCTLI_CTRL_EXT_MDIO_DIR)
1373 &
1374 ~
1375 (BPCTLI_CTRL_EXT_MDIO_DATA
1376 |
1377 BPCTLI_CTRL_EXT_MCLK_DATA)));
1378 } else {
1379
1380 // writel((0x0), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
1381 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1382 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1383 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1384 (ctrl_ext &
1385 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1386 //BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |BP10G_MDIO_DIR)&~BP10G_MDIO_DATA));
1387
1388 }
1389 if (pbpctl_dev->bp_10g9) {
1390 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
1391 /* DATA 0 CLK 1 */
1392 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1393 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1394 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1395 (ctrl | BP10G_MCLK_DATA_OUT9 |
1396 BP10G_MCLK_DIR_OUT9));
1397
1398 } else if (pbpctl_dev->bp_fiber5) {
1399 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1400 BPCTLI_CTRL_EXT_MCLK_DIR5
1401 |
1402 BPCTLI_CTRL_EXT_MDIO_DIR5
1403 |
1404 BPCTLI_CTRL_EXT_MCLK_DATA5)
1405 &
1406 ~
1407 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
1408 } else if (pbpctl_dev->bp_i80) {
1409 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1410 BPCTLI_CTRL_EXT_MDIO_DIR80)
1411 &
1412 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1413 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1414 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1415 BPCTLI_CTRL_EXT_MCLK_DATA80));
1416
1417 } else if (pbpctl_dev->bp_540) {
1418 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
1419 BP540_MDIO_DIR |
1420 BP540_MCLK_DIR |
1421 BP540_MCLK_DATA) &
1422 ~BP540_MDIO_DATA));
1423
1424 } else if (pbpctl_dev->bp_10gb) {
1425 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1426
1427 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1428 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_SET)
1429 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1430 BP10GB_MDIO_SET | BP10GB_MCLK_CLR));
1431
1432 } else if (!pbpctl_dev->bp_10g)
1433 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1434 BPCTLI_CTRL_EXT_MCLK_DIR
1435 |
1436 BPCTLI_CTRL_EXT_MDIO_DIR
1437 |
1438 BPCTLI_CTRL_EXT_MCLK_DATA)
1439 &
1440 ~
1441 (BPCTLI_CTRL_EXT_MDIO_DATA)));
1442 else {
1443
1444 //writel((0x8), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
1445 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1446 ((ctrl_ext | BP10G_MCLK_DATA_OUT) &
1447 ~BP10G_MDIO_DATA_OUT));
1448 //BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |BP10G_MDIO_DIR)&~BP10G_MDIO_DATA));
1449
1450 }
1451
1452 usec_delay(WDT_INTERVAL);
1453 if (pbpctl_dev->bp_10g9) {
1454 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1455 /* DATA 0 CLK 0 */
1456 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1457 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1458 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1459 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1460 ~(BP10G_MCLK_DATA_OUT9)));
1461
1462 } else if (pbpctl_dev->bp_fiber5) {
1463 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1464 BPCTLI_CTRL_EXT_MCLK_DIR5
1465 |
1466 BPCTLI_CTRL_EXT_MDIO_DIR5)
1467 &
1468 ~
1469 (BPCTLI_CTRL_EXT_MCLK_DATA5
1470 |
1471 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1472 } else if (pbpctl_dev->bp_i80) {
1473 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1474 BPCTLI_CTRL_EXT_MDIO_DIR80)
1475 &
1476 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1477 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1478 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1479 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1480
1481 } else if (pbpctl_dev->bp_540) {
1482 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1483 BP540_MDIO_DIR) &
1484 ~(BP540_MDIO_DATA |
1485 BP540_MCLK_DATA)));
1486
1487 } else if (pbpctl_dev->bp_10gb) {
1488 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1489 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1490 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1491 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1492 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1493
1494 } else if (!pbpctl_dev->bp_10g)
1495 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1496 BPCTLI_CTRL_EXT_MCLK_DIR
1497 |
1498 BPCTLI_CTRL_EXT_MDIO_DIR)
1499 &
1500 ~
1501 (BPCTLI_CTRL_EXT_MCLK_DATA
1502 |
1503 BPCTLI_CTRL_EXT_MDIO_DATA)));
1504 else {
1505
1506 //writel((0x0), (void *)(((pbpctl_dev)->mem_map) + 0x28)) ;
1507 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1508 (ctrl_ext &
1509 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
1510 //BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |BP10G_MDIO_DIR)&~BP10G_MDIO_DATA));
1511 }
1512 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) /*&&
1513 (pbpctl_dev->bp_ext_ver<PXG4BPFI_VER) */ )
1514 pbpctl_dev->bypass_wdt_on_time = jiffies;
1515#ifdef BP_SYNC_FLAG
1516 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1517#endif
1518 usec_delay(CMND_INTERVAL * 4);
1519 return 0;
1520}
1521
01448bbb 1522static void data_pulse(bpctl_dev_t *pbpctl_dev, unsigned char value)
7040e556
D		 1523{
1524
1525 uint32_t ctrl_ext = 0;
1526#ifdef BP_SYNC_FLAG
1527 unsigned long flags;
1528#endif
1529 wdt_time_left(pbpctl_dev);
1530#ifdef BP_SYNC_FLAG
1531 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1532#else
1533 atomic_set(&pbpctl_dev->wdt_busy, 1);
1534#endif
1535
1536 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1537 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1538 BPCTLI_CTRL_EXT_SDP6_DIR |
1539 BPCTLI_CTRL_EXT_SDP7_DIR) &
1540 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1541 BPCTLI_CTRL_EXT_SDP7_DATA)));
1542
1543 usec_delay(INIT_CMND_INTERVAL);
1544 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1545 BPCTLI_CTRL_EXT_SDP6_DIR |
1546 BPCTLI_CTRL_EXT_SDP7_DIR |
1547 BPCTLI_CTRL_EXT_SDP6_DATA) &
1548 ~
1549 (BPCTLI_CTRL_EXT_SDP7_DATA)));
1550 usec_delay(INIT_CMND_INTERVAL);
1551
1552 while (value) {
1553 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1554 BPCTLI_CTRL_EXT_SDP6_DIR |
1555 BPCTLI_CTRL_EXT_SDP7_DIR |
1556 BPCTLI_CTRL_EXT_SDP6_DATA |
1557 BPCTLI_CTRL_EXT_SDP7_DATA);
1558 usec_delay(PULSE_INTERVAL);
1559 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1560 BPCTLI_CTRL_EXT_SDP6_DIR
1561 |
1562 BPCTLI_CTRL_EXT_SDP7_DIR
1563 |
1564 BPCTLI_CTRL_EXT_SDP6_DATA)
1565 &
1566 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1567 usec_delay(PULSE_INTERVAL);
1568 value--;
1569
1570 }
1571 usec_delay(INIT_CMND_INTERVAL - PULSE_INTERVAL);
1572 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1573 BPCTLI_CTRL_EXT_SDP6_DIR |
1574 BPCTLI_CTRL_EXT_SDP7_DIR) &
1575 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1576 BPCTLI_CTRL_EXT_SDP7_DATA)));
1577 usec_delay(WDT_TIME_CNT);
1578 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1579 pbpctl_dev->bypass_wdt_on_time = jiffies;
1580#ifdef BP_SYNC_FLAG
1581 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1582#else
1583 atomic_set(&pbpctl_dev->wdt_busy, 0);
1584#endif
1585
1586}
1587
01448bbb 1588static int send_wdt_pulse(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1589{
1590 uint32_t ctrl_ext = 0;
1591
1592#ifdef BP_SYNC_FLAG
1593 unsigned long flags;
1594
1595 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1596#else
1597
1598 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1599 return -1;
1600#endif
1601 wdt_time_left(pbpctl_dev);
1602 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1603
1604 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1605 BPCTLI_CTRL_EXT_SDP7_DIR |
1606 BPCTLI_CTRL_EXT_SDP7_DATA);
1607 usec_delay(PULSE_INTERVAL);
1608 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1609 BPCTLI_CTRL_EXT_SDP7_DIR) &
1610 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1611
1612 usec_delay(PULSE_INTERVAL);
1613 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1614 pbpctl_dev->bypass_wdt_on_time = jiffies;
1615#ifdef BP_SYNC_FLAG
1616 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1617#endif
1618
1619 return 0;
1620}
1621
01448bbb 1622void send_bypass_clear_pulse(bpctl_dev_t *pbpctl_dev, unsigned int value)
7040e556
D		 1623{
1624 uint32_t ctrl_ext = 0;
1625
1626 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1627 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1628 BPCTLI_CTRL_EXT_SDP6_DIR) &
1629 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1630
1631 usec_delay(PULSE_INTERVAL);
1632 while (value) {
1633 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1634 BPCTLI_CTRL_EXT_SDP6_DIR |
1635 BPCTLI_CTRL_EXT_SDP6_DATA);
1636 usec_delay(PULSE_INTERVAL);
1637 value--;
1638 }
1639 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1640 BPCTLI_CTRL_EXT_SDP6_DIR) &
1641 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1642 usec_delay(PULSE_INTERVAL);
1643}
1644
1645/* #endif OLD_FW */
1646#ifdef BYPASS_DEBUG
1647
01448bbb 1648int pulse_set_fn(bpctl_dev_t *pbpctl_dev, unsigned int counter)
7040e556
D		 1649{
1650 uint32_t ctrl_ext = 0;
1651
1652 if (!pbpctl_dev)
1653 return -1;
1654
1655 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1656 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1657
1658 pbpctl_dev->bypass_wdt_status = 0;
1659 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1660 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1661 } else {
1662 wdt_time_left(pbpctl_dev);
1663 if (pbpctl_dev->wdt_status == WDT_STATUS_EN) {
1664 pbpctl_dev->wdt_status = 0;
1665 data_pulse(pbpctl_dev, counter);
1666 pbpctl_dev->wdt_status = WDT_STATUS_EN;
1667 pbpctl_dev->bypass_wdt_on_time = jiffies;
1668
1669 } else
1670 data_pulse(pbpctl_dev, counter);
1671 }
1672
1673 return 0;
1674}
1675
01448bbb 1676int zero_set_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1677{
1678 uint32_t ctrl_ext = 0, ctrl_value = 0;
1679 if (!pbpctl_dev)
1680 return -1;
1681
1682 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1683 printk("zero_set");
1684
1685 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1686
1687 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1688 BPCTLI_CTRL_EXT_MCLK_DIR)
1689 &
1690 ~
1691 (BPCTLI_CTRL_EXT_MCLK_DATA
1692 |
1693 BPCTLI_CTRL_EXT_MDIO_DIR
1694 |
1695 BPCTLI_CTRL_EXT_MDIO_DATA)));
1696
1697 }
1698 return ctrl_value;
1699}
1700
1701int pulse_get2_fn(bpctl_dev_t * pbpctl_dev)
1702{
1703 uint32_t ctrl_ext = 0, ctrl_value = 0;
1704 if (!pbpctl_dev)
1705 return -1;
1706
1707 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1708 printk("pulse_get_fn\n");
1709 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1710 ctrl_value = read_pulse_2(pbpctl_dev, ctrl_ext);
1711 printk("read:%d\n", ctrl_value);
1712 }
1713 return ctrl_value;
1714}
1715
1716int pulse_get1_fn(bpctl_dev_t * pbpctl_dev)
1717{
1718 uint32_t ctrl_ext = 0, ctrl_value = 0;
1719 if (!pbpctl_dev)
1720 return -1;
1721
1722 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1723
1724 printk("pulse_get_fn\n");
1725
1726 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1727 ctrl_value = read_pulse_1(pbpctl_dev, ctrl_ext);
1728 printk("read:%d\n", ctrl_value);
1729 }
1730 return ctrl_value;
1731}
1732
1733int gpio6_set_fn(bpctl_dev_t * pbpctl_dev)
1734{
1735 uint32_t ctrl_ext = 0;
1736
1737 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1738 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1739 BPCTLI_CTRL_EXT_SDP6_DIR |
1740 BPCTLI_CTRL_EXT_SDP6_DATA);
1741 return 0;
1742}
1743
1744int gpio7_set_fn(bpctl_dev_t * pbpctl_dev)
1745{
1746 uint32_t ctrl_ext = 0;
1747
1748 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1749 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1750 BPCTLI_CTRL_EXT_SDP7_DIR |
1751 BPCTLI_CTRL_EXT_SDP7_DATA);
1752 return 0;
1753}
1754
1755int gpio7_clear_fn(bpctl_dev_t * pbpctl_dev)
1756{
1757 uint32_t ctrl_ext = 0;
1758
1759 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1760 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1761 BPCTLI_CTRL_EXT_SDP7_DIR) &
1762 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1763 return 0;
1764}
1765
1766int gpio6_clear_fn(bpctl_dev_t * pbpctl_dev)
1767{
1768 uint32_t ctrl_ext = 0;
1769
1770 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1771 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1772 BPCTLI_CTRL_EXT_SDP6_DIR) &
1773 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1774 return 0;
1775}
1776#endif /*BYPASS_DEBUG */
1777
1778static bpctl_dev_t *get_status_port_fn(bpctl_dev_t * pbpctl_dev)
1779{
1780 int idx_dev = 0;
1781
1782 if (pbpctl_dev == NULL)
1783 return NULL;
1784
1785 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
1786 for (idx_dev = 0;
1787 ((bpctl_dev_arr[idx_dev].pdev != NULL)
1788 && (idx_dev < device_num)); idx_dev++) {
1789 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
1790 && (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot)
1791 && ((bpctl_dev_arr[idx_dev].func == 1)
1792 && (pbpctl_dev->func == 0))) {
1793
1794 return (&(bpctl_dev_arr[idx_dev]));
1795 }
1796 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus) &&
1797 (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot) &&
1798 ((bpctl_dev_arr[idx_dev].func == 3)
1799 && (pbpctl_dev->func == 2))) {
1800
1801 return (&(bpctl_dev_arr[idx_dev]));
1802 }
1803 }
1804 }
1805 return NULL;
1806}
1807
1808static bpctl_dev_t *get_master_port_fn(bpctl_dev_t * pbpctl_dev)
1809{
1810 int idx_dev = 0;
1811
1812 if (pbpctl_dev == NULL)
1813 return NULL;
1814
1815 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3)) {
1816 for (idx_dev = 0;
1817 ((bpctl_dev_arr[idx_dev].pdev != NULL)
1818 && (idx_dev < device_num)); idx_dev++) {
1819 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
1820 && (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot)
1821 && ((bpctl_dev_arr[idx_dev].func == 0)
1822 && (pbpctl_dev->func == 1))) {
1823
1824 return (&(bpctl_dev_arr[idx_dev]));
1825 }
1826 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus) &&
1827 (bpctl_dev_arr[idx_dev].slot == pbpctl_dev->slot) &&
1828 ((bpctl_dev_arr[idx_dev].func == 2)
1829 && (pbpctl_dev->func == 3))) {
1830
1831 return (&(bpctl_dev_arr[idx_dev]));
1832 }
1833 }
1834 }
1835 return NULL;
1836}
1837
1838/**************************************/
1839/**************INTEL API***************/
1840/**************************************/
1841
1842static void write_data_port_int(bpctl_dev_t * pbpctl_dev,
1843 unsigned char ctrl_value)
1844{
1845 uint32_t value;
1846
1847 value = BPCTL_READ_REG(pbpctl_dev, CTRL);
1848/* Make SDP0 Pin Directonality to Output */
1849 value |= BPCTLI_CTRL_SDP0_DIR;
1850 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1851
1852 value &= ~BPCTLI_CTRL_SDP0_DATA;
1853 value |= ((ctrl_value & 0x1) << BPCTLI_CTRL_SDP0_SHIFT);
1854 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1855
1856 value = (BPCTL_READ_REG(pbpctl_dev, CTRL_EXT));
1857/* Make SDP2 Pin Directonality to Output */
1858 value |= BPCTLI_CTRL_EXT_SDP6_DIR;
1859 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1860
1861 value &= ~BPCTLI_CTRL_EXT_SDP6_DATA;
1862 value |= (((ctrl_value & 0x2) >> 1) << BPCTLI_CTRL_EXT_SDP6_SHIFT);
1863 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1864
1865}
1866
1867static int write_data_int(bpctl_dev_t * pbpctl_dev, unsigned char value)
1868{
1869 bpctl_dev_t *pbpctl_dev_b = NULL;
1870
1871 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
1872 return -1;
1873 atomic_set(&pbpctl_dev->wdt_busy, 1);
1874 write_data_port_int(pbpctl_dev, value & 0x3);
1875 write_data_port_int(pbpctl_dev_b, ((value & 0xc) >> 2));
1876 atomic_set(&pbpctl_dev->wdt_busy, 0);
1877
1878 return 0;
1879}
1880
1881static int wdt_pulse_int(bpctl_dev_t * pbpctl_dev)
1882{
1883
1884 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1885 return -1;
1886
1887 if ((write_data_int(pbpctl_dev, RESET_WDT_INT)) < 0)
1888 return -1;
1889 msec_delay_bp(CMND_INTERVAL_INT);
1890 if ((write_data_int(pbpctl_dev, CMND_OFF_INT)) < 0)
1891 return -1;
1892 msec_delay_bp(CMND_INTERVAL_INT);
1893
1894 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1895 pbpctl_dev->bypass_wdt_on_time = jiffies;
1896
1897 return 0;
1898}
1899
1900/*************************************/
1901/************* COMMANDS **************/
1902/*************************************/
1903
1904/* CMND_ON 0x4 (100)*/
1905int cmnd_on(bpctl_dev_t * pbpctl_dev)
1906{
1907 int ret = BP_NOT_CAP;
1908
1909 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1910 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
1911 return 0;
1912 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1913 write_data(pbpctl_dev, CMND_ON);
1914 else
1915 data_pulse(pbpctl_dev, CMND_ON);
1916 ret = 0;
1917 }
1918 return ret;
1919}
1920
1921/* CMND_OFF 0x2 (10)*/
1922int cmnd_off(bpctl_dev_t * pbpctl_dev)
1923{
1924 int ret = BP_NOT_CAP;
1925
1926 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1927 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1928 write_data_int(pbpctl_dev, CMND_OFF_INT);
1929 msec_delay_bp(CMND_INTERVAL_INT);
1930 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1931 write_data(pbpctl_dev, CMND_OFF);
1932 else
1933 data_pulse(pbpctl_dev, CMND_OFF);
1934 ret = 0;
1935 };
1936 return ret;
1937}
1938
1939/* BYPASS_ON (0xa)*/
1940int bypass_on(bpctl_dev_t * pbpctl_dev)
1941{
1942 int ret = BP_NOT_CAP;
1943
1944 if (pbpctl_dev->bp_caps & BP_CAP) {
1945 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1946 write_data_int(pbpctl_dev, BYPASS_ON_INT);
1947 msec_delay_bp(BYPASS_DELAY_INT);
1948 pbpctl_dev->bp_status_un = 0;
1949 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1950 write_data(pbpctl_dev, BYPASS_ON);
1951 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1952 msec_delay_bp(LATCH_DELAY);
1953 } else
1954 data_pulse(pbpctl_dev, BYPASS_ON);
1955 ret = 0;
1956 };
1957 return ret;
1958}
1959
1960/* BYPASS_OFF (0x8 111)*/
1961int bypass_off(bpctl_dev_t * pbpctl_dev)
1962{
1963 int ret = BP_NOT_CAP;
1964
1965 if (pbpctl_dev->bp_caps & BP_CAP) {
1966 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1967 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
1968 msec_delay_bp(BYPASS_DELAY_INT);
1969 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
1970 msec_delay_bp(BYPASS_DELAY_INT);
1971 pbpctl_dev->bp_status_un = 0;
1972 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1973 write_data(pbpctl_dev, BYPASS_OFF);
1974 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1975 msec_delay_bp(LATCH_DELAY);
1976 } else
1977 data_pulse(pbpctl_dev, BYPASS_OFF);
1978 ret = 0;
1979 }
1980 return ret;
1981}
1982
1983/* TAP_OFF (0x9)*/
1984int tap_off(bpctl_dev_t * pbpctl_dev)
1985{
1986 int ret = BP_NOT_CAP;
1987 if ((pbpctl_dev->bp_caps & TAP_CAP)
1988 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1989 write_data(pbpctl_dev, TAP_OFF);
1990 msec_delay_bp(LATCH_DELAY);
1991 ret = 0;
1992 };
1993 return ret;
1994}
1995
1996/* TAP_ON (0xb)*/
1997int tap_on(bpctl_dev_t * pbpctl_dev)
1998{
1999 int ret = BP_NOT_CAP;
2000 if ((pbpctl_dev->bp_caps & TAP_CAP)
2001 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
2002 write_data(pbpctl_dev, TAP_ON);
2003 msec_delay_bp(LATCH_DELAY);
2004 ret = 0;
2005 };
2006 return ret;
2007}
2008
2009/* DISC_OFF (0x9)*/
2010int disc_off(bpctl_dev_t * pbpctl_dev)
2011{
2012 int ret = 0;
2013 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
2014 write_data(pbpctl_dev, DISC_OFF);
2015 msec_delay_bp(LATCH_DELAY);
2016 } else
2017 ret = BP_NOT_CAP;
2018 return ret;
2019}
2020
2021/* DISC_ON (0xb)*/
2022int disc_on(bpctl_dev_t * pbpctl_dev)
2023{
2024 int ret = 0;
2025 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
2026 write_data(pbpctl_dev, /*DISC_ON */ 0x85);
2027 msec_delay_bp(LATCH_DELAY);
2028 } else
2029 ret = BP_NOT_CAP;
2030 return ret;
2031}
2032
2033/* DISC_PORT_ON */
2034int disc_port_on(bpctl_dev_t * pbpctl_dev)
2035{
2036 int ret = 0;
2037 bpctl_dev_t *pbpctl_dev_m;
2038
2039 if ((is_bypass_fn(pbpctl_dev)) == 1)
2040 pbpctl_dev_m = pbpctl_dev;
2041 else
2042 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2043 if (pbpctl_dev_m == NULL)
2044 return BP_NOT_CAP;
2045
2046 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2047 if (is_bypass_fn(pbpctl_dev) == 1) {
2048
2049 write_data(pbpctl_dev_m, TX_DISA);
2050 } else {
2051
2052 write_data(pbpctl_dev_m, TX_DISB);
2053 }
2054
2055 msec_delay_bp(LATCH_DELAY);
2056
2057 }
2058 return ret;
2059}
2060
2061/* DISC_PORT_OFF */
2062int disc_port_off(bpctl_dev_t * pbpctl_dev)
2063{
2064 int ret = 0;
2065 bpctl_dev_t *pbpctl_dev_m;
2066
2067 if ((is_bypass_fn(pbpctl_dev)) == 1)
2068 pbpctl_dev_m = pbpctl_dev;
2069 else
2070 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2071 if (pbpctl_dev_m == NULL)
2072 return BP_NOT_CAP;
2073
2074 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2075 if (is_bypass_fn(pbpctl_dev) == 1)
2076 write_data(pbpctl_dev_m, TX_ENA);
2077 else
2078 write_data(pbpctl_dev_m, TX_ENB);
2079
2080 msec_delay_bp(LATCH_DELAY);
2081
2082 }
2083 return ret;
2084}
2085
2086/*TWO_PORT_LINK_HW_EN (0xe)*/
2087int tpl_hw_on(bpctl_dev_t * pbpctl_dev)
2088{
2089 int ret = 0, ctrl = 0;
2090 bpctl_dev_t *pbpctl_dev_b = NULL;
2091
2092 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
2093 return BP_NOT_CAP;
2094
2095 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
2096 cmnd_on(pbpctl_dev);
2097 write_data(pbpctl_dev, TPL2_ON);
2098 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2099 cmnd_off(pbpctl_dev);
2100 return ret;
2101 }
2102
2103 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2104 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2105 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2106 ((ctrl | BPCTLI_CTRL_SWDPIO0) &
2107 ~BPCTLI_CTRL_SWDPIN0));
2108 } else
2109 ret = BP_NOT_CAP;
2110 return ret;
2111}
2112
2113/*TWO_PORT_LINK_HW_DIS (0xc)*/
2114int tpl_hw_off(bpctl_dev_t * pbpctl_dev)
2115{
2116 int ret = 0, ctrl = 0;
2117 bpctl_dev_t *pbpctl_dev_b = NULL;
2118
2119 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
2120 return BP_NOT_CAP;
2121 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
2122 cmnd_on(pbpctl_dev);
2123 write_data(pbpctl_dev, TPL2_OFF);
2124 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2125 cmnd_off(pbpctl_dev);
2126 return ret;
2127 }
2128 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2129 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2130 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2131 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2132 BPCTLI_CTRL_SWDPIN0));
2133 } else
2134 ret = BP_NOT_CAP;
2135 return ret;
2136}
2137
2138/* WDT_OFF (0x6 110)*/
2139int wdt_off(bpctl_dev_t * pbpctl_dev)
2140{
2141 int ret = BP_NOT_CAP;
2142
2143 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2144 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2145 bypass_off(pbpctl_dev);
2146 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2147 write_data(pbpctl_dev, WDT_OFF);
2148 else
2149 data_pulse(pbpctl_dev, WDT_OFF);
2150 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
2151 ret = 0;
2152 };
2153 return ret;
2154}
2155
2156/* WDT_ON (0x10)*/
2157
2158/***Global***/
2159static unsigned int
2160 wdt_val_array[] = { 1000, 1500, 2000, 3000, 4000, 8000, 16000, 32000, 0 };
2161
2162int wdt_on(bpctl_dev_t * pbpctl_dev, unsigned int timeout)
2163{
2164
2165 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2166 unsigned int pulse = 0, temp_value = 0, temp_cnt = 0;
2167 pbpctl_dev->wdt_status = 0;
2168
2169 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2170 for (; wdt_val_array[temp_cnt]; temp_cnt++)
2171 if (timeout <= wdt_val_array[temp_cnt])
2172 break;
2173
2174 if (!wdt_val_array[temp_cnt])
2175 temp_cnt--;
2176
2177 timeout = wdt_val_array[temp_cnt];
2178 temp_cnt += 0x7;
2179
2180 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2181 msec_delay_bp(BYPASS_DELAY_INT);
2182 pbpctl_dev->bp_status_un = 0;
2183 write_data_int(pbpctl_dev, temp_cnt);
2184 pbpctl_dev->bypass_wdt_on_time = jiffies;
2185 msec_delay_bp(CMND_INTERVAL_INT);
2186 pbpctl_dev->bypass_timer_interval = timeout;
2187 } else {
2188 timeout =
2189 (timeout <
2190 TIMEOUT_UNIT ? TIMEOUT_UNIT : (timeout >
2191 WDT_TIMEOUT_MAX ?
2192 WDT_TIMEOUT_MAX :
2193 timeout));
2194 temp_value = timeout / 100;
2195 while ((temp_value >>= 1))
2196 temp_cnt++;
2197 if (timeout > ((1 << temp_cnt) * 100))
2198 temp_cnt++;
2199 pbpctl_dev->bypass_wdt_on_time = jiffies;
2200 pulse = (WDT_ON | temp_cnt);
2201 if (pbpctl_dev->bp_ext_ver == OLD_IF_VER)
2202 data_pulse(pbpctl_dev, pulse);
2203 else
2204 write_data(pbpctl_dev, pulse);
2205 pbpctl_dev->bypass_timer_interval =
2206 (1 << temp_cnt) * 100;
2207 }
2208 pbpctl_dev->wdt_status = WDT_STATUS_EN;
2209 return 0;
2210 }
2211 return BP_NOT_CAP;
2212}
2213
2214void bp75_put_hw_semaphore_generic(bpctl_dev_t * pbpctl_dev)
2215{
2216 u32 swsm;
2217
2218 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2219
2220 swsm &= ~(BPCTLI_SWSM_SMBI | BPCTLI_SWSM_SWESMBI);
2221
2222 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm);
2223}
2224
2225s32 bp75_get_hw_semaphore_generic(bpctl_dev_t * pbpctl_dev)
2226{
2227 u32 swsm;
2228 s32 ret_val = 0;
2229 s32 timeout = 8192 + 1;
2230 s32 i = 0;
2231
2232 /* Get the SW semaphore */
2233 while (i < timeout) {
2234 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2235 if (!(swsm & BPCTLI_SWSM_SMBI))
2236 break;
2237
2238 usec_delay(50);
2239 i++;
2240 }
2241
2242 if (i == timeout) {
2243 printk
2244 ("bpctl_mod: Driver can't access device - SMBI bit is set.\n");
2245 ret_val = -1;
2246 goto out;
2247 }
2248
2249 /* Get the FW semaphore. */
2250 for (i = 0; i < timeout; i++) {
2251 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2252 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm | BPCTLI_SWSM_SWESMBI);
2253
2254 /* Semaphore acquired if bit latched */
2255 if (BPCTL_READ_REG(pbpctl_dev, SWSM) & BPCTLI_SWSM_SWESMBI)
2256 break;
2257
2258 usec_delay(50);
2259 }
2260
2261 if (i == timeout) {
2262 /* Release semaphores */
2263 bp75_put_hw_semaphore_generic(pbpctl_dev);
2264 printk("bpctl_mod: Driver can't access the NVM\n");
2265 ret_val = -1;
2266 goto out;
2267 }
2268
2269 out:
2270 return ret_val;
2271}
2272
2273static void bp75_release_phy(bpctl_dev_t * pbpctl_dev)
2274{
2275 u16 mask = BPCTLI_SWFW_PHY0_SM;
2276 u32 swfw_sync;
2277
2278 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2279 mask = BPCTLI_SWFW_PHY1_SM;
2280
2281 while (bp75_get_hw_semaphore_generic(pbpctl_dev) != 0) ;
2282 /* Empty */
2283
2284 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2285 swfw_sync &= ~mask;
2286 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2287
2288 bp75_put_hw_semaphore_generic(pbpctl_dev);
2289}
2290
2291static s32 bp75_acquire_phy(bpctl_dev_t * pbpctl_dev)
2292{
2293 u16 mask = BPCTLI_SWFW_PHY0_SM;
2294 u32 swfw_sync;
2295 u32 swmask;
2296 u32 fwmask;
2297 s32 ret_val = 0;
2298 s32 i = 0, timeout = 200;
2299
2300 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2301 mask = BPCTLI_SWFW_PHY1_SM;
2302
2303 swmask = mask;
2304 fwmask = mask << 16;
2305
2306 while (i < timeout) {
2307 if (bp75_get_hw_semaphore_generic(pbpctl_dev)) {
2308 ret_val = -1;
2309 goto out;
2310 }
2311
2312 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2313 if (!(swfw_sync & (fwmask | swmask)))
2314 break;
2315
2316 bp75_put_hw_semaphore_generic(pbpctl_dev);
2317 mdelay(5);
2318 i++;
2319 }
2320
2321 if (i == timeout) {
2322 printk
2323 ("bpctl_mod: Driver can't access resource, SW_FW_SYNC timeout.\n");
2324 ret_val = -1;
2325 goto out;
2326 }
2327
2328 swfw_sync |= swmask;
2329 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2330
2331 bp75_put_hw_semaphore_generic(pbpctl_dev);
2332
2333 out:
2334 return ret_val;
2335}
2336
2337s32 bp75_read_phy_reg_mdic(bpctl_dev_t * pbpctl_dev, u32 offset, u16 * data)
2338{
2339 u32 i, mdic = 0;
2340 s32 ret_val = 0;
2341 u32 phy_addr = 1;
2342
2343 mdic = ((offset << BPCTLI_MDIC_REG_SHIFT) |
2344 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_READ));
2345
2346 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2347
2348 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2349 usec_delay(50);
2350 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2351 if (mdic & BPCTLI_MDIC_READY)
2352 break;
2353 }
2354 if (!(mdic & BPCTLI_MDIC_READY)) {
2355 printk("bpctl_mod: MDI Read did not complete\n");
2356 ret_val = -1;
2357 goto out;
2358 }
2359 if (mdic & BPCTLI_MDIC_ERROR) {
2360 printk("bpctl_mod: MDI Error\n");
2361 ret_val = -1;
2362 goto out;
2363 }
2364 *data = (u16) mdic;
2365
2366 out:
2367 return ret_val;
2368}
2369
2370s32 bp75_write_phy_reg_mdic(bpctl_dev_t * pbpctl_dev, u32 offset, u16 data)
2371{
2372 u32 i, mdic = 0;
2373 s32 ret_val = 0;
2374 u32 phy_addr = 1;
2375
2376 mdic = (((u32) data) |
2377 (offset << BPCTLI_MDIC_REG_SHIFT) |
2378 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_WRITE));
2379
2380 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2381
2382 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2383 usec_delay(50);
2384 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2385 if (mdic & BPCTLI_MDIC_READY)
2386 break;
2387 }
2388 if (!(mdic & BPCTLI_MDIC_READY)) {
2389 printk("bpctl_mod: MDI Write did not complete\n");
2390 ret_val = -1;
2391 goto out;
2392 }
2393 if (mdic & BPCTLI_MDIC_ERROR) {
2394 printk("bpctl_mod: MDI Error\n");
2395 ret_val = -1;
2396 goto out;
2397 }
2398
2399 out:
2400 return ret_val;
2401}
2402
2403static s32 bp75_read_phy_reg(bpctl_dev_t * pbpctl_dev, u32 offset, u16 * data)
2404{
2405 s32 ret_val = 0;
2406
2407 ret_val = bp75_acquire_phy(pbpctl_dev);
2408 if (ret_val)
2409 goto out;
2410
2411 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2412 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2413 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2414 (u16) offset);
2415 if (ret_val)
2416 goto release;
2417 }
2418
2419 ret_val =
2420 bp75_read_phy_reg_mdic(pbpctl_dev,
2421 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2422
2423 release:
2424 bp75_release_phy(pbpctl_dev);
2425 out:
2426 return ret_val;
2427}
2428
2429static s32 bp75_write_phy_reg(bpctl_dev_t * pbpctl_dev, u32 offset, u16 data)
2430{
2431 s32 ret_val = 0;
2432
2433 ret_val = bp75_acquire_phy(pbpctl_dev);
2434 if (ret_val)
2435 goto out;
2436
2437 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2438 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2439 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2440 (u16) offset);
2441 if (ret_val)
2442 goto release;
2443 }
2444
2445 ret_val =
2446 bp75_write_phy_reg_mdic(pbpctl_dev,
2447 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2448
2449 release:
2450 bp75_release_phy(pbpctl_dev);
2451
2452 out:
2453 return ret_val;
2454}
2455
2456/* SET_TX (non-Bypass command :)) */
2457static int set_tx(bpctl_dev_t * pbpctl_dev, int tx_state)
2458{
2459 int ret = 0, ctrl = 0;
2460 bpctl_dev_t *pbpctl_dev_m;
2461 if ((is_bypass_fn(pbpctl_dev)) == 1)
2462 pbpctl_dev_m = pbpctl_dev;
2463 else
2464 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2465 if (pbpctl_dev_m == NULL)
2466 return BP_NOT_CAP;
2467 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2468 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2469 if (!tx_state) {
2470 if (pbpctl_dev->bp_540) {
2471 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2472 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2473 (ctrl | BP10G_SDP1_DIR |
2474 BP10G_SDP1_DATA));
2475
2476 } else {
2477 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2478 (ctrl | BPCTLI_CTRL_SDP1_DIR
2479 | BPCTLI_CTRL_SWDPIN1));
2480 }
2481 } else {
2482 if (pbpctl_dev->bp_540) {
2483 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2484 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2485 ((ctrl | BP10G_SDP1_DIR) &
2486 ~BP10G_SDP1_DATA));
2487 } else {
2488 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2489 ((ctrl |
2490 BPCTLI_CTRL_SDP1_DIR) &
2491 ~BPCTLI_CTRL_SWDPIN1));
2492 }
2493 return ret;
2494
2495 }
2496 } else if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
2497 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
2498 if (tx_state) {
2499 uint16_t mii_reg;
2500 if (!
2501 (ret =
2502 bp75_read_phy_reg(pbpctl_dev,
2503 BPCTLI_PHY_CONTROL,
2504 &mii_reg))) {
2505 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN) {
2506 ret =
2507 bp75_write_phy_reg
2508 (pbpctl_dev,
2509 BPCTLI_PHY_CONTROL,
2510 mii_reg &
2511 ~BPCTLI_MII_CR_POWER_DOWN);
2512 }
2513 }
2514 } else {
2515 uint16_t mii_reg;
2516 if (!
2517 (ret =
2518 bp75_read_phy_reg(pbpctl_dev,
2519 BPCTLI_PHY_CONTROL,
2520 &mii_reg))) {
2521
2522 mii_reg |= BPCTLI_MII_CR_POWER_DOWN;
2523 ret =
2524 bp75_write_phy_reg(pbpctl_dev,
2525 BPCTLI_PHY_CONTROL,
2526 mii_reg);
2527 }
2528 }
2529
2530 }
2531 if (pbpctl_dev->bp_fiber5) {
2532 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
2533
2534 } else if (pbpctl_dev->bp_10gb)
2535 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
2536
2537 else if (!pbpctl_dev->bp_10g)
2538 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2539 else
2540 //ctrl =readl((void *)((pbpctl_dev)->mem_map) + 0x20);
2541 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2542
2543 if (!tx_state)
2544 if (pbpctl_dev->bp_10g9) {
2545 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2546 (ctrl | BP10G_SDP3_DATA |
2547 BP10G_SDP3_DIR));
2548
2549 } else if (pbpctl_dev->bp_fiber5) {
2550 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2551 (ctrl |
2552 BPCTLI_CTRL_EXT_SDP6_DIR |
2553 BPCTLI_CTRL_EXT_SDP6_DATA));
2554
2555 } else if (pbpctl_dev->bp_10gb) {
2556 if ((pbpctl_dev->func == 1)
2557 || (pbpctl_dev->func == 3))
2558 BP10GB_WRITE_REG(pbpctl_dev,
2559 MISC_REG_GPIO,
2560 (ctrl |
2561 BP10GB_GPIO0_SET_P1) &
2562 ~(BP10GB_GPIO0_CLR_P1 |
2563 BP10GB_GPIO0_OE_P1));
2564 else
2565 BP10GB_WRITE_REG(pbpctl_dev,
2566 MISC_REG_GPIO,
2567 (ctrl |
2568 BP10GB_GPIO0_OE_P0 |
2569 BP10GB_GPIO0_SET_P0));
2570
2571 } else if (pbpctl_dev->bp_i80) {
2572 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2573 (ctrl | BPCTLI_CTRL_SDP1_DIR
2574 | BPCTLI_CTRL_SWDPIN1));
2575
2576 } else if (pbpctl_dev->bp_540) {
2577 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2578 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2579 (ctrl | BP10G_SDP1_DIR |
2580 BP10G_SDP1_DATA));
2581
2582 }
2583
2584 else if (!pbpctl_dev->bp_10g)
2585 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2586 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2587 BPCTLI_CTRL_SWDPIN0));
2588
2589 else
2590 //writel((ctrl|(0x1|0x100)), (void *)(((pbpctl_dev)->mem_map) + 0x20)) ;
2591 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2592 (ctrl | BP10G_SDP0_DATA |
2593 BP10G_SDP0_DIR));
2594
2595 else {
2596 if (pbpctl_dev->bp_10g9) {
2597 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2598 ((ctrl | BP10G_SDP3_DIR) &
2599 ~BP10G_SDP3_DATA));
2600
2601 } else if (pbpctl_dev->bp_fiber5) {
2602 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2603 ((ctrl |
2604 BPCTLI_CTRL_EXT_SDP6_DIR) &
2605 ~BPCTLI_CTRL_EXT_SDP6_DATA));
2606
2607 } else if (pbpctl_dev->bp_10gb) {
2608 if ((bpctl_dev_arr->func == 1)
2609 || (bpctl_dev_arr->func == 3))
2610 BP10GB_WRITE_REG(pbpctl_dev,
2611 MISC_REG_GPIO,
2612 (ctrl |
2613 BP10GB_GPIO0_CLR_P1) &
2614 ~(BP10GB_GPIO0_SET_P1 |
2615 BP10GB_GPIO0_OE_P1));
2616 else
2617 BP10GB_WRITE_REG(pbpctl_dev,
2618 MISC_REG_GPIO,
2619 (ctrl |
2620 BP10GB_GPIO0_OE_P0 |
2621 BP10GB_GPIO0_CLR_P0));
2622
2623 } else if (pbpctl_dev->bp_i80) {
2624 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2625 ((ctrl |
2626 BPCTLI_CTRL_SDP1_DIR) &
2627 ~BPCTLI_CTRL_SWDPIN1));
2628 } else if (pbpctl_dev->bp_540) {
2629 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2630 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2631 ((ctrl | BP10G_SDP1_DIR) &
2632 ~BP10G_SDP1_DATA));
2633 }
2634
2635 else if (!pbpctl_dev->bp_10g) {
2636 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2637 ((ctrl | BPCTLI_CTRL_SWDPIO0)
2638 & ~BPCTLI_CTRL_SWDPIN0));
2639 if (!PEGF_IF_SERIES(pbpctl_dev->subdevice)) {
2640 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2641 (ctrl &
2642 ~
2643 (BPCTLI_CTRL_SDP0_DATA
2644 |
2645 BPCTLI_CTRL_SDP0_DIR)));
2646 }
2647 } else
2648 //writel(((ctrl|0x100)&~0x1), (void *)(((pbpctl_dev)->mem_map) + 0x20)) ;
2649 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2650 ((ctrl | BP10G_SDP0_DIR) &
2651 ~BP10G_SDP0_DATA));
2652
2653 }
2654
2655 } else
2656 ret = BP_NOT_CAP;
2657 return ret;
2658
2659}
2660
2661/* SET_FORCE_LINK (non-Bypass command :)) */
2662static int set_bp_force_link(bpctl_dev_t * pbpctl_dev, int tx_state)
2663{
2664 int ret = 0, ctrl = 0;
2665
2666 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
2667
2668 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
2669
2670 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2671 if (!tx_state)
2672 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2673 ctrl & ~BP10G_SDP1_DIR);
2674 else
2675 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2676 ((ctrl | BP10G_SDP1_DIR) &
2677 ~BP10G_SDP1_DATA));
2678 return ret;
2679 }
2680
2681 }
2682 return BP_NOT_CAP;
2683}
2684
2685/*RESET_CONT 0x20 */
2686int reset_cont(bpctl_dev_t * pbpctl_dev)
2687{
2688 int ret = BP_NOT_CAP;
2689
2690 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2691 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2692 return BP_NOT_CAP;
2693 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2694 write_data(pbpctl_dev, RESET_CONT);
2695 else
2696 data_pulse(pbpctl_dev, RESET_CONT);
2697 ret = 0;
2698 };
2699 return ret;
2700}
2701
2702/*DIS_BYPASS_CAP 0x22 */
2703int dis_bypass_cap(bpctl_dev_t * pbpctl_dev)
2704{
2705
2706 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2707 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2708 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2709 msec_delay_bp(BYPASS_DELAY_INT);
2710 } else {
2711 write_data(pbpctl_dev, BYPASS_OFF);
2712 msec_delay_bp(LATCH_DELAY);
2713 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2714 msec_delay_bp(BYPASS_CAP_DELAY);
2715 }
2716 return 0;
2717 }
2718 return BP_NOT_CAP;
2719}
2720
2721/*EN_BYPASS_CAP 0x24 */
2722int en_bypass_cap(bpctl_dev_t * pbpctl_dev)
2723{
2724 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2725 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2726 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2727 msec_delay_bp(BYPASS_DELAY_INT);
2728 } else {
2729 write_data(pbpctl_dev, EN_BYPASS_CAP);
2730 msec_delay_bp(BYPASS_CAP_DELAY);
2731 }
2732 return 0;
2733 }
2734 return BP_NOT_CAP;
2735}
2736
2737/* BYPASS_STATE_PWRON 0x26*/
2738int bypass_state_pwron(bpctl_dev_t * pbpctl_dev)
2739{
2740 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2741 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2742 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2743 msec_delay_bp(DFLT_PWRON_DELAY);
2744 else
2745 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2746 return 0;
2747 }
2748 return BP_NOT_CAP;
2749}
2750
2751/* NORMAL_STATE_PWRON 0x28*/
2752int normal_state_pwron(bpctl_dev_t * pbpctl_dev)
2753{
2754 if ((pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP)
2755 || (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)) {
2756 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2757 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2758 msec_delay_bp(DFLT_PWRON_DELAY);
2759 else
2760 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2761 return 0;
2762 }
2763 return BP_NOT_CAP;
2764}
2765
2766/* BYPASS_STATE_PWROFF 0x27*/
2767int bypass_state_pwroff(bpctl_dev_t * pbpctl_dev)
2768{
2769 if (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP) {
2770 write_data(pbpctl_dev, BYPASS_STATE_PWROFF);
2771 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2772 return 0;
2773 }
2774 return BP_NOT_CAP;
2775}
2776
2777/* NORMAL_STATE_PWROFF 0x29*/
2778int normal_state_pwroff(bpctl_dev_t * pbpctl_dev)
2779{
2780 if ((pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
2781 write_data(pbpctl_dev, NORMAL_STATE_PWROFF);
2782 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2783 return 0;
2784 }
2785 return BP_NOT_CAP;
2786}
2787
2788/*TAP_STATE_PWRON 0x2a*/
2789int tap_state_pwron(bpctl_dev_t * pbpctl_dev)
2790{
2791 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2792 write_data(pbpctl_dev, TAP_STATE_PWRON);
2793 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2794 return 0;
2795 }
2796 return BP_NOT_CAP;
2797}
2798
2799/*DIS_TAP_CAP 0x2c*/
2800int dis_tap_cap(bpctl_dev_t * pbpctl_dev)
2801{
2802 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2803 write_data(pbpctl_dev, DIS_TAP_CAP);
2804 msec_delay_bp(BYPASS_CAP_DELAY);
2805 return 0;
2806 }
2807 return BP_NOT_CAP;
2808}
2809
2810/*EN_TAP_CAP 0x2e*/
2811int en_tap_cap(bpctl_dev_t * pbpctl_dev)
2812{
2813 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2814 write_data(pbpctl_dev, EN_TAP_CAP);
2815 msec_delay_bp(BYPASS_CAP_DELAY);
2816 return 0;
2817 }
2818 return BP_NOT_CAP;
2819}
2820
2821/*DISC_STATE_PWRON 0x2a*/
2822int disc_state_pwron(bpctl_dev_t * pbpctl_dev)
2823{
2824 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
2825 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2826 write_data(pbpctl_dev, DISC_STATE_PWRON);
2827 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2828 return BP_OK;
2829 }
2830 }
2831 return BP_NOT_CAP;
2832}
2833
2834/*DIS_DISC_CAP 0x2c*/
2835int dis_disc_cap(bpctl_dev_t * pbpctl_dev)
2836{
2837 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2838 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2839 write_data(pbpctl_dev, DIS_DISC_CAP);
2840 msec_delay_bp(BYPASS_CAP_DELAY);
2841 return BP_OK;
2842 }
2843 }
2844 return BP_NOT_CAP;
2845}
2846
2847/*DISC_STATE_PWRON 0x2a*/
2848int disc_port_state_pwron(bpctl_dev_t * pbpctl_dev)
2849{
2850 int ret = 0;
2851 bpctl_dev_t *pbpctl_dev_m;
2852
2853 return BP_NOT_CAP;
2854
2855 if ((is_bypass_fn(pbpctl_dev)) == 1)
2856 pbpctl_dev_m = pbpctl_dev;
2857 else
2858 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2859 if (pbpctl_dev_m == NULL)
2860 return BP_NOT_CAP;
2861
2862 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2863 if (is_bypass_fn(pbpctl_dev) == 1)
2864 write_data(pbpctl_dev_m, TX_DISA_PWRUP);
2865 else
2866 write_data(pbpctl_dev_m, TX_DISB_PWRUP);
2867
2868 msec_delay_bp(LATCH_DELAY);
2869
2870 }
2871 return ret;
2872}
2873
2874int normal_port_state_pwron(bpctl_dev_t * pbpctl_dev)
2875{
2876 int ret = 0;
2877 bpctl_dev_t *pbpctl_dev_m;
2878 return BP_NOT_CAP;
2879
2880 if ((is_bypass_fn(pbpctl_dev)) == 1)
2881 pbpctl_dev_m = pbpctl_dev;
2882 else
2883 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2884 if (pbpctl_dev_m == NULL)
2885 return BP_NOT_CAP;
2886
2887 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2888 if (is_bypass_fn(pbpctl_dev) == 1)
2889 write_data(pbpctl_dev_m, TX_ENA_PWRUP);
2890 else
2891 write_data(pbpctl_dev_m, TX_ENB_PWRUP);
2892
2893 msec_delay_bp(LATCH_DELAY);
2894
2895 }
2896 return ret;
2897}
2898
2899/*EN_TAP_CAP 0x2e*/
2900int en_disc_cap(bpctl_dev_t * pbpctl_dev)
2901{
2902 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2903 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2904 write_data(pbpctl_dev, EN_DISC_CAP);
2905 msec_delay_bp(BYPASS_CAP_DELAY);
2906 return BP_OK;
2907 }
2908 }
2909 return BP_NOT_CAP;
2910}
2911
2912int std_nic_on(bpctl_dev_t * pbpctl_dev)
2913{
2914
2915 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2916
2917 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2918 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2919 msec_delay_bp(BYPASS_DELAY_INT);
2920 pbpctl_dev->bp_status_un = 0;
2921 return BP_OK;
2922 }
2923
2924 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2925 write_data(pbpctl_dev, STD_NIC_ON);
2926 msec_delay_bp(BYPASS_CAP_DELAY);
2927 return BP_OK;
2928
2929 }
2930
2931 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2932 wdt_off(pbpctl_dev);
2933
2934 if (pbpctl_dev->bp_caps & BP_CAP) {
2935 write_data(pbpctl_dev, BYPASS_OFF);
2936 msec_delay_bp(LATCH_DELAY);
2937 }
2938
2939 if (pbpctl_dev->bp_caps & TAP_CAP) {
2940 write_data(pbpctl_dev, TAP_OFF);
2941 msec_delay_bp(LATCH_DELAY);
2942 }
2943
2944 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2945 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2946 msec_delay_bp(DFLT_PWRON_DELAY);
2947 else
2948 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2949
2950 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2951 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2952 msec_delay_bp(BYPASS_CAP_DELAY);
2953 }
2954
2955 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2956 write_data(pbpctl_dev, DIS_TAP_CAP);
2957 msec_delay_bp(BYPASS_CAP_DELAY);
2958
2959 }
2960 return 0;
2961 }
2962 }
2963 return BP_NOT_CAP;
2964}
2965
2966int std_nic_off(bpctl_dev_t * pbpctl_dev)
2967{
2968
2969 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2970 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2971 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2972 msec_delay_bp(BYPASS_DELAY_INT);
2973 return BP_OK;
2974 }
2975 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2976 write_data(pbpctl_dev, STD_NIC_OFF);
2977 msec_delay_bp(BYPASS_CAP_DELAY);
2978 return BP_OK;
2979
2980 }
2981
2982 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2983
2984 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2985 write_data(pbpctl_dev, TAP_STATE_PWRON);
2986 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2987 }
2988
2989 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2990 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2991 if (pbpctl_dev->bp_ext_ver > PXG2BPI_VER)
2992 msec_delay_bp(LATCH_DELAY +
2993 EEPROM_WR_DELAY);
2994 else
2995 msec_delay_bp(DFLT_PWRON_DELAY);
2996 }
2997
2998 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2999 write_data(pbpctl_dev, EN_TAP_CAP);
3000 msec_delay_bp(BYPASS_CAP_DELAY);
3001 }
3002 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
3003 write_data(pbpctl_dev, EN_DISC_CAP);
3004 msec_delay_bp(BYPASS_CAP_DELAY);
3005 }
3006
3007 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
3008 write_data(pbpctl_dev, EN_BYPASS_CAP);
3009 msec_delay_bp(BYPASS_CAP_DELAY);
3010 }
3011
3012 return 0;
3013 }
3014 }
3015 return BP_NOT_CAP;
3016}
3017
3018int wdt_time_left(bpctl_dev_t * pbpctl_dev)
3019{
3020
3021 //unsigned long curr_time=((long long)(jiffies*1000))/HZ, delta_time=0,wdt_on_time=((long long)(pbpctl_dev->bypass_wdt_on_time*1000))/HZ;
3022 unsigned long curr_time = jiffies, delta_time = 0, wdt_on_time =
3023 pbpctl_dev->bypass_wdt_on_time, delta_time_msec = 0;
3024 int time_left = 0;
3025
3026 switch (pbpctl_dev->wdt_status) {
3027 case WDT_STATUS_DIS:
3028 time_left = 0;
3029 break;
3030 case WDT_STATUS_EN:
3031 delta_time =
3032 (curr_time >=
3033 wdt_on_time) ? (curr_time - wdt_on_time) : (~wdt_on_time +
3034 curr_time);
3035 delta_time_msec = jiffies_to_msecs(delta_time);
3036 time_left = pbpctl_dev->bypass_timer_interval - delta_time_msec;
3037 if (time_left < 0) {
3038 time_left = -1;
3039 pbpctl_dev->wdt_status = WDT_STATUS_EXP;
3040 }
3041 break;
3042 case WDT_STATUS_EXP:
3043 time_left = -1;
3044 break;
3045 }
3046
3047 return time_left;
3048}
3049
3050static int wdt_timer(bpctl_dev_t * pbpctl_dev, int *time_left)
3051{
3052 int ret = 0;
3053 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3054 {
3055 if (pbpctl_dev->wdt_status == WDT_STATUS_UNKNOWN)
3056 ret = BP_NOT_CAP;
3057 else
3058 *time_left = wdt_time_left(pbpctl_dev);
3059 }
3060
3061 } else
3062 ret = BP_NOT_CAP;
3063 return ret;
3064}
3065
3066static int wdt_timer_reload(bpctl_dev_t * pbpctl_dev)
3067{
3068
3069 int ret = 0;
3070
3071 if ((pbpctl_dev->bp_caps & WD_CTL_CAP) &&
3072 (pbpctl_dev->wdt_status != WDT_STATUS_UNKNOWN)) {
3073 if (pbpctl_dev->wdt_status == WDT_STATUS_DIS)
3074 return 0;
3075 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
3076 ret = wdt_pulse(pbpctl_dev);
3077 else if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
3078 ret = wdt_pulse_int(pbpctl_dev);
3079 else
3080 ret = send_wdt_pulse(pbpctl_dev);
3081 //if (ret==-1)
3082 // mod_timer(&pbpctl_dev->bp_timer, jiffies+1);
3083 return 1;
3084 }
3085 return BP_NOT_CAP;
3086}
3087
3088static void wd_reset_timer(unsigned long param)
3089{
3090 bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
3091#ifdef BP_SELF_TEST
3092 struct sk_buff *skb_tmp;
3093#endif
3094
3095 if ((pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) &&
3096 ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)) {
3097 mod_timer(&pbpctl_dev->bp_timer, jiffies + 1);
3098 return;
3099 }
3100#ifdef BP_SELF_TEST
3101
3102 if (pbpctl_dev->bp_self_test_flag == 1) {
3103 skb_tmp = dev_alloc_skb(BPTEST_DATA_LEN + 2);
3104 if ((skb_tmp) && (pbpctl_dev->ndev) && (pbpctl_dev->bp_tx_data)) {
3105 memcpy(skb_put(skb_tmp, BPTEST_DATA_LEN),
3106 pbpctl_dev->bp_tx_data, BPTEST_DATA_LEN);
3107 skb_tmp->dev = pbpctl_dev->ndev;
3108 skb_tmp->protocol =
3109 eth_type_trans(skb_tmp, pbpctl_dev->ndev);
3110 skb_tmp->ip_summed = CHECKSUM_UNNECESSARY;
3111 netif_receive_skb(skb_tmp);
3112 goto bp_timer_reload;
3113 return;
3114 }
3115 }
3116#endif
3117
3118 wdt_timer_reload(pbpctl_dev);
3119#ifdef BP_SELF_TEST
3120 bp_timer_reload:
3121#endif
3122 if (pbpctl_dev->reset_time) {
3123 mod_timer(&pbpctl_dev->bp_timer,
3124 jiffies + (HZ * pbpctl_dev->reset_time) / 1000);
3125 }
3126}
3127
3128//#ifdef PMC_FIX_FLAG
3129/*WAIT_AT_PWRUP 0x80 */
3130int bp_wait_at_pwup_en(bpctl_dev_t * pbpctl_dev)
3131{
3132
3133 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3134 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3135 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_EN);
3136 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3137
3138 return BP_OK;
3139 }
3140 }
3141 return BP_NOT_CAP;
3142}
3143
3144/*DIS_WAIT_AT_PWRUP 0x81 */
3145int bp_wait_at_pwup_dis(bpctl_dev_t * pbpctl_dev)
3146{
3147
3148 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3149
3150 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3151 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_DIS);
3152 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3153
3154 return BP_OK;
3155 }
3156 }
3157 return BP_NOT_CAP;
3158}
3159
3160/*EN_HW_RESET 0x82 */
3161
3162int bp_hw_reset_en(bpctl_dev_t * pbpctl_dev)
3163{
3164
3165 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3166 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3167 write_data(pbpctl_dev, BP_HW_RESET_EN);
3168 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3169
3170 return BP_OK;
3171 }
3172 }
3173 return BP_NOT_CAP;
3174}
3175
3176/*DIS_HW_RESET 0x83 */
3177
3178int bp_hw_reset_dis(bpctl_dev_t * pbpctl_dev)
3179{
3180
3181 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3182 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3183 write_data(pbpctl_dev, BP_HW_RESET_DIS);
3184 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3185
3186 return BP_OK;
3187 }
3188 }
3189 return BP_NOT_CAP;
3190}
3191
3192//#endif /*PMC_FIX_FLAG*/
3193
3194int wdt_exp_mode(bpctl_dev_t * pbpctl_dev, int mode)
3195{
3196 uint32_t status_reg = 0, status_reg1 = 0;
3197
3198 if ((pbpctl_dev->bp_caps & (TAP_STATUS_CAP | DISC_CAP)) &&
3199 (pbpctl_dev->bp_caps & BP_CAP)) {
3200 if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3201
3202 if ((pbpctl_dev->bp_ext_ver >= 0x8) &&
3203 (mode == 2) && (pbpctl_dev->bp_caps & DISC_CAP)) {
3204 status_reg1 =
3205 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3206 if (!(status_reg1 & WDTE_DISC_BPN_MASK))
3207 write_reg(pbpctl_dev,
3208 status_reg1 |
3209 WDTE_DISC_BPN_MASK,
3210 STATUS_DISC_REG_ADDR);
3211 return BP_OK;
3212 }
3213 }
3214 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3215
3216 if ((mode == 0) && (pbpctl_dev->bp_caps & BP_CAP)) {
3217 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3218 status_reg1 =
3219 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3220 if (status_reg1 & WDTE_DISC_BPN_MASK)
3221 write_reg(pbpctl_dev,
3222 status_reg1 &
3223 ~WDTE_DISC_BPN_MASK,
3224 STATUS_DISC_REG_ADDR);
3225 }
3226 if (status_reg & WDTE_TAP_BPN_MASK)
3227 write_reg(pbpctl_dev,
3228 status_reg & ~WDTE_TAP_BPN_MASK,
3229 STATUS_TAP_REG_ADDR);
3230 return BP_OK;
3231
3232 } else if ((mode == 1) && (pbpctl_dev->bp_caps & TAP_CAP)) {
3233 if (!(status_reg & WDTE_TAP_BPN_MASK))
3234 write_reg(pbpctl_dev,
3235 status_reg | WDTE_TAP_BPN_MASK,
3236 STATUS_TAP_REG_ADDR);
3237 /*else return BP_NOT_CAP; */
3238 return BP_OK;
3239 }
3240
3241 }
3242 return BP_NOT_CAP;
3243}
3244
3245int bypass_fw_ver(bpctl_dev_t * pbpctl_dev)
3246{
3247 if (is_bypass_fn(pbpctl_dev))
3248 return ((read_reg(pbpctl_dev, VER_REG_ADDR)));
3249 else
3250 return BP_NOT_CAP;
3251}
3252
3253int bypass_sign_check(bpctl_dev_t * pbpctl_dev)
3254{
3255
3256 if (is_bypass_fn(pbpctl_dev))
3257 return (((read_reg(pbpctl_dev, PIC_SIGN_REG_ADDR)) ==
3258 PIC_SIGN_VALUE) ? 1 : 0);
3259 else
3260 return BP_NOT_CAP;
3261}
3262
3263static int tx_status(bpctl_dev_t * pbpctl_dev)
3264{
3265 uint32_t ctrl = 0;
3266 bpctl_dev_t *pbpctl_dev_m;
3267 if ((is_bypass_fn(pbpctl_dev)) == 1)
3268 pbpctl_dev_m = pbpctl_dev;
3269 else
3270 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3271 if (pbpctl_dev_m == NULL)
3272 return BP_NOT_CAP;
3273 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3274
3275 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3276 if (pbpctl_dev->bp_i80)
3277 return ((ctrl & BPCTLI_CTRL_SWDPIN1) != 0 ? 0 : 1);
3278 if (pbpctl_dev->bp_540) {
3279 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3280
3281 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3282 }
3283
3284 }
3285
3286 if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
3287 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
3288 uint16_t mii_reg;
3289 if (!
3290 (bp75_read_phy_reg
3291 (pbpctl_dev, BPCTLI_PHY_CONTROL, &mii_reg))) {
3292 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN)
3293 return 0;
3294
3295 else
3296 return 1;
3297 }
3298 return -1;
3299 }
3300
3301 if (pbpctl_dev->bp_10g9) {
3302 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3303 BP10G_SDP3_DATA) != 0 ? 0 : 1);
3304
3305 } else if (pbpctl_dev->bp_fiber5) {
3306 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
3307 if (ctrl & BPCTLI_CTRL_EXT_SDP6_DATA)
3308 return 0;
3309 return 1;
3310 } else if (pbpctl_dev->bp_10gb) {
3311 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3312 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3313 (ctrl | BP10GB_GPIO0_OE_P1) &
3314 ~(BP10GB_GPIO0_SET_P1 |
3315 BP10GB_GPIO0_CLR_P1));
3316
3317 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
3318 return (((BP10GB_READ_REG
3319 (pbpctl_dev,
3320 MISC_REG_GPIO)) & BP10GB_GPIO0_P1) !=
3321 0 ? 0 : 1);
3322 else
3323 return (((BP10GB_READ_REG
3324 (pbpctl_dev,
3325 MISC_REG_GPIO)) & BP10GB_GPIO0_P0) !=
3326 0 ? 0 : 1);
3327 }
3328
3329 if (!pbpctl_dev->bp_10g) {
3330
3331 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3332 if (pbpctl_dev->bp_i80)
3333 return ((ctrl & BPCTLI_CTRL_SWDPIN1) !=
3334 0 ? 0 : 1);
3335 if (pbpctl_dev->bp_540) {
3336 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3337
3338 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3339 }
3340
3341 return ((ctrl & BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3342 } else
3343 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3344 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3345
3346 }
3347 return BP_NOT_CAP;
3348}
3349
3350static int bp_force_link_status(bpctl_dev_t * pbpctl_dev)
3351{
3352
3353 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
3354
3355 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
3356 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3357 BP10G_SDP1_DIR) != 0 ? 1 : 0);
3358
3359 }
3360 }
3361 return BP_NOT_CAP;
3362}
3363
3364int bypass_from_last_read(bpctl_dev_t * pbpctl_dev)
3365{
3366 uint32_t ctrl_ext = 0;
3367 bpctl_dev_t *pbpctl_dev_b = NULL;
3368
3369 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3370 && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3371 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3372 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL_EXT,
3373 (ctrl_ext & ~BPCTLI_CTRL_EXT_SDP7_DIR));
3374 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3375 if (ctrl_ext & BPCTLI_CTRL_EXT_SDP7_DATA)
3376 return 0;
3377 return 1;
3378 } else
3379 return BP_NOT_CAP;
3380}
3381
3382int bypass_status_clear(bpctl_dev_t * pbpctl_dev)
3383{
3384 bpctl_dev_t *pbpctl_dev_b = NULL;
3385
3386 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3387 && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3388
3389 send_bypass_clear_pulse(pbpctl_dev_b, 1);
3390 return 0;
3391 } else
3392 return BP_NOT_CAP;
3393}
3394
3395int bypass_flag_status(bpctl_dev_t * pbpctl_dev)
3396{
3397
3398 if ((pbpctl_dev->bp_caps & BP_CAP)) {
3399 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3400 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3401 BYPASS_FLAG_MASK) ==
3402 BYPASS_FLAG_MASK) ? 1 : 0);
3403 }
3404 }
3405 return BP_NOT_CAP;
3406}
3407
3408int bypass_flag_status_clear(bpctl_dev_t * pbpctl_dev)
3409{
3410
3411 if (pbpctl_dev->bp_caps & BP_CAP) {
3412 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3413 uint32_t status_reg = 0;
3414 status_reg = read_reg(pbpctl_dev, STATUS_REG_ADDR);
3415 write_reg(pbpctl_dev, status_reg & ~BYPASS_FLAG_MASK,
3416 STATUS_REG_ADDR);
3417 return 0;
3418 }
3419 }
3420 return BP_NOT_CAP;
3421}
3422
3423int bypass_change_status(bpctl_dev_t * pbpctl_dev)
3424{
3425 int ret = BP_NOT_CAP;
3426
3427 if (pbpctl_dev->bp_caps & BP_STATUS_CHANGE_CAP) {
3428 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3429 ret = bypass_flag_status(pbpctl_dev);
3430 bypass_flag_status_clear(pbpctl_dev);
3431 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3432 ret = bypass_flag_status(pbpctl_dev);
3433 bypass_flag_status_clear(pbpctl_dev);
3434 } else {
3435 ret = bypass_from_last_read(pbpctl_dev);
3436 bypass_status_clear(pbpctl_dev);
3437 }
3438 }
3439 return ret;
3440}
3441
3442int bypass_off_status(bpctl_dev_t * pbpctl_dev)
3443{
3444
3445 if (pbpctl_dev->bp_caps & BP_CAP) {
3446 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3447 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3448 BYPASS_OFF_MASK) == BYPASS_OFF_MASK) ? 1 : 0);
3449 }
3450 }
3451 return BP_NOT_CAP;
3452}
3453
3454static int bypass_status(bpctl_dev_t * pbpctl_dev)
3455{
3456 u32 ctrl_ext = 0;
3457 if (pbpctl_dev->bp_caps & BP_CAP) {
3458
3459 bpctl_dev_t *pbpctl_dev_b = NULL;
3460
3461 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3462 return BP_NOT_CAP;
3463
3464 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
3465
3466 if (!pbpctl_dev->bp_status_un)
3467 return (((BPCTL_READ_REG
3468 (pbpctl_dev_b,
3469 CTRL_EXT)) &
3470 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3471 0 ? 1 : 0);
3472 else
3473 return BP_NOT_CAP;
3474 }
3475 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3476
3477 //BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, (BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT))&~BPCTLI_CTRL_EXT_SDP7_DIR);
3478 if (pbpctl_dev->bp_10g9) {
3479 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3480 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3481 (ctrl_ext | BP10G_I2C_CLK_OUT));
3482 //return(((readl((void *)((pbpctl_dev)->mem_map) + 0x28))&0x4)!=0?0:1);
3483 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3484 BP10G_I2C_CLK_IN) != 0 ? 0 : 1);
3485
3486 } else if (pbpctl_dev->bp_540) {
3487 return (((BP10G_READ_REG(pbpctl_dev_b, ESDP)) &
3488 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3489 }
3490
3491 else if ((pbpctl_dev->bp_fiber5)
3492 || (pbpctl_dev->bp_i80)) {
3493 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3494 BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3495 } else if (pbpctl_dev->bp_10gb) {
3496 ctrl_ext =
3497 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3498 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3499 (ctrl_ext | BP10GB_GPIO3_OE_P0)
3500 & ~(BP10GB_GPIO3_SET_P0 |
3501 BP10GB_GPIO3_CLR_P0));
3502
3503 return (((BP10GB_READ_REG
3504 (pbpctl_dev,
3505 MISC_REG_GPIO)) & BP10GB_GPIO3_P0) !=
3506 0 ? 0 : 1);
3507 }
3508
3509 else if (!pbpctl_dev->bp_10g)
3510 return (((BPCTL_READ_REG
3511 (pbpctl_dev_b,
3512 CTRL_EXT)) &
3513 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3514 0 ? 0 : 1);
3515
3516 else {
3517 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3518 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3519 (ctrl_ext |
3520 BP10G_SDP7_DATA_OUT));
3521 //return(((readl((void *)((pbpctl_dev)->mem_map) + 0x28))&0x4)!=0?0:1);
3522 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3523 BP10G_SDP7_DATA_IN) != 0 ? 0 : 1);
3524 }
3525
3526 } else if (pbpctl_dev->media_type == bp_copper) {
3527
3528 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3529 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3530 } else {
3531 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3532 return (bypass_from_last_read(pbpctl_dev));
3533 }
3534
3535 }
3536 return BP_NOT_CAP;
3537}
3538
3539int default_pwron_status(bpctl_dev_t * pbpctl_dev)
3540{
3541
3542 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3543 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
3544 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3545 return ((((read_reg
3546 (pbpctl_dev,
3547 STATUS_REG_ADDR)) & DFLT_PWRON_MASK)
3548 == DFLT_PWRON_MASK) ? 0 : 1);
3549 }
3550 } /*else if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3551 (pbpctl_dev->bp_caps&BP_PWUP_ON_CAP))
3552 return 1; */
3553 }
3554 return BP_NOT_CAP;
3555}
3556
3557static int default_pwroff_status(bpctl_dev_t * pbpctl_dev)
3558{
3559
3560 /*if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3561 (pbpctl_dev->bp_caps&BP_PWOFF_ON_CAP))
3562 return 1; */
3563 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3564 && (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
3565 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3566 DFLT_PWROFF_MASK) == DFLT_PWROFF_MASK) ? 0 : 1);
3567 }
3568 return BP_NOT_CAP;
3569}
3570
3571int dis_bypass_cap_status(bpctl_dev_t * pbpctl_dev)
3572{
3573
3574 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
3575 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3576 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3577 DIS_BYPASS_CAP_MASK) ==
3578 DIS_BYPASS_CAP_MASK) ? 1 : 0);
3579 }
3580 }
3581 return BP_NOT_CAP;
3582}
3583
3584int cmd_en_status(bpctl_dev_t * pbpctl_dev)
3585{
3586
3587 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3588 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3589 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3590 CMND_EN_MASK) == CMND_EN_MASK) ? 1 : 0);
3591 }
3592 }
3593 return BP_NOT_CAP;
3594}
3595
3596int wdt_en_status(bpctl_dev_t * pbpctl_dev)
3597{
3598
3599 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3600 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3601 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3602 WDT_EN_MASK) == WDT_EN_MASK) ? 1 : 0);
3603 }
3604 }
3605 return BP_NOT_CAP;
3606}
3607
3608int wdt_programmed(bpctl_dev_t * pbpctl_dev, int *timeout)
3609{
3610 int ret = 0;
3611 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3612 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3613 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3614 WDT_EN_MASK) {
3615 u8 wdt_val;
3616 wdt_val = read_reg(pbpctl_dev, WDT_REG_ADDR);
3617 *timeout = (1 << wdt_val) * 100;
3618 } else
3619 *timeout = 0;
3620 } else {
3621 int curr_wdt_status = pbpctl_dev->wdt_status;
3622 if (curr_wdt_status == WDT_STATUS_UNKNOWN)
3623 *timeout = -1;
3624 else
3625 *timeout =
3626 curr_wdt_status ==
3627 0 ? 0 : pbpctl_dev->bypass_timer_interval;
3628 };
3629 } else
3630 ret = BP_NOT_CAP;
3631 return ret;
3632}
3633
3634int bypass_support(bpctl_dev_t * pbpctl_dev)
3635{
3636 int ret = 0;
3637
3638 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3639 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3640 ret =
3641 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3642 BYPASS_SUPPORT_MASK) ==
3643 BYPASS_SUPPORT_MASK) ? 1 : 0);
3644 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3645 ret = 1;
3646 } else
3647 ret = BP_NOT_CAP;
3648 return ret;
3649}
3650
3651int tap_support(bpctl_dev_t * pbpctl_dev)
3652{
3653 int ret = 0;
3654
3655 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3656 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3657 ret =
3658 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3659 TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) ? 1 : 0);
3660 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3661 ret = 0;
3662 } else
3663 ret = BP_NOT_CAP;
3664 return ret;
3665}
3666
3667int normal_support(bpctl_dev_t * pbpctl_dev)
3668{
3669 int ret = BP_NOT_CAP;
3670
3671 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3672 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3673 ret =
3674 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3675 NORMAL_UNSUPPORT_MASK) ==
3676 NORMAL_UNSUPPORT_MASK) ? 0 : 1);
3677 } else
3678 ret = 1;
3679 };
3680 return ret;
3681}
3682
3683int get_bp_prod_caps(bpctl_dev_t * pbpctl_dev)
3684{
3685 if ((pbpctl_dev->bp_caps & SW_CTL_CAP) &&
3686 (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER))
3687 return (read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR));
3688 return BP_NOT_CAP;
3689
3690}
3691
3692int tap_flag_status(bpctl_dev_t * pbpctl_dev)
3693{
3694
3695 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3696 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3697 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3698 TAP_FLAG_MASK) == TAP_FLAG_MASK) ? 1 : 0);
3699
3700 }
3701 return BP_NOT_CAP;
3702}
3703
3704int tap_flag_status_clear(bpctl_dev_t * pbpctl_dev)
3705{
3706 uint32_t status_reg = 0;
3707 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3708 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3709 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3710 write_reg(pbpctl_dev, status_reg & ~TAP_FLAG_MASK,
3711 STATUS_TAP_REG_ADDR);
3712 return 0;
3713 }
3714 }
3715 return BP_NOT_CAP;
3716}
3717
3718int tap_change_status(bpctl_dev_t * pbpctl_dev)
3719{
3720 int ret = BP_NOT_CAP;
3721 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3722 if (pbpctl_dev->bp_caps & TAP_CAP) {
3723 if (pbpctl_dev->bp_caps & BP_CAP) {
3724 ret = tap_flag_status(pbpctl_dev);
3725 tap_flag_status_clear(pbpctl_dev);
3726 } else {
3727 ret = bypass_from_last_read(pbpctl_dev);
3728 bypass_status_clear(pbpctl_dev);
3729 }
3730 }
3731 }
3732 return ret;
3733}
3734
3735int tap_off_status(bpctl_dev_t * pbpctl_dev)
3736{
3737 if (pbpctl_dev->bp_caps & TAP_CAP) {
3738 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3739 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3740 TAP_OFF_MASK) == TAP_OFF_MASK) ? 1 : 0);
3741 }
3742 return BP_NOT_CAP;
3743}
3744
3745int tap_status(bpctl_dev_t * pbpctl_dev)
3746{
3747 u32 ctrl_ext = 0;
3748
3749 if (pbpctl_dev->bp_caps & TAP_CAP) {
3750 bpctl_dev_t *pbpctl_dev_b = NULL;
3751
3752 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3753 return BP_NOT_CAP;
3754
3755 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3756 if (!pbpctl_dev->bp_10g)
3757 return (((BPCTL_READ_REG
3758 (pbpctl_dev_b,
3759 CTRL_EXT)) &
3760 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3761 0 ? 0 : 1);
3762 else {
3763 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3764 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3765 (ctrl_ext |
3766 BP10G_SDP6_DATA_OUT));
3767 // return(((readl((void *)((pbpctl_dev)->mem_map) + 0x28))&0x1)!=0?0:1);
3768 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3769 BP10G_SDP6_DATA_IN) != 0 ? 0 : 1);
3770 }
3771
3772 } else if (pbpctl_dev->media_type == bp_copper)
3773 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3774 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3775 else {
3776 if ((bypass_status_clear(pbpctl_dev)) >= 0)
3777 return (bypass_from_last_read(pbpctl_dev));
3778 }
3779
3780 }
3781 return BP_NOT_CAP;
3782}
3783
3784int default_pwron_tap_status(bpctl_dev_t * pbpctl_dev)
3785{
3786 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3787 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3788 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3789 DFLT_PWRON_TAP_MASK) ==
3790 DFLT_PWRON_TAP_MASK) ? 1 : 0);
3791 }
3792 return BP_NOT_CAP;
3793}
3794
3795int dis_tap_cap_status(bpctl_dev_t * pbpctl_dev)
3796{
3797 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3798 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3799 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3800 DIS_TAP_CAP_MASK) ==
3801 DIS_TAP_CAP_MASK) ? 1 : 0);
3802 }
3803 return BP_NOT_CAP;
3804}
3805
3806int disc_flag_status(bpctl_dev_t * pbpctl_dev)
3807{
3808
3809 if (pbpctl_dev->bp_caps & DISC_CAP) {
3810 if (pbpctl_dev->bp_ext_ver >= 0x8)
3811 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3812 DISC_FLAG_MASK) == DISC_FLAG_MASK) ? 1 : 0);
3813
3814 }
3815 return BP_NOT_CAP;
3816}
3817
3818int disc_flag_status_clear(bpctl_dev_t * pbpctl_dev)
3819{
3820 uint32_t status_reg = 0;
3821 if (pbpctl_dev->bp_caps & DISC_CAP) {
3822 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3823 status_reg = read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3824 write_reg(pbpctl_dev, status_reg & ~DISC_FLAG_MASK,
3825 STATUS_DISC_REG_ADDR);
3826 return BP_OK;
3827 }
3828 }
3829 return BP_NOT_CAP;
3830}
3831
3832int disc_change_status(bpctl_dev_t * pbpctl_dev)
3833{
3834 int ret = BP_NOT_CAP;
3835 if (pbpctl_dev->bp_caps & DISC_CAP) {
3836 ret = disc_flag_status(pbpctl_dev);
3837 disc_flag_status_clear(pbpctl_dev);
3838 return ret;
3839 }
3840 return BP_NOT_CAP;
3841}
3842
3843int disc_off_status(bpctl_dev_t * pbpctl_dev)
3844{
3845 bpctl_dev_t *pbpctl_dev_b = NULL;
3846 u32 ctrl_ext = 0;
3847
3848 if (pbpctl_dev->bp_caps & DISC_CAP) {
3849 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3850 return BP_NOT_CAP;
3851 if (DISCF_IF_SERIES(pbpctl_dev->subdevice))
3852 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3853 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3854
3855 if (pbpctl_dev->bp_i80) {
3856 // return((((read_reg(pbpctl_dev,STATUS_DISC_REG_ADDR)) & DISC_OFF_MASK)==DISC_OFF_MASK)?1:0);
3857 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT)) &
3858 BPCTLI_CTRL_EXT_SDP6_DATA) != 0 ? 1 : 0);
3859
3860 }
3861 if (pbpctl_dev->bp_540) {
3862 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, ESDP);
3863 //return(((readl((void *)((pbpctl_dev)->mem_map) + 0x28))&0x4)!=0?0:1);
3864 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3865 BP10G_SDP2_DATA) != 0 ? 1 : 0);
3866
3867 }
3868 //if (pbpctl_dev->device==SILICOM_PXG2TBI_SSID) {
3869 if (pbpctl_dev->media_type == bp_copper) {
3870
3871#if 0
3872 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3873 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3874#endif
3875 if (!pbpctl_dev->bp_10g)
3876 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3877 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3878 else
3879 // return(((readl((void *)((pbpctl_dev)->mem_map) + 0x20)) & 0x2)!=0?1:0);
3880 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3881 BP10G_SDP1_DATA) != 0 ? 1 : 0);
3882
3883 } else {
3884
3885 if (pbpctl_dev->bp_10g9) {
3886 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3887 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3888 (ctrl_ext |
3889 BP10G_I2C_DATA_OUT));
3890 //return(((readl((void *)((pbpctl_dev)->mem_map) + 0x28))&0x4)!=0?0:1);
3891 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3892 BP10G_I2C_DATA_IN) != 0 ? 1 : 0);
3893
3894 } else if (pbpctl_dev->bp_fiber5) {
3895 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3896 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3897 } else if (pbpctl_dev->bp_10gb) {
3898 ctrl_ext =
3899 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3900 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3901 (ctrl_ext | BP10GB_GPIO3_OE_P1)
3902 & ~(BP10GB_GPIO3_SET_P1 |
3903 BP10GB_GPIO3_CLR_P1));
3904
3905 return (((BP10GB_READ_REG
3906 (pbpctl_dev,
3907 MISC_REG_GPIO)) & BP10GB_GPIO3_P1) !=
3908 0 ? 1 : 0);
3909 }
3910 if (!pbpctl_dev->bp_10g) {
3911
3912 return (((BPCTL_READ_REG
3913 (pbpctl_dev_b,
3914 CTRL_EXT)) &
3915 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3916 0 ? 1 : 0);
3917 } else {
3918 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3919 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3920 (ctrl_ext |
3921 BP10G_SDP6_DATA_OUT));
3922 // temp= (((BP10G_READ_REG(pbpctl_dev_b,EODSDP))&BP10G_SDP6_DATA_IN)!=0?1:0);
3923 //return(((readl((void *)((pbpctl_dev)->mem_map) + 0x28)) & 0x1)!=0?1:0);
3924 return (((BP10G_READ_REG(pbpctl_dev_b, EODSDP))
3925 & BP10G_SDP6_DATA_IN) != 0 ? 1 : 0);
3926 }
3927
3928 }
3929 }
3930 return BP_NOT_CAP;
3931}
3932
3933static int disc_status(bpctl_dev_t * pbpctl_dev)
3934{
3935 int ctrl = 0;
3936 if (pbpctl_dev->bp_caps & DISC_CAP) {
3937
3938 if ((ctrl = disc_off_status(pbpctl_dev)) < 0)
3939 return ctrl;
3940 return ((ctrl == 0) ? 1 : 0);
3941
3942 }
3943 return BP_NOT_CAP;
3944}
3945
3946int default_pwron_disc_status(bpctl_dev_t * pbpctl_dev)
3947{
3948 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
3949 if (pbpctl_dev->bp_ext_ver >= 0x8)
3950 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3951 DFLT_PWRON_DISC_MASK) ==
3952 DFLT_PWRON_DISC_MASK) ? 1 : 0);
3953 }
3954 return BP_NOT_CAP;
3955}
3956
3957int dis_disc_cap_status(bpctl_dev_t * pbpctl_dev)
3958{
3959 if (pbpctl_dev->bp_caps & DIS_DISC_CAP) {
3960 if (pbpctl_dev->bp_ext_ver >= 0x8)
3961 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3962 DIS_DISC_CAP_MASK) ==
3963 DIS_DISC_CAP_MASK) ? 1 : 0);
3964 }
3965 return BP_NOT_CAP;
3966}
3967
3968int disc_port_status(bpctl_dev_t * pbpctl_dev)
3969{
3970 int ret = BP_NOT_CAP;
3971 bpctl_dev_t *pbpctl_dev_m;
3972
3973 if ((is_bypass_fn(pbpctl_dev)) == 1)
3974 pbpctl_dev_m = pbpctl_dev;
3975 else
3976 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3977 if (pbpctl_dev_m == NULL)
3978 return BP_NOT_CAP;
3979
3980 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3981 if (is_bypass_fn(pbpctl_dev) == 1) {
3982 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3983 TX_DISA_MASK) == TX_DISA_MASK) ? 1 : 0);
3984 } else
3985 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3986 TX_DISB_MASK) == TX_DISB_MASK) ? 1 : 0);
3987
3988 }
3989 return ret;
3990}
3991
3992int default_pwron_disc_port_status(bpctl_dev_t * pbpctl_dev)
3993{
3994 int ret = BP_NOT_CAP;
3995 bpctl_dev_t *pbpctl_dev_m;
3996
3997 if ((is_bypass_fn(pbpctl_dev)) == 1)
3998 pbpctl_dev_m = pbpctl_dev;
3999 else
4000 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4001 if (pbpctl_dev_m == NULL)
4002 return BP_NOT_CAP;
4003
4004 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
4005 if (is_bypass_fn(pbpctl_dev) == 1)
4006 return ret;
4007 // return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0);
4008 else
4009 return ret;
4010 // return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0);
4011
4012 }
4013 return ret;
4014}
4015
4016int wdt_exp_mode_status(bpctl_dev_t * pbpctl_dev)
4017{
4018 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4019 if (pbpctl_dev->bp_ext_ver <= PXG2BPI_VER)
4020 return 0; /* bypass mode */
4021 else if (pbpctl_dev->bp_ext_ver == PXG2TBPI_VER)
4022 return 1; /* tap mode */
4023 else if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
4024 if (pbpctl_dev->bp_ext_ver >= 0x8) {
4025 if (((read_reg
4026 (pbpctl_dev,
4027 STATUS_DISC_REG_ADDR)) &
4028 WDTE_DISC_BPN_MASK) == WDTE_DISC_BPN_MASK)
4029 return 2;
4030 }
4031 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
4032 WDTE_TAP_BPN_MASK) ==
4033 WDTE_TAP_BPN_MASK) ? 1 : 0);
4034 }
4035 }
4036 return BP_NOT_CAP;
4037}
4038
4039int tpl2_flag_status(bpctl_dev_t * pbpctl_dev)
4040{
4041
4042 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
4043 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
4044 TPL2_FLAG_MASK) == TPL2_FLAG_MASK) ? 1 : 0);
4045
4046 }
4047 return BP_NOT_CAP;
4048}
4049
4050int tpl_hw_status(bpctl_dev_t * pbpctl_dev)
4051{
4052 bpctl_dev_t *pbpctl_dev_b = NULL;
4053
4054 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
4055 return BP_NOT_CAP;
4056
4057 if (TPL_IF_SERIES(pbpctl_dev->subdevice))
4058 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
4059 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
4060 return BP_NOT_CAP;
4061}
4062
4063//#ifdef PMC_FIX_FLAG
4064
4065int bp_wait_at_pwup_status(bpctl_dev_t * pbpctl_dev)
4066{
4067 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
4068 if (pbpctl_dev->bp_ext_ver >= 0x8)
4069 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
4070 WAIT_AT_PWUP_MASK) ==
4071 WAIT_AT_PWUP_MASK) ? 1 : 0);
4072 }
4073 return BP_NOT_CAP;
4074}
4075
4076int bp_hw_reset_status(bpctl_dev_t * pbpctl_dev)
4077{
4078
4079 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
4080
4081 if (pbpctl_dev->bp_ext_ver >= 0x8)
4082 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
4083 EN_HW_RESET_MASK) ==
4084 EN_HW_RESET_MASK) ? 1 : 0);
4085 }
4086 return BP_NOT_CAP;
4087}
4088
4089//#endif /*PMC_FIX_FLAG*/
4090
4091int std_nic_status(bpctl_dev_t * pbpctl_dev)
4092{
4093 int status_val = 0;
4094
4095 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
4096 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4097 return BP_NOT_CAP;
4098 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4099 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
4100 STD_NIC_ON_MASK) == STD_NIC_ON_MASK) ? 1 : 0);
4101 }
4102
4103 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4104 if (pbpctl_dev->bp_caps & BP_CAP) {
4105 status_val =
4106 read_reg(pbpctl_dev, STATUS_REG_ADDR);
4107 if (((!(status_val & WDT_EN_MASK))
4108 && ((status_val & STD_NIC_MASK) ==
4109 STD_NIC_MASK)))
4110 status_val = 1;
4111 else
4112 return 0;
4113 }
4114 if (pbpctl_dev->bp_caps & TAP_CAP) {
4115 status_val =
4116 read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4117 if ((status_val & STD_NIC_TAP_MASK) ==
4118 STD_NIC_TAP_MASK)
4119 status_val = 1;
4120 else
4121 return 0;
4122 }
4123 if (pbpctl_dev->bp_caps & TAP_CAP) {
4124 if ((disc_off_status(pbpctl_dev)))
4125 status_val = 1;
4126 else
4127 return 0;
4128 }
4129
4130 return status_val;
4131 }
4132 }
4133 return BP_NOT_CAP;
4134}
4135
4136/******************************************************/
4137/**************SW_INIT*********************************/
4138/******************************************************/
4139void bypass_caps_init(bpctl_dev_t * pbpctl_dev)
4140{
4141 u_int32_t ctrl_ext = 0;
4142 bpctl_dev_t *pbpctl_dev_m = NULL;
4143
4144#ifdef BYPASS_DEBUG
4145 int ret = 0;
4146 if (!(INTEL_IF_SERIES(adapter->bp_device_block.subdevice))) {
4147 ret = read_reg(pbpctl_dev, VER_REG_ADDR);
4148 printk("VER_REG reg1=%x\n", ret);
4149 ret = read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
4150 printk("PRODUCT_CAP reg=%x\n", ret);
4151 ret = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4152 printk("STATUS_TAP reg1=%x\n", ret);
4153 ret = read_reg(pbpctl_dev, 0x7);
4154 printk("SIG_REG reg1=%x\n", ret);
4155 ret = read_reg(pbpctl_dev, STATUS_REG_ADDR);
4156 printk("STATUS_REG_ADDR=%x\n", ret);
4157 ret = read_reg(pbpctl_dev, WDT_REG_ADDR);
4158 printk("WDT_REG_ADDR=%x\n", ret);
4159 ret = read_reg(pbpctl_dev, TMRL_REG_ADDR);
4160 printk("TMRL_REG_ADDR=%x\n", ret);
4161 ret = read_reg(pbpctl_dev, TMRH_REG_ADDR);
4162 printk("TMRH_REG_ADDR=%x\n", ret);
4163 }
4164#endif
4165 if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_10g9)) {
4166 pbpctl_dev->media_type = bp_fiber;
4167 } else if (pbpctl_dev->bp_10gb) {
4168 if (BP10GB_CX4_SERIES(pbpctl_dev->subdevice))
4169 pbpctl_dev->media_type = bp_cx4;
4170 else
4171 pbpctl_dev->media_type = bp_fiber;
4172
4173 }
4174
4175 else if (pbpctl_dev->bp_540)
4176 pbpctl_dev->media_type = bp_none;
4177 else if (!pbpctl_dev->bp_10g) {
4178
4179 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
4180 if ((ctrl_ext & BPCTLI_CTRL_EXT_LINK_MODE_MASK) == 0x0)
4181 pbpctl_dev->media_type = bp_copper;
4182 else
4183 pbpctl_dev->media_type = bp_fiber;
4184
4185 }
4186 //if (!pbpctl_dev->bp_10g)
4187 // pbpctl_dev->media_type=((BPCTL_READ_REG(pbpctl_dev, STATUS))&BPCTLI_STATUS_TBIMODE)?bp_fiber:bp_copper;
4188 else {
4189 if (BP10G_CX4_SERIES(pbpctl_dev->subdevice))
4190 pbpctl_dev->media_type = bp_cx4;
4191 else
4192 pbpctl_dev->media_type = bp_fiber;
4193 }
4194
4195 //pbpctl_dev->bp_fw_ver=0xa8;
4196 if (is_bypass_fn(pbpctl_dev)) {
4197
4198 pbpctl_dev->bp_caps |= BP_PWOFF_ON_CAP;
4199 if (pbpctl_dev->media_type == bp_fiber)
4200 pbpctl_dev->bp_caps |=
4201 (TX_CTL_CAP | TX_STATUS_CAP | TPL_CAP);
4202
4203 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
4204 pbpctl_dev->bp_caps |= TPL_CAP;
4205 }
4206
4207 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
4208 pbpctl_dev->bp_caps |=
4209 (BP_CAP | BP_STATUS_CAP | SW_CTL_CAP |
4210 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWOFF_OFF_CAP
4211 | WD_CTL_CAP | WD_STATUS_CAP | STD_NIC_CAP |
4212 WD_TIMEOUT_CAP);
4213
4214 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4215 return;
4216 }
4217
4218 if ((pbpctl_dev->bp_fw_ver == 0xff) &&
4219 OLD_IF_SERIES(pbpctl_dev->subdevice)) {
4220
4221 pbpctl_dev->bp_caps |=
4222 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4223 SW_CTL_CAP | BP_PWUP_ON_CAP | WD_CTL_CAP |
4224 WD_STATUS_CAP | WD_TIMEOUT_CAP);
4225
4226 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4227 return;
4228 }
4229
4230 else {
4231 switch (pbpctl_dev->bp_fw_ver) {
4232 case BP_FW_VER_A0:
4233 case BP_FW_VER_A1:{
4234 pbpctl_dev->bp_ext_ver =
4235 (pbpctl_dev->
4236 bp_fw_ver & EXT_VER_MASK);
4237 break;
4238 }
4239 default:{
4240 if ((bypass_sign_check(pbpctl_dev)) !=
4241 1) {
4242 pbpctl_dev->bp_caps = 0;
4243 return;
4244 }
4245 pbpctl_dev->bp_ext_ver =
4246 (pbpctl_dev->
4247 bp_fw_ver & EXT_VER_MASK);
4248 }
4249 }
4250 }
4251
4252 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
4253 pbpctl_dev->bp_caps |=
4254 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4255 SW_CTL_CAP | BP_DIS_CAP | BP_DIS_STATUS_CAP |
4256 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP
4257 | WD_CTL_CAP | STD_NIC_CAP | WD_STATUS_CAP |
4258 WD_TIMEOUT_CAP);
4259 else if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
4260 int cap_reg;
4261
4262 pbpctl_dev->bp_caps |=
4263 (SW_CTL_CAP | WD_CTL_CAP | WD_STATUS_CAP |
4264 WD_TIMEOUT_CAP);
4265 cap_reg = get_bp_prod_caps(pbpctl_dev);
4266
4267 if ((cap_reg & NORMAL_UNSUPPORT_MASK) ==
4268 NORMAL_UNSUPPORT_MASK)
4269 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4270 else
4271 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4272
4273 if ((normal_support(pbpctl_dev)) == 1)
4274
4275 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4276
4277 else
4278 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4279 if ((cap_reg & BYPASS_SUPPORT_MASK) ==
4280 BYPASS_SUPPORT_MASK) {
4281 pbpctl_dev->bp_caps |=
4282 (BP_CAP | BP_STATUS_CAP |
4283 BP_STATUS_CHANGE_CAP | BP_DIS_CAP |
4284 BP_DIS_STATUS_CAP | BP_PWUP_ON_CAP |
4285 BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP);
4286 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER7)
4287 pbpctl_dev->bp_caps |=
4288 BP_PWOFF_ON_CAP | BP_PWOFF_OFF_CAP |
4289 BP_PWOFF_CTL_CAP;
4290 }
4291 if ((cap_reg & TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) {
4292 pbpctl_dev->bp_caps |=
4293 (TAP_CAP | TAP_STATUS_CAP |
4294 TAP_STATUS_CHANGE_CAP | TAP_DIS_CAP |
4295 TAP_DIS_STATUS_CAP | TAP_PWUP_ON_CAP |
4296 TAP_PWUP_OFF_CAP | TAP_PWUP_CTL_CAP);
4297 }
4298 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4299 if ((cap_reg & DISC_SUPPORT_MASK) ==
4300 DISC_SUPPORT_MASK)
4301 pbpctl_dev->bp_caps |=
4302 (DISC_CAP | DISC_DIS_CAP |
4303 DISC_PWUP_CTL_CAP);
4304 if ((cap_reg & TPL2_SUPPORT_MASK) ==
4305 TPL2_SUPPORT_MASK) {
4306 pbpctl_dev->bp_caps_ex |= TPL2_CAP_EX;
4307 pbpctl_dev->bp_caps |= TPL_CAP;
4308 pbpctl_dev->bp_tpl_flag =
4309 tpl2_flag_status(pbpctl_dev);
4310 }
4311
4312 }
4313
4314 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER9) {
4315 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4316 DISC_PORT_SUPPORT_MASK) {
4317 pbpctl_dev->bp_caps_ex |=
4318 DISC_PORT_CAP_EX;
4319 pbpctl_dev->bp_caps |=
4320 (TX_CTL_CAP | TX_STATUS_CAP);
4321 }
4322
4323 }
4324
4325 }
4326 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4327 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
4328 WDT_EN_MASK)
4329 pbpctl_dev->wdt_status = WDT_STATUS_EN;
4330 else
4331 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
4332 }
4333
4334 } else if ((P2BPFI_IF_SERIES(pbpctl_dev->subdevice)) ||
4335 (PEGF5_IF_SERIES(pbpctl_dev->subdevice)) ||
4336 (PEGF80_IF_SERIES(pbpctl_dev->subdevice)) ||
4337 (BP10G9_IF_SERIES(pbpctl_dev->subdevice))) {
4338 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4339 }
4340 if ((pbpctl_dev->subdevice & 0xa00) == 0xa00)
4341 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4342 if (PEG5_IF_SERIES(pbpctl_dev->subdevice))
4343 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4344
4345 if (BP10GB_IF_SERIES(pbpctl_dev->subdevice)) {
4346 pbpctl_dev->bp_caps &= ~(TX_CTL_CAP | TX_STATUS_CAP);
4347 }
4348 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4349 if (pbpctl_dev_m != NULL) {
4350 int cap_reg = 0;
4351 if (pbpctl_dev_m->bp_ext_ver >= 0x9) {
4352 cap_reg = get_bp_prod_caps(pbpctl_dev_m);
4353 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4354 DISC_PORT_SUPPORT_MASK)
4355 pbpctl_dev->bp_caps |=
4356 (TX_CTL_CAP | TX_STATUS_CAP);
4357 pbpctl_dev->bp_caps_ex |= DISC_PORT_CAP_EX;
4358 }
4359 }
4360}
4361
4362int bypass_off_init(bpctl_dev_t * pbpctl_dev)
4363{
4364 int ret = 0;
4365
4366 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4367 return ret;
4368 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4369 return (dis_bypass_cap(pbpctl_dev));
4370 wdt_off(pbpctl_dev);
4371 if (pbpctl_dev->bp_caps & BP_CAP)
4372 bypass_off(pbpctl_dev);
4373 if (pbpctl_dev->bp_caps & TAP_CAP)
4374 tap_off(pbpctl_dev);
4375 cmnd_off(pbpctl_dev);
4376 return 0;
4377}
4378
4379void remove_bypass_wd_auto(bpctl_dev_t * pbpctl_dev)
4380{
4381#ifdef BP_SELF_TEST
4382 bpctl_dev_t *pbpctl_dev_sl = NULL;
4383#endif
4384
4385 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4386
4387 del_timer_sync(&pbpctl_dev->bp_timer);
4388#ifdef BP_SELF_TEST
4389 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4390#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
4391 if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)
4392 && (pbpctl_dev_sl->ndev->hard_start_xmit)
4393 && (pbpctl_dev_sl->hard_start_xmit_save)) {
4394 rtnl_lock();
4395 pbpctl_dev_sl->ndev->hard_start_xmit =
4396 pbpctl_dev_sl->hard_start_xmit_save;
4397 rtnl_unlock();
4398 }
4399#else
4400 if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)) {
4401 if ((pbpctl_dev_sl->ndev->netdev_ops)
4402 && (pbpctl_dev_sl->old_ops)) {
4403 rtnl_lock();
4404 pbpctl_dev_sl->ndev->netdev_ops =
4405 pbpctl_dev_sl->old_ops;
4406 pbpctl_dev_sl->old_ops = NULL;
4407
4408 rtnl_unlock();
4409
4410 }
4411
4412 }
4413
4414#endif
4415#endif
4416 }
4417
4418}
4419
4420int init_bypass_wd_auto(bpctl_dev_t * pbpctl_dev)
4421{
4422 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4423 init_timer(&pbpctl_dev->bp_timer);
4424 pbpctl_dev->bp_timer.function = &wd_reset_timer;
4425 pbpctl_dev->bp_timer.data = (unsigned long)pbpctl_dev;
4426 return 1;
4427 }
4428 return BP_NOT_CAP;
4429}
4430
4431#ifdef BP_SELF_TEST
4432int bp_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
4433{
4434 bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
4435 int idx_dev = 0;
4436 struct ethhdr *eth = (struct ethhdr *)skb->data;
4437
4438 for (idx_dev = 0;
4439 ((bpctl_dev_arr[idx_dev].ndev != NULL) && (idx_dev < device_num));
4440 idx_dev++) {
4441 if (bpctl_dev_arr[idx_dev].ndev == dev) {
4442 pbpctl_dev = &bpctl_dev_arr[idx_dev];
4443 break;
4444 }
4445 }
4446 if (!pbpctl_dev)
4447 return 1;
4448 if ((htons(ETH_P_BPTEST) == eth->h_proto)) {
4449
4450 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4451 if (pbpctl_dev_m) {
4452
4453 if (bypass_status(pbpctl_dev_m)) {
4454 cmnd_on(pbpctl_dev_m);
4455 bypass_off(pbpctl_dev_m);
4456 cmnd_off(pbpctl_dev_m);
4457 }
4458 wdt_timer_reload(pbpctl_dev_m);
4459 }
4460 dev_kfree_skb_irq(skb);
4461 return 0;
4462 }
4463 return (pbpctl_dev->hard_start_xmit_save(skb, dev));
4464}
4465#endif
4466
4467int set_bypass_wd_auto(bpctl_dev_t * pbpctl_dev, unsigned int param)
4468{
4469 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4470 if (pbpctl_dev->reset_time != param) {
4471 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4472 pbpctl_dev->reset_time =
4473 (param <
4474 WDT_AUTO_MIN_INT) ? WDT_AUTO_MIN_INT :
4475 param;
4476 else
4477 pbpctl_dev->reset_time = param;
4478 if (param)
4479 mod_timer(&pbpctl_dev->bp_timer, jiffies);
4480 }
4481 return 0;
4482 }
4483 return BP_NOT_CAP;
4484}
4485
4486int get_bypass_wd_auto(bpctl_dev_t * pbpctl_dev)
4487{
4488
4489 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4490 return pbpctl_dev->reset_time;
4491 }
4492 return BP_NOT_CAP;
4493}
4494
4495#ifdef BP_SELF_TEST
4496
4497int set_bp_self_test(bpctl_dev_t * pbpctl_dev, unsigned int param)
4498{
4499 bpctl_dev_t *pbpctl_dev_sl = NULL;
4500
4501 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4502 pbpctl_dev->bp_self_test_flag = param == 0 ? 0 : 1;
4503 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
4504#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
4505 if ((pbpctl_dev_sl->ndev) &&
4506 (pbpctl_dev_sl->ndev->hard_start_xmit)) {
4507 rtnl_lock();
4508 if (pbpctl_dev->bp_self_test_flag == 1) {
4509
4510 pbpctl_dev_sl->hard_start_xmit_save =
4511 pbpctl_dev_sl->ndev->hard_start_xmit;
4512 pbpctl_dev_sl->ndev->hard_start_xmit =
4513 bp_hard_start_xmit;
4514 } else if (pbpctl_dev_sl->hard_start_xmit_save) {
4515 pbpctl_dev_sl->ndev->hard_start_xmit =
4516 pbpctl_dev_sl->hard_start_xmit_save;
4517 }
4518 rtnl_unlock();
4519 }
4520#else
4521 if ((pbpctl_dev_sl->ndev) && (pbpctl_dev_sl->ndev->netdev_ops)) {
4522 rtnl_lock();
4523 if (pbpctl_dev->bp_self_test_flag == 1) {
4524
4525 pbpctl_dev_sl->old_ops =
4526 pbpctl_dev_sl->ndev->netdev_ops;
4527 pbpctl_dev_sl->new_ops =
4528 *pbpctl_dev_sl->old_ops;
4529 pbpctl_dev_sl->new_ops.ndo_start_xmit =
4530 bp_hard_start_xmit;
4531 pbpctl_dev_sl->ndev->netdev_ops =
4532 &pbpctl_dev_sl->new_ops;
4533
4534 } else if (pbpctl_dev_sl->old_ops) {
4535 pbpctl_dev_sl->ndev->netdev_ops =
4536 pbpctl_dev_sl->old_ops;
4537 pbpctl_dev_sl->old_ops = NULL;
4538 }
4539 rtnl_unlock();
4540 }
4541#endif
4542
4543 set_bypass_wd_auto(pbpctl_dev, param);
4544 return 0;
4545 }
4546 return BP_NOT_CAP;
4547}
4548
4549int get_bp_self_test(bpctl_dev_t * pbpctl_dev)
4550{
4551
4552 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4553 if (pbpctl_dev->bp_self_test_flag == 1)
4554 return pbpctl_dev->reset_time;
4555 else
4556 return 0;
4557 }
4558 return BP_NOT_CAP;
4559}
4560
4561#endif
4562
4563/**************************************************************/
4564/************************* API ********************************/
4565/**************************************************************/
4566
4567int is_bypass_fn(bpctl_dev_t * pbpctl_dev)
4568{
4569 if (!pbpctl_dev)
4570 return -1;
4571
4572 return (((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) ? 1 : 0);
4573}
4574
4575int set_bypass_fn(bpctl_dev_t * pbpctl_dev, int bypass_mode)
4576{
4577 int ret = 0;
4578
4579 if (!(pbpctl_dev->bp_caps & BP_CAP))
4580 return BP_NOT_CAP;
4581 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4582 return ret;
4583 if (!bypass_mode)
4584 ret = bypass_off(pbpctl_dev);
4585 else
4586 ret = bypass_on(pbpctl_dev);
4587 cmnd_off(pbpctl_dev);
4588
4589 return ret;
4590}
4591
4592int get_bypass_fn(bpctl_dev_t * pbpctl_dev)
4593{
4594 return (bypass_status(pbpctl_dev));
4595}
4596
4597int get_bypass_change_fn(bpctl_dev_t * pbpctl_dev)
4598{
4599 if (!pbpctl_dev)
4600 return -1;
4601
4602 return (bypass_change_status(pbpctl_dev));
4603}
4604
4605int set_dis_bypass_fn(bpctl_dev_t * pbpctl_dev, int dis_param)
4606{
4607 int ret = 0;
4608 if (!pbpctl_dev)
4609 return -1;
4610
4611 if (!(pbpctl_dev->bp_caps & BP_DIS_CAP))
4612 return BP_NOT_CAP;
4613 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4614 return ret;
4615 if (dis_param)
4616 ret = dis_bypass_cap(pbpctl_dev);
4617 else
4618 ret = en_bypass_cap(pbpctl_dev);
4619 cmnd_off(pbpctl_dev);
4620 return ret;
4621}
4622
4623int get_dis_bypass_fn(bpctl_dev_t * pbpctl_dev)
4624{
4625 if (!pbpctl_dev)
4626 return -1;
4627
4628 return (dis_bypass_cap_status(pbpctl_dev));
4629}
4630
4631int set_bypass_pwoff_fn(bpctl_dev_t * pbpctl_dev, int bypass_mode)
4632{
4633 int ret = 0;
4634 if (!pbpctl_dev)
4635 return -1;
4636
4637 if (!(pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP))
4638 return BP_NOT_CAP;
4639 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4640 return ret;
4641 if (bypass_mode)
4642 ret = bypass_state_pwroff(pbpctl_dev);
4643 else
4644 ret = normal_state_pwroff(pbpctl_dev);
4645 cmnd_off(pbpctl_dev);
4646 return ret;
4647}
4648
4649int get_bypass_pwoff_fn(bpctl_dev_t * pbpctl_dev)
4650{
4651 if (!pbpctl_dev)
4652 return -1;
4653
4654 return (default_pwroff_status(pbpctl_dev));
4655}
4656
4657int set_bypass_pwup_fn(bpctl_dev_t * pbpctl_dev, int bypass_mode)
4658{
4659 int ret = 0;
4660 if (!pbpctl_dev)
4661 return -1;
4662
4663 if (!(pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP))
4664 return BP_NOT_CAP;
4665 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4666 return ret;
4667 if (bypass_mode)
4668 ret = bypass_state_pwron(pbpctl_dev);
4669 else
4670 ret = normal_state_pwron(pbpctl_dev);
4671 cmnd_off(pbpctl_dev);
4672 return ret;
4673}
4674
4675int get_bypass_pwup_fn(bpctl_dev_t * pbpctl_dev)
4676{
4677 if (!pbpctl_dev)
4678 return -1;
4679
4680 return (default_pwron_status(pbpctl_dev));
4681}
4682
4683int set_bypass_wd_fn(bpctl_dev_t * pbpctl_dev, int timeout)
4684{
4685 int ret = 0;
4686 if (!pbpctl_dev)
4687 return -1;
4688
4689 if (!(pbpctl_dev->bp_caps & WD_CTL_CAP))
4690 return BP_NOT_CAP;
4691
4692 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4693 return ret;
4694 if (!timeout)
4695 ret = wdt_off(pbpctl_dev);
4696 else {
4697 wdt_on(pbpctl_dev, timeout);
4698 ret = pbpctl_dev->bypass_timer_interval;
4699 }
4700 cmnd_off(pbpctl_dev);
4701 return ret;
4702}
4703
4704int get_bypass_wd_fn(bpctl_dev_t * pbpctl_dev, int *timeout)
4705{
4706 if (!pbpctl_dev)
4707 return -1;
4708
4709 return wdt_programmed(pbpctl_dev, timeout);
4710}
4711
4712int get_wd_expire_time_fn(bpctl_dev_t * pbpctl_dev, int *time_left)
4713{
4714 if (!pbpctl_dev)
4715 return -1;
4716
4717 return (wdt_timer(pbpctl_dev, time_left));
4718}
4719
4720int reset_bypass_wd_timer_fn(bpctl_dev_t * pbpctl_dev)
4721{
4722 if (!pbpctl_dev)
4723 return -1;
4724
4725 return (wdt_timer_reload(pbpctl_dev));
4726}
4727
4728int get_wd_set_caps_fn(bpctl_dev_t * pbpctl_dev)
4729{
4730 int bp_status = 0;
4731
4732 unsigned int step_value = TIMEOUT_MAX_STEP + 1, bit_cnt = 0;
4733 if (!pbpctl_dev)
4734 return -1;
4735
4736 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4737 return BP_NOT_CAP;
4738
4739 while ((step_value >>= 1))
4740 bit_cnt++;
4741
4742 if (is_bypass_fn(pbpctl_dev)) {
4743 bp_status =
4744 WD_STEP_COUNT_MASK(bit_cnt) | WDT_STEP_TIME |
4745 WD_MIN_TIME_MASK(TIMEOUT_UNIT / 100);
4746 } else
4747 return -1;
4748
4749 return bp_status;
4750}
4751
4752int set_std_nic_fn(bpctl_dev_t * pbpctl_dev, int nic_mode)
4753{
4754 int ret = 0;
4755 if (!pbpctl_dev)
4756 return -1;
4757
4758 if (!(pbpctl_dev->bp_caps & STD_NIC_CAP))
4759 return BP_NOT_CAP;
4760
4761 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4762 return ret;
4763 if (nic_mode)
4764 ret = std_nic_on(pbpctl_dev);
4765 else
4766 ret = std_nic_off(pbpctl_dev);
4767 cmnd_off(pbpctl_dev);
4768 return ret;
4769}
4770
4771int get_std_nic_fn(bpctl_dev_t * pbpctl_dev)
4772{
4773 if (!pbpctl_dev)
4774 return -1;
4775
4776 return (std_nic_status(pbpctl_dev));
4777}
4778
4779int set_tap_fn(bpctl_dev_t * pbpctl_dev, int tap_mode)
4780{
4781 if (!pbpctl_dev)
4782 return -1;
4783
4784 if ((pbpctl_dev->bp_caps & TAP_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4785 if (!tap_mode)
4786 tap_off(pbpctl_dev);
4787 else
4788 tap_on(pbpctl_dev);
4789 cmnd_off(pbpctl_dev);
4790 return 0;
4791 }
4792 return BP_NOT_CAP;
4793}
4794
4795int get_tap_fn(bpctl_dev_t * pbpctl_dev)
4796{
4797 if (!pbpctl_dev)
4798 return -1;
4799
4800 return (tap_status(pbpctl_dev));
4801}
4802
4803int set_tap_pwup_fn(bpctl_dev_t * pbpctl_dev, int tap_mode)
4804{
4805 int ret = 0;
4806 if (!pbpctl_dev)
4807 return -1;
4808
4809 if ((pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)
4810 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4811 if (tap_mode)
4812 ret = tap_state_pwron(pbpctl_dev);
4813 else
4814 ret = normal_state_pwron(pbpctl_dev);
4815 cmnd_off(pbpctl_dev);
4816 } else
4817 ret = BP_NOT_CAP;
4818 return ret;
4819}
4820
4821int get_tap_pwup_fn(bpctl_dev_t * pbpctl_dev)
4822{
4823 int ret = 0;
4824 if (!pbpctl_dev)
4825 return -1;
4826
4827 if ((ret = default_pwron_tap_status(pbpctl_dev)) < 0)
4828 return ret;
4829 return ((ret == 0) ? 1 : 0);
4830}
4831
4832int get_tap_change_fn(bpctl_dev_t * pbpctl_dev)
4833{
4834 if (!pbpctl_dev)
4835 return -1;
4836
4837 return (tap_change_status(pbpctl_dev));
4838}
4839
4840int set_dis_tap_fn(bpctl_dev_t * pbpctl_dev, int dis_param)
4841{
4842 int ret = 0;
4843 if (!pbpctl_dev)
4844 return -1;
4845
4846 if ((pbpctl_dev->bp_caps & TAP_DIS_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4847 if (dis_param)
4848 ret = dis_tap_cap(pbpctl_dev);
4849 else
4850 ret = en_tap_cap(pbpctl_dev);
4851 cmnd_off(pbpctl_dev);
4852 return ret;
4853 } else
4854 return BP_NOT_CAP;
4855}
4856
4857int get_dis_tap_fn(bpctl_dev_t * pbpctl_dev)
4858{
4859 if (!pbpctl_dev)
4860 return -1;
4861
4862 return (dis_tap_cap_status(pbpctl_dev));
4863}
4864
4865int set_disc_fn(bpctl_dev_t * pbpctl_dev, int disc_mode)
4866{
4867 if (!pbpctl_dev)
4868 return -1;
4869
4870 if ((pbpctl_dev->bp_caps & DISC_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4871 if (!disc_mode)
4872 disc_off(pbpctl_dev);
4873 else
4874 disc_on(pbpctl_dev);
4875 cmnd_off(pbpctl_dev);
4876
4877 return BP_OK;
4878 }
4879 return BP_NOT_CAP;
4880}
4881
4882int get_disc_fn(bpctl_dev_t * pbpctl_dev)
4883{
4884 int ret = 0;
4885 if (!pbpctl_dev)
4886 return -1;
4887
4888 ret = disc_status(pbpctl_dev);
4889
4890 return ret;
4891}
4892
4893int set_disc_pwup_fn(bpctl_dev_t * pbpctl_dev, int disc_mode)
4894{
4895 int ret = 0;
4896 if (!pbpctl_dev)
4897 return -1;
4898
4899 if ((pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP)
4900 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4901 if (disc_mode)
4902 ret = disc_state_pwron(pbpctl_dev);
4903 else
4904 ret = normal_state_pwron(pbpctl_dev);
4905 cmnd_off(pbpctl_dev);
4906 } else
4907 ret = BP_NOT_CAP;
4908 return ret;
4909}
4910
4911int get_disc_pwup_fn(bpctl_dev_t * pbpctl_dev)
4912{
4913 int ret = 0;
4914 if (!pbpctl_dev)
4915 return -1;
4916
4917 ret = default_pwron_disc_status(pbpctl_dev);
4918 return (ret == 0 ? 1 : (ret < 0 ? BP_NOT_CAP : 0));
4919}
4920
4921int get_disc_change_fn(bpctl_dev_t * pbpctl_dev)
4922{
4923 int ret = 0;
4924 if (!pbpctl_dev)
4925 return -1;
4926
4927 ret = disc_change_status(pbpctl_dev);
4928 return ret;
4929}
4930
4931int set_dis_disc_fn(bpctl_dev_t * pbpctl_dev, int dis_param)
4932{
4933 int ret = 0;
4934 if (!pbpctl_dev)
4935 return -1;
4936
4937 if ((pbpctl_dev->bp_caps & DISC_DIS_CAP)
4938 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4939 if (dis_param)
4940 ret = dis_disc_cap(pbpctl_dev);
4941 else
4942 ret = en_disc_cap(pbpctl_dev);
4943 cmnd_off(pbpctl_dev);
4944 return ret;
4945 } else
4946 return BP_NOT_CAP;
4947}
4948
4949int get_dis_disc_fn(bpctl_dev_t * pbpctl_dev)
4950{
4951 int ret = 0;
4952 if (!pbpctl_dev)
4953 return -1;
4954
4955 ret = dis_disc_cap_status(pbpctl_dev);
4956
4957 return ret;
4958}
4959
4960int set_disc_port_fn(bpctl_dev_t * pbpctl_dev, int disc_mode)
4961{
4962 int ret = BP_NOT_CAP;
4963 if (!pbpctl_dev)
4964 return -1;
4965
4966 if (!disc_mode)
4967 ret = disc_port_off(pbpctl_dev);
4968 else
4969 ret = disc_port_on(pbpctl_dev);
4970
4971 return ret;
4972}
4973
4974int get_disc_port_fn(bpctl_dev_t * pbpctl_dev)
4975{
4976 if (!pbpctl_dev)
4977 return -1;
4978
4979 return (disc_port_status(pbpctl_dev));
4980}
4981
4982int set_disc_port_pwup_fn(bpctl_dev_t * pbpctl_dev, int disc_mode)
4983{
4984 int ret = BP_NOT_CAP;
4985 if (!pbpctl_dev)
4986 return -1;
4987
4988 if (!disc_mode)
4989 ret = normal_port_state_pwron(pbpctl_dev);
4990 else
4991 ret = disc_port_state_pwron(pbpctl_dev);
4992
4993 return ret;
4994}
4995
4996int get_disc_port_pwup_fn(bpctl_dev_t * pbpctl_dev)
4997{
4998 int ret = 0;
4999 if (!pbpctl_dev)
5000 return -1;
5001
5002 if ((ret = default_pwron_disc_port_status(pbpctl_dev)) < 0)
5003 return ret;
5004 return ((ret == 0) ? 1 : 0);
5005}
5006
5007int get_wd_exp_mode_fn(bpctl_dev_t * pbpctl_dev)
5008{
5009 if (!pbpctl_dev)
5010 return -1;
5011
5012 return (wdt_exp_mode_status(pbpctl_dev));
5013}
5014
5015int set_wd_exp_mode_fn(bpctl_dev_t * pbpctl_dev, int param)
5016{
5017 if (!pbpctl_dev)
5018 return -1;
5019
5020 return (wdt_exp_mode(pbpctl_dev, param));
5021}
5022
5023int reset_cont_fn(bpctl_dev_t * pbpctl_dev)
5024{
5025 int ret = 0;
5026 if (!pbpctl_dev)
5027 return -1;
5028
5029 if ((ret = cmnd_on(pbpctl_dev)) < 0)
5030 return ret;
5031 return (reset_cont(pbpctl_dev));
5032}
5033
5034int set_tx_fn(bpctl_dev_t * pbpctl_dev, int tx_state)
5035{
5036
5037 bpctl_dev_t *pbpctl_dev_b = NULL;
5038 if (!pbpctl_dev)
5039 return -1;
5040
5041 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
5042 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
5043 if ((pbpctl_dev->bp_tpl_flag))
5044 return BP_NOT_CAP;
5045 } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
5046 if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
5047 (pbpctl_dev_b->bp_tpl_flag))
5048 return BP_NOT_CAP;
5049 }
5050 return (set_tx(pbpctl_dev, tx_state));
5051}
5052
5053int set_bp_force_link_fn(int dev_num, int tx_state)
5054{
5055 static bpctl_dev_t *bpctl_dev_curr;
5056
5057 if ((dev_num < 0) || (dev_num > device_num)
5058 || (bpctl_dev_arr[dev_num].pdev == NULL))
5059 return -1;
5060 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
5061
5062 return (set_bp_force_link(bpctl_dev_curr, tx_state));
5063}
5064
5065int set_wd_autoreset_fn(bpctl_dev_t * pbpctl_dev, int param)
5066{
5067 if (!pbpctl_dev)
5068 return -1;
5069
5070 return (set_bypass_wd_auto(pbpctl_dev, param));
5071}
5072
5073int get_wd_autoreset_fn(bpctl_dev_t * pbpctl_dev)
5074{
5075 if (!pbpctl_dev)
5076 return -1;
5077
5078 return (get_bypass_wd_auto(pbpctl_dev));
5079}
5080
5081#ifdef BP_SELF_TEST
5082int set_bp_self_test_fn(bpctl_dev_t * pbpctl_dev, int param)
5083{
5084 if (!pbpctl_dev)
5085 return -1;
5086
5087 return (set_bp_self_test(pbpctl_dev, param));
5088}
5089
5090int get_bp_self_test_fn(bpctl_dev_t * pbpctl_dev)
5091{
5092 if (!pbpctl_dev)
5093 return -1;
5094
5095 return (get_bp_self_test(pbpctl_dev));
5096}
5097
5098#endif
5099
5100int get_bypass_caps_fn(bpctl_dev_t * pbpctl_dev)
5101{
5102 if (!pbpctl_dev)
5103 return -1;
5104
5105 return (pbpctl_dev->bp_caps);
5106
5107}
5108
5109int get_bypass_slave_fn(bpctl_dev_t * pbpctl_dev, bpctl_dev_t ** pbpctl_dev_out)
5110{
5111 int idx_dev = 0;
5112 if (!pbpctl_dev)
5113 return -1;
5114
5115 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
5116 for (idx_dev = 0;
5117 ((bpctl_dev_arr[idx_dev].pdev != NULL)
5118 && (idx_dev < device_num)); idx_dev++) {
5119 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
5120 && (bpctl_dev_arr[idx_dev].slot ==
5121 pbpctl_dev->slot)) {
5122 if ((pbpctl_dev->func == 0)
5123 && (bpctl_dev_arr[idx_dev].func == 1)) {
5124 *pbpctl_dev_out =
5125 &bpctl_dev_arr[idx_dev];
5126 return 1;
5127 }
5128 if ((pbpctl_dev->func == 2) &&
5129 (bpctl_dev_arr[idx_dev].func == 3)) {
5130 *pbpctl_dev_out =
5131 &bpctl_dev_arr[idx_dev];
5132 return 1;
5133 }
5134 }
5135 }
5136 return -1;
5137 } else
5138 return 0;
5139}
5140
5141int is_bypass(bpctl_dev_t * pbpctl_dev)
5142{
5143 if (!pbpctl_dev)
5144 return -1;
5145
5146 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2))
5147 return 1;
5148 else
5149 return 0;
5150}
5151
5152int get_tx_fn(bpctl_dev_t * pbpctl_dev)
5153{
5154 bpctl_dev_t *pbpctl_dev_b = NULL;
5155 if (!pbpctl_dev)
5156 return -1;
5157
5158 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
5159 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
5160 if ((pbpctl_dev->bp_tpl_flag))
5161 return BP_NOT_CAP;
5162 } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
5163 if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
5164 (pbpctl_dev_b->bp_tpl_flag))
5165 return BP_NOT_CAP;
5166 }
5167 return (tx_status(pbpctl_dev));
5168}
5169
5170int get_bp_force_link_fn(int dev_num)
5171{
5172 static bpctl_dev_t *bpctl_dev_curr;
5173
5174 if ((dev_num < 0) || (dev_num > device_num)
5175 || (bpctl_dev_arr[dev_num].pdev == NULL))
5176 return -1;
5177 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
5178
5179 return (bp_force_link_status(bpctl_dev_curr));
5180}
5181
5182static int get_bypass_link_status(bpctl_dev_t * pbpctl_dev)
5183{
5184 if (!pbpctl_dev)
5185 return -1;
5186
5187 if (pbpctl_dev->media_type == bp_fiber)
5188 return ((BPCTL_READ_REG(pbpctl_dev, CTRL) &
5189 BPCTLI_CTRL_SWDPIN1));
5190 else
5191 return ((BPCTL_READ_REG(pbpctl_dev, STATUS) &
5192 BPCTLI_STATUS_LU));
5193
5194}
5195
5196static void bp_tpl_timer_fn(unsigned long param)
5197{
5198 bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
5199 uint32_t link1, link2;
5200 bpctl_dev_t *pbpctl_dev_b = NULL;
5201
5202 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5203 return;
5204
5205 if (!pbpctl_dev->bp_tpl_flag) {
5206 set_tx(pbpctl_dev_b, 1);
5207 set_tx(pbpctl_dev, 1);
5208 return;
5209 }
5210 link1 = get_bypass_link_status(pbpctl_dev);
5211
5212 link2 = get_bypass_link_status(pbpctl_dev_b);
5213 if ((link1) && (tx_status(pbpctl_dev))) {
5214 if ((!link2) && (tx_status(pbpctl_dev_b))) {
5215 set_tx(pbpctl_dev, 0);
5216 } else if (!tx_status(pbpctl_dev_b)) {
5217 set_tx(pbpctl_dev_b, 1);
5218 }
5219 } else if ((!link1) && (tx_status(pbpctl_dev))) {
5220 if ((link2) && (tx_status(pbpctl_dev_b))) {
5221 set_tx(pbpctl_dev_b, 0);
5222 }
5223 } else if ((link1) && (!tx_status(pbpctl_dev))) {
5224 if ((link2) && (tx_status(pbpctl_dev_b))) {
5225 set_tx(pbpctl_dev, 1);
5226 }
5227 } else if ((!link1) && (!tx_status(pbpctl_dev))) {
5228 if ((link2) && (tx_status(pbpctl_dev_b))) {
5229 set_tx(pbpctl_dev, 1);
5230 }
5231 }
5232
5233 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + BP_LINK_MON_DELAY * HZ);
5234}
5235
5236void remove_bypass_tpl_auto(bpctl_dev_t * pbpctl_dev)
5237{
5238 bpctl_dev_t *pbpctl_dev_b = NULL;
5239 if (!pbpctl_dev)
5240 return;
5241 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5242
5243 if (pbpctl_dev->bp_caps & TPL_CAP) {
5244 del_timer_sync(&pbpctl_dev->bp_tpl_timer);
5245 pbpctl_dev->bp_tpl_flag = 0;
5246 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5247 if (pbpctl_dev_b)
5248 set_tx(pbpctl_dev_b, 1);
5249 set_tx(pbpctl_dev, 1);
5250 }
5251 return;
5252}
5253
5254int init_bypass_tpl_auto(bpctl_dev_t * pbpctl_dev)
5255{
5256 if (!pbpctl_dev)
5257 return -1;
5258 if (pbpctl_dev->bp_caps & TPL_CAP) {
5259 init_timer(&pbpctl_dev->bp_tpl_timer);
5260 pbpctl_dev->bp_tpl_timer.function = &bp_tpl_timer_fn;
5261 pbpctl_dev->bp_tpl_timer.data = (unsigned long)pbpctl_dev;
5262 return BP_OK;
5263 }
5264 return BP_NOT_CAP;
5265}
5266
5267int set_bypass_tpl_auto(bpctl_dev_t * pbpctl_dev, unsigned int param)
5268{
5269 if (!pbpctl_dev)
5270 return -1;
5271 if (pbpctl_dev->bp_caps & TPL_CAP) {
5272 if ((param) && (!pbpctl_dev->bp_tpl_flag)) {
5273 pbpctl_dev->bp_tpl_flag = param;
5274 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + 1);
5275 return BP_OK;
5276 };
5277 if ((!param) && (pbpctl_dev->bp_tpl_flag))
5278 remove_bypass_tpl_auto(pbpctl_dev);
5279
5280 return BP_OK;
5281 }
5282 return BP_NOT_CAP;
5283}
5284
5285int get_bypass_tpl_auto(bpctl_dev_t * pbpctl_dev)
5286{
5287 if (!pbpctl_dev)
5288 return -1;
5289 if (pbpctl_dev->bp_caps & TPL_CAP) {
5290 return pbpctl_dev->bp_tpl_flag;
5291 }
5292 return BP_NOT_CAP;
5293}
5294
5295int set_tpl_fn(bpctl_dev_t * pbpctl_dev, int tpl_mode)
5296{
5297
5298 bpctl_dev_t *pbpctl_dev_b = NULL;
5299 if (!pbpctl_dev)
5300 return -1;
5301
5302 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5303
5304 if (pbpctl_dev->bp_caps & TPL_CAP) {
5305 if (tpl_mode) {
5306 if ((pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5307 set_tx(pbpctl_dev_b, 1);
5308 set_tx(pbpctl_dev, 1);
5309 }
5310 if ((TPL_IF_SERIES(pbpctl_dev->subdevice)) ||
5311 (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)) {
5312 pbpctl_dev->bp_tpl_flag = tpl_mode;
5313 if (!tpl_mode)
5314 tpl_hw_off(pbpctl_dev);
5315 else
5316 tpl_hw_on(pbpctl_dev);
5317 } else
5318 set_bypass_tpl_auto(pbpctl_dev, tpl_mode);
5319 return 0;
5320 }
5321 return BP_NOT_CAP;
5322}
5323
5324int get_tpl_fn(bpctl_dev_t * pbpctl_dev)
5325{
5326 int ret = BP_NOT_CAP;
5327 if (!pbpctl_dev)
5328 return -1;
5329
5330 if (pbpctl_dev->bp_caps & TPL_CAP) {
5331 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)
5332 return (tpl2_flag_status(pbpctl_dev));
5333 ret = pbpctl_dev->bp_tpl_flag;
5334 }
5335 return ret;
5336}
5337
5338//#ifdef PMC_FIX_FLAG
5339int set_bp_wait_at_pwup_fn(bpctl_dev_t * pbpctl_dev, int tap_mode)
5340{
5341 if (!pbpctl_dev)
5342 return -1;
5343
5344 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5345 //bp_lock(pbp_device_block);
5346 cmnd_on(pbpctl_dev);
5347 if (!tap_mode)
5348 bp_wait_at_pwup_dis(pbpctl_dev);
5349 else
5350 bp_wait_at_pwup_en(pbpctl_dev);
5351 cmnd_off(pbpctl_dev);
5352
5353 // bp_unlock(pbp_device_block);
5354 return BP_OK;
5355 }
5356 return BP_NOT_CAP;
5357}
5358
5359int get_bp_wait_at_pwup_fn(bpctl_dev_t * pbpctl_dev)
5360{
5361 int ret = 0;
5362 if (!pbpctl_dev)
5363 return -1;
5364
5365 // bp_lock(pbp_device_block);
5366 ret = bp_wait_at_pwup_status(pbpctl_dev);
5367 // bp_unlock(pbp_device_block);
5368
5369 return ret;
5370}
5371
5372int set_bp_hw_reset_fn(bpctl_dev_t * pbpctl_dev, int tap_mode)
5373{
5374 if (!pbpctl_dev)
5375 return -1;
5376
5377 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
5378 // bp_lock(pbp_device_block);
5379 cmnd_on(pbpctl_dev);
5380
5381 if (!tap_mode)
5382 bp_hw_reset_dis(pbpctl_dev);
5383 else
5384 bp_hw_reset_en(pbpctl_dev);
5385 cmnd_off(pbpctl_dev);
5386 // bp_unlock(pbp_device_block);
5387 return BP_OK;
5388 }
5389 return BP_NOT_CAP;
5390}
5391
5392int get_bp_hw_reset_fn(bpctl_dev_t * pbpctl_dev)
5393{
5394 int ret = 0;
5395 if (!pbpctl_dev)
5396 return -1;
5397
5398 //bp_lock(pbp_device_block);
5399 ret = bp_hw_reset_status(pbpctl_dev);
5400
5401 //bp_unlock(pbp_device_block);
5402
5403 return ret;
5404}
5405
5406//#endif /*PMC_FIX_FLAG*/
5407
5408int get_bypass_info_fn(bpctl_dev_t * pbpctl_dev, char *dev_name,
5409 char *add_param)
5410{
5411 if (!pbpctl_dev)
5412 return -1;
5413 if (!is_bypass_fn(pbpctl_dev))
5414 return -1;
5415 strcpy(dev_name, pbpctl_dev->name);
5416 *add_param = pbpctl_dev->bp_fw_ver;
5417 return 0;
5418}
5419
5420int get_dev_idx_bsf(int bus, int slot, int func)
5421{
5422 int idx_dev = 0;
5423 //if_scan();
5424 for (idx_dev = 0;
5425 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5426 idx_dev++) {
5427 if ((bus == bpctl_dev_arr[idx_dev].bus)
5428 && (slot == bpctl_dev_arr[idx_dev].slot)
5429 && (func == bpctl_dev_arr[idx_dev].func))
5430
5431 return idx_dev;
5432 }
5433 return -1;
5434}
5435
5436static void str_low(char *str)
5437{
5438 int i;
5439
5440 for (i = 0; i < strlen(str); i++)
5441 if ((str[i] >= 65) && (str[i] <= 90))
5442 str[i] += 32;
5443}
5444
5445static unsigned long str_to_hex(char *p)
5446{
5447 unsigned long hex = 0;
5448 unsigned long length = strlen(p), shift = 0;
5449 unsigned char dig = 0;
5450
5451 str_low(p);
5452 length = strlen(p);
5453
5454 if (length == 0)
5455 return 0;
5456
5457 do {
5458 dig = p[--length];
5459 dig = dig < 'a' ? (dig - '0') : (dig - 'a' + 0xa);
5460 hex |= (dig << shift);
5461 shift += 4;
5462 } while (length);
5463 return hex;
5464}
5465
5466static int get_dev_idx(int ifindex)
5467{
5468 int idx_dev = 0;
5469
5470 for (idx_dev = 0;
5471 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5472 idx_dev++) {
5473 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5474 return idx_dev;
5475 }
5476
5477 return -1;
5478}
5479
5480static bpctl_dev_t *get_dev_idx_p(int ifindex)
5481{
5482 int idx_dev = 0;
5483
5484 for (idx_dev = 0;
5485 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5486 idx_dev++) {
5487 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5488 return &bpctl_dev_arr[idx_dev];
5489 }
5490
5491 return NULL;
5492}
5493
5494static void if_scan_init(void)
5495{
5496 int idx_dev = 0;
5497 struct net_device *dev;
5498 int ifindex;
5499 //rcu_read_lock();
5500 //rtnl_lock();
5501 //rcu_read_lock();
5502#if 1
5503#if (LINUX_VERSION_CODE >= 0x020618)
5504 for_each_netdev(&init_net, dev)
5505#elif (LINUX_VERSION_CODE >= 0x20616)
5506 for_each_netdev(dev)
5507#else
5508 for (dev = dev_base; dev; dev = dev->next)
5509#endif
5510 {
5511
5512 struct ethtool_drvinfo drvinfo;
5513 // char *str=NULL;
5514 char cbuf[32];
5515 char *buf = NULL;
5516 char res[10];
5517 int i = 0;
5518 int bus = 0, slot = 0, func = 0;
5519 ifindex = dev->ifindex;
5520
5521 memset(res, 0, 10);
5522 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
5523
5524 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5525 memset(&drvinfo, 0, sizeof(drvinfo));
5526 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5527 } else
5528 continue;
5529 if (!drvinfo.bus_info)
5530 continue;
5531 if (!strcmp(drvinfo.bus_info, "N/A"))
5532 continue;
5533 memcpy(&cbuf, drvinfo.bus_info, 32);
5534 buf = &cbuf[0];
5535
5536 // while(*buf++){
5537
5538 /*if(*buf==':'){
5539 buf++;
5540 break;
5541 } */
5542 //}
5543 while (*buf++ != ':') ;
5544 for (i = 0; i < 10; i++, buf++) {
5545 if (*buf == ':')
5546 break;
5547 res[i] = *buf;
5548
5549 }
5550 buf++;
5551 bus = str_to_hex(res);
5552 memset(res, 0, 10);
5553
5554 for (i = 0; i < 10; i++, buf++) {
5555 if (*buf == '.')
5556 break;
5557 res[i] = *buf;
5558
5559 }
5560 buf++;
5561 slot = str_to_hex(res);
5562 func = str_to_hex(buf);
5563 idx_dev = get_dev_idx_bsf(bus, slot, func);
5564
5565 if (idx_dev != -1) {
5566
5567 bpctl_dev_arr[idx_dev].ifindex = ifindex;
5568 bpctl_dev_arr[idx_dev].ndev = dev;
5569
5570 }
5571
5572 }
5573#endif
5574 //rtnl_unlock();
5575 //rcu_read_unlock();
5576
5577}
5578
5579#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
5580static int device_ioctl(struct inode *inode, /* see include/linux/fs.h */
5581 struct file *file, /* ditto */
5582 unsigned int ioctl_num, /* number and param for ioctl */
5583 unsigned long ioctl_param)
5584#else
5585static long device_ioctl(struct file *file, /* ditto */
5586 unsigned int ioctl_num, /* number and param for ioctl */
5587 unsigned long ioctl_param)
5588#endif
5589{
5590 struct bpctl_cmd bpctl_cmd;
5591 int dev_idx = 0;
5592 bpctl_dev_t *pbpctl_dev_out;
5593 void __user *argp = (void __user *)ioctl_param;
5594 int ret = 0;
5595 unsigned long flags;
5596
5597 static bpctl_dev_t *pbpctl_dev;
5598
5599#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
5600 //lock_kernel();
5601#endif
5602 lock_bpctl();
5603 //local_irq_save(flags);
5604 /*if(!spin_trylock_irqsave(&bpvm_lock)){
5605 local_irq_restore(flags);
5606 //unlock_bpctl();
5607 //unlock_kernel();
5608 return -1;
5609 } */
5610 //spin_lock_irqsave(&bpvm_lock, flags);
5611
5612/*
5613* Switch according to the ioctl called
5614*/
5615 if (ioctl_num == IOCTL_TX_MSG(IF_SCAN)) {
5616 if_scan_init();
5617 ret = SUCCESS;
5618 goto bp_exit;
5619 }
5620 if (copy_from_user(&bpctl_cmd, argp, sizeof(struct bpctl_cmd))) {
5621
5622 ret = -EFAULT;
5623 goto bp_exit;
5624 }
5625
5626 if (ioctl_num == IOCTL_TX_MSG(GET_DEV_NUM)) {
5627 bpctl_cmd.out_param[0] = device_num;
5628 if (copy_to_user
5629 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5630 ret = -EFAULT;
5631 goto bp_exit;
5632 }
5633 ret = SUCCESS;
5634 goto bp_exit;
5635
5636 }
5637 //lock_bpctl();
5638 //preempt_disable();
5639 local_irq_save(flags);
5640 if (!spin_trylock(&bpvm_lock)) {
5641 local_irq_restore(flags);
5642 unlock_bpctl();
5643 //unlock_kernel();
5644 return -1;
5645 }
5646// preempt_disable();
5647 //rcu_read_lock();
5648// spin_lock_irqsave(&bpvm_lock, flags);
5649 if ((bpctl_cmd.in_param[5]) ||
5650 (bpctl_cmd.in_param[6]) || (bpctl_cmd.in_param[7]))
5651 dev_idx = get_dev_idx_bsf(bpctl_cmd.in_param[5],
5652 bpctl_cmd.in_param[6],
5653 bpctl_cmd.in_param[7]);
5654 else if (bpctl_cmd.in_param[1] == 0)
5655 dev_idx = bpctl_cmd.in_param[0];
5656 else
5657 dev_idx = get_dev_idx(bpctl_cmd.in_param[1]);
5658
5659 if (dev_idx < 0 || dev_idx > device_num) {
5660 //unlock_bpctl();
5661 //preempt_enable();
5662 ret = -EOPNOTSUPP;
5663 //preempt_enable();
5664 //rcu_read_unlock();
5665 spin_unlock_irqrestore(&bpvm_lock, flags);
5666 goto bp_exit;
5667 }
5668
5669 bpctl_cmd.out_param[0] = bpctl_dev_arr[dev_idx].bus;
5670 bpctl_cmd.out_param[1] = bpctl_dev_arr[dev_idx].slot;
5671 bpctl_cmd.out_param[2] = bpctl_dev_arr[dev_idx].func;
5672 bpctl_cmd.out_param[3] = bpctl_dev_arr[dev_idx].ifindex;
5673
5674 if ((bpctl_dev_arr[dev_idx].bp_10gb)
5675 && (!(bpctl_dev_arr[dev_idx].ifindex))) {
5676 printk("Please load network driver for %s adapter!\n",
5677 bpctl_dev_arr[dev_idx].name);
5678 bpctl_cmd.status = -1;
5679 ret = SUCCESS;
5680 /*preempt_enable(); */
5681 //rcu_read_unlock();
5682 spin_unlock_irqrestore(&bpvm_lock, flags);
5683 goto bp_exit;
5684
5685 }
5686 if ((bpctl_dev_arr[dev_idx].bp_10gb) && (bpctl_dev_arr[dev_idx].ndev)) {
5687 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5688 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5689 printk
5690 ("Please bring up network interfaces for %s adapter!\n",
5691 bpctl_dev_arr[dev_idx].name);
5692 bpctl_cmd.status = -1;
5693 ret = SUCCESS;
5694 /*preempt_enable(); */
5695 //rcu_read_unlock();
5696 spin_unlock_irqrestore(&bpvm_lock, flags);
5697 goto bp_exit;
5698 }
5699
5700 }
5701 }
5702
5703 if ((dev_idx < 0) || (dev_idx > device_num)
5704 || (bpctl_dev_arr[dev_idx].pdev == NULL)) {
5705 bpctl_cmd.status = -1;
5706 goto bpcmd_exit;
5707 }
5708
5709 pbpctl_dev = &bpctl_dev_arr[dev_idx];
5710
5711 switch (ioctl_num) {
5712 case IOCTL_TX_MSG(SET_BYPASS_PWOFF):
5713 bpctl_cmd.status =
5714 set_bypass_pwoff_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5715 break;
5716
5717 case IOCTL_TX_MSG(GET_BYPASS_PWOFF):
5718 bpctl_cmd.status = get_bypass_pwoff_fn(pbpctl_dev);
5719 break;
5720
5721 case IOCTL_TX_MSG(SET_BYPASS_PWUP):
5722 bpctl_cmd.status =
5723 set_bypass_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5724 break;
5725
5726 case IOCTL_TX_MSG(GET_BYPASS_PWUP):
5727 bpctl_cmd.status = get_bypass_pwup_fn(pbpctl_dev);
5728 break;
5729
5730 case IOCTL_TX_MSG(SET_BYPASS_WD):
5731 bpctl_cmd.status =
5732 set_bypass_wd_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5733 break;
5734
5735 case IOCTL_TX_MSG(GET_BYPASS_WD):
5736 bpctl_cmd.status =
5737 get_bypass_wd_fn(pbpctl_dev, (int *)&(bpctl_cmd.data[0]));
5738 break;
5739
5740 case IOCTL_TX_MSG(GET_WD_EXPIRE_TIME):
5741 bpctl_cmd.status =
5742 get_wd_expire_time_fn(pbpctl_dev,
5743 (int *)&(bpctl_cmd.data[0]));
5744 break;
5745
5746 case IOCTL_TX_MSG(RESET_BYPASS_WD_TIMER):
5747 bpctl_cmd.status = reset_bypass_wd_timer_fn(pbpctl_dev);
5748 break;
5749
5750 case IOCTL_TX_MSG(GET_WD_SET_CAPS):
5751 bpctl_cmd.status = get_wd_set_caps_fn(pbpctl_dev);
5752 break;
5753
5754 case IOCTL_TX_MSG(SET_STD_NIC):
5755 bpctl_cmd.status =
5756 set_std_nic_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5757 break;
5758
5759 case IOCTL_TX_MSG(GET_STD_NIC):
5760 bpctl_cmd.status = get_std_nic_fn(pbpctl_dev);
5761 break;
5762
5763 case IOCTL_TX_MSG(SET_TAP):
5764 bpctl_cmd.status =
5765 set_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5766 break;
5767
5768 case IOCTL_TX_MSG(GET_TAP):
5769 bpctl_cmd.status = get_tap_fn(pbpctl_dev);
5770 break;
5771
5772 case IOCTL_TX_MSG(GET_TAP_CHANGE):
5773 bpctl_cmd.status = get_tap_change_fn(pbpctl_dev);
5774 break;
5775
5776 case IOCTL_TX_MSG(SET_DIS_TAP):
5777 bpctl_cmd.status =
5778 set_dis_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5779 break;
5780
5781 case IOCTL_TX_MSG(GET_DIS_TAP):
5782 bpctl_cmd.status = get_dis_tap_fn(pbpctl_dev);
5783 break;
5784
5785 case IOCTL_TX_MSG(SET_TAP_PWUP):
5786 bpctl_cmd.status =
5787 set_tap_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5788 break;
5789
5790 case IOCTL_TX_MSG(GET_TAP_PWUP):
5791 bpctl_cmd.status = get_tap_pwup_fn(pbpctl_dev);
5792 break;
5793
5794 case IOCTL_TX_MSG(SET_WD_EXP_MODE):
5795 bpctl_cmd.status =
5796 set_wd_exp_mode_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5797 break;
5798
5799 case IOCTL_TX_MSG(GET_WD_EXP_MODE):
5800 bpctl_cmd.status = get_wd_exp_mode_fn(pbpctl_dev);
5801 break;
5802
5803 case IOCTL_TX_MSG(GET_DIS_BYPASS):
5804 bpctl_cmd.status = get_dis_bypass_fn(pbpctl_dev);
5805 break;
5806
5807 case IOCTL_TX_MSG(SET_DIS_BYPASS):
5808 bpctl_cmd.status =
5809 set_dis_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5810 break;
5811
5812 case IOCTL_TX_MSG(GET_BYPASS_CHANGE):
5813 bpctl_cmd.status = get_bypass_change_fn(pbpctl_dev);
5814 break;
5815
5816 case IOCTL_TX_MSG(GET_BYPASS):
5817 bpctl_cmd.status = get_bypass_fn(pbpctl_dev);
5818 break;
5819
5820 case IOCTL_TX_MSG(SET_BYPASS):
5821 bpctl_cmd.status =
5822 set_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5823 break;
5824
5825 case IOCTL_TX_MSG(GET_BYPASS_CAPS):
5826 bpctl_cmd.status = get_bypass_caps_fn(pbpctl_dev);
5827 /*preempt_enable(); */
5828 //rcu_read_unlock();
5829 spin_unlock_irqrestore(&bpvm_lock, flags);
5830 if (copy_to_user
5831 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5832 //unlock_bpctl();
5833 //preempt_enable();
5834 ret = -EFAULT;
5835 goto bp_exit;
5836 }
5837 goto bp_exit;
5838
5839 case IOCTL_TX_MSG(GET_BYPASS_SLAVE):
5840 bpctl_cmd.status =
5841 get_bypass_slave_fn(pbpctl_dev, &pbpctl_dev_out);
5842 if (bpctl_cmd.status == 1) {
5843 bpctl_cmd.out_param[4] = pbpctl_dev_out->bus;
5844 bpctl_cmd.out_param[5] = pbpctl_dev_out->slot;
5845 bpctl_cmd.out_param[6] = pbpctl_dev_out->func;
5846 bpctl_cmd.out_param[7] = pbpctl_dev_out->ifindex;
5847 }
5848 break;
5849
5850 case IOCTL_TX_MSG(IS_BYPASS):
5851 bpctl_cmd.status = is_bypass(pbpctl_dev);
5852 break;
5853 case IOCTL_TX_MSG(SET_TX):
5854 bpctl_cmd.status = set_tx_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5855 break;
5856 case IOCTL_TX_MSG(GET_TX):
5857 bpctl_cmd.status = get_tx_fn(pbpctl_dev);
5858 break;
5859 case IOCTL_TX_MSG(SET_WD_AUTORESET):
5860 bpctl_cmd.status =
5861 set_wd_autoreset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5862
5863 break;
5864 case IOCTL_TX_MSG(GET_WD_AUTORESET):
5865
5866 bpctl_cmd.status = get_wd_autoreset_fn(pbpctl_dev);
5867 break;
5868 case IOCTL_TX_MSG(SET_DISC):
5869 bpctl_cmd.status =
5870 set_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5871 break;
5872 case IOCTL_TX_MSG(GET_DISC):
5873 bpctl_cmd.status = get_disc_fn(pbpctl_dev);
5874 break;
5875 case IOCTL_TX_MSG(GET_DISC_CHANGE):
5876 bpctl_cmd.status = get_disc_change_fn(pbpctl_dev);
5877 break;
5878 case IOCTL_TX_MSG(SET_DIS_DISC):
5879 bpctl_cmd.status =
5880 set_dis_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5881 break;
5882 case IOCTL_TX_MSG(GET_DIS_DISC):
5883 bpctl_cmd.status = get_dis_disc_fn(pbpctl_dev);
5884 break;
5885 case IOCTL_TX_MSG(SET_DISC_PWUP):
5886 bpctl_cmd.status =
5887 set_disc_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5888 break;
5889 case IOCTL_TX_MSG(GET_DISC_PWUP):
5890 bpctl_cmd.status = get_disc_pwup_fn(pbpctl_dev);
5891 break;
5892
5893 case IOCTL_TX_MSG(GET_BYPASS_INFO):
5894
5895 bpctl_cmd.status =
5896 get_bypass_info_fn(pbpctl_dev, (char *)&bpctl_cmd.data,
5897 (char *)&bpctl_cmd.out_param[4]);
5898 break;
5899
5900 case IOCTL_TX_MSG(SET_TPL):
5901 bpctl_cmd.status =
5902 set_tpl_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5903 break;
5904
5905 case IOCTL_TX_MSG(GET_TPL):
5906 bpctl_cmd.status = get_tpl_fn(pbpctl_dev);
5907 break;
5908//#ifdef PMC_FIX_FLAG
5909 case IOCTL_TX_MSG(SET_BP_WAIT_AT_PWUP):
5910 bpctl_cmd.status =
5911 set_bp_wait_at_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5912 break;
5913
5914 case IOCTL_TX_MSG(GET_BP_WAIT_AT_PWUP):
5915 bpctl_cmd.status = get_bp_wait_at_pwup_fn(pbpctl_dev);
5916 break;
5917 case IOCTL_TX_MSG(SET_BP_HW_RESET):
5918 bpctl_cmd.status =
5919 set_bp_hw_reset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5920 break;
5921
5922 case IOCTL_TX_MSG(GET_BP_HW_RESET):
5923 bpctl_cmd.status = get_bp_hw_reset_fn(pbpctl_dev);
5924 break;
5925//#endif
5926#ifdef BP_SELF_TEST
5927 case IOCTL_TX_MSG(SET_BP_SELF_TEST):
5928 bpctl_cmd.status =
5929 set_bp_self_test_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5930
5931 break;
5932 case IOCTL_TX_MSG(GET_BP_SELF_TEST):
5933 bpctl_cmd.status = get_bp_self_test_fn(pbpctl_dev);
5934 break;
5935
5936#endif
5937#if 0
5938 case IOCTL_TX_MSG(SET_DISC_PORT):
5939 bpctl_cmd.status =
5940 set_disc_port_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5941 break;
5942
5943 case IOCTL_TX_MSG(GET_DISC_PORT):
5944 bpctl_cmd.status = get_disc_port_fn(pbpctl_dev);
5945 break;
5946
5947 case IOCTL_TX_MSG(SET_DISC_PORT_PWUP):
5948 bpctl_cmd.status =
5949 set_disc_port_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5950 break;
5951
5952 case IOCTL_TX_MSG(GET_DISC_PORT_PWUP):
5953 bpctl_cmd.status = get_disc_port_pwup_fn(pbpctl_dev);
5954 break;
5955#endif
5956 case IOCTL_TX_MSG(SET_BP_FORCE_LINK):
5957 bpctl_cmd.status =
5958 set_bp_force_link_fn(dev_idx, bpctl_cmd.in_param[2]);
5959 break;
5960
5961 case IOCTL_TX_MSG(GET_BP_FORCE_LINK):
5962 bpctl_cmd.status = get_bp_force_link_fn(dev_idx);
5963 break;
5964
5965 default:
5966 // unlock_bpctl();
5967
5968 ret = -EOPNOTSUPP;
5969 /*preempt_enable(); */
5970 //rcu_read_unlock();
5971 spin_unlock_irqrestore(&bpvm_lock, flags);
5972 goto bp_exit;
5973 }
5974 //unlock_bpctl();
5975 /*preempt_enable(); */
5976 bpcmd_exit:
5977 //rcu_read_unlock();
5978 spin_unlock_irqrestore(&bpvm_lock, flags);
5979 if (copy_to_user(argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd)))
5980 ret = -EFAULT;
5981 ret = SUCCESS;
5982 bp_exit:
5983#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
5984 //unlock_kernel();
5985#endif
5986 //spin_unlock_irqrestore(&bpvm_lock, flags);
5987 unlock_bpctl();
5988 //unlock_kernel();
5989 return ret;
5990}
5991
5992struct file_operations Fops = {
5993 .owner = THIS_MODULE,
5994#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
5995 .ioctl = device_ioctl,
5996#else
5997 .unlocked_ioctl = device_ioctl,
5998#endif
5999
6000 .open = device_open,
6001 .release = device_release, /* a.k.a. close */
6002};
6003
6004#ifndef PCI_DEVICE
6005#define PCI_DEVICE(vend,dev) \
6006 .vendor = (vend), .device = (dev), \
6007 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
6008#endif
6009
6010#define SILICOM_E1000BP_ETHERNET_DEVICE(device_id) {\
6011 PCI_DEVICE(SILICOM_VID, device_id)}
6012
6013typedef enum {
6014 PXG2BPFI,
6015 PXG2BPFIL,
6016 PXG2BPFILX,
6017 PXG2BPFILLX,
6018 PXGBPI,
6019 PXGBPIG,
6020 PXG2TBFI,
6021 PXG4BPI,
6022 PXG4BPFI,
6023 PEG4BPI,
6024 PEG2BPI,
6025 PEG4BPIN,
6026 PEG2BPFI,
6027 PEG2BPFILX,
6028 PMCXG2BPFI,
6029 PMCXG2BPFIN,
6030 PEG4BPII,
6031 PEG4BPFII,
6032 PXG4BPFILX,
6033 PMCXG2BPIN,
6034 PMCXG4BPIN,
6035 PXG2BISC1,
6036 PEG2TBFI,
6037 PXG2TBI,
6038 PXG4BPFID,
6039 PEG4BPFI,
6040 PEG4BPIPT,
6041 PXG6BPI,
6042 PEG4BPIL,
6043 PMCXG2BPIN2,
6044 PMCXG4BPIN2,
6045 PMCX2BPI,
6046 PEG2BPFID,
6047 PEG2BPFIDLX,
6048 PMCX4BPI,
6049 MEG2BPFILN,
6050 MEG2BPFINX,
6051 PEG4BPFILX,
6052 PE10G2BPISR,
6053 PE10G2BPILR,
6054 MHIO8AD,
6055 PE10G2BPICX4,
6056 PEG2BPI5,
6057 PEG6BPI,
6058 PEG4BPFI5,
6059 PEG4BPFI5LX,
6060 MEG2BPFILXLN,
6061 PEG2BPIX1,
6062 MEG2BPFILXNX,
6063 XE10G2BPIT,
6064 XE10G2BPICX4,
6065 XE10G2BPISR,
6066 XE10G2BPILR,
6067 PEG4BPIIO,
6068 XE10G2BPIXR,
6069 PE10GDBISR,
6070 PE10GDBILR,
6071 PEG2BISC6,
6072 PEG6BPIFC,
6073 PE10G2BPTCX4,
6074 PE10G2BPTSR,
6075 PE10G2BPTLR,
6076 PE10G2BPTT,
6077 PEG4BPI6,
6078 PEG4BPFI6,
6079 PEG4BPFI6LX,
6080 PEG4BPFI6ZX,
6081 PEG2BPI6,
6082 PEG2BPFI6,
6083 PEG2BPFI6LX,
6084 PEG2BPFI6ZX,
6085 PEG2BPFI6FLXM,
6086 PEG4BPI6FC,
6087 PEG4BPFI6FC,
6088 PEG4BPFI6FCLX,
6089 PEG4BPFI6FCZX,
6090 PEG6BPI6,
6091 PEG2BPI6SC6,
6092 MEG2BPI6,
6093 XEG2BPI6,
6094 MEG4BPI6,
6095 PEG2BPFI5,
6096 PEG2BPFI5LX,
6097 PXEG4BPFI,
6098 M1EG2BPI6,
6099 M1EG2BPFI6,
6100 M1EG2BPFI6LX,
6101 M1EG2BPFI6ZX,
6102 M1EG4BPI6,
6103 M1EG4BPFI6,
6104 M1EG4BPFI6LX,
6105 M1EG4BPFI6ZX,
6106 M1EG6BPI6,
6107 M1E2G4BPi80,
6108 M1E2G4BPFi80,
6109 M1E2G4BPFi80LX,
6110 M1E2G4BPFi80ZX,
6111 PE210G2SPI9,
6112 M1E10G2BPI9CX4,
6113 M1E10G2BPI9SR,
6114 M1E10G2BPI9LR,
6115 M1E10G2BPI9T,
6116 PE210G2BPI9CX4,
6117 PE210G2BPI9SR,
6118 PE210G2BPI9LR,
6119 PE210G2BPI9T,
6120 M2EG2BPFI6,
6121 M2EG2BPFI6LX,
6122 M2EG2BPFI6ZX,
6123 M2EG4BPI6,
6124 M2EG4BPFI6,
6125 M2EG4BPFI6LX,
6126 M2EG4BPFI6ZX,
6127 M2EG6BPI6,
6128 PEG2DBI6,
6129 PEG2DBFI6,
6130 PEG2DBFI6LX,
6131 PEG2DBFI6ZX,
6132 PE2G4BPi80,
6133 PE2G4BPFi80,
6134 PE2G4BPFi80LX,
6135 PE2G4BPFi80ZX,
6136 PE2G4BPi80L,
6137 M6E2G8BPi80A,
6138
6139 PE2G2BPi35,
6140 PAC1200BPi35,
6141 PE2G2BPFi35,
6142 PE2G2BPFi35LX,
6143 PE2G2BPFi35ZX,
6144 PE2G4BPi35,
6145 PE2G4BPi35L,
6146 PE2G4BPFi35,
6147 PE2G4BPFi35LX,
6148 PE2G4BPFi35ZX,
6149
6150 PE2G6BPi35,
6151 PE2G6BPi35CX,
6152
6153 PE2G2BPi80,
6154 PE2G2BPFi80,
6155 PE2G2BPFi80LX,
6156 PE2G2BPFi80ZX,
6157 M2E10G2BPI9CX4,
6158 M2E10G2BPI9SR,
6159 M2E10G2BPI9LR,
6160 M2E10G2BPI9T,
6161 M6E2G8BPi80,
6162 PE210G2DBi9SR,
6163 PE210G2DBi9SRRB,
6164 PE210G2DBi9LR,
6165 PE210G2DBi9LRRB,
6166 PE310G4DBi940SR,
6167 PE310G4BPi9T,
6168 PE310G4BPi9SR,
6169 PE310G4BPi9LR,
6170 PE210G2BPi40,
6171} board_t;
6172
6173typedef struct _bpmod_info_t {
6174 unsigned int vendor;
6175 unsigned int device;
6176 unsigned int subvendor;
6177 unsigned int subdevice;
6178 unsigned int index;
6179 char *bp_name;
6180
6181} bpmod_info_t;
6182
6183typedef struct _dev_desc {
6184 char *name;
6185} dev_desc_t;
6186
6187dev_desc_t dev_desc[] = {
6188 {"Silicom Bypass PXG2BPFI-SD series adapter"},
6189 {"Silicom Bypass PXG2BPFIL-SD series adapter"},
6190 {"Silicom Bypass PXG2BPFILX-SD series adapter"},
6191 {"Silicom Bypass PXG2BPFILLX-SD series adapter"},
6192 {"Silicom Bypass PXG2BPI-SD series adapter"},
6193 {"Silicom Bypass PXG2BPIG-SD series adapter"},
6194 {"Silicom Bypass PXG2TBFI-SD series adapter"},
6195 {"Silicom Bypass PXG4BPI-SD series adapter"},
6196 {"Silicom Bypass PXG4BPFI-SD series adapter"},
6197 {"Silicom Bypass PEG4BPI-SD series adapter"},
6198 {"Silicom Bypass PEG2BPI-SD series adapter"},
6199 {"Silicom Bypass PEG4BPIN-SD series adapter"},
6200 {"Silicom Bypass PEG2BPFI-SD series adapter"},
6201 {"Silicom Bypass PEG2BPFI-LX-SD series adapter"},
6202 {"Silicom Bypass PMCX2BPFI-SD series adapter"},
6203 {"Silicom Bypass PMCX2BPFI-N series adapter"},
6204 {"Intel Bypass PEG2BPII series adapter"},
6205 {"Intel Bypass PEG2BPFII series adapter"},
6206 {"Silicom Bypass PXG4BPFILX-SD series adapter"},
6207 {"Silicom Bypass PMCX2BPI-N series adapter"},
6208 {"Silicom Bypass PMCX4BPI-N series adapter"},
6209 {"Silicom Bypass PXG2BISC1-SD series adapter"},
6210 {"Silicom Bypass PEG2TBFI-SD series adapter"},
6211 {"Silicom Bypass PXG2TBI-SD series adapter"},
6212 {"Silicom Bypass PXG4BPFID-SD series adapter"},
6213 {"Silicom Bypass PEG4BPFI-SD series adapter"},
6214 {"Silicom Bypass PEG4BPIPT-SD series adapter"},
6215 {"Silicom Bypass PXG6BPI-SD series adapter"},
6216 {"Silicom Bypass PEG4BPIL-SD series adapter"},
6217 {"Silicom Bypass PMCX2BPI-N2 series adapter"},
6218 {"Silicom Bypass PMCX4BPI-N2 series adapter"},
6219 {"Silicom Bypass PMCX2BPI-SD series adapter"},
6220 {"Silicom Bypass PEG2BPFID-SD series adapter"},
6221 {"Silicom Bypass PEG2BPFIDLX-SD series adapter"},
6222 {"Silicom Bypass PMCX4BPI-SD series adapter"},
6223 {"Silicom Bypass MEG2BPFILN-SD series adapter"},
6224 {"Silicom Bypass MEG2BPFINX-SD series adapter"},
6225 {"Silicom Bypass PEG4BPFILX-SD series adapter"},
6226 {"Silicom Bypass PE10G2BPISR-SD series adapter"},
6227 {"Silicom Bypass PE10G2BPILR-SD series adapter"},
6228 {"Silicom Bypass MHIO8AD-SD series adapter"},
6229 {"Silicom Bypass PE10G2BPICX4-SD series adapter"},
6230 {"Silicom Bypass PEG2BPI5-SD series adapter"},
6231 {"Silicom Bypass PEG6BPI5-SD series adapter"},
6232 {"Silicom Bypass PEG4BPFI5-SD series adapter"},
6233 {"Silicom Bypass PEG4BPFI5LX-SD series adapter"},
6234 {"Silicom Bypass MEG2BPFILXLN-SD series adapter"},
6235 {"Silicom Bypass PEG2BPIX1-SD series adapter"},
6236 {"Silicom Bypass MEG2BPFILXNX-SD series adapter"},
6237 {"Silicom Bypass XE10G2BPIT-SD series adapter"},
6238 {"Silicom Bypass XE10G2BPICX4-SD series adapter"},
6239 {"Silicom Bypass XE10G2BPISR-SD series adapter"},
6240 {"Silicom Bypass XE10G2BPILR-SD series adapter"},
6241 {"Intel Bypass PEG2BPFII0 series adapter"},
6242 {"Silicom Bypass XE10G2BPIXR series adapter"},
6243 {"Silicom Bypass PE10G2DBISR series adapter"},
6244 {"Silicom Bypass PEG2BI5SC6 series adapter"},
6245 {"Silicom Bypass PEG6BPI5FC series adapter"},
6246
6247 {"Silicom Bypass PE10G2BPTCX4 series adapter"},
6248 {"Silicom Bypass PE10G2BPTSR series adapter"},
6249 {"Silicom Bypass PE10G2BPTLR series adapter"},
6250 {"Silicom Bypass PE10G2BPTT series adapter"},
6251 {"Silicom Bypass PEG4BPI6 series adapter"},
6252 {"Silicom Bypass PEG4BPFI6 series adapter"},
6253 {"Silicom Bypass PEG4BPFI6LX series adapter"},
6254 {"Silicom Bypass PEG4BPFI6ZX series adapter"},
6255 {"Silicom Bypass PEG2BPI6 series adapter"},
6256 {"Silicom Bypass PEG2BPFI6 series adapter"},
6257 {"Silicom Bypass PEG2BPFI6LX series adapter"},
6258 {"Silicom Bypass PEG2BPFI6ZX series adapter"},
6259 {"Silicom Bypass PEG2BPFI6FLXM series adapter"},
6260 {"Silicom Bypass PEG4BPI6FC series adapter"},
6261 {"Silicom Bypass PEG4BPFI6FC series adapter"},
6262 {"Silicom Bypass PEG4BPFI6FCLX series adapter"},
6263 {"Silicom Bypass PEG4BPFI6FCZX series adapter"},
6264 {"Silicom Bypass PEG6BPI6 series adapter"},
6265 {"Silicom Bypass PEG2BPI6SC6 series adapter"},
6266 {"Silicom Bypass MEG2BPI6 series adapter"},
6267 {"Silicom Bypass XEG2BPI6 series adapter"},
6268 {"Silicom Bypass MEG4BPI6 series adapter"},
6269 {"Silicom Bypass PEG2BPFI5-SD series adapter"},
6270 {"Silicom Bypass PEG2BPFI5LX-SD series adapter"},
6271 {"Silicom Bypass PXEG4BPFI-SD series adapter"},
6272 {"Silicom Bypass MxEG2BPI6 series adapter"},
6273 {"Silicom Bypass MxEG2BPFI6 series adapter"},
6274 {"Silicom Bypass MxEG2BPFI6LX series adapter"},
6275 {"Silicom Bypass MxEG2BPFI6ZX series adapter"},
6276 {"Silicom Bypass MxEG4BPI6 series adapter"},
6277 {"Silicom Bypass MxEG4BPFI6 series adapter"},
6278 {"Silicom Bypass MxEG4BPFI6LX series adapter"},
6279 {"Silicom Bypass MxEG4BPFI6ZX series adapter"},
6280 {"Silicom Bypass MxEG6BPI6 series adapter"},
6281 {"Silicom Bypass MxE2G4BPi80 series adapter"},
6282 {"Silicom Bypass MxE2G4BPFi80 series adapter"},
6283 {"Silicom Bypass MxE2G4BPFi80LX series adapter"},
6284 {"Silicom Bypass MxE2G4BPFi80ZX series adapter"},
6285
6286 {"Silicom Bypass PE210G2SPI9 series adapter"},
6287
6288 {"Silicom Bypass MxE210G2BPI9CX4 series adapter"},
6289 {"Silicom Bypass MxE210G2BPI9SR series adapter"},
6290 {"Silicom Bypass MxE210G2BPI9LR series adapter"},
6291 {"Silicom Bypass MxE210G2BPI9T series adapter"},
6292
6293 {"Silicom Bypass PE210G2BPI9CX4 series adapter"},
6294 {"Silicom Bypass PE210G2BPI9SR series adapter"},
6295 {"Silicom Bypass PE210G2BPI9LR series adapter"},
6296 {"Silicom Bypass PE210G2BPI9T series adapter"},
6297
6298 {"Silicom Bypass M2EG2BPFI6 series adapter"},
6299 {"Silicom Bypass M2EG2BPFI6LX series adapter"},
6300 {"Silicom Bypass M2EG2BPFI6ZX series adapter"},
6301 {"Silicom Bypass M2EG4BPI6 series adapter"},
6302 {"Silicom Bypass M2EG4BPFI6 series adapter"},
6303 {"Silicom Bypass M2EG4BPFI6LX series adapter"},
6304 {"Silicom Bypass M2EG4BPFI6ZX series adapter"},
6305 {"Silicom Bypass M2EG6BPI6 series adapter"},
6306
6307 {"Silicom Bypass PEG2DBI6 series adapter"},
6308 {"Silicom Bypass PEG2DBFI6 series adapter"},
6309 {"Silicom Bypass PEG2DBFI6LX series adapter"},
6310 {"Silicom Bypass PEG2DBFI6ZX series adapter"},
6311
6312 {"Silicom Bypass PE2G4BPi80 series adapter"},
6313 {"Silicom Bypass PE2G4BPFi80 series adapter"},
6314 {"Silicom Bypass PE2G4BPFi80LX series adapter"},
6315 {"Silicom Bypass PE2G4BPFi80ZX series adapter"},
6316
6317 {"Silicom Bypass PE2G4BPi80L series adapter"},
6318 {"Silicom Bypass MxE2G8BPi80A series adapter"},
6319
6320 {"Silicom Bypass PE2G2BPi35 series adapter"},
6321 {"Silicom Bypass PAC1200BPi35 series adapter"},
6322 {"Silicom Bypass PE2G2BPFi35 series adapter"},
6323 {"Silicom Bypass PE2G2BPFi35LX series adapter"},
6324 {"Silicom Bypass PE2G2BPFi35ZX series adapter"},
6325
6326 {"Silicom Bypass PE2G4BPi35 series adapter"},
6327 {"Silicom Bypass PE2G4BPi35L series adapter"},
6328 {"Silicom Bypass PE2G4BPFi35 series adapter"},
6329 {"Silicom Bypass PE2G4BPFi35LX series adapter"},
6330 {"Silicom Bypass PE2G4BPFi35ZX series adapter"},
6331
6332 {"Silicom Bypass PE2G6BPi35 series adapter"},
6333 {"Silicom Bypass PE2G6BPi35CX series adapter"},
6334
6335 {"Silicom Bypass PE2G2BPi80 series adapter"},
6336 {"Silicom Bypass PE2G2BPFi80 series adapter"},
6337 {"Silicom Bypass PE2G2BPFi80LX series adapter"},
6338 {"Silicom Bypass PE2G2BPFi80ZX series adapter"},
6339
6340 {"Silicom Bypass M2E10G2BPI9CX4 series adapter"},
6341 {"Silicom Bypass M2E10G2BPI9SR series adapter"},
6342 {"Silicom Bypass M2E10G2BPI9LR series adapter"},
6343 {"Silicom Bypass M2E10G2BPI9T series adapter"},
6344 {"Silicom Bypass MxE2G8BPi80 series adapter"},
6345 {"Silicom Bypass PE210G2DBi9SR series adapter"},
6346 {"Silicom Bypass PE210G2DBi9SRRB series adapter"},
6347 {"Silicom Bypass PE210G2DBi9LR series adapter"},
6348 {"Silicom Bypass PE210G2DBi9LRRB series adapter"},
6349 {"Silicom Bypass PE310G4DBi9-SR series adapter"},
6350 {"Silicom Bypass PE310G4BPi9T series adapter"},
6351 {"Silicom Bypass PE310G4BPi9SR series adapter"},
6352 {"Silicom Bypass PE310G4BPi9LR series adapter"},
6353 {"Silicom Bypass PE210G2BPi40T series adapter"},
6354 {0},
6355};
6356
6357static bpmod_info_t tx_ctl_pci_tbl[] = {
6358 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFI_SSID, PXG2BPFI,
6359 "PXG2BPFI-SD"},
6360 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFIL_SSID, PXG2BPFIL,
6361 "PXG2BPFIL-SD"},
6362 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILX_SSID, PXG2BPFILX,
6363 "PXG2BPFILX-SD"},
6364 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILLX_SSID, PXG2BPFILLX,
6365 "PXG2BPFILLXSD"},
6366 {0x8086, 0x1010, SILICOM_SVID, SILICOM_PXGBPI_SSID, PXGBPI,
6367 "PXG2BPI-SD"},
6368 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXGBPIG_SSID, PXGBPIG,
6369 "PXG2BPIG-SD"},
6370 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2TBFI_SSID, PXG2TBFI,
6371 "PXG2TBFI-SD"},
6372 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6373 "PXG4BPI-SD"},
6374 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6375 "PXG4BPFI-SD"},
6376 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFILX_SSID, PXG4BPFILX,
6377 "PXG4BPFILX-SD"},
6378 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PEG4BPI_SSID, PEG4BPI,
6379 "PEXG4BPI-SD"},
6380 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPI_SSID, PEG2BPI,
6381 "PEG2BPI-SD"},
6382 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIN_SSID, PEG4BPIN,
6383 "PEG4BPI-SD"},
6384 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFI_SSID, PEG2BPFI,
6385 "PEG2BPFI-SD"},
6386 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFILX_SSID, PEG2BPFILX,
6387 "PEG2BPFILX-SD"},
6388 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PMCXG2BPFI_SSID, PMCXG2BPFI,
6389 "PMCX2BPFI-SD"},
6390 {0x8086, 0x107a, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPFIN_SSID,
6391 PMCXG2BPFIN, "PMCX2BPFI-N"},
6392 {0x8086, INTEL_PEG4BPII_PID, 0x8086, INTEL_PEG4BPII_SSID, PEG4BPII,
6393 "PEG4BPII"},
6394 {0x8086, INTEL_PEG4BPIIO_PID, 0x8086, INTEL_PEG4BPIIO_SSID, PEG4BPIIO,
6395 "PEG4BPII0"},
6396 {0x8086, INTEL_PEG4BPFII_PID, 0x8086, INTEL_PEG4BPFII_SSID, PEG4BPFII,
6397 "PEG4BPFII"},
6398 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN_SSID,
6399 PMCXG2BPIN, "PMCX2BPI-N"},
6400 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN_SSID,
6401 PMCXG4BPIN, "PMCX4BPI-N"},
6402 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6403 "PXG2BISC1-SD"},
6404 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2TBFI_SSID, PEG2TBFI,
6405 "PEG2TBFI-SD"},
6406 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6407 "PXG2TBI-SD"},
6408 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFID_SSID, PXG4BPFID,
6409 "PXG4BPFID-SD"},
6410 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6411 "PEG4BPFI-SD"},
6412 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIPT_SSID, PEG4BPIPT,
6413 "PEG4BPIPT-SD"},
6414 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG6BPI_SSID, PXG6BPI,
6415 "PXG6BPI-SD"},
6416 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6417 SILICOM_PEG4BPIL_SSID /*PCI_ANY_ID */ , PEG4BPIL, "PEG4BPIL-SD"},
6418 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN2_SSID,
6419 PMCXG2BPIN2, "PMCX2BPI-N2"},
6420 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN2_SSID,
6421 PMCXG4BPIN2, "PMCX4BPI-N2"},
6422 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX2BPI_SSID, PMCX2BPI,
6423 "PMCX2BPI-SD"},
6424 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX4BPI_SSID, PMCX4BPI,
6425 "PMCX4BPI-SD"},
6426 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFID_SSID, PEG2BPFID,
6427 "PEG2BPFID-SD"},
6428 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFIDLX_SSID, PEG2BPFIDLX,
6429 "PEG2BPFIDLXSD"},
6430 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILN_SSID, MEG2BPFILN,
6431 "MEG2BPFILN-SD"},
6432 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFINX_SSID, MEG2BPFINX,
6433 "MEG2BPFINX-SD"},
6434 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFILX_SSID, PEG4BPFILX,
6435 "PEG4BPFILX-SD"},
6436 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPISR_SSID,
6437 PE10G2BPISR, "PE10G2BPISR"},
6438 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPILR_SSID,
6439 PE10G2BPILR, "PE10G2BPILR"},
6440 {0x8086, 0x10a9, SILICOM_SVID, SILICOM_MHIO8AD_SSID, MHIO8AD,
6441 "MHIO8AD-SD"},
6442 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPICX4_SSID,
6443 PE10G2BPISR, "PE10G2BPICX4"},
6444 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6445 SILICOM_PEG2BPI5_SSID /*PCI_ANY_ID */ , PEG2BPI5, "PEG2BPI5-SD"},
6446 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6447 SILICOM_PEG6BPI_SSID /*PCI_ANY_ID */ , PEG6BPI, "PEG6BPI5"},
6448 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG4BPFI5_SSID,
6449 PEG4BPFI5, "PEG4BPFI5"},
6450 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6451 SILICOM_PEG4BPFI5LX_SSID, PEG4BPFI5LX, "PEG4BPFI5LX"},
6452 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXLN_SSID, MEG2BPFILXLN,
6453 "MEG2BPFILXLN"},
6454 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPIX1_SSID, PEG2BPIX1,
6455 "PEG2BPIX1-SD"},
6456 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXNX_SSID, MEG2BPFILXNX,
6457 "MEG2BPFILXNX"},
6458 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPIT_SSID, XE10G2BPIT,
6459 "XE10G2BPIT"},
6460 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPICX4_SSID,
6461 XE10G2BPICX4, "XE10G2BPICX4"},
6462 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPISR_SSID, XE10G2BPISR,
6463 "XE10G2BPISR"},
6464 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPILR_SSID, XE10G2BPILR,
6465 "XE10G2BPILR"},
6466 {0x8086, 0x10C6, NOKIA_XE10G2BPIXR_SVID, NOKIA_XE10G2BPIXR_SSID,
6467 XE10G2BPIXR, "XE10G2BPIXR"},
6468 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBISR_SSID, PE10GDBISR,
6469 "PE10G2DBISR"},
6470 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBILR_SSID, PE10GDBILR,
6471 "PE10G2DBILR"},
6472 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6473 SILICOM_PEG2BISC6_SSID /*PCI_ANY_ID */ , PEG2BISC6, "PEG2BI5SC6"},
6474 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6475 SILICOM_PEG6BPIFC_SSID /*PCI_ANY_ID */ , PEG6BPIFC, "PEG6BPI5FC"},
6476
6477 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6478 SILICOM_PE10G2BPTCX4_SSID, PE10G2BPTCX4, "PE10G2BPTCX4"},
6479 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6480 SILICOM_PE10G2BPTSR_SSID, PE10G2BPTSR, "PE10G2BPTSR"},
6481 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6482 SILICOM_PE10G2BPTLR_SSID, PE10G2BPTLR, "PE10G2BPTLR"},
6483 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6484 SILICOM_PE10G2BPTT_SSID, PE10G2BPTT, "PE10G2BPTT"},
6485
6486 //{BROADCOM_VID, BROADCOM_PE10G2_PID, PCI_ANY_ID, PCI_ANY_ID, PE10G2BPTCX4, "PE10G2BPTCX4"},
6487
6488 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6489 SILICOM_PEG4BPI6_SSID /*PCI_ANY_ID */ , PEG4BPI6, "PEG4BPI6"},
6490 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6491 SILICOM_PEG4BPFI6_SSID /*PCI_ANY_ID */ , PEG4BPFI6, "PEG4BPFI6"},
6492 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6493 SILICOM_PEG4BPFI6LX_SSID /*PCI_ANY_ID */ , PEG4BPFI6LX, "PEG4BPFI6LX"},
6494 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6495 SILICOM_PEG4BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6ZX, "PEG4BPFI6ZX"},
6496 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6497 SILICOM_PEG2BPI6_SSID /*PCI_ANY_ID */ , PEG2BPI6, "PEG2BPI6"},
6498 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6499 SILICOM_PEG2BPFI6_SSID /*PCI_ANY_ID */ , PEG2BPFI6, "PEG2BPFI6"},
6500 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6501 SILICOM_PEG2BPFI6LX_SSID /*PCI_ANY_ID */ , PEG2BPFI6LX, "PEG2BPFI6LX"},
6502 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6503 SILICOM_PEG2BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG2BPFI6ZX, "PEG2BPFI6ZX"},
6504 {0x8086, 0x10e7, SILICOM_SVID /*PCI_ANY_ID */ ,
6505 SILICOM_PEG2BPFI6FLXM_SSID /*PCI_ANY_ID */ , PEG2BPFI6FLXM,
6506 "PEG2BPFI6FLXM"},
6507 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6508 SILICOM_PEG4BPI6FC_SSID /*PCI_ANY_ID */ , PEG4BPI6FC, "PEG4BPI6FC"},
6509 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6510 SILICOM_PEG4BPFI6FC_SSID /*PCI_ANY_ID */ , PEG4BPFI6FC, "PEG4BPFI6FC"},
6511 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6512 SILICOM_PEG4BPFI6FCLX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCLX,
6513 "PEG4BPFI6FCLX"},
6514 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6515 SILICOM_PEG4BPFI6FCZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCZX,
6516 "PEG4BPFI6FCZX"},
6517 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6518 SILICOM_PEG6BPI6_SSID /*PCI_ANY_ID */ , PEG6BPI6, "PEG6BPI6"},
6519 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6520 SILICOM_PEG2BPI6SC6_SSID /*PCI_ANY_ID */ , PEG2BPI6SC6,
6521 "PEG6BPI62SC6"},
6522 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6523 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6524 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6525 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6526 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6527 SILICOM_MEG4BPI6_SSID /*PCI_ANY_ID */ , MEG4BPI6, "MEG4BPI6"},
6528
6529 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG2BPFI5_SSID,
6530 PEG2BPFI5, "PEG2BPFI5"},
6531 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6532 SILICOM_PEG2BPFI5LX_SSID, PEG2BPFI5LX, "PEG2BPFI5LX"},
6533
6534 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PXEG4BPFI_SSID, PXEG4BPFI,
6535 "PXEG4BPFI-SD"},
6536
6537 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6538 SILICOM_M1EG2BPI6_SSID /*PCI_ANY_ID */ , M1EG2BPI6, "MxEG2BPI6"},
6539
6540 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6541 SILICOM_M1EG2BPFI6_SSID /*PCI_ANY_ID */ , M1EG2BPFI6, "MxEG2BPFI6"},
6542 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6543 SILICOM_M1EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6LX,
6544 "MxEG2BPFI6LX"},
6545 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6546 SILICOM_M1EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6ZX,
6547 "MxEG2BPFI6ZX"},
6548
6549 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6550 SILICOM_M1EG4BPI6_SSID /*PCI_ANY_ID */ , M1EG4BPI6, "MxEG4BPI6"},
6551
6552 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6553 SILICOM_M1EG4BPFI6_SSID /*PCI_ANY_ID */ , M1EG4BPFI6, "MxEG4BPFI6"},
6554 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6555 SILICOM_M1EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6LX,
6556 "MxEG4BPFI6LX"},
6557 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6558 SILICOM_M1EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6ZX,
6559 "MxEG4BPFI6ZX"},
6560
6561 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6562 SILICOM_M1EG6BPI6_SSID /*PCI_ANY_ID */ , M1EG6BPI6, "MxEG6BPI6"},
6563
6564 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6565 SILICOM_M1E2G4BPi80_SSID /*PCI_ANY_ID */ , M1E2G4BPi80, "MxE2G4BPi80"},
6566 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6567 SILICOM_M1E2G4BPFi80_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80,
6568 "MxE2G4BPFi80"},
6569 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6570 SILICOM_M1E2G4BPFi80LX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80LX,
6571 "MxE2G4BPFi80LX"},
6572 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6573 SILICOM_M1E2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80ZX,
6574 "MxE2G4BPFi80ZX"},
6575
6576 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6577 SILICOM_M2EG2BPFI6_SSID /*PCI_ANY_ID */ , M2EG2BPFI6, "M2EG2BPFI6"},
6578 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6579 SILICOM_M2EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6LX,
6580 "M2EG2BPFI6LX"},
6581 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6582 SILICOM_M2EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6ZX,
6583 "M2EG2BPFI6ZX"},
6584
6585 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6586 SILICOM_M2EG4BPI6_SSID /*PCI_ANY_ID */ , M2EG4BPI6, "M2EG4BPI6"},
6587
6588 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6589 SILICOM_M2EG4BPFI6_SSID /*PCI_ANY_ID */ , M2EG4BPFI6, "M2EG4BPFI6"},
6590 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6591 SILICOM_M2EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6LX,
6592 "M2EG4BPFI6LX"},
6593 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6594 SILICOM_M2EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6ZX,
6595 "M2EG4BPFI6ZX"},
6596
6597 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6598 SILICOM_M2EG6BPI6_SSID /*PCI_ANY_ID */ , M2EG6BPI6, "M2EG6BPI6"},
6599
6600 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6601 SILICOM_PEG2DBI6_SSID /*PCI_ANY_ID */ , PEG2DBI6, "PEG2DBI6"},
6602 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6603 SILICOM_PEG2DBFI6_SSID /*PCI_ANY_ID */ , PEG2DBFI6, "PEG2DBFI6"},
6604 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6605 SILICOM_PEG2DBFI6LX_SSID /*PCI_ANY_ID */ , PEG2DBFI6LX, "PEG2DBFI6LX"},
6606 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6607 SILICOM_PEG2DBFI6ZX_SSID /*PCI_ANY_ID */ , PEG2DBFI6ZX, "PEG2DBFI6ZX"},
6608
6609 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6610 SILICOM_PE210G2DBi9SR_SSID, PE210G2DBi9SR, "PE210G2DBi9SR"},
6611 //{0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID*/, SILICOM_PE210G2DBi9SRRB_SSID , PE210G2DBi9SRRB, "PE210G2DBi9SRRB"},
6612 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6613 SILICOM_PE210G2DBi9LR_SSID, PE210G2DBi9LR, "PE210G2DBi9LR"},
6614 // {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID*/, SILICOM_PE210G2DBi9LRRB_SSID , PE210G2DBi9LRRB, "PE210G2DBi9LRRB"},
6615 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6616 SILICOM_PE310G4DBi940SR_SSID, PE310G4DBi940SR, "PE310G4DBi9SR"},
6617
6618 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6619 SILICOM_PE310G4BPi9T_SSID, PE310G4BPi9T, "PE310G4BPi9T"},
6620 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6621 SILICOM_PE310G4BPi9SR_SSID, PE310G4BPi9SR, "PE310G4BPi9SR"},
6622 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6623 SILICOM_PE310G4BPi9LR_SSID, PE310G4BPi9LR, "PE310G4BPi9LR"},
6624
6625 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6626 SILICOM_PE2G4BPi80_SSID /*PCI_ANY_ID */ , PE2G4BPi80, "PE2G4BPi80"},
6627 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6628 SILICOM_PE2G4BPFi80_SSID /*PCI_ANY_ID */ , PE2G4BPFi80, "PE2G4BPFi80"},
6629 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6630 SILICOM_PE2G4BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80LX,
6631 "PE2G4BPFi80LX"},
6632 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6633 SILICOM_PE2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80ZX,
6634 "PE2G4BPFi80ZX"},
6635
6636 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6637 SILICOM_PE2G4BPi80L_SSID /*PCI_ANY_ID */ , PE2G4BPi80L, "PE2G4BPi80L"},
6638
6639 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6640 SILICOM_M6E2G8BPi80A_SSID /*PCI_ANY_ID */ , M6E2G8BPi80A,
6641 "MxE2G8BPi80A"},
6642
6643 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6644 SILICOM_PE2G2BPi35_SSID /*PCI_ANY_ID */ , PE2G2BPi35, "PE2G2BPi35"},
6645 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6646 SILICOM_PAC1200BPi35_SSID /*PCI_ANY_ID */ , PAC1200BPi35,
6647 "PAC1200BPi35"},
6648
6649 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6650 SILICOM_PE2G2BPFi35_SSID /*PCI_ANY_ID */ , PE2G2BPFi35, "PE2G2BPFi35"},
6651 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6652 SILICOM_PE2G2BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35LX,
6653 "PE2G2BPFi35LX"},
6654 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6655 SILICOM_PE2G2BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35ZX,
6656 "PE2G2BPFi35ZX"},
6657
6658 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6659 SILICOM_PE2G4BPi35_SSID /*PCI_ANY_ID */ , PE2G4BPi35, "PE2G4BPi35"},
6660
6661 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6662 SILICOM_PE2G4BPi35L_SSID /*PCI_ANY_ID */ , PE2G4BPi35L, "PE2G4BPi35L"},
6663
6664 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6665 SILICOM_PE2G4BPFi35_SSID /*PCI_ANY_ID */ , PE2G4BPFi35, "PE2G4BPFi35"},
6666 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6667 SILICOM_PE2G4BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35LX,
6668 "PE2G4BPFi35LX"},
6669 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6670 SILICOM_PE2G4BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35ZX,
6671 "PE2G4BPFi35ZX"},
6672
6673 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6674 SILICOM_PE2G6BPi35_SSID /*PCI_ANY_ID */ , PE2G6BPi35, "PE2G6BPi35"},
6675
6676 // {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID*/,0xaa0,PE2G6BPi35CX,"PE2G6BPi35CX"},
6677 // {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID*/,0xaa1,PE2G6BPi35CX,"PE2G6BPi35CX"},
6678 // {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID*/,0xaa2,PE2G6BPi35CX,"PE2G6BPi35CX"},
6679
6680 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa0, PE2G6BPi35CX,
6681 "PE2G6BPi35CX"},
6682 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa1, PE2G6BPi35CX,
6683 "PE2G6BPi35CX"},
6684 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa2, PE2G6BPi35CX,
6685 "PE2G6BPi35CX"},
6686 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa3, PE2G6BPi35CX,
6687 "PE2G6BPi35CX"},
6688 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa4, PE2G6BPi35CX,
6689 "PE2G6BPi35CX"},
6690 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa5, PE2G6BPi35CX,
6691 "PE2G6BPi35CX"},
6692 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa6, PE2G6BPi35CX,
6693 "PE2G6BPi35CX"},
6694 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa7, PE2G6BPi35CX,
6695 "PE2G6BPi35CX"},
6696 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa8, PE2G6BPi35CX,
6697 "PE2G6BPi35CX"},
6698 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa9, PE2G6BPi35CX,
6699 "PE2G6BPi35CX"},
6700 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaa, PE2G6BPi35CX,
6701 "PE2G6BPi35CX"},
6702 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaab, PE2G6BPi35CX,
6703 "PE2G6BPi35CX"},
6704 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaac, PE2G6BPi35CX,
6705 "PE2G6BPi35CX"},
6706 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaad, PE2G6BPi35CX,
6707 "PE2G6BPi35CX"},
6708 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaae, PE2G6BPi35CX,
6709 "PE2G6BPi35CX"},
6710 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaf, PE2G6BPi35CX,
6711 "PE2G6BPi35CX"},
6712 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab0, PE2G6BPi35CX,
6713 "PE2G6BPi35CX"},
6714 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab1, PE2G6BPi35CX,
6715 "PE2G6BPi35CX"},
6716 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab2, PE2G6BPi35CX,
6717 "PE2G6BPi35CX"},
6718 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab3, PE2G6BPi35CX,
6719 "PE2G6BPi35CX"},
6720 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab4, PE2G6BPi35CX,
6721 "PE2G6BPi35CX"},
6722 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab5, PE2G6BPi35CX,
6723 "PE2G6BPi35CX"},
6724 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab6, PE2G6BPi35CX,
6725 "PE2G6BPi35CX"},
6726 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab7, PE2G6BPi35CX,
6727 "PE2G6BPi35CX"},
6728 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab8, PE2G6BPi35CX,
6729 "PE2G6BPi35CX"},
6730 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab9, PE2G6BPi35CX,
6731 "PE2G6BPi35CX"},
6732 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaba, PE2G6BPi35CX,
6733 "PE2G6BPi35CX"},
6734 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabb, PE2G6BPi35CX,
6735 "PE2G6BPi35CX"},
6736 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabc, PE2G6BPi35CX,
6737 "PE2G6BPi35CX"},
6738 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabd, PE2G6BPi35CX,
6739 "PE2G6BPi35CX"},
6740 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabe, PE2G6BPi35CX,
6741 "PE2G6BPi35CX"},
6742 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabf, PE2G6BPi35CX,
6743 "PE2G6BPi35CX"},
6744
6745 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6746 SILICOM_PE2G2BPi80_SSID /*PCI_ANY_ID */ , PE2G2BPi80, "PE2G2BPi80"},
6747 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6748 SILICOM_PE2G2BPFi80_SSID /*PCI_ANY_ID */ , PE2G2BPFi80, "PE2G2BPFi80"},
6749 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6750 SILICOM_PE2G2BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80LX,
6751 "PE2G2BPFi80LX"},
6752 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6753 SILICOM_PE2G2BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80ZX,
6754 "PE2G2BPFi80ZX"},
6755
6756 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6757 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6758 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6759 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6760
6761#if 0
6762 {0x8086, 0x10fb, 0x8086, INTEL_PE210G2SPI9_SSID, PE210G2SPI9,
6763 "PE210G2SPI9"},
6764#endif
6765 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6766 SILICOM_M1E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M1E10G2BPI9CX4,
6767 "MxE210G2BPI9CX4"},
6768 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6769 SILICOM_M1E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9SR,
6770 "MxE210G2BPI9SR"},
6771 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6772 SILICOM_M1E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9LR,
6773 "MxE210G2BPI9LR"},
6774 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6775 SILICOM_M1E10G2BPI9T_SSID /*PCI_ANY_ID */ , M1E10G2BPI9T,
6776 "MxE210G2BPI9T"},
6777
6778 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6779 SILICOM_M2E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M2E10G2BPI9CX4,
6780 "M2E10G2BPI9CX4"},
6781 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6782 SILICOM_M2E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9SR,
6783 "M2E10G2BPI9SR"},
6784 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6785 SILICOM_M2E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9LR,
6786 "M2E10G2BPI9LR"},
6787 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6788 SILICOM_M2E10G2BPI9T_SSID /*PCI_ANY_ID */ , M2E10G2BPI9T,
6789 "M2E10G2BPI9T"},
6790
6791 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9CX4_SSID,
6792 PE210G2BPI9CX4, "PE210G2BPI9CX4"},
6793 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9SR_SSID,
6794 PE210G2BPI9SR, "PE210G2BPI9SR"},
6795 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9LR_SSID,
6796 PE210G2BPI9LR, "PE210G2BPI9LR"},
6797 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9T_SSID, PE210G2BPI9T,
6798 "PE210G2BPI9T"},
6799
6800#if 0
6801 {0x1374, 0x2c, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6802 "PXG4BPI-SD"},
6803
6804 {0x1374, 0x2d, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6805 "PXG4BPFI-SD"},
6806
6807 {0x1374, 0x3f, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6808 "PXG2TBI-SD"},
6809
6810 {0x1374, 0x3d, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6811 "PXG2BISC1-SD"},
6812
6813 {0x1374, 0x40, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6814 "PEG4BPFI-SD"},
6815
6816#ifdef BP_SELF_TEST
6817 {0x1374, 0x28, SILICOM_SVID, 0x28, PXGBPI, "PXG2BPI-SD"},
6818#endif
6819#endif
6820 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6821 SILICOM_M6E2G8BPi80_SSID /*PCI_ANY_ID */ , M6E2G8BPi80, "MxE2G8BPi80"},
6822 {0x8086, 0x1528, SILICOM_SVID /*PCI_ANY_ID */ ,
6823 SILICOM_PE210G2BPi40_SSID /*PCI_ANY_ID */ , PE210G2BPi40,
6824 "PE210G2BPi40T"},
6825
6826 /* required last entry */
6827 {0,}
6828};
6829
6830/*
6831* Initialize the module - Register the character device
6832*/
6833
6834static int __init bypass_init_module(void)
6835{
6836 int ret_val, idx, idx_dev = 0;
6837 struct pci_dev *pdev1 = NULL;
6838 unsigned long mmio_start, mmio_len;
6839
6840 printk(BP_MOD_DESCR " v" BP_MOD_VER "\n");
6841 ret_val = register_chrdev(major_num, DEVICE_NAME, &Fops);
6842 if (ret_val < 0) {
6843 printk("%s failed with %d\n", DEVICE_NAME, ret_val);
6844 return ret_val;
6845 }
6846 major_num = ret_val; /* dynamic */
6847 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6848 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6849 tx_ctl_pci_tbl[idx].device,
6850 tx_ctl_pci_tbl[idx].subvendor,
6851 tx_ctl_pci_tbl[idx].subdevice,
6852 pdev1))) {
6853
6854 device_num++;
6855 }
6856 }
6857 if (!device_num) {
6858 printk("No such device\n");
6859 unregister_chrdev(major_num, DEVICE_NAME);
6860 return -1;
6861 }
6862
6863 bpctl_dev_arr = kmalloc((device_num) * sizeof(bpctl_dev_t), GFP_KERNEL);
6864
6865 if (!bpctl_dev_arr) {
6866 printk("Allocation error\n");
6867 unregister_chrdev(major_num, DEVICE_NAME);
6868 return -1;
6869 }
6870 memset(bpctl_dev_arr, 0, ((device_num) * sizeof(bpctl_dev_t)));
6871
6872 pdev1 = NULL;
6873 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6874 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6875 tx_ctl_pci_tbl[idx].device,
6876 tx_ctl_pci_tbl[idx].subvendor,
6877 tx_ctl_pci_tbl[idx].subdevice,
6878 pdev1))) {
6879 bpctl_dev_arr[idx_dev].pdev = pdev1;
6880
6881 mmio_start = pci_resource_start(pdev1, 0);
6882 mmio_len = pci_resource_len(pdev1, 0);
6883
6884 bpctl_dev_arr[idx_dev].desc =
6885 dev_desc[tx_ctl_pci_tbl[idx].index].name;
6886 bpctl_dev_arr[idx_dev].name =
6887 tx_ctl_pci_tbl[idx].bp_name;
6888 bpctl_dev_arr[idx_dev].device =
6889 tx_ctl_pci_tbl[idx].device;
6890 bpctl_dev_arr[idx_dev].vendor =
6891 tx_ctl_pci_tbl[idx].vendor;
6892 bpctl_dev_arr[idx_dev].subdevice =
6893 tx_ctl_pci_tbl[idx].subdevice;
6894 bpctl_dev_arr[idx_dev].subvendor =
6895 tx_ctl_pci_tbl[idx].subvendor;
6896 //bpctl_dev_arr[idx_dev].pdev=pdev1;
6897 bpctl_dev_arr[idx_dev].func = PCI_FUNC(pdev1->devfn);
6898 bpctl_dev_arr[idx_dev].slot = PCI_SLOT(pdev1->devfn);
6899 bpctl_dev_arr[idx_dev].bus = pdev1->bus->number;
6900 bpctl_dev_arr[idx_dev].mem_map =
6901 (unsigned long)ioremap(mmio_start, mmio_len);
6902#ifdef BP_SYNC_FLAG
6903 spin_lock_init(&bpctl_dev_arr[idx_dev].bypass_wr_lock);
6904#endif
6905 if (BP10G9_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6906 bpctl_dev_arr[idx_dev].bp_10g9 = 1;
6907 if (BP10G_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6908 bpctl_dev_arr[idx_dev].bp_10g = 1;
6909 if (PEG540_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice)) {
6910
6911 bpctl_dev_arr[idx_dev].bp_540 = 1;
6912 }
6913 if (PEGF5_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6914 bpctl_dev_arr[idx_dev].bp_fiber5 = 1;
6915 if (PEG80_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6916 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6917 if (PEGF80_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6918 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6919 if ((bpctl_dev_arr[idx_dev].subdevice & 0xa00) == 0xa00)
6920 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6921 if (BP10GB_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice)) {
6922 if (bpctl_dev_arr[idx_dev].ifindex == 0) {
6923 unregister_chrdev(major_num,
6924 DEVICE_NAME);
6925 printk
6926 ("Please load network driver for %s adapter!\n",
6927 bpctl_dev_arr[idx_dev].name);
6928 return -1;
6929 }
6930
6931 if (bpctl_dev_arr[idx_dev].ndev) {
6932 if (!
6933 (bpctl_dev_arr[idx_dev].ndev->
6934 flags & IFF_UP)) {
6935 if (!
6936 (bpctl_dev_arr[idx_dev].
6937 ndev->flags & IFF_UP)) {
6938 unregister_chrdev
6939 (major_num,
6940 DEVICE_NAME);
6941 printk
6942 ("Please bring up network interfaces for %s adapter!\n",
6943 bpctl_dev_arr
6944 [idx_dev].name);
6945 return -1;
6946 }
6947
6948 }
6949 }
6950 bpctl_dev_arr[idx_dev].bp_10gb = 1;
6951 }
6952
6953 if (!bpctl_dev_arr[idx_dev].bp_10g9) {
6954
6955 if (is_bypass_fn(&bpctl_dev_arr[idx_dev])) {
6956 printk(KERN_INFO "%s found, ",
6957 bpctl_dev_arr[idx_dev].name);
6958 if ((OLD_IF_SERIES
6959 (bpctl_dev_arr[idx_dev].subdevice))
6960 ||
6961 (INTEL_IF_SERIES
6962 (bpctl_dev_arr[idx_dev].
6963 subdevice)))
6964 bpctl_dev_arr[idx_dev].
6965 bp_fw_ver = 0xff;
6966 else
6967 bpctl_dev_arr[idx_dev].
6968 bp_fw_ver =
6969 bypass_fw_ver(&bpctl_dev_arr
6970 [idx_dev]);
6971 if ((bpctl_dev_arr[idx_dev].bp_10gb ==
6972 1)
6973 && (bpctl_dev_arr[idx_dev].
6974 bp_fw_ver == 0xff)) {
6975 int cnt = 100;
6976 while (cnt--) {
6977 iounmap((void
6978 *)
6979 (bpctl_dev_arr
6980 [idx_dev].
6981 mem_map));
6982 mmio_start =
6983 pci_resource_start
6984 (pdev1, 0);
6985 mmio_len =
6986 pci_resource_len
6987 (pdev1, 0);
6988
6989 bpctl_dev_arr[idx_dev].
6990 mem_map =
6991 (unsigned long)
6992 ioremap(mmio_start,
6993 mmio_len);
6994
6995 bpctl_dev_arr[idx_dev].
6996 bp_fw_ver =
6997 bypass_fw_ver
6998 (&bpctl_dev_arr
6999 [idx_dev]);
7000 if (bpctl_dev_arr
7001 [idx_dev].
7002 bp_fw_ver == 0xa8)
7003 break;
7004
7005 }
7006 }
7007 //bpctl_dev_arr[idx_dev].bp_fw_ver=0xa8;
7008 printk("firmware version: 0x%x\n",
7009 bpctl_dev_arr[idx_dev].
7010 bp_fw_ver);
7011 }
7012 bpctl_dev_arr[idx_dev].wdt_status =
7013 WDT_STATUS_UNKNOWN;
7014 bpctl_dev_arr[idx_dev].reset_time = 0;
7015 atomic_set(&bpctl_dev_arr[idx_dev].wdt_busy, 0);
7016 bpctl_dev_arr[idx_dev].bp_status_un = 1;
7017
7018 bypass_caps_init(&bpctl_dev_arr[idx_dev]);
7019
7020 init_bypass_wd_auto(&bpctl_dev_arr[idx_dev]);
7021 init_bypass_tpl_auto(&bpctl_dev_arr[idx_dev]);
7022 if (NOKIA_SERIES
7023 (bpctl_dev_arr[idx_dev].subdevice))
7024 reset_cont(&bpctl_dev_arr[idx_dev]);
7025 }
7026#ifdef BP_SELF_TEST
7027 if ((bpctl_dev_arr[idx_dev].bp_tx_data =
7028 kmalloc(BPTEST_DATA_LEN, GFP_KERNEL))) {
7029
7030 memset(bpctl_dev_arr[idx_dev].bp_tx_data, 0x0,
7031 BPTEST_DATA_LEN);
7032
7033 memset(bpctl_dev_arr[idx_dev].bp_tx_data, 0xff,
7034 6);
7035 memset(bpctl_dev_arr[idx_dev].bp_tx_data + 6,
7036 0x0, 1);
7037 memset(bpctl_dev_arr[idx_dev].bp_tx_data + 7,
7038 0xaa, 5);
7039
7040#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
7041 bpctl_dev_arr[idx_dev].bp_tx_data[12] =
7042 (ETH_P_BPTEST >> 8) & 0xff;
7043 bpctl_dev_arr[idx_dev].bp_tx_data[13] =
7044 ETH_P_BPTEST & 0xff;
7045#else
7046 *(__be16 *) (bpctl_dev_arr[idx_dev].bp_tx_data +
7047 12) = htons(ETH_P_BPTEST);
7048#endif
7049
7050 } else
7051 printk("bp_ctl: Memory allocation error!\n");
7052#endif
7053 idx_dev++;
7054
7055 }
7056 }
7057 if_scan_init();
7058
7059 sema_init(&bpctl_sema, 1);
7060 spin_lock_init(&bpvm_lock);
7061 {
7062
7063 bpctl_dev_t *pbpctl_dev_c = NULL;
7064 for (idx_dev = 0;
7065 ((bpctl_dev_arr[idx_dev].pdev != NULL)
7066 && (idx_dev < device_num)); idx_dev++) {
7067 if (bpctl_dev_arr[idx_dev].bp_10g9) {
7068 pbpctl_dev_c =
7069 get_status_port_fn(&bpctl_dev_arr[idx_dev]);
7070 if (is_bypass_fn(&bpctl_dev_arr[idx_dev])) {
7071 printk(KERN_INFO "%s found, ",
7072 bpctl_dev_arr[idx_dev].name);
7073 bpctl_dev_arr[idx_dev].bp_fw_ver =
7074 bypass_fw_ver(&bpctl_dev_arr
7075 [idx_dev]);
7076 printk("firmware version: 0x%x\n",
7077 bpctl_dev_arr[idx_dev].
7078 bp_fw_ver);
7079
7080 }
7081 bpctl_dev_arr[idx_dev].wdt_status =
7082 WDT_STATUS_UNKNOWN;
7083 bpctl_dev_arr[idx_dev].reset_time = 0;
7084 atomic_set(&bpctl_dev_arr[idx_dev].wdt_busy, 0);
7085 bpctl_dev_arr[idx_dev].bp_status_un = 1;
7086
7087 bypass_caps_init(&bpctl_dev_arr[idx_dev]);
7088
7089 init_bypass_wd_auto(&bpctl_dev_arr[idx_dev]);
7090 init_bypass_tpl_auto(&bpctl_dev_arr[idx_dev]);
7091
7092 }
7093
7094 }
7095 }
7096
7097#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7098 inter_module_register("is_bypass_sd", THIS_MODULE, &is_bypass_sd);
7099 inter_module_register("get_bypass_slave_sd", THIS_MODULE,
7100 &get_bypass_slave_sd);
7101 inter_module_register("get_bypass_caps_sd", THIS_MODULE,
7102 &get_bypass_caps_sd);
7103 inter_module_register("get_wd_set_caps_sd", THIS_MODULE,
7104 &get_wd_set_caps_sd);
7105 inter_module_register("set_bypass_sd", THIS_MODULE, &set_bypass_sd);
7106 inter_module_register("get_bypass_sd", THIS_MODULE, &get_bypass_sd);
7107 inter_module_register("get_bypass_change_sd", THIS_MODULE,
7108 &get_bypass_change_sd);
7109 inter_module_register("set_dis_bypass_sd", THIS_MODULE,
7110 &set_dis_bypass_sd);
7111 inter_module_register("get_dis_bypass_sd", THIS_MODULE,
7112 &get_dis_bypass_sd);
7113 inter_module_register("set_bypass_pwoff_sd", THIS_MODULE,
7114 &set_bypass_pwoff_sd);
7115 inter_module_register("get_bypass_pwoff_sd", THIS_MODULE,
7116 &get_bypass_pwoff_sd);
7117 inter_module_register("set_bypass_pwup_sd", THIS_MODULE,
7118 &set_bypass_pwup_sd);
7119 inter_module_register("get_bypass_pwup_sd", THIS_MODULE,
7120 &get_bypass_pwup_sd);
7121 inter_module_register("get_bypass_wd_sd", THIS_MODULE,
7122 &get_bypass_wd_sd);
7123 inter_module_register("set_bypass_wd_sd", THIS_MODULE,
7124 &set_bypass_wd_sd);
7125 inter_module_register("get_wd_expire_time_sd", THIS_MODULE,
7126 &get_wd_expire_time_sd);
7127 inter_module_register("reset_bypass_wd_timer_sd", THIS_MODULE,
7128 &reset_bypass_wd_timer_sd);
7129 inter_module_register("set_std_nic_sd", THIS_MODULE, &set_std_nic_sd);
7130 inter_module_register("get_std_nic_sd", THIS_MODULE, &get_std_nic_sd);
7131 inter_module_register("set_tx_sd", THIS_MODULE, &set_tx_sd);
7132 inter_module_register("get_tx_sd", THIS_MODULE, &get_tx_sd);
7133 inter_module_register("set_tpl_sd", THIS_MODULE, &set_tpl_sd);
7134 inter_module_register("get_tpl_sd", THIS_MODULE, &get_tpl_sd);
7135
7136 inter_module_register("set_bp_hw_reset_sd", THIS_MODULE,
7137 &set_bp_hw_reset_sd);
7138 inter_module_register("get_bp_hw_reset_sd", THIS_MODULE,
7139 &get_bp_hw_reset_sd);
7140
7141 inter_module_register("set_tap_sd", THIS_MODULE, &set_tap_sd);
7142 inter_module_register("get_tap_sd", THIS_MODULE, &get_tap_sd);
7143 inter_module_register("get_tap_change_sd", THIS_MODULE,
7144 &get_tap_change_sd);
7145 inter_module_register("set_dis_tap_sd", THIS_MODULE, &set_dis_tap_sd);
7146 inter_module_register("get_dis_tap_sd", THIS_MODULE, &get_dis_tap_sd);
7147 inter_module_register("set_tap_pwup_sd", THIS_MODULE, &set_tap_pwup_sd);
7148 inter_module_register("get_tap_pwup_sd", THIS_MODULE, &get_tap_pwup_sd);
7149 inter_module_register("set_bp_disc_sd", THIS_MODULE, &set_bp_disc_sd);
7150 inter_module_register("get_bp_disc_sd", THIS_MODULE, &get_bp_disc_sd);
7151 inter_module_register("get_bp_disc_change_sd", THIS_MODULE,
7152 &get_bp_disc_change_sd);
7153 inter_module_register("set_bp_dis_disc_sd", THIS_MODULE,
7154 &set_bp_dis_disc_sd);
7155 inter_module_register("get_bp_dis_disc_sd", THIS_MODULE,
7156 &get_bp_dis_disc_sd);
7157 inter_module_register("set_bp_disc_pwup_sd", THIS_MODULE,
7158 &set_bp_disc_pwup_sd);
7159 inter_module_register("get_bp_disc_pwup_sd", THIS_MODULE,
7160 &get_bp_disc_pwup_sd);
7161 inter_module_register("set_wd_exp_mode_sd", THIS_MODULE,
7162 &set_wd_exp_mode_sd);
7163 inter_module_register("get_wd_exp_mode_sd", THIS_MODULE,
7164 &get_wd_exp_mode_sd);
7165 inter_module_register("set_wd_autoreset_sd", THIS_MODULE,
7166 &set_wd_autoreset_sd);
7167 inter_module_register("get_wd_autoreset_sd", THIS_MODULE,
7168 &get_wd_autoreset_sd);
7169 inter_module_register("get_bypass_info_sd", THIS_MODULE,
7170 &get_bypass_info_sd);
7171 inter_module_register("bp_if_scan_sd", THIS_MODULE, &bp_if_scan_sd);
7172
7173#endif
7174 register_netdevice_notifier(&bp_notifier_block);
7175#ifdef BP_PROC_SUPPORT
7176 {
7177 int i = 0;
7178 //unsigned long flags;
7179 //rcu_read_lock();
7180 bp_proc_create();
7181 for (i = 0; i < device_num; i++) {
7182 if (bpctl_dev_arr[i].ifindex) {
7183 //spin_lock_irqsave(&bpvm_lock, flags);
7184 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
7185 bypass_proc_create_dev_sd(&bpctl_dev_arr[i]);
7186 //spin_unlock_irqrestore(&bpvm_lock, flags);
7187 }
7188
7189 }
7190 //rcu_read_unlock();
7191 }
7192#endif
7193
7194 //register_netdevice_notifier(&bp_notifier_block);
7195 return 0;
7196}
7197
7198/*
7199* Cleanup - unregister the appropriate file from /proc
7200*/
7201static void __exit bypass_cleanup_module(void)
7202{
7203 int i;
7204#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23))
7205 int ret;
7206#endif
7207 unregister_netdevice_notifier(&bp_notifier_block);
7208
7209#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7210 inter_module_unregister("is_bypass_sd");
7211 inter_module_unregister("get_bypass_slave_sd");
7212 inter_module_unregister("get_bypass_caps_sd");
7213 inter_module_unregister("get_wd_set_caps_sd");
7214 inter_module_unregister("set_bypass_sd");
7215 inter_module_unregister("get_bypass_sd");
7216 inter_module_unregister("get_bypass_change_sd");
7217 inter_module_unregister("set_dis_bypass_sd");
7218 inter_module_unregister("get_dis_bypass_sd");
7219 inter_module_unregister("set_bypass_pwoff_sd");
7220 inter_module_unregister("get_bypass_pwoff_sd");
7221 inter_module_unregister("set_bypass_pwup_sd");
7222 inter_module_unregister("get_bypass_pwup_sd");
7223 inter_module_unregister("set_bypass_wd_sd");
7224 inter_module_unregister("get_bypass_wd_sd");
7225 inter_module_unregister("get_wd_expire_time_sd");
7226 inter_module_unregister("reset_bypass_wd_timer_sd");
7227 inter_module_unregister("set_std_nic_sd");
7228 inter_module_unregister("get_std_nic_sd");
7229 inter_module_unregister("set_tx_sd");
7230 inter_module_unregister("get_tx_sd");
7231 inter_module_unregister("set_tpl_sd");
7232 inter_module_unregister("get_tpl_sd");
7233 inter_module_unregister("set_tap_sd");
7234 inter_module_unregister("get_tap_sd");
7235 inter_module_unregister("get_tap_change_sd");
7236 inter_module_unregister("set_dis_tap_sd");
7237 inter_module_unregister("get_dis_tap_sd");
7238 inter_module_unregister("set_tap_pwup_sd");
7239 inter_module_unregister("get_tap_pwup_sd");
7240 inter_module_unregister("set_bp_disc_sd");
7241 inter_module_unregister("get_bp_disc_sd");
7242 inter_module_unregister("get_bp_disc_change_sd");
7243 inter_module_unregister("set_bp_dis_disc_sd");
7244 inter_module_unregister("get_bp_dis_disc_sd");
7245 inter_module_unregister("set_bp_disc_pwup_sd");
7246 inter_module_unregister("get_bp_disc_pwup_sd");
7247 inter_module_unregister("set_wd_exp_mode_sd");
7248 inter_module_unregister("get_wd_exp_mode_sd");
7249 inter_module_unregister("set_wd_autoreset_sd");
7250 inter_module_unregister("get_wd_autoreset_sd");
7251 inter_module_unregister("get_bypass_info_sd");
7252 inter_module_unregister("bp_if_scan_sd");
7253
7254#endif
7255
7256 for (i = 0; i < device_num; i++) {
7257 //unsigned long flags;
7258#ifdef BP_PROC_SUPPORT
7259//spin_lock_irqsave(&bpvm_lock, flags);
7260//rcu_read_lock();
7261 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
7262//spin_unlock_irqrestore(&bpvm_lock, flags);
7263//rcu_read_unlock();
7264#endif
7265 remove_bypass_wd_auto(&bpctl_dev_arr[i]);
7266 bpctl_dev_arr[i].reset_time = 0;
7267
7268 remove_bypass_tpl_auto(&bpctl_dev_arr[i]);
7269 }
7270
7271 /* unmap all devices */
7272 for (i = 0; i < device_num; i++) {
7273#ifdef BP_SELF_TEST
7274 if (bpctl_dev_arr[i].bp_tx_data)
7275 kfree(bpctl_dev_arr[i].bp_tx_data);
7276#endif
7277 iounmap((void *)(bpctl_dev_arr[i].mem_map));
7278 }
7279
7280 /* free all devices space */
7281 if (bpctl_dev_arr)
7282 kfree(bpctl_dev_arr);
7283
7284/*
7285* Unregister the device
7286*/
7287#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23))
7288 ret = unregister_chrdev(major_num, DEVICE_NAME);
7289/*
7290* If there's an error, report it
7291*/
7292 if (ret < 0)
7293 printk("Error in module_unregister_chrdev: %d\n", ret);
7294#else
7295 unregister_chrdev(major_num, DEVICE_NAME);
7296
7297#endif
7298}
7299
7300module_init(bypass_init_module);
7301module_exit(bypass_cleanup_module);
7302
7303int is_bypass_sd(int ifindex)
7304{
7305 return (is_bypass(get_dev_idx_p(ifindex)));
7306}
7307
7308int set_bypass_sd(int ifindex, int bypass_mode)
7309{
7310
7311 return (set_bypass_fn(get_dev_idx_p(ifindex), bypass_mode));
7312}
7313
7314int get_bypass_sd(int ifindex)
7315{
7316
7317 return (get_bypass_fn(get_dev_idx_p(ifindex)));
7318}
7319
7320int get_bypass_change_sd(int ifindex)
7321{
7322
7323 return (get_bypass_change_fn(get_dev_idx_p(ifindex)));
7324}
7325
7326int set_dis_bypass_sd(int ifindex, int dis_param)
7327{
7328 return (set_dis_bypass_fn(get_dev_idx_p(ifindex), dis_param));
7329}
7330
7331int get_dis_bypass_sd(int ifindex)
7332{
7333
7334 return (get_dis_bypass_fn(get_dev_idx_p(ifindex)));
7335}
7336
7337int set_bypass_pwoff_sd(int ifindex, int bypass_mode)
7338{
7339 return (set_bypass_pwoff_fn(get_dev_idx_p(ifindex), bypass_mode));
7340
7341}
7342
7343int get_bypass_pwoff_sd(int ifindex)
7344{
7345 return (get_bypass_pwoff_fn(get_dev_idx_p(ifindex)));
7346
7347}
7348
7349int set_bypass_pwup_sd(int ifindex, int bypass_mode)
7350{
7351 return (set_bypass_pwup_fn(get_dev_idx_p(ifindex), bypass_mode));
7352
7353}
7354
7355int get_bypass_pwup_sd(int ifindex)
7356{
7357 return (get_bypass_pwup_fn(get_dev_idx_p(ifindex)));
7358
7359}
7360
7361int set_bypass_wd_sd(int if_index, int ms_timeout, int *ms_timeout_set)
7362{
7363 if ((is_bypass(get_dev_idx_p(if_index))) <= 0)
7364 return BP_NOT_CAP;
7365 *ms_timeout_set = set_bypass_wd_fn(get_dev_idx_p(if_index), ms_timeout);
7366 return 0;
7367}
7368
7369int get_bypass_wd_sd(int ifindex, int *timeout)
7370{
7371 return (get_bypass_wd_fn(get_dev_idx_p(ifindex), timeout));
7372
7373}
7374
7375int get_wd_expire_time_sd(int ifindex, int *time_left)
7376{
7377 return (get_wd_expire_time_fn(get_dev_idx_p(ifindex), time_left));
7378}
7379
7380int reset_bypass_wd_timer_sd(int ifindex)
7381{
7382 return (reset_bypass_wd_timer_fn(get_dev_idx_p(ifindex)));
7383
7384}
7385
7386int get_wd_set_caps_sd(int ifindex)
7387{
7388 return (get_wd_set_caps_fn(get_dev_idx_p(ifindex)));
7389
7390}
7391
7392int set_std_nic_sd(int ifindex, int nic_mode)
7393{
7394 return (set_std_nic_fn(get_dev_idx_p(ifindex), nic_mode));
7395
7396}
7397
7398int get_std_nic_sd(int ifindex)
7399{
7400 return (get_std_nic_fn(get_dev_idx_p(ifindex)));
7401
7402}
7403
7404int set_tap_sd(int ifindex, int tap_mode)
7405{
7406 return (set_tap_fn(get_dev_idx_p(ifindex), tap_mode));
7407
7408}
7409
7410int get_tap_sd(int ifindex)
7411{
7412 return (get_tap_fn(get_dev_idx_p(ifindex)));
7413
7414}
7415
7416int set_tap_pwup_sd(int ifindex, int tap_mode)
7417{
7418 return (set_tap_pwup_fn(get_dev_idx_p(ifindex), tap_mode));
7419
7420}
7421
7422int get_tap_pwup_sd(int ifindex)
7423{
7424 return (get_tap_pwup_fn(get_dev_idx_p(ifindex)));
7425
7426}
7427
7428int get_tap_change_sd(int ifindex)
7429{
7430 return (get_tap_change_fn(get_dev_idx_p(ifindex)));
7431
7432}
7433
7434int set_dis_tap_sd(int ifindex, int dis_param)
7435{
7436 return (set_dis_tap_fn(get_dev_idx_p(ifindex), dis_param));
7437
7438}
7439
7440int get_dis_tap_sd(int ifindex)
7441{
7442 return (get_dis_tap_fn(get_dev_idx_p(ifindex)));
7443
7444}
7445
7446int set_bp_disc_sd(int ifindex, int disc_mode)
7447{
7448 return (set_disc_fn(get_dev_idx_p(ifindex), disc_mode));
7449
7450}
7451
7452int get_bp_disc_sd(int ifindex)
7453{
7454 return (get_disc_fn(get_dev_idx_p(ifindex)));
7455
7456}
7457
7458int set_bp_disc_pwup_sd(int ifindex, int disc_mode)
7459{
7460 return (set_disc_pwup_fn(get_dev_idx_p(ifindex), disc_mode));
7461
7462}
7463
7464int get_bp_disc_pwup_sd(int ifindex)
7465{
7466 return (get_disc_pwup_fn(get_dev_idx_p(ifindex)));
7467
7468}
7469
7470int get_bp_disc_change_sd(int ifindex)
7471{
7472 return (get_disc_change_fn(get_dev_idx_p(ifindex)));
7473
7474}
7475
7476int set_bp_dis_disc_sd(int ifindex, int dis_param)
7477{
7478 return (set_dis_disc_fn(get_dev_idx_p(ifindex), dis_param));
7479
7480}
7481
7482int get_bp_dis_disc_sd(int ifindex)
7483{
7484 return (get_dis_disc_fn(get_dev_idx_p(ifindex)));
7485
7486}
7487
7488int get_wd_exp_mode_sd(int ifindex)
7489{
7490 return (get_wd_exp_mode_fn(get_dev_idx_p(ifindex)));
7491}
7492
7493int set_wd_exp_mode_sd(int ifindex, int param)
7494{
7495 return (set_wd_exp_mode_fn(get_dev_idx_p(ifindex), param));
7496
7497}
7498
7499int reset_cont_sd(int ifindex)
7500{
7501 return (reset_cont_fn(get_dev_idx_p(ifindex)));
7502
7503}
7504
7505int set_tx_sd(int ifindex, int tx_state)
7506{
7507 return (set_tx_fn(get_dev_idx_p(ifindex), tx_state));
7508
7509}
7510
7511int set_tpl_sd(int ifindex, int tpl_state)
7512{
7513 return (set_tpl_fn(get_dev_idx_p(ifindex), tpl_state));
7514
7515}
7516
7517int set_bp_hw_reset_sd(int ifindex, int status)
7518{
7519 return (set_bp_hw_reset_fn(get_dev_idx_p(ifindex), status));
7520
7521}
7522
7523int set_wd_autoreset_sd(int ifindex, int param)
7524{
7525 return (set_wd_autoreset_fn(get_dev_idx_p(ifindex), param));
7526
7527}
7528
7529int get_wd_autoreset_sd(int ifindex)
7530{
7531 return (get_wd_autoreset_fn(get_dev_idx_p(ifindex)));
7532
7533}
7534
7535int get_bypass_caps_sd(int ifindex)
7536{
7537 return (get_bypass_caps_fn(get_dev_idx_p(ifindex)));
7538}
7539
7540int get_bypass_slave_sd(int ifindex)
7541{
7542 bpctl_dev_t *pbpctl_dev_out;
7543 int ret = get_bypass_slave_fn(get_dev_idx_p(ifindex), &pbpctl_dev_out);
7544 if (ret == 1)
7545 return (pbpctl_dev_out->ifindex);
7546 return -1;
7547
7548}
7549
7550int get_tx_sd(int ifindex)
7551{
7552 return (get_tx_fn(get_dev_idx_p(ifindex)));
7553
7554}
7555
7556int get_tpl_sd(int ifindex)
7557{
7558 return (get_tpl_fn(get_dev_idx_p(ifindex)));
7559
7560}
7561
7562int get_bp_hw_reset_sd(int ifindex)
7563{
7564 return (get_bp_hw_reset_fn(get_dev_idx_p(ifindex)));
7565
7566}
7567
7568int get_bypass_info_sd(int ifindex, struct bp_info *bp_info)
7569{
7570 return (get_bypass_info_fn
7571 (get_dev_idx_p(ifindex), bp_info->prod_name, &bp_info->fw_ver));
7572}
7573
7574int bp_if_scan_sd(void)
7575{
7576 if_scan_init();
7577 return 0;
7578}
7579
7580EXPORT_SYMBOL_NOVERS(is_bypass_sd);
7581EXPORT_SYMBOL_NOVERS(get_bypass_slave_sd);
7582EXPORT_SYMBOL_NOVERS(get_bypass_caps_sd);
7583EXPORT_SYMBOL_NOVERS(get_wd_set_caps_sd);
7584EXPORT_SYMBOL_NOVERS(set_bypass_sd);
7585EXPORT_SYMBOL_NOVERS(get_bypass_sd);
7586EXPORT_SYMBOL_NOVERS(get_bypass_change_sd);
7587EXPORT_SYMBOL_NOVERS(set_dis_bypass_sd);
7588EXPORT_SYMBOL_NOVERS(get_dis_bypass_sd);
7589EXPORT_SYMBOL_NOVERS(set_bypass_pwoff_sd);
7590EXPORT_SYMBOL_NOVERS(get_bypass_pwoff_sd);
7591EXPORT_SYMBOL_NOVERS(set_bypass_pwup_sd);
7592EXPORT_SYMBOL_NOVERS(get_bypass_pwup_sd);
7593EXPORT_SYMBOL_NOVERS(set_bypass_wd_sd);
7594EXPORT_SYMBOL_NOVERS(get_bypass_wd_sd);
7595EXPORT_SYMBOL_NOVERS(get_wd_expire_time_sd);
7596EXPORT_SYMBOL_NOVERS(reset_bypass_wd_timer_sd);
7597EXPORT_SYMBOL_NOVERS(set_std_nic_sd);
7598EXPORT_SYMBOL_NOVERS(get_std_nic_sd);
7599EXPORT_SYMBOL_NOVERS(set_tx_sd);
7600EXPORT_SYMBOL_NOVERS(get_tx_sd);
7601EXPORT_SYMBOL_NOVERS(set_tpl_sd);
7602EXPORT_SYMBOL_NOVERS(get_tpl_sd);
7603EXPORT_SYMBOL_NOVERS(set_bp_hw_reset_sd);
7604EXPORT_SYMBOL_NOVERS(get_bp_hw_reset_sd);
7605EXPORT_SYMBOL_NOVERS(set_tap_sd);
7606EXPORT_SYMBOL_NOVERS(get_tap_sd);
7607EXPORT_SYMBOL_NOVERS(get_tap_change_sd);
7608EXPORT_SYMBOL_NOVERS(set_dis_tap_sd);
7609EXPORT_SYMBOL_NOVERS(get_dis_tap_sd);
7610EXPORT_SYMBOL_NOVERS(set_tap_pwup_sd);
7611EXPORT_SYMBOL_NOVERS(get_tap_pwup_sd);
7612EXPORT_SYMBOL_NOVERS(set_wd_exp_mode_sd);
7613EXPORT_SYMBOL_NOVERS(get_wd_exp_mode_sd);
7614EXPORT_SYMBOL_NOVERS(set_wd_autoreset_sd);
7615EXPORT_SYMBOL_NOVERS(get_wd_autoreset_sd);
7616EXPORT_SYMBOL_NOVERS(set_bp_disc_sd);
7617EXPORT_SYMBOL_NOVERS(get_bp_disc_sd);
7618EXPORT_SYMBOL_NOVERS(get_bp_disc_change_sd);
7619EXPORT_SYMBOL_NOVERS(set_bp_dis_disc_sd);
7620EXPORT_SYMBOL_NOVERS(get_bp_dis_disc_sd);
7621EXPORT_SYMBOL_NOVERS(set_bp_disc_pwup_sd);
7622EXPORT_SYMBOL_NOVERS(get_bp_disc_pwup_sd);
7623EXPORT_SYMBOL_NOVERS(get_bypass_info_sd);
7624EXPORT_SYMBOL_NOVERS(bp_if_scan_sd);
7625
7626#define BP_PROC_DIR "bypass"
7627
7628#define GPIO6_SET_ENTRY_SD "gpio6_set"
7629#define GPIO6_CLEAR_ENTRY_SD "gpio6_clear"
7630
7631#define GPIO7_SET_ENTRY_SD "gpio7_set"
7632#define GPIO7_CLEAR_ENTRY_SD "gpio7_clear"
7633
7634#define PULSE_SET_ENTRY_SD "pulse_set"
7635#define ZERO_SET_ENTRY_SD "zero_set"
7636#define PULSE_GET1_ENTRY_SD "pulse_get1"
7637#define PULSE_GET2_ENTRY_SD "pulse_get2"
7638
7639#define CMND_ON_ENTRY_SD "cmnd_on"
7640#define CMND_OFF_ENTRY_SD "cmnd_off"
7641#define RESET_CONT_ENTRY_SD "reset_cont"
7642
7643 /*COMMANDS*/
7644#define BYPASS_INFO_ENTRY_SD "bypass_info"
7645#define BYPASS_SLAVE_ENTRY_SD "bypass_slave"
7646#define BYPASS_CAPS_ENTRY_SD "bypass_caps"
7647#define WD_SET_CAPS_ENTRY_SD "wd_set_caps"
7648#define BYPASS_ENTRY_SD "bypass"
7649#define BYPASS_CHANGE_ENTRY_SD "bypass_change"
7650#define BYPASS_WD_ENTRY_SD "bypass_wd"
7651#define WD_EXPIRE_TIME_ENTRY_SD "wd_expire_time"
7652#define RESET_BYPASS_WD_ENTRY_SD "reset_bypass_wd"
7653#define DIS_BYPASS_ENTRY_SD "dis_bypass"
7654#define BYPASS_PWUP_ENTRY_SD "bypass_pwup"
7655#define BYPASS_PWOFF_ENTRY_SD "bypass_pwoff"
7656#define STD_NIC_ENTRY_SD "std_nic"
7657#define STD_NIC_ENTRY_SD "std_nic"
7658#define TAP_ENTRY_SD "tap"
7659#define TAP_CHANGE_ENTRY_SD "tap_change"
7660#define DIS_TAP_ENTRY_SD "dis_tap"
7661#define TAP_PWUP_ENTRY_SD "tap_pwup"
7662#define TWO_PORT_LINK_ENTRY_SD "two_port_link"
7663#define WD_EXP_MODE_ENTRY_SD "wd_exp_mode"
7664#define WD_AUTORESET_ENTRY_SD "wd_autoreset"
7665#define TPL_ENTRY_SD "tpl"
7666#define WAIT_AT_PWUP_ENTRY_SD "wait_at_pwup"
7667#define HW_RESET_ENTRY_SD "hw_reset"
7668#define DISC_ENTRY_SD "disc"
7669#define DISC_CHANGE_ENTRY_SD "disc_change"
7670#define DIS_DISC_ENTRY_SD "dis_disc"
7671#define DISC_PWUP_ENTRY_SD "disc_pwup"
7672static struct proc_dir_entry *bp_procfs_dir;
7673
7674static struct proc_dir_entry *proc_getdir(char *name,
7675 struct proc_dir_entry *proc_dir)
7676{
7677 struct proc_dir_entry *pde = proc_dir;
7678
7679 for (pde = pde->subdir; pde; pde = pde->next) {
7680 if (pde->namelen && (strcmp(name, pde->name) == 0)) {
7681 /* directory exists */
7682 break;
7683 }
7684 }
7685 if (pde == (struct proc_dir_entry *)0) {
7686 /* create the directory */
7687#if (LINUX_VERSION_CODE > 0x20300)
7688 pde = proc_mkdir(name, proc_dir);
7689#else
7690 pde = create_proc_entry(name, S_IFDIR, proc_dir);
7691#endif
7692 if (pde == (struct proc_dir_entry *)0) {
7693
7694 return (pde);
7695 }
7696 }
7697
7698 return (pde);
7699}
7700
7701int bp_proc_create(void)
7702{
7703 bp_procfs_dir = proc_getdir(BP_PROC_DIR, init_net.proc_net);
7704 if (bp_procfs_dir == (struct proc_dir_entry *)0) {
7705 printk(KERN_DEBUG
7706 "Could not create procfs nicinfo directory %s\n",
7707 BP_PROC_DIR);
7708 return -1;
7709 }
7710 return 0;
7711}
7712
7713int
7714bypass_proc_create_entry_sd(struct pfs_unit_sd *pfs_unit_curr,
7715 char *proc_name,
7716 write_proc_t * write_proc,
7717 read_proc_t * read_proc,
7718 struct proc_dir_entry *parent_pfs, void *data)
7719{
7720 strcpy(pfs_unit_curr->proc_name, proc_name);
7721 pfs_unit_curr->proc_entry = create_proc_entry(pfs_unit_curr->proc_name,
7722 S_IFREG | S_IRUSR |
7723 S_IWUSR | S_IRGRP |
f325129a 7724 S_IROTH, parent_pfs);
0c4a9f6e 7725 if (pfs_unit_curr->proc_entry == NULL)
7040e556 7726 return -1;
7040e556
D		 7727
7728 pfs_unit_curr->proc_entry->read_proc = read_proc;
7729 pfs_unit_curr->proc_entry->write_proc = write_proc;
7730 pfs_unit_curr->proc_entry->data = data;
7731
7732 return 0;
7733
7734}
7735
7736int
7737get_bypass_info_pfs(char *page, char **start, off_t off, int count,
7738 int *eof, void *data)
7739{
7740 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7741 int len = 0;
7742
7743 len += sprintf(page, "Name\t\t\t%s\n", pbp_device_block->name);
7744 len +=
7745 sprintf(page + len, "Firmware version\t0x%x\n",
7746 pbp_device_block->bp_fw_ver);
7747
7748 *eof = 1;
7749 return len;
7750}
7751
7752int
7753get_bypass_slave_pfs(char *page, char **start, off_t off, int count,
7754 int *eof, void *data)
7755{
7756 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7757
7758 int len = 0;
7759 bpctl_dev_t *pbp_device_block_slave = NULL;
7760 int idx_dev = 0;
7761 struct net_device *net_slave_dev = NULL;
7762
7763 if ((pbp_device_block->func == 0) || (pbp_device_block->func == 2)) {
7764 for (idx_dev = 0;
7765 ((bpctl_dev_arr[idx_dev].pdev != NULL)
7766 && (idx_dev < device_num)); idx_dev++) {
7767 if ((bpctl_dev_arr[idx_dev].bus ==
7768 pbp_device_block->bus)
7769 && (bpctl_dev_arr[idx_dev].slot ==
7770 pbp_device_block->slot)) {
7771 if ((pbp_device_block->func == 0)
7772 && (bpctl_dev_arr[idx_dev].func == 1)) {
7773 pbp_device_block_slave =
7774 &bpctl_dev_arr[idx_dev];
7775 break;
7776 }
7777 if ((pbp_device_block->func == 2) &&
7778 (bpctl_dev_arr[idx_dev].func == 3)) {
7779 pbp_device_block_slave =
7780 &bpctl_dev_arr[idx_dev];
7781 break;
7782 }
7783 }
7784 }
7785 } else
7786 pbp_device_block_slave = pbp_device_block;
7787 if (!pbp_device_block_slave) {
7788 len = sprintf(page, "fail\n");
7789 *eof = 1;
7790 return len;
7791 }
7792 net_slave_dev = pbp_device_block_slave->ndev;
7793 if (net_slave_dev) {
7794 if (net_slave_dev)
7795 len = sprintf(page, "%s\n", net_slave_dev->name);
7796 else
7797 len = sprintf(page, "fail\n");
7798
7799 }
7800
7801 *eof = 1;
7802 return len;
7803}
7804
7805int
7806get_bypass_caps_pfs(char *page, char **start, off_t off, int count,
7807 int *eof, void *data)
7808{
7809 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7810
7811 int len = 0, ret = 0;
7812
7813 ret = get_bypass_caps_fn(pbp_device_block);
7814 if (ret == BP_NOT_CAP)
7815 len = sprintf(page, "-1\n");
7816 else
7817 len = sprintf(page, "0x%x\n", ret);
7818 *eof = 1;
7819 return len;
7820
7821}
7822
7823int
7824get_wd_set_caps_pfs(char *page, char **start, off_t off, int count,
7825 int *eof, void *data)
7826{
7827 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7828
7829 int len = 0, ret = 0;
7830
7831 ret = get_wd_set_caps_fn(pbp_device_block);
7832 if (ret == BP_NOT_CAP)
7833 len = sprintf(page, "-1\n");
7834 else
7835 len = sprintf(page, "0x%x\n", ret);
7836 *eof = 1;
7837 return len;
7838}
7839
7840int
7841set_bypass_pfs(struct file *file, const char *buffer,
7842 unsigned long count, void *data)
7843{
7844
7845 char kbuf[256];
7846 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7847
7848 int bypass_param = 0, length = 0;
7849
7850 if (count > (sizeof(kbuf) - 1))
7851 return -1;
7852
7853 if (copy_from_user(&kbuf, buffer, count)) {
7854 return -1;
7855 }
7856
7857 kbuf[count] = '\0';
7858 length = strlen(kbuf);
7859 if (kbuf[length - 1] == '\n')
7860 kbuf[--length] = '\0';
7861
7862 if (strcmp(kbuf, "on") == 0)
7863 bypass_param = 1;
7864 else if (strcmp(kbuf, "off") == 0)
7865 bypass_param = 0;
7866
7867 set_bypass_fn(pbp_device_block, bypass_param);
7868
7869 return count;
7870}
7871
7872int
7873set_tap_pfs(struct file *file, const char *buffer,
7874 unsigned long count, void *data)
7875{
7876
7877 char kbuf[256];
7878 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7879
7880 int tap_param = 0, length = 0;
7881
7882 if (count > (sizeof(kbuf) - 1))
7883 return -1;
7884
7885 if (copy_from_user(&kbuf, buffer, count)) {
7886 return -1;
7887 }
7888
7889 kbuf[count] = '\0';
7890 length = strlen(kbuf);
7891 if (kbuf[length - 1] == '\n')
7892 kbuf[--length] = '\0';
7893
7894 if (strcmp(kbuf, "on") == 0)
7895 tap_param = 1;
7896 else if (strcmp(kbuf, "off") == 0)
7897 tap_param = 0;
7898
7899 set_tap_fn(pbp_device_block, tap_param);
7900
7901 return count;
7902}
7903
7904int
7905set_disc_pfs(struct file *file, const char *buffer,
7906 unsigned long count, void *data)
7907{
7908
7909 char kbuf[256];
7910 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7911
7912 int tap_param = 0, length = 0;
7913
7914 if (count > (sizeof(kbuf) - 1))
7915 return -1;
7916
7917 if (copy_from_user(&kbuf, buffer, count)) {
7918 return -1;
7919 }
7920
7921 kbuf[count] = '\0';
7922 length = strlen(kbuf);
7923 if (kbuf[length - 1] == '\n')
7924 kbuf[--length] = '\0';
7925
7926 if (strcmp(kbuf, "on") == 0)
7927 tap_param = 1;
7928 else if (strcmp(kbuf, "off") == 0)
7929 tap_param = 0;
7930
7931 set_disc_fn(pbp_device_block, tap_param);
7932
7933 return count;
7934}
7935
7936int
7937get_bypass_pfs(char *page, char **start, off_t off, int count,
7938 int *eof, void *data)
7939{
7940 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7941
7942 int len = 0, ret = 0;
7943
7944 ret = get_bypass_fn(pbp_device_block);
7945 if (ret == BP_NOT_CAP)
7946 len = sprintf(page, "fail\n");
7947 else if (ret == 1)
7948 len = sprintf(page, "on\n");
7949 else if (ret == 0)
7950 len = sprintf(page, "off\n");
7951
7952 *eof = 1;
7953 return len;
7954}
7955
7956int
7957get_tap_pfs(char *page, char **start, off_t off, int count,
7958 int *eof, void *data)
7959{
7960 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7961
7962 int len = 0, ret = 0;
7963
7964 ret = get_tap_fn(pbp_device_block);
7965 if (ret == BP_NOT_CAP)
7966 len = sprintf(page, "fail\n");
7967 else if (ret == 1)
7968 len = sprintf(page, "on\n");
7969 else if (ret == 0)
7970 len = sprintf(page, "off\n");
7971
7972 *eof = 1;
7973 return len;
7974}
7975
7976int
7977get_disc_pfs(char *page, char **start, off_t off, int count,
7978 int *eof, void *data)
7979{
7980 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7981
7982 int len = 0, ret = 0;
7983
7984 ret = get_disc_fn(pbp_device_block);
7985 if (ret == BP_NOT_CAP)
7986 len = sprintf(page, "fail\n");
7987 else if (ret == 1)
7988 len = sprintf(page, "on\n");
7989 else if (ret == 0)
7990 len = sprintf(page, "off\n");
7991
7992 *eof = 1;
7993 return len;
7994}
7995
7996int
7997get_bypass_change_pfs(char *page, char **start, off_t off, int count,
7998 int *eof, void *data)
7999{
8000 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8001
8002 int len = 0, ret = 0;
8003
8004 ret = get_bypass_change_fn(pbp_device_block);
8005 if (ret == 1)
8006 len = sprintf(page, "on\n");
8007 else if (ret == 0)
8008 len = sprintf(page, "off\n");
8009 else
8010 len = sprintf(page, "fail\n");
8011
8012 *eof = 1;
8013 return len;
8014}
8015
8016int
8017get_tap_change_pfs(char *page, char **start, off_t off, int count,
8018 int *eof, void *data)
8019{
8020 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8021
8022 int len = 0, ret = 0;
8023
8024 ret = get_tap_change_fn(pbp_device_block);
8025 if (ret == 1)
8026 len = sprintf(page, "on\n");
8027 else if (ret == 0)
8028 len = sprintf(page, "off\n");
8029 else
8030 len = sprintf(page, "fail\n");
8031
8032 *eof = 1;
8033 return len;
8034}
8035
8036int
8037get_disc_change_pfs(char *page, char **start, off_t off, int count,
8038 int *eof, void *data)
8039{
8040 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8041
8042 int len = 0, ret = 0;
8043
8044 ret = get_disc_change_fn(pbp_device_block);
8045 if (ret == 1)
8046 len = sprintf(page, "on\n");
8047 else if (ret == 0)
8048 len = sprintf(page, "off\n");
8049 else
8050 len = sprintf(page, "fail\n");
8051
8052 *eof = 1;
8053 return len;
8054}
8055
8056#define isdigit(c) (c >= '0' && c <= '9')
8057__inline static int atoi(char **s)
8058{
8059 int i = 0;
8060 while (isdigit(**s))
8061 i = i * 10 + *((*s)++) - '0';
8062 return i;
8063}
8064
8065int
8066set_bypass_wd_pfs(struct file *file, const char *buffer,
8067 unsigned long count, void *data)
8068{
7040e556 8069 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
82e6bb03
DC		 8070 int timeout;
8071 int ret;
7040e556 8072
82e6bb03
DC		 8073 ret = kstrtoint_from_user(buffer, count, 10, &timeout);
8074 if (ret)
8075 return ret;
7040e556
D		 8076 set_bypass_wd_fn(pbp_device_block, timeout);
8077
8078 return count;
8079}
8080
8081int
8082get_bypass_wd_pfs(char *page, char **start, off_t off, int count,
8083 int *eof, void *data)
8084{
8085 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8086
8087 int len = 0, ret = 0, timeout = 0;
8088
8089 ret = get_bypass_wd_fn(pbp_device_block, &timeout);
8090 if (ret == BP_NOT_CAP)
8091 len = sprintf(page, "fail\n");
8092 else if (timeout == -1)
8093 len = sprintf(page, "unknown\n");
8094 else if (timeout == 0)
8095 len = sprintf(page, "disable\n");
8096 else
8097 len = sprintf(page, "%d\n", timeout);
8098
8099 *eof = 1;
8100 return len;
8101}
8102
8103int
8104get_wd_expire_time_pfs(char *page, char **start, off_t off, int count,
8105 int *eof, void *data)
8106{
8107 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8108
8109 int len = 0, ret = 0, timeout = 0;
8110
8111 ret = get_wd_expire_time_fn(pbp_device_block, &timeout);
8112 if (ret == BP_NOT_CAP)
8113 len = sprintf(page, "fail\n");
8114 else if (timeout == -1)
8115 len = sprintf(page, "expire\n");
8116 else if (timeout == 0)
8117 len = sprintf(page, "disable\n");
8118
8119 else
8120 len = sprintf(page, "%d\n", timeout);
8121 *eof = 1;
8122 return len;
8123}
8124
8125int
8126get_tpl_pfs(char *page, char **start, off_t off, int count,
8127 int *eof, void *data)
8128{
8129 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8130
8131 int len = 0, ret = 0;
8132
8133 ret = get_tpl_fn(pbp_device_block);
8134 if (ret == BP_NOT_CAP)
8135 len = sprintf(page, "fail\n");
8136 else if (ret == 1)
8137 len = sprintf(page, "on\n");
8138 else if (ret == 0)
8139 len = sprintf(page, "off\n");
8140
8141 *eof = 1;
8142 return len;
8143}
8144
8145#ifdef PMC_FIX_FLAG
8146int
8147get_wait_at_pwup_pfs(char *page, char **start, off_t off, int count,
8148 int *eof, void *data)
8149{
8150 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8151
8152 int len = 0, ret = 0;
8153
8154 ret = get_bp_wait_at_pwup_fn(pbp_device_block);
8155 if (ret == BP_NOT_CAP)
8156 len = sprintf(page, "fail\n");
8157 else if (ret == 1)
8158 len = sprintf(page, "on\n");
8159 else if (ret == 0)
8160 len = sprintf(page, "off\n");
8161
8162 *eof = 1;
8163 return len;
8164}
8165
8166int
8167get_hw_reset_pfs(char *page, char **start, off_t off, int count,
8168 int *eof, void *data)
8169{
8170 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8171
8172 int len = 0, ret = 0;
8173
8174 ret = get_bp_hw_reset_fn(pbp_device_block);
8175 if (ret == BP_NOT_CAP)
8176 len = sprintf(page, "fail\n");
8177 else if (ret == 1)
8178 len = sprintf(page, "on\n");
8179 else if (ret == 0)
8180 len = sprintf(page, "off\n");
8181
8182 *eof = 1;
8183 return len;
8184}
8185
8186#endif /*PMC_WAIT_FLAG */
8187
8188int
8189reset_bypass_wd_pfs(char *page, char **start, off_t off, int count,
8190 int *eof, void *data)
8191{
8192 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8193
8194 int len = 0, ret = 0;
8195
8196 ret = reset_bypass_wd_timer_fn(pbp_device_block);
8197 if (ret == BP_NOT_CAP)
8198 len = sprintf(page, "fail\n");
8199 else if (ret == 0)
8200 len = sprintf(page, "disable\n");
8201 else if (ret == 1)
8202 len = sprintf(page, "success\n");
8203
8204 *eof = 1;
8205 return len;
8206}
8207
8208int
8209set_dis_bypass_pfs(struct file *file, const char *buffer,
8210 unsigned long count, void *data)
8211{
8212
8213 char kbuf[256];
8214 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8215
8216 int bypass_param = 0, length = 0;
8217
e4c536b7
DC		 8218 if (count >= sizeof(kbuf))
8219 return -EINVAL;
8220
7040e556
D		 8221 if (copy_from_user(&kbuf, buffer, count)) {
8222 return -1;
8223 }
8224
8225 kbuf[count] = '\0';
8226 length = strlen(kbuf);
8227 if (kbuf[length - 1] == '\n')
8228 kbuf[--length] = '\0';
8229
8230 if (strcmp(kbuf, "on") == 0)
8231 bypass_param = 1;
8232 else if (strcmp(kbuf, "off") == 0)
8233 bypass_param = 0;
8234
8235 set_dis_bypass_fn(pbp_device_block, bypass_param);
8236
8237 return count;
8238}
8239
8240int
8241set_dis_tap_pfs(struct file *file, const char *buffer,
8242 unsigned long count, void *data)
8243{
8244
8245 char kbuf[256];
8246 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8247
8248 int tap_param = 0, length = 0;
8249
e4c536b7
DC		 8250 if (count >= sizeof(kbuf))
8251 return -EINVAL;
8252
7040e556
D		 8253 if (copy_from_user(&kbuf, buffer, count)) {
8254 return -1;
8255 }
8256
8257 kbuf[count] = '\0';
8258 length = strlen(kbuf);
8259 if (kbuf[length - 1] == '\n')
8260 kbuf[--length] = '\0';
8261
8262 if (strcmp(kbuf, "on") == 0)
8263 tap_param = 1;
8264 else if (strcmp(kbuf, "off") == 0)
8265 tap_param = 0;
8266
8267 set_dis_tap_fn(pbp_device_block, tap_param);
8268
8269 return count;
8270}
8271
8272int
8273set_dis_disc_pfs(struct file *file, const char *buffer,
8274 unsigned long count, void *data)
8275{
8276
8277 char kbuf[256];
8278 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8279
8280 int tap_param = 0, length = 0;
8281
e4c536b7
DC		 8282 if (count >= sizeof(kbuf))
8283 return -EINVAL;
8284
7040e556
D		 8285 if (copy_from_user(&kbuf, buffer, count)) {
8286 return -1;
8287 }
8288
8289 kbuf[count] = '\0';
8290 length = strlen(kbuf);
8291 if (kbuf[length - 1] == '\n')
8292 kbuf[--length] = '\0';
8293
8294 if (strcmp(kbuf, "on") == 0)
8295 tap_param = 1;
8296 else if (strcmp(kbuf, "off") == 0)
8297 tap_param = 0;
8298
8299 set_dis_disc_fn(pbp_device_block, tap_param);
8300
8301 return count;
8302}
8303
8304int
8305get_dis_bypass_pfs(char *page, char **start, off_t off, int count,
8306 int *eof, void *data)
8307{
8308 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8309
8310 int len = 0, ret = 0;
8311
8312 ret = get_dis_bypass_fn(pbp_device_block);
8313 if (ret == BP_NOT_CAP)
8314 len = sprintf(page, "fail\n");
8315 else if (ret == 0)
8316 len = sprintf(page, "off\n");
8317 else
8318 len = sprintf(page, "on\n");
8319
8320 *eof = 1;
8321 return len;
8322}
8323
8324int
8325get_dis_tap_pfs(char *page, char **start, off_t off, int count,
8326 int *eof, void *data)
8327{
8328 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8329
8330 int len = 0, ret = 0;
8331
8332 ret = get_dis_tap_fn(pbp_device_block);
8333 if (ret == BP_NOT_CAP)
8334 len = sprintf(page, "fail\n");
8335 else if (ret == 0)
8336 len = sprintf(page, "off\n");
8337 else
8338 len = sprintf(page, "on\n");
8339
8340 *eof = 1;
8341 return len;
8342}
8343
8344int
8345get_dis_disc_pfs(char *page, char **start, off_t off, int count,
8346 int *eof, void *data)
8347{
8348 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8349
8350 int len = 0, ret = 0;
8351
8352 ret = get_dis_disc_fn(pbp_device_block);
8353 if (ret == BP_NOT_CAP)
8354 len = sprintf(page, "fail\n");
8355 else if (ret == 0)
8356 len = sprintf(page, "off\n");
8357 else
8358 len = sprintf(page, "on\n");
8359
8360 *eof = 1;
8361 return len;
8362}
8363
8364int
8365set_bypass_pwup_pfs(struct file *file, const char *buffer,
8366 unsigned long count, void *data)
8367{
8368
8369 char kbuf[256];
8370 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8371
8372 int bypass_param = 0, length = 0;
8373
e4c536b7
DC		 8374 if (count >= sizeof(kbuf))
8375 return -EINVAL;
8376
7040e556
D		 8377 if (copy_from_user(&kbuf, buffer, count)) {
8378 return -1;
8379 }
8380
8381 kbuf[count] = '\0';
8382 length = strlen(kbuf);
8383 if (kbuf[length - 1] == '\n')
8384 kbuf[--length] = '\0';
8385
8386 if (strcmp(kbuf, "on") == 0)
8387 bypass_param = 1;
8388 else if (strcmp(kbuf, "off") == 0)
8389 bypass_param = 0;
8390
8391 set_bypass_pwup_fn(pbp_device_block, bypass_param);
8392
8393 return count;
8394}
8395
8396int
8397set_bypass_pwoff_pfs(struct file *file, const char *buffer,
8398 unsigned long count, void *data)
8399{
8400
8401 char kbuf[256];
8402 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8403
8404 int bypass_param = 0, length = 0;
8405
e4c536b7
DC		 8406 if (count >= sizeof(kbuf))
8407 return -EINVAL;
8408
7040e556
D		 8409 if (copy_from_user(&kbuf, buffer, count)) {
8410 return -1;
8411 }
8412
8413 kbuf[count] = '\0';
8414 length = strlen(kbuf);
8415 if (kbuf[length - 1] == '\n')
8416 kbuf[--length] = '\0';
8417
8418 if (strcmp(kbuf, "on") == 0)
8419 bypass_param = 1;
8420 else if (strcmp(kbuf, "off") == 0)
8421 bypass_param = 0;
8422
8423 set_bypass_pwoff_fn(pbp_device_block, bypass_param);
8424
8425 return count;
8426}
8427
8428int
8429set_tap_pwup_pfs(struct file *file, const char *buffer,
8430 unsigned long count, void *data)
8431{
8432
8433 char kbuf[256];
8434 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8435
8436 int tap_param = 0, length = 0;
8437
e4c536b7
DC		 8438 if (count >= sizeof(kbuf))
8439 return -EINVAL;
8440
7040e556
D		 8441 if (copy_from_user(&kbuf, buffer, count)) {
8442 return -1;
8443 }
8444
8445 kbuf[count] = '\0';
8446 length = strlen(kbuf);
8447 if (kbuf[length - 1] == '\n')
8448 kbuf[--length] = '\0';
8449
8450 if (strcmp(kbuf, "on") == 0)
8451 tap_param = 1;
8452 else if (strcmp(kbuf, "off") == 0)
8453 tap_param = 0;
8454
8455 set_tap_pwup_fn(pbp_device_block, tap_param);
8456
8457 return count;
8458}
8459
8460int
8461set_disc_pwup_pfs(struct file *file, const char *buffer,
8462 unsigned long count, void *data)
8463{
8464
8465 char kbuf[256];
8466 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8467
8468 int tap_param = 0, length = 0;
8469
e4c536b7
DC		 8470 if (count >= sizeof(kbuf))
8471 return -EINVAL;
8472
7040e556
D		 8473 if (copy_from_user(&kbuf, buffer, count)) {
8474 return -1;
8475 }
8476
8477 kbuf[count] = '\0';
8478 length = strlen(kbuf);
8479 if (kbuf[length - 1] == '\n')
8480 kbuf[--length] = '\0';
8481
8482 if (strcmp(kbuf, "on") == 0)
8483 tap_param = 1;
8484 else if (strcmp(kbuf, "off") == 0)
8485 tap_param = 0;
8486
8487 set_disc_pwup_fn(pbp_device_block, tap_param);
8488
8489 return count;
8490}
8491
8492int
8493get_bypass_pwup_pfs(char *page, char **start, off_t off, int count,
8494 int *eof, void *data)
8495{
8496 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8497
8498 int len = 0, ret = 0;
8499
8500 ret = get_bypass_pwup_fn(pbp_device_block);
8501 if (ret == BP_NOT_CAP)
8502 len = sprintf(page, "fail\n");
8503 else if (ret == 0)
8504 len = sprintf(page, "off\n");
8505 else
8506 len = sprintf(page, "on\n");
8507
8508 *eof = 1;
8509 return len;
8510}
8511
8512int
8513get_bypass_pwoff_pfs(char *page, char **start, off_t off, int count,
8514 int *eof, void *data)
8515{
8516 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8517
8518 int len = 0, ret = 0;
8519
8520 ret = get_bypass_pwoff_fn(pbp_device_block);
8521 if (ret == BP_NOT_CAP)
8522 len = sprintf(page, "fail\n");
8523 else if (ret == 0)
8524 len = sprintf(page, "off\n");
8525 else
8526 len = sprintf(page, "on\n");
8527
8528 *eof = 1;
8529 return len;
8530}
8531
8532int
8533get_tap_pwup_pfs(char *page, char **start, off_t off, int count,
8534 int *eof, void *data)
8535{
8536 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8537
8538 int len = 0, ret = 0;
8539
8540 ret = get_tap_pwup_fn(pbp_device_block);
8541 if (ret == BP_NOT_CAP)
8542 len = sprintf(page, "fail\n");
8543 else if (ret == 0)
8544 len = sprintf(page, "off\n");
8545 else
8546 len = sprintf(page, "on\n");
8547
8548 *eof = 1;
8549 return len;
8550}
8551
8552int
8553get_disc_pwup_pfs(char *page, char **start, off_t off, int count,
8554 int *eof, void *data)
8555{
8556 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8557
8558 int len = 0, ret = 0;
8559
8560 ret = get_disc_pwup_fn(pbp_device_block);
8561 if (ret == BP_NOT_CAP)
8562 len = sprintf(page, "fail\n");
8563 else if (ret == 0)
8564 len = sprintf(page, "off\n");
8565 else
8566 len = sprintf(page, "on\n");
8567
8568 *eof = 1;
8569 return len;
8570}
8571
8572int
8573set_std_nic_pfs(struct file *file, const char *buffer,
8574 unsigned long count, void *data)
8575{
8576
8577 char kbuf[256];
8578 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8579
8580 int bypass_param = 0, length = 0;
8581
e4c536b7
DC		 8582 if (count >= sizeof(kbuf))
8583 return -EINVAL;
8584
7040e556
D		 8585 if (copy_from_user(&kbuf, buffer, count)) {
8586 return -1;
8587 }
8588
8589 kbuf[count] = '\0';
8590 length = strlen(kbuf);
8591 if (kbuf[length - 1] == '\n')
8592 kbuf[--length] = '\0';
8593
8594 if (strcmp(kbuf, "on") == 0)
8595 bypass_param = 1;
8596 else if (strcmp(kbuf, "off") == 0)
8597 bypass_param = 0;
8598
8599 set_std_nic_fn(pbp_device_block, bypass_param);
8600
8601 return count;
8602}
8603
8604int
8605get_std_nic_pfs(char *page, char **start, off_t off, int count,
8606 int *eof, void *data)
8607{
8608 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8609
8610 int len = 0, ret = 0;
8611
8612 ret = get_std_nic_fn(pbp_device_block);
8613 if (ret == BP_NOT_CAP)
8614 len = sprintf(page, "fail\n");
8615 else if (ret == 0)
8616 len = sprintf(page, "off\n");
8617 else
8618 len = sprintf(page, "on\n");
8619
8620 *eof = 1;
8621 return len;
8622}
8623
8624int
8625get_wd_exp_mode_pfs(char *page, char **start, off_t off, int count,
8626 int *eof, void *data)
8627{
8628 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8629
8630 int len = 0, ret = 0;
8631
8632 ret = get_wd_exp_mode_fn(pbp_device_block);
8633 if (ret == 1)
8634 len = sprintf(page, "tap\n");
8635 else if (ret == 0)
8636 len = sprintf(page, "bypass\n");
8637 else if (ret == 2)
8638 len = sprintf(page, "disc\n");
8639
8640 else
8641 len = sprintf(page, "fail\n");
8642
8643 *eof = 1;
8644 return len;
8645}
8646
8647int
8648set_wd_exp_mode_pfs(struct file *file, const char *buffer,
8649 unsigned long count, void *data)
8650{
8651
8652 char kbuf[256];
8653 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8654
8655 int bypass_param = 0, length = 0;
8656
8657 if (count > (sizeof(kbuf) - 1))
8658 return -1;
8659
8660 if (copy_from_user(&kbuf, buffer, count)) {
8661 return -1;
8662 }
8663
8664 kbuf[count] = '\0';
8665 length = strlen(kbuf);
8666 if (kbuf[length - 1] == '\n')
8667 kbuf[--length] = '\0';
8668
8669 if (strcmp(kbuf, "tap") == 0)
8670 bypass_param = 1;
8671 else if (strcmp(kbuf, "bypass") == 0)
8672 bypass_param = 0;
8673 else if (strcmp(kbuf, "disc") == 0)
8674 bypass_param = 2;
8675
8676 set_wd_exp_mode_fn(pbp_device_block, bypass_param);
8677
8678 return count;
8679}
8680
8681int
8682get_wd_autoreset_pfs(char *page, char **start, off_t off, int count,
8683 int *eof, void *data)
8684{
8685 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8686
8687 int len = 0, ret = 0;
8688
8689 ret = get_wd_autoreset_fn(pbp_device_block);
8690 if (ret >= 0)
8691 len = sprintf(page, "%d\n", ret);
8692 else
8693 len = sprintf(page, "fail\n");
8694
8695 *eof = 1;
8696 return len;
8697}
8698
8699int
8700set_wd_autoreset_pfs(struct file *file, const char *buffer,
8701 unsigned long count, void *data)
8702{
7040e556 8703 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
82e6bb03
DC		 8704 int timeout;
8705 int ret;
7040e556 8706
82e6bb03
DC		 8707 ret = kstrtoint_from_user(buffer, count, 10, &timeout);
8708 if (ret)
8709 return ret;
7040e556
D		 8710 set_wd_autoreset_fn(pbp_device_block, timeout);
8711
8712 return count;
8713}
8714
8715int
8716set_tpl_pfs(struct file *file, const char *buffer,
8717 unsigned long count, void *data)
8718{
8719
8720 char kbuf[256];
8721 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8722
8723 int tpl_param = 0, length = 0;
8724
8725 if (count > (sizeof(kbuf) - 1))
8726 return -1;
8727
8728 if (copy_from_user(&kbuf, buffer, count)) {
8729 return -1;
8730 }
8731
8732 kbuf[count] = '\0';
8733 length = strlen(kbuf);
8734 if (kbuf[length - 1] == '\n')
8735 kbuf[--length] = '\0';
8736
8737 if (strcmp(kbuf, "on") == 0)
8738 tpl_param = 1;
8739 else if (strcmp(kbuf, "off") == 0)
8740 tpl_param = 0;
8741
8742 set_tpl_fn(pbp_device_block, tpl_param);
8743
8744 return count;
8745}
8746
8747#ifdef PMC_FIX_FLAG
8748int
8749set_wait_at_pwup_pfs(struct file *file, const char *buffer,
8750 unsigned long count, void *data)
8751{
8752
8753 char kbuf[256];
8754 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8755
8756 int tpl_param = 0, length = 0;
8757
8758 if (count > (sizeof(kbuf) - 1))
8759 return -1;
8760
8761 if (copy_from_user(&kbuf, buffer, count)) {
8762 return -1;
8763 }
8764
8765 kbuf[count] = '\0';
8766 length = strlen(kbuf);
8767 if (kbuf[length - 1] == '\n')
8768 kbuf[--length] = '\0';
8769
8770 if (strcmp(kbuf, "on") == 0)
8771 tpl_param = 1;
8772 else if (strcmp(kbuf, "off") == 0)
8773 tpl_param = 0;
8774
8775 set_bp_wait_at_pwup_fn(pbp_device_block, tpl_param);
8776
8777 return count;
8778}
8779
8780int
8781set_hw_reset_pfs(struct file *file, const char *buffer,
8782 unsigned long count, void *data)
8783{
8784
8785 char kbuf[256];
8786 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8787
8788 int tpl_param = 0, length = 0;
8789
8790 if (count > (sizeof(kbuf) - 1))
8791 return -1;
8792
8793 if (copy_from_user(&kbuf, buffer, count)) {
8794 return -1;
8795 }
8796
8797 kbuf[count] = '\0';
8798 length = strlen(kbuf);
8799 if (kbuf[length - 1] == '\n')
8800 kbuf[--length] = '\0';
8801
8802 if (strcmp(kbuf, "on") == 0)
8803 tpl_param = 1;
8804 else if (strcmp(kbuf, "off") == 0)
8805 tpl_param = 0;
8806
8807 set_bp_hw_reset_fn(pbp_device_block, tpl_param);
8808
8809 return count;
8810}
8811
8812#endif /*PMC_FIX_FLAG */
8813
8814int bypass_proc_create_dev_sd(bpctl_dev_t * pbp_device_block)
8815{
8816 struct bypass_pfs_sd *current_pfs = &(pbp_device_block->bypass_pfs_set);
8817 static struct proc_dir_entry *procfs_dir = NULL;
8818 int ret = 0;
8819
8820 if (!pbp_device_block->ndev)
8821 return -1;
8822 sprintf(current_pfs->dir_name, "bypass_%s",
8823 pbp_device_block->ndev->name);
8824
8825 if (!bp_procfs_dir)
8826 return -1;
8827
8828 /* create device proc dir */
8829 procfs_dir = proc_getdir(current_pfs->dir_name, bp_procfs_dir);
8830 if (procfs_dir == 0) {
8831 printk(KERN_DEBUG "Could not create procfs directory %s\n",
8832 current_pfs->dir_name);
8833 return -1;
8834 }
8835 current_pfs->bypass_entry = procfs_dir;
8836
8837 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_info), BYPASS_INFO_ENTRY_SD, NULL, /* write */
8838 get_bypass_info_pfs, /* read */
8839 procfs_dir, pbp_device_block))
8840 ret = -1;
8841
8842 if (pbp_device_block->bp_caps & SW_CTL_CAP) {
8843
8844 /* Create set param proc's */
8845 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_slave), BYPASS_SLAVE_ENTRY_SD, NULL, /* write */
8846 get_bypass_slave_pfs, /* read */
8847 procfs_dir, pbp_device_block))
8848 ret = -1;
8849
8850 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_caps), BYPASS_CAPS_ENTRY_SD, NULL, /* write */
8851 get_bypass_caps_pfs, /* read */
8852 procfs_dir, pbp_device_block))
8853 ret = -1;
8854
8855 if (bypass_proc_create_entry_sd(&(current_pfs->wd_set_caps), WD_SET_CAPS_ENTRY_SD, NULL, /* write */
8856 get_wd_set_caps_pfs, /* read */
8857 procfs_dir, pbp_device_block))
8858 ret = -1;
8859 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_wd), BYPASS_WD_ENTRY_SD, set_bypass_wd_pfs, /* write */
8860 get_bypass_wd_pfs, /* read */
8861 procfs_dir, pbp_device_block))
8862 ret = -1;
8863
8864 if (bypass_proc_create_entry_sd(&(current_pfs->wd_expire_time), WD_EXPIRE_TIME_ENTRY_SD, NULL, /* write */
8865 get_wd_expire_time_pfs, /* read */
8866 procfs_dir, pbp_device_block))
8867 ret = -1;
8868
8869 if (bypass_proc_create_entry_sd(&(current_pfs->reset_bypass_wd), RESET_BYPASS_WD_ENTRY_SD, NULL, /* write */
8870 reset_bypass_wd_pfs, /* read */
8871 procfs_dir, pbp_device_block))
8872 ret = -1;
8873
8874 if (bypass_proc_create_entry_sd(&(current_pfs->std_nic), STD_NIC_ENTRY_SD, set_std_nic_pfs, /* write */
8875 get_std_nic_pfs, /* read */
8876 procfs_dir, pbp_device_block))
8877 ret = -1;
8878
8879 if (pbp_device_block->bp_caps & BP_CAP) {
8880 if (bypass_proc_create_entry_sd(&(current_pfs->bypass), BYPASS_ENTRY_SD, set_bypass_pfs, /* write */
8881 get_bypass_pfs, /* read */
8882 procfs_dir,
8883 pbp_device_block))
8884 ret = -1;
8885
8886 if (bypass_proc_create_entry_sd(&(current_pfs->dis_bypass), DIS_BYPASS_ENTRY_SD, set_dis_bypass_pfs, /* write */
8887 get_dis_bypass_pfs, /* read */
8888 procfs_dir,
8889 pbp_device_block))
8890 ret = -1;
8891
8892 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_pwup), BYPASS_PWUP_ENTRY_SD, set_bypass_pwup_pfs, /* write */
8893 get_bypass_pwup_pfs, /* read */
8894 procfs_dir,
8895 pbp_device_block))
8896 ret = -1;
8897 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_pwoff), BYPASS_PWOFF_ENTRY_SD, set_bypass_pwoff_pfs, /* write */
8898 get_bypass_pwoff_pfs, /* read */
8899 procfs_dir,
8900 pbp_device_block))
8901 ret = -1;
8902
8903 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_change), BYPASS_CHANGE_ENTRY_SD, NULL, /* write */
8904 get_bypass_change_pfs, /* read */
8905 procfs_dir,
8906 pbp_device_block))
8907 ret = -1;
8908 }
8909
8910 if (pbp_device_block->bp_caps & TAP_CAP) {
8911
8912 if (bypass_proc_create_entry_sd(&(current_pfs->tap), TAP_ENTRY_SD, set_tap_pfs, /* write */
8913 get_tap_pfs, /* read */
8914 procfs_dir,
8915 pbp_device_block))
8916 ret = -1;
8917
8918 if (bypass_proc_create_entry_sd(&(current_pfs->dis_tap), DIS_TAP_ENTRY_SD, set_dis_tap_pfs, /* write */
8919 get_dis_tap_pfs, /* read */
8920 procfs_dir,
8921 pbp_device_block))
8922 ret = -1;
8923
8924 if (bypass_proc_create_entry_sd(&(current_pfs->tap_pwup), TAP_PWUP_ENTRY_SD, set_tap_pwup_pfs, /* write */
8925 get_tap_pwup_pfs, /* read */
8926 procfs_dir,
8927 pbp_device_block))
8928 ret = -1;
8929
8930 if (bypass_proc_create_entry_sd(&(current_pfs->tap_change), TAP_CHANGE_ENTRY_SD, NULL, /* write */
8931 get_tap_change_pfs, /* read */
8932 procfs_dir,
8933 pbp_device_block))
8934 ret = -1;
8935 }
8936 if (pbp_device_block->bp_caps & DISC_CAP) {
8937
8938 if (bypass_proc_create_entry_sd(&(current_pfs->tap), DISC_ENTRY_SD, set_disc_pfs, /* write */
8939 get_disc_pfs, /* read */
8940 procfs_dir,
8941 pbp_device_block))
8942 ret = -1;
8943#if 1
8944
8945 if (bypass_proc_create_entry_sd(&(current_pfs->dis_tap), DIS_DISC_ENTRY_SD, set_dis_disc_pfs, /* write */
8946 get_dis_disc_pfs, /* read */
8947 procfs_dir,
8948 pbp_device_block))
8949 ret = -1;
8950#endif
8951
8952 if (bypass_proc_create_entry_sd(&(current_pfs->tap_pwup), DISC_PWUP_ENTRY_SD, set_disc_pwup_pfs, /* write */
8953 get_disc_pwup_pfs, /* read */
8954 procfs_dir,
8955 pbp_device_block))
8956 ret = -1;
8957
8958 if (bypass_proc_create_entry_sd(&(current_pfs->tap_change), DISC_CHANGE_ENTRY_SD, NULL, /* write */
8959 get_disc_change_pfs, /* read */
8960 procfs_dir,
8961 pbp_device_block))
8962 ret = -1;
8963 }
8964
8965 if (bypass_proc_create_entry_sd(&(current_pfs->wd_exp_mode), WD_EXP_MODE_ENTRY_SD, set_wd_exp_mode_pfs, /* write */
8966 get_wd_exp_mode_pfs, /* read */
8967 procfs_dir, pbp_device_block))
8968 ret = -1;
8969
8970 if (bypass_proc_create_entry_sd(&(current_pfs->wd_autoreset), WD_AUTORESET_ENTRY_SD, set_wd_autoreset_pfs, /* write */
8971 get_wd_autoreset_pfs, /* read */
8972 procfs_dir, pbp_device_block))
8973 ret = -1;
8974 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), TPL_ENTRY_SD, set_tpl_pfs, /* write */
8975 get_tpl_pfs, /* read */
8976 procfs_dir, pbp_device_block))
8977 ret = -1;
8978#ifdef PMC_FIX_FLAG
8979 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), WAIT_AT_PWUP_ENTRY_SD, set_wait_at_pwup_pfs, /* write */
8980 get_wait_at_pwup_pfs, /* read */
8981 procfs_dir, pbp_device_block))
8982 ret = -1;
8983 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), HW_RESET_ENTRY_SD, set_hw_reset_pfs, /* write */
8984 get_hw_reset_pfs, /* read */
8985 procfs_dir, pbp_device_block))
8986 ret = -1;
8987
8988#endif
8989
8990 }
8991 if (ret < 0)
8992 printk(KERN_DEBUG "Create proc entry failed\n");
8993
8994 return ret;
8995}
8996
8997int bypass_proc_remove_dev_sd(bpctl_dev_t * pbp_device_block)
8998{
8999
9000 struct bypass_pfs_sd *current_pfs = &pbp_device_block->bypass_pfs_set;
9001 struct proc_dir_entry *pde = current_pfs->bypass_entry, *pde_curr =
9002 NULL;
9003 char name[256];
9004
9005 if (!pde)
9006 return 0;
9007 for (pde = pde->subdir; pde;) {
9008 strcpy(name, pde->name);
9009 pde_curr = pde;
9010 pde = pde->next;
9011 remove_proc_entry(name, current_pfs->bypass_entry);
9012 }
9013 if (!pde)
9014 remove_proc_entry(current_pfs->dir_name, bp_procfs_dir);
9015 current_pfs->bypass_entry = NULL;
9016
9017 return 0;
9018}
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