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silicom: get_bypass_slave_pfs() open-codes lookup_port()
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / silicom / bp_mod.c
CommitLineData
7040e556
D		 1/******************************************************************************/
2/* */
3/* Bypass Control utility, Copyright (c) 2005-20011 Silicom */
4/* */
5/* This program is free software; you can redistribute it and/or modify */
6/* it under the terms of the GNU General Public License as published by */
7/* the Free Software Foundation, located in the file LICENSE. */
8/* Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. */
9/* */
10/* */
11/******************************************************************************/
7040e556
D		 12
13#include <linux/kernel.h> /* We're doing kernel work */
14#include <linux/module.h> /* Specifically, a module */
15#include <linux/fs.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/netdevice.h>
19#include <linux/rtnetlink.h>
20#include <linux/rcupdate.h>
21#include <linux/etherdevice.h>
22
86bc9ebb 23#include <linux/uaccess.h> /* for get_user and put_user */
7040e556
D		 24#include <linux/sched.h>
25#include <linux/ethtool.h>
26#include <linux/proc_fs.h>
27
28#include "bp_ioctl.h"
29#include "bp_mod.h"
30#include "bypass.h"
31#include "libbp_sd.h"
32
33#define SUCCESS 0
34#define BP_MOD_VER "9.0.4"
35#define BP_MOD_DESCR "Silicom Bypass-SD Control driver"
36#define BP_SYNC_FLAG 1
37
38static int Device_Open = 0;
39static int major_num = 0;
40
41MODULE_AUTHOR("Anna Lukin, annal@silicom.co.il");
42MODULE_LICENSE("GPL");
43MODULE_DESCRIPTION(BP_MOD_DESCR);
44MODULE_VERSION(BP_MOD_VER);
45spinlock_t bpvm_lock;
46
47#define lock_bpctl() \
48if (down_interruptible(&bpctl_sema)) { \
49 return -ERESTARTSYS; \
50} \
51
52#define unlock_bpctl() \
53 up(&bpctl_sema);
54
55/* Media Types */
56typedef enum {
57 bp_copper = 0,
58 bp_fiber,
59 bp_cx4,
60 bp_none,
61} bp_media_type;
62
63struct pfs_unit_sd {
64 struct proc_dir_entry *proc_entry;
65 char proc_name[32];
66};
67
68struct bypass_pfs_sd {
69 char dir_name[32];
70 struct proc_dir_entry *bypass_entry;
71 struct pfs_unit_sd bypass_info;
72 struct pfs_unit_sd bypass_slave;
73 struct pfs_unit_sd bypass_caps;
74 struct pfs_unit_sd wd_set_caps;
75 struct pfs_unit_sd bypass;
76 struct pfs_unit_sd bypass_change;
77 struct pfs_unit_sd bypass_wd;
78 struct pfs_unit_sd wd_expire_time;
79 struct pfs_unit_sd reset_bypass_wd;
80 struct pfs_unit_sd dis_bypass;
81 struct pfs_unit_sd bypass_pwup;
82 struct pfs_unit_sd bypass_pwoff;
83 struct pfs_unit_sd std_nic;
84 struct pfs_unit_sd tap;
85 struct pfs_unit_sd dis_tap;
86 struct pfs_unit_sd tap_pwup;
87 struct pfs_unit_sd tap_change;
88 struct pfs_unit_sd wd_exp_mode;
89 struct pfs_unit_sd wd_autoreset;
90 struct pfs_unit_sd tpl;
91
92};
93
94typedef struct _bpctl_dev {
95 char *name;
96 char *desc;
97 struct pci_dev *pdev; /* PCI device */
98 struct net_device *ndev; /* net device */
99 unsigned long mem_map;
100 uint8_t bus;
101 uint8_t slot;
102 uint8_t func;
103 u_int32_t device;
104 u_int32_t vendor;
105 u_int32_t subvendor;
106 u_int32_t subdevice;
107 int ifindex;
108 uint32_t bp_caps;
109 uint32_t bp_caps_ex;
110 uint8_t bp_fw_ver;
111 int bp_ext_ver;
112 int wdt_status;
113 unsigned long bypass_wdt_on_time;
114 uint32_t bypass_timer_interval;
115 struct timer_list bp_timer;
116 uint32_t reset_time;
117 uint8_t bp_status_un;
118 atomic_t wdt_busy;
119 bp_media_type media_type;
120 int bp_tpl_flag;
121 struct timer_list bp_tpl_timer;
122 spinlock_t bypass_wr_lock;
123 int bp_10g;
124 int bp_10gb;
125 int bp_fiber5;
126 int bp_10g9;
127 int bp_i80;
128 int bp_540;
01448bbb
DC		 129 int (*hard_start_xmit_save) (struct sk_buff *skb,
130 struct net_device *dev);
7040e556
D		 131 const struct net_device_ops *old_ops;
132 struct net_device_ops new_ops;
133 int bp_self_test_flag;
134 char *bp_tx_data;
7040e556
D		 135 struct bypass_pfs_sd bypass_pfs_set;
136
137} bpctl_dev_t;
138
139static bpctl_dev_t *bpctl_dev_arr;
140
141static struct semaphore bpctl_sema;
142static int device_num = 0;
143
144static int get_dev_idx(int ifindex);
01448bbb
DC		 145static bpctl_dev_t *get_master_port_fn(bpctl_dev_t *pbpctl_dev);
146static int disc_status(bpctl_dev_t *pbpctl_dev);
147static int bypass_status(bpctl_dev_t *pbpctl_dev);
148static int wdt_timer(bpctl_dev_t *pbpctl_dev, int *time_left);
149static bpctl_dev_t *get_status_port_fn(bpctl_dev_t *pbpctl_dev);
7040e556
D		 150static void if_scan_init(void);
151
01448bbb
DC		 152int bypass_proc_create_dev_sd(bpctl_dev_t *pbp_device_block);
153int bypass_proc_remove_dev_sd(bpctl_dev_t *pbp_device_block);
7040e556
D		 154int bp_proc_create(void);
155
01448bbb 156int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
7040e556
D		 157int get_dev_idx_bsf(int bus, int slot, int func);
158
159static unsigned long str_to_hex(char *p);
160static int bp_device_event(struct notifier_block *unused,
161 unsigned long event, void *ptr)
162{
163 struct net_device *dev = ptr;
164 static bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
165 int dev_num = 0, ret = 0, ret_d = 0, time_left = 0;
687bcca0
DC		 166 /* printk("BP_PROC_SUPPORT event =%d %s %d\n", event,dev->name, dev->ifindex ); */
167 /* return NOTIFY_DONE; */
7040e556
D		 168 if (!dev)
169 return NOTIFY_DONE;
170 if (event == NETDEV_REGISTER) {
171 {
172 struct ethtool_drvinfo drvinfo;
7040e556
D		 173 char cbuf[32];
174 char *buf = NULL;
175 char res[10];
176 int i = 0, ifindex, idx_dev = 0;
177 int bus = 0, slot = 0, func = 0;
178 ifindex = dev->ifindex;
179
180 memset(res, 0, 10);
181 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
182
183 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
184 memset(&drvinfo, 0, sizeof(drvinfo));
185 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
186 } else
187 return NOTIFY_DONE;
188 if (!drvinfo.bus_info)
189 return NOTIFY_DONE;
190 if (!strcmp(drvinfo.bus_info, "N/A"))
191 return NOTIFY_DONE;
192 memcpy(&cbuf, drvinfo.bus_info, 32);
193 buf = &cbuf[0];
194
7040e556
D		 195 while (*buf++ != ':') ;
196 for (i = 0; i < 10; i++, buf++) {
197 if (*buf == ':')
198 break;
199 res[i] = *buf;
200
201 }
202 buf++;
203 bus = str_to_hex(res);
204 memset(res, 0, 10);
205
206 for (i = 0; i < 10; i++, buf++) {
207 if (*buf == '.')
208 break;
209 res[i] = *buf;
210
211 }
212 buf++;
213 slot = str_to_hex(res);
214 func = str_to_hex(buf);
215 idx_dev = get_dev_idx_bsf(bus, slot, func);
216
217 if (idx_dev != -1) {
218
219 bpctl_dev_arr[idx_dev].ifindex = ifindex;
220 bpctl_dev_arr[idx_dev].ndev = dev;
221
222 bypass_proc_remove_dev_sd(&bpctl_dev_arr
223 [idx_dev]);
224 bypass_proc_create_dev_sd(&bpctl_dev_arr
225 [idx_dev]);
226
227 }
228
229 }
230 return NOTIFY_DONE;
231
232 }
233 if (event == NETDEV_UNREGISTER) {
234 int idx_dev = 0;
7040e556
D		 235 for (idx_dev = 0;
236 ((bpctl_dev_arr[idx_dev].pdev != NULL)
237 && (idx_dev < device_num)); idx_dev++) {
238 if (bpctl_dev_arr[idx_dev].ndev == dev) {
239 bypass_proc_remove_dev_sd(&bpctl_dev_arr
240 [idx_dev]);
241 bpctl_dev_arr[idx_dev].ndev = NULL;
242
243 return NOTIFY_DONE;
244
245 }
246
247 }
248 return NOTIFY_DONE;
249 }
250 if (event == NETDEV_CHANGENAME) {
251 int idx_dev = 0;
7040e556
D		 252 for (idx_dev = 0;
253 ((bpctl_dev_arr[idx_dev].pdev != NULL)
254 && (idx_dev < device_num)); idx_dev++) {
255 if (bpctl_dev_arr[idx_dev].ndev == dev) {
256 bypass_proc_remove_dev_sd(&bpctl_dev_arr
257 [idx_dev]);
258 bypass_proc_create_dev_sd(&bpctl_dev_arr
259 [idx_dev]);
260
261 return NOTIFY_DONE;
262
263 }
264
265 }
266 return NOTIFY_DONE;
267
268 }
7040e556
D		 269
270 switch (event) {
271
272 case NETDEV_CHANGE:{
273 if (netif_carrier_ok(dev))
274 return NOTIFY_DONE;
275
7040e556
D		 276 if (((dev_num = get_dev_idx(dev->ifindex)) == -1) ||
277 (!(pbpctl_dev = &bpctl_dev_arr[dev_num])))
278 return NOTIFY_DONE;
279
280 if ((is_bypass_fn(pbpctl_dev)) == 1)
281 pbpctl_dev_m = pbpctl_dev;
282 else
283 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
284 if (!pbpctl_dev_m)
285 return NOTIFY_DONE;
286 ret = bypass_status(pbpctl_dev_m);
287 if (ret == 1)
288 printk("bpmod: %s is in the Bypass mode now",
289 dev->name);
290 ret_d = disc_status(pbpctl_dev_m);
291 if (ret_d == 1)
292 printk
293 ("bpmod: %s is in the Disconnect mode now",
294 dev->name);
295 if (ret || ret_d) {
296 wdt_timer(pbpctl_dev_m, &time_left);
297 if (time_left == -1)
298 printk("; WDT has expired");
299 printk(".\n");
300
301 }
302 return NOTIFY_DONE;
303
304 }
305
306 default:
307 return NOTIFY_DONE;
308
309 }
310 return NOTIFY_DONE;
311
312}
313
314static struct notifier_block bp_notifier_block = {
315 .notifier_call = bp_device_event,
316};
317
318static int device_open(struct inode *inode, struct file *file)
319{
320#ifdef DEBUG
321 printk("device_open(%p)\n", file);
322#endif
323 Device_Open++;
324/*
325* Initialize the message
326*/
327 return SUCCESS;
328}
329
330static int device_release(struct inode *inode, struct file *file)
331{
332#ifdef DEBUG
333 printk("device_release(%p,%p)\n", inode, file);
334#endif
335 Device_Open--;
336 return SUCCESS;
337}
338
01448bbb
DC		 339int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
340int wdt_time_left(bpctl_dev_t *pbpctl_dev);
7040e556 341
01448bbb 342static void write_pulse(bpctl_dev_t *pbpctl_dev,
7040e556
D		 343 unsigned int ctrl_ext,
344 unsigned char value, unsigned char len)
345{
346 unsigned char ctrl_val = 0;
347 unsigned int i = len;
348 unsigned int ctrl = 0;
349 bpctl_dev_t *pbpctl_dev_c = NULL;
350
351 if (pbpctl_dev->bp_i80)
352 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
353 if (pbpctl_dev->bp_540)
354 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
355
356 if (pbpctl_dev->bp_10g9) {
357 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
358 return;
359 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
360 }
361
362 while (i--) {
363 ctrl_val = (value >> i) & 0x1;
364 if (ctrl_val) {
365 if (pbpctl_dev->bp_10g9) {
366
367 /* To start management : MCLK 1, MDIO 1, output */
368 /* DATA 1 CLK 1 */
369 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
370 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
371 ctrl_ext |
372 BP10G_MDIO_DATA_OUT9);
373 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
374 (ctrl | BP10G_MCLK_DATA_OUT9 |
375 BP10G_MCLK_DIR_OUT9));
376
377 } else if (pbpctl_dev->bp_fiber5) {
378 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
379 BPCTLI_CTRL_EXT_MCLK_DIR5
380 |
381 BPCTLI_CTRL_EXT_MDIO_DIR5
382 |
383 BPCTLI_CTRL_EXT_MDIO_DATA5
384 |
385 BPCTLI_CTRL_EXT_MCLK_DATA5));
386
387 } else if (pbpctl_dev->bp_i80) {
388 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
389 BPCTLI_CTRL_EXT_MDIO_DIR80
390 |
391 BPCTLI_CTRL_EXT_MDIO_DATA80));
392
393 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, (ctrl |
394 BPCTLI_CTRL_EXT_MCLK_DIR80
395 |
396 BPCTLI_CTRL_EXT_MCLK_DATA80));
397
398 } else if (pbpctl_dev->bp_540) {
399 BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl |
400 BP540_MDIO_DIR
401 |
402 BP540_MDIO_DATA
403 |
404 BP540_MCLK_DIR
405 |
406 BP540_MCLK_DATA));
407
408 } else if (pbpctl_dev->bp_10gb) {
409 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
410 (ctrl_ext | BP10GB_MDIO_SET |
411 BP10GB_MCLK_SET) &
412 ~(BP10GB_MCLK_DIR |
413 BP10GB_MDIO_DIR |
414 BP10GB_MDIO_CLR |
415 BP10GB_MCLK_CLR));
416
417 } else if (!pbpctl_dev->bp_10g)
418 /* To start management : MCLK 1, MDIO 1, output */
419 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
420 (ctrl_ext |
421 BPCTLI_CTRL_EXT_MCLK_DIR |
422 BPCTLI_CTRL_EXT_MDIO_DIR |
423 BPCTLI_CTRL_EXT_MDIO_DATA |
424 BPCTLI_CTRL_EXT_MCLK_DATA));
425 else {
426
687bcca0 427 /* To start management : MCLK 1, MDIO 1, output*/
7040e556
D		 428 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
429 (ctrl_ext | BP10G_MCLK_DATA_OUT
430 | BP10G_MDIO_DATA_OUT));
7040e556
D		 431
432 }
433
434 usec_delay(PULSE_TIME);
435 if (pbpctl_dev->bp_10g9) {
436
437 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~(BP10G_MCLK_DATA_OUT9))); */
438 /* DATA 1 CLK 0 */
439 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
440 ctrl_ext |
441 BP10G_MDIO_DATA_OUT9);
442 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
443 (ctrl | BP10G_MCLK_DIR_OUT9) &
444 ~BP10G_MCLK_DATA_OUT9);
445
446 } else if (pbpctl_dev->bp_fiber5) {
447 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
448 ((ctrl_ext |
449 BPCTLI_CTRL_EXT_MCLK_DIR5 |
450 BPCTLI_CTRL_EXT_MDIO_DIR5 |
451 BPCTLI_CTRL_EXT_MDIO_DATA5)
452 &
453 ~
454 (BPCTLI_CTRL_EXT_MCLK_DATA5)));
455
456 } else if (pbpctl_dev->bp_i80) {
457 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
458 BPCTLI_CTRL_EXT_MDIO_DIR80
459 |
460 BPCTLI_CTRL_EXT_MDIO_DATA80));
461 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
462 ((ctrl |
463 BPCTLI_CTRL_EXT_MCLK_DIR80)
464 &
465 ~
466 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
467
468 } else if (pbpctl_dev->bp_540) {
469 BP10G_WRITE_REG(pbpctl_dev, ESDP,
470 (ctrl | BP540_MDIO_DIR |
471 BP540_MDIO_DATA |
472 BP540_MCLK_DIR) &
473 ~(BP540_MCLK_DATA));
474
475 } else if (pbpctl_dev->bp_10gb) {
476
477 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
478 (ctrl_ext | BP10GB_MDIO_SET |
479 BP10GB_MCLK_CLR) &
480 ~(BP10GB_MCLK_DIR |
481 BP10GB_MDIO_DIR |
482 BP10GB_MDIO_CLR |
483 BP10GB_MCLK_SET));
484
485 } else if (!pbpctl_dev->bp_10g)
486
487 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
488 ((ctrl_ext |
489 BPCTLI_CTRL_EXT_MCLK_DIR |
490 BPCTLI_CTRL_EXT_MDIO_DIR |
491 BPCTLI_CTRL_EXT_MDIO_DATA)
492 &
493 ~
494 (BPCTLI_CTRL_EXT_MCLK_DATA)));
495 else {
496
7040e556
D		 497 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
498 ((ctrl_ext |
499 BP10G_MDIO_DATA_OUT) &
500 ~(BP10G_MCLK_DATA_OUT)));
7040e556
D		 501 }
502
503 usec_delay(PULSE_TIME);
504
505 } else {
506 if (pbpctl_dev->bp_10g9) {
507 /* DATA 0 CLK 1 */
508 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
509 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
510 (ctrl_ext &
511 ~BP10G_MDIO_DATA_OUT9));
512 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
513 (ctrl | BP10G_MCLK_DATA_OUT9 |
514 BP10G_MCLK_DIR_OUT9));
515
516 } else if (pbpctl_dev->bp_fiber5) {
517 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
518 ((ctrl_ext |
519 BPCTLI_CTRL_EXT_MCLK_DIR5 |
520 BPCTLI_CTRL_EXT_MDIO_DIR5 |
521 BPCTLI_CTRL_EXT_MCLK_DATA5)
522 &
523 ~
524 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
525
526 } else if (pbpctl_dev->bp_i80) {
527 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
528 ((ctrl_ext |
529 BPCTLI_CTRL_EXT_MDIO_DIR80)
530 &
531 ~
532 (BPCTLI_CTRL_EXT_MDIO_DATA80)));
533 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
534 (ctrl |
535 BPCTLI_CTRL_EXT_MCLK_DIR80 |
536 BPCTLI_CTRL_EXT_MCLK_DATA80));
537
538 } else if (pbpctl_dev->bp_540) {
539 BP10G_WRITE_REG(pbpctl_dev, ESDP,
540 ((ctrl | BP540_MCLK_DIR |
541 BP540_MCLK_DATA |
542 BP540_MDIO_DIR) &
543 ~(BP540_MDIO_DATA)));
544
545 } else if (pbpctl_dev->bp_10gb) {
546 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
547 (ctrl_ext | BP10GB_MDIO_CLR |
548 BP10GB_MCLK_SET) &
549 ~(BP10GB_MCLK_DIR |
550 BP10GB_MDIO_DIR |
551 BP10GB_MDIO_SET |
552 BP10GB_MCLK_CLR));
553
554 } else if (!pbpctl_dev->bp_10g)
555
556 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
557 ((ctrl_ext |
558 BPCTLI_CTRL_EXT_MCLK_DIR |
559 BPCTLI_CTRL_EXT_MDIO_DIR |
560 BPCTLI_CTRL_EXT_MCLK_DATA)
561 &
562 ~
563 (BPCTLI_CTRL_EXT_MDIO_DATA)));
564 else {
565
7040e556
D		 566 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
567 ((ctrl_ext |
568 BP10G_MCLK_DATA_OUT) &
569 ~BP10G_MDIO_DATA_OUT));
7040e556
D		 570
571 }
572 usec_delay(PULSE_TIME);
573 if (pbpctl_dev->bp_10g9) {
574 /* DATA 0 CLK 0 */
575 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
576 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
577 (ctrl_ext &
578 ~BP10G_MDIO_DATA_OUT9));
579 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
580 ((ctrl | BP10G_MCLK_DIR_OUT9) &
581 ~(BP10G_MCLK_DATA_OUT9)));
582
583 } else if (pbpctl_dev->bp_fiber5) {
584 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
585 ((ctrl_ext |
586 BPCTLI_CTRL_EXT_MCLK_DIR5 |
587 BPCTLI_CTRL_EXT_MDIO_DIR5)
588 &
589 ~(BPCTLI_CTRL_EXT_MCLK_DATA5
590 |
591 BPCTLI_CTRL_EXT_MDIO_DATA5)));
592
593 } else if (pbpctl_dev->bp_i80) {
594 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
595 ((ctrl_ext |
596 BPCTLI_CTRL_EXT_MDIO_DIR80)
597 &
598 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
599 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
600 ((ctrl |
601 BPCTLI_CTRL_EXT_MCLK_DIR80)
602 &
603 ~
604 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
605
606 } else if (pbpctl_dev->bp_540) {
607 BP10G_WRITE_REG(pbpctl_dev, ESDP,
608 ((ctrl | BP540_MCLK_DIR |
609 BP540_MDIO_DIR) &
610 ~(BP540_MDIO_DATA |
611 BP540_MCLK_DATA)));
612 } else if (pbpctl_dev->bp_10gb) {
613
614 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
615 (ctrl_ext | BP10GB_MDIO_CLR |
616 BP10GB_MCLK_CLR) &
617 ~(BP10GB_MCLK_DIR |
618 BP10GB_MDIO_DIR |
619 BP10GB_MDIO_SET |
620 BP10GB_MCLK_SET));
621
622 } else if (!pbpctl_dev->bp_10g)
623 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
624 ((ctrl_ext |
625 BPCTLI_CTRL_EXT_MCLK_DIR |
626 BPCTLI_CTRL_EXT_MDIO_DIR) &
627 ~(BPCTLI_CTRL_EXT_MCLK_DATA
628 |
629 BPCTLI_CTRL_EXT_MDIO_DATA)));
630 else {
631
7040e556
D		 632 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
633 (ctrl_ext &
634 ~(BP10G_MCLK_DATA_OUT |
635 BP10G_MDIO_DATA_OUT)));
7040e556
D		 636 }
637
638 usec_delay(PULSE_TIME);
639 }
640
641 }
642}
643
01448bbb 644static int read_pulse(bpctl_dev_t *pbpctl_dev, unsigned int ctrl_ext,
7040e556
D		 645 unsigned char len)
646{
647 unsigned char ctrl_val = 0;
648 unsigned int i = len;
649 unsigned int ctrl = 0;
650 bpctl_dev_t *pbpctl_dev_c = NULL;
651
652 if (pbpctl_dev->bp_i80)
653 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
654 if (pbpctl_dev->bp_540)
655 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
656 if (pbpctl_dev->bp_10g9) {
657 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
658 return -1;
659 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
660 }
661
7040e556
D		 662
663 while (i--) {
664 if (pbpctl_dev->bp_10g9) {
665 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~BP10G_MCLK_DATA_OUT9)); */
666 /* DATA ? CLK 0 */
667 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
668 ((ctrl | BP10G_MCLK_DIR_OUT9) &
669 ~(BP10G_MCLK_DATA_OUT9)));
670
671 } else if (pbpctl_dev->bp_fiber5) {
672 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
673 BPCTLI_CTRL_EXT_MCLK_DIR5)
674 &
675 ~
676 (BPCTLI_CTRL_EXT_MDIO_DIR5
677 |
678 BPCTLI_CTRL_EXT_MCLK_DATA5)));
679
680 } else if (pbpctl_dev->bp_i80) {
681 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
682 (ctrl_ext &
683 ~BPCTLI_CTRL_EXT_MDIO_DIR80));
684 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
685 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80)
686 & ~(BPCTLI_CTRL_EXT_MCLK_DATA80)));
687
688 } else if (pbpctl_dev->bp_540) {
689 BP10G_WRITE_REG(pbpctl_dev, ESDP,
690 ((ctrl | BP540_MCLK_DIR) &
691 ~(BP540_MDIO_DIR | BP540_MCLK_DATA)));
692
693 } else if (pbpctl_dev->bp_10gb) {
694
695 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
696 (ctrl_ext | BP10GB_MDIO_DIR |
697 BP10GB_MCLK_CLR) & ~(BP10GB_MCLK_DIR |
698 BP10GB_MDIO_CLR |
699 BP10GB_MDIO_SET |
700 BP10GB_MCLK_SET));
701
702 } else if (!pbpctl_dev->bp_10g)
703 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
704 BPCTLI_CTRL_EXT_MCLK_DIR)
705 &
706 ~
707 (BPCTLI_CTRL_EXT_MDIO_DIR
708 |
709 BPCTLI_CTRL_EXT_MCLK_DATA)));
710 else {
711
7040e556 712 BP10G_WRITE_REG(pbpctl_dev, EODSDP, ((ctrl_ext | BP10G_MDIO_DATA_OUT) & ~BP10G_MCLK_DATA_OUT)); /* ? */
687bcca0 713 /* printk("0x28=0x%x\n",BP10G_READ_REG(pbpctl_dev,EODSDP);); */
7040e556
D		 714
715 }
716
717 usec_delay(PULSE_TIME);
718 if (pbpctl_dev->bp_10g9) {
719 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
720 /* DATA ? CLK 1 */
721 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
722 (ctrl | BP10G_MCLK_DATA_OUT9 |
723 BP10G_MCLK_DIR_OUT9));
724
725 } else if (pbpctl_dev->bp_fiber5) {
726 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
727 BPCTLI_CTRL_EXT_MCLK_DIR5
728 |
729 BPCTLI_CTRL_EXT_MCLK_DATA5)
730 &
731 ~
732 (BPCTLI_CTRL_EXT_MDIO_DIR5)));
733
734 } else if (pbpctl_dev->bp_i80) {
735 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
736 (ctrl_ext &
737 ~(BPCTLI_CTRL_EXT_MDIO_DIR80)));
738 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
739 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
740 BPCTLI_CTRL_EXT_MCLK_DATA80));
741
742 } else if (pbpctl_dev->bp_540) {
743 BP10G_WRITE_REG(pbpctl_dev, ESDP,
744 ((ctrl | BP540_MCLK_DIR |
745 BP540_MCLK_DATA) &
746 ~(BP540_MDIO_DIR)));
747
748 } else if (pbpctl_dev->bp_10gb) {
749 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
750 (ctrl_ext | BP10GB_MDIO_DIR |
751 BP10GB_MCLK_SET) & ~(BP10GB_MCLK_DIR |
752 BP10GB_MDIO_CLR |
753 BP10GB_MDIO_SET |
754 BP10GB_MCLK_CLR));
755
756 } else if (!pbpctl_dev->bp_10g)
757 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
758 BPCTLI_CTRL_EXT_MCLK_DIR
759 |
760 BPCTLI_CTRL_EXT_MCLK_DATA)
761 &
762 ~
763 (BPCTLI_CTRL_EXT_MDIO_DIR)));
764 else {
765
7040e556
D		 766 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
767 (ctrl_ext | BP10G_MCLK_DATA_OUT |
768 BP10G_MDIO_DATA_OUT));
7040e556
D		 769
770 }
771 if (pbpctl_dev->bp_10g9) {
772 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
773
774 } else if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_i80)) {
775 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
776 } else if (pbpctl_dev->bp_540) {
777 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
778 } else if (pbpctl_dev->bp_10gb)
779 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
780
781 else if (!pbpctl_dev->bp_10g)
782 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
783 else
784 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
7040e556
D		 785
786 usec_delay(PULSE_TIME);
787 if (pbpctl_dev->bp_10g9) {
788 if (ctrl_ext & BP10G_MDIO_DATA_IN9)
789 ctrl_val |= 1 << i;
790
791 } else if (pbpctl_dev->bp_fiber5) {
792 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA5)
793 ctrl_val |= 1 << i;
794 } else if (pbpctl_dev->bp_i80) {
795 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA80)
796 ctrl_val |= 1 << i;
797 } else if (pbpctl_dev->bp_540) {
798 if (ctrl_ext & BP540_MDIO_DATA)
799 ctrl_val |= 1 << i;
800 } else if (pbpctl_dev->bp_10gb) {
801 if (ctrl_ext & BP10GB_MDIO_DATA)
802 ctrl_val |= 1 << i;
803
804 } else if (!pbpctl_dev->bp_10g) {
805
806 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA)
807 ctrl_val |= 1 << i;
808 } else {
809
810 if (ctrl_ext & BP10G_MDIO_DATA_IN)
811 ctrl_val |= 1 << i;
812 }
813
814 }
815
816 return ctrl_val;
817}
818
01448bbb 819static void write_reg(bpctl_dev_t *pbpctl_dev, unsigned char value,
7040e556
D		 820 unsigned char addr)
821{
822 uint32_t ctrl_ext = 0, ctrl = 0;
823 bpctl_dev_t *pbpctl_dev_c = NULL;
824 unsigned long flags;
825 if (pbpctl_dev->bp_10g9) {
826 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
827 return;
828 }
829 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
830 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER))
831 wdt_time_left(pbpctl_dev);
832
833#ifdef BP_SYNC_FLAG
834 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
835#else
836 atomic_set(&pbpctl_dev->wdt_busy, 1);
837#endif
838 if (pbpctl_dev->bp_10g9) {
839
840 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
841 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
842 /* DATA 0 CLK 0 */
843 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
844 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
845 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
846 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
847 ((ctrl | BP10G_MCLK_DIR_OUT9) &
848 ~(BP10G_MCLK_DATA_OUT9)));
849
850 } else if (pbpctl_dev->bp_fiber5) {
851 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
852 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
853 BPCTLI_CTRL_EXT_MCLK_DIR5
854 |
855 BPCTLI_CTRL_EXT_MDIO_DIR5)
856 &
857 ~
858 (BPCTLI_CTRL_EXT_MDIO_DATA5
859 |
860 BPCTLI_CTRL_EXT_MCLK_DATA5)));
861 } else if (pbpctl_dev->bp_i80) {
862 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
863 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
864 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
865 BPCTLI_CTRL_EXT_MDIO_DIR80)
866 &
867 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
868 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
869 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
870 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
871
872 } else if (pbpctl_dev->bp_540) {
873 ctrl = ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
874 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
875 BP540_MDIO_DIR |
876 BP540_MCLK_DIR) &
877 ~(BP540_MDIO_DATA |
878 BP540_MCLK_DATA)));
879
880 } else if (pbpctl_dev->bp_10gb) {
881 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
882
883 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
884 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
885 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
886 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
887
888 } else if (!pbpctl_dev->bp_10g) {
889
890 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
891 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
892 BPCTLI_CTRL_EXT_MCLK_DIR
893 |
894 BPCTLI_CTRL_EXT_MDIO_DIR)
895 &
896 ~
897 (BPCTLI_CTRL_EXT_MDIO_DATA
898 |
899 BPCTLI_CTRL_EXT_MCLK_DATA)));
900 } else {
901 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
902 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
903 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
904 (ctrl_ext &
905 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556
D		 906 }
907 usec_delay(CMND_INTERVAL);
908
909 /*send sync cmd */
910 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
911 /*send wr cmd */
912 write_pulse(pbpctl_dev, ctrl_ext, WR_CMD_VAL, WR_CMD_LEN);
913 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
914
915 /*write data */
916 write_pulse(pbpctl_dev, ctrl_ext, value, WR_DATA_LEN);
917 if (pbpctl_dev->bp_10g9) {
918 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
919 /* DATA 0 CLK 0 */
920 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
921 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
922 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
923 ((ctrl | BP10G_MCLK_DIR_OUT9) &
924 ~(BP10G_MCLK_DATA_OUT9)));
925
926 } else if (pbpctl_dev->bp_fiber5) {
927 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
928 BPCTLI_CTRL_EXT_MCLK_DIR5
929 |
930 BPCTLI_CTRL_EXT_MDIO_DIR5)
931 &
932 ~
933 (BPCTLI_CTRL_EXT_MDIO_DATA5
934 |
935 BPCTLI_CTRL_EXT_MCLK_DATA5)));
936 } else if (pbpctl_dev->bp_i80) {
937 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
938 BPCTLI_CTRL_EXT_MDIO_DIR80)
939 &
940 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
941 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
942 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
943 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
944 } else if (pbpctl_dev->bp_540) {
945 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
946 BP540_MDIO_DIR |
947 BP540_MCLK_DIR) &
948 ~(BP540_MDIO_DATA |
949 BP540_MCLK_DATA)));
950 } else if (pbpctl_dev->bp_10gb) {
951 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
952 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
953 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
954 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
955
956 } else if (!pbpctl_dev->bp_10g)
957
958 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
959 BPCTLI_CTRL_EXT_MCLK_DIR
960 |
961 BPCTLI_CTRL_EXT_MDIO_DIR)
962 &
963 ~
964 (BPCTLI_CTRL_EXT_MDIO_DATA
965 |
966 BPCTLI_CTRL_EXT_MCLK_DATA)));
967 else {
968 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
969 (ctrl_ext &
970 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556 971
7040e556
D		 972 }
973
974 usec_delay(CMND_INTERVAL * 4);
975
976 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
977 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER) && (addr == CMND_REG_ADDR))
978 pbpctl_dev->bypass_wdt_on_time = jiffies;
979#ifdef BP_SYNC_FLAG
980 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
981#else
982 atomic_set(&pbpctl_dev->wdt_busy, 0);
983#endif
984
985}
986
01448bbb 987static void write_data(bpctl_dev_t *pbpctl_dev, unsigned char value)
7040e556
D		 988{
989 write_reg(pbpctl_dev, value, CMND_REG_ADDR);
990}
991
01448bbb 992static int read_reg(bpctl_dev_t *pbpctl_dev, unsigned char addr)
7040e556
D		 993{
994 uint32_t ctrl_ext = 0, ctrl = 0, ctrl_value = 0;
995 bpctl_dev_t *pbpctl_dev_c = NULL;
996
997#ifdef BP_SYNC_FLAG
998 unsigned long flags;
999 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1000#else
1001 atomic_set(&pbpctl_dev->wdt_busy, 1);
1002#endif
1003 if (pbpctl_dev->bp_10g9) {
1004 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
1005 return -1;
1006 }
1007
1008 if (pbpctl_dev->bp_10g9) {
1009 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1010 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1011
1012 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1013 /* DATA 0 CLK 0 */
1014 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1015 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1016 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1017 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1018 ~(BP10G_MCLK_DATA_OUT9)));
1019
1020 } else if (pbpctl_dev->bp_fiber5) {
1021 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1022
1023 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1024 BPCTLI_CTRL_EXT_MCLK_DIR5
1025 |
1026 BPCTLI_CTRL_EXT_MDIO_DIR5)
1027 &
1028 ~
1029 (BPCTLI_CTRL_EXT_MDIO_DATA5
1030 |
1031 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1032 } else if (pbpctl_dev->bp_i80) {
1033 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1034 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1035
1036 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1037 BPCTLI_CTRL_EXT_MDIO_DIR80)
1038 &
1039 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1040 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1041 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1042 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1043 } else if (pbpctl_dev->bp_540) {
1044 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
1045 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1046
1047 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1048 BP540_MDIO_DIR) &
1049 ~(BP540_MDIO_DATA |
1050 BP540_MCLK_DATA)));
1051 } else if (pbpctl_dev->bp_10gb) {
1052 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1053
1054 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1055 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1056 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1057 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1058#if 0
1059
1060 /*BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, (ctrl_ext | BP10GB_MCLK_DIR | BP10GB_MDIO_DIR|
1061 BP10GB_MCLK_CLR|BP10GB_MDIO_CLR));
1062 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1063 printk("1reg=%x\n", ctrl_ext); */
1064
1065 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, ((ctrl_ext |
1066 BP10GB_MCLK_SET |
1067 BP10GB_MDIO_CLR))
1068 & ~(BP10GB_MCLK_CLR | BP10GB_MDIO_SET |
1069 BP10GB_MCLK_DIR | BP10GB_MDIO_DIR));
1070
1071 /* bnx2x_set_spio(pbpctl_dev, 5, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1072 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1073 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_INPUT_HI_Z); */
1074
1075 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1076
687bcca0 1077 printk("2reg=%x\n", ctrl_ext);
7040e556
D		 1078
1079#ifdef BP_SYNC_FLAG
1080 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1081#else
1082 atomic_set(&pbpctl_dev->wdt_busy, 0);
1083#endif
1084
1085 return 0;
1086
1087#endif
1088
1089 } else if (!pbpctl_dev->bp_10g) {
1090
1091 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1092
1093 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1094 BPCTLI_CTRL_EXT_MCLK_DIR
1095 |
1096 BPCTLI_CTRL_EXT_MDIO_DIR)
1097 &
1098 ~
1099 (BPCTLI_CTRL_EXT_MDIO_DATA
1100 |
1101 BPCTLI_CTRL_EXT_MCLK_DATA)));
1102 } else {
1103
7040e556
D		 1104 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1105 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1106 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1107 (ctrl_ext &
1108 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556
D		 1109
1110 }
1111
1112 usec_delay(CMND_INTERVAL);
1113
1114 /*send sync cmd */
1115 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
1116 /*send rd cmd */
1117 write_pulse(pbpctl_dev, ctrl_ext, RD_CMD_VAL, RD_CMD_LEN);
1118 /*send addr */
1119 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
1120 /*read data */
1121 /* zero */
1122 if (pbpctl_dev->bp_10g9) {
1123 /* DATA 0 CLK 1 */
1124 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
1125 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1126 (ctrl_ext | BP10G_MDIO_DATA_OUT9));
1127 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1128 (ctrl | BP10G_MCLK_DATA_OUT9 |
1129 BP10G_MCLK_DIR_OUT9));
1130
1131 } else if (pbpctl_dev->bp_fiber5) {
1132 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1133 BPCTLI_CTRL_EXT_MCLK_DIR5
1134 |
1135 BPCTLI_CTRL_EXT_MCLK_DATA5)
1136 &
1137 ~
1138 (BPCTLI_CTRL_EXT_MDIO_DIR5
1139 |
1140 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1141
1142 } else if (pbpctl_dev->bp_i80) {
1143 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
1144 (ctrl_ext &
1145 ~(BPCTLI_CTRL_EXT_MDIO_DATA80 |
1146 BPCTLI_CTRL_EXT_MDIO_DIR80)));
1147 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1148 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1149 BPCTLI_CTRL_EXT_MCLK_DATA80));
1150
1151 } else if (pbpctl_dev->bp_540) {
1152 BP10G_WRITE_REG(pbpctl_dev, ESDP,
1153 (((ctrl | BP540_MDIO_DIR | BP540_MCLK_DIR |
1154 BP540_MCLK_DATA) & ~BP540_MDIO_DATA)));
1155
1156 } else if (pbpctl_dev->bp_10gb) {
1157
1158 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1159 (ctrl_ext | BP10GB_MDIO_DIR | BP10GB_MCLK_SET)
1160 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_SET |
1161 BP10GB_MDIO_CLR | BP10GB_MCLK_CLR));
1162
1163 } else if (!pbpctl_dev->bp_10g)
1164 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1165 BPCTLI_CTRL_EXT_MCLK_DIR
1166 |
1167 BPCTLI_CTRL_EXT_MCLK_DATA)
1168 &
1169 ~
1170 (BPCTLI_CTRL_EXT_MDIO_DIR
1171 |
1172 BPCTLI_CTRL_EXT_MDIO_DATA)));
1173 else {
1174
7040e556
D		 1175 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1176 (ctrl_ext | BP10G_MCLK_DATA_OUT |
1177 BP10G_MDIO_DATA_OUT));
1178
7040e556
D		 1179
1180 }
1181 usec_delay(PULSE_TIME);
1182
1183 ctrl_value = read_pulse(pbpctl_dev, ctrl_ext, RD_DATA_LEN);
1184
1185 if (pbpctl_dev->bp_10g9) {
1186 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1187 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1188
1189 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1190 /* DATA 0 CLK 0 */
1191 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1192 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1193 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1194 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1195 ~(BP10G_MCLK_DATA_OUT9)));
1196
1197 } else if (pbpctl_dev->bp_fiber5) {
1198 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1199 BPCTLI_CTRL_EXT_MCLK_DIR5
1200 |
1201 BPCTLI_CTRL_EXT_MDIO_DIR5)
1202 &
1203 ~
1204 (BPCTLI_CTRL_EXT_MDIO_DATA5
1205 |
1206 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1207 } else if (pbpctl_dev->bp_i80) {
1208 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1209 BPCTLI_CTRL_EXT_MDIO_DIR80)
1210 &
1211 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1212 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1213 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1214 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1215
1216 } else if (pbpctl_dev->bp_540) {
1217 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1218 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1219 BP540_MDIO_DIR) &
1220 ~(BP540_MDIO_DATA |
1221 BP540_MCLK_DATA)));
1222
1223 } else if (pbpctl_dev->bp_10gb) {
1224 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1225 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1226 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1227 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1228 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1229
1230 } else if (!pbpctl_dev->bp_10g) {
1231 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1232 BPCTLI_CTRL_EXT_MCLK_DIR
1233 |
1234 BPCTLI_CTRL_EXT_MDIO_DIR)
1235 &
1236 ~
1237 (BPCTLI_CTRL_EXT_MDIO_DATA
1238 |
1239 BPCTLI_CTRL_EXT_MCLK_DATA)));
1240 } else {
1241
7040e556
D		 1242 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1243 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1244 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1245 (ctrl_ext &
1246 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556
D		 1247
1248 }
1249
1250 usec_delay(CMND_INTERVAL * 4);
1251#ifdef BP_SYNC_FLAG
1252 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1253#else
1254 atomic_set(&pbpctl_dev->wdt_busy, 0);
1255#endif
1256
1257 return ctrl_value;
1258}
1259
01448bbb 1260static int wdt_pulse(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1261{
1262 uint32_t ctrl_ext = 0, ctrl = 0;
1263 bpctl_dev_t *pbpctl_dev_c = NULL;
1264
1265#ifdef BP_SYNC_FLAG
1266 unsigned long flags;
1267
1268 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1269#else
1270
1271 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1272 return -1;
1273#endif
1274 if (pbpctl_dev->bp_10g9) {
1275 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
1276 return -1;
1277 }
1278
1279 if (pbpctl_dev->bp_10g9) {
1280 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1281 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1282
1283 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1284 /* DATA 0 CLK 0 */
1285 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1286 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1287 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1288 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1289 ~(BP10G_MCLK_DATA_OUT9)));
1290
1291 } else if (pbpctl_dev->bp_fiber5) {
1292 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1293 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1294 BPCTLI_CTRL_EXT_MCLK_DIR5
1295 |
1296 BPCTLI_CTRL_EXT_MDIO_DIR5)
1297 &
1298 ~
1299 (BPCTLI_CTRL_EXT_MDIO_DATA5
1300 |
1301 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1302 } else if (pbpctl_dev->bp_i80) {
1303 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1304 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1305 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1306 BPCTLI_CTRL_EXT_MDIO_DIR80)
1307 &
1308 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1309 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1310 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1311 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1312 } else if (pbpctl_dev->bp_540) {
1313 ctrl_ext = ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1314 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1315 BP540_MDIO_DIR) &
1316 ~(BP540_MDIO_DATA |
1317 BP540_MCLK_DATA)));
1318 } else if (pbpctl_dev->bp_10gb) {
1319 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1320 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1321 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1322 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1323 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1324
1325 } else if (!pbpctl_dev->bp_10g) {
1326
1327 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1328 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1329 BPCTLI_CTRL_EXT_MCLK_DIR
1330 |
1331 BPCTLI_CTRL_EXT_MDIO_DIR)
1332 &
1333 ~
1334 (BPCTLI_CTRL_EXT_MDIO_DATA
1335 |
1336 BPCTLI_CTRL_EXT_MCLK_DATA)));
1337 } else {
1338
7040e556
D		 1339 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1340 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1341 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1342 (ctrl_ext &
1343 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556
D		 1344
1345 }
1346 if (pbpctl_dev->bp_10g9) {
1347 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
1348 /* DATA 0 CLK 1 */
1349 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1350 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1351 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1352 (ctrl | BP10G_MCLK_DATA_OUT9 |
1353 BP10G_MCLK_DIR_OUT9));
1354
1355 } else if (pbpctl_dev->bp_fiber5) {
1356 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1357 BPCTLI_CTRL_EXT_MCLK_DIR5
1358 |
1359 BPCTLI_CTRL_EXT_MDIO_DIR5
1360 |
1361 BPCTLI_CTRL_EXT_MCLK_DATA5)
1362 &
1363 ~
1364 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
1365 } else if (pbpctl_dev->bp_i80) {
1366 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1367 BPCTLI_CTRL_EXT_MDIO_DIR80)
1368 &
1369 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1370 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1371 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1372 BPCTLI_CTRL_EXT_MCLK_DATA80));
1373
1374 } else if (pbpctl_dev->bp_540) {
1375 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
1376 BP540_MDIO_DIR |
1377 BP540_MCLK_DIR |
1378 BP540_MCLK_DATA) &
1379 ~BP540_MDIO_DATA));
1380
1381 } else if (pbpctl_dev->bp_10gb) {
1382 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1383
1384 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1385 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_SET)
1386 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1387 BP10GB_MDIO_SET | BP10GB_MCLK_CLR));
1388
1389 } else if (!pbpctl_dev->bp_10g)
1390 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1391 BPCTLI_CTRL_EXT_MCLK_DIR
1392 |
1393 BPCTLI_CTRL_EXT_MDIO_DIR
1394 |
1395 BPCTLI_CTRL_EXT_MCLK_DATA)
1396 &
1397 ~
1398 (BPCTLI_CTRL_EXT_MDIO_DATA)));
1399 else {
1400
7040e556
D		 1401 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1402 ((ctrl_ext | BP10G_MCLK_DATA_OUT) &
1403 ~BP10G_MDIO_DATA_OUT));
7040e556
D		 1404
1405 }
1406
1407 usec_delay(WDT_INTERVAL);
1408 if (pbpctl_dev->bp_10g9) {
1409 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1410 /* DATA 0 CLK 0 */
1411 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1412 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1413 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1414 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1415 ~(BP10G_MCLK_DATA_OUT9)));
1416
1417 } else if (pbpctl_dev->bp_fiber5) {
1418 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1419 BPCTLI_CTRL_EXT_MCLK_DIR5
1420 |
1421 BPCTLI_CTRL_EXT_MDIO_DIR5)
1422 &
1423 ~
1424 (BPCTLI_CTRL_EXT_MCLK_DATA5
1425 |
1426 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1427 } else if (pbpctl_dev->bp_i80) {
1428 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1429 BPCTLI_CTRL_EXT_MDIO_DIR80)
1430 &
1431 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1432 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1433 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1434 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1435
1436 } else if (pbpctl_dev->bp_540) {
1437 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1438 BP540_MDIO_DIR) &
1439 ~(BP540_MDIO_DATA |
1440 BP540_MCLK_DATA)));
1441
1442 } else if (pbpctl_dev->bp_10gb) {
1443 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1444 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1445 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1446 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1447 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1448
1449 } else if (!pbpctl_dev->bp_10g)
1450 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1451 BPCTLI_CTRL_EXT_MCLK_DIR
1452 |
1453 BPCTLI_CTRL_EXT_MDIO_DIR)
1454 &
1455 ~
1456 (BPCTLI_CTRL_EXT_MCLK_DATA
1457 |
1458 BPCTLI_CTRL_EXT_MDIO_DATA)));
1459 else {
1460
7040e556
D		 1461 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1462 (ctrl_ext &
1463 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556
D		 1464 }
1465 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) /*&&
1466 (pbpctl_dev->bp_ext_ver<PXG4BPFI_VER) */ )
1467 pbpctl_dev->bypass_wdt_on_time = jiffies;
1468#ifdef BP_SYNC_FLAG
1469 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1470#endif
1471 usec_delay(CMND_INTERVAL * 4);
1472 return 0;
1473}
1474
01448bbb 1475static void data_pulse(bpctl_dev_t *pbpctl_dev, unsigned char value)
7040e556
D		 1476{
1477
1478 uint32_t ctrl_ext = 0;
1479#ifdef BP_SYNC_FLAG
1480 unsigned long flags;
1481#endif
1482 wdt_time_left(pbpctl_dev);
1483#ifdef BP_SYNC_FLAG
1484 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1485#else
1486 atomic_set(&pbpctl_dev->wdt_busy, 1);
1487#endif
1488
1489 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1490 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1491 BPCTLI_CTRL_EXT_SDP6_DIR |
1492 BPCTLI_CTRL_EXT_SDP7_DIR) &
1493 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1494 BPCTLI_CTRL_EXT_SDP7_DATA)));
1495
1496 usec_delay(INIT_CMND_INTERVAL);
1497 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1498 BPCTLI_CTRL_EXT_SDP6_DIR |
1499 BPCTLI_CTRL_EXT_SDP7_DIR |
1500 BPCTLI_CTRL_EXT_SDP6_DATA) &
1501 ~
1502 (BPCTLI_CTRL_EXT_SDP7_DATA)));
1503 usec_delay(INIT_CMND_INTERVAL);
1504
1505 while (value) {
1506 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1507 BPCTLI_CTRL_EXT_SDP6_DIR |
1508 BPCTLI_CTRL_EXT_SDP7_DIR |
1509 BPCTLI_CTRL_EXT_SDP6_DATA |
1510 BPCTLI_CTRL_EXT_SDP7_DATA);
1511 usec_delay(PULSE_INTERVAL);
1512 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1513 BPCTLI_CTRL_EXT_SDP6_DIR
1514 |
1515 BPCTLI_CTRL_EXT_SDP7_DIR
1516 |
1517 BPCTLI_CTRL_EXT_SDP6_DATA)
1518 &
1519 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1520 usec_delay(PULSE_INTERVAL);
1521 value--;
1522
1523 }
1524 usec_delay(INIT_CMND_INTERVAL - PULSE_INTERVAL);
1525 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1526 BPCTLI_CTRL_EXT_SDP6_DIR |
1527 BPCTLI_CTRL_EXT_SDP7_DIR) &
1528 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1529 BPCTLI_CTRL_EXT_SDP7_DATA)));
1530 usec_delay(WDT_TIME_CNT);
1531 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1532 pbpctl_dev->bypass_wdt_on_time = jiffies;
1533#ifdef BP_SYNC_FLAG
1534 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1535#else
1536 atomic_set(&pbpctl_dev->wdt_busy, 0);
1537#endif
1538
1539}
1540
01448bbb 1541static int send_wdt_pulse(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1542{
1543 uint32_t ctrl_ext = 0;
1544
1545#ifdef BP_SYNC_FLAG
1546 unsigned long flags;
1547
1548 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1549#else
1550
1551 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1552 return -1;
1553#endif
1554 wdt_time_left(pbpctl_dev);
1555 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1556
1557 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1558 BPCTLI_CTRL_EXT_SDP7_DIR |
1559 BPCTLI_CTRL_EXT_SDP7_DATA);
1560 usec_delay(PULSE_INTERVAL);
1561 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1562 BPCTLI_CTRL_EXT_SDP7_DIR) &
1563 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1564
1565 usec_delay(PULSE_INTERVAL);
1566 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1567 pbpctl_dev->bypass_wdt_on_time = jiffies;
1568#ifdef BP_SYNC_FLAG
1569 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1570#endif
1571
1572 return 0;
1573}
1574
01448bbb 1575void send_bypass_clear_pulse(bpctl_dev_t *pbpctl_dev, unsigned int value)
7040e556
D		 1576{
1577 uint32_t ctrl_ext = 0;
1578
1579 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1580 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1581 BPCTLI_CTRL_EXT_SDP6_DIR) &
1582 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1583
1584 usec_delay(PULSE_INTERVAL);
1585 while (value) {
1586 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1587 BPCTLI_CTRL_EXT_SDP6_DIR |
1588 BPCTLI_CTRL_EXT_SDP6_DATA);
1589 usec_delay(PULSE_INTERVAL);
1590 value--;
1591 }
1592 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1593 BPCTLI_CTRL_EXT_SDP6_DIR) &
1594 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1595 usec_delay(PULSE_INTERVAL);
1596}
1597
1598/* #endif OLD_FW */
1599#ifdef BYPASS_DEBUG
1600
01448bbb 1601int pulse_set_fn(bpctl_dev_t *pbpctl_dev, unsigned int counter)
7040e556
D		 1602{
1603 uint32_t ctrl_ext = 0;
1604
1605 if (!pbpctl_dev)
1606 return -1;
1607
1608 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1609 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1610
1611 pbpctl_dev->bypass_wdt_status = 0;
1612 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1613 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1614 } else {
1615 wdt_time_left(pbpctl_dev);
1616 if (pbpctl_dev->wdt_status == WDT_STATUS_EN) {
1617 pbpctl_dev->wdt_status = 0;
1618 data_pulse(pbpctl_dev, counter);
1619 pbpctl_dev->wdt_status = WDT_STATUS_EN;
1620 pbpctl_dev->bypass_wdt_on_time = jiffies;
1621
1622 } else
1623 data_pulse(pbpctl_dev, counter);
1624 }
1625
1626 return 0;
1627}
1628
01448bbb 1629int zero_set_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1630{
1631 uint32_t ctrl_ext = 0, ctrl_value = 0;
1632 if (!pbpctl_dev)
1633 return -1;
1634
1635 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1636 printk("zero_set");
1637
1638 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1639
1640 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1641 BPCTLI_CTRL_EXT_MCLK_DIR)
1642 &
1643 ~
1644 (BPCTLI_CTRL_EXT_MCLK_DATA
1645 |
1646 BPCTLI_CTRL_EXT_MDIO_DIR
1647 |
1648 BPCTLI_CTRL_EXT_MDIO_DATA)));
1649
1650 }
1651 return ctrl_value;
1652}
1653
1bd5374d 1654int pulse_get2_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1655{
1656 uint32_t ctrl_ext = 0, ctrl_value = 0;
1657 if (!pbpctl_dev)
1658 return -1;
1659
1660 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1661 printk("pulse_get_fn\n");
1662 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1663 ctrl_value = read_pulse_2(pbpctl_dev, ctrl_ext);
1664 printk("read:%d\n", ctrl_value);
1665 }
1666 return ctrl_value;
1667}
1668
1bd5374d 1669int pulse_get1_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1670{
1671 uint32_t ctrl_ext = 0, ctrl_value = 0;
1672 if (!pbpctl_dev)
1673 return -1;
1674
1675 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1676
1677 printk("pulse_get_fn\n");
1678
1679 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1680 ctrl_value = read_pulse_1(pbpctl_dev, ctrl_ext);
1681 printk("read:%d\n", ctrl_value);
1682 }
1683 return ctrl_value;
1684}
1685
1bd5374d 1686int gpio6_set_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1687{
1688 uint32_t ctrl_ext = 0;
1689
1690 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1691 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1692 BPCTLI_CTRL_EXT_SDP6_DIR |
1693 BPCTLI_CTRL_EXT_SDP6_DATA);
1694 return 0;
1695}
1696
1bd5374d 1697int gpio7_set_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1698{
1699 uint32_t ctrl_ext = 0;
1700
1701 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1702 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1703 BPCTLI_CTRL_EXT_SDP7_DIR |
1704 BPCTLI_CTRL_EXT_SDP7_DATA);
1705 return 0;
1706}
1707
1bd5374d 1708int gpio7_clear_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1709{
1710 uint32_t ctrl_ext = 0;
1711
1712 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1713 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1714 BPCTLI_CTRL_EXT_SDP7_DIR) &
1715 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1716 return 0;
1717}
1718
1bd5374d 1719int gpio6_clear_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1720{
1721 uint32_t ctrl_ext = 0;
1722
1723 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1724 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1725 BPCTLI_CTRL_EXT_SDP6_DIR) &
1726 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1727 return 0;
1728}
1729#endif /*BYPASS_DEBUG */
1730
fb8004d3 1731static bpctl_dev_t *lookup_port(bpctl_dev_t *dev)
7040e556 1732{
fb8004d3
AV		 1733 bpctl_dev_t *p;
1734 int n;
1735 for (n = 0, p = bpctl_dev_arr; n < device_num && p->pdev; n++) {
1736 if (p->bus == dev->bus
1737 && p->slot == dev->slot
1738 && p->func == (dev->func ^ 1))
1739 return p;
1740 }
1741 return NULL;
1742}
7040e556 1743
fb8004d3
AV		 1744static bpctl_dev_t *get_status_port_fn(bpctl_dev_t *pbpctl_dev)
1745{
1746 if (pbpctl_dev) {
1747 if (pbpctl_dev->func == 0 || pbpctl_dev->func == 2)
1748 return lookup_port(pbpctl_dev);
7040e556
D		 1749 }
1750 return NULL;
1751}
1752
1bd5374d 1753static bpctl_dev_t *get_master_port_fn(bpctl_dev_t *pbpctl_dev)
7040e556 1754{
fb8004d3
AV		 1755 if (pbpctl_dev) {
1756 if (pbpctl_dev->func == 1 || pbpctl_dev->func == 3)
1757 return lookup_port(pbpctl_dev);
7040e556
D		 1758 }
1759 return NULL;
1760}
1761
1762/**************************************/
1763/**************INTEL API***************/
1764/**************************************/
1765
1bd5374d 1766static void write_data_port_int(bpctl_dev_t *pbpctl_dev,
7040e556
D		 1767 unsigned char ctrl_value)
1768{
1769 uint32_t value;
1770
1771 value = BPCTL_READ_REG(pbpctl_dev, CTRL);
1772/* Make SDP0 Pin Directonality to Output */
1773 value |= BPCTLI_CTRL_SDP0_DIR;
1774 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1775
1776 value &= ~BPCTLI_CTRL_SDP0_DATA;
1777 value |= ((ctrl_value & 0x1) << BPCTLI_CTRL_SDP0_SHIFT);
1778 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1779
1780 value = (BPCTL_READ_REG(pbpctl_dev, CTRL_EXT));
1781/* Make SDP2 Pin Directonality to Output */
1782 value |= BPCTLI_CTRL_EXT_SDP6_DIR;
1783 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1784
1785 value &= ~BPCTLI_CTRL_EXT_SDP6_DATA;
1786 value |= (((ctrl_value & 0x2) >> 1) << BPCTLI_CTRL_EXT_SDP6_SHIFT);
1787 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1788
1789}
1790
1bd5374d 1791static int write_data_int(bpctl_dev_t *pbpctl_dev, unsigned char value)
7040e556
D		 1792{
1793 bpctl_dev_t *pbpctl_dev_b = NULL;
1794
1795 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
1796 return -1;
1797 atomic_set(&pbpctl_dev->wdt_busy, 1);
1798 write_data_port_int(pbpctl_dev, value & 0x3);
1799 write_data_port_int(pbpctl_dev_b, ((value & 0xc) >> 2));
1800 atomic_set(&pbpctl_dev->wdt_busy, 0);
1801
1802 return 0;
1803}
1804
1bd5374d 1805static int wdt_pulse_int(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1806{
1807
1808 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1809 return -1;
1810
1811 if ((write_data_int(pbpctl_dev, RESET_WDT_INT)) < 0)
1812 return -1;
1813 msec_delay_bp(CMND_INTERVAL_INT);
1814 if ((write_data_int(pbpctl_dev, CMND_OFF_INT)) < 0)
1815 return -1;
1816 msec_delay_bp(CMND_INTERVAL_INT);
1817
1818 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1819 pbpctl_dev->bypass_wdt_on_time = jiffies;
1820
1821 return 0;
1822}
1823
1824/*************************************/
1825/************* COMMANDS **************/
1826/*************************************/
1827
1828/* CMND_ON 0x4 (100)*/
1bd5374d 1829int cmnd_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1830{
1831 int ret = BP_NOT_CAP;
1832
1833 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1834 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
1835 return 0;
1836 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1837 write_data(pbpctl_dev, CMND_ON);
1838 else
1839 data_pulse(pbpctl_dev, CMND_ON);
1840 ret = 0;
1841 }
1842 return ret;
1843}
1844
1845/* CMND_OFF 0x2 (10)*/
1bd5374d 1846int cmnd_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1847{
1848 int ret = BP_NOT_CAP;
1849
1850 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1851 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1852 write_data_int(pbpctl_dev, CMND_OFF_INT);
1853 msec_delay_bp(CMND_INTERVAL_INT);
1854 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1855 write_data(pbpctl_dev, CMND_OFF);
1856 else
1857 data_pulse(pbpctl_dev, CMND_OFF);
1858 ret = 0;
1859 };
1860 return ret;
1861}
1862
1863/* BYPASS_ON (0xa)*/
1bd5374d 1864int bypass_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1865{
1866 int ret = BP_NOT_CAP;
1867
1868 if (pbpctl_dev->bp_caps & BP_CAP) {
1869 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1870 write_data_int(pbpctl_dev, BYPASS_ON_INT);
1871 msec_delay_bp(BYPASS_DELAY_INT);
1872 pbpctl_dev->bp_status_un = 0;
1873 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1874 write_data(pbpctl_dev, BYPASS_ON);
1875 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1876 msec_delay_bp(LATCH_DELAY);
1877 } else
1878 data_pulse(pbpctl_dev, BYPASS_ON);
1879 ret = 0;
1880 };
1881 return ret;
1882}
1883
1884/* BYPASS_OFF (0x8 111)*/
1bd5374d 1885int bypass_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1886{
1887 int ret = BP_NOT_CAP;
1888
1889 if (pbpctl_dev->bp_caps & BP_CAP) {
1890 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1891 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
1892 msec_delay_bp(BYPASS_DELAY_INT);
1893 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
1894 msec_delay_bp(BYPASS_DELAY_INT);
1895 pbpctl_dev->bp_status_un = 0;
1896 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1897 write_data(pbpctl_dev, BYPASS_OFF);
1898 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1899 msec_delay_bp(LATCH_DELAY);
1900 } else
1901 data_pulse(pbpctl_dev, BYPASS_OFF);
1902 ret = 0;
1903 }
1904 return ret;
1905}
1906
1907/* TAP_OFF (0x9)*/
1bd5374d 1908int tap_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1909{
1910 int ret = BP_NOT_CAP;
1911 if ((pbpctl_dev->bp_caps & TAP_CAP)
1912 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1913 write_data(pbpctl_dev, TAP_OFF);
1914 msec_delay_bp(LATCH_DELAY);
1915 ret = 0;
1916 };
1917 return ret;
1918}
1919
1920/* TAP_ON (0xb)*/
1bd5374d 1921int tap_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1922{
1923 int ret = BP_NOT_CAP;
1924 if ((pbpctl_dev->bp_caps & TAP_CAP)
1925 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1926 write_data(pbpctl_dev, TAP_ON);
1927 msec_delay_bp(LATCH_DELAY);
1928 ret = 0;
1929 };
1930 return ret;
1931}
1932
1933/* DISC_OFF (0x9)*/
1bd5374d 1934int disc_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1935{
1936 int ret = 0;
1937 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1938 write_data(pbpctl_dev, DISC_OFF);
1939 msec_delay_bp(LATCH_DELAY);
1940 } else
1941 ret = BP_NOT_CAP;
1942 return ret;
1943}
1944
1945/* DISC_ON (0xb)*/
1bd5374d 1946int disc_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1947{
1948 int ret = 0;
1949 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1950 write_data(pbpctl_dev, /*DISC_ON */ 0x85);
1951 msec_delay_bp(LATCH_DELAY);
1952 } else
1953 ret = BP_NOT_CAP;
1954 return ret;
1955}
1956
1957/* DISC_PORT_ON */
1bd5374d 1958int disc_port_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1959{
1960 int ret = 0;
1961 bpctl_dev_t *pbpctl_dev_m;
1962
1963 if ((is_bypass_fn(pbpctl_dev)) == 1)
1964 pbpctl_dev_m = pbpctl_dev;
1965 else
1966 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1967 if (pbpctl_dev_m == NULL)
1968 return BP_NOT_CAP;
1969
1970 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
1971 if (is_bypass_fn(pbpctl_dev) == 1) {
1972
1973 write_data(pbpctl_dev_m, TX_DISA);
1974 } else {
1975
1976 write_data(pbpctl_dev_m, TX_DISB);
1977 }
1978
1979 msec_delay_bp(LATCH_DELAY);
1980
1981 }
1982 return ret;
1983}
1984
1985/* DISC_PORT_OFF */
1bd5374d 1986int disc_port_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1987{
1988 int ret = 0;
1989 bpctl_dev_t *pbpctl_dev_m;
1990
1991 if ((is_bypass_fn(pbpctl_dev)) == 1)
1992 pbpctl_dev_m = pbpctl_dev;
1993 else
1994 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1995 if (pbpctl_dev_m == NULL)
1996 return BP_NOT_CAP;
1997
1998 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
1999 if (is_bypass_fn(pbpctl_dev) == 1)
2000 write_data(pbpctl_dev_m, TX_ENA);
2001 else
2002 write_data(pbpctl_dev_m, TX_ENB);
2003
2004 msec_delay_bp(LATCH_DELAY);
2005
2006 }
2007 return ret;
2008}
2009
2010/*TWO_PORT_LINK_HW_EN (0xe)*/
1bd5374d 2011int tpl_hw_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2012{
2013 int ret = 0, ctrl = 0;
2014 bpctl_dev_t *pbpctl_dev_b = NULL;
2015
2016 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
2017 return BP_NOT_CAP;
2018
2019 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
2020 cmnd_on(pbpctl_dev);
2021 write_data(pbpctl_dev, TPL2_ON);
2022 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2023 cmnd_off(pbpctl_dev);
2024 return ret;
2025 }
2026
2027 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2028 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2029 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2030 ((ctrl | BPCTLI_CTRL_SWDPIO0) &
2031 ~BPCTLI_CTRL_SWDPIN0));
2032 } else
2033 ret = BP_NOT_CAP;
2034 return ret;
2035}
2036
2037/*TWO_PORT_LINK_HW_DIS (0xc)*/
1bd5374d 2038int tpl_hw_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2039{
2040 int ret = 0, ctrl = 0;
2041 bpctl_dev_t *pbpctl_dev_b = NULL;
2042
2043 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
2044 return BP_NOT_CAP;
2045 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
2046 cmnd_on(pbpctl_dev);
2047 write_data(pbpctl_dev, TPL2_OFF);
2048 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2049 cmnd_off(pbpctl_dev);
2050 return ret;
2051 }
2052 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2053 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2054 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2055 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2056 BPCTLI_CTRL_SWDPIN0));
2057 } else
2058 ret = BP_NOT_CAP;
2059 return ret;
2060}
2061
2062/* WDT_OFF (0x6 110)*/
1bd5374d 2063int wdt_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2064{
2065 int ret = BP_NOT_CAP;
2066
2067 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2068 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2069 bypass_off(pbpctl_dev);
2070 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2071 write_data(pbpctl_dev, WDT_OFF);
2072 else
2073 data_pulse(pbpctl_dev, WDT_OFF);
2074 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
2075 ret = 0;
2076 };
2077 return ret;
2078}
2079
2080/* WDT_ON (0x10)*/
2081
2082/***Global***/
2083static unsigned int
2084 wdt_val_array[] = { 1000, 1500, 2000, 3000, 4000, 8000, 16000, 32000, 0 };
2085
1bd5374d 2086int wdt_on(bpctl_dev_t *pbpctl_dev, unsigned int timeout)
7040e556
D		 2087{
2088
2089 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2090 unsigned int pulse = 0, temp_value = 0, temp_cnt = 0;
2091 pbpctl_dev->wdt_status = 0;
2092
2093 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2094 for (; wdt_val_array[temp_cnt]; temp_cnt++)
2095 if (timeout <= wdt_val_array[temp_cnt])
2096 break;
2097
2098 if (!wdt_val_array[temp_cnt])
2099 temp_cnt--;
2100
2101 timeout = wdt_val_array[temp_cnt];
2102 temp_cnt += 0x7;
2103
2104 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2105 msec_delay_bp(BYPASS_DELAY_INT);
2106 pbpctl_dev->bp_status_un = 0;
2107 write_data_int(pbpctl_dev, temp_cnt);
2108 pbpctl_dev->bypass_wdt_on_time = jiffies;
2109 msec_delay_bp(CMND_INTERVAL_INT);
2110 pbpctl_dev->bypass_timer_interval = timeout;
2111 } else {
2112 timeout =
2113 (timeout <
2114 TIMEOUT_UNIT ? TIMEOUT_UNIT : (timeout >
2115 WDT_TIMEOUT_MAX ?
2116 WDT_TIMEOUT_MAX :
2117 timeout));
2118 temp_value = timeout / 100;
2119 while ((temp_value >>= 1))
2120 temp_cnt++;
2121 if (timeout > ((1 << temp_cnt) * 100))
2122 temp_cnt++;
2123 pbpctl_dev->bypass_wdt_on_time = jiffies;
2124 pulse = (WDT_ON | temp_cnt);
2125 if (pbpctl_dev->bp_ext_ver == OLD_IF_VER)
2126 data_pulse(pbpctl_dev, pulse);
2127 else
2128 write_data(pbpctl_dev, pulse);
2129 pbpctl_dev->bypass_timer_interval =
2130 (1 << temp_cnt) * 100;
2131 }
2132 pbpctl_dev->wdt_status = WDT_STATUS_EN;
2133 return 0;
2134 }
2135 return BP_NOT_CAP;
2136}
2137
1bd5374d 2138void bp75_put_hw_semaphore_generic(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2139{
2140 u32 swsm;
2141
2142 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2143
2144 swsm &= ~(BPCTLI_SWSM_SMBI | BPCTLI_SWSM_SWESMBI);
2145
2146 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm);
2147}
2148
1bd5374d 2149s32 bp75_get_hw_semaphore_generic(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2150{
2151 u32 swsm;
2152 s32 ret_val = 0;
2153 s32 timeout = 8192 + 1;
2154 s32 i = 0;
2155
2156 /* Get the SW semaphore */
2157 while (i < timeout) {
2158 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2159 if (!(swsm & BPCTLI_SWSM_SMBI))
2160 break;
2161
2162 usec_delay(50);
2163 i++;
2164 }
2165
2166 if (i == timeout) {
2167 printk
2168 ("bpctl_mod: Driver can't access device - SMBI bit is set.\n");
2169 ret_val = -1;
2170 goto out;
2171 }
2172
2173 /* Get the FW semaphore. */
2174 for (i = 0; i < timeout; i++) {
2175 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2176 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm | BPCTLI_SWSM_SWESMBI);
2177
2178 /* Semaphore acquired if bit latched */
2179 if (BPCTL_READ_REG(pbpctl_dev, SWSM) & BPCTLI_SWSM_SWESMBI)
2180 break;
2181
2182 usec_delay(50);
2183 }
2184
2185 if (i == timeout) {
2186 /* Release semaphores */
2187 bp75_put_hw_semaphore_generic(pbpctl_dev);
2188 printk("bpctl_mod: Driver can't access the NVM\n");
2189 ret_val = -1;
2190 goto out;
2191 }
2192
2193 out:
2194 return ret_val;
2195}
2196
1bd5374d 2197static void bp75_release_phy(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2198{
2199 u16 mask = BPCTLI_SWFW_PHY0_SM;
2200 u32 swfw_sync;
2201
2202 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2203 mask = BPCTLI_SWFW_PHY1_SM;
2204
2205 while (bp75_get_hw_semaphore_generic(pbpctl_dev) != 0) ;
2206 /* Empty */
2207
2208 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2209 swfw_sync &= ~mask;
2210 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2211
2212 bp75_put_hw_semaphore_generic(pbpctl_dev);
2213}
2214
1bd5374d 2215static s32 bp75_acquire_phy(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2216{
2217 u16 mask = BPCTLI_SWFW_PHY0_SM;
2218 u32 swfw_sync;
2219 u32 swmask;
2220 u32 fwmask;
2221 s32 ret_val = 0;
2222 s32 i = 0, timeout = 200;
2223
2224 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2225 mask = BPCTLI_SWFW_PHY1_SM;
2226
2227 swmask = mask;
2228 fwmask = mask << 16;
2229
2230 while (i < timeout) {
2231 if (bp75_get_hw_semaphore_generic(pbpctl_dev)) {
2232 ret_val = -1;
2233 goto out;
2234 }
2235
2236 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2237 if (!(swfw_sync & (fwmask | swmask)))
2238 break;
2239
2240 bp75_put_hw_semaphore_generic(pbpctl_dev);
2241 mdelay(5);
2242 i++;
2243 }
2244
2245 if (i == timeout) {
2246 printk
2247 ("bpctl_mod: Driver can't access resource, SW_FW_SYNC timeout.\n");
2248 ret_val = -1;
2249 goto out;
2250 }
2251
2252 swfw_sync |= swmask;
2253 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2254
2255 bp75_put_hw_semaphore_generic(pbpctl_dev);
2256
2257 out:
2258 return ret_val;
2259}
2260
1bd5374d 2261s32 bp75_read_phy_reg_mdic(bpctl_dev_t *pbpctl_dev, u32 offset, u16 *data)
7040e556
D		 2262{
2263 u32 i, mdic = 0;
2264 s32 ret_val = 0;
2265 u32 phy_addr = 1;
2266
2267 mdic = ((offset << BPCTLI_MDIC_REG_SHIFT) |
2268 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_READ));
2269
2270 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2271
2272 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2273 usec_delay(50);
2274 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2275 if (mdic & BPCTLI_MDIC_READY)
2276 break;
2277 }
2278 if (!(mdic & BPCTLI_MDIC_READY)) {
2279 printk("bpctl_mod: MDI Read did not complete\n");
2280 ret_val = -1;
2281 goto out;
2282 }
2283 if (mdic & BPCTLI_MDIC_ERROR) {
2284 printk("bpctl_mod: MDI Error\n");
2285 ret_val = -1;
2286 goto out;
2287 }
2288 *data = (u16) mdic;
2289
2290 out:
2291 return ret_val;
2292}
2293
1bd5374d 2294s32 bp75_write_phy_reg_mdic(bpctl_dev_t *pbpctl_dev, u32 offset, u16 data)
7040e556
D		 2295{
2296 u32 i, mdic = 0;
2297 s32 ret_val = 0;
2298 u32 phy_addr = 1;
2299
2300 mdic = (((u32) data) |
2301 (offset << BPCTLI_MDIC_REG_SHIFT) |
2302 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_WRITE));
2303
2304 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2305
2306 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2307 usec_delay(50);
2308 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2309 if (mdic & BPCTLI_MDIC_READY)
2310 break;
2311 }
2312 if (!(mdic & BPCTLI_MDIC_READY)) {
2313 printk("bpctl_mod: MDI Write did not complete\n");
2314 ret_val = -1;
2315 goto out;
2316 }
2317 if (mdic & BPCTLI_MDIC_ERROR) {
2318 printk("bpctl_mod: MDI Error\n");
2319 ret_val = -1;
2320 goto out;
2321 }
2322
2323 out:
2324 return ret_val;
2325}
2326
1bd5374d 2327static s32 bp75_read_phy_reg(bpctl_dev_t *pbpctl_dev, u32 offset, u16 *data)
7040e556
D		 2328{
2329 s32 ret_val = 0;
2330
2331 ret_val = bp75_acquire_phy(pbpctl_dev);
2332 if (ret_val)
2333 goto out;
2334
2335 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2336 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2337 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2338 (u16) offset);
2339 if (ret_val)
2340 goto release;
2341 }
2342
2343 ret_val =
2344 bp75_read_phy_reg_mdic(pbpctl_dev,
2345 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2346
2347 release:
2348 bp75_release_phy(pbpctl_dev);
2349 out:
2350 return ret_val;
2351}
2352
81908e8b 2353static s32 bp75_write_phy_reg(bpctl_dev_t *pbpctl_dev, u32 offset, u16 data)
7040e556
D		 2354{
2355 s32 ret_val = 0;
2356
2357 ret_val = bp75_acquire_phy(pbpctl_dev);
2358 if (ret_val)
2359 goto out;
2360
2361 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2362 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2363 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2364 (u16) offset);
2365 if (ret_val)
2366 goto release;
2367 }
2368
2369 ret_val =
2370 bp75_write_phy_reg_mdic(pbpctl_dev,
2371 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2372
2373 release:
2374 bp75_release_phy(pbpctl_dev);
2375
2376 out:
2377 return ret_val;
2378}
2379
2380/* SET_TX (non-Bypass command :)) */
81908e8b 2381static int set_tx(bpctl_dev_t *pbpctl_dev, int tx_state)
7040e556
D		 2382{
2383 int ret = 0, ctrl = 0;
2384 bpctl_dev_t *pbpctl_dev_m;
2385 if ((is_bypass_fn(pbpctl_dev)) == 1)
2386 pbpctl_dev_m = pbpctl_dev;
2387 else
2388 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2389 if (pbpctl_dev_m == NULL)
2390 return BP_NOT_CAP;
2391 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2392 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2393 if (!tx_state) {
2394 if (pbpctl_dev->bp_540) {
2395 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2396 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2397 (ctrl | BP10G_SDP1_DIR |
2398 BP10G_SDP1_DATA));
2399
2400 } else {
2401 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2402 (ctrl | BPCTLI_CTRL_SDP1_DIR
2403 | BPCTLI_CTRL_SWDPIN1));
2404 }
2405 } else {
2406 if (pbpctl_dev->bp_540) {
2407 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2408 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2409 ((ctrl | BP10G_SDP1_DIR) &
2410 ~BP10G_SDP1_DATA));
2411 } else {
2412 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2413 ((ctrl |
2414 BPCTLI_CTRL_SDP1_DIR) &
2415 ~BPCTLI_CTRL_SWDPIN1));
2416 }
2417 return ret;
2418
2419 }
2420 } else if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
2421 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
2422 if (tx_state) {
2423 uint16_t mii_reg;
2424 if (!
2425 (ret =
2426 bp75_read_phy_reg(pbpctl_dev,
2427 BPCTLI_PHY_CONTROL,
2428 &mii_reg))) {
2429 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN) {
2430 ret =
2431 bp75_write_phy_reg
2432 (pbpctl_dev,
2433 BPCTLI_PHY_CONTROL,
2434 mii_reg &
2435 ~BPCTLI_MII_CR_POWER_DOWN);
2436 }
2437 }
2438 } else {
2439 uint16_t mii_reg;
2440 if (!
2441 (ret =
2442 bp75_read_phy_reg(pbpctl_dev,
2443 BPCTLI_PHY_CONTROL,
2444 &mii_reg))) {
2445
2446 mii_reg |= BPCTLI_MII_CR_POWER_DOWN;
2447 ret =
2448 bp75_write_phy_reg(pbpctl_dev,
2449 BPCTLI_PHY_CONTROL,
2450 mii_reg);
2451 }
2452 }
2453
2454 }
2455 if (pbpctl_dev->bp_fiber5) {
2456 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
2457
2458 } else if (pbpctl_dev->bp_10gb)
2459 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
2460
2461 else if (!pbpctl_dev->bp_10g)
2462 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2463 else
7040e556
D		 2464 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2465
2466 if (!tx_state)
2467 if (pbpctl_dev->bp_10g9) {
2468 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2469 (ctrl | BP10G_SDP3_DATA |
2470 BP10G_SDP3_DIR));
2471
2472 } else if (pbpctl_dev->bp_fiber5) {
2473 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2474 (ctrl |
2475 BPCTLI_CTRL_EXT_SDP6_DIR |
2476 BPCTLI_CTRL_EXT_SDP6_DATA));
2477
2478 } else if (pbpctl_dev->bp_10gb) {
2479 if ((pbpctl_dev->func == 1)
2480 || (pbpctl_dev->func == 3))
2481 BP10GB_WRITE_REG(pbpctl_dev,
2482 MISC_REG_GPIO,
2483 (ctrl |
2484 BP10GB_GPIO0_SET_P1) &
2485 ~(BP10GB_GPIO0_CLR_P1 |
2486 BP10GB_GPIO0_OE_P1));
2487 else
2488 BP10GB_WRITE_REG(pbpctl_dev,
2489 MISC_REG_GPIO,
2490 (ctrl |
2491 BP10GB_GPIO0_OE_P0 |
2492 BP10GB_GPIO0_SET_P0));
2493
2494 } else if (pbpctl_dev->bp_i80) {
2495 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2496 (ctrl | BPCTLI_CTRL_SDP1_DIR
2497 | BPCTLI_CTRL_SWDPIN1));
2498
2499 } else if (pbpctl_dev->bp_540) {
2500 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2501 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2502 (ctrl | BP10G_SDP1_DIR |
2503 BP10G_SDP1_DATA));
2504
2505 }
2506
2507 else if (!pbpctl_dev->bp_10g)
2508 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2509 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2510 BPCTLI_CTRL_SWDPIN0));
2511
2512 else
7040e556
D		 2513 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2514 (ctrl | BP10G_SDP0_DATA |
2515 BP10G_SDP0_DIR));
2516
2517 else {
2518 if (pbpctl_dev->bp_10g9) {
2519 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2520 ((ctrl | BP10G_SDP3_DIR) &
2521 ~BP10G_SDP3_DATA));
2522
2523 } else if (pbpctl_dev->bp_fiber5) {
2524 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2525 ((ctrl |
2526 BPCTLI_CTRL_EXT_SDP6_DIR) &
2527 ~BPCTLI_CTRL_EXT_SDP6_DATA));
2528
2529 } else if (pbpctl_dev->bp_10gb) {
2530 if ((bpctl_dev_arr->func == 1)
2531 || (bpctl_dev_arr->func == 3))
2532 BP10GB_WRITE_REG(pbpctl_dev,
2533 MISC_REG_GPIO,
2534 (ctrl |
2535 BP10GB_GPIO0_CLR_P1) &
2536 ~(BP10GB_GPIO0_SET_P1 |
2537 BP10GB_GPIO0_OE_P1));
2538 else
2539 BP10GB_WRITE_REG(pbpctl_dev,
2540 MISC_REG_GPIO,
2541 (ctrl |
2542 BP10GB_GPIO0_OE_P0 |
2543 BP10GB_GPIO0_CLR_P0));
2544
2545 } else if (pbpctl_dev->bp_i80) {
2546 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2547 ((ctrl |
2548 BPCTLI_CTRL_SDP1_DIR) &
2549 ~BPCTLI_CTRL_SWDPIN1));
2550 } else if (pbpctl_dev->bp_540) {
2551 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2552 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2553 ((ctrl | BP10G_SDP1_DIR) &
2554 ~BP10G_SDP1_DATA));
2555 }
2556
2557 else if (!pbpctl_dev->bp_10g) {
2558 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2559 ((ctrl | BPCTLI_CTRL_SWDPIO0)
2560 & ~BPCTLI_CTRL_SWDPIN0));
2561 if (!PEGF_IF_SERIES(pbpctl_dev->subdevice)) {
2562 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2563 (ctrl &
2564 ~
2565 (BPCTLI_CTRL_SDP0_DATA
2566 |
2567 BPCTLI_CTRL_SDP0_DIR)));
2568 }
2569 } else
7040e556
D		 2570 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2571 ((ctrl | BP10G_SDP0_DIR) &
2572 ~BP10G_SDP0_DATA));
2573
2574 }
2575
2576 } else
2577 ret = BP_NOT_CAP;
2578 return ret;
2579
2580}
2581
2582/* SET_FORCE_LINK (non-Bypass command :)) */
81908e8b 2583static int set_bp_force_link(bpctl_dev_t *pbpctl_dev, int tx_state)
7040e556
D		 2584{
2585 int ret = 0, ctrl = 0;
2586
2587 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
2588
2589 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
2590
2591 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2592 if (!tx_state)
2593 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2594 ctrl & ~BP10G_SDP1_DIR);
2595 else
2596 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2597 ((ctrl | BP10G_SDP1_DIR) &
2598 ~BP10G_SDP1_DATA));
2599 return ret;
2600 }
2601
2602 }
2603 return BP_NOT_CAP;
2604}
2605
2606/*RESET_CONT 0x20 */
81908e8b 2607int reset_cont(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2608{
2609 int ret = BP_NOT_CAP;
2610
2611 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2612 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2613 return BP_NOT_CAP;
2614 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2615 write_data(pbpctl_dev, RESET_CONT);
2616 else
2617 data_pulse(pbpctl_dev, RESET_CONT);
2618 ret = 0;
2619 };
2620 return ret;
2621}
2622
2623/*DIS_BYPASS_CAP 0x22 */
81908e8b 2624int dis_bypass_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2625{
2626
2627 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2628 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2629 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2630 msec_delay_bp(BYPASS_DELAY_INT);
2631 } else {
2632 write_data(pbpctl_dev, BYPASS_OFF);
2633 msec_delay_bp(LATCH_DELAY);
2634 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2635 msec_delay_bp(BYPASS_CAP_DELAY);
2636 }
2637 return 0;
2638 }
2639 return BP_NOT_CAP;
2640}
2641
2642/*EN_BYPASS_CAP 0x24 */
81908e8b 2643int en_bypass_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2644{
2645 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2646 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2647 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2648 msec_delay_bp(BYPASS_DELAY_INT);
2649 } else {
2650 write_data(pbpctl_dev, EN_BYPASS_CAP);
2651 msec_delay_bp(BYPASS_CAP_DELAY);
2652 }
2653 return 0;
2654 }
2655 return BP_NOT_CAP;
2656}
2657
2658/* BYPASS_STATE_PWRON 0x26*/
81908e8b 2659int bypass_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2660{
2661 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2662 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2663 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2664 msec_delay_bp(DFLT_PWRON_DELAY);
2665 else
2666 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2667 return 0;
2668 }
2669 return BP_NOT_CAP;
2670}
2671
2672/* NORMAL_STATE_PWRON 0x28*/
81908e8b 2673int normal_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2674{
2675 if ((pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP)
2676 || (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)) {
2677 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2678 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2679 msec_delay_bp(DFLT_PWRON_DELAY);
2680 else
2681 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2682 return 0;
2683 }
2684 return BP_NOT_CAP;
2685}
2686
2687/* BYPASS_STATE_PWROFF 0x27*/
81908e8b 2688int bypass_state_pwroff(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2689{
2690 if (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP) {
2691 write_data(pbpctl_dev, BYPASS_STATE_PWROFF);
2692 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2693 return 0;
2694 }
2695 return BP_NOT_CAP;
2696}
2697
2698/* NORMAL_STATE_PWROFF 0x29*/
81908e8b 2699int normal_state_pwroff(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2700{
2701 if ((pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
2702 write_data(pbpctl_dev, NORMAL_STATE_PWROFF);
2703 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2704 return 0;
2705 }
2706 return BP_NOT_CAP;
2707}
2708
2709/*TAP_STATE_PWRON 0x2a*/
81908e8b 2710int tap_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2711{
2712 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2713 write_data(pbpctl_dev, TAP_STATE_PWRON);
2714 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2715 return 0;
2716 }
2717 return BP_NOT_CAP;
2718}
2719
2720/*DIS_TAP_CAP 0x2c*/
81908e8b 2721int dis_tap_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2722{
2723 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2724 write_data(pbpctl_dev, DIS_TAP_CAP);
2725 msec_delay_bp(BYPASS_CAP_DELAY);
2726 return 0;
2727 }
2728 return BP_NOT_CAP;
2729}
2730
2731/*EN_TAP_CAP 0x2e*/
81908e8b 2732int en_tap_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2733{
2734 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2735 write_data(pbpctl_dev, EN_TAP_CAP);
2736 msec_delay_bp(BYPASS_CAP_DELAY);
2737 return 0;
2738 }
2739 return BP_NOT_CAP;
2740}
2741
2742/*DISC_STATE_PWRON 0x2a*/
81908e8b 2743int disc_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2744{
2745 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
2746 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2747 write_data(pbpctl_dev, DISC_STATE_PWRON);
2748 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2749 return BP_OK;
2750 }
2751 }
2752 return BP_NOT_CAP;
2753}
2754
2755/*DIS_DISC_CAP 0x2c*/
81908e8b 2756int dis_disc_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2757{
2758 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2759 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2760 write_data(pbpctl_dev, DIS_DISC_CAP);
2761 msec_delay_bp(BYPASS_CAP_DELAY);
2762 return BP_OK;
2763 }
2764 }
2765 return BP_NOT_CAP;
2766}
2767
2768/*DISC_STATE_PWRON 0x2a*/
81908e8b 2769int disc_port_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2770{
2771 int ret = 0;
2772 bpctl_dev_t *pbpctl_dev_m;
2773
2774 return BP_NOT_CAP;
2775
2776 if ((is_bypass_fn(pbpctl_dev)) == 1)
2777 pbpctl_dev_m = pbpctl_dev;
2778 else
2779 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2780 if (pbpctl_dev_m == NULL)
2781 return BP_NOT_CAP;
2782
2783 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2784 if (is_bypass_fn(pbpctl_dev) == 1)
2785 write_data(pbpctl_dev_m, TX_DISA_PWRUP);
2786 else
2787 write_data(pbpctl_dev_m, TX_DISB_PWRUP);
2788
2789 msec_delay_bp(LATCH_DELAY);
2790
2791 }
2792 return ret;
2793}
2794
81908e8b 2795int normal_port_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2796{
2797 int ret = 0;
2798 bpctl_dev_t *pbpctl_dev_m;
2799 return BP_NOT_CAP;
2800
2801 if ((is_bypass_fn(pbpctl_dev)) == 1)
2802 pbpctl_dev_m = pbpctl_dev;
2803 else
2804 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2805 if (pbpctl_dev_m == NULL)
2806 return BP_NOT_CAP;
2807
2808 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2809 if (is_bypass_fn(pbpctl_dev) == 1)
2810 write_data(pbpctl_dev_m, TX_ENA_PWRUP);
2811 else
2812 write_data(pbpctl_dev_m, TX_ENB_PWRUP);
2813
2814 msec_delay_bp(LATCH_DELAY);
2815
2816 }
2817 return ret;
2818}
2819
2820/*EN_TAP_CAP 0x2e*/
81908e8b 2821int en_disc_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2822{
2823 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2824 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2825 write_data(pbpctl_dev, EN_DISC_CAP);
2826 msec_delay_bp(BYPASS_CAP_DELAY);
2827 return BP_OK;
2828 }
2829 }
2830 return BP_NOT_CAP;
2831}
2832
81908e8b 2833int std_nic_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2834{
2835
2836 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2837
2838 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2839 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2840 msec_delay_bp(BYPASS_DELAY_INT);
2841 pbpctl_dev->bp_status_un = 0;
2842 return BP_OK;
2843 }
2844
2845 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2846 write_data(pbpctl_dev, STD_NIC_ON);
2847 msec_delay_bp(BYPASS_CAP_DELAY);
2848 return BP_OK;
2849
2850 }
2851
2852 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2853 wdt_off(pbpctl_dev);
2854
2855 if (pbpctl_dev->bp_caps & BP_CAP) {
2856 write_data(pbpctl_dev, BYPASS_OFF);
2857 msec_delay_bp(LATCH_DELAY);
2858 }
2859
2860 if (pbpctl_dev->bp_caps & TAP_CAP) {
2861 write_data(pbpctl_dev, TAP_OFF);
2862 msec_delay_bp(LATCH_DELAY);
2863 }
2864
2865 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2866 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2867 msec_delay_bp(DFLT_PWRON_DELAY);
2868 else
2869 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2870
2871 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2872 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2873 msec_delay_bp(BYPASS_CAP_DELAY);
2874 }
2875
2876 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2877 write_data(pbpctl_dev, DIS_TAP_CAP);
2878 msec_delay_bp(BYPASS_CAP_DELAY);
2879
2880 }
2881 return 0;
2882 }
2883 }
2884 return BP_NOT_CAP;
2885}
2886
81908e8b 2887int std_nic_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2888{
2889
2890 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2891 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2892 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2893 msec_delay_bp(BYPASS_DELAY_INT);
2894 return BP_OK;
2895 }
2896 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2897 write_data(pbpctl_dev, STD_NIC_OFF);
2898 msec_delay_bp(BYPASS_CAP_DELAY);
2899 return BP_OK;
2900
2901 }
2902
2903 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2904
2905 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2906 write_data(pbpctl_dev, TAP_STATE_PWRON);
2907 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2908 }
2909
2910 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2911 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2912 if (pbpctl_dev->bp_ext_ver > PXG2BPI_VER)
2913 msec_delay_bp(LATCH_DELAY +
2914 EEPROM_WR_DELAY);
2915 else
2916 msec_delay_bp(DFLT_PWRON_DELAY);
2917 }
2918
2919 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2920 write_data(pbpctl_dev, EN_TAP_CAP);
2921 msec_delay_bp(BYPASS_CAP_DELAY);
2922 }
2923 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2924 write_data(pbpctl_dev, EN_DISC_CAP);
2925 msec_delay_bp(BYPASS_CAP_DELAY);
2926 }
2927
2928 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2929 write_data(pbpctl_dev, EN_BYPASS_CAP);
2930 msec_delay_bp(BYPASS_CAP_DELAY);
2931 }
2932
2933 return 0;
2934 }
2935 }
2936 return BP_NOT_CAP;
2937}
2938
81908e8b 2939int wdt_time_left(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2940{
2941
687bcca0 2942 /* unsigned long curr_time=((long long)(jiffies*1000))/HZ, delta_time=0,wdt_on_time=((long long)(pbpctl_dev->bypass_wdt_on_time*1000))/HZ; */
7040e556
D		 2943 unsigned long curr_time = jiffies, delta_time = 0, wdt_on_time =
2944 pbpctl_dev->bypass_wdt_on_time, delta_time_msec = 0;
2945 int time_left = 0;
2946
2947 switch (pbpctl_dev->wdt_status) {
2948 case WDT_STATUS_DIS:
2949 time_left = 0;
2950 break;
2951 case WDT_STATUS_EN:
2952 delta_time =
2953 (curr_time >=
2954 wdt_on_time) ? (curr_time - wdt_on_time) : (~wdt_on_time +
2955 curr_time);
2956 delta_time_msec = jiffies_to_msecs(delta_time);
2957 time_left = pbpctl_dev->bypass_timer_interval - delta_time_msec;
2958 if (time_left < 0) {
2959 time_left = -1;
2960 pbpctl_dev->wdt_status = WDT_STATUS_EXP;
2961 }
2962 break;
2963 case WDT_STATUS_EXP:
2964 time_left = -1;
2965 break;
2966 }
2967
2968 return time_left;
2969}
2970
81908e8b 2971static int wdt_timer(bpctl_dev_t *pbpctl_dev, int *time_left)
7040e556
D		 2972{
2973 int ret = 0;
2974 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2975 {
2976 if (pbpctl_dev->wdt_status == WDT_STATUS_UNKNOWN)
2977 ret = BP_NOT_CAP;
2978 else
2979 *time_left = wdt_time_left(pbpctl_dev);
2980 }
2981
2982 } else
2983 ret = BP_NOT_CAP;
2984 return ret;
2985}
2986
81908e8b 2987static int wdt_timer_reload(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2988{
2989
2990 int ret = 0;
2991
2992 if ((pbpctl_dev->bp_caps & WD_CTL_CAP) &&
2993 (pbpctl_dev->wdt_status != WDT_STATUS_UNKNOWN)) {
2994 if (pbpctl_dev->wdt_status == WDT_STATUS_DIS)
2995 return 0;
2996 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2997 ret = wdt_pulse(pbpctl_dev);
2998 else if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2999 ret = wdt_pulse_int(pbpctl_dev);
3000 else
3001 ret = send_wdt_pulse(pbpctl_dev);
687bcca0
DC		 3002 /* if (ret==-1)
3003 mod_timer(&pbpctl_dev->bp_timer, jiffies+1);*/
7040e556
D		 3004 return 1;
3005 }
3006 return BP_NOT_CAP;
3007}
3008
3009static void wd_reset_timer(unsigned long param)
3010{
3011 bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
3012#ifdef BP_SELF_TEST
3013 struct sk_buff *skb_tmp;
3014#endif
3015
3016 if ((pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) &&
3017 ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)) {
3018 mod_timer(&pbpctl_dev->bp_timer, jiffies + 1);
3019 return;
3020 }
3021#ifdef BP_SELF_TEST
3022
3023 if (pbpctl_dev->bp_self_test_flag == 1) {
3024 skb_tmp = dev_alloc_skb(BPTEST_DATA_LEN + 2);
3025 if ((skb_tmp) && (pbpctl_dev->ndev) && (pbpctl_dev->bp_tx_data)) {
3026 memcpy(skb_put(skb_tmp, BPTEST_DATA_LEN),
3027 pbpctl_dev->bp_tx_data, BPTEST_DATA_LEN);
3028 skb_tmp->dev = pbpctl_dev->ndev;
3029 skb_tmp->protocol =
3030 eth_type_trans(skb_tmp, pbpctl_dev->ndev);
3031 skb_tmp->ip_summed = CHECKSUM_UNNECESSARY;
3032 netif_receive_skb(skb_tmp);
3033 goto bp_timer_reload;
3034 return;
3035 }
3036 }
3037#endif
3038
3039 wdt_timer_reload(pbpctl_dev);
3040#ifdef BP_SELF_TEST
3041 bp_timer_reload:
3042#endif
3043 if (pbpctl_dev->reset_time) {
3044 mod_timer(&pbpctl_dev->bp_timer,
3045 jiffies + (HZ * pbpctl_dev->reset_time) / 1000);
3046 }
3047}
3048
7040e556 3049/*WAIT_AT_PWRUP 0x80 */
81908e8b 3050int bp_wait_at_pwup_en(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3051{
3052
3053 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3054 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3055 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_EN);
3056 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3057
3058 return BP_OK;
3059 }
3060 }
3061 return BP_NOT_CAP;
3062}
3063
3064/*DIS_WAIT_AT_PWRUP 0x81 */
81908e8b 3065int bp_wait_at_pwup_dis(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3066{
3067
3068 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3069
3070 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3071 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_DIS);
3072 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3073
3074 return BP_OK;
3075 }
3076 }
3077 return BP_NOT_CAP;
3078}
3079
3080/*EN_HW_RESET 0x82 */
3081
81908e8b 3082int bp_hw_reset_en(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3083{
3084
3085 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3086 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3087 write_data(pbpctl_dev, BP_HW_RESET_EN);
3088 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3089
3090 return BP_OK;
3091 }
3092 }
3093 return BP_NOT_CAP;
3094}
3095
3096/*DIS_HW_RESET 0x83 */
3097
81908e8b 3098int bp_hw_reset_dis(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3099{
3100
3101 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3102 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3103 write_data(pbpctl_dev, BP_HW_RESET_DIS);
3104 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3105
3106 return BP_OK;
3107 }
3108 }
3109 return BP_NOT_CAP;
3110}
3111
7040e556 3112
81908e8b 3113int wdt_exp_mode(bpctl_dev_t *pbpctl_dev, int mode)
7040e556
D		 3114{
3115 uint32_t status_reg = 0, status_reg1 = 0;
3116
3117 if ((pbpctl_dev->bp_caps & (TAP_STATUS_CAP | DISC_CAP)) &&
3118 (pbpctl_dev->bp_caps & BP_CAP)) {
3119 if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3120
3121 if ((pbpctl_dev->bp_ext_ver >= 0x8) &&
3122 (mode == 2) && (pbpctl_dev->bp_caps & DISC_CAP)) {
3123 status_reg1 =
3124 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3125 if (!(status_reg1 & WDTE_DISC_BPN_MASK))
3126 write_reg(pbpctl_dev,
3127 status_reg1 |
3128 WDTE_DISC_BPN_MASK,
3129 STATUS_DISC_REG_ADDR);
3130 return BP_OK;
3131 }
3132 }
3133 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3134
3135 if ((mode == 0) && (pbpctl_dev->bp_caps & BP_CAP)) {
3136 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3137 status_reg1 =
3138 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3139 if (status_reg1 & WDTE_DISC_BPN_MASK)
3140 write_reg(pbpctl_dev,
3141 status_reg1 &
3142 ~WDTE_DISC_BPN_MASK,
3143 STATUS_DISC_REG_ADDR);
3144 }
3145 if (status_reg & WDTE_TAP_BPN_MASK)
3146 write_reg(pbpctl_dev,
3147 status_reg & ~WDTE_TAP_BPN_MASK,
3148 STATUS_TAP_REG_ADDR);
3149 return BP_OK;
3150
3151 } else if ((mode == 1) && (pbpctl_dev->bp_caps & TAP_CAP)) {
3152 if (!(status_reg & WDTE_TAP_BPN_MASK))
3153 write_reg(pbpctl_dev,
3154 status_reg | WDTE_TAP_BPN_MASK,
3155 STATUS_TAP_REG_ADDR);
3156 /*else return BP_NOT_CAP; */
3157 return BP_OK;
3158 }
3159
3160 }
3161 return BP_NOT_CAP;
3162}
3163
81908e8b 3164int bypass_fw_ver(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3165{
3166 if (is_bypass_fn(pbpctl_dev))
7935c80c 3167 return read_reg(pbpctl_dev, VER_REG_ADDR);
7040e556
D		 3168 else
3169 return BP_NOT_CAP;
3170}
3171
81908e8b 3172int bypass_sign_check(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3173{
3174
3175 if (is_bypass_fn(pbpctl_dev))
3176 return (((read_reg(pbpctl_dev, PIC_SIGN_REG_ADDR)) ==
3177 PIC_SIGN_VALUE) ? 1 : 0);
3178 else
3179 return BP_NOT_CAP;
3180}
3181
81908e8b 3182static int tx_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3183{
3184 uint32_t ctrl = 0;
3185 bpctl_dev_t *pbpctl_dev_m;
3186 if ((is_bypass_fn(pbpctl_dev)) == 1)
3187 pbpctl_dev_m = pbpctl_dev;
3188 else
3189 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3190 if (pbpctl_dev_m == NULL)
3191 return BP_NOT_CAP;
3192 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3193
3194 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3195 if (pbpctl_dev->bp_i80)
3196 return ((ctrl & BPCTLI_CTRL_SWDPIN1) != 0 ? 0 : 1);
3197 if (pbpctl_dev->bp_540) {
3198 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3199
3200 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3201 }
3202
3203 }
3204
3205 if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
3206 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
3207 uint16_t mii_reg;
3208 if (!
3209 (bp75_read_phy_reg
3210 (pbpctl_dev, BPCTLI_PHY_CONTROL, &mii_reg))) {
3211 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN)
3212 return 0;
3213
3214 else
3215 return 1;
3216 }
3217 return -1;
3218 }
3219
3220 if (pbpctl_dev->bp_10g9) {
3221 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3222 BP10G_SDP3_DATA) != 0 ? 0 : 1);
3223
3224 } else if (pbpctl_dev->bp_fiber5) {
3225 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
3226 if (ctrl & BPCTLI_CTRL_EXT_SDP6_DATA)
3227 return 0;
3228 return 1;
3229 } else if (pbpctl_dev->bp_10gb) {
3230 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3231 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3232 (ctrl | BP10GB_GPIO0_OE_P1) &
3233 ~(BP10GB_GPIO0_SET_P1 |
3234 BP10GB_GPIO0_CLR_P1));
3235
3236 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
3237 return (((BP10GB_READ_REG
3238 (pbpctl_dev,
3239 MISC_REG_GPIO)) & BP10GB_GPIO0_P1) !=
3240 0 ? 0 : 1);
3241 else
3242 return (((BP10GB_READ_REG
3243 (pbpctl_dev,
3244 MISC_REG_GPIO)) & BP10GB_GPIO0_P0) !=
3245 0 ? 0 : 1);
3246 }
3247
3248 if (!pbpctl_dev->bp_10g) {
3249
3250 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3251 if (pbpctl_dev->bp_i80)
3252 return ((ctrl & BPCTLI_CTRL_SWDPIN1) !=
3253 0 ? 0 : 1);
3254 if (pbpctl_dev->bp_540) {
3255 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3256
3257 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3258 }
3259
3260 return ((ctrl & BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3261 } else
3262 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3263 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3264
3265 }
3266 return BP_NOT_CAP;
3267}
3268
81908e8b 3269static int bp_force_link_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3270{
3271
3272 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
3273
3274 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
3275 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3276 BP10G_SDP1_DIR) != 0 ? 1 : 0);
3277
3278 }
3279 }
3280 return BP_NOT_CAP;
3281}
3282
81908e8b 3283int bypass_from_last_read(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3284{
3285 uint32_t ctrl_ext = 0;
3286 bpctl_dev_t *pbpctl_dev_b = NULL;
3287
3288 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3289 && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3290 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3291 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL_EXT,
3292 (ctrl_ext & ~BPCTLI_CTRL_EXT_SDP7_DIR));
3293 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3294 if (ctrl_ext & BPCTLI_CTRL_EXT_SDP7_DATA)
3295 return 0;
3296 return 1;
3297 } else
3298 return BP_NOT_CAP;
3299}
3300
0920af72 3301int bypass_status_clear(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3302{
3303 bpctl_dev_t *pbpctl_dev_b = NULL;
3304
3305 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3306 && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3307
3308 send_bypass_clear_pulse(pbpctl_dev_b, 1);
3309 return 0;
3310 } else
3311 return BP_NOT_CAP;
3312}
3313
0920af72 3314int bypass_flag_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3315{
3316
3317 if ((pbpctl_dev->bp_caps & BP_CAP)) {
3318 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3319 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3320 BYPASS_FLAG_MASK) ==
3321 BYPASS_FLAG_MASK) ? 1 : 0);
3322 }
3323 }
3324 return BP_NOT_CAP;
3325}
3326
0920af72 3327int bypass_flag_status_clear(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3328{
3329
3330 if (pbpctl_dev->bp_caps & BP_CAP) {
3331 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3332 uint32_t status_reg = 0;
3333 status_reg = read_reg(pbpctl_dev, STATUS_REG_ADDR);
3334 write_reg(pbpctl_dev, status_reg & ~BYPASS_FLAG_MASK,
3335 STATUS_REG_ADDR);
3336 return 0;
3337 }
3338 }
3339 return BP_NOT_CAP;
3340}
3341
0920af72 3342int bypass_change_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3343{
3344 int ret = BP_NOT_CAP;
3345
3346 if (pbpctl_dev->bp_caps & BP_STATUS_CHANGE_CAP) {
3347 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3348 ret = bypass_flag_status(pbpctl_dev);
3349 bypass_flag_status_clear(pbpctl_dev);
3350 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3351 ret = bypass_flag_status(pbpctl_dev);
3352 bypass_flag_status_clear(pbpctl_dev);
3353 } else {
3354 ret = bypass_from_last_read(pbpctl_dev);
3355 bypass_status_clear(pbpctl_dev);
3356 }
3357 }
3358 return ret;
3359}
3360
0920af72 3361int bypass_off_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3362{
3363
3364 if (pbpctl_dev->bp_caps & BP_CAP) {
3365 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3366 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3367 BYPASS_OFF_MASK) == BYPASS_OFF_MASK) ? 1 : 0);
3368 }
3369 }
3370 return BP_NOT_CAP;
3371}
3372
0920af72 3373static int bypass_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3374{
3375 u32 ctrl_ext = 0;
3376 if (pbpctl_dev->bp_caps & BP_CAP) {
3377
3378 bpctl_dev_t *pbpctl_dev_b = NULL;
3379
3380 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3381 return BP_NOT_CAP;
3382
3383 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
3384
3385 if (!pbpctl_dev->bp_status_un)
3386 return (((BPCTL_READ_REG
3387 (pbpctl_dev_b,
3388 CTRL_EXT)) &
3389 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3390 0 ? 1 : 0);
3391 else
3392 return BP_NOT_CAP;
3393 }
3394 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3395
7040e556
D		 3396 if (pbpctl_dev->bp_10g9) {
3397 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3398 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3399 (ctrl_ext | BP10G_I2C_CLK_OUT));
7040e556
D		 3400 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3401 BP10G_I2C_CLK_IN) != 0 ? 0 : 1);
3402
3403 } else if (pbpctl_dev->bp_540) {
3404 return (((BP10G_READ_REG(pbpctl_dev_b, ESDP)) &
3405 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3406 }
3407
3408 else if ((pbpctl_dev->bp_fiber5)
3409 || (pbpctl_dev->bp_i80)) {
3410 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3411 BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3412 } else if (pbpctl_dev->bp_10gb) {
3413 ctrl_ext =
3414 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3415 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3416 (ctrl_ext | BP10GB_GPIO3_OE_P0)
3417 & ~(BP10GB_GPIO3_SET_P0 |
3418 BP10GB_GPIO3_CLR_P0));
3419
3420 return (((BP10GB_READ_REG
3421 (pbpctl_dev,
3422 MISC_REG_GPIO)) & BP10GB_GPIO3_P0) !=
3423 0 ? 0 : 1);
3424 }
3425
3426 else if (!pbpctl_dev->bp_10g)
3427 return (((BPCTL_READ_REG
3428 (pbpctl_dev_b,
3429 CTRL_EXT)) &
3430 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3431 0 ? 0 : 1);
3432
3433 else {
3434 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3435 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3436 (ctrl_ext |
3437 BP10G_SDP7_DATA_OUT));
7040e556
D		 3438 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3439 BP10G_SDP7_DATA_IN) != 0 ? 0 : 1);
3440 }
3441
3442 } else if (pbpctl_dev->media_type == bp_copper) {
3443
3444 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3445 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3446 } else {
3447 if ((bypass_status_clear(pbpctl_dev)) >= 0)
7935c80c 3448 return bypass_from_last_read(pbpctl_dev);
7040e556
D		 3449 }
3450
3451 }
3452 return BP_NOT_CAP;
3453}
3454
0920af72 3455int default_pwron_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3456{
3457
3458 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3459 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
3460 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3461 return ((((read_reg
3462 (pbpctl_dev,
3463 STATUS_REG_ADDR)) & DFLT_PWRON_MASK)
3464 == DFLT_PWRON_MASK) ? 0 : 1);
3465 }
3466 } /*else if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3467 (pbpctl_dev->bp_caps&BP_PWUP_ON_CAP))
3468 return 1; */
3469 }
3470 return BP_NOT_CAP;
3471}
3472
0920af72 3473static int default_pwroff_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3474{
3475
3476 /*if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3477 (pbpctl_dev->bp_caps&BP_PWOFF_ON_CAP))
3478 return 1; */
3479 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3480 && (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
3481 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3482 DFLT_PWROFF_MASK) == DFLT_PWROFF_MASK) ? 0 : 1);
3483 }
3484 return BP_NOT_CAP;
3485}
3486
0920af72 3487int dis_bypass_cap_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3488{
3489
3490 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
3491 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3492 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3493 DIS_BYPASS_CAP_MASK) ==
3494 DIS_BYPASS_CAP_MASK) ? 1 : 0);
3495 }
3496 }
3497 return BP_NOT_CAP;
3498}
3499
0920af72 3500int cmd_en_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3501{
3502
3503 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3504 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3505 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3506 CMND_EN_MASK) == CMND_EN_MASK) ? 1 : 0);
3507 }
3508 }
3509 return BP_NOT_CAP;
3510}
3511
0920af72 3512int wdt_en_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3513{
3514
3515 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3516 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3517 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3518 WDT_EN_MASK) == WDT_EN_MASK) ? 1 : 0);
3519 }
3520 }
3521 return BP_NOT_CAP;
3522}
3523
0920af72 3524int wdt_programmed(bpctl_dev_t *pbpctl_dev, int *timeout)
7040e556
D		 3525{
3526 int ret = 0;
3527 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3528 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3529 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3530 WDT_EN_MASK) {
3531 u8 wdt_val;
3532 wdt_val = read_reg(pbpctl_dev, WDT_REG_ADDR);
3533 *timeout = (1 << wdt_val) * 100;
3534 } else
3535 *timeout = 0;
3536 } else {
3537 int curr_wdt_status = pbpctl_dev->wdt_status;
3538 if (curr_wdt_status == WDT_STATUS_UNKNOWN)
3539 *timeout = -1;
3540 else
3541 *timeout =
3542 curr_wdt_status ==
3543 0 ? 0 : pbpctl_dev->bypass_timer_interval;
3544 };
3545 } else
3546 ret = BP_NOT_CAP;
3547 return ret;
3548}
3549
0920af72 3550int bypass_support(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3551{
3552 int ret = 0;
3553
3554 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3555 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3556 ret =
3557 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3558 BYPASS_SUPPORT_MASK) ==
3559 BYPASS_SUPPORT_MASK) ? 1 : 0);
3560 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3561 ret = 1;
3562 } else
3563 ret = BP_NOT_CAP;
3564 return ret;
3565}
3566
0920af72 3567int tap_support(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3568{
3569 int ret = 0;
3570
3571 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3572 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3573 ret =
3574 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3575 TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) ? 1 : 0);
3576 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3577 ret = 0;
3578 } else
3579 ret = BP_NOT_CAP;
3580 return ret;
3581}
3582
0920af72 3583int normal_support(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3584{
3585 int ret = BP_NOT_CAP;
3586
3587 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3588 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3589 ret =
3590 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3591 NORMAL_UNSUPPORT_MASK) ==
3592 NORMAL_UNSUPPORT_MASK) ? 0 : 1);
3593 } else
3594 ret = 1;
3595 };
3596 return ret;
3597}
3598
0920af72 3599int get_bp_prod_caps(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3600{
3601 if ((pbpctl_dev->bp_caps & SW_CTL_CAP) &&
3602 (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER))
7935c80c 3603 return read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
7040e556
D		 3604 return BP_NOT_CAP;
3605
3606}
3607
0920af72 3608int tap_flag_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3609{
3610
3611 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3612 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3613 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3614 TAP_FLAG_MASK) == TAP_FLAG_MASK) ? 1 : 0);
3615
3616 }
3617 return BP_NOT_CAP;
3618}
3619
0920af72 3620int tap_flag_status_clear(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3621{
3622 uint32_t status_reg = 0;
3623 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3624 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3625 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3626 write_reg(pbpctl_dev, status_reg & ~TAP_FLAG_MASK,
3627 STATUS_TAP_REG_ADDR);
3628 return 0;
3629 }
3630 }
3631 return BP_NOT_CAP;
3632}
3633
0920af72 3634int tap_change_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3635{
3636 int ret = BP_NOT_CAP;
3637 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3638 if (pbpctl_dev->bp_caps & TAP_CAP) {
3639 if (pbpctl_dev->bp_caps & BP_CAP) {
3640 ret = tap_flag_status(pbpctl_dev);
3641 tap_flag_status_clear(pbpctl_dev);
3642 } else {
3643 ret = bypass_from_last_read(pbpctl_dev);
3644 bypass_status_clear(pbpctl_dev);
3645 }
3646 }
3647 }
3648 return ret;
3649}
3650
0920af72 3651int tap_off_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3652{
3653 if (pbpctl_dev->bp_caps & TAP_CAP) {
3654 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3655 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3656 TAP_OFF_MASK) == TAP_OFF_MASK) ? 1 : 0);
3657 }
3658 return BP_NOT_CAP;
3659}
3660
0920af72 3661int tap_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3662{
3663 u32 ctrl_ext = 0;
3664
3665 if (pbpctl_dev->bp_caps & TAP_CAP) {
3666 bpctl_dev_t *pbpctl_dev_b = NULL;
3667
3668 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3669 return BP_NOT_CAP;
3670
3671 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3672 if (!pbpctl_dev->bp_10g)
3673 return (((BPCTL_READ_REG
3674 (pbpctl_dev_b,
3675 CTRL_EXT)) &
3676 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3677 0 ? 0 : 1);
3678 else {
3679 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3680 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3681 (ctrl_ext |
3682 BP10G_SDP6_DATA_OUT));
7040e556
D		 3683 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3684 BP10G_SDP6_DATA_IN) != 0 ? 0 : 1);
3685 }
3686
3687 } else if (pbpctl_dev->media_type == bp_copper)
3688 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3689 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3690 else {
3691 if ((bypass_status_clear(pbpctl_dev)) >= 0)
7935c80c 3692 return bypass_from_last_read(pbpctl_dev);
7040e556
D		 3693 }
3694
3695 }
3696 return BP_NOT_CAP;
3697}
3698
0920af72 3699int default_pwron_tap_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3700{
3701 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3702 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3703 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3704 DFLT_PWRON_TAP_MASK) ==
3705 DFLT_PWRON_TAP_MASK) ? 1 : 0);
3706 }
3707 return BP_NOT_CAP;
3708}
3709
0920af72 3710int dis_tap_cap_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3711{
3712 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3713 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3714 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3715 DIS_TAP_CAP_MASK) ==
3716 DIS_TAP_CAP_MASK) ? 1 : 0);
3717 }
3718 return BP_NOT_CAP;
3719}
3720
0920af72 3721int disc_flag_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3722{
3723
3724 if (pbpctl_dev->bp_caps & DISC_CAP) {
3725 if (pbpctl_dev->bp_ext_ver >= 0x8)
3726 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3727 DISC_FLAG_MASK) == DISC_FLAG_MASK) ? 1 : 0);
3728
3729 }
3730 return BP_NOT_CAP;
3731}
3732
0920af72 3733int disc_flag_status_clear(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3734{
3735 uint32_t status_reg = 0;
3736 if (pbpctl_dev->bp_caps & DISC_CAP) {
3737 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3738 status_reg = read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3739 write_reg(pbpctl_dev, status_reg & ~DISC_FLAG_MASK,
3740 STATUS_DISC_REG_ADDR);
3741 return BP_OK;
3742 }
3743 }
3744 return BP_NOT_CAP;
3745}
3746
0920af72 3747int disc_change_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3748{
3749 int ret = BP_NOT_CAP;
3750 if (pbpctl_dev->bp_caps & DISC_CAP) {
3751 ret = disc_flag_status(pbpctl_dev);
3752 disc_flag_status_clear(pbpctl_dev);
3753 return ret;
3754 }
3755 return BP_NOT_CAP;
3756}
3757
0920af72 3758int disc_off_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3759{
3760 bpctl_dev_t *pbpctl_dev_b = NULL;
3761 u32 ctrl_ext = 0;
3762
3763 if (pbpctl_dev->bp_caps & DISC_CAP) {
3764 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3765 return BP_NOT_CAP;
3766 if (DISCF_IF_SERIES(pbpctl_dev->subdevice))
3767 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3768 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3769
3770 if (pbpctl_dev->bp_i80) {
7040e556
D		 3771 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT)) &
3772 BPCTLI_CTRL_EXT_SDP6_DATA) != 0 ? 1 : 0);
3773
3774 }
3775 if (pbpctl_dev->bp_540) {
3776 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, ESDP);
7040e556
D		 3777 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3778 BP10G_SDP2_DATA) != 0 ? 1 : 0);
3779
3780 }
7040e556
D		 3781 if (pbpctl_dev->media_type == bp_copper) {
3782
3783#if 0
3784 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3785 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3786#endif
3787 if (!pbpctl_dev->bp_10g)
3788 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3789 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3790 else
7040e556
D		 3791 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3792 BP10G_SDP1_DATA) != 0 ? 1 : 0);
3793
3794 } else {
3795
3796 if (pbpctl_dev->bp_10g9) {
3797 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3798 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3799 (ctrl_ext |
3800 BP10G_I2C_DATA_OUT));
7040e556
D		 3801 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3802 BP10G_I2C_DATA_IN) != 0 ? 1 : 0);
3803
3804 } else if (pbpctl_dev->bp_fiber5) {
3805 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3806 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3807 } else if (pbpctl_dev->bp_10gb) {
3808 ctrl_ext =
3809 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3810 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3811 (ctrl_ext | BP10GB_GPIO3_OE_P1)
3812 & ~(BP10GB_GPIO3_SET_P1 |
3813 BP10GB_GPIO3_CLR_P1));
3814
3815 return (((BP10GB_READ_REG
3816 (pbpctl_dev,
3817 MISC_REG_GPIO)) & BP10GB_GPIO3_P1) !=
3818 0 ? 1 : 0);
3819 }
3820 if (!pbpctl_dev->bp_10g) {
3821
3822 return (((BPCTL_READ_REG
3823 (pbpctl_dev_b,
3824 CTRL_EXT)) &
3825 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3826 0 ? 1 : 0);
3827 } else {
3828 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3829 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3830 (ctrl_ext |
3831 BP10G_SDP6_DATA_OUT));
7040e556
D		 3832 return (((BP10G_READ_REG(pbpctl_dev_b, EODSDP))
3833 & BP10G_SDP6_DATA_IN) != 0 ? 1 : 0);
3834 }
3835
3836 }
3837 }
3838 return BP_NOT_CAP;
3839}
3840
0920af72 3841static int disc_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3842{
3843 int ctrl = 0;
3844 if (pbpctl_dev->bp_caps & DISC_CAP) {
3845
3846 if ((ctrl = disc_off_status(pbpctl_dev)) < 0)
3847 return ctrl;
3848 return ((ctrl == 0) ? 1 : 0);
3849
3850 }
3851 return BP_NOT_CAP;
3852}
3853
0920af72 3854int default_pwron_disc_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3855{
3856 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
3857 if (pbpctl_dev->bp_ext_ver >= 0x8)
3858 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3859 DFLT_PWRON_DISC_MASK) ==
3860 DFLT_PWRON_DISC_MASK) ? 1 : 0);
3861 }
3862 return BP_NOT_CAP;
3863}
3864
0920af72 3865int dis_disc_cap_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3866{
3867 if (pbpctl_dev->bp_caps & DIS_DISC_CAP) {
3868 if (pbpctl_dev->bp_ext_ver >= 0x8)
3869 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3870 DIS_DISC_CAP_MASK) ==
3871 DIS_DISC_CAP_MASK) ? 1 : 0);
3872 }
3873 return BP_NOT_CAP;
3874}
3875
0920af72 3876int disc_port_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3877{
3878 int ret = BP_NOT_CAP;
3879 bpctl_dev_t *pbpctl_dev_m;
3880
3881 if ((is_bypass_fn(pbpctl_dev)) == 1)
3882 pbpctl_dev_m = pbpctl_dev;
3883 else
3884 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3885 if (pbpctl_dev_m == NULL)
3886 return BP_NOT_CAP;
3887
3888 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3889 if (is_bypass_fn(pbpctl_dev) == 1) {
3890 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3891 TX_DISA_MASK) == TX_DISA_MASK) ? 1 : 0);
3892 } else
3893 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3894 TX_DISB_MASK) == TX_DISB_MASK) ? 1 : 0);
3895
3896 }
3897 return ret;
3898}
3899
0920af72 3900int default_pwron_disc_port_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3901{
3902 int ret = BP_NOT_CAP;
3903 bpctl_dev_t *pbpctl_dev_m;
3904
3905 if ((is_bypass_fn(pbpctl_dev)) == 1)
3906 pbpctl_dev_m = pbpctl_dev;
3907 else
3908 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3909 if (pbpctl_dev_m == NULL)
3910 return BP_NOT_CAP;
3911
3912 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3913 if (is_bypass_fn(pbpctl_dev) == 1)
3914 return ret;
687bcca0 3915 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
7040e556
D		 3916 else
3917 return ret;
687bcca0 3918 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
7040e556
D		 3919
3920 }
3921 return ret;
3922}
3923
0920af72 3924int wdt_exp_mode_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3925{
3926 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3927 if (pbpctl_dev->bp_ext_ver <= PXG2BPI_VER)
3928 return 0; /* bypass mode */
3929 else if (pbpctl_dev->bp_ext_ver == PXG2TBPI_VER)
3930 return 1; /* tap mode */
3931 else if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3932 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3933 if (((read_reg
3934 (pbpctl_dev,
3935 STATUS_DISC_REG_ADDR)) &
3936 WDTE_DISC_BPN_MASK) == WDTE_DISC_BPN_MASK)
3937 return 2;
3938 }
3939 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3940 WDTE_TAP_BPN_MASK) ==
3941 WDTE_TAP_BPN_MASK) ? 1 : 0);
3942 }
3943 }
3944 return BP_NOT_CAP;
3945}
3946
9f7a6f33 3947int tpl2_flag_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3948{
3949
3950 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
3951 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3952 TPL2_FLAG_MASK) == TPL2_FLAG_MASK) ? 1 : 0);
3953
3954 }
3955 return BP_NOT_CAP;
3956}
3957
9f7a6f33 3958int tpl_hw_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3959{
3960 bpctl_dev_t *pbpctl_dev_b = NULL;
3961
3962 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3963 return BP_NOT_CAP;
3964
3965 if (TPL_IF_SERIES(pbpctl_dev->subdevice))
3966 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3967 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3968 return BP_NOT_CAP;
3969}
3970
7040e556 3971
9f7a6f33 3972int bp_wait_at_pwup_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3973{
3974 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3975 if (pbpctl_dev->bp_ext_ver >= 0x8)
3976 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3977 WAIT_AT_PWUP_MASK) ==
3978 WAIT_AT_PWUP_MASK) ? 1 : 0);
3979 }
3980 return BP_NOT_CAP;
3981}
3982
9f7a6f33 3983int bp_hw_reset_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3984{
3985
3986 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3987
3988 if (pbpctl_dev->bp_ext_ver >= 0x8)
3989 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3990 EN_HW_RESET_MASK) ==
3991 EN_HW_RESET_MASK) ? 1 : 0);
3992 }
3993 return BP_NOT_CAP;
3994}
3995
7040e556 3996
9f7a6f33 3997int std_nic_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3998{
3999 int status_val = 0;
4000
4001 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
4002 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4003 return BP_NOT_CAP;
4004 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4005 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
4006 STD_NIC_ON_MASK) == STD_NIC_ON_MASK) ? 1 : 0);
4007 }
4008
4009 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4010 if (pbpctl_dev->bp_caps & BP_CAP) {
4011 status_val =
4012 read_reg(pbpctl_dev, STATUS_REG_ADDR);
4013 if (((!(status_val & WDT_EN_MASK))
4014 && ((status_val & STD_NIC_MASK) ==
4015 STD_NIC_MASK)))
4016 status_val = 1;
4017 else
4018 return 0;
4019 }
4020 if (pbpctl_dev->bp_caps & TAP_CAP) {
4021 status_val =
4022 read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4023 if ((status_val & STD_NIC_TAP_MASK) ==
4024 STD_NIC_TAP_MASK)
4025 status_val = 1;
4026 else
4027 return 0;
4028 }
4029 if (pbpctl_dev->bp_caps & TAP_CAP) {
4030 if ((disc_off_status(pbpctl_dev)))
4031 status_val = 1;
4032 else
4033 return 0;
4034 }
4035
4036 return status_val;
4037 }
4038 }
4039 return BP_NOT_CAP;
4040}
4041
4042/******************************************************/
4043/**************SW_INIT*********************************/
4044/******************************************************/
9f7a6f33 4045void bypass_caps_init(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4046{
4047 u_int32_t ctrl_ext = 0;
4048 bpctl_dev_t *pbpctl_dev_m = NULL;
4049
4050#ifdef BYPASS_DEBUG
4051 int ret = 0;
4052 if (!(INTEL_IF_SERIES(adapter->bp_device_block.subdevice))) {
4053 ret = read_reg(pbpctl_dev, VER_REG_ADDR);
4054 printk("VER_REG reg1=%x\n", ret);
4055 ret = read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
4056 printk("PRODUCT_CAP reg=%x\n", ret);
4057 ret = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4058 printk("STATUS_TAP reg1=%x\n", ret);
4059 ret = read_reg(pbpctl_dev, 0x7);
4060 printk("SIG_REG reg1=%x\n", ret);
4061 ret = read_reg(pbpctl_dev, STATUS_REG_ADDR);
4062 printk("STATUS_REG_ADDR=%x\n", ret);
4063 ret = read_reg(pbpctl_dev, WDT_REG_ADDR);
4064 printk("WDT_REG_ADDR=%x\n", ret);
4065 ret = read_reg(pbpctl_dev, TMRL_REG_ADDR);
4066 printk("TMRL_REG_ADDR=%x\n", ret);
4067 ret = read_reg(pbpctl_dev, TMRH_REG_ADDR);
4068 printk("TMRH_REG_ADDR=%x\n", ret);
4069 }
4070#endif
4071 if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_10g9)) {
4072 pbpctl_dev->media_type = bp_fiber;
4073 } else if (pbpctl_dev->bp_10gb) {
4074 if (BP10GB_CX4_SERIES(pbpctl_dev->subdevice))
4075 pbpctl_dev->media_type = bp_cx4;
4076 else
4077 pbpctl_dev->media_type = bp_fiber;
4078
4079 }
4080
4081 else if (pbpctl_dev->bp_540)
4082 pbpctl_dev->media_type = bp_none;
4083 else if (!pbpctl_dev->bp_10g) {
4084
4085 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
4086 if ((ctrl_ext & BPCTLI_CTRL_EXT_LINK_MODE_MASK) == 0x0)
4087 pbpctl_dev->media_type = bp_copper;
4088 else
4089 pbpctl_dev->media_type = bp_fiber;
4090
687bcca0 4091 } else {
7040e556
D		 4092 if (BP10G_CX4_SERIES(pbpctl_dev->subdevice))
4093 pbpctl_dev->media_type = bp_cx4;
4094 else
4095 pbpctl_dev->media_type = bp_fiber;
4096 }
4097
7040e556
D		 4098 if (is_bypass_fn(pbpctl_dev)) {
4099
4100 pbpctl_dev->bp_caps |= BP_PWOFF_ON_CAP;
4101 if (pbpctl_dev->media_type == bp_fiber)
4102 pbpctl_dev->bp_caps |=
4103 (TX_CTL_CAP | TX_STATUS_CAP | TPL_CAP);
4104
4105 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
4106 pbpctl_dev->bp_caps |= TPL_CAP;
4107 }
4108
4109 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
4110 pbpctl_dev->bp_caps |=
4111 (BP_CAP | BP_STATUS_CAP | SW_CTL_CAP |
4112 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWOFF_OFF_CAP
4113 | WD_CTL_CAP | WD_STATUS_CAP | STD_NIC_CAP |
4114 WD_TIMEOUT_CAP);
4115
4116 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4117 return;
4118 }
4119
4120 if ((pbpctl_dev->bp_fw_ver == 0xff) &&
4121 OLD_IF_SERIES(pbpctl_dev->subdevice)) {
4122
4123 pbpctl_dev->bp_caps |=
4124 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4125 SW_CTL_CAP | BP_PWUP_ON_CAP | WD_CTL_CAP |
4126 WD_STATUS_CAP | WD_TIMEOUT_CAP);
4127
4128 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4129 return;
4130 }
4131
4132 else {
4133 switch (pbpctl_dev->bp_fw_ver) {
4134 case BP_FW_VER_A0:
4135 case BP_FW_VER_A1:{
4136 pbpctl_dev->bp_ext_ver =
4137 (pbpctl_dev->
4138 bp_fw_ver & EXT_VER_MASK);
4139 break;
4140 }
4141 default:{
4142 if ((bypass_sign_check(pbpctl_dev)) !=
4143 1) {
4144 pbpctl_dev->bp_caps = 0;
4145 return;
4146 }
4147 pbpctl_dev->bp_ext_ver =
4148 (pbpctl_dev->
4149 bp_fw_ver & EXT_VER_MASK);
4150 }
4151 }
4152 }
4153
4154 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
4155 pbpctl_dev->bp_caps |=
4156 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4157 SW_CTL_CAP | BP_DIS_CAP | BP_DIS_STATUS_CAP |
4158 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP
4159 | WD_CTL_CAP | STD_NIC_CAP | WD_STATUS_CAP |
4160 WD_TIMEOUT_CAP);
4161 else if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
4162 int cap_reg;
4163
4164 pbpctl_dev->bp_caps |=
4165 (SW_CTL_CAP | WD_CTL_CAP | WD_STATUS_CAP |
4166 WD_TIMEOUT_CAP);
4167 cap_reg = get_bp_prod_caps(pbpctl_dev);
4168
4169 if ((cap_reg & NORMAL_UNSUPPORT_MASK) ==
4170 NORMAL_UNSUPPORT_MASK)
4171 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4172 else
4173 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4174
4175 if ((normal_support(pbpctl_dev)) == 1)
4176
4177 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4178
4179 else
4180 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4181 if ((cap_reg & BYPASS_SUPPORT_MASK) ==
4182 BYPASS_SUPPORT_MASK) {
4183 pbpctl_dev->bp_caps |=
4184 (BP_CAP | BP_STATUS_CAP |
4185 BP_STATUS_CHANGE_CAP | BP_DIS_CAP |
4186 BP_DIS_STATUS_CAP | BP_PWUP_ON_CAP |
4187 BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP);
4188 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER7)
4189 pbpctl_dev->bp_caps |=
4190 BP_PWOFF_ON_CAP | BP_PWOFF_OFF_CAP |
4191 BP_PWOFF_CTL_CAP;
4192 }
4193 if ((cap_reg & TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) {
4194 pbpctl_dev->bp_caps |=
4195 (TAP_CAP | TAP_STATUS_CAP |
4196 TAP_STATUS_CHANGE_CAP | TAP_DIS_CAP |
4197 TAP_DIS_STATUS_CAP | TAP_PWUP_ON_CAP |
4198 TAP_PWUP_OFF_CAP | TAP_PWUP_CTL_CAP);
4199 }
4200 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4201 if ((cap_reg & DISC_SUPPORT_MASK) ==
4202 DISC_SUPPORT_MASK)
4203 pbpctl_dev->bp_caps |=
4204 (DISC_CAP | DISC_DIS_CAP |
4205 DISC_PWUP_CTL_CAP);
4206 if ((cap_reg & TPL2_SUPPORT_MASK) ==
4207 TPL2_SUPPORT_MASK) {
4208 pbpctl_dev->bp_caps_ex |= TPL2_CAP_EX;
4209 pbpctl_dev->bp_caps |= TPL_CAP;
4210 pbpctl_dev->bp_tpl_flag =
4211 tpl2_flag_status(pbpctl_dev);
4212 }
4213
4214 }
4215
4216 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER9) {
4217 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4218 DISC_PORT_SUPPORT_MASK) {
4219 pbpctl_dev->bp_caps_ex |=
4220 DISC_PORT_CAP_EX;
4221 pbpctl_dev->bp_caps |=
4222 (TX_CTL_CAP | TX_STATUS_CAP);
4223 }
4224
4225 }
4226
4227 }
4228 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4229 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
4230 WDT_EN_MASK)
4231 pbpctl_dev->wdt_status = WDT_STATUS_EN;
4232 else
4233 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
4234 }
4235
4236 } else if ((P2BPFI_IF_SERIES(pbpctl_dev->subdevice)) ||
4237 (PEGF5_IF_SERIES(pbpctl_dev->subdevice)) ||
4238 (PEGF80_IF_SERIES(pbpctl_dev->subdevice)) ||
4239 (BP10G9_IF_SERIES(pbpctl_dev->subdevice))) {
4240 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4241 }
4242 if ((pbpctl_dev->subdevice & 0xa00) == 0xa00)
4243 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4244 if (PEG5_IF_SERIES(pbpctl_dev->subdevice))
4245 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4246
4247 if (BP10GB_IF_SERIES(pbpctl_dev->subdevice)) {
4248 pbpctl_dev->bp_caps &= ~(TX_CTL_CAP | TX_STATUS_CAP);
4249 }
4250 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4251 if (pbpctl_dev_m != NULL) {
4252 int cap_reg = 0;
4253 if (pbpctl_dev_m->bp_ext_ver >= 0x9) {
4254 cap_reg = get_bp_prod_caps(pbpctl_dev_m);
4255 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4256 DISC_PORT_SUPPORT_MASK)
4257 pbpctl_dev->bp_caps |=
4258 (TX_CTL_CAP | TX_STATUS_CAP);
4259 pbpctl_dev->bp_caps_ex |= DISC_PORT_CAP_EX;
4260 }
4261 }
4262}
4263
9f7a6f33 4264int bypass_off_init(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4265{
4266 int ret = 0;
4267
4268 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4269 return ret;
4270 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
7935c80c 4271 return dis_bypass_cap(pbpctl_dev);
7040e556
D		 4272 wdt_off(pbpctl_dev);
4273 if (pbpctl_dev->bp_caps & BP_CAP)
4274 bypass_off(pbpctl_dev);
4275 if (pbpctl_dev->bp_caps & TAP_CAP)
4276 tap_off(pbpctl_dev);
4277 cmnd_off(pbpctl_dev);
4278 return 0;
4279}
4280
9f7a6f33 4281void remove_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4282{
4283#ifdef BP_SELF_TEST
4284 bpctl_dev_t *pbpctl_dev_sl = NULL;
4285#endif
4286
4287 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4288
4289 del_timer_sync(&pbpctl_dev->bp_timer);
4290#ifdef BP_SELF_TEST
4291 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
7040e556
D		 4292 if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)) {
4293 if ((pbpctl_dev_sl->ndev->netdev_ops)
4294 && (pbpctl_dev_sl->old_ops)) {
4295 rtnl_lock();
4296 pbpctl_dev_sl->ndev->netdev_ops =
4297 pbpctl_dev_sl->old_ops;
4298 pbpctl_dev_sl->old_ops = NULL;
4299
4300 rtnl_unlock();
4301
4302 }
4303
4304 }
7040e556
D		 4305#endif
4306 }
4307
4308}
4309
9f7a6f33 4310int init_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4311{
4312 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4313 init_timer(&pbpctl_dev->bp_timer);
4314 pbpctl_dev->bp_timer.function = &wd_reset_timer;
4315 pbpctl_dev->bp_timer.data = (unsigned long)pbpctl_dev;
4316 return 1;
4317 }
4318 return BP_NOT_CAP;
4319}
4320
4321#ifdef BP_SELF_TEST
4322int bp_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
4323{
4324 bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
4325 int idx_dev = 0;
4326 struct ethhdr *eth = (struct ethhdr *)skb->data;
4327
4328 for (idx_dev = 0;
4329 ((bpctl_dev_arr[idx_dev].ndev != NULL) && (idx_dev < device_num));
4330 idx_dev++) {
4331 if (bpctl_dev_arr[idx_dev].ndev == dev) {
4332 pbpctl_dev = &bpctl_dev_arr[idx_dev];
4333 break;
4334 }
4335 }
4336 if (!pbpctl_dev)
4337 return 1;
4338 if ((htons(ETH_P_BPTEST) == eth->h_proto)) {
4339
4340 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4341 if (pbpctl_dev_m) {
4342
4343 if (bypass_status(pbpctl_dev_m)) {
4344 cmnd_on(pbpctl_dev_m);
4345 bypass_off(pbpctl_dev_m);
4346 cmnd_off(pbpctl_dev_m);
4347 }
4348 wdt_timer_reload(pbpctl_dev_m);
4349 }
4350 dev_kfree_skb_irq(skb);
4351 return 0;
4352 }
7935c80c 4353 return pbpctl_dev->hard_start_xmit_save(skb, dev);
7040e556
D		 4354}
4355#endif
4356
9f7a6f33 4357int set_bypass_wd_auto(bpctl_dev_t *pbpctl_dev, unsigned int param)
7040e556
D		 4358{
4359 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4360 if (pbpctl_dev->reset_time != param) {
4361 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4362 pbpctl_dev->reset_time =
4363 (param <
4364 WDT_AUTO_MIN_INT) ? WDT_AUTO_MIN_INT :
4365 param;
4366 else
4367 pbpctl_dev->reset_time = param;
4368 if (param)
4369 mod_timer(&pbpctl_dev->bp_timer, jiffies);
4370 }
4371 return 0;
4372 }
4373 return BP_NOT_CAP;
4374}
4375
9f7a6f33 4376int get_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4377{
4378
4379 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4380 return pbpctl_dev->reset_time;
4381 }
4382 return BP_NOT_CAP;
4383}
4384
4385#ifdef BP_SELF_TEST
4386
9f7a6f33 4387int set_bp_self_test(bpctl_dev_t *pbpctl_dev, unsigned int param)
7040e556
D		 4388{
4389 bpctl_dev_t *pbpctl_dev_sl = NULL;
4390
4391 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4392 pbpctl_dev->bp_self_test_flag = param == 0 ? 0 : 1;
4393 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
7040e556 4394
7040e556
D		 4395 if ((pbpctl_dev_sl->ndev) && (pbpctl_dev_sl->ndev->netdev_ops)) {
4396 rtnl_lock();
4397 if (pbpctl_dev->bp_self_test_flag == 1) {
4398
4399 pbpctl_dev_sl->old_ops =
4400 pbpctl_dev_sl->ndev->netdev_ops;
4401 pbpctl_dev_sl->new_ops =
4402 *pbpctl_dev_sl->old_ops;
4403 pbpctl_dev_sl->new_ops.ndo_start_xmit =
4404 bp_hard_start_xmit;
4405 pbpctl_dev_sl->ndev->netdev_ops =
4406 &pbpctl_dev_sl->new_ops;
4407
4408 } else if (pbpctl_dev_sl->old_ops) {
4409 pbpctl_dev_sl->ndev->netdev_ops =
4410 pbpctl_dev_sl->old_ops;
4411 pbpctl_dev_sl->old_ops = NULL;
4412 }
4413 rtnl_unlock();
4414 }
7040e556
D		 4415
4416 set_bypass_wd_auto(pbpctl_dev, param);
4417 return 0;
4418 }
4419 return BP_NOT_CAP;
4420}
4421
9f7a6f33 4422int get_bp_self_test(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4423{
4424
4425 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4426 if (pbpctl_dev->bp_self_test_flag == 1)
4427 return pbpctl_dev->reset_time;
4428 else
4429 return 0;
4430 }
4431 return BP_NOT_CAP;
4432}
4433
4434#endif
4435
4436/**************************************************************/
4437/************************* API ********************************/
4438/**************************************************************/
4439
9f7a6f33 4440int is_bypass_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4441{
4442 if (!pbpctl_dev)
4443 return -1;
4444
4445 return (((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) ? 1 : 0);
4446}
4447
9f7a6f33 4448int set_bypass_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
7040e556
D		 4449{
4450 int ret = 0;
4451
4452 if (!(pbpctl_dev->bp_caps & BP_CAP))
4453 return BP_NOT_CAP;
4454 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4455 return ret;
4456 if (!bypass_mode)
4457 ret = bypass_off(pbpctl_dev);
4458 else
4459 ret = bypass_on(pbpctl_dev);
4460 cmnd_off(pbpctl_dev);
4461
4462 return ret;
4463}
4464
9f7a6f33 4465int get_bypass_fn(bpctl_dev_t *pbpctl_dev)
7040e556 4466{
7935c80c 4467 return bypass_status(pbpctl_dev);
7040e556
D		 4468}
4469
9f7a6f33 4470int get_bypass_change_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4471{
4472 if (!pbpctl_dev)
4473 return -1;
4474
7935c80c 4475 return bypass_change_status(pbpctl_dev);
7040e556
D		 4476}
4477
9f7a6f33 4478int set_dis_bypass_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
7040e556
D		 4479{
4480 int ret = 0;
4481 if (!pbpctl_dev)
4482 return -1;
4483
4484 if (!(pbpctl_dev->bp_caps & BP_DIS_CAP))
4485 return BP_NOT_CAP;
4486 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4487 return ret;
4488 if (dis_param)
4489 ret = dis_bypass_cap(pbpctl_dev);
4490 else
4491 ret = en_bypass_cap(pbpctl_dev);
4492 cmnd_off(pbpctl_dev);
4493 return ret;
4494}
4495
9f7a6f33 4496int get_dis_bypass_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4497{
4498 if (!pbpctl_dev)
4499 return -1;
4500
7935c80c 4501 return dis_bypass_cap_status(pbpctl_dev);
7040e556
D		 4502}
4503
9f7a6f33 4504int set_bypass_pwoff_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
7040e556
D		 4505{
4506 int ret = 0;
4507 if (!pbpctl_dev)
4508 return -1;
4509
4510 if (!(pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP))
4511 return BP_NOT_CAP;
4512 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4513 return ret;
4514 if (bypass_mode)
4515 ret = bypass_state_pwroff(pbpctl_dev);
4516 else
4517 ret = normal_state_pwroff(pbpctl_dev);
4518 cmnd_off(pbpctl_dev);
4519 return ret;
4520}
4521
9f7a6f33 4522int get_bypass_pwoff_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4523{
4524 if (!pbpctl_dev)
4525 return -1;
4526
7935c80c 4527 return default_pwroff_status(pbpctl_dev);
7040e556
D		 4528}
4529
9f7a6f33 4530int set_bypass_pwup_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
7040e556
D		 4531{
4532 int ret = 0;
4533 if (!pbpctl_dev)
4534 return -1;
4535
4536 if (!(pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP))
4537 return BP_NOT_CAP;
4538 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4539 return ret;
4540 if (bypass_mode)
4541 ret = bypass_state_pwron(pbpctl_dev);
4542 else
4543 ret = normal_state_pwron(pbpctl_dev);
4544 cmnd_off(pbpctl_dev);
4545 return ret;
4546}
4547
9f7a6f33 4548int get_bypass_pwup_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4549{
4550 if (!pbpctl_dev)
4551 return -1;
4552
7935c80c 4553 return default_pwron_status(pbpctl_dev);
7040e556
D		 4554}
4555
9f7a6f33 4556int set_bypass_wd_fn(bpctl_dev_t *pbpctl_dev, int timeout)
7040e556
D		 4557{
4558 int ret = 0;
4559 if (!pbpctl_dev)
4560 return -1;
4561
4562 if (!(pbpctl_dev->bp_caps & WD_CTL_CAP))
4563 return BP_NOT_CAP;
4564
4565 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4566 return ret;
4567 if (!timeout)
4568 ret = wdt_off(pbpctl_dev);
4569 else {
4570 wdt_on(pbpctl_dev, timeout);
4571 ret = pbpctl_dev->bypass_timer_interval;
4572 }
4573 cmnd_off(pbpctl_dev);
4574 return ret;
4575}
4576
9f7a6f33 4577int get_bypass_wd_fn(bpctl_dev_t *pbpctl_dev, int *timeout)
7040e556
D		 4578{
4579 if (!pbpctl_dev)
4580 return -1;
4581
4582 return wdt_programmed(pbpctl_dev, timeout);
4583}
4584
9f7a6f33 4585int get_wd_expire_time_fn(bpctl_dev_t *pbpctl_dev, int *time_left)
7040e556
D		 4586{
4587 if (!pbpctl_dev)
4588 return -1;
4589
7935c80c 4590 return wdt_timer(pbpctl_dev, time_left);
7040e556
D		 4591}
4592
9f7a6f33 4593int reset_bypass_wd_timer_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4594{
4595 if (!pbpctl_dev)
4596 return -1;
4597
7935c80c 4598 return wdt_timer_reload(pbpctl_dev);
7040e556
D		 4599}
4600
9f7a6f33 4601int get_wd_set_caps_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4602{
4603 int bp_status = 0;
4604
4605 unsigned int step_value = TIMEOUT_MAX_STEP + 1, bit_cnt = 0;
4606 if (!pbpctl_dev)
4607 return -1;
4608
4609 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4610 return BP_NOT_CAP;
4611
4612 while ((step_value >>= 1))
4613 bit_cnt++;
4614
4615 if (is_bypass_fn(pbpctl_dev)) {
4616 bp_status =
4617 WD_STEP_COUNT_MASK(bit_cnt) | WDT_STEP_TIME |
4618 WD_MIN_TIME_MASK(TIMEOUT_UNIT / 100);
4619 } else
4620 return -1;
4621
4622 return bp_status;
4623}
4624
9f7a6f33 4625int set_std_nic_fn(bpctl_dev_t *pbpctl_dev, int nic_mode)
7040e556
D		 4626{
4627 int ret = 0;
4628 if (!pbpctl_dev)
4629 return -1;
4630
4631 if (!(pbpctl_dev->bp_caps & STD_NIC_CAP))
4632 return BP_NOT_CAP;
4633
4634 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4635 return ret;
4636 if (nic_mode)
4637 ret = std_nic_on(pbpctl_dev);
4638 else
4639 ret = std_nic_off(pbpctl_dev);
4640 cmnd_off(pbpctl_dev);
4641 return ret;
4642}
4643
9f7a6f33 4644int get_std_nic_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4645{
4646 if (!pbpctl_dev)
4647 return -1;
4648
7935c80c 4649 return std_nic_status(pbpctl_dev);
7040e556
D		 4650}
4651
9f7a6f33 4652int set_tap_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
7040e556
D		 4653{
4654 if (!pbpctl_dev)
4655 return -1;
4656
4657 if ((pbpctl_dev->bp_caps & TAP_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4658 if (!tap_mode)
4659 tap_off(pbpctl_dev);
4660 else
4661 tap_on(pbpctl_dev);
4662 cmnd_off(pbpctl_dev);
4663 return 0;
4664 }
4665 return BP_NOT_CAP;
4666}
4667
9f7a6f33 4668int get_tap_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4669{
4670 if (!pbpctl_dev)
4671 return -1;
4672
7935c80c 4673 return tap_status(pbpctl_dev);
7040e556
D		 4674}
4675
9f7a6f33 4676int set_tap_pwup_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
7040e556
D		 4677{
4678 int ret = 0;
4679 if (!pbpctl_dev)
4680 return -1;
4681
4682 if ((pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)
4683 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4684 if (tap_mode)
4685 ret = tap_state_pwron(pbpctl_dev);
4686 else
4687 ret = normal_state_pwron(pbpctl_dev);
4688 cmnd_off(pbpctl_dev);
4689 } else
4690 ret = BP_NOT_CAP;
4691 return ret;
4692}
4693
9f7a6f33 4694int get_tap_pwup_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4695{
4696 int ret = 0;
4697 if (!pbpctl_dev)
4698 return -1;
4699
4700 if ((ret = default_pwron_tap_status(pbpctl_dev)) < 0)
4701 return ret;
4702 return ((ret == 0) ? 1 : 0);
4703}
4704
9f7a6f33 4705int get_tap_change_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4706{
4707 if (!pbpctl_dev)
4708 return -1;
4709
7935c80c 4710 return tap_change_status(pbpctl_dev);
7040e556
D		 4711}
4712
9f7a6f33 4713int set_dis_tap_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
7040e556
D		 4714{
4715 int ret = 0;
4716 if (!pbpctl_dev)
4717 return -1;
4718
4719 if ((pbpctl_dev->bp_caps & TAP_DIS_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4720 if (dis_param)
4721 ret = dis_tap_cap(pbpctl_dev);
4722 else
4723 ret = en_tap_cap(pbpctl_dev);
4724 cmnd_off(pbpctl_dev);
4725 return ret;
4726 } else
4727 return BP_NOT_CAP;
4728}
4729
9f7a6f33 4730int get_dis_tap_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4731{
4732 if (!pbpctl_dev)
4733 return -1;
4734
7935c80c 4735 return dis_tap_cap_status(pbpctl_dev);
7040e556
D		 4736}
4737
9f7a6f33 4738int set_disc_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
7040e556
D		 4739{
4740 if (!pbpctl_dev)
4741 return -1;
4742
4743 if ((pbpctl_dev->bp_caps & DISC_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4744 if (!disc_mode)
4745 disc_off(pbpctl_dev);
4746 else
4747 disc_on(pbpctl_dev);
4748 cmnd_off(pbpctl_dev);
4749
4750 return BP_OK;
4751 }
4752 return BP_NOT_CAP;
4753}
4754
9f7a6f33 4755int get_disc_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4756{
4757 int ret = 0;
4758 if (!pbpctl_dev)
4759 return -1;
4760
4761 ret = disc_status(pbpctl_dev);
4762
4763 return ret;
4764}
4765
9f7a6f33 4766int set_disc_pwup_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
7040e556
D		 4767{
4768 int ret = 0;
4769 if (!pbpctl_dev)
4770 return -1;
4771
4772 if ((pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP)
4773 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4774 if (disc_mode)
4775 ret = disc_state_pwron(pbpctl_dev);
4776 else
4777 ret = normal_state_pwron(pbpctl_dev);
4778 cmnd_off(pbpctl_dev);
4779 } else
4780 ret = BP_NOT_CAP;
4781 return ret;
4782}
4783
9f7a6f33 4784int get_disc_pwup_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4785{
4786 int ret = 0;
4787 if (!pbpctl_dev)
4788 return -1;
4789
4790 ret = default_pwron_disc_status(pbpctl_dev);
4791 return (ret == 0 ? 1 : (ret < 0 ? BP_NOT_CAP : 0));
4792}
4793
7c014321 4794int get_disc_change_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4795{
4796 int ret = 0;
4797 if (!pbpctl_dev)
4798 return -1;
4799
4800 ret = disc_change_status(pbpctl_dev);
4801 return ret;
4802}
4803
7c014321 4804int set_dis_disc_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
7040e556
D		 4805{
4806 int ret = 0;
4807 if (!pbpctl_dev)
4808 return -1;
4809
4810 if ((pbpctl_dev->bp_caps & DISC_DIS_CAP)
4811 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4812 if (dis_param)
4813 ret = dis_disc_cap(pbpctl_dev);
4814 else
4815 ret = en_disc_cap(pbpctl_dev);
4816 cmnd_off(pbpctl_dev);
4817 return ret;
4818 } else
4819 return BP_NOT_CAP;
4820}
4821
7c014321 4822int get_dis_disc_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4823{
4824 int ret = 0;
4825 if (!pbpctl_dev)
4826 return -1;
4827
4828 ret = dis_disc_cap_status(pbpctl_dev);
4829
4830 return ret;
4831}
4832
7c014321 4833int set_disc_port_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
7040e556
D		 4834{
4835 int ret = BP_NOT_CAP;
4836 if (!pbpctl_dev)
4837 return -1;
4838
4839 if (!disc_mode)
4840 ret = disc_port_off(pbpctl_dev);
4841 else
4842 ret = disc_port_on(pbpctl_dev);
4843
4844 return ret;
4845}
4846
7c014321 4847int get_disc_port_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4848{
4849 if (!pbpctl_dev)
4850 return -1;
4851
7935c80c 4852 return disc_port_status(pbpctl_dev);
7040e556
D		 4853}
4854
7c014321 4855int set_disc_port_pwup_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
7040e556
D		 4856{
4857 int ret = BP_NOT_CAP;
4858 if (!pbpctl_dev)
4859 return -1;
4860
4861 if (!disc_mode)
4862 ret = normal_port_state_pwron(pbpctl_dev);
4863 else
4864 ret = disc_port_state_pwron(pbpctl_dev);
4865
4866 return ret;
4867}
4868
7c014321 4869int get_disc_port_pwup_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4870{
4871 int ret = 0;
4872 if (!pbpctl_dev)
4873 return -1;
4874
4875 if ((ret = default_pwron_disc_port_status(pbpctl_dev)) < 0)
4876 return ret;
4877 return ((ret == 0) ? 1 : 0);
4878}
4879
7c014321 4880int get_wd_exp_mode_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4881{
4882 if (!pbpctl_dev)
4883 return -1;
4884
7935c80c 4885 return wdt_exp_mode_status(pbpctl_dev);
7040e556
D		 4886}
4887
7c014321 4888int set_wd_exp_mode_fn(bpctl_dev_t *pbpctl_dev, int param)
7040e556
D		 4889{
4890 if (!pbpctl_dev)
4891 return -1;
4892
7935c80c 4893 return wdt_exp_mode(pbpctl_dev, param);
7040e556
D		 4894}
4895
7c014321 4896int reset_cont_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4897{
4898 int ret = 0;
4899 if (!pbpctl_dev)
4900 return -1;
4901
4902 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4903 return ret;
7935c80c 4904 return reset_cont(pbpctl_dev);
7040e556
D		 4905}
4906
7c014321 4907int set_tx_fn(bpctl_dev_t *pbpctl_dev, int tx_state)
7040e556
D		 4908{
4909
4910 bpctl_dev_t *pbpctl_dev_b = NULL;
4911 if (!pbpctl_dev)
4912 return -1;
4913
4914 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4915 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4916 if ((pbpctl_dev->bp_tpl_flag))
4917 return BP_NOT_CAP;
4918 } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
4919 if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
4920 (pbpctl_dev_b->bp_tpl_flag))
4921 return BP_NOT_CAP;
4922 }
7935c80c 4923 return set_tx(pbpctl_dev, tx_state);
7040e556
D		 4924}
4925
4926int set_bp_force_link_fn(int dev_num, int tx_state)
4927{
4928 static bpctl_dev_t *bpctl_dev_curr;
4929
4930 if ((dev_num < 0) || (dev_num > device_num)
4931 || (bpctl_dev_arr[dev_num].pdev == NULL))
4932 return -1;
4933 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
4934
7935c80c 4935 return set_bp_force_link(bpctl_dev_curr, tx_state);
7040e556
D		 4936}
4937
7c014321 4938int set_wd_autoreset_fn(bpctl_dev_t *pbpctl_dev, int param)
7040e556
D		 4939{
4940 if (!pbpctl_dev)
4941 return -1;
4942
7935c80c 4943 return set_bypass_wd_auto(pbpctl_dev, param);
7040e556
D		 4944}
4945
7c014321 4946int get_wd_autoreset_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4947{
4948 if (!pbpctl_dev)
4949 return -1;
4950
7935c80c 4951 return get_bypass_wd_auto(pbpctl_dev);
7040e556
D		 4952}
4953
4954#ifdef BP_SELF_TEST
7c014321 4955int set_bp_self_test_fn(bpctl_dev_t *pbpctl_dev, int param)
7040e556
D		 4956{
4957 if (!pbpctl_dev)
4958 return -1;
4959
7935c80c 4960 return set_bp_self_test(pbpctl_dev, param);
7040e556
D		 4961}
4962
7c014321 4963int get_bp_self_test_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4964{
4965 if (!pbpctl_dev)
4966 return -1;
4967
7935c80c 4968 return get_bp_self_test(pbpctl_dev);
7040e556
D		 4969}
4970
4971#endif
4972
7c014321 4973int get_bypass_caps_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4974{
4975 if (!pbpctl_dev)
4976 return -1;
4977
7935c80c 4978 return pbpctl_dev->bp_caps;
7040e556
D		 4979
4980}
4981
7c014321 4982int get_bypass_slave_fn(bpctl_dev_t *pbpctl_dev, bpctl_dev_t **pbpctl_dev_out)
7040e556
D		 4983{
4984 int idx_dev = 0;
4985 if (!pbpctl_dev)
4986 return -1;
4987
4988 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
4989 for (idx_dev = 0;
4990 ((bpctl_dev_arr[idx_dev].pdev != NULL)
4991 && (idx_dev < device_num)); idx_dev++) {
4992 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
4993 && (bpctl_dev_arr[idx_dev].slot ==
4994 pbpctl_dev->slot)) {
4995 if ((pbpctl_dev->func == 0)
4996 && (bpctl_dev_arr[idx_dev].func == 1)) {
4997 *pbpctl_dev_out =
4998 &bpctl_dev_arr[idx_dev];
4999 return 1;
5000 }
5001 if ((pbpctl_dev->func == 2) &&
5002 (bpctl_dev_arr[idx_dev].func == 3)) {
5003 *pbpctl_dev_out =
5004 &bpctl_dev_arr[idx_dev];
5005 return 1;
5006 }
5007 }
5008 }
5009 return -1;
5010 } else
5011 return 0;
5012}
5013
7c014321 5014int is_bypass(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5015{
5016 if (!pbpctl_dev)
5017 return -1;
5018
5019 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2))
5020 return 1;
5021 else
5022 return 0;
5023}
5024
7c014321 5025int get_tx_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5026{
5027 bpctl_dev_t *pbpctl_dev_b = NULL;
5028 if (!pbpctl_dev)
5029 return -1;
5030
5031 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
5032 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
5033 if ((pbpctl_dev->bp_tpl_flag))
5034 return BP_NOT_CAP;
5035 } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
5036 if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
5037 (pbpctl_dev_b->bp_tpl_flag))
5038 return BP_NOT_CAP;
5039 }
7935c80c 5040 return tx_status(pbpctl_dev);
7040e556
D		 5041}
5042
5043int get_bp_force_link_fn(int dev_num)
5044{
5045 static bpctl_dev_t *bpctl_dev_curr;
5046
5047 if ((dev_num < 0) || (dev_num > device_num)
5048 || (bpctl_dev_arr[dev_num].pdev == NULL))
5049 return -1;
5050 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
5051
7935c80c 5052 return bp_force_link_status(bpctl_dev_curr);
7040e556
D		 5053}
5054
7c014321 5055static int get_bypass_link_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5056{
5057 if (!pbpctl_dev)
5058 return -1;
5059
5060 if (pbpctl_dev->media_type == bp_fiber)
5061 return ((BPCTL_READ_REG(pbpctl_dev, CTRL) &
5062 BPCTLI_CTRL_SWDPIN1));
5063 else
5064 return ((BPCTL_READ_REG(pbpctl_dev, STATUS) &
5065 BPCTLI_STATUS_LU));
5066
5067}
5068
5069static void bp_tpl_timer_fn(unsigned long param)
5070{
5071 bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
5072 uint32_t link1, link2;
5073 bpctl_dev_t *pbpctl_dev_b = NULL;
5074
5075 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5076 return;
5077
5078 if (!pbpctl_dev->bp_tpl_flag) {
5079 set_tx(pbpctl_dev_b, 1);
5080 set_tx(pbpctl_dev, 1);
5081 return;
5082 }
5083 link1 = get_bypass_link_status(pbpctl_dev);
5084
5085 link2 = get_bypass_link_status(pbpctl_dev_b);
5086 if ((link1) && (tx_status(pbpctl_dev))) {
5087 if ((!link2) && (tx_status(pbpctl_dev_b))) {
5088 set_tx(pbpctl_dev, 0);
5089 } else if (!tx_status(pbpctl_dev_b)) {
5090 set_tx(pbpctl_dev_b, 1);
5091 }
5092 } else if ((!link1) && (tx_status(pbpctl_dev))) {
5093 if ((link2) && (tx_status(pbpctl_dev_b))) {
5094 set_tx(pbpctl_dev_b, 0);
5095 }
5096 } else if ((link1) && (!tx_status(pbpctl_dev))) {
5097 if ((link2) && (tx_status(pbpctl_dev_b))) {
5098 set_tx(pbpctl_dev, 1);
5099 }
5100 } else if ((!link1) && (!tx_status(pbpctl_dev))) {
5101 if ((link2) && (tx_status(pbpctl_dev_b))) {
5102 set_tx(pbpctl_dev, 1);
5103 }
5104 }
5105
5106 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + BP_LINK_MON_DELAY * HZ);
5107}
5108
7c014321 5109void remove_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5110{
5111 bpctl_dev_t *pbpctl_dev_b = NULL;
5112 if (!pbpctl_dev)
5113 return;
5114 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5115
5116 if (pbpctl_dev->bp_caps & TPL_CAP) {
5117 del_timer_sync(&pbpctl_dev->bp_tpl_timer);
5118 pbpctl_dev->bp_tpl_flag = 0;
5119 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5120 if (pbpctl_dev_b)
5121 set_tx(pbpctl_dev_b, 1);
5122 set_tx(pbpctl_dev, 1);
5123 }
5124 return;
5125}
5126
7c014321 5127int init_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5128{
5129 if (!pbpctl_dev)
5130 return -1;
5131 if (pbpctl_dev->bp_caps & TPL_CAP) {
5132 init_timer(&pbpctl_dev->bp_tpl_timer);
5133 pbpctl_dev->bp_tpl_timer.function = &bp_tpl_timer_fn;
5134 pbpctl_dev->bp_tpl_timer.data = (unsigned long)pbpctl_dev;
5135 return BP_OK;
5136 }
5137 return BP_NOT_CAP;
5138}
5139
7c014321 5140int set_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev, unsigned int param)
7040e556
D		 5141{
5142 if (!pbpctl_dev)
5143 return -1;
5144 if (pbpctl_dev->bp_caps & TPL_CAP) {
5145 if ((param) && (!pbpctl_dev->bp_tpl_flag)) {
5146 pbpctl_dev->bp_tpl_flag = param;
5147 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + 1);
5148 return BP_OK;
5149 };
5150 if ((!param) && (pbpctl_dev->bp_tpl_flag))
5151 remove_bypass_tpl_auto(pbpctl_dev);
5152
5153 return BP_OK;
5154 }
5155 return BP_NOT_CAP;
5156}
5157
7c014321 5158int get_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5159{
5160 if (!pbpctl_dev)
5161 return -1;
5162 if (pbpctl_dev->bp_caps & TPL_CAP) {
5163 return pbpctl_dev->bp_tpl_flag;
5164 }
5165 return BP_NOT_CAP;
5166}
5167
7c014321 5168int set_tpl_fn(bpctl_dev_t *pbpctl_dev, int tpl_mode)
7040e556
D		 5169{
5170
5171 bpctl_dev_t *pbpctl_dev_b = NULL;
5172 if (!pbpctl_dev)
5173 return -1;
5174
5175 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5176
5177 if (pbpctl_dev->bp_caps & TPL_CAP) {
5178 if (tpl_mode) {
5179 if ((pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5180 set_tx(pbpctl_dev_b, 1);
5181 set_tx(pbpctl_dev, 1);
5182 }
5183 if ((TPL_IF_SERIES(pbpctl_dev->subdevice)) ||
5184 (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)) {
5185 pbpctl_dev->bp_tpl_flag = tpl_mode;
5186 if (!tpl_mode)
5187 tpl_hw_off(pbpctl_dev);
5188 else
5189 tpl_hw_on(pbpctl_dev);
5190 } else
5191 set_bypass_tpl_auto(pbpctl_dev, tpl_mode);
5192 return 0;
5193 }
5194 return BP_NOT_CAP;
5195}
5196
7c014321 5197int get_tpl_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5198{
5199 int ret = BP_NOT_CAP;
5200 if (!pbpctl_dev)
5201 return -1;
5202
5203 if (pbpctl_dev->bp_caps & TPL_CAP) {
5204 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)
7935c80c 5205 return tpl2_flag_status(pbpctl_dev);
7040e556
D		 5206 ret = pbpctl_dev->bp_tpl_flag;
5207 }
5208 return ret;
5209}
5210
7c014321 5211int set_bp_wait_at_pwup_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
7040e556
D		 5212{
5213 if (!pbpctl_dev)
5214 return -1;
5215
5216 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
687bcca0 5217 /* bp_lock(pbp_device_block); */
7040e556
D		 5218 cmnd_on(pbpctl_dev);
5219 if (!tap_mode)
5220 bp_wait_at_pwup_dis(pbpctl_dev);
5221 else
5222 bp_wait_at_pwup_en(pbpctl_dev);
5223 cmnd_off(pbpctl_dev);
5224
687bcca0 5225 /* bp_unlock(pbp_device_block); */
7040e556
D		 5226 return BP_OK;
5227 }
5228 return BP_NOT_CAP;
5229}
5230
7c014321 5231int get_bp_wait_at_pwup_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5232{
5233 int ret = 0;
5234 if (!pbpctl_dev)
5235 return -1;
5236
687bcca0 5237 /* bp_lock(pbp_device_block); */
7040e556 5238 ret = bp_wait_at_pwup_status(pbpctl_dev);
687bcca0 5239 /* bp_unlock(pbp_device_block); */
7040e556
D		 5240
5241 return ret;
5242}
5243
7c014321 5244int set_bp_hw_reset_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
7040e556
D		 5245{
5246 if (!pbpctl_dev)
5247 return -1;
5248
5249 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
687bcca0 5250 /* bp_lock(pbp_device_block); */
7040e556
D		 5251 cmnd_on(pbpctl_dev);
5252
5253 if (!tap_mode)
5254 bp_hw_reset_dis(pbpctl_dev);
5255 else
5256 bp_hw_reset_en(pbpctl_dev);
5257 cmnd_off(pbpctl_dev);
687bcca0 5258 /* bp_unlock(pbp_device_block); */
7040e556
D		 5259 return BP_OK;
5260 }
5261 return BP_NOT_CAP;
5262}
5263
7c014321 5264int get_bp_hw_reset_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5265{
5266 int ret = 0;
5267 if (!pbpctl_dev)
5268 return -1;
5269
687bcca0 5270 /* bp_lock(pbp_device_block); */
7040e556
D		 5271 ret = bp_hw_reset_status(pbpctl_dev);
5272
687bcca0 5273 /* bp_unlock(pbp_device_block); */
7040e556
D		 5274
5275 return ret;
5276}
5277
7040e556 5278
7c014321 5279int get_bypass_info_fn(bpctl_dev_t *pbpctl_dev, char *dev_name,
7040e556
D		 5280 char *add_param)
5281{
5282 if (!pbpctl_dev)
5283 return -1;
5284 if (!is_bypass_fn(pbpctl_dev))
5285 return -1;
5286 strcpy(dev_name, pbpctl_dev->name);
5287 *add_param = pbpctl_dev->bp_fw_ver;
5288 return 0;
5289}
5290
5291int get_dev_idx_bsf(int bus, int slot, int func)
5292{
5293 int idx_dev = 0;
7040e556
D		 5294 for (idx_dev = 0;
5295 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5296 idx_dev++) {
5297 if ((bus == bpctl_dev_arr[idx_dev].bus)
5298 && (slot == bpctl_dev_arr[idx_dev].slot)
5299 && (func == bpctl_dev_arr[idx_dev].func))
5300
5301 return idx_dev;
5302 }
5303 return -1;
5304}
5305
5306static void str_low(char *str)
5307{
5308 int i;
5309
5310 for (i = 0; i < strlen(str); i++)
5311 if ((str[i] >= 65) && (str[i] <= 90))
5312 str[i] += 32;
5313}
5314
5315static unsigned long str_to_hex(char *p)
5316{
5317 unsigned long hex = 0;
5318 unsigned long length = strlen(p), shift = 0;
5319 unsigned char dig = 0;
5320
5321 str_low(p);
5322 length = strlen(p);
5323
5324 if (length == 0)
5325 return 0;
5326
5327 do {
5328 dig = p[--length];
5329 dig = dig < 'a' ? (dig - '0') : (dig - 'a' + 0xa);
5330 hex |= (dig << shift);
5331 shift += 4;
5332 } while (length);
5333 return hex;
5334}
5335
5336static int get_dev_idx(int ifindex)
5337{
5338 int idx_dev = 0;
5339
5340 for (idx_dev = 0;
5341 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5342 idx_dev++) {
5343 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5344 return idx_dev;
5345 }
5346
5347 return -1;
5348}
5349
5350static bpctl_dev_t *get_dev_idx_p(int ifindex)
5351{
5352 int idx_dev = 0;
5353
5354 for (idx_dev = 0;
5355 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5356 idx_dev++) {
5357 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5358 return &bpctl_dev_arr[idx_dev];
5359 }
5360
5361 return NULL;
5362}
5363
5364static void if_scan_init(void)
5365{
5366 int idx_dev = 0;
5367 struct net_device *dev;
5368 int ifindex;
687bcca0
DC		 5369 /* rcu_read_lock(); */
5370 /* rtnl_lock(); */
5371 /* rcu_read_lock(); */
3e4cce9d
CW		 5372
5373 for_each_netdev(&init_net, dev) {
7040e556
D		 5374
5375 struct ethtool_drvinfo drvinfo;
7040e556
D		 5376 char cbuf[32];
5377 char *buf = NULL;
5378 char res[10];
5379 int i = 0;
5380 int bus = 0, slot = 0, func = 0;
5381 ifindex = dev->ifindex;
5382
5383 memset(res, 0, 10);
5384 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
5385
5386 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5387 memset(&drvinfo, 0, sizeof(drvinfo));
5388 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5389 } else
5390 continue;
7040e556
D		 5391 if (!strcmp(drvinfo.bus_info, "N/A"))
5392 continue;
5393 memcpy(&cbuf, drvinfo.bus_info, 32);
5394 buf = &cbuf[0];
5395
7040e556
D		 5396 while (*buf++ != ':') ;
5397 for (i = 0; i < 10; i++, buf++) {
5398 if (*buf == ':')
5399 break;
5400 res[i] = *buf;
5401
5402 }
5403 buf++;
5404 bus = str_to_hex(res);
5405 memset(res, 0, 10);
5406
5407 for (i = 0; i < 10; i++, buf++) {
5408 if (*buf == '.')
5409 break;
5410 res[i] = *buf;
5411
5412 }
5413 buf++;
5414 slot = str_to_hex(res);
5415 func = str_to_hex(buf);
5416 idx_dev = get_dev_idx_bsf(bus, slot, func);
5417
5418 if (idx_dev != -1) {
5419
5420 bpctl_dev_arr[idx_dev].ifindex = ifindex;
5421 bpctl_dev_arr[idx_dev].ndev = dev;
5422
5423 }
5424
5425 }
687bcca0
DC		 5426 /* rtnl_unlock(); */
5427 /* rcu_read_unlock(); */
7040e556
D		 5428
5429}
5430
3e4cce9d 5431static long device_ioctl(struct file *file, /* see include/linux/fs.h */
7040e556
D		 5432 unsigned int ioctl_num, /* number and param for ioctl */
5433 unsigned long ioctl_param)
7040e556
D		 5434{
5435 struct bpctl_cmd bpctl_cmd;
5436 int dev_idx = 0;
5437 bpctl_dev_t *pbpctl_dev_out;
5438 void __user *argp = (void __user *)ioctl_param;
5439 int ret = 0;
5440 unsigned long flags;
5441
5442 static bpctl_dev_t *pbpctl_dev;
5443
687bcca0 5444 /* lock_kernel(); */
7040e556 5445 lock_bpctl();
687bcca0
DC		 5446 /* local_irq_save(flags); */
5447 /* if(!spin_trylock_irqsave(&bpvm_lock)){
7040e556 5448 local_irq_restore(flags);
687bcca0
DC		 5449 unlock_bpctl();
5450 unlock_kernel();
7040e556
D		 5451 return -1;
5452 } */
687bcca0 5453 /* spin_lock_irqsave(&bpvm_lock, flags); */
7040e556
D		 5454
5455/*
5456* Switch according to the ioctl called
5457*/
5458 if (ioctl_num == IOCTL_TX_MSG(IF_SCAN)) {
5459 if_scan_init();
5460 ret = SUCCESS;
5461 goto bp_exit;
5462 }
5463 if (copy_from_user(&bpctl_cmd, argp, sizeof(struct bpctl_cmd))) {
5464
5465 ret = -EFAULT;
5466 goto bp_exit;
5467 }
5468
5469 if (ioctl_num == IOCTL_TX_MSG(GET_DEV_NUM)) {
5470 bpctl_cmd.out_param[0] = device_num;
5471 if (copy_to_user
5472 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5473 ret = -EFAULT;
5474 goto bp_exit;
5475 }
5476 ret = SUCCESS;
5477 goto bp_exit;
5478
5479 }
687bcca0
DC		 5480 /* lock_bpctl(); */
5481 /* preempt_disable(); */
7040e556
D		 5482 local_irq_save(flags);
5483 if (!spin_trylock(&bpvm_lock)) {
5484 local_irq_restore(flags);
5485 unlock_bpctl();
7040e556
D		 5486 return -1;
5487 }
687bcca0
DC		 5488
5489/* preempt_disable();
5490 rcu_read_lock();
5491 spin_lock_irqsave(&bpvm_lock, flags);
5492*/
7040e556
D		 5493 if ((bpctl_cmd.in_param[5]) ||
5494 (bpctl_cmd.in_param[6]) || (bpctl_cmd.in_param[7]))
5495 dev_idx = get_dev_idx_bsf(bpctl_cmd.in_param[5],
5496 bpctl_cmd.in_param[6],
5497 bpctl_cmd.in_param[7]);
5498 else if (bpctl_cmd.in_param[1] == 0)
5499 dev_idx = bpctl_cmd.in_param[0];
5500 else
5501 dev_idx = get_dev_idx(bpctl_cmd.in_param[1]);
5502
5503 if (dev_idx < 0 || dev_idx > device_num) {
687bcca0
DC		 5504 /* unlock_bpctl();
5505 preempt_enable(); */
7040e556 5506 ret = -EOPNOTSUPP;
687bcca0
DC		 5507 /* preempt_enable();
5508 rcu_read_unlock(); */
7040e556
D		 5509 spin_unlock_irqrestore(&bpvm_lock, flags);
5510 goto bp_exit;
5511 }
5512
5513 bpctl_cmd.out_param[0] = bpctl_dev_arr[dev_idx].bus;
5514 bpctl_cmd.out_param[1] = bpctl_dev_arr[dev_idx].slot;
5515 bpctl_cmd.out_param[2] = bpctl_dev_arr[dev_idx].func;
5516 bpctl_cmd.out_param[3] = bpctl_dev_arr[dev_idx].ifindex;
5517
5518 if ((bpctl_dev_arr[dev_idx].bp_10gb)
5519 && (!(bpctl_dev_arr[dev_idx].ifindex))) {
5520 printk("Please load network driver for %s adapter!\n",
5521 bpctl_dev_arr[dev_idx].name);
5522 bpctl_cmd.status = -1;
5523 ret = SUCCESS;
687bcca0
DC		 5524 /* preempt_enable(); */
5525 /* rcu_read_unlock(); */
7040e556
D		 5526 spin_unlock_irqrestore(&bpvm_lock, flags);
5527 goto bp_exit;
5528
5529 }
5530 if ((bpctl_dev_arr[dev_idx].bp_10gb) && (bpctl_dev_arr[dev_idx].ndev)) {
5531 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5532 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5533 printk
5534 ("Please bring up network interfaces for %s adapter!\n",
5535 bpctl_dev_arr[dev_idx].name);
5536 bpctl_cmd.status = -1;
5537 ret = SUCCESS;
687bcca0
DC		 5538 /* preempt_enable(); */
5539 /* rcu_read_unlock(); */
7040e556
D		 5540 spin_unlock_irqrestore(&bpvm_lock, flags);
5541 goto bp_exit;
5542 }
5543
5544 }
5545 }
5546
5547 if ((dev_idx < 0) || (dev_idx > device_num)
5548 || (bpctl_dev_arr[dev_idx].pdev == NULL)) {
5549 bpctl_cmd.status = -1;
5550 goto bpcmd_exit;
5551 }
5552
5553 pbpctl_dev = &bpctl_dev_arr[dev_idx];
5554
5555 switch (ioctl_num) {
5556 case IOCTL_TX_MSG(SET_BYPASS_PWOFF):
5557 bpctl_cmd.status =
5558 set_bypass_pwoff_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5559 break;
5560
5561 case IOCTL_TX_MSG(GET_BYPASS_PWOFF):
5562 bpctl_cmd.status = get_bypass_pwoff_fn(pbpctl_dev);
5563 break;
5564
5565 case IOCTL_TX_MSG(SET_BYPASS_PWUP):
5566 bpctl_cmd.status =
5567 set_bypass_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5568 break;
5569
5570 case IOCTL_TX_MSG(GET_BYPASS_PWUP):
5571 bpctl_cmd.status = get_bypass_pwup_fn(pbpctl_dev);
5572 break;
5573
5574 case IOCTL_TX_MSG(SET_BYPASS_WD):
5575 bpctl_cmd.status =
5576 set_bypass_wd_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5577 break;
5578
5579 case IOCTL_TX_MSG(GET_BYPASS_WD):
5580 bpctl_cmd.status =
5581 get_bypass_wd_fn(pbpctl_dev, (int *)&(bpctl_cmd.data[0]));
5582 break;
5583
5584 case IOCTL_TX_MSG(GET_WD_EXPIRE_TIME):
5585 bpctl_cmd.status =
5586 get_wd_expire_time_fn(pbpctl_dev,
5587 (int *)&(bpctl_cmd.data[0]));
5588 break;
5589
5590 case IOCTL_TX_MSG(RESET_BYPASS_WD_TIMER):
5591 bpctl_cmd.status = reset_bypass_wd_timer_fn(pbpctl_dev);
5592 break;
5593
5594 case IOCTL_TX_MSG(GET_WD_SET_CAPS):
5595 bpctl_cmd.status = get_wd_set_caps_fn(pbpctl_dev);
5596 break;
5597
5598 case IOCTL_TX_MSG(SET_STD_NIC):
5599 bpctl_cmd.status =
5600 set_std_nic_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5601 break;
5602
5603 case IOCTL_TX_MSG(GET_STD_NIC):
5604 bpctl_cmd.status = get_std_nic_fn(pbpctl_dev);
5605 break;
5606
5607 case IOCTL_TX_MSG(SET_TAP):
5608 bpctl_cmd.status =
5609 set_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5610 break;
5611
5612 case IOCTL_TX_MSG(GET_TAP):
5613 bpctl_cmd.status = get_tap_fn(pbpctl_dev);
5614 break;
5615
5616 case IOCTL_TX_MSG(GET_TAP_CHANGE):
5617 bpctl_cmd.status = get_tap_change_fn(pbpctl_dev);
5618 break;
5619
5620 case IOCTL_TX_MSG(SET_DIS_TAP):
5621 bpctl_cmd.status =
5622 set_dis_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5623 break;
5624
5625 case IOCTL_TX_MSG(GET_DIS_TAP):
5626 bpctl_cmd.status = get_dis_tap_fn(pbpctl_dev);
5627 break;
5628
5629 case IOCTL_TX_MSG(SET_TAP_PWUP):
5630 bpctl_cmd.status =
5631 set_tap_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5632 break;
5633
5634 case IOCTL_TX_MSG(GET_TAP_PWUP):
5635 bpctl_cmd.status = get_tap_pwup_fn(pbpctl_dev);
5636 break;
5637
5638 case IOCTL_TX_MSG(SET_WD_EXP_MODE):
5639 bpctl_cmd.status =
5640 set_wd_exp_mode_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5641 break;
5642
5643 case IOCTL_TX_MSG(GET_WD_EXP_MODE):
5644 bpctl_cmd.status = get_wd_exp_mode_fn(pbpctl_dev);
5645 break;
5646
5647 case IOCTL_TX_MSG(GET_DIS_BYPASS):
5648 bpctl_cmd.status = get_dis_bypass_fn(pbpctl_dev);
5649 break;
5650
5651 case IOCTL_TX_MSG(SET_DIS_BYPASS):
5652 bpctl_cmd.status =
5653 set_dis_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5654 break;
5655
5656 case IOCTL_TX_MSG(GET_BYPASS_CHANGE):
5657 bpctl_cmd.status = get_bypass_change_fn(pbpctl_dev);
5658 break;
5659
5660 case IOCTL_TX_MSG(GET_BYPASS):
5661 bpctl_cmd.status = get_bypass_fn(pbpctl_dev);
5662 break;
5663
5664 case IOCTL_TX_MSG(SET_BYPASS):
5665 bpctl_cmd.status =
5666 set_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5667 break;
5668
5669 case IOCTL_TX_MSG(GET_BYPASS_CAPS):
5670 bpctl_cmd.status = get_bypass_caps_fn(pbpctl_dev);
5671 /*preempt_enable(); */
687bcca0 5672 /*rcu_read_unlock();*/
7040e556
D		 5673 spin_unlock_irqrestore(&bpvm_lock, flags);
5674 if (copy_to_user
5675 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
687bcca0
DC		 5676 /*unlock_bpctl(); */
5677 /*preempt_enable(); */
7040e556
D		 5678 ret = -EFAULT;
5679 goto bp_exit;
5680 }
5681 goto bp_exit;
5682
5683 case IOCTL_TX_MSG(GET_BYPASS_SLAVE):
5684 bpctl_cmd.status =
5685 get_bypass_slave_fn(pbpctl_dev, &pbpctl_dev_out);
5686 if (bpctl_cmd.status == 1) {
5687 bpctl_cmd.out_param[4] = pbpctl_dev_out->bus;
5688 bpctl_cmd.out_param[5] = pbpctl_dev_out->slot;
5689 bpctl_cmd.out_param[6] = pbpctl_dev_out->func;
5690 bpctl_cmd.out_param[7] = pbpctl_dev_out->ifindex;
5691 }
5692 break;
5693
5694 case IOCTL_TX_MSG(IS_BYPASS):
5695 bpctl_cmd.status = is_bypass(pbpctl_dev);
5696 break;
5697 case IOCTL_TX_MSG(SET_TX):
5698 bpctl_cmd.status = set_tx_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5699 break;
5700 case IOCTL_TX_MSG(GET_TX):
5701 bpctl_cmd.status = get_tx_fn(pbpctl_dev);
5702 break;
5703 case IOCTL_TX_MSG(SET_WD_AUTORESET):
5704 bpctl_cmd.status =
5705 set_wd_autoreset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5706
5707 break;
5708 case IOCTL_TX_MSG(GET_WD_AUTORESET):
5709
5710 bpctl_cmd.status = get_wd_autoreset_fn(pbpctl_dev);
5711 break;
5712 case IOCTL_TX_MSG(SET_DISC):
5713 bpctl_cmd.status =
5714 set_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5715 break;
5716 case IOCTL_TX_MSG(GET_DISC):
5717 bpctl_cmd.status = get_disc_fn(pbpctl_dev);
5718 break;
5719 case IOCTL_TX_MSG(GET_DISC_CHANGE):
5720 bpctl_cmd.status = get_disc_change_fn(pbpctl_dev);
5721 break;
5722 case IOCTL_TX_MSG(SET_DIS_DISC):
5723 bpctl_cmd.status =
5724 set_dis_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5725 break;
5726 case IOCTL_TX_MSG(GET_DIS_DISC):
5727 bpctl_cmd.status = get_dis_disc_fn(pbpctl_dev);
5728 break;
5729 case IOCTL_TX_MSG(SET_DISC_PWUP):
5730 bpctl_cmd.status =
5731 set_disc_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5732 break;
5733 case IOCTL_TX_MSG(GET_DISC_PWUP):
5734 bpctl_cmd.status = get_disc_pwup_fn(pbpctl_dev);
5735 break;
5736
5737 case IOCTL_TX_MSG(GET_BYPASS_INFO):
5738
5739 bpctl_cmd.status =
5740 get_bypass_info_fn(pbpctl_dev, (char *)&bpctl_cmd.data,
5741 (char *)&bpctl_cmd.out_param[4]);
5742 break;
5743
5744 case IOCTL_TX_MSG(SET_TPL):
5745 bpctl_cmd.status =
5746 set_tpl_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5747 break;
5748
5749 case IOCTL_TX_MSG(GET_TPL):
5750 bpctl_cmd.status = get_tpl_fn(pbpctl_dev);
5751 break;
7040e556
D		 5752 case IOCTL_TX_MSG(SET_BP_WAIT_AT_PWUP):
5753 bpctl_cmd.status =
5754 set_bp_wait_at_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5755 break;
5756
5757 case IOCTL_TX_MSG(GET_BP_WAIT_AT_PWUP):
5758 bpctl_cmd.status = get_bp_wait_at_pwup_fn(pbpctl_dev);
5759 break;
5760 case IOCTL_TX_MSG(SET_BP_HW_RESET):
5761 bpctl_cmd.status =
5762 set_bp_hw_reset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5763 break;
5764
5765 case IOCTL_TX_MSG(GET_BP_HW_RESET):
5766 bpctl_cmd.status = get_bp_hw_reset_fn(pbpctl_dev);
5767 break;
7040e556
D		 5768#ifdef BP_SELF_TEST
5769 case IOCTL_TX_MSG(SET_BP_SELF_TEST):
5770 bpctl_cmd.status =
5771 set_bp_self_test_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5772
5773 break;
5774 case IOCTL_TX_MSG(GET_BP_SELF_TEST):
5775 bpctl_cmd.status = get_bp_self_test_fn(pbpctl_dev);
5776 break;
5777
5778#endif
5779#if 0
5780 case IOCTL_TX_MSG(SET_DISC_PORT):
5781 bpctl_cmd.status =
5782 set_disc_port_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5783 break;
5784
5785 case IOCTL_TX_MSG(GET_DISC_PORT):
5786 bpctl_cmd.status = get_disc_port_fn(pbpctl_dev);
5787 break;
5788
5789 case IOCTL_TX_MSG(SET_DISC_PORT_PWUP):
5790 bpctl_cmd.status =
5791 set_disc_port_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5792 break;
5793
5794 case IOCTL_TX_MSG(GET_DISC_PORT_PWUP):
5795 bpctl_cmd.status = get_disc_port_pwup_fn(pbpctl_dev);
5796 break;
5797#endif
5798 case IOCTL_TX_MSG(SET_BP_FORCE_LINK):
5799 bpctl_cmd.status =
5800 set_bp_force_link_fn(dev_idx, bpctl_cmd.in_param[2]);
5801 break;
5802
5803 case IOCTL_TX_MSG(GET_BP_FORCE_LINK):
5804 bpctl_cmd.status = get_bp_force_link_fn(dev_idx);
5805 break;
5806
5807 default:
687bcca0 5808 /* unlock_bpctl(); */
7040e556
D		 5809
5810 ret = -EOPNOTSUPP;
687bcca0
DC		 5811 /* preempt_enable(); */
5812 /* rcu_read_unlock();*/
7040e556
D		 5813 spin_unlock_irqrestore(&bpvm_lock, flags);
5814 goto bp_exit;
5815 }
687bcca0
DC		 5816 /* unlock_bpctl(); */
5817 /* preempt_enable(); */
7040e556 5818 bpcmd_exit:
687bcca0 5819 /* rcu_read_unlock(); */
7040e556
D		 5820 spin_unlock_irqrestore(&bpvm_lock, flags);
5821 if (copy_to_user(argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd)))
5822 ret = -EFAULT;
5823 ret = SUCCESS;
5824 bp_exit:
687bcca0 5825 /* unlock_kernel(); */
687bcca0 5826 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
7040e556 5827 unlock_bpctl();
687bcca0 5828 /* unlock_kernel(); */
7040e556
D		 5829 return ret;
5830}
5831
5832struct file_operations Fops = {
5833 .owner = THIS_MODULE,
7040e556 5834 .unlocked_ioctl = device_ioctl,
7040e556
D		 5835 .open = device_open,
5836 .release = device_release, /* a.k.a. close */
5837};
5838
5839#ifndef PCI_DEVICE
5840#define PCI_DEVICE(vend,dev) \
5841 .vendor = (vend), .device = (dev), \
5842 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
5843#endif
5844
5845#define SILICOM_E1000BP_ETHERNET_DEVICE(device_id) {\
5846 PCI_DEVICE(SILICOM_VID, device_id)}
5847
5848typedef enum {
5849 PXG2BPFI,
5850 PXG2BPFIL,
5851 PXG2BPFILX,
5852 PXG2BPFILLX,
5853 PXGBPI,
5854 PXGBPIG,
5855 PXG2TBFI,
5856 PXG4BPI,
5857 PXG4BPFI,
5858 PEG4BPI,
5859 PEG2BPI,
5860 PEG4BPIN,
5861 PEG2BPFI,
5862 PEG2BPFILX,
5863 PMCXG2BPFI,
5864 PMCXG2BPFIN,
5865 PEG4BPII,
5866 PEG4BPFII,
5867 PXG4BPFILX,
5868 PMCXG2BPIN,
5869 PMCXG4BPIN,
5870 PXG2BISC1,
5871 PEG2TBFI,
5872 PXG2TBI,
5873 PXG4BPFID,
5874 PEG4BPFI,
5875 PEG4BPIPT,
5876 PXG6BPI,
5877 PEG4BPIL,
5878 PMCXG2BPIN2,
5879 PMCXG4BPIN2,
5880 PMCX2BPI,
5881 PEG2BPFID,
5882 PEG2BPFIDLX,
5883 PMCX4BPI,
5884 MEG2BPFILN,
5885 MEG2BPFINX,
5886 PEG4BPFILX,
5887 PE10G2BPISR,
5888 PE10G2BPILR,
5889 MHIO8AD,
5890 PE10G2BPICX4,
5891 PEG2BPI5,
5892 PEG6BPI,
5893 PEG4BPFI5,
5894 PEG4BPFI5LX,
5895 MEG2BPFILXLN,
5896 PEG2BPIX1,
5897 MEG2BPFILXNX,
5898 XE10G2BPIT,
5899 XE10G2BPICX4,
5900 XE10G2BPISR,
5901 XE10G2BPILR,
5902 PEG4BPIIO,
5903 XE10G2BPIXR,
5904 PE10GDBISR,
5905 PE10GDBILR,
5906 PEG2BISC6,
5907 PEG6BPIFC,
5908 PE10G2BPTCX4,
5909 PE10G2BPTSR,
5910 PE10G2BPTLR,
5911 PE10G2BPTT,
5912 PEG4BPI6,
5913 PEG4BPFI6,
5914 PEG4BPFI6LX,
5915 PEG4BPFI6ZX,
5916 PEG2BPI6,
5917 PEG2BPFI6,
5918 PEG2BPFI6LX,
5919 PEG2BPFI6ZX,
5920 PEG2BPFI6FLXM,
5921 PEG4BPI6FC,
5922 PEG4BPFI6FC,
5923 PEG4BPFI6FCLX,
5924 PEG4BPFI6FCZX,
5925 PEG6BPI6,
5926 PEG2BPI6SC6,
5927 MEG2BPI6,
5928 XEG2BPI6,
5929 MEG4BPI6,
5930 PEG2BPFI5,
5931 PEG2BPFI5LX,
5932 PXEG4BPFI,
5933 M1EG2BPI6,
5934 M1EG2BPFI6,
5935 M1EG2BPFI6LX,
5936 M1EG2BPFI6ZX,
5937 M1EG4BPI6,
5938 M1EG4BPFI6,
5939 M1EG4BPFI6LX,
5940 M1EG4BPFI6ZX,
5941 M1EG6BPI6,
5942 M1E2G4BPi80,
5943 M1E2G4BPFi80,
5944 M1E2G4BPFi80LX,
5945 M1E2G4BPFi80ZX,
5946 PE210G2SPI9,
5947 M1E10G2BPI9CX4,
5948 M1E10G2BPI9SR,
5949 M1E10G2BPI9LR,
5950 M1E10G2BPI9T,
5951 PE210G2BPI9CX4,
5952 PE210G2BPI9SR,
5953 PE210G2BPI9LR,
5954 PE210G2BPI9T,
5955 M2EG2BPFI6,
5956 M2EG2BPFI6LX,
5957 M2EG2BPFI6ZX,
5958 M2EG4BPI6,
5959 M2EG4BPFI6,
5960 M2EG4BPFI6LX,
5961 M2EG4BPFI6ZX,
5962 M2EG6BPI6,
5963 PEG2DBI6,
5964 PEG2DBFI6,
5965 PEG2DBFI6LX,
5966 PEG2DBFI6ZX,
5967 PE2G4BPi80,
5968 PE2G4BPFi80,
5969 PE2G4BPFi80LX,
5970 PE2G4BPFi80ZX,
5971 PE2G4BPi80L,
5972 M6E2G8BPi80A,
5973
5974 PE2G2BPi35,
5975 PAC1200BPi35,
5976 PE2G2BPFi35,
5977 PE2G2BPFi35LX,
5978 PE2G2BPFi35ZX,
5979 PE2G4BPi35,
5980 PE2G4BPi35L,
5981 PE2G4BPFi35,
5982 PE2G4BPFi35LX,
5983 PE2G4BPFi35ZX,
5984
5985 PE2G6BPi35,
5986 PE2G6BPi35CX,
5987
5988 PE2G2BPi80,
5989 PE2G2BPFi80,
5990 PE2G2BPFi80LX,
5991 PE2G2BPFi80ZX,
5992 M2E10G2BPI9CX4,
5993 M2E10G2BPI9SR,
5994 M2E10G2BPI9LR,
5995 M2E10G2BPI9T,
5996 M6E2G8BPi80,
5997 PE210G2DBi9SR,
5998 PE210G2DBi9SRRB,
5999 PE210G2DBi9LR,
6000 PE210G2DBi9LRRB,
6001 PE310G4DBi940SR,
6002 PE310G4BPi9T,
6003 PE310G4BPi9SR,
6004 PE310G4BPi9LR,
6005 PE210G2BPi40,
6006} board_t;
6007
6008typedef struct _bpmod_info_t {
6009 unsigned int vendor;
6010 unsigned int device;
6011 unsigned int subvendor;
6012 unsigned int subdevice;
6013 unsigned int index;
6014 char *bp_name;
6015
6016} bpmod_info_t;
6017
6018typedef struct _dev_desc {
6019 char *name;
6020} dev_desc_t;
6021
6022dev_desc_t dev_desc[] = {
6023 {"Silicom Bypass PXG2BPFI-SD series adapter"},
6024 {"Silicom Bypass PXG2BPFIL-SD series adapter"},
6025 {"Silicom Bypass PXG2BPFILX-SD series adapter"},
6026 {"Silicom Bypass PXG2BPFILLX-SD series adapter"},
6027 {"Silicom Bypass PXG2BPI-SD series adapter"},
6028 {"Silicom Bypass PXG2BPIG-SD series adapter"},
6029 {"Silicom Bypass PXG2TBFI-SD series adapter"},
6030 {"Silicom Bypass PXG4BPI-SD series adapter"},
6031 {"Silicom Bypass PXG4BPFI-SD series adapter"},
6032 {"Silicom Bypass PEG4BPI-SD series adapter"},
6033 {"Silicom Bypass PEG2BPI-SD series adapter"},
6034 {"Silicom Bypass PEG4BPIN-SD series adapter"},
6035 {"Silicom Bypass PEG2BPFI-SD series adapter"},
6036 {"Silicom Bypass PEG2BPFI-LX-SD series adapter"},
6037 {"Silicom Bypass PMCX2BPFI-SD series adapter"},
6038 {"Silicom Bypass PMCX2BPFI-N series adapter"},
6039 {"Intel Bypass PEG2BPII series adapter"},
6040 {"Intel Bypass PEG2BPFII series adapter"},
6041 {"Silicom Bypass PXG4BPFILX-SD series adapter"},
6042 {"Silicom Bypass PMCX2BPI-N series adapter"},
6043 {"Silicom Bypass PMCX4BPI-N series adapter"},
6044 {"Silicom Bypass PXG2BISC1-SD series adapter"},
6045 {"Silicom Bypass PEG2TBFI-SD series adapter"},
6046 {"Silicom Bypass PXG2TBI-SD series adapter"},
6047 {"Silicom Bypass PXG4BPFID-SD series adapter"},
6048 {"Silicom Bypass PEG4BPFI-SD series adapter"},
6049 {"Silicom Bypass PEG4BPIPT-SD series adapter"},
6050 {"Silicom Bypass PXG6BPI-SD series adapter"},
6051 {"Silicom Bypass PEG4BPIL-SD series adapter"},
6052 {"Silicom Bypass PMCX2BPI-N2 series adapter"},
6053 {"Silicom Bypass PMCX4BPI-N2 series adapter"},
6054 {"Silicom Bypass PMCX2BPI-SD series adapter"},
6055 {"Silicom Bypass PEG2BPFID-SD series adapter"},
6056 {"Silicom Bypass PEG2BPFIDLX-SD series adapter"},
6057 {"Silicom Bypass PMCX4BPI-SD series adapter"},
6058 {"Silicom Bypass MEG2BPFILN-SD series adapter"},
6059 {"Silicom Bypass MEG2BPFINX-SD series adapter"},
6060 {"Silicom Bypass PEG4BPFILX-SD series adapter"},
6061 {"Silicom Bypass PE10G2BPISR-SD series adapter"},
6062 {"Silicom Bypass PE10G2BPILR-SD series adapter"},
6063 {"Silicom Bypass MHIO8AD-SD series adapter"},
6064 {"Silicom Bypass PE10G2BPICX4-SD series adapter"},
6065 {"Silicom Bypass PEG2BPI5-SD series adapter"},
6066 {"Silicom Bypass PEG6BPI5-SD series adapter"},
6067 {"Silicom Bypass PEG4BPFI5-SD series adapter"},
6068 {"Silicom Bypass PEG4BPFI5LX-SD series adapter"},
6069 {"Silicom Bypass MEG2BPFILXLN-SD series adapter"},
6070 {"Silicom Bypass PEG2BPIX1-SD series adapter"},
6071 {"Silicom Bypass MEG2BPFILXNX-SD series adapter"},
6072 {"Silicom Bypass XE10G2BPIT-SD series adapter"},
6073 {"Silicom Bypass XE10G2BPICX4-SD series adapter"},
6074 {"Silicom Bypass XE10G2BPISR-SD series adapter"},
6075 {"Silicom Bypass XE10G2BPILR-SD series adapter"},
6076 {"Intel Bypass PEG2BPFII0 series adapter"},
6077 {"Silicom Bypass XE10G2BPIXR series adapter"},
6078 {"Silicom Bypass PE10G2DBISR series adapter"},
6079 {"Silicom Bypass PEG2BI5SC6 series adapter"},
6080 {"Silicom Bypass PEG6BPI5FC series adapter"},
6081
6082 {"Silicom Bypass PE10G2BPTCX4 series adapter"},
6083 {"Silicom Bypass PE10G2BPTSR series adapter"},
6084 {"Silicom Bypass PE10G2BPTLR series adapter"},
6085 {"Silicom Bypass PE10G2BPTT series adapter"},
6086 {"Silicom Bypass PEG4BPI6 series adapter"},
6087 {"Silicom Bypass PEG4BPFI6 series adapter"},
6088 {"Silicom Bypass PEG4BPFI6LX series adapter"},
6089 {"Silicom Bypass PEG4BPFI6ZX series adapter"},
6090 {"Silicom Bypass PEG2BPI6 series adapter"},
6091 {"Silicom Bypass PEG2BPFI6 series adapter"},
6092 {"Silicom Bypass PEG2BPFI6LX series adapter"},
6093 {"Silicom Bypass PEG2BPFI6ZX series adapter"},
6094 {"Silicom Bypass PEG2BPFI6FLXM series adapter"},
6095 {"Silicom Bypass PEG4BPI6FC series adapter"},
6096 {"Silicom Bypass PEG4BPFI6FC series adapter"},
6097 {"Silicom Bypass PEG4BPFI6FCLX series adapter"},
6098 {"Silicom Bypass PEG4BPFI6FCZX series adapter"},
6099 {"Silicom Bypass PEG6BPI6 series adapter"},
6100 {"Silicom Bypass PEG2BPI6SC6 series adapter"},
6101 {"Silicom Bypass MEG2BPI6 series adapter"},
6102 {"Silicom Bypass XEG2BPI6 series adapter"},
6103 {"Silicom Bypass MEG4BPI6 series adapter"},
6104 {"Silicom Bypass PEG2BPFI5-SD series adapter"},
6105 {"Silicom Bypass PEG2BPFI5LX-SD series adapter"},
6106 {"Silicom Bypass PXEG4BPFI-SD series adapter"},
6107 {"Silicom Bypass MxEG2BPI6 series adapter"},
6108 {"Silicom Bypass MxEG2BPFI6 series adapter"},
6109 {"Silicom Bypass MxEG2BPFI6LX series adapter"},
6110 {"Silicom Bypass MxEG2BPFI6ZX series adapter"},
6111 {"Silicom Bypass MxEG4BPI6 series adapter"},
6112 {"Silicom Bypass MxEG4BPFI6 series adapter"},
6113 {"Silicom Bypass MxEG4BPFI6LX series adapter"},
6114 {"Silicom Bypass MxEG4BPFI6ZX series adapter"},
6115 {"Silicom Bypass MxEG6BPI6 series adapter"},
6116 {"Silicom Bypass MxE2G4BPi80 series adapter"},
6117 {"Silicom Bypass MxE2G4BPFi80 series adapter"},
6118 {"Silicom Bypass MxE2G4BPFi80LX series adapter"},
6119 {"Silicom Bypass MxE2G4BPFi80ZX series adapter"},
6120
6121 {"Silicom Bypass PE210G2SPI9 series adapter"},
6122
6123 {"Silicom Bypass MxE210G2BPI9CX4 series adapter"},
6124 {"Silicom Bypass MxE210G2BPI9SR series adapter"},
6125 {"Silicom Bypass MxE210G2BPI9LR series adapter"},
6126 {"Silicom Bypass MxE210G2BPI9T series adapter"},
6127
6128 {"Silicom Bypass PE210G2BPI9CX4 series adapter"},
6129 {"Silicom Bypass PE210G2BPI9SR series adapter"},
6130 {"Silicom Bypass PE210G2BPI9LR series adapter"},
6131 {"Silicom Bypass PE210G2BPI9T series adapter"},
6132
6133 {"Silicom Bypass M2EG2BPFI6 series adapter"},
6134 {"Silicom Bypass M2EG2BPFI6LX series adapter"},
6135 {"Silicom Bypass M2EG2BPFI6ZX series adapter"},
6136 {"Silicom Bypass M2EG4BPI6 series adapter"},
6137 {"Silicom Bypass M2EG4BPFI6 series adapter"},
6138 {"Silicom Bypass M2EG4BPFI6LX series adapter"},
6139 {"Silicom Bypass M2EG4BPFI6ZX series adapter"},
6140 {"Silicom Bypass M2EG6BPI6 series adapter"},
6141
6142 {"Silicom Bypass PEG2DBI6 series adapter"},
6143 {"Silicom Bypass PEG2DBFI6 series adapter"},
6144 {"Silicom Bypass PEG2DBFI6LX series adapter"},
6145 {"Silicom Bypass PEG2DBFI6ZX series adapter"},
6146
6147 {"Silicom Bypass PE2G4BPi80 series adapter"},
6148 {"Silicom Bypass PE2G4BPFi80 series adapter"},
6149 {"Silicom Bypass PE2G4BPFi80LX series adapter"},
6150 {"Silicom Bypass PE2G4BPFi80ZX series adapter"},
6151
6152 {"Silicom Bypass PE2G4BPi80L series adapter"},
6153 {"Silicom Bypass MxE2G8BPi80A series adapter"},
6154
6155 {"Silicom Bypass PE2G2BPi35 series adapter"},
6156 {"Silicom Bypass PAC1200BPi35 series adapter"},
6157 {"Silicom Bypass PE2G2BPFi35 series adapter"},
6158 {"Silicom Bypass PE2G2BPFi35LX series adapter"},
6159 {"Silicom Bypass PE2G2BPFi35ZX series adapter"},
6160
6161 {"Silicom Bypass PE2G4BPi35 series adapter"},
6162 {"Silicom Bypass PE2G4BPi35L series adapter"},
6163 {"Silicom Bypass PE2G4BPFi35 series adapter"},
6164 {"Silicom Bypass PE2G4BPFi35LX series adapter"},
6165 {"Silicom Bypass PE2G4BPFi35ZX series adapter"},
6166
6167 {"Silicom Bypass PE2G6BPi35 series adapter"},
6168 {"Silicom Bypass PE2G6BPi35CX series adapter"},
6169
6170 {"Silicom Bypass PE2G2BPi80 series adapter"},
6171 {"Silicom Bypass PE2G2BPFi80 series adapter"},
6172 {"Silicom Bypass PE2G2BPFi80LX series adapter"},
6173 {"Silicom Bypass PE2G2BPFi80ZX series adapter"},
6174
6175 {"Silicom Bypass M2E10G2BPI9CX4 series adapter"},
6176 {"Silicom Bypass M2E10G2BPI9SR series adapter"},
6177 {"Silicom Bypass M2E10G2BPI9LR series adapter"},
6178 {"Silicom Bypass M2E10G2BPI9T series adapter"},
6179 {"Silicom Bypass MxE2G8BPi80 series adapter"},
6180 {"Silicom Bypass PE210G2DBi9SR series adapter"},
6181 {"Silicom Bypass PE210G2DBi9SRRB series adapter"},
6182 {"Silicom Bypass PE210G2DBi9LR series adapter"},
6183 {"Silicom Bypass PE210G2DBi9LRRB series adapter"},
6184 {"Silicom Bypass PE310G4DBi9-SR series adapter"},
6185 {"Silicom Bypass PE310G4BPi9T series adapter"},
6186 {"Silicom Bypass PE310G4BPi9SR series adapter"},
6187 {"Silicom Bypass PE310G4BPi9LR series adapter"},
6188 {"Silicom Bypass PE210G2BPi40T series adapter"},
6189 {0},
6190};
6191
6192static bpmod_info_t tx_ctl_pci_tbl[] = {
6193 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFI_SSID, PXG2BPFI,
6194 "PXG2BPFI-SD"},
6195 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFIL_SSID, PXG2BPFIL,
6196 "PXG2BPFIL-SD"},
6197 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILX_SSID, PXG2BPFILX,
6198 "PXG2BPFILX-SD"},
6199 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILLX_SSID, PXG2BPFILLX,
6200 "PXG2BPFILLXSD"},
6201 {0x8086, 0x1010, SILICOM_SVID, SILICOM_PXGBPI_SSID, PXGBPI,
6202 "PXG2BPI-SD"},
6203 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXGBPIG_SSID, PXGBPIG,
6204 "PXG2BPIG-SD"},
6205 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2TBFI_SSID, PXG2TBFI,
6206 "PXG2TBFI-SD"},
6207 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6208 "PXG4BPI-SD"},
6209 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6210 "PXG4BPFI-SD"},
6211 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFILX_SSID, PXG4BPFILX,
6212 "PXG4BPFILX-SD"},
6213 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PEG4BPI_SSID, PEG4BPI,
6214 "PEXG4BPI-SD"},
6215 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPI_SSID, PEG2BPI,
6216 "PEG2BPI-SD"},
6217 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIN_SSID, PEG4BPIN,
6218 "PEG4BPI-SD"},
6219 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFI_SSID, PEG2BPFI,
6220 "PEG2BPFI-SD"},
6221 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFILX_SSID, PEG2BPFILX,
6222 "PEG2BPFILX-SD"},
6223 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PMCXG2BPFI_SSID, PMCXG2BPFI,
6224 "PMCX2BPFI-SD"},
6225 {0x8086, 0x107a, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPFIN_SSID,
6226 PMCXG2BPFIN, "PMCX2BPFI-N"},
6227 {0x8086, INTEL_PEG4BPII_PID, 0x8086, INTEL_PEG4BPII_SSID, PEG4BPII,
6228 "PEG4BPII"},
6229 {0x8086, INTEL_PEG4BPIIO_PID, 0x8086, INTEL_PEG4BPIIO_SSID, PEG4BPIIO,
6230 "PEG4BPII0"},
6231 {0x8086, INTEL_PEG4BPFII_PID, 0x8086, INTEL_PEG4BPFII_SSID, PEG4BPFII,
6232 "PEG4BPFII"},
6233 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN_SSID,
6234 PMCXG2BPIN, "PMCX2BPI-N"},
6235 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN_SSID,
6236 PMCXG4BPIN, "PMCX4BPI-N"},
6237 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6238 "PXG2BISC1-SD"},
6239 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2TBFI_SSID, PEG2TBFI,
6240 "PEG2TBFI-SD"},
6241 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6242 "PXG2TBI-SD"},
6243 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFID_SSID, PXG4BPFID,
6244 "PXG4BPFID-SD"},
6245 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6246 "PEG4BPFI-SD"},
6247 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIPT_SSID, PEG4BPIPT,
6248 "PEG4BPIPT-SD"},
6249 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG6BPI_SSID, PXG6BPI,
6250 "PXG6BPI-SD"},
6251 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6252 SILICOM_PEG4BPIL_SSID /*PCI_ANY_ID */ , PEG4BPIL, "PEG4BPIL-SD"},
6253 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN2_SSID,
6254 PMCXG2BPIN2, "PMCX2BPI-N2"},
6255 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN2_SSID,
6256 PMCXG4BPIN2, "PMCX4BPI-N2"},
6257 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX2BPI_SSID, PMCX2BPI,
6258 "PMCX2BPI-SD"},
6259 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX4BPI_SSID, PMCX4BPI,
6260 "PMCX4BPI-SD"},
6261 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFID_SSID, PEG2BPFID,
6262 "PEG2BPFID-SD"},
6263 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFIDLX_SSID, PEG2BPFIDLX,
6264 "PEG2BPFIDLXSD"},
6265 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILN_SSID, MEG2BPFILN,
6266 "MEG2BPFILN-SD"},
6267 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFINX_SSID, MEG2BPFINX,
6268 "MEG2BPFINX-SD"},
6269 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFILX_SSID, PEG4BPFILX,
6270 "PEG4BPFILX-SD"},
6271 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPISR_SSID,
6272 PE10G2BPISR, "PE10G2BPISR"},
6273 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPILR_SSID,
6274 PE10G2BPILR, "PE10G2BPILR"},
6275 {0x8086, 0x10a9, SILICOM_SVID, SILICOM_MHIO8AD_SSID, MHIO8AD,
6276 "MHIO8AD-SD"},
6277 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPICX4_SSID,
6278 PE10G2BPISR, "PE10G2BPICX4"},
6279 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6280 SILICOM_PEG2BPI5_SSID /*PCI_ANY_ID */ , PEG2BPI5, "PEG2BPI5-SD"},
6281 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6282 SILICOM_PEG6BPI_SSID /*PCI_ANY_ID */ , PEG6BPI, "PEG6BPI5"},
6283 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG4BPFI5_SSID,
6284 PEG4BPFI5, "PEG4BPFI5"},
6285 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6286 SILICOM_PEG4BPFI5LX_SSID, PEG4BPFI5LX, "PEG4BPFI5LX"},
6287 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXLN_SSID, MEG2BPFILXLN,
6288 "MEG2BPFILXLN"},
6289 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPIX1_SSID, PEG2BPIX1,
6290 "PEG2BPIX1-SD"},
6291 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXNX_SSID, MEG2BPFILXNX,
6292 "MEG2BPFILXNX"},
6293 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPIT_SSID, XE10G2BPIT,
6294 "XE10G2BPIT"},
6295 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPICX4_SSID,
6296 XE10G2BPICX4, "XE10G2BPICX4"},
6297 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPISR_SSID, XE10G2BPISR,
6298 "XE10G2BPISR"},
6299 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPILR_SSID, XE10G2BPILR,
6300 "XE10G2BPILR"},
6301 {0x8086, 0x10C6, NOKIA_XE10G2BPIXR_SVID, NOKIA_XE10G2BPIXR_SSID,
6302 XE10G2BPIXR, "XE10G2BPIXR"},
6303 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBISR_SSID, PE10GDBISR,
6304 "PE10G2DBISR"},
6305 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBILR_SSID, PE10GDBILR,
6306 "PE10G2DBILR"},
6307 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6308 SILICOM_PEG2BISC6_SSID /*PCI_ANY_ID */ , PEG2BISC6, "PEG2BI5SC6"},
6309 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6310 SILICOM_PEG6BPIFC_SSID /*PCI_ANY_ID */ , PEG6BPIFC, "PEG6BPI5FC"},
6311
6312 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6313 SILICOM_PE10G2BPTCX4_SSID, PE10G2BPTCX4, "PE10G2BPTCX4"},
6314 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6315 SILICOM_PE10G2BPTSR_SSID, PE10G2BPTSR, "PE10G2BPTSR"},
6316 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6317 SILICOM_PE10G2BPTLR_SSID, PE10G2BPTLR, "PE10G2BPTLR"},
6318 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6319 SILICOM_PE10G2BPTT_SSID, PE10G2BPTT, "PE10G2BPTT"},
6320
687bcca0 6321 /* {BROADCOM_VID, BROADCOM_PE10G2_PID, PCI_ANY_ID, PCI_ANY_ID, PE10G2BPTCX4, "PE10G2BPTCX4"}, */
7040e556
D		 6322
6323 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6324 SILICOM_PEG4BPI6_SSID /*PCI_ANY_ID */ , PEG4BPI6, "PEG4BPI6"},
6325 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6326 SILICOM_PEG4BPFI6_SSID /*PCI_ANY_ID */ , PEG4BPFI6, "PEG4BPFI6"},
6327 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6328 SILICOM_PEG4BPFI6LX_SSID /*PCI_ANY_ID */ , PEG4BPFI6LX, "PEG4BPFI6LX"},
6329 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6330 SILICOM_PEG4BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6ZX, "PEG4BPFI6ZX"},
6331 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6332 SILICOM_PEG2BPI6_SSID /*PCI_ANY_ID */ , PEG2BPI6, "PEG2BPI6"},
6333 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6334 SILICOM_PEG2BPFI6_SSID /*PCI_ANY_ID */ , PEG2BPFI6, "PEG2BPFI6"},
6335 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6336 SILICOM_PEG2BPFI6LX_SSID /*PCI_ANY_ID */ , PEG2BPFI6LX, "PEG2BPFI6LX"},
6337 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6338 SILICOM_PEG2BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG2BPFI6ZX, "PEG2BPFI6ZX"},
6339 {0x8086, 0x10e7, SILICOM_SVID /*PCI_ANY_ID */ ,
6340 SILICOM_PEG2BPFI6FLXM_SSID /*PCI_ANY_ID */ , PEG2BPFI6FLXM,
6341 "PEG2BPFI6FLXM"},
6342 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6343 SILICOM_PEG4BPI6FC_SSID /*PCI_ANY_ID */ , PEG4BPI6FC, "PEG4BPI6FC"},
6344 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6345 SILICOM_PEG4BPFI6FC_SSID /*PCI_ANY_ID */ , PEG4BPFI6FC, "PEG4BPFI6FC"},
6346 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6347 SILICOM_PEG4BPFI6FCLX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCLX,
6348 "PEG4BPFI6FCLX"},
6349 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6350 SILICOM_PEG4BPFI6FCZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCZX,
6351 "PEG4BPFI6FCZX"},
6352 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6353 SILICOM_PEG6BPI6_SSID /*PCI_ANY_ID */ , PEG6BPI6, "PEG6BPI6"},
6354 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6355 SILICOM_PEG2BPI6SC6_SSID /*PCI_ANY_ID */ , PEG2BPI6SC6,
6356 "PEG6BPI62SC6"},
6357 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6358 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6359 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6360 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6361 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6362 SILICOM_MEG4BPI6_SSID /*PCI_ANY_ID */ , MEG4BPI6, "MEG4BPI6"},
6363
6364 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG2BPFI5_SSID,
6365 PEG2BPFI5, "PEG2BPFI5"},
6366 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6367 SILICOM_PEG2BPFI5LX_SSID, PEG2BPFI5LX, "PEG2BPFI5LX"},
6368
6369 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PXEG4BPFI_SSID, PXEG4BPFI,
6370 "PXEG4BPFI-SD"},
6371
6372 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6373 SILICOM_M1EG2BPI6_SSID /*PCI_ANY_ID */ , M1EG2BPI6, "MxEG2BPI6"},
6374
6375 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6376 SILICOM_M1EG2BPFI6_SSID /*PCI_ANY_ID */ , M1EG2BPFI6, "MxEG2BPFI6"},
6377 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6378 SILICOM_M1EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6LX,
6379 "MxEG2BPFI6LX"},
6380 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6381 SILICOM_M1EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6ZX,
6382 "MxEG2BPFI6ZX"},
6383
6384 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6385 SILICOM_M1EG4BPI6_SSID /*PCI_ANY_ID */ , M1EG4BPI6, "MxEG4BPI6"},
6386
6387 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6388 SILICOM_M1EG4BPFI6_SSID /*PCI_ANY_ID */ , M1EG4BPFI6, "MxEG4BPFI6"},
6389 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6390 SILICOM_M1EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6LX,
6391 "MxEG4BPFI6LX"},
6392 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6393 SILICOM_M1EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6ZX,
6394 "MxEG4BPFI6ZX"},
6395
6396 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6397 SILICOM_M1EG6BPI6_SSID /*PCI_ANY_ID */ , M1EG6BPI6, "MxEG6BPI6"},
6398
6399 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6400 SILICOM_M1E2G4BPi80_SSID /*PCI_ANY_ID */ , M1E2G4BPi80, "MxE2G4BPi80"},
6401 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6402 SILICOM_M1E2G4BPFi80_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80,
6403 "MxE2G4BPFi80"},
6404 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6405 SILICOM_M1E2G4BPFi80LX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80LX,
6406 "MxE2G4BPFi80LX"},
6407 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6408 SILICOM_M1E2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80ZX,
6409 "MxE2G4BPFi80ZX"},
6410
6411 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6412 SILICOM_M2EG2BPFI6_SSID /*PCI_ANY_ID */ , M2EG2BPFI6, "M2EG2BPFI6"},
6413 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6414 SILICOM_M2EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6LX,
6415 "M2EG2BPFI6LX"},
6416 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6417 SILICOM_M2EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6ZX,
6418 "M2EG2BPFI6ZX"},
6419
6420 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6421 SILICOM_M2EG4BPI6_SSID /*PCI_ANY_ID */ , M2EG4BPI6, "M2EG4BPI6"},
6422
6423 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6424 SILICOM_M2EG4BPFI6_SSID /*PCI_ANY_ID */ , M2EG4BPFI6, "M2EG4BPFI6"},
6425 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6426 SILICOM_M2EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6LX,
6427 "M2EG4BPFI6LX"},
6428 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6429 SILICOM_M2EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6ZX,
6430 "M2EG4BPFI6ZX"},
6431
6432 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6433 SILICOM_M2EG6BPI6_SSID /*PCI_ANY_ID */ , M2EG6BPI6, "M2EG6BPI6"},
6434
6435 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6436 SILICOM_PEG2DBI6_SSID /*PCI_ANY_ID */ , PEG2DBI6, "PEG2DBI6"},
6437 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6438 SILICOM_PEG2DBFI6_SSID /*PCI_ANY_ID */ , PEG2DBFI6, "PEG2DBFI6"},
6439 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6440 SILICOM_PEG2DBFI6LX_SSID /*PCI_ANY_ID */ , PEG2DBFI6LX, "PEG2DBFI6LX"},
6441 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6442 SILICOM_PEG2DBFI6ZX_SSID /*PCI_ANY_ID */ , PEG2DBFI6ZX, "PEG2DBFI6ZX"},
6443
6444 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6445 SILICOM_PE210G2DBi9SR_SSID, PE210G2DBi9SR, "PE210G2DBi9SR"},
7040e556
D		 6446 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6447 SILICOM_PE210G2DBi9LR_SSID, PE210G2DBi9LR, "PE210G2DBi9LR"},
7040e556
D		 6448 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6449 SILICOM_PE310G4DBi940SR_SSID, PE310G4DBi940SR, "PE310G4DBi9SR"},
6450
6451 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6452 SILICOM_PE310G4BPi9T_SSID, PE310G4BPi9T, "PE310G4BPi9T"},
6453 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6454 SILICOM_PE310G4BPi9SR_SSID, PE310G4BPi9SR, "PE310G4BPi9SR"},
6455 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6456 SILICOM_PE310G4BPi9LR_SSID, PE310G4BPi9LR, "PE310G4BPi9LR"},
6457
6458 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6459 SILICOM_PE2G4BPi80_SSID /*PCI_ANY_ID */ , PE2G4BPi80, "PE2G4BPi80"},
6460 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6461 SILICOM_PE2G4BPFi80_SSID /*PCI_ANY_ID */ , PE2G4BPFi80, "PE2G4BPFi80"},
6462 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6463 SILICOM_PE2G4BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80LX,
6464 "PE2G4BPFi80LX"},
6465 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6466 SILICOM_PE2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80ZX,
6467 "PE2G4BPFi80ZX"},
6468
6469 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6470 SILICOM_PE2G4BPi80L_SSID /*PCI_ANY_ID */ , PE2G4BPi80L, "PE2G4BPi80L"},
6471
6472 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6473 SILICOM_M6E2G8BPi80A_SSID /*PCI_ANY_ID */ , M6E2G8BPi80A,
6474 "MxE2G8BPi80A"},
6475
6476 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6477 SILICOM_PE2G2BPi35_SSID /*PCI_ANY_ID */ , PE2G2BPi35, "PE2G2BPi35"},
6478 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6479 SILICOM_PAC1200BPi35_SSID /*PCI_ANY_ID */ , PAC1200BPi35,
6480 "PAC1200BPi35"},
6481
6482 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6483 SILICOM_PE2G2BPFi35_SSID /*PCI_ANY_ID */ , PE2G2BPFi35, "PE2G2BPFi35"},
6484 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6485 SILICOM_PE2G2BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35LX,
6486 "PE2G2BPFi35LX"},
6487 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6488 SILICOM_PE2G2BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35ZX,
6489 "PE2G2BPFi35ZX"},
6490
6491 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6492 SILICOM_PE2G4BPi35_SSID /*PCI_ANY_ID */ , PE2G4BPi35, "PE2G4BPi35"},
6493
6494 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6495 SILICOM_PE2G4BPi35L_SSID /*PCI_ANY_ID */ , PE2G4BPi35L, "PE2G4BPi35L"},
6496
6497 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6498 SILICOM_PE2G4BPFi35_SSID /*PCI_ANY_ID */ , PE2G4BPFi35, "PE2G4BPFi35"},
6499 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6500 SILICOM_PE2G4BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35LX,
6501 "PE2G4BPFi35LX"},
6502 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6503 SILICOM_PE2G4BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35ZX,
6504 "PE2G4BPFi35ZX"},
6505
6506 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6507 SILICOM_PE2G6BPi35_SSID /*PCI_ANY_ID */ , PE2G6BPi35, "PE2G6BPi35"},
6508
7040e556
D		 6509
6510 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa0, PE2G6BPi35CX,
6511 "PE2G6BPi35CX"},
6512 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa1, PE2G6BPi35CX,
6513 "PE2G6BPi35CX"},
6514 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa2, PE2G6BPi35CX,
6515 "PE2G6BPi35CX"},
6516 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa3, PE2G6BPi35CX,
6517 "PE2G6BPi35CX"},
6518 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa4, PE2G6BPi35CX,
6519 "PE2G6BPi35CX"},
6520 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa5, PE2G6BPi35CX,
6521 "PE2G6BPi35CX"},
6522 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa6, PE2G6BPi35CX,
6523 "PE2G6BPi35CX"},
6524 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa7, PE2G6BPi35CX,
6525 "PE2G6BPi35CX"},
6526 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa8, PE2G6BPi35CX,
6527 "PE2G6BPi35CX"},
6528 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa9, PE2G6BPi35CX,
6529 "PE2G6BPi35CX"},
6530 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaa, PE2G6BPi35CX,
6531 "PE2G6BPi35CX"},
6532 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaab, PE2G6BPi35CX,
6533 "PE2G6BPi35CX"},
6534 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaac, PE2G6BPi35CX,
6535 "PE2G6BPi35CX"},
6536 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaad, PE2G6BPi35CX,
6537 "PE2G6BPi35CX"},
6538 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaae, PE2G6BPi35CX,
6539 "PE2G6BPi35CX"},
6540 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaf, PE2G6BPi35CX,
6541 "PE2G6BPi35CX"},
6542 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab0, PE2G6BPi35CX,
6543 "PE2G6BPi35CX"},
6544 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab1, PE2G6BPi35CX,
6545 "PE2G6BPi35CX"},
6546 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab2, PE2G6BPi35CX,
6547 "PE2G6BPi35CX"},
6548 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab3, PE2G6BPi35CX,
6549 "PE2G6BPi35CX"},
6550 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab4, PE2G6BPi35CX,
6551 "PE2G6BPi35CX"},
6552 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab5, PE2G6BPi35CX,
6553 "PE2G6BPi35CX"},
6554 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab6, PE2G6BPi35CX,
6555 "PE2G6BPi35CX"},
6556 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab7, PE2G6BPi35CX,
6557 "PE2G6BPi35CX"},
6558 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab8, PE2G6BPi35CX,
6559 "PE2G6BPi35CX"},
6560 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab9, PE2G6BPi35CX,
6561 "PE2G6BPi35CX"},
6562 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaba, PE2G6BPi35CX,
6563 "PE2G6BPi35CX"},
6564 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabb, PE2G6BPi35CX,
6565 "PE2G6BPi35CX"},
6566 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabc, PE2G6BPi35CX,
6567 "PE2G6BPi35CX"},
6568 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabd, PE2G6BPi35CX,
6569 "PE2G6BPi35CX"},
6570 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabe, PE2G6BPi35CX,
6571 "PE2G6BPi35CX"},
6572 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabf, PE2G6BPi35CX,
6573 "PE2G6BPi35CX"},
6574
6575 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6576 SILICOM_PE2G2BPi80_SSID /*PCI_ANY_ID */ , PE2G2BPi80, "PE2G2BPi80"},
6577 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6578 SILICOM_PE2G2BPFi80_SSID /*PCI_ANY_ID */ , PE2G2BPFi80, "PE2G2BPFi80"},
6579 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6580 SILICOM_PE2G2BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80LX,
6581 "PE2G2BPFi80LX"},
6582 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6583 SILICOM_PE2G2BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80ZX,
6584 "PE2G2BPFi80ZX"},
6585
6586 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6587 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6588 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6589 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6590
6591#if 0
6592 {0x8086, 0x10fb, 0x8086, INTEL_PE210G2SPI9_SSID, PE210G2SPI9,
6593 "PE210G2SPI9"},
6594#endif
6595 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6596 SILICOM_M1E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M1E10G2BPI9CX4,
6597 "MxE210G2BPI9CX4"},
6598 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6599 SILICOM_M1E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9SR,
6600 "MxE210G2BPI9SR"},
6601 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6602 SILICOM_M1E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9LR,
6603 "MxE210G2BPI9LR"},
6604 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6605 SILICOM_M1E10G2BPI9T_SSID /*PCI_ANY_ID */ , M1E10G2BPI9T,
6606 "MxE210G2BPI9T"},
6607
6608 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6609 SILICOM_M2E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M2E10G2BPI9CX4,
6610 "M2E10G2BPI9CX4"},
6611 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6612 SILICOM_M2E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9SR,
6613 "M2E10G2BPI9SR"},
6614 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6615 SILICOM_M2E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9LR,
6616 "M2E10G2BPI9LR"},
6617 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6618 SILICOM_M2E10G2BPI9T_SSID /*PCI_ANY_ID */ , M2E10G2BPI9T,
6619 "M2E10G2BPI9T"},
6620
6621 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9CX4_SSID,
6622 PE210G2BPI9CX4, "PE210G2BPI9CX4"},
6623 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9SR_SSID,
6624 PE210G2BPI9SR, "PE210G2BPI9SR"},
6625 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9LR_SSID,
6626 PE210G2BPI9LR, "PE210G2BPI9LR"},
6627 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9T_SSID, PE210G2BPI9T,
6628 "PE210G2BPI9T"},
6629
6630#if 0
6631 {0x1374, 0x2c, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6632 "PXG4BPI-SD"},
6633
6634 {0x1374, 0x2d, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6635 "PXG4BPFI-SD"},
6636
6637 {0x1374, 0x3f, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6638 "PXG2TBI-SD"},
6639
6640 {0x1374, 0x3d, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6641 "PXG2BISC1-SD"},
6642
6643 {0x1374, 0x40, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6644 "PEG4BPFI-SD"},
6645
6646#ifdef BP_SELF_TEST
6647 {0x1374, 0x28, SILICOM_SVID, 0x28, PXGBPI, "PXG2BPI-SD"},
6648#endif
6649#endif
6650 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6651 SILICOM_M6E2G8BPi80_SSID /*PCI_ANY_ID */ , M6E2G8BPi80, "MxE2G8BPi80"},
6652 {0x8086, 0x1528, SILICOM_SVID /*PCI_ANY_ID */ ,
6653 SILICOM_PE210G2BPi40_SSID /*PCI_ANY_ID */ , PE210G2BPi40,
6654 "PE210G2BPi40T"},
6655
6656 /* required last entry */
6657 {0,}
6658};
6659
6660/*
6661* Initialize the module - Register the character device
6662*/
6663
6664static int __init bypass_init_module(void)
6665{
6666 int ret_val, idx, idx_dev = 0;
6667 struct pci_dev *pdev1 = NULL;
6668 unsigned long mmio_start, mmio_len;
6669
6670 printk(BP_MOD_DESCR " v" BP_MOD_VER "\n");
6671 ret_val = register_chrdev(major_num, DEVICE_NAME, &Fops);
6672 if (ret_val < 0) {
6673 printk("%s failed with %d\n", DEVICE_NAME, ret_val);
6674 return ret_val;
6675 }
6676 major_num = ret_val; /* dynamic */
6677 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6678 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6679 tx_ctl_pci_tbl[idx].device,
6680 tx_ctl_pci_tbl[idx].subvendor,
6681 tx_ctl_pci_tbl[idx].subdevice,
6682 pdev1))) {
6683
6684 device_num++;
6685 }
6686 }
6687 if (!device_num) {
6688 printk("No such device\n");
6689 unregister_chrdev(major_num, DEVICE_NAME);
6690 return -1;
6691 }
6692
6693 bpctl_dev_arr = kmalloc((device_num) * sizeof(bpctl_dev_t), GFP_KERNEL);
6694
6695 if (!bpctl_dev_arr) {
6696 printk("Allocation error\n");
6697 unregister_chrdev(major_num, DEVICE_NAME);
6698 return -1;
6699 }
6700 memset(bpctl_dev_arr, 0, ((device_num) * sizeof(bpctl_dev_t)));
6701
6702 pdev1 = NULL;
6703 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6704 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6705 tx_ctl_pci_tbl[idx].device,
6706 tx_ctl_pci_tbl[idx].subvendor,
6707 tx_ctl_pci_tbl[idx].subdevice,
6708 pdev1))) {
6709 bpctl_dev_arr[idx_dev].pdev = pdev1;
6710
6711 mmio_start = pci_resource_start(pdev1, 0);
6712 mmio_len = pci_resource_len(pdev1, 0);
6713
6714 bpctl_dev_arr[idx_dev].desc =
6715 dev_desc[tx_ctl_pci_tbl[idx].index].name;
6716 bpctl_dev_arr[idx_dev].name =
6717 tx_ctl_pci_tbl[idx].bp_name;
6718 bpctl_dev_arr[idx_dev].device =
6719 tx_ctl_pci_tbl[idx].device;
6720 bpctl_dev_arr[idx_dev].vendor =
6721 tx_ctl_pci_tbl[idx].vendor;
6722 bpctl_dev_arr[idx_dev].subdevice =
6723 tx_ctl_pci_tbl[idx].subdevice;
6724 bpctl_dev_arr[idx_dev].subvendor =
6725 tx_ctl_pci_tbl[idx].subvendor;
687bcca0 6726 /* bpctl_dev_arr[idx_dev].pdev=pdev1; */
7040e556
D		 6727 bpctl_dev_arr[idx_dev].func = PCI_FUNC(pdev1->devfn);
6728 bpctl_dev_arr[idx_dev].slot = PCI_SLOT(pdev1->devfn);
6729 bpctl_dev_arr[idx_dev].bus = pdev1->bus->number;
6730 bpctl_dev_arr[idx_dev].mem_map =
6731 (unsigned long)ioremap(mmio_start, mmio_len);
6732#ifdef BP_SYNC_FLAG
6733 spin_lock_init(&bpctl_dev_arr[idx_dev].bypass_wr_lock);
6734#endif
6735 if (BP10G9_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6736 bpctl_dev_arr[idx_dev].bp_10g9 = 1;
6737 if (BP10G_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6738 bpctl_dev_arr[idx_dev].bp_10g = 1;
6739 if (PEG540_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice)) {
6740
6741 bpctl_dev_arr[idx_dev].bp_540 = 1;
6742 }
6743 if (PEGF5_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6744 bpctl_dev_arr[idx_dev].bp_fiber5 = 1;
6745 if (PEG80_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6746 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6747 if (PEGF80_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice))
6748 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6749 if ((bpctl_dev_arr[idx_dev].subdevice & 0xa00) == 0xa00)
6750 bpctl_dev_arr[idx_dev].bp_i80 = 1;
6751 if (BP10GB_IF_SERIES(bpctl_dev_arr[idx_dev].subdevice)) {
6752 if (bpctl_dev_arr[idx_dev].ifindex == 0) {
6753 unregister_chrdev(major_num,
6754 DEVICE_NAME);
6755 printk
6756 ("Please load network driver for %s adapter!\n",
6757 bpctl_dev_arr[idx_dev].name);
6758 return -1;
6759 }
6760
6761 if (bpctl_dev_arr[idx_dev].ndev) {
6762 if (!
6763 (bpctl_dev_arr[idx_dev].ndev->
6764 flags & IFF_UP)) {
6765 if (!
6766 (bpctl_dev_arr[idx_dev].
6767 ndev->flags & IFF_UP)) {
6768 unregister_chrdev
6769 (major_num,
6770 DEVICE_NAME);
6771 printk
6772 ("Please bring up network interfaces for %s adapter!\n",
6773 bpctl_dev_arr
6774 [idx_dev].name);
6775 return -1;
6776 }
6777
6778 }
6779 }
6780 bpctl_dev_arr[idx_dev].bp_10gb = 1;
6781 }
6782
6783 if (!bpctl_dev_arr[idx_dev].bp_10g9) {
6784
6785 if (is_bypass_fn(&bpctl_dev_arr[idx_dev])) {
6786 printk(KERN_INFO "%s found, ",
6787 bpctl_dev_arr[idx_dev].name);
6788 if ((OLD_IF_SERIES
6789 (bpctl_dev_arr[idx_dev].subdevice))
6790 ||
6791 (INTEL_IF_SERIES
6792 (bpctl_dev_arr[idx_dev].
6793 subdevice)))
6794 bpctl_dev_arr[idx_dev].
6795 bp_fw_ver = 0xff;
6796 else
6797 bpctl_dev_arr[idx_dev].
6798 bp_fw_ver =
6799 bypass_fw_ver(&bpctl_dev_arr
6800 [idx_dev]);
6801 if ((bpctl_dev_arr[idx_dev].bp_10gb ==
6802 1)
6803 && (bpctl_dev_arr[idx_dev].
6804 bp_fw_ver == 0xff)) {
6805 int cnt = 100;
6806 while (cnt--) {
6807 iounmap((void
6808 *)
6809 (bpctl_dev_arr
6810 [idx_dev].
6811 mem_map));
6812 mmio_start =
6813 pci_resource_start
6814 (pdev1, 0);
6815 mmio_len =
6816 pci_resource_len
6817 (pdev1, 0);
6818
6819 bpctl_dev_arr[idx_dev].
6820 mem_map =
6821 (unsigned long)
6822 ioremap(mmio_start,
6823 mmio_len);
6824
6825 bpctl_dev_arr[idx_dev].
6826 bp_fw_ver =
6827 bypass_fw_ver
6828 (&bpctl_dev_arr
6829 [idx_dev]);
6830 if (bpctl_dev_arr
6831 [idx_dev].
6832 bp_fw_ver == 0xa8)
6833 break;
6834
6835 }
6836 }
687bcca0 6837 /* bpctl_dev_arr[idx_dev].bp_fw_ver=0xa8; */
7040e556
D		 6838 printk("firmware version: 0x%x\n",
6839 bpctl_dev_arr[idx_dev].
6840 bp_fw_ver);
6841 }
6842 bpctl_dev_arr[idx_dev].wdt_status =
6843 WDT_STATUS_UNKNOWN;
6844 bpctl_dev_arr[idx_dev].reset_time = 0;
6845 atomic_set(&bpctl_dev_arr[idx_dev].wdt_busy, 0);
6846 bpctl_dev_arr[idx_dev].bp_status_un = 1;
6847
6848 bypass_caps_init(&bpctl_dev_arr[idx_dev]);
6849
6850 init_bypass_wd_auto(&bpctl_dev_arr[idx_dev]);
6851 init_bypass_tpl_auto(&bpctl_dev_arr[idx_dev]);
6852 if (NOKIA_SERIES
6853 (bpctl_dev_arr[idx_dev].subdevice))
6854 reset_cont(&bpctl_dev_arr[idx_dev]);
6855 }
6856#ifdef BP_SELF_TEST
6857 if ((bpctl_dev_arr[idx_dev].bp_tx_data =
6858 kmalloc(BPTEST_DATA_LEN, GFP_KERNEL))) {
6859
6860 memset(bpctl_dev_arr[idx_dev].bp_tx_data, 0x0,
6861 BPTEST_DATA_LEN);
6862
6863 memset(bpctl_dev_arr[idx_dev].bp_tx_data, 0xff,
6864 6);
6865 memset(bpctl_dev_arr[idx_dev].bp_tx_data + 6,
6866 0x0, 1);
6867 memset(bpctl_dev_arr[idx_dev].bp_tx_data + 7,
6868 0xaa, 5);
6869
7040e556
D		 6870 *(__be16 *) (bpctl_dev_arr[idx_dev].bp_tx_data +
6871 12) = htons(ETH_P_BPTEST);
7040e556
D		 6872
6873 } else
6874 printk("bp_ctl: Memory allocation error!\n");
6875#endif
6876 idx_dev++;
6877
6878 }
6879 }
6880 if_scan_init();
6881
6882 sema_init(&bpctl_sema, 1);
6883 spin_lock_init(&bpvm_lock);
6884 {
6885
6886 bpctl_dev_t *pbpctl_dev_c = NULL;
6887 for (idx_dev = 0;
6888 ((bpctl_dev_arr[idx_dev].pdev != NULL)
6889 && (idx_dev < device_num)); idx_dev++) {
6890 if (bpctl_dev_arr[idx_dev].bp_10g9) {
6891 pbpctl_dev_c =
6892 get_status_port_fn(&bpctl_dev_arr[idx_dev]);
6893 if (is_bypass_fn(&bpctl_dev_arr[idx_dev])) {
6894 printk(KERN_INFO "%s found, ",
6895 bpctl_dev_arr[idx_dev].name);
6896 bpctl_dev_arr[idx_dev].bp_fw_ver =
6897 bypass_fw_ver(&bpctl_dev_arr
6898 [idx_dev]);
6899 printk("firmware version: 0x%x\n",
6900 bpctl_dev_arr[idx_dev].
6901 bp_fw_ver);
6902
6903 }
6904 bpctl_dev_arr[idx_dev].wdt_status =
6905 WDT_STATUS_UNKNOWN;
6906 bpctl_dev_arr[idx_dev].reset_time = 0;
6907 atomic_set(&bpctl_dev_arr[idx_dev].wdt_busy, 0);
6908 bpctl_dev_arr[idx_dev].bp_status_un = 1;
6909
6910 bypass_caps_init(&bpctl_dev_arr[idx_dev]);
6911
6912 init_bypass_wd_auto(&bpctl_dev_arr[idx_dev]);
6913 init_bypass_tpl_auto(&bpctl_dev_arr[idx_dev]);
6914
6915 }
6916
6917 }
6918 }
6919
7040e556
D		 6920 register_netdevice_notifier(&bp_notifier_block);
6921#ifdef BP_PROC_SUPPORT
6922 {
6923 int i = 0;
687bcca0
DC		 6924 /* unsigned long flags; */
6925 /* rcu_read_lock(); */
7040e556
D		 6926 bp_proc_create();
6927 for (i = 0; i < device_num; i++) {
6928 if (bpctl_dev_arr[i].ifindex) {
687bcca0 6929 /* spin_lock_irqsave(&bpvm_lock, flags); */
7040e556
D		 6930 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
6931 bypass_proc_create_dev_sd(&bpctl_dev_arr[i]);
687bcca0 6932 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
7040e556
D		 6933 }
6934
6935 }
687bcca0 6936 /* rcu_read_unlock(); */
7040e556
D		 6937 }
6938#endif
6939
7040e556
D		 6940 return 0;
6941}
6942
6943/*
6944* Cleanup - unregister the appropriate file from /proc
6945*/
6946static void __exit bypass_cleanup_module(void)
6947{
6948 int i;
7040e556
D		 6949 unregister_netdevice_notifier(&bp_notifier_block);
6950
7040e556 6951 for (i = 0; i < device_num; i++) {
687bcca0 6952 /* unsigned long flags; */
7040e556 6953#ifdef BP_PROC_SUPPORT
687bcca0
DC		 6954/* spin_lock_irqsave(&bpvm_lock, flags);
6955 rcu_read_lock(); */
7040e556 6956 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
687bcca0
DC		 6957/* spin_unlock_irqrestore(&bpvm_lock, flags);
6958 rcu_read_unlock(); */
7040e556
D		 6959#endif
6960 remove_bypass_wd_auto(&bpctl_dev_arr[i]);
6961 bpctl_dev_arr[i].reset_time = 0;
6962
6963 remove_bypass_tpl_auto(&bpctl_dev_arr[i]);
6964 }
6965
6966 /* unmap all devices */
6967 for (i = 0; i < device_num; i++) {
6968#ifdef BP_SELF_TEST
6969 if (bpctl_dev_arr[i].bp_tx_data)
6970 kfree(bpctl_dev_arr[i].bp_tx_data);
6971#endif
6972 iounmap((void *)(bpctl_dev_arr[i].mem_map));
6973 }
6974
6975 /* free all devices space */
6976 if (bpctl_dev_arr)
6977 kfree(bpctl_dev_arr);
6978
6979/*
6980* Unregister the device
6981*/
7040e556 6982 unregister_chrdev(major_num, DEVICE_NAME);
7040e556
D		 6983}
6984
6985module_init(bypass_init_module);
6986module_exit(bypass_cleanup_module);
6987
6988int is_bypass_sd(int ifindex)
6989{
7935c80c 6990 return is_bypass(get_dev_idx_p(ifindex));
7040e556
D		 6991}
6992
6993int set_bypass_sd(int ifindex, int bypass_mode)
6994{
6995
7935c80c 6996 return set_bypass_fn(get_dev_idx_p(ifindex), bypass_mode);
7040e556
D		 6997}
6998
6999int get_bypass_sd(int ifindex)
7000{
7001
7935c80c 7002 return get_bypass_fn(get_dev_idx_p(ifindex));
7040e556
D		 7003}
7004
7005int get_bypass_change_sd(int ifindex)
7006{
7007
7935c80c 7008 return get_bypass_change_fn(get_dev_idx_p(ifindex));
7040e556
D		 7009}
7010
7011int set_dis_bypass_sd(int ifindex, int dis_param)
7012{
7935c80c 7013 return set_dis_bypass_fn(get_dev_idx_p(ifindex), dis_param);
7040e556
D		 7014}
7015
7016int get_dis_bypass_sd(int ifindex)
7017{
7018
7935c80c 7019 return get_dis_bypass_fn(get_dev_idx_p(ifindex));
7040e556
D		 7020}
7021
7022int set_bypass_pwoff_sd(int ifindex, int bypass_mode)
7023{
7935c80c 7024 return set_bypass_pwoff_fn(get_dev_idx_p(ifindex), bypass_mode);
7040e556
D		 7025
7026}
7027
7028int get_bypass_pwoff_sd(int ifindex)
7029{
7935c80c 7030 return get_bypass_pwoff_fn(get_dev_idx_p(ifindex));
7040e556
D		 7031
7032}
7033
7034int set_bypass_pwup_sd(int ifindex, int bypass_mode)
7035{
7935c80c 7036 return set_bypass_pwup_fn(get_dev_idx_p(ifindex), bypass_mode);
7040e556
D		 7037
7038}
7039
7040int get_bypass_pwup_sd(int ifindex)
7041{
7935c80c 7042 return get_bypass_pwup_fn(get_dev_idx_p(ifindex));
7040e556
D		 7043
7044}
7045
7046int set_bypass_wd_sd(int if_index, int ms_timeout, int *ms_timeout_set)
7047{
7048 if ((is_bypass(get_dev_idx_p(if_index))) <= 0)
7049 return BP_NOT_CAP;
7050 *ms_timeout_set = set_bypass_wd_fn(get_dev_idx_p(if_index), ms_timeout);
7051 return 0;
7052}
7053
7054int get_bypass_wd_sd(int ifindex, int *timeout)
7055{
7935c80c 7056 return get_bypass_wd_fn(get_dev_idx_p(ifindex), timeout);
7040e556
D		 7057
7058}
7059
7060int get_wd_expire_time_sd(int ifindex, int *time_left)
7061{
7935c80c 7062 return get_wd_expire_time_fn(get_dev_idx_p(ifindex), time_left);
7040e556
D		 7063}
7064
7065int reset_bypass_wd_timer_sd(int ifindex)
7066{
7935c80c 7067 return reset_bypass_wd_timer_fn(get_dev_idx_p(ifindex));
7040e556
D		 7068
7069}
7070
7071int get_wd_set_caps_sd(int ifindex)
7072{
7935c80c 7073 return get_wd_set_caps_fn(get_dev_idx_p(ifindex));
7040e556
D		 7074
7075}
7076
7077int set_std_nic_sd(int ifindex, int nic_mode)
7078{
7935c80c 7079 return set_std_nic_fn(get_dev_idx_p(ifindex), nic_mode);
7040e556
D		 7080
7081}
7082
7083int get_std_nic_sd(int ifindex)
7084{
7935c80c 7085 return get_std_nic_fn(get_dev_idx_p(ifindex));
7040e556
D		 7086
7087}
7088
7089int set_tap_sd(int ifindex, int tap_mode)
7090{
7935c80c 7091 return set_tap_fn(get_dev_idx_p(ifindex), tap_mode);
7040e556
D		 7092
7093}
7094
7095int get_tap_sd(int ifindex)
7096{
7935c80c 7097 return get_tap_fn(get_dev_idx_p(ifindex));
7040e556
D		 7098
7099}
7100
7101int set_tap_pwup_sd(int ifindex, int tap_mode)
7102{
7935c80c 7103 return set_tap_pwup_fn(get_dev_idx_p(ifindex), tap_mode);
7040e556
D		 7104
7105}
7106
7107int get_tap_pwup_sd(int ifindex)
7108{
7935c80c 7109 return get_tap_pwup_fn(get_dev_idx_p(ifindex));
7040e556
D		 7110
7111}
7112
7113int get_tap_change_sd(int ifindex)
7114{
7935c80c 7115 return get_tap_change_fn(get_dev_idx_p(ifindex));
7040e556
D		 7116
7117}
7118
7119int set_dis_tap_sd(int ifindex, int dis_param)
7120{
7935c80c 7121 return set_dis_tap_fn(get_dev_idx_p(ifindex), dis_param);
7040e556
D		 7122
7123}
7124
7125int get_dis_tap_sd(int ifindex)
7126{
7935c80c 7127 return get_dis_tap_fn(get_dev_idx_p(ifindex));
7040e556
D		 7128
7129}
7130
7131int set_bp_disc_sd(int ifindex, int disc_mode)
7132{
7935c80c 7133 return set_disc_fn(get_dev_idx_p(ifindex), disc_mode);
7040e556
D		 7134
7135}
7136
7137int get_bp_disc_sd(int ifindex)
7138{
7935c80c 7139 return get_disc_fn(get_dev_idx_p(ifindex));
7040e556
D		 7140
7141}
7142
7143int set_bp_disc_pwup_sd(int ifindex, int disc_mode)
7144{
7935c80c 7145 return set_disc_pwup_fn(get_dev_idx_p(ifindex), disc_mode);
7040e556
D		 7146
7147}
7148
7149int get_bp_disc_pwup_sd(int ifindex)
7150{
7935c80c 7151 return get_disc_pwup_fn(get_dev_idx_p(ifindex));
7040e556
D		 7152
7153}
7154
7155int get_bp_disc_change_sd(int ifindex)
7156{
7935c80c 7157 return get_disc_change_fn(get_dev_idx_p(ifindex));
7040e556
D		 7158
7159}
7160
7161int set_bp_dis_disc_sd(int ifindex, int dis_param)
7162{
7935c80c 7163 return set_dis_disc_fn(get_dev_idx_p(ifindex), dis_param);
7040e556
D		 7164
7165}
7166
7167int get_bp_dis_disc_sd(int ifindex)
7168{
7935c80c 7169 return get_dis_disc_fn(get_dev_idx_p(ifindex));
7040e556
D		 7170
7171}
7172
7173int get_wd_exp_mode_sd(int ifindex)
7174{
7935c80c 7175 return get_wd_exp_mode_fn(get_dev_idx_p(ifindex));
7040e556
D		 7176}
7177
7178int set_wd_exp_mode_sd(int ifindex, int param)
7179{
7935c80c 7180 return set_wd_exp_mode_fn(get_dev_idx_p(ifindex), param);
7040e556
D		 7181
7182}
7183
7184int reset_cont_sd(int ifindex)
7185{
7935c80c 7186 return reset_cont_fn(get_dev_idx_p(ifindex));
7040e556
D		 7187
7188}
7189
7190int set_tx_sd(int ifindex, int tx_state)
7191{
7935c80c 7192 return set_tx_fn(get_dev_idx_p(ifindex), tx_state);
7040e556
D		 7193
7194}
7195
7196int set_tpl_sd(int ifindex, int tpl_state)
7197{
7935c80c 7198 return set_tpl_fn(get_dev_idx_p(ifindex), tpl_state);
7040e556
D		 7199
7200}
7201
7202int set_bp_hw_reset_sd(int ifindex, int status)
7203{
7935c80c 7204 return set_bp_hw_reset_fn(get_dev_idx_p(ifindex), status);
7040e556
D		 7205
7206}
7207
7208int set_wd_autoreset_sd(int ifindex, int param)
7209{
7935c80c 7210 return set_wd_autoreset_fn(get_dev_idx_p(ifindex), param);
7040e556
D		 7211
7212}
7213
7214int get_wd_autoreset_sd(int ifindex)
7215{
7935c80c 7216 return get_wd_autoreset_fn(get_dev_idx_p(ifindex));
7040e556
D		 7217
7218}
7219
7220int get_bypass_caps_sd(int ifindex)
7221{
7935c80c 7222 return get_bypass_caps_fn(get_dev_idx_p(ifindex));
7040e556
D		 7223}
7224
7225int get_bypass_slave_sd(int ifindex)
7226{
7227 bpctl_dev_t *pbpctl_dev_out;
7228 int ret = get_bypass_slave_fn(get_dev_idx_p(ifindex), &pbpctl_dev_out);
7229 if (ret == 1)
7935c80c 7230 return pbpctl_dev_out->ifindex;
7040e556
D		 7231 return -1;
7232
7233}
7234
7235int get_tx_sd(int ifindex)
7236{
7935c80c 7237 return get_tx_fn(get_dev_idx_p(ifindex));
7040e556
D		 7238
7239}
7240
7241int get_tpl_sd(int ifindex)
7242{
7935c80c 7243 return get_tpl_fn(get_dev_idx_p(ifindex));
7040e556
D		 7244
7245}
7246
7247int get_bp_hw_reset_sd(int ifindex)
7248{
7935c80c 7249 return get_bp_hw_reset_fn(get_dev_idx_p(ifindex));
7040e556
D		 7250
7251}
7252
7253int get_bypass_info_sd(int ifindex, struct bp_info *bp_info)
7254{
7935c80c 7255 return get_bypass_info_fn(get_dev_idx_p(ifindex), bp_info->prod_name, &bp_info->fw_ver);
7040e556
D		 7256}
7257
7258int bp_if_scan_sd(void)
7259{
7260 if_scan_init();
7261 return 0;
7262}
7263
7264EXPORT_SYMBOL_NOVERS(is_bypass_sd);
7265EXPORT_SYMBOL_NOVERS(get_bypass_slave_sd);
7266EXPORT_SYMBOL_NOVERS(get_bypass_caps_sd);
7267EXPORT_SYMBOL_NOVERS(get_wd_set_caps_sd);
7268EXPORT_SYMBOL_NOVERS(set_bypass_sd);
7269EXPORT_SYMBOL_NOVERS(get_bypass_sd);
7270EXPORT_SYMBOL_NOVERS(get_bypass_change_sd);
7271EXPORT_SYMBOL_NOVERS(set_dis_bypass_sd);
7272EXPORT_SYMBOL_NOVERS(get_dis_bypass_sd);
7273EXPORT_SYMBOL_NOVERS(set_bypass_pwoff_sd);
7274EXPORT_SYMBOL_NOVERS(get_bypass_pwoff_sd);
7275EXPORT_SYMBOL_NOVERS(set_bypass_pwup_sd);
7276EXPORT_SYMBOL_NOVERS(get_bypass_pwup_sd);
7277EXPORT_SYMBOL_NOVERS(set_bypass_wd_sd);
7278EXPORT_SYMBOL_NOVERS(get_bypass_wd_sd);
7279EXPORT_SYMBOL_NOVERS(get_wd_expire_time_sd);
7280EXPORT_SYMBOL_NOVERS(reset_bypass_wd_timer_sd);
7281EXPORT_SYMBOL_NOVERS(set_std_nic_sd);
7282EXPORT_SYMBOL_NOVERS(get_std_nic_sd);
7283EXPORT_SYMBOL_NOVERS(set_tx_sd);
7284EXPORT_SYMBOL_NOVERS(get_tx_sd);
7285EXPORT_SYMBOL_NOVERS(set_tpl_sd);
7286EXPORT_SYMBOL_NOVERS(get_tpl_sd);
7287EXPORT_SYMBOL_NOVERS(set_bp_hw_reset_sd);
7288EXPORT_SYMBOL_NOVERS(get_bp_hw_reset_sd);
7289EXPORT_SYMBOL_NOVERS(set_tap_sd);
7290EXPORT_SYMBOL_NOVERS(get_tap_sd);
7291EXPORT_SYMBOL_NOVERS(get_tap_change_sd);
7292EXPORT_SYMBOL_NOVERS(set_dis_tap_sd);
7293EXPORT_SYMBOL_NOVERS(get_dis_tap_sd);
7294EXPORT_SYMBOL_NOVERS(set_tap_pwup_sd);
7295EXPORT_SYMBOL_NOVERS(get_tap_pwup_sd);
7296EXPORT_SYMBOL_NOVERS(set_wd_exp_mode_sd);
7297EXPORT_SYMBOL_NOVERS(get_wd_exp_mode_sd);
7298EXPORT_SYMBOL_NOVERS(set_wd_autoreset_sd);
7299EXPORT_SYMBOL_NOVERS(get_wd_autoreset_sd);
7300EXPORT_SYMBOL_NOVERS(set_bp_disc_sd);
7301EXPORT_SYMBOL_NOVERS(get_bp_disc_sd);
7302EXPORT_SYMBOL_NOVERS(get_bp_disc_change_sd);
7303EXPORT_SYMBOL_NOVERS(set_bp_dis_disc_sd);
7304EXPORT_SYMBOL_NOVERS(get_bp_dis_disc_sd);
7305EXPORT_SYMBOL_NOVERS(set_bp_disc_pwup_sd);
7306EXPORT_SYMBOL_NOVERS(get_bp_disc_pwup_sd);
7307EXPORT_SYMBOL_NOVERS(get_bypass_info_sd);
7308EXPORT_SYMBOL_NOVERS(bp_if_scan_sd);
7309
7310#define BP_PROC_DIR "bypass"
7311
7312#define GPIO6_SET_ENTRY_SD "gpio6_set"
7313#define GPIO6_CLEAR_ENTRY_SD "gpio6_clear"
7314
7315#define GPIO7_SET_ENTRY_SD "gpio7_set"
7316#define GPIO7_CLEAR_ENTRY_SD "gpio7_clear"
7317
7318#define PULSE_SET_ENTRY_SD "pulse_set"
7319#define ZERO_SET_ENTRY_SD "zero_set"
7320#define PULSE_GET1_ENTRY_SD "pulse_get1"
7321#define PULSE_GET2_ENTRY_SD "pulse_get2"
7322
7323#define CMND_ON_ENTRY_SD "cmnd_on"
7324#define CMND_OFF_ENTRY_SD "cmnd_off"
7325#define RESET_CONT_ENTRY_SD "reset_cont"
7326
7327 /*COMMANDS*/
7328#define BYPASS_INFO_ENTRY_SD "bypass_info"
7329#define BYPASS_SLAVE_ENTRY_SD "bypass_slave"
7330#define BYPASS_CAPS_ENTRY_SD "bypass_caps"
7331#define WD_SET_CAPS_ENTRY_SD "wd_set_caps"
7332#define BYPASS_ENTRY_SD "bypass"
7333#define BYPASS_CHANGE_ENTRY_SD "bypass_change"
7334#define BYPASS_WD_ENTRY_SD "bypass_wd"
7335#define WD_EXPIRE_TIME_ENTRY_SD "wd_expire_time"
7336#define RESET_BYPASS_WD_ENTRY_SD "reset_bypass_wd"
7337#define DIS_BYPASS_ENTRY_SD "dis_bypass"
7338#define BYPASS_PWUP_ENTRY_SD "bypass_pwup"
7339#define BYPASS_PWOFF_ENTRY_SD "bypass_pwoff"
7340#define STD_NIC_ENTRY_SD "std_nic"
7341#define STD_NIC_ENTRY_SD "std_nic"
7342#define TAP_ENTRY_SD "tap"
7343#define TAP_CHANGE_ENTRY_SD "tap_change"
7344#define DIS_TAP_ENTRY_SD "dis_tap"
7345#define TAP_PWUP_ENTRY_SD "tap_pwup"
7346#define TWO_PORT_LINK_ENTRY_SD "two_port_link"
7347#define WD_EXP_MODE_ENTRY_SD "wd_exp_mode"
7348#define WD_AUTORESET_ENTRY_SD "wd_autoreset"
7349#define TPL_ENTRY_SD "tpl"
7350#define WAIT_AT_PWUP_ENTRY_SD "wait_at_pwup"
7351#define HW_RESET_ENTRY_SD "hw_reset"
7352#define DISC_ENTRY_SD "disc"
7353#define DISC_CHANGE_ENTRY_SD "disc_change"
7354#define DIS_DISC_ENTRY_SD "dis_disc"
7355#define DISC_PWUP_ENTRY_SD "disc_pwup"
7356static struct proc_dir_entry *bp_procfs_dir;
7357
7358static struct proc_dir_entry *proc_getdir(char *name,
7359 struct proc_dir_entry *proc_dir)
7360{
7361 struct proc_dir_entry *pde = proc_dir;
7362
7363 for (pde = pde->subdir; pde; pde = pde->next) {
7364 if (pde->namelen && (strcmp(name, pde->name) == 0)) {
7365 /* directory exists */
7366 break;
7367 }
7368 }
7369 if (pde == (struct proc_dir_entry *)0) {
7370 /* create the directory */
7040e556 7371 pde = proc_mkdir(name, proc_dir);
7040e556
D		 7372 if (pde == (struct proc_dir_entry *)0) {
7373
7935c80c 7374 return pde;
7040e556
D		 7375 }
7376 }
7377
7935c80c 7378 return pde;
7040e556
D		 7379}
7380
7381int bp_proc_create(void)
7382{
7383 bp_procfs_dir = proc_getdir(BP_PROC_DIR, init_net.proc_net);
7384 if (bp_procfs_dir == (struct proc_dir_entry *)0) {
7385 printk(KERN_DEBUG
7386 "Could not create procfs nicinfo directory %s\n",
7387 BP_PROC_DIR);
7388 return -1;
7389 }
7390 return 0;
7391}
7392
7393int
7394bypass_proc_create_entry_sd(struct pfs_unit_sd *pfs_unit_curr,
7395 char *proc_name,
7c014321
DC		 7396 write_proc_t *write_proc,
7397 read_proc_t *read_proc,
7040e556
D		 7398 struct proc_dir_entry *parent_pfs, void *data)
7399{
7400 strcpy(pfs_unit_curr->proc_name, proc_name);
7401 pfs_unit_curr->proc_entry = create_proc_entry(pfs_unit_curr->proc_name,
7402 S_IFREG | S_IRUSR |
7403 S_IWUSR | S_IRGRP |
f325129a 7404 S_IROTH, parent_pfs);
0c4a9f6e 7405 if (pfs_unit_curr->proc_entry == NULL)
7040e556 7406 return -1;
7040e556
D		 7407
7408 pfs_unit_curr->proc_entry->read_proc = read_proc;
7409 pfs_unit_curr->proc_entry->write_proc = write_proc;
7410 pfs_unit_curr->proc_entry->data = data;
7411
7412 return 0;
7413
7414}
7415
7416int
7417get_bypass_info_pfs(char *page, char **start, off_t off, int count,
7418 int *eof, void *data)
7419{
7420 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7421 int len = 0;
7422
7423 len += sprintf(page, "Name\t\t\t%s\n", pbp_device_block->name);
7424 len +=
7425 sprintf(page + len, "Firmware version\t0x%x\n",
7426 pbp_device_block->bp_fw_ver);
7427
7428 *eof = 1;
7429 return len;
7430}
7431
7432int
7433get_bypass_slave_pfs(char *page, char **start, off_t off, int count,
7434 int *eof, void *data)
7435{
7436 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7437
7438 int len = 0;
f1b68d4b 7439 bpctl_dev_t *pbp_device_block_slave = get_status_port_fn(pbp_device_block);
7040e556
D		 7440 struct net_device *net_slave_dev = NULL;
7441
f1b68d4b 7442 if (!pbp_device_block_slave)
7040e556
D		 7443 pbp_device_block_slave = pbp_device_block;
7444 if (!pbp_device_block_slave) {
7445 len = sprintf(page, "fail\n");
7446 *eof = 1;
7447 return len;
7448 }
7449 net_slave_dev = pbp_device_block_slave->ndev;
b1a4fdde
AC		 7450 if (net_slave_dev)
7451 len = sprintf(page, "%s\n", net_slave_dev->name);
7040e556
D		 7452
7453 *eof = 1;
7454 return len;
7455}
7456
7457int
7458get_bypass_caps_pfs(char *page, char **start, off_t off, int count,
7459 int *eof, void *data)
7460{
7461 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7462
7463 int len = 0, ret = 0;
7464
7465 ret = get_bypass_caps_fn(pbp_device_block);
7466 if (ret == BP_NOT_CAP)
7467 len = sprintf(page, "-1\n");
7468 else
7469 len = sprintf(page, "0x%x\n", ret);
7470 *eof = 1;
7471 return len;
7472
7473}
7474
7475int
7476get_wd_set_caps_pfs(char *page, char **start, off_t off, int count,
7477 int *eof, void *data)
7478{
7479 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7480
7481 int len = 0, ret = 0;
7482
7483 ret = get_wd_set_caps_fn(pbp_device_block);
7484 if (ret == BP_NOT_CAP)
7485 len = sprintf(page, "-1\n");
7486 else
7487 len = sprintf(page, "0x%x\n", ret);
7488 *eof = 1;
7489 return len;
7490}
7491
7e1be8a5 7492static int user_on_off(const void __user *buffer, size_t count)
7040e556
D		 7493{
7494
7495 char kbuf[256];
7e1be8a5 7496 int length = 0;
7040e556
D		 7497
7498 if (count > (sizeof(kbuf) - 1))
7499 return -1;
7500
7e1be8a5 7501 if (copy_from_user(&kbuf, buffer, count))
7040e556 7502 return -1;
7040e556
D		 7503
7504 kbuf[count] = '\0';
7505 length = strlen(kbuf);
7506 if (kbuf[length - 1] == '\n')
7507 kbuf[--length] = '\0';
7508
7509 if (strcmp(kbuf, "on") == 0)
7e1be8a5
AV		 7510 return 1;
7511 if (strcmp(kbuf, "off") == 0)
7512 return 0;
7513 return 0;
7514}
7040e556 7515
7e1be8a5
AV		 7516int
7517set_bypass_pfs(struct file *file, const char *buffer,
7518 unsigned long count, void *data)
7519{
7520 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7521 int bypass_param = user_on_off(buffer, count);
7522 if (bypass_param < 0)
7523 return -1;
7040e556 7524
7e1be8a5 7525 set_bypass_fn(pbp_device_block, bypass_param);
7040e556
D		 7526 return count;
7527}
7528
7529int
7530set_tap_pfs(struct file *file, const char *buffer,
7531 unsigned long count, void *data)
7532{
7533
7040e556 7534 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 7535 int tap_param = user_on_off(buffer, count);
7536 if (tap_param < 0)
7040e556
D		 7537 return -1;
7538
7040e556 7539 set_tap_fn(pbp_device_block, tap_param);
7040e556
D		 7540 return count;
7541}
7542
7543int
7544set_disc_pfs(struct file *file, const char *buffer,
7545 unsigned long count, void *data)
7546{
7547
7040e556 7548 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 7549 int tap_param = user_on_off(buffer, count);
7550 if (tap_param < 0)
7040e556
D		 7551 return -1;
7552
7040e556 7553 set_disc_fn(pbp_device_block, tap_param);
7040e556
D		 7554 return count;
7555}
7556
7557int
7558get_bypass_pfs(char *page, char **start, off_t off, int count,
7559 int *eof, void *data)
7560{
7561 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7562
7563 int len = 0, ret = 0;
7564
7565 ret = get_bypass_fn(pbp_device_block);
7566 if (ret == BP_NOT_CAP)
7567 len = sprintf(page, "fail\n");
7568 else if (ret == 1)
7569 len = sprintf(page, "on\n");
7570 else if (ret == 0)
7571 len = sprintf(page, "off\n");
7572
7573 *eof = 1;
7574 return len;
7575}
7576
7577int
7578get_tap_pfs(char *page, char **start, off_t off, int count,
7579 int *eof, void *data)
7580{
7581 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7582
7583 int len = 0, ret = 0;
7584
7585 ret = get_tap_fn(pbp_device_block);
7586 if (ret == BP_NOT_CAP)
7587 len = sprintf(page, "fail\n");
7588 else if (ret == 1)
7589 len = sprintf(page, "on\n");
7590 else if (ret == 0)
7591 len = sprintf(page, "off\n");
7592
7593 *eof = 1;
7594 return len;
7595}
7596
7597int
7598get_disc_pfs(char *page, char **start, off_t off, int count,
7599 int *eof, void *data)
7600{
7601 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7602
7603 int len = 0, ret = 0;
7604
7605 ret = get_disc_fn(pbp_device_block);
7606 if (ret == BP_NOT_CAP)
7607 len = sprintf(page, "fail\n");
7608 else if (ret == 1)
7609 len = sprintf(page, "on\n");
7610 else if (ret == 0)
7611 len = sprintf(page, "off\n");
7612
7613 *eof = 1;
7614 return len;
7615}
7616
7617int
7618get_bypass_change_pfs(char *page, char **start, off_t off, int count,
7619 int *eof, void *data)
7620{
7621 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7622
7623 int len = 0, ret = 0;
7624
7625 ret = get_bypass_change_fn(pbp_device_block);
7626 if (ret == 1)
7627 len = sprintf(page, "on\n");
7628 else if (ret == 0)
7629 len = sprintf(page, "off\n");
7630 else
7631 len = sprintf(page, "fail\n");
7632
7633 *eof = 1;
7634 return len;
7635}
7636
7637int
7638get_tap_change_pfs(char *page, char **start, off_t off, int count,
7639 int *eof, void *data)
7640{
7641 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7642
7643 int len = 0, ret = 0;
7644
7645 ret = get_tap_change_fn(pbp_device_block);
7646 if (ret == 1)
7647 len = sprintf(page, "on\n");
7648 else if (ret == 0)
7649 len = sprintf(page, "off\n");
7650 else
7651 len = sprintf(page, "fail\n");
7652
7653 *eof = 1;
7654 return len;
7655}
7656
7657int
7658get_disc_change_pfs(char *page, char **start, off_t off, int count,
7659 int *eof, void *data)
7660{
7661 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7662
7663 int len = 0, ret = 0;
7664
7665 ret = get_disc_change_fn(pbp_device_block);
7666 if (ret == 1)
7667 len = sprintf(page, "on\n");
7668 else if (ret == 0)
7669 len = sprintf(page, "off\n");
7670 else
7671 len = sprintf(page, "fail\n");
7672
7673 *eof = 1;
7674 return len;
7675}
7676
7677#define isdigit(c) (c >= '0' && c <= '9')
7678__inline static int atoi(char **s)
7679{
7680 int i = 0;
7681 while (isdigit(**s))
7682 i = i * 10 + *((*s)++) - '0';
7683 return i;
7684}
7685
7686int
7687set_bypass_wd_pfs(struct file *file, const char *buffer,
7688 unsigned long count, void *data)
7689{
7040e556 7690 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
82e6bb03
DC		 7691 int timeout;
7692 int ret;
7040e556 7693
82e6bb03
DC		 7694 ret = kstrtoint_from_user(buffer, count, 10, &timeout);
7695 if (ret)
7696 return ret;
7040e556
D		 7697 set_bypass_wd_fn(pbp_device_block, timeout);
7698
7699 return count;
7700}
7701
7702int
7703get_bypass_wd_pfs(char *page, char **start, off_t off, int count,
7704 int *eof, void *data)
7705{
7706 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7707
7708 int len = 0, ret = 0, timeout = 0;
7709
7710 ret = get_bypass_wd_fn(pbp_device_block, &timeout);
7711 if (ret == BP_NOT_CAP)
7712 len = sprintf(page, "fail\n");
7713 else if (timeout == -1)
7714 len = sprintf(page, "unknown\n");
7715 else if (timeout == 0)
7716 len = sprintf(page, "disable\n");
7717 else
7718 len = sprintf(page, "%d\n", timeout);
7719
7720 *eof = 1;
7721 return len;
7722}
7723
7724int
7725get_wd_expire_time_pfs(char *page, char **start, off_t off, int count,
7726 int *eof, void *data)
7727{
7728 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7729
7730 int len = 0, ret = 0, timeout = 0;
7731
7732 ret = get_wd_expire_time_fn(pbp_device_block, &timeout);
7733 if (ret == BP_NOT_CAP)
7734 len = sprintf(page, "fail\n");
7735 else if (timeout == -1)
7736 len = sprintf(page, "expire\n");
7737 else if (timeout == 0)
7738 len = sprintf(page, "disable\n");
7739
7740 else
7741 len = sprintf(page, "%d\n", timeout);
7742 *eof = 1;
7743 return len;
7744}
7745
7746int
7747get_tpl_pfs(char *page, char **start, off_t off, int count,
7748 int *eof, void *data)
7749{
7750 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7751
7752 int len = 0, ret = 0;
7753
7754 ret = get_tpl_fn(pbp_device_block);
7755 if (ret == BP_NOT_CAP)
7756 len = sprintf(page, "fail\n");
7757 else if (ret == 1)
7758 len = sprintf(page, "on\n");
7759 else if (ret == 0)
7760 len = sprintf(page, "off\n");
7761
7762 *eof = 1;
7763 return len;
7764}
7765
7766#ifdef PMC_FIX_FLAG
7767int
7768get_wait_at_pwup_pfs(char *page, char **start, off_t off, int count,
7769 int *eof, void *data)
7770{
7771 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7772
7773 int len = 0, ret = 0;
7774
7775 ret = get_bp_wait_at_pwup_fn(pbp_device_block);
7776 if (ret == BP_NOT_CAP)
7777 len = sprintf(page, "fail\n");
7778 else if (ret == 1)
7779 len = sprintf(page, "on\n");
7780 else if (ret == 0)
7781 len = sprintf(page, "off\n");
7782
7783 *eof = 1;
7784 return len;
7785}
7786
7787int
7788get_hw_reset_pfs(char *page, char **start, off_t off, int count,
7789 int *eof, void *data)
7790{
7791 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7792
7793 int len = 0, ret = 0;
7794
7795 ret = get_bp_hw_reset_fn(pbp_device_block);
7796 if (ret == BP_NOT_CAP)
7797 len = sprintf(page, "fail\n");
7798 else if (ret == 1)
7799 len = sprintf(page, "on\n");
7800 else if (ret == 0)
7801 len = sprintf(page, "off\n");
7802
7803 *eof = 1;
7804 return len;
7805}
7806
7807#endif /*PMC_WAIT_FLAG */
7808
7809int
7810reset_bypass_wd_pfs(char *page, char **start, off_t off, int count,
7811 int *eof, void *data)
7812{
7813 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7814
7815 int len = 0, ret = 0;
7816
7817 ret = reset_bypass_wd_timer_fn(pbp_device_block);
7818 if (ret == BP_NOT_CAP)
7819 len = sprintf(page, "fail\n");
7820 else if (ret == 0)
7821 len = sprintf(page, "disable\n");
7822 else if (ret == 1)
7823 len = sprintf(page, "success\n");
7824
7825 *eof = 1;
7826 return len;
7827}
7828
7829int
7830set_dis_bypass_pfs(struct file *file, const char *buffer,
7831 unsigned long count, void *data)
7832{
7833
7040e556 7834 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 7835 int bypass_param = user_on_off(buffer, count);
7836 if (bypass_param < 0)
e4c536b7
DC		 7837 return -EINVAL;
7838
7040e556 7839 set_dis_bypass_fn(pbp_device_block, bypass_param);
7040e556
D		 7840 return count;
7841}
7842
7843int
7844set_dis_tap_pfs(struct file *file, const char *buffer,
7845 unsigned long count, void *data)
7846{
7847
7040e556 7848 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 7849 int tap_param = user_on_off(buffer, count);
7850 if (tap_param < 0)
e4c536b7
DC		 7851 return -EINVAL;
7852
7040e556 7853 set_dis_tap_fn(pbp_device_block, tap_param);
7040e556
D		 7854 return count;
7855}
7856
7857int
7858set_dis_disc_pfs(struct file *file, const char *buffer,
7859 unsigned long count, void *data)
7860{
7861
7040e556 7862 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 7863 int tap_param = user_on_off(buffer, count);
7864 if (tap_param < 0)
e4c536b7
DC		 7865 return -EINVAL;
7866
7040e556 7867 set_dis_disc_fn(pbp_device_block, tap_param);
7040e556
D		 7868 return count;
7869}
7870
7871int
7872get_dis_bypass_pfs(char *page, char **start, off_t off, int count,
7873 int *eof, void *data)
7874{
7875 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7876
7877 int len = 0, ret = 0;
7878
7879 ret = get_dis_bypass_fn(pbp_device_block);
7880 if (ret == BP_NOT_CAP)
7881 len = sprintf(page, "fail\n");
7882 else if (ret == 0)
7883 len = sprintf(page, "off\n");
7884 else
7885 len = sprintf(page, "on\n");
7886
7887 *eof = 1;
7888 return len;
7889}
7890
7891int
7892get_dis_tap_pfs(char *page, char **start, off_t off, int count,
7893 int *eof, void *data)
7894{
7895 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7896
7897 int len = 0, ret = 0;
7898
7899 ret = get_dis_tap_fn(pbp_device_block);
7900 if (ret == BP_NOT_CAP)
7901 len = sprintf(page, "fail\n");
7902 else if (ret == 0)
7903 len = sprintf(page, "off\n");
7904 else
7905 len = sprintf(page, "on\n");
7906
7907 *eof = 1;
7908 return len;
7909}
7910
7911int
7912get_dis_disc_pfs(char *page, char **start, off_t off, int count,
7913 int *eof, void *data)
7914{
7915 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7916
7917 int len = 0, ret = 0;
7918
7919 ret = get_dis_disc_fn(pbp_device_block);
7920 if (ret == BP_NOT_CAP)
7921 len = sprintf(page, "fail\n");
7922 else if (ret == 0)
7923 len = sprintf(page, "off\n");
7924 else
7925 len = sprintf(page, "on\n");
7926
7927 *eof = 1;
7928 return len;
7929}
7930
7931int
7932set_bypass_pwup_pfs(struct file *file, const char *buffer,
7933 unsigned long count, void *data)
7934{
7040e556 7935 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 7936 int bypass_param = user_on_off(buffer, count);
7937 if (bypass_param < 0)
e4c536b7
DC		 7938 return -EINVAL;
7939
7040e556 7940 set_bypass_pwup_fn(pbp_device_block, bypass_param);
7040e556
D		 7941 return count;
7942}
7943
7944int
7945set_bypass_pwoff_pfs(struct file *file, const char *buffer,
7946 unsigned long count, void *data)
7947{
7040e556 7948 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 7949 int bypass_param = user_on_off(buffer, count);
7950 if (bypass_param < 0)
e4c536b7
DC		 7951 return -EINVAL;
7952
7040e556 7953 set_bypass_pwoff_fn(pbp_device_block, bypass_param);
7040e556
D		 7954 return count;
7955}
7956
7957int
7958set_tap_pwup_pfs(struct file *file, const char *buffer,
7959 unsigned long count, void *data)
7960{
7040e556 7961 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 7962 int tap_param = user_on_off(buffer, count);
7963 if (tap_param < 0)
e4c536b7
DC		 7964 return -EINVAL;
7965
7040e556 7966 set_tap_pwup_fn(pbp_device_block, tap_param);
7040e556
D		 7967 return count;
7968}
7969
7970int
7971set_disc_pwup_pfs(struct file *file, const char *buffer,
7972 unsigned long count, void *data)
7973{
7040e556 7974 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 7975 int tap_param = user_on_off(buffer, count);
7976 if (tap_param < 0)
e4c536b7
DC		 7977 return -EINVAL;
7978
7040e556 7979 set_disc_pwup_fn(pbp_device_block, tap_param);
7040e556
D		 7980 return count;
7981}
7982
7983int
7984get_bypass_pwup_pfs(char *page, char **start, off_t off, int count,
7985 int *eof, void *data)
7986{
7987 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7988
7989 int len = 0, ret = 0;
7990
7991 ret = get_bypass_pwup_fn(pbp_device_block);
7992 if (ret == BP_NOT_CAP)
7993 len = sprintf(page, "fail\n");
7994 else if (ret == 0)
7995 len = sprintf(page, "off\n");
7996 else
7997 len = sprintf(page, "on\n");
7998
7999 *eof = 1;
8000 return len;
8001}
8002
8003int
8004get_bypass_pwoff_pfs(char *page, char **start, off_t off, int count,
8005 int *eof, void *data)
8006{
8007 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8008
8009 int len = 0, ret = 0;
8010
8011 ret = get_bypass_pwoff_fn(pbp_device_block);
8012 if (ret == BP_NOT_CAP)
8013 len = sprintf(page, "fail\n");
8014 else if (ret == 0)
8015 len = sprintf(page, "off\n");
8016 else
8017 len = sprintf(page, "on\n");
8018
8019 *eof = 1;
8020 return len;
8021}
8022
8023int
8024get_tap_pwup_pfs(char *page, char **start, off_t off, int count,
8025 int *eof, void *data)
8026{
8027 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8028
8029 int len = 0, ret = 0;
8030
8031 ret = get_tap_pwup_fn(pbp_device_block);
8032 if (ret == BP_NOT_CAP)
8033 len = sprintf(page, "fail\n");
8034 else if (ret == 0)
8035 len = sprintf(page, "off\n");
8036 else
8037 len = sprintf(page, "on\n");
8038
8039 *eof = 1;
8040 return len;
8041}
8042
8043int
8044get_disc_pwup_pfs(char *page, char **start, off_t off, int count,
8045 int *eof, void *data)
8046{
8047 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8048
8049 int len = 0, ret = 0;
8050
8051 ret = get_disc_pwup_fn(pbp_device_block);
8052 if (ret == BP_NOT_CAP)
8053 len = sprintf(page, "fail\n");
8054 else if (ret == 0)
8055 len = sprintf(page, "off\n");
8056 else
8057 len = sprintf(page, "on\n");
8058
8059 *eof = 1;
8060 return len;
8061}
8062
8063int
8064set_std_nic_pfs(struct file *file, const char *buffer,
8065 unsigned long count, void *data)
8066{
7040e556 8067 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 8068 int bypass_param = user_on_off(buffer, count);
8069 if (bypass_param < 0)
e4c536b7
DC		 8070 return -EINVAL;
8071
7040e556 8072 set_std_nic_fn(pbp_device_block, bypass_param);
7040e556
D		 8073 return count;
8074}
8075
8076int
8077get_std_nic_pfs(char *page, char **start, off_t off, int count,
8078 int *eof, void *data)
8079{
8080 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8081
8082 int len = 0, ret = 0;
8083
8084 ret = get_std_nic_fn(pbp_device_block);
8085 if (ret == BP_NOT_CAP)
8086 len = sprintf(page, "fail\n");
8087 else if (ret == 0)
8088 len = sprintf(page, "off\n");
8089 else
8090 len = sprintf(page, "on\n");
8091
8092 *eof = 1;
8093 return len;
8094}
8095
8096int
8097get_wd_exp_mode_pfs(char *page, char **start, off_t off, int count,
8098 int *eof, void *data)
8099{
8100 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8101
8102 int len = 0, ret = 0;
8103
8104 ret = get_wd_exp_mode_fn(pbp_device_block);
8105 if (ret == 1)
8106 len = sprintf(page, "tap\n");
8107 else if (ret == 0)
8108 len = sprintf(page, "bypass\n");
8109 else if (ret == 2)
8110 len = sprintf(page, "disc\n");
8111
8112 else
8113 len = sprintf(page, "fail\n");
8114
8115 *eof = 1;
8116 return len;
8117}
8118
8119int
8120set_wd_exp_mode_pfs(struct file *file, const char *buffer,
8121 unsigned long count, void *data)
8122{
8123
8124 char kbuf[256];
8125 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8126
8127 int bypass_param = 0, length = 0;
8128
8129 if (count > (sizeof(kbuf) - 1))
8130 return -1;
8131
8132 if (copy_from_user(&kbuf, buffer, count)) {
8133 return -1;
8134 }
8135
8136 kbuf[count] = '\0';
8137 length = strlen(kbuf);
8138 if (kbuf[length - 1] == '\n')
8139 kbuf[--length] = '\0';
8140
8141 if (strcmp(kbuf, "tap") == 0)
8142 bypass_param = 1;
8143 else if (strcmp(kbuf, "bypass") == 0)
8144 bypass_param = 0;
8145 else if (strcmp(kbuf, "disc") == 0)
8146 bypass_param = 2;
8147
8148 set_wd_exp_mode_fn(pbp_device_block, bypass_param);
8149
8150 return count;
8151}
8152
8153int
8154get_wd_autoreset_pfs(char *page, char **start, off_t off, int count,
8155 int *eof, void *data)
8156{
8157 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
8158
8159 int len = 0, ret = 0;
8160
8161 ret = get_wd_autoreset_fn(pbp_device_block);
8162 if (ret >= 0)
8163 len = sprintf(page, "%d\n", ret);
8164 else
8165 len = sprintf(page, "fail\n");
8166
8167 *eof = 1;
8168 return len;
8169}
8170
8171int
8172set_wd_autoreset_pfs(struct file *file, const char *buffer,
8173 unsigned long count, void *data)
8174{
7040e556 8175 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
82e6bb03
DC		 8176 int timeout;
8177 int ret;
7040e556 8178
82e6bb03
DC		 8179 ret = kstrtoint_from_user(buffer, count, 10, &timeout);
8180 if (ret)
8181 return ret;
7040e556
D		 8182 set_wd_autoreset_fn(pbp_device_block, timeout);
8183
8184 return count;
8185}
8186
8187int
8188set_tpl_pfs(struct file *file, const char *buffer,
8189 unsigned long count, void *data)
8190{
7040e556 8191 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 8192 int tpl_param = user_on_off(buffer, count);
8193 if (tpl_param < 0)
7040e556 8194 return -1;
7040e556
D		 8195
8196 set_tpl_fn(pbp_device_block, tpl_param);
7040e556
D		 8197 return count;
8198}
8199
8200#ifdef PMC_FIX_FLAG
8201int
8202set_wait_at_pwup_pfs(struct file *file, const char *buffer,
8203 unsigned long count, void *data)
8204{
7040e556 8205 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 8206 int tpl_param = user_on_off(buffer, count);
8207 if (tpl_param < 0)
7040e556 8208 return -1;
7040e556
D		 8209
8210 set_bp_wait_at_pwup_fn(pbp_device_block, tpl_param);
7040e556
D		 8211 return count;
8212}
8213
8214int
8215set_hw_reset_pfs(struct file *file, const char *buffer,
8216 unsigned long count, void *data)
8217{
7040e556 8218 bpctl_dev_t *pbp_device_block = (bpctl_dev_t *) data;
7e1be8a5
AV		 8219 int tpl_param = user_on_off(buffer, count);
8220 if (tpl_param < 0)
7040e556 8221 return -1;
7040e556
D		 8222
8223 set_bp_hw_reset_fn(pbp_device_block, tpl_param);
7040e556
D		 8224 return count;
8225}
8226
8227#endif /*PMC_FIX_FLAG */
8228
7c014321 8229int bypass_proc_create_dev_sd(bpctl_dev_t *pbp_device_block)
7040e556
D		 8230{
8231 struct bypass_pfs_sd *current_pfs = &(pbp_device_block->bypass_pfs_set);
8232 static struct proc_dir_entry *procfs_dir = NULL;
8233 int ret = 0;
8234
8235 if (!pbp_device_block->ndev)
8236 return -1;
8237 sprintf(current_pfs->dir_name, "bypass_%s",
8238 pbp_device_block->ndev->name);
8239
8240 if (!bp_procfs_dir)
8241 return -1;
8242
8243 /* create device proc dir */
8244 procfs_dir = proc_getdir(current_pfs->dir_name, bp_procfs_dir);
8245 if (procfs_dir == 0) {
8246 printk(KERN_DEBUG "Could not create procfs directory %s\n",
8247 current_pfs->dir_name);
8248 return -1;
8249 }
8250 current_pfs->bypass_entry = procfs_dir;
8251
8252 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_info), BYPASS_INFO_ENTRY_SD, NULL, /* write */
8253 get_bypass_info_pfs, /* read */
8254 procfs_dir, pbp_device_block))
8255 ret = -1;
8256
8257 if (pbp_device_block->bp_caps & SW_CTL_CAP) {
8258
8259 /* Create set param proc's */
8260 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_slave), BYPASS_SLAVE_ENTRY_SD, NULL, /* write */
8261 get_bypass_slave_pfs, /* read */
8262 procfs_dir, pbp_device_block))
8263 ret = -1;
8264
8265 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_caps), BYPASS_CAPS_ENTRY_SD, NULL, /* write */
8266 get_bypass_caps_pfs, /* read */
8267 procfs_dir, pbp_device_block))
8268 ret = -1;
8269
8270 if (bypass_proc_create_entry_sd(&(current_pfs->wd_set_caps), WD_SET_CAPS_ENTRY_SD, NULL, /* write */
8271 get_wd_set_caps_pfs, /* read */
8272 procfs_dir, pbp_device_block))
8273 ret = -1;
8274 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_wd), BYPASS_WD_ENTRY_SD, set_bypass_wd_pfs, /* write */
8275 get_bypass_wd_pfs, /* read */
8276 procfs_dir, pbp_device_block))
8277 ret = -1;
8278
8279 if (bypass_proc_create_entry_sd(&(current_pfs->wd_expire_time), WD_EXPIRE_TIME_ENTRY_SD, NULL, /* write */
8280 get_wd_expire_time_pfs, /* read */
8281 procfs_dir, pbp_device_block))
8282 ret = -1;
8283
8284 if (bypass_proc_create_entry_sd(&(current_pfs->reset_bypass_wd), RESET_BYPASS_WD_ENTRY_SD, NULL, /* write */
8285 reset_bypass_wd_pfs, /* read */
8286 procfs_dir, pbp_device_block))
8287 ret = -1;
8288
8289 if (bypass_proc_create_entry_sd(&(current_pfs->std_nic), STD_NIC_ENTRY_SD, set_std_nic_pfs, /* write */
8290 get_std_nic_pfs, /* read */
8291 procfs_dir, pbp_device_block))
8292 ret = -1;
8293
8294 if (pbp_device_block->bp_caps & BP_CAP) {
8295 if (bypass_proc_create_entry_sd(&(current_pfs->bypass), BYPASS_ENTRY_SD, set_bypass_pfs, /* write */
8296 get_bypass_pfs, /* read */
8297 procfs_dir,
8298 pbp_device_block))
8299 ret = -1;
8300
8301 if (bypass_proc_create_entry_sd(&(current_pfs->dis_bypass), DIS_BYPASS_ENTRY_SD, set_dis_bypass_pfs, /* write */
8302 get_dis_bypass_pfs, /* read */
8303 procfs_dir,
8304 pbp_device_block))
8305 ret = -1;
8306
8307 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_pwup), BYPASS_PWUP_ENTRY_SD, set_bypass_pwup_pfs, /* write */
8308 get_bypass_pwup_pfs, /* read */
8309 procfs_dir,
8310 pbp_device_block))
8311 ret = -1;
8312 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_pwoff), BYPASS_PWOFF_ENTRY_SD, set_bypass_pwoff_pfs, /* write */
8313 get_bypass_pwoff_pfs, /* read */
8314 procfs_dir,
8315 pbp_device_block))
8316 ret = -1;
8317
8318 if (bypass_proc_create_entry_sd(&(current_pfs->bypass_change), BYPASS_CHANGE_ENTRY_SD, NULL, /* write */
8319 get_bypass_change_pfs, /* read */
8320 procfs_dir,
8321 pbp_device_block))
8322 ret = -1;
8323 }
8324
8325 if (pbp_device_block->bp_caps & TAP_CAP) {
8326
8327 if (bypass_proc_create_entry_sd(&(current_pfs->tap), TAP_ENTRY_SD, set_tap_pfs, /* write */
8328 get_tap_pfs, /* read */
8329 procfs_dir,
8330 pbp_device_block))
8331 ret = -1;
8332
8333 if (bypass_proc_create_entry_sd(&(current_pfs->dis_tap), DIS_TAP_ENTRY_SD, set_dis_tap_pfs, /* write */
8334 get_dis_tap_pfs, /* read */
8335 procfs_dir,
8336 pbp_device_block))
8337 ret = -1;
8338
8339 if (bypass_proc_create_entry_sd(&(current_pfs->tap_pwup), TAP_PWUP_ENTRY_SD, set_tap_pwup_pfs, /* write */
8340 get_tap_pwup_pfs, /* read */
8341 procfs_dir,
8342 pbp_device_block))
8343 ret = -1;
8344
8345 if (bypass_proc_create_entry_sd(&(current_pfs->tap_change), TAP_CHANGE_ENTRY_SD, NULL, /* write */
8346 get_tap_change_pfs, /* read */
8347 procfs_dir,
8348 pbp_device_block))
8349 ret = -1;
8350 }
8351 if (pbp_device_block->bp_caps & DISC_CAP) {
8352
8353 if (bypass_proc_create_entry_sd(&(current_pfs->tap), DISC_ENTRY_SD, set_disc_pfs, /* write */
8354 get_disc_pfs, /* read */
8355 procfs_dir,
8356 pbp_device_block))
8357 ret = -1;
8358#if 1
8359
8360 if (bypass_proc_create_entry_sd(&(current_pfs->dis_tap), DIS_DISC_ENTRY_SD, set_dis_disc_pfs, /* write */
8361 get_dis_disc_pfs, /* read */
8362 procfs_dir,
8363 pbp_device_block))
8364 ret = -1;
8365#endif
8366
8367 if (bypass_proc_create_entry_sd(&(current_pfs->tap_pwup), DISC_PWUP_ENTRY_SD, set_disc_pwup_pfs, /* write */
8368 get_disc_pwup_pfs, /* read */
8369 procfs_dir,
8370 pbp_device_block))
8371 ret = -1;
8372
8373 if (bypass_proc_create_entry_sd(&(current_pfs->tap_change), DISC_CHANGE_ENTRY_SD, NULL, /* write */
8374 get_disc_change_pfs, /* read */
8375 procfs_dir,
8376 pbp_device_block))
8377 ret = -1;
8378 }
8379
8380 if (bypass_proc_create_entry_sd(&(current_pfs->wd_exp_mode), WD_EXP_MODE_ENTRY_SD, set_wd_exp_mode_pfs, /* write */
8381 get_wd_exp_mode_pfs, /* read */
8382 procfs_dir, pbp_device_block))
8383 ret = -1;
8384
8385 if (bypass_proc_create_entry_sd(&(current_pfs->wd_autoreset), WD_AUTORESET_ENTRY_SD, set_wd_autoreset_pfs, /* write */
8386 get_wd_autoreset_pfs, /* read */
8387 procfs_dir, pbp_device_block))
8388 ret = -1;
8389 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), TPL_ENTRY_SD, set_tpl_pfs, /* write */
8390 get_tpl_pfs, /* read */
8391 procfs_dir, pbp_device_block))
8392 ret = -1;
8393#ifdef PMC_FIX_FLAG
8394 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), WAIT_AT_PWUP_ENTRY_SD, set_wait_at_pwup_pfs, /* write */
8395 get_wait_at_pwup_pfs, /* read */
8396 procfs_dir, pbp_device_block))
8397 ret = -1;
8398 if (bypass_proc_create_entry_sd(&(current_pfs->tpl), HW_RESET_ENTRY_SD, set_hw_reset_pfs, /* write */
8399 get_hw_reset_pfs, /* read */
8400 procfs_dir, pbp_device_block))
8401 ret = -1;
8402
8403#endif
8404
8405 }
8406 if (ret < 0)
8407 printk(KERN_DEBUG "Create proc entry failed\n");
8408
8409 return ret;
8410}
8411
7c014321 8412int bypass_proc_remove_dev_sd(bpctl_dev_t *pbp_device_block)
7040e556
D		 8413{
8414
8415 struct bypass_pfs_sd *current_pfs = &pbp_device_block->bypass_pfs_set;
8416 struct proc_dir_entry *pde = current_pfs->bypass_entry, *pde_curr =
8417 NULL;
8418 char name[256];
8419
8420 if (!pde)
8421 return 0;
8422 for (pde = pde->subdir; pde;) {
8423 strcpy(name, pde->name);
8424 pde_curr = pde;
8425 pde = pde->next;
8426 remove_proc_entry(name, current_pfs->bypass_entry);
8427 }
8428 if (!pde)
8429 remove_proc_entry(current_pfs->dir_name, bp_procfs_dir);
8430 current_pfs->bypass_entry = NULL;
8431
8432 return 0;
8433}
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