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7040e556
D		 1/******************************************************************************/
2/* */
3/* Bypass Control utility, Copyright (c) 2005-20011 Silicom */
4/* */
5/* This program is free software; you can redistribute it and/or modify */
6/* it under the terms of the GNU General Public License as published by */
7/* the Free Software Foundation, located in the file LICENSE. */
8/* Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. */
9/* */
10/* */
11/******************************************************************************/
7040e556
D		 12
13#include <linux/kernel.h> /* We're doing kernel work */
14#include <linux/module.h> /* Specifically, a module */
15#include <linux/fs.h>
16#include <linux/pci.h>
17#include <linux/delay.h>
18#include <linux/netdevice.h>
19#include <linux/rtnetlink.h>
20#include <linux/rcupdate.h>
21#include <linux/etherdevice.h>
22
86bc9ebb 23#include <linux/uaccess.h> /* for get_user and put_user */
7040e556
D		 24#include <linux/sched.h>
25#include <linux/ethtool.h>
26#include <linux/proc_fs.h>
27
28#include "bp_ioctl.h"
29#include "bp_mod.h"
30#include "bypass.h"
31#include "libbp_sd.h"
32
33#define SUCCESS 0
34#define BP_MOD_VER "9.0.4"
35#define BP_MOD_DESCR "Silicom Bypass-SD Control driver"
36#define BP_SYNC_FLAG 1
37
38static int Device_Open = 0;
39static int major_num = 0;
40
41MODULE_AUTHOR("Anna Lukin, annal@silicom.co.il");
42MODULE_LICENSE("GPL");
43MODULE_DESCRIPTION(BP_MOD_DESCR);
44MODULE_VERSION(BP_MOD_VER);
45spinlock_t bpvm_lock;
46
47#define lock_bpctl() \
48if (down_interruptible(&bpctl_sema)) { \
49 return -ERESTARTSYS; \
50} \
51
52#define unlock_bpctl() \
53 up(&bpctl_sema);
54
55/* Media Types */
56typedef enum {
57 bp_copper = 0,
58 bp_fiber,
59 bp_cx4,
60 bp_none,
61} bp_media_type;
62
7040e556
D		 63struct bypass_pfs_sd {
64 char dir_name[32];
65 struct proc_dir_entry *bypass_entry;
7040e556
D		 66};
67
68typedef struct _bpctl_dev {
69 char *name;
70 char *desc;
71 struct pci_dev *pdev; /* PCI device */
72 struct net_device *ndev; /* net device */
73 unsigned long mem_map;
74 uint8_t bus;
75 uint8_t slot;
76 uint8_t func;
77 u_int32_t device;
78 u_int32_t vendor;
79 u_int32_t subvendor;
80 u_int32_t subdevice;
81 int ifindex;
82 uint32_t bp_caps;
83 uint32_t bp_caps_ex;
84 uint8_t bp_fw_ver;
85 int bp_ext_ver;
86 int wdt_status;
87 unsigned long bypass_wdt_on_time;
88 uint32_t bypass_timer_interval;
89 struct timer_list bp_timer;
90 uint32_t reset_time;
91 uint8_t bp_status_un;
92 atomic_t wdt_busy;
93 bp_media_type media_type;
94 int bp_tpl_flag;
95 struct timer_list bp_tpl_timer;
96 spinlock_t bypass_wr_lock;
97 int bp_10g;
98 int bp_10gb;
99 int bp_fiber5;
100 int bp_10g9;
101 int bp_i80;
102 int bp_540;
01448bbb
DC		 103 int (*hard_start_xmit_save) (struct sk_buff *skb,
104 struct net_device *dev);
7040e556
D		 105 const struct net_device_ops *old_ops;
106 struct net_device_ops new_ops;
107 int bp_self_test_flag;
108 char *bp_tx_data;
7040e556
D		 109 struct bypass_pfs_sd bypass_pfs_set;
110
111} bpctl_dev_t;
112
113static bpctl_dev_t *bpctl_dev_arr;
114
115static struct semaphore bpctl_sema;
116static int device_num = 0;
117
118static int get_dev_idx(int ifindex);
01448bbb
DC		 119static bpctl_dev_t *get_master_port_fn(bpctl_dev_t *pbpctl_dev);
120static int disc_status(bpctl_dev_t *pbpctl_dev);
121static int bypass_status(bpctl_dev_t *pbpctl_dev);
122static int wdt_timer(bpctl_dev_t *pbpctl_dev, int *time_left);
123static bpctl_dev_t *get_status_port_fn(bpctl_dev_t *pbpctl_dev);
7040e556
D		 124static void if_scan_init(void);
125
01448bbb
DC		 126int bypass_proc_create_dev_sd(bpctl_dev_t *pbp_device_block);
127int bypass_proc_remove_dev_sd(bpctl_dev_t *pbp_device_block);
7040e556
D		 128int bp_proc_create(void);
129
01448bbb 130int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
7040e556
D		 131int get_dev_idx_bsf(int bus, int slot, int func);
132
133static unsigned long str_to_hex(char *p);
134static int bp_device_event(struct notifier_block *unused,
135 unsigned long event, void *ptr)
136{
137 struct net_device *dev = ptr;
138 static bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
139 int dev_num = 0, ret = 0, ret_d = 0, time_left = 0;
687bcca0
DC		 140 /* printk("BP_PROC_SUPPORT event =%d %s %d\n", event,dev->name, dev->ifindex ); */
141 /* return NOTIFY_DONE; */
7040e556
D		 142 if (!dev)
143 return NOTIFY_DONE;
144 if (event == NETDEV_REGISTER) {
145 {
146 struct ethtool_drvinfo drvinfo;
7040e556
D		 147 char cbuf[32];
148 char *buf = NULL;
149 char res[10];
150 int i = 0, ifindex, idx_dev = 0;
151 int bus = 0, slot = 0, func = 0;
152 ifindex = dev->ifindex;
153
154 memset(res, 0, 10);
155 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
156
157 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
158 memset(&drvinfo, 0, sizeof(drvinfo));
159 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
160 } else
161 return NOTIFY_DONE;
162 if (!drvinfo.bus_info)
163 return NOTIFY_DONE;
164 if (!strcmp(drvinfo.bus_info, "N/A"))
165 return NOTIFY_DONE;
166 memcpy(&cbuf, drvinfo.bus_info, 32);
167 buf = &cbuf[0];
168
7040e556
D		 169 while (*buf++ != ':') ;
170 for (i = 0; i < 10; i++, buf++) {
171 if (*buf == ':')
172 break;
173 res[i] = *buf;
174
175 }
176 buf++;
177 bus = str_to_hex(res);
178 memset(res, 0, 10);
179
180 for (i = 0; i < 10; i++, buf++) {
181 if (*buf == '.')
182 break;
183 res[i] = *buf;
184
185 }
186 buf++;
187 slot = str_to_hex(res);
188 func = str_to_hex(buf);
189 idx_dev = get_dev_idx_bsf(bus, slot, func);
190
191 if (idx_dev != -1) {
192
193 bpctl_dev_arr[idx_dev].ifindex = ifindex;
194 bpctl_dev_arr[idx_dev].ndev = dev;
195
196 bypass_proc_remove_dev_sd(&bpctl_dev_arr
197 [idx_dev]);
198 bypass_proc_create_dev_sd(&bpctl_dev_arr
199 [idx_dev]);
200
201 }
202
203 }
204 return NOTIFY_DONE;
205
206 }
207 if (event == NETDEV_UNREGISTER) {
208 int idx_dev = 0;
7040e556
D		 209 for (idx_dev = 0;
210 ((bpctl_dev_arr[idx_dev].pdev != NULL)
211 && (idx_dev < device_num)); idx_dev++) {
212 if (bpctl_dev_arr[idx_dev].ndev == dev) {
213 bypass_proc_remove_dev_sd(&bpctl_dev_arr
214 [idx_dev]);
215 bpctl_dev_arr[idx_dev].ndev = NULL;
216
217 return NOTIFY_DONE;
218
219 }
220
221 }
222 return NOTIFY_DONE;
223 }
224 if (event == NETDEV_CHANGENAME) {
225 int idx_dev = 0;
7040e556
D		 226 for (idx_dev = 0;
227 ((bpctl_dev_arr[idx_dev].pdev != NULL)
228 && (idx_dev < device_num)); idx_dev++) {
229 if (bpctl_dev_arr[idx_dev].ndev == dev) {
230 bypass_proc_remove_dev_sd(&bpctl_dev_arr
231 [idx_dev]);
232 bypass_proc_create_dev_sd(&bpctl_dev_arr
233 [idx_dev]);
234
235 return NOTIFY_DONE;
236
237 }
238
239 }
240 return NOTIFY_DONE;
241
242 }
7040e556
D		 243
244 switch (event) {
245
246 case NETDEV_CHANGE:{
247 if (netif_carrier_ok(dev))
248 return NOTIFY_DONE;
249
7040e556
D		 250 if (((dev_num = get_dev_idx(dev->ifindex)) == -1) ||
251 (!(pbpctl_dev = &bpctl_dev_arr[dev_num])))
252 return NOTIFY_DONE;
253
254 if ((is_bypass_fn(pbpctl_dev)) == 1)
255 pbpctl_dev_m = pbpctl_dev;
256 else
257 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
258 if (!pbpctl_dev_m)
259 return NOTIFY_DONE;
260 ret = bypass_status(pbpctl_dev_m);
261 if (ret == 1)
262 printk("bpmod: %s is in the Bypass mode now",
263 dev->name);
264 ret_d = disc_status(pbpctl_dev_m);
265 if (ret_d == 1)
266 printk
267 ("bpmod: %s is in the Disconnect mode now",
268 dev->name);
269 if (ret || ret_d) {
270 wdt_timer(pbpctl_dev_m, &time_left);
271 if (time_left == -1)
272 printk("; WDT has expired");
273 printk(".\n");
274
275 }
276 return NOTIFY_DONE;
277
278 }
279
280 default:
281 return NOTIFY_DONE;
282
283 }
284 return NOTIFY_DONE;
285
286}
287
288static struct notifier_block bp_notifier_block = {
289 .notifier_call = bp_device_event,
290};
291
292static int device_open(struct inode *inode, struct file *file)
293{
294#ifdef DEBUG
295 printk("device_open(%p)\n", file);
296#endif
297 Device_Open++;
298/*
299* Initialize the message
300*/
301 return SUCCESS;
302}
303
304static int device_release(struct inode *inode, struct file *file)
305{
306#ifdef DEBUG
307 printk("device_release(%p,%p)\n", inode, file);
308#endif
309 Device_Open--;
310 return SUCCESS;
311}
312
01448bbb
DC		 313int is_bypass_fn(bpctl_dev_t *pbpctl_dev);
314int wdt_time_left(bpctl_dev_t *pbpctl_dev);
7040e556 315
01448bbb 316static void write_pulse(bpctl_dev_t *pbpctl_dev,
7040e556
D		 317 unsigned int ctrl_ext,
318 unsigned char value, unsigned char len)
319{
320 unsigned char ctrl_val = 0;
321 unsigned int i = len;
322 unsigned int ctrl = 0;
323 bpctl_dev_t *pbpctl_dev_c = NULL;
324
325 if (pbpctl_dev->bp_i80)
326 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
327 if (pbpctl_dev->bp_540)
328 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
329
330 if (pbpctl_dev->bp_10g9) {
331 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
332 return;
333 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
334 }
335
336 while (i--) {
337 ctrl_val = (value >> i) & 0x1;
338 if (ctrl_val) {
339 if (pbpctl_dev->bp_10g9) {
340
341 /* To start management : MCLK 1, MDIO 1, output */
342 /* DATA 1 CLK 1 */
343 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
344 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
345 ctrl_ext |
346 BP10G_MDIO_DATA_OUT9);
347 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
348 (ctrl | BP10G_MCLK_DATA_OUT9 |
349 BP10G_MCLK_DIR_OUT9));
350
351 } else if (pbpctl_dev->bp_fiber5) {
352 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
353 BPCTLI_CTRL_EXT_MCLK_DIR5
354 |
355 BPCTLI_CTRL_EXT_MDIO_DIR5
356 |
357 BPCTLI_CTRL_EXT_MDIO_DATA5
358 |
359 BPCTLI_CTRL_EXT_MCLK_DATA5));
360
361 } else if (pbpctl_dev->bp_i80) {
362 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
363 BPCTLI_CTRL_EXT_MDIO_DIR80
364 |
365 BPCTLI_CTRL_EXT_MDIO_DATA80));
366
367 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, (ctrl |
368 BPCTLI_CTRL_EXT_MCLK_DIR80
369 |
370 BPCTLI_CTRL_EXT_MCLK_DATA80));
371
372 } else if (pbpctl_dev->bp_540) {
373 BP10G_WRITE_REG(pbpctl_dev, ESDP, (ctrl |
374 BP540_MDIO_DIR
375 |
376 BP540_MDIO_DATA
377 |
378 BP540_MCLK_DIR
379 |
380 BP540_MCLK_DATA));
381
382 } else if (pbpctl_dev->bp_10gb) {
383 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
384 (ctrl_ext | BP10GB_MDIO_SET |
385 BP10GB_MCLK_SET) &
386 ~(BP10GB_MCLK_DIR |
387 BP10GB_MDIO_DIR |
388 BP10GB_MDIO_CLR |
389 BP10GB_MCLK_CLR));
390
391 } else if (!pbpctl_dev->bp_10g)
392 /* To start management : MCLK 1, MDIO 1, output */
393 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
394 (ctrl_ext |
395 BPCTLI_CTRL_EXT_MCLK_DIR |
396 BPCTLI_CTRL_EXT_MDIO_DIR |
397 BPCTLI_CTRL_EXT_MDIO_DATA |
398 BPCTLI_CTRL_EXT_MCLK_DATA));
399 else {
400
687bcca0 401 /* To start management : MCLK 1, MDIO 1, output*/
7040e556
D		 402 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
403 (ctrl_ext | BP10G_MCLK_DATA_OUT
404 | BP10G_MDIO_DATA_OUT));
7040e556
D		 405
406 }
407
408 usec_delay(PULSE_TIME);
409 if (pbpctl_dev->bp_10g9) {
410
411 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~(BP10G_MCLK_DATA_OUT9))); */
412 /* DATA 1 CLK 0 */
413 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
414 ctrl_ext |
415 BP10G_MDIO_DATA_OUT9);
416 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
417 (ctrl | BP10G_MCLK_DIR_OUT9) &
418 ~BP10G_MCLK_DATA_OUT9);
419
420 } else if (pbpctl_dev->bp_fiber5) {
421 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
422 ((ctrl_ext |
423 BPCTLI_CTRL_EXT_MCLK_DIR5 |
424 BPCTLI_CTRL_EXT_MDIO_DIR5 |
425 BPCTLI_CTRL_EXT_MDIO_DATA5)
426 &
427 ~
428 (BPCTLI_CTRL_EXT_MCLK_DATA5)));
429
430 } else if (pbpctl_dev->bp_i80) {
431 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, (ctrl_ext |
432 BPCTLI_CTRL_EXT_MDIO_DIR80
433 |
434 BPCTLI_CTRL_EXT_MDIO_DATA80));
435 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
436 ((ctrl |
437 BPCTLI_CTRL_EXT_MCLK_DIR80)
438 &
439 ~
440 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
441
442 } else if (pbpctl_dev->bp_540) {
443 BP10G_WRITE_REG(pbpctl_dev, ESDP,
444 (ctrl | BP540_MDIO_DIR |
445 BP540_MDIO_DATA |
446 BP540_MCLK_DIR) &
447 ~(BP540_MCLK_DATA));
448
449 } else if (pbpctl_dev->bp_10gb) {
450
451 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
452 (ctrl_ext | BP10GB_MDIO_SET |
453 BP10GB_MCLK_CLR) &
454 ~(BP10GB_MCLK_DIR |
455 BP10GB_MDIO_DIR |
456 BP10GB_MDIO_CLR |
457 BP10GB_MCLK_SET));
458
459 } else if (!pbpctl_dev->bp_10g)
460
461 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
462 ((ctrl_ext |
463 BPCTLI_CTRL_EXT_MCLK_DIR |
464 BPCTLI_CTRL_EXT_MDIO_DIR |
465 BPCTLI_CTRL_EXT_MDIO_DATA)
466 &
467 ~
468 (BPCTLI_CTRL_EXT_MCLK_DATA)));
469 else {
470
7040e556
D		 471 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
472 ((ctrl_ext |
473 BP10G_MDIO_DATA_OUT) &
474 ~(BP10G_MCLK_DATA_OUT)));
7040e556
D		 475 }
476
477 usec_delay(PULSE_TIME);
478
479 } else {
480 if (pbpctl_dev->bp_10g9) {
481 /* DATA 0 CLK 1 */
482 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
483 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
484 (ctrl_ext &
485 ~BP10G_MDIO_DATA_OUT9));
486 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
487 (ctrl | BP10G_MCLK_DATA_OUT9 |
488 BP10G_MCLK_DIR_OUT9));
489
490 } else if (pbpctl_dev->bp_fiber5) {
491 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
492 ((ctrl_ext |
493 BPCTLI_CTRL_EXT_MCLK_DIR5 |
494 BPCTLI_CTRL_EXT_MDIO_DIR5 |
495 BPCTLI_CTRL_EXT_MCLK_DATA5)
496 &
497 ~
498 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
499
500 } else if (pbpctl_dev->bp_i80) {
501 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
502 ((ctrl_ext |
503 BPCTLI_CTRL_EXT_MDIO_DIR80)
504 &
505 ~
506 (BPCTLI_CTRL_EXT_MDIO_DATA80)));
507 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
508 (ctrl |
509 BPCTLI_CTRL_EXT_MCLK_DIR80 |
510 BPCTLI_CTRL_EXT_MCLK_DATA80));
511
512 } else if (pbpctl_dev->bp_540) {
513 BP10G_WRITE_REG(pbpctl_dev, ESDP,
514 ((ctrl | BP540_MCLK_DIR |
515 BP540_MCLK_DATA |
516 BP540_MDIO_DIR) &
517 ~(BP540_MDIO_DATA)));
518
519 } else if (pbpctl_dev->bp_10gb) {
520 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
521 (ctrl_ext | BP10GB_MDIO_CLR |
522 BP10GB_MCLK_SET) &
523 ~(BP10GB_MCLK_DIR |
524 BP10GB_MDIO_DIR |
525 BP10GB_MDIO_SET |
526 BP10GB_MCLK_CLR));
527
528 } else if (!pbpctl_dev->bp_10g)
529
530 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
531 ((ctrl_ext |
532 BPCTLI_CTRL_EXT_MCLK_DIR |
533 BPCTLI_CTRL_EXT_MDIO_DIR |
534 BPCTLI_CTRL_EXT_MCLK_DATA)
535 &
536 ~
537 (BPCTLI_CTRL_EXT_MDIO_DATA)));
538 else {
539
7040e556
D		 540 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
541 ((ctrl_ext |
542 BP10G_MCLK_DATA_OUT) &
543 ~BP10G_MDIO_DATA_OUT));
7040e556
D		 544
545 }
546 usec_delay(PULSE_TIME);
547 if (pbpctl_dev->bp_10g9) {
548 /* DATA 0 CLK 0 */
549 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
550 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
551 (ctrl_ext &
552 ~BP10G_MDIO_DATA_OUT9));
553 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
554 ((ctrl | BP10G_MCLK_DIR_OUT9) &
555 ~(BP10G_MCLK_DATA_OUT9)));
556
557 } else if (pbpctl_dev->bp_fiber5) {
558 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
559 ((ctrl_ext |
560 BPCTLI_CTRL_EXT_MCLK_DIR5 |
561 BPCTLI_CTRL_EXT_MDIO_DIR5)
562 &
563 ~(BPCTLI_CTRL_EXT_MCLK_DATA5
564 |
565 BPCTLI_CTRL_EXT_MDIO_DATA5)));
566
567 } else if (pbpctl_dev->bp_i80) {
568 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
569 ((ctrl_ext |
570 BPCTLI_CTRL_EXT_MDIO_DIR80)
571 &
572 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
573 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
574 ((ctrl |
575 BPCTLI_CTRL_EXT_MCLK_DIR80)
576 &
577 ~
578 (BPCTLI_CTRL_EXT_MCLK_DATA80)));
579
580 } else if (pbpctl_dev->bp_540) {
581 BP10G_WRITE_REG(pbpctl_dev, ESDP,
582 ((ctrl | BP540_MCLK_DIR |
583 BP540_MDIO_DIR) &
584 ~(BP540_MDIO_DATA |
585 BP540_MCLK_DATA)));
586 } else if (pbpctl_dev->bp_10gb) {
587
588 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
589 (ctrl_ext | BP10GB_MDIO_CLR |
590 BP10GB_MCLK_CLR) &
591 ~(BP10GB_MCLK_DIR |
592 BP10GB_MDIO_DIR |
593 BP10GB_MDIO_SET |
594 BP10GB_MCLK_SET));
595
596 } else if (!pbpctl_dev->bp_10g)
597 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
598 ((ctrl_ext |
599 BPCTLI_CTRL_EXT_MCLK_DIR |
600 BPCTLI_CTRL_EXT_MDIO_DIR) &
601 ~(BPCTLI_CTRL_EXT_MCLK_DATA
602 |
603 BPCTLI_CTRL_EXT_MDIO_DATA)));
604 else {
605
7040e556
D		 606 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
607 (ctrl_ext &
608 ~(BP10G_MCLK_DATA_OUT |
609 BP10G_MDIO_DATA_OUT)));
7040e556
D		 610 }
611
612 usec_delay(PULSE_TIME);
613 }
614
615 }
616}
617
01448bbb 618static int read_pulse(bpctl_dev_t *pbpctl_dev, unsigned int ctrl_ext,
7040e556
D		 619 unsigned char len)
620{
621 unsigned char ctrl_val = 0;
622 unsigned int i = len;
623 unsigned int ctrl = 0;
624 bpctl_dev_t *pbpctl_dev_c = NULL;
625
626 if (pbpctl_dev->bp_i80)
627 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
628 if (pbpctl_dev->bp_540)
629 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
630 if (pbpctl_dev->bp_10g9) {
631 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
632 return -1;
633 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
634 }
635
7040e556
D		 636
637 while (i--) {
638 if (pbpctl_dev->bp_10g9) {
639 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MDIO_DATA_OUT9)&~BP10G_MCLK_DATA_OUT9)); */
640 /* DATA ? CLK 0 */
641 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
642 ((ctrl | BP10G_MCLK_DIR_OUT9) &
643 ~(BP10G_MCLK_DATA_OUT9)));
644
645 } else if (pbpctl_dev->bp_fiber5) {
646 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
647 BPCTLI_CTRL_EXT_MCLK_DIR5)
648 &
649 ~
650 (BPCTLI_CTRL_EXT_MDIO_DIR5
651 |
652 BPCTLI_CTRL_EXT_MCLK_DATA5)));
653
654 } else if (pbpctl_dev->bp_i80) {
655 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
656 (ctrl_ext &
657 ~BPCTLI_CTRL_EXT_MDIO_DIR80));
658 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
659 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80)
660 & ~(BPCTLI_CTRL_EXT_MCLK_DATA80)));
661
662 } else if (pbpctl_dev->bp_540) {
663 BP10G_WRITE_REG(pbpctl_dev, ESDP,
664 ((ctrl | BP540_MCLK_DIR) &
665 ~(BP540_MDIO_DIR | BP540_MCLK_DATA)));
666
667 } else if (pbpctl_dev->bp_10gb) {
668
669 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
670 (ctrl_ext | BP10GB_MDIO_DIR |
671 BP10GB_MCLK_CLR) & ~(BP10GB_MCLK_DIR |
672 BP10GB_MDIO_CLR |
673 BP10GB_MDIO_SET |
674 BP10GB_MCLK_SET));
675
676 } else if (!pbpctl_dev->bp_10g)
677 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
678 BPCTLI_CTRL_EXT_MCLK_DIR)
679 &
680 ~
681 (BPCTLI_CTRL_EXT_MDIO_DIR
682 |
683 BPCTLI_CTRL_EXT_MCLK_DATA)));
684 else {
685
7040e556 686 BP10G_WRITE_REG(pbpctl_dev, EODSDP, ((ctrl_ext | BP10G_MDIO_DATA_OUT) & ~BP10G_MCLK_DATA_OUT)); /* ? */
687bcca0 687 /* printk("0x28=0x%x\n",BP10G_READ_REG(pbpctl_dev,EODSDP);); */
7040e556
D		 688
689 }
690
691 usec_delay(PULSE_TIME);
692 if (pbpctl_dev->bp_10g9) {
693 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
694 /* DATA ? CLK 1 */
695 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
696 (ctrl | BP10G_MCLK_DATA_OUT9 |
697 BP10G_MCLK_DIR_OUT9));
698
699 } else if (pbpctl_dev->bp_fiber5) {
700 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
701 BPCTLI_CTRL_EXT_MCLK_DIR5
702 |
703 BPCTLI_CTRL_EXT_MCLK_DATA5)
704 &
705 ~
706 (BPCTLI_CTRL_EXT_MDIO_DIR5)));
707
708 } else if (pbpctl_dev->bp_i80) {
709 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
710 (ctrl_ext &
711 ~(BPCTLI_CTRL_EXT_MDIO_DIR80)));
712 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
713 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
714 BPCTLI_CTRL_EXT_MCLK_DATA80));
715
716 } else if (pbpctl_dev->bp_540) {
717 BP10G_WRITE_REG(pbpctl_dev, ESDP,
718 ((ctrl | BP540_MCLK_DIR |
719 BP540_MCLK_DATA) &
720 ~(BP540_MDIO_DIR)));
721
722 } else if (pbpctl_dev->bp_10gb) {
723 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
724 (ctrl_ext | BP10GB_MDIO_DIR |
725 BP10GB_MCLK_SET) & ~(BP10GB_MCLK_DIR |
726 BP10GB_MDIO_CLR |
727 BP10GB_MDIO_SET |
728 BP10GB_MCLK_CLR));
729
730 } else if (!pbpctl_dev->bp_10g)
731 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
732 BPCTLI_CTRL_EXT_MCLK_DIR
733 |
734 BPCTLI_CTRL_EXT_MCLK_DATA)
735 &
736 ~
737 (BPCTLI_CTRL_EXT_MDIO_DIR)));
738 else {
739
7040e556
D		 740 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
741 (ctrl_ext | BP10G_MCLK_DATA_OUT |
742 BP10G_MDIO_DATA_OUT));
7040e556
D		 743
744 }
745 if (pbpctl_dev->bp_10g9) {
746 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
747
748 } else if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_i80)) {
749 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
750 } else if (pbpctl_dev->bp_540) {
751 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
752 } else if (pbpctl_dev->bp_10gb)
753 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
754
755 else if (!pbpctl_dev->bp_10g)
756 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
757 else
758 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
7040e556
D		 759
760 usec_delay(PULSE_TIME);
761 if (pbpctl_dev->bp_10g9) {
762 if (ctrl_ext & BP10G_MDIO_DATA_IN9)
763 ctrl_val |= 1 << i;
764
765 } else if (pbpctl_dev->bp_fiber5) {
766 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA5)
767 ctrl_val |= 1 << i;
768 } else if (pbpctl_dev->bp_i80) {
769 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA80)
770 ctrl_val |= 1 << i;
771 } else if (pbpctl_dev->bp_540) {
772 if (ctrl_ext & BP540_MDIO_DATA)
773 ctrl_val |= 1 << i;
774 } else if (pbpctl_dev->bp_10gb) {
775 if (ctrl_ext & BP10GB_MDIO_DATA)
776 ctrl_val |= 1 << i;
777
778 } else if (!pbpctl_dev->bp_10g) {
779
780 if (ctrl_ext & BPCTLI_CTRL_EXT_MDIO_DATA)
781 ctrl_val |= 1 << i;
782 } else {
783
784 if (ctrl_ext & BP10G_MDIO_DATA_IN)
785 ctrl_val |= 1 << i;
786 }
787
788 }
789
790 return ctrl_val;
791}
792
01448bbb 793static void write_reg(bpctl_dev_t *pbpctl_dev, unsigned char value,
7040e556
D		 794 unsigned char addr)
795{
796 uint32_t ctrl_ext = 0, ctrl = 0;
797 bpctl_dev_t *pbpctl_dev_c = NULL;
798 unsigned long flags;
799 if (pbpctl_dev->bp_10g9) {
800 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
801 return;
802 }
803 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
804 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER))
805 wdt_time_left(pbpctl_dev);
806
807#ifdef BP_SYNC_FLAG
808 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
809#else
810 atomic_set(&pbpctl_dev->wdt_busy, 1);
811#endif
812 if (pbpctl_dev->bp_10g9) {
813
814 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
815 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
816 /* DATA 0 CLK 0 */
817 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
818 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
819 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
820 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
821 ((ctrl | BP10G_MCLK_DIR_OUT9) &
822 ~(BP10G_MCLK_DATA_OUT9)));
823
824 } else if (pbpctl_dev->bp_fiber5) {
825 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
826 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
827 BPCTLI_CTRL_EXT_MCLK_DIR5
828 |
829 BPCTLI_CTRL_EXT_MDIO_DIR5)
830 &
831 ~
832 (BPCTLI_CTRL_EXT_MDIO_DATA5
833 |
834 BPCTLI_CTRL_EXT_MCLK_DATA5)));
835 } else if (pbpctl_dev->bp_i80) {
836 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
837 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
838 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
839 BPCTLI_CTRL_EXT_MDIO_DIR80)
840 &
841 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
842 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
843 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
844 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
845
846 } else if (pbpctl_dev->bp_540) {
847 ctrl = ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
848 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
849 BP540_MDIO_DIR |
850 BP540_MCLK_DIR) &
851 ~(BP540_MDIO_DATA |
852 BP540_MCLK_DATA)));
853
854 } else if (pbpctl_dev->bp_10gb) {
855 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
856
857 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
858 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
859 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
860 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
861
862 } else if (!pbpctl_dev->bp_10g) {
863
864 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
865 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
866 BPCTLI_CTRL_EXT_MCLK_DIR
867 |
868 BPCTLI_CTRL_EXT_MDIO_DIR)
869 &
870 ~
871 (BPCTLI_CTRL_EXT_MDIO_DATA
872 |
873 BPCTLI_CTRL_EXT_MCLK_DATA)));
874 } else {
875 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
876 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
877 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
878 (ctrl_ext &
879 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556
D		 880 }
881 usec_delay(CMND_INTERVAL);
882
883 /*send sync cmd */
884 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
885 /*send wr cmd */
886 write_pulse(pbpctl_dev, ctrl_ext, WR_CMD_VAL, WR_CMD_LEN);
887 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
888
889 /*write data */
890 write_pulse(pbpctl_dev, ctrl_ext, value, WR_DATA_LEN);
891 if (pbpctl_dev->bp_10g9) {
892 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
893 /* DATA 0 CLK 0 */
894 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
895 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
896 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
897 ((ctrl | BP10G_MCLK_DIR_OUT9) &
898 ~(BP10G_MCLK_DATA_OUT9)));
899
900 } else if (pbpctl_dev->bp_fiber5) {
901 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
902 BPCTLI_CTRL_EXT_MCLK_DIR5
903 |
904 BPCTLI_CTRL_EXT_MDIO_DIR5)
905 &
906 ~
907 (BPCTLI_CTRL_EXT_MDIO_DATA5
908 |
909 BPCTLI_CTRL_EXT_MCLK_DATA5)));
910 } else if (pbpctl_dev->bp_i80) {
911 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
912 BPCTLI_CTRL_EXT_MDIO_DIR80)
913 &
914 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
915 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
916 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
917 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
918 } else if (pbpctl_dev->bp_540) {
919 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
920 BP540_MDIO_DIR |
921 BP540_MCLK_DIR) &
922 ~(BP540_MDIO_DATA |
923 BP540_MCLK_DATA)));
924 } else if (pbpctl_dev->bp_10gb) {
925 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
926 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
927 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
928 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
929
930 } else if (!pbpctl_dev->bp_10g)
931
932 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
933 BPCTLI_CTRL_EXT_MCLK_DIR
934 |
935 BPCTLI_CTRL_EXT_MDIO_DIR)
936 &
937 ~
938 (BPCTLI_CTRL_EXT_MDIO_DATA
939 |
940 BPCTLI_CTRL_EXT_MCLK_DATA)));
941 else {
942 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
943 (ctrl_ext &
944 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556 945
7040e556
D		 946 }
947
948 usec_delay(CMND_INTERVAL * 4);
949
950 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) &&
951 (pbpctl_dev->bp_ext_ver < PXG4BPFI_VER) && (addr == CMND_REG_ADDR))
952 pbpctl_dev->bypass_wdt_on_time = jiffies;
953#ifdef BP_SYNC_FLAG
954 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
955#else
956 atomic_set(&pbpctl_dev->wdt_busy, 0);
957#endif
958
959}
960
01448bbb 961static void write_data(bpctl_dev_t *pbpctl_dev, unsigned char value)
7040e556
D		 962{
963 write_reg(pbpctl_dev, value, CMND_REG_ADDR);
964}
965
01448bbb 966static int read_reg(bpctl_dev_t *pbpctl_dev, unsigned char addr)
7040e556
D		 967{
968 uint32_t ctrl_ext = 0, ctrl = 0, ctrl_value = 0;
969 bpctl_dev_t *pbpctl_dev_c = NULL;
970
971#ifdef BP_SYNC_FLAG
972 unsigned long flags;
973 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
974#else
975 atomic_set(&pbpctl_dev->wdt_busy, 1);
976#endif
977 if (pbpctl_dev->bp_10g9) {
978 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
979 return -1;
980 }
981
982 if (pbpctl_dev->bp_10g9) {
983 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
984 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
985
986 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
987 /* DATA 0 CLK 0 */
988 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
989 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
990 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
991 ((ctrl | BP10G_MCLK_DIR_OUT9) &
992 ~(BP10G_MCLK_DATA_OUT9)));
993
994 } else if (pbpctl_dev->bp_fiber5) {
995 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
996
997 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
998 BPCTLI_CTRL_EXT_MCLK_DIR5
999 |
1000 BPCTLI_CTRL_EXT_MDIO_DIR5)
1001 &
1002 ~
1003 (BPCTLI_CTRL_EXT_MDIO_DATA5
1004 |
1005 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1006 } else if (pbpctl_dev->bp_i80) {
1007 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1008 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1009
1010 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1011 BPCTLI_CTRL_EXT_MDIO_DIR80)
1012 &
1013 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1014 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1015 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1016 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1017 } else if (pbpctl_dev->bp_540) {
1018 ctrl_ext = BP10G_READ_REG(pbpctl_dev, ESDP);
1019 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1020
1021 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1022 BP540_MDIO_DIR) &
1023 ~(BP540_MDIO_DATA |
1024 BP540_MCLK_DATA)));
1025 } else if (pbpctl_dev->bp_10gb) {
1026 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1027
1028 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1029 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1030 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1031 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1032#if 0
1033
1034 /*BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, (ctrl_ext | BP10GB_MCLK_DIR | BP10GB_MDIO_DIR|
1035 BP10GB_MCLK_CLR|BP10GB_MDIO_CLR));
1036 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1037 printk("1reg=%x\n", ctrl_ext); */
1038
1039 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO, ((ctrl_ext |
1040 BP10GB_MCLK_SET |
1041 BP10GB_MDIO_CLR))
1042 & ~(BP10GB_MCLK_CLR | BP10GB_MDIO_SET |
1043 BP10GB_MCLK_DIR | BP10GB_MDIO_DIR));
1044
1045 /* bnx2x_set_spio(pbpctl_dev, 5, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1046 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_OUTPUT_LOW);
1047 bnx2x_set_spio(pbpctl_dev, 4, MISC_REGISTERS_SPIO_INPUT_HI_Z); */
1048
1049 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1050
687bcca0 1051 printk("2reg=%x\n", ctrl_ext);
7040e556
D		 1052
1053#ifdef BP_SYNC_FLAG
1054 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1055#else
1056 atomic_set(&pbpctl_dev->wdt_busy, 0);
1057#endif
1058
1059 return 0;
1060
1061#endif
1062
1063 } else if (!pbpctl_dev->bp_10g) {
1064
1065 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1066
1067 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1068 BPCTLI_CTRL_EXT_MCLK_DIR
1069 |
1070 BPCTLI_CTRL_EXT_MDIO_DIR)
1071 &
1072 ~
1073 (BPCTLI_CTRL_EXT_MDIO_DATA
1074 |
1075 BPCTLI_CTRL_EXT_MCLK_DATA)));
1076 } else {
1077
7040e556
D		 1078 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1079 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1080 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1081 (ctrl_ext &
1082 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556
D		 1083
1084 }
1085
1086 usec_delay(CMND_INTERVAL);
1087
1088 /*send sync cmd */
1089 write_pulse(pbpctl_dev, ctrl_ext, SYNC_CMD_VAL, SYNC_CMD_LEN);
1090 /*send rd cmd */
1091 write_pulse(pbpctl_dev, ctrl_ext, RD_CMD_VAL, RD_CMD_LEN);
1092 /*send addr */
1093 write_pulse(pbpctl_dev, ctrl_ext, addr, ADDR_CMD_LEN);
1094 /*read data */
1095 /* zero */
1096 if (pbpctl_dev->bp_10g9) {
1097 /* DATA 0 CLK 1 */
1098 /*BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext|BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9)); */
1099 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1100 (ctrl_ext | BP10G_MDIO_DATA_OUT9));
1101 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1102 (ctrl | BP10G_MCLK_DATA_OUT9 |
1103 BP10G_MCLK_DIR_OUT9));
1104
1105 } else if (pbpctl_dev->bp_fiber5) {
1106 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1107 BPCTLI_CTRL_EXT_MCLK_DIR5
1108 |
1109 BPCTLI_CTRL_EXT_MCLK_DATA5)
1110 &
1111 ~
1112 (BPCTLI_CTRL_EXT_MDIO_DIR5
1113 |
1114 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1115
1116 } else if (pbpctl_dev->bp_i80) {
1117 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
1118 (ctrl_ext &
1119 ~(BPCTLI_CTRL_EXT_MDIO_DATA80 |
1120 BPCTLI_CTRL_EXT_MDIO_DIR80)));
1121 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1122 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1123 BPCTLI_CTRL_EXT_MCLK_DATA80));
1124
1125 } else if (pbpctl_dev->bp_540) {
1126 BP10G_WRITE_REG(pbpctl_dev, ESDP,
1127 (((ctrl | BP540_MDIO_DIR | BP540_MCLK_DIR |
1128 BP540_MCLK_DATA) & ~BP540_MDIO_DATA)));
1129
1130 } else if (pbpctl_dev->bp_10gb) {
1131
1132 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1133 (ctrl_ext | BP10GB_MDIO_DIR | BP10GB_MCLK_SET)
1134 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_SET |
1135 BP10GB_MDIO_CLR | BP10GB_MCLK_CLR));
1136
1137 } else if (!pbpctl_dev->bp_10g)
1138 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1139 BPCTLI_CTRL_EXT_MCLK_DIR
1140 |
1141 BPCTLI_CTRL_EXT_MCLK_DATA)
1142 &
1143 ~
1144 (BPCTLI_CTRL_EXT_MDIO_DIR
1145 |
1146 BPCTLI_CTRL_EXT_MDIO_DATA)));
1147 else {
1148
7040e556
D		 1149 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1150 (ctrl_ext | BP10G_MCLK_DATA_OUT |
1151 BP10G_MDIO_DATA_OUT));
1152
7040e556
D		 1153
1154 }
1155 usec_delay(PULSE_TIME);
1156
1157 ctrl_value = read_pulse(pbpctl_dev, ctrl_ext, RD_DATA_LEN);
1158
1159 if (pbpctl_dev->bp_10g9) {
1160 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1161 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1162
1163 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1164 /* DATA 0 CLK 0 */
1165 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1166 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1167 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1168 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1169 ~(BP10G_MCLK_DATA_OUT9)));
1170
1171 } else if (pbpctl_dev->bp_fiber5) {
1172 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1173 BPCTLI_CTRL_EXT_MCLK_DIR5
1174 |
1175 BPCTLI_CTRL_EXT_MDIO_DIR5)
1176 &
1177 ~
1178 (BPCTLI_CTRL_EXT_MDIO_DATA5
1179 |
1180 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1181 } else if (pbpctl_dev->bp_i80) {
1182 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1183 BPCTLI_CTRL_EXT_MDIO_DIR80)
1184 &
1185 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1186 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1187 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1188 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1189
1190 } else if (pbpctl_dev->bp_540) {
1191 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1192 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1193 BP540_MDIO_DIR) &
1194 ~(BP540_MDIO_DATA |
1195 BP540_MCLK_DATA)));
1196
1197 } else if (pbpctl_dev->bp_10gb) {
1198 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1199 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1200 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1201 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1202 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1203
1204 } else if (!pbpctl_dev->bp_10g) {
1205 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1206 BPCTLI_CTRL_EXT_MCLK_DIR
1207 |
1208 BPCTLI_CTRL_EXT_MDIO_DIR)
1209 &
1210 ~
1211 (BPCTLI_CTRL_EXT_MDIO_DATA
1212 |
1213 BPCTLI_CTRL_EXT_MCLK_DATA)));
1214 } else {
1215
7040e556
D		 1216 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1217 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1218 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1219 (ctrl_ext &
1220 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556
D		 1221
1222 }
1223
1224 usec_delay(CMND_INTERVAL * 4);
1225#ifdef BP_SYNC_FLAG
1226 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1227#else
1228 atomic_set(&pbpctl_dev->wdt_busy, 0);
1229#endif
1230
1231 return ctrl_value;
1232}
1233
01448bbb 1234static int wdt_pulse(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1235{
1236 uint32_t ctrl_ext = 0, ctrl = 0;
1237 bpctl_dev_t *pbpctl_dev_c = NULL;
1238
1239#ifdef BP_SYNC_FLAG
1240 unsigned long flags;
1241
1242 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1243#else
1244
1245 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1246 return -1;
1247#endif
1248 if (pbpctl_dev->bp_10g9) {
1249 if (!(pbpctl_dev_c = get_status_port_fn(pbpctl_dev)))
1250 return -1;
1251 }
1252
1253 if (pbpctl_dev->bp_10g9) {
1254 ctrl_ext = BP10G_READ_REG(pbpctl_dev, I2CCTL);
1255 ctrl = BP10G_READ_REG(pbpctl_dev_c, ESDP);
1256
1257 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1258 /* DATA 0 CLK 0 */
1259 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1260 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1261 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1262 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1263 ~(BP10G_MCLK_DATA_OUT9)));
1264
1265 } else if (pbpctl_dev->bp_fiber5) {
1266 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1267 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1268 BPCTLI_CTRL_EXT_MCLK_DIR5
1269 |
1270 BPCTLI_CTRL_EXT_MDIO_DIR5)
1271 &
1272 ~
1273 (BPCTLI_CTRL_EXT_MDIO_DATA5
1274 |
1275 BPCTLI_CTRL_EXT_MCLK_DATA5)));
1276 } else if (pbpctl_dev->bp_i80) {
1277 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL);
1278 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1279 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1280 BPCTLI_CTRL_EXT_MDIO_DIR80)
1281 &
1282 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1283 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1284 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1285 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1286 } else if (pbpctl_dev->bp_540) {
1287 ctrl_ext = ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1288 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1289 BP540_MDIO_DIR) &
1290 ~(BP540_MDIO_DATA |
1291 BP540_MCLK_DATA)));
1292 } else if (pbpctl_dev->bp_10gb) {
1293 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1294 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1295 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1296 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1297 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1298
1299 } else if (!pbpctl_dev->bp_10g) {
1300
1301 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1302 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1303 BPCTLI_CTRL_EXT_MCLK_DIR
1304 |
1305 BPCTLI_CTRL_EXT_MDIO_DIR)
1306 &
1307 ~
1308 (BPCTLI_CTRL_EXT_MDIO_DATA
1309 |
1310 BPCTLI_CTRL_EXT_MCLK_DATA)));
1311 } else {
1312
7040e556
D		 1313 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
1314 ctrl_ext = BP10G_READ_REG(pbpctl_dev, EODSDP);
1315 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1316 (ctrl_ext &
1317 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556
D		 1318
1319 }
1320 if (pbpctl_dev->bp_10g9) {
1321 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, ((ctrl_ext|BP10G_MCLK_DATA_OUT9)&~BP10G_MDIO_DATA_OUT9)); */
1322 /* DATA 0 CLK 1 */
1323 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1324 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1325 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1326 (ctrl | BP10G_MCLK_DATA_OUT9 |
1327 BP10G_MCLK_DIR_OUT9));
1328
1329 } else if (pbpctl_dev->bp_fiber5) {
1330 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1331 BPCTLI_CTRL_EXT_MCLK_DIR5
1332 |
1333 BPCTLI_CTRL_EXT_MDIO_DIR5
1334 |
1335 BPCTLI_CTRL_EXT_MCLK_DATA5)
1336 &
1337 ~
1338 (BPCTLI_CTRL_EXT_MDIO_DATA5)));
1339 } else if (pbpctl_dev->bp_i80) {
1340 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1341 BPCTLI_CTRL_EXT_MDIO_DIR80)
1342 &
1343 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1344 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1345 (ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80 |
1346 BPCTLI_CTRL_EXT_MCLK_DATA80));
1347
1348 } else if (pbpctl_dev->bp_540) {
1349 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl |
1350 BP540_MDIO_DIR |
1351 BP540_MCLK_DIR |
1352 BP540_MCLK_DATA) &
1353 ~BP540_MDIO_DATA));
1354
1355 } else if (pbpctl_dev->bp_10gb) {
1356 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1357
1358 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1359 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_SET)
1360 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1361 BP10GB_MDIO_SET | BP10GB_MCLK_CLR));
1362
1363 } else if (!pbpctl_dev->bp_10g)
1364 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1365 BPCTLI_CTRL_EXT_MCLK_DIR
1366 |
1367 BPCTLI_CTRL_EXT_MDIO_DIR
1368 |
1369 BPCTLI_CTRL_EXT_MCLK_DATA)
1370 &
1371 ~
1372 (BPCTLI_CTRL_EXT_MDIO_DATA)));
1373 else {
1374
7040e556
D		 1375 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1376 ((ctrl_ext | BP10G_MCLK_DATA_OUT) &
1377 ~BP10G_MDIO_DATA_OUT));
7040e556
D		 1378
1379 }
1380
1381 usec_delay(WDT_INTERVAL);
1382 if (pbpctl_dev->bp_10g9) {
1383 /* BP10G_WRITE_REG(pbpctl_dev, I2CCTL, (ctrl_ext&~(BP10G_MCLK_DATA_OUT9|BP10G_MDIO_DATA_OUT9))); */
1384 /* DATA 0 CLK 0 */
1385 BP10G_WRITE_REG(pbpctl_dev, I2CCTL,
1386 (ctrl_ext & ~BP10G_MDIO_DATA_OUT9));
1387 BP10G_WRITE_REG(pbpctl_dev_c, ESDP,
1388 ((ctrl | BP10G_MCLK_DIR_OUT9) &
1389 ~(BP10G_MCLK_DATA_OUT9)));
1390
1391 } else if (pbpctl_dev->bp_fiber5) {
1392 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1393 BPCTLI_CTRL_EXT_MCLK_DIR5
1394 |
1395 BPCTLI_CTRL_EXT_MDIO_DIR5)
1396 &
1397 ~
1398 (BPCTLI_CTRL_EXT_MCLK_DATA5
1399 |
1400 BPCTLI_CTRL_EXT_MDIO_DATA5)));
1401 } else if (pbpctl_dev->bp_i80) {
1402 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, ((ctrl_ext |
1403 BPCTLI_CTRL_EXT_MDIO_DIR80)
1404 &
1405 ~BPCTLI_CTRL_EXT_MDIO_DATA80));
1406 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
1407 ((ctrl | BPCTLI_CTRL_EXT_MCLK_DIR80) &
1408 ~BPCTLI_CTRL_EXT_MCLK_DATA80));
1409
1410 } else if (pbpctl_dev->bp_540) {
1411 BP10G_WRITE_REG(pbpctl_dev, ESDP, ((ctrl | BP540_MCLK_DIR |
1412 BP540_MDIO_DIR) &
1413 ~(BP540_MDIO_DATA |
1414 BP540_MCLK_DATA)));
1415
1416 } else if (pbpctl_dev->bp_10gb) {
1417 ctrl_ext = BP10GB_READ_REG(pbpctl_dev, MISC_REG_SPIO);
1418 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_SPIO,
1419 (ctrl_ext | BP10GB_MDIO_CLR | BP10GB_MCLK_CLR)
1420 & ~(BP10GB_MCLK_DIR | BP10GB_MDIO_DIR |
1421 BP10GB_MDIO_SET | BP10GB_MCLK_SET));
1422
1423 } else if (!pbpctl_dev->bp_10g)
1424 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1425 BPCTLI_CTRL_EXT_MCLK_DIR
1426 |
1427 BPCTLI_CTRL_EXT_MDIO_DIR)
1428 &
1429 ~
1430 (BPCTLI_CTRL_EXT_MCLK_DATA
1431 |
1432 BPCTLI_CTRL_EXT_MDIO_DATA)));
1433 else {
1434
7040e556
D		 1435 BP10G_WRITE_REG(pbpctl_dev, EODSDP,
1436 (ctrl_ext &
1437 ~(BP10G_MCLK_DATA_OUT | BP10G_MDIO_DATA_OUT)));
7040e556
D		 1438 }
1439 if ((pbpctl_dev->wdt_status == WDT_STATUS_EN) /*&&
1440 (pbpctl_dev->bp_ext_ver<PXG4BPFI_VER) */ )
1441 pbpctl_dev->bypass_wdt_on_time = jiffies;
1442#ifdef BP_SYNC_FLAG
1443 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1444#endif
1445 usec_delay(CMND_INTERVAL * 4);
1446 return 0;
1447}
1448
01448bbb 1449static void data_pulse(bpctl_dev_t *pbpctl_dev, unsigned char value)
7040e556
D		 1450{
1451
1452 uint32_t ctrl_ext = 0;
1453#ifdef BP_SYNC_FLAG
1454 unsigned long flags;
1455#endif
1456 wdt_time_left(pbpctl_dev);
1457#ifdef BP_SYNC_FLAG
1458 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1459#else
1460 atomic_set(&pbpctl_dev->wdt_busy, 1);
1461#endif
1462
1463 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1464 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1465 BPCTLI_CTRL_EXT_SDP6_DIR |
1466 BPCTLI_CTRL_EXT_SDP7_DIR) &
1467 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1468 BPCTLI_CTRL_EXT_SDP7_DATA)));
1469
1470 usec_delay(INIT_CMND_INTERVAL);
1471 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1472 BPCTLI_CTRL_EXT_SDP6_DIR |
1473 BPCTLI_CTRL_EXT_SDP7_DIR |
1474 BPCTLI_CTRL_EXT_SDP6_DATA) &
1475 ~
1476 (BPCTLI_CTRL_EXT_SDP7_DATA)));
1477 usec_delay(INIT_CMND_INTERVAL);
1478
1479 while (value) {
1480 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1481 BPCTLI_CTRL_EXT_SDP6_DIR |
1482 BPCTLI_CTRL_EXT_SDP7_DIR |
1483 BPCTLI_CTRL_EXT_SDP6_DATA |
1484 BPCTLI_CTRL_EXT_SDP7_DATA);
1485 usec_delay(PULSE_INTERVAL);
1486 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1487 BPCTLI_CTRL_EXT_SDP6_DIR
1488 |
1489 BPCTLI_CTRL_EXT_SDP7_DIR
1490 |
1491 BPCTLI_CTRL_EXT_SDP6_DATA)
1492 &
1493 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1494 usec_delay(PULSE_INTERVAL);
1495 value--;
1496
1497 }
1498 usec_delay(INIT_CMND_INTERVAL - PULSE_INTERVAL);
1499 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1500 BPCTLI_CTRL_EXT_SDP6_DIR |
1501 BPCTLI_CTRL_EXT_SDP7_DIR) &
1502 ~(BPCTLI_CTRL_EXT_SDP6_DATA |
1503 BPCTLI_CTRL_EXT_SDP7_DATA)));
1504 usec_delay(WDT_TIME_CNT);
1505 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1506 pbpctl_dev->bypass_wdt_on_time = jiffies;
1507#ifdef BP_SYNC_FLAG
1508 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1509#else
1510 atomic_set(&pbpctl_dev->wdt_busy, 0);
1511#endif
1512
1513}
1514
01448bbb 1515static int send_wdt_pulse(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1516{
1517 uint32_t ctrl_ext = 0;
1518
1519#ifdef BP_SYNC_FLAG
1520 unsigned long flags;
1521
1522 spin_lock_irqsave(&pbpctl_dev->bypass_wr_lock, flags);
1523#else
1524
1525 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1526 return -1;
1527#endif
1528 wdt_time_left(pbpctl_dev);
1529 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1530
1531 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1532 BPCTLI_CTRL_EXT_SDP7_DIR |
1533 BPCTLI_CTRL_EXT_SDP7_DATA);
1534 usec_delay(PULSE_INTERVAL);
1535 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1536 BPCTLI_CTRL_EXT_SDP7_DIR) &
1537 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1538
1539 usec_delay(PULSE_INTERVAL);
1540 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1541 pbpctl_dev->bypass_wdt_on_time = jiffies;
1542#ifdef BP_SYNC_FLAG
1543 spin_unlock_irqrestore(&pbpctl_dev->bypass_wr_lock, flags);
1544#endif
1545
1546 return 0;
1547}
1548
01448bbb 1549void send_bypass_clear_pulse(bpctl_dev_t *pbpctl_dev, unsigned int value)
7040e556
D		 1550{
1551 uint32_t ctrl_ext = 0;
1552
1553 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1554 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1555 BPCTLI_CTRL_EXT_SDP6_DIR) &
1556 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1557
1558 usec_delay(PULSE_INTERVAL);
1559 while (value) {
1560 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext | /* 1 */
1561 BPCTLI_CTRL_EXT_SDP6_DIR |
1562 BPCTLI_CTRL_EXT_SDP6_DATA);
1563 usec_delay(PULSE_INTERVAL);
1564 value--;
1565 }
1566 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext | /* 0 */
1567 BPCTLI_CTRL_EXT_SDP6_DIR) &
1568 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1569 usec_delay(PULSE_INTERVAL);
1570}
1571
1572/* #endif OLD_FW */
1573#ifdef BYPASS_DEBUG
1574
01448bbb 1575int pulse_set_fn(bpctl_dev_t *pbpctl_dev, unsigned int counter)
7040e556
D		 1576{
1577 uint32_t ctrl_ext = 0;
1578
1579 if (!pbpctl_dev)
1580 return -1;
1581
1582 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1583 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1584
1585 pbpctl_dev->bypass_wdt_status = 0;
1586 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1587 write_pulse_1(pbpctl_dev, ctrl_ext, counter, counter);
1588 } else {
1589 wdt_time_left(pbpctl_dev);
1590 if (pbpctl_dev->wdt_status == WDT_STATUS_EN) {
1591 pbpctl_dev->wdt_status = 0;
1592 data_pulse(pbpctl_dev, counter);
1593 pbpctl_dev->wdt_status = WDT_STATUS_EN;
1594 pbpctl_dev->bypass_wdt_on_time = jiffies;
1595
1596 } else
1597 data_pulse(pbpctl_dev, counter);
1598 }
1599
1600 return 0;
1601}
1602
01448bbb 1603int zero_set_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1604{
1605 uint32_t ctrl_ext = 0, ctrl_value = 0;
1606 if (!pbpctl_dev)
1607 return -1;
1608
1609 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1610 printk("zero_set");
1611
1612 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1613
1614 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1615 BPCTLI_CTRL_EXT_MCLK_DIR)
1616 &
1617 ~
1618 (BPCTLI_CTRL_EXT_MCLK_DATA
1619 |
1620 BPCTLI_CTRL_EXT_MDIO_DIR
1621 |
1622 BPCTLI_CTRL_EXT_MDIO_DATA)));
1623
1624 }
1625 return ctrl_value;
1626}
1627
1bd5374d 1628int pulse_get2_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1629{
1630 uint32_t ctrl_ext = 0, ctrl_value = 0;
1631 if (!pbpctl_dev)
1632 return -1;
1633
1634 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1635 printk("pulse_get_fn\n");
1636 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1637 ctrl_value = read_pulse_2(pbpctl_dev, ctrl_ext);
1638 printk("read:%d\n", ctrl_value);
1639 }
1640 return ctrl_value;
1641}
1642
1bd5374d 1643int pulse_get1_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1644{
1645 uint32_t ctrl_ext = 0, ctrl_value = 0;
1646 if (!pbpctl_dev)
1647 return -1;
1648
1649 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1650
1651 printk("pulse_get_fn\n");
1652
1653 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1654 ctrl_value = read_pulse_1(pbpctl_dev, ctrl_ext);
1655 printk("read:%d\n", ctrl_value);
1656 }
1657 return ctrl_value;
1658}
1659
1bd5374d 1660int gpio6_set_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1661{
1662 uint32_t ctrl_ext = 0;
1663
1664 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1665 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1666 BPCTLI_CTRL_EXT_SDP6_DIR |
1667 BPCTLI_CTRL_EXT_SDP6_DATA);
1668 return 0;
1669}
1670
1bd5374d 1671int gpio7_set_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1672{
1673 uint32_t ctrl_ext = 0;
1674
1675 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1676 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ctrl_ext |
1677 BPCTLI_CTRL_EXT_SDP7_DIR |
1678 BPCTLI_CTRL_EXT_SDP7_DATA);
1679 return 0;
1680}
1681
1bd5374d 1682int gpio7_clear_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1683{
1684 uint32_t ctrl_ext = 0;
1685
1686 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1687 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1688 BPCTLI_CTRL_EXT_SDP7_DIR) &
1689 ~BPCTLI_CTRL_EXT_SDP7_DATA));
1690 return 0;
1691}
1692
1bd5374d 1693int gpio6_clear_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1694{
1695 uint32_t ctrl_ext = 0;
1696
1697 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
1698 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, ((ctrl_ext |
1699 BPCTLI_CTRL_EXT_SDP6_DIR) &
1700 ~BPCTLI_CTRL_EXT_SDP6_DATA));
1701 return 0;
1702}
1703#endif /*BYPASS_DEBUG */
1704
fb8004d3 1705static bpctl_dev_t *lookup_port(bpctl_dev_t *dev)
7040e556 1706{
fb8004d3
AV		 1707 bpctl_dev_t *p;
1708 int n;
1709 for (n = 0, p = bpctl_dev_arr; n < device_num && p->pdev; n++) {
1710 if (p->bus == dev->bus
1711 && p->slot == dev->slot
1712 && p->func == (dev->func ^ 1))
1713 return p;
1714 }
1715 return NULL;
1716}
7040e556 1717
fb8004d3
AV		 1718static bpctl_dev_t *get_status_port_fn(bpctl_dev_t *pbpctl_dev)
1719{
1720 if (pbpctl_dev) {
1721 if (pbpctl_dev->func == 0 || pbpctl_dev->func == 2)
1722 return lookup_port(pbpctl_dev);
7040e556
D		 1723 }
1724 return NULL;
1725}
1726
1bd5374d 1727static bpctl_dev_t *get_master_port_fn(bpctl_dev_t *pbpctl_dev)
7040e556 1728{
fb8004d3
AV		 1729 if (pbpctl_dev) {
1730 if (pbpctl_dev->func == 1 || pbpctl_dev->func == 3)
1731 return lookup_port(pbpctl_dev);
7040e556
D		 1732 }
1733 return NULL;
1734}
1735
1736/**************************************/
1737/**************INTEL API***************/
1738/**************************************/
1739
1bd5374d 1740static void write_data_port_int(bpctl_dev_t *pbpctl_dev,
7040e556
D		 1741 unsigned char ctrl_value)
1742{
1743 uint32_t value;
1744
1745 value = BPCTL_READ_REG(pbpctl_dev, CTRL);
1746/* Make SDP0 Pin Directonality to Output */
1747 value |= BPCTLI_CTRL_SDP0_DIR;
1748 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1749
1750 value &= ~BPCTLI_CTRL_SDP0_DATA;
1751 value |= ((ctrl_value & 0x1) << BPCTLI_CTRL_SDP0_SHIFT);
1752 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL, value);
1753
1754 value = (BPCTL_READ_REG(pbpctl_dev, CTRL_EXT));
1755/* Make SDP2 Pin Directonality to Output */
1756 value |= BPCTLI_CTRL_EXT_SDP6_DIR;
1757 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1758
1759 value &= ~BPCTLI_CTRL_EXT_SDP6_DATA;
1760 value |= (((ctrl_value & 0x2) >> 1) << BPCTLI_CTRL_EXT_SDP6_SHIFT);
1761 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT, value);
1762
1763}
1764
1bd5374d 1765static int write_data_int(bpctl_dev_t *pbpctl_dev, unsigned char value)
7040e556
D		 1766{
1767 bpctl_dev_t *pbpctl_dev_b = NULL;
1768
1769 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
1770 return -1;
1771 atomic_set(&pbpctl_dev->wdt_busy, 1);
1772 write_data_port_int(pbpctl_dev, value & 0x3);
1773 write_data_port_int(pbpctl_dev_b, ((value & 0xc) >> 2));
1774 atomic_set(&pbpctl_dev->wdt_busy, 0);
1775
1776 return 0;
1777}
1778
1bd5374d 1779static int wdt_pulse_int(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1780{
1781
1782 if ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)
1783 return -1;
1784
1785 if ((write_data_int(pbpctl_dev, RESET_WDT_INT)) < 0)
1786 return -1;
1787 msec_delay_bp(CMND_INTERVAL_INT);
1788 if ((write_data_int(pbpctl_dev, CMND_OFF_INT)) < 0)
1789 return -1;
1790 msec_delay_bp(CMND_INTERVAL_INT);
1791
1792 if (pbpctl_dev->wdt_status == WDT_STATUS_EN)
1793 pbpctl_dev->bypass_wdt_on_time = jiffies;
1794
1795 return 0;
1796}
1797
1798/*************************************/
1799/************* COMMANDS **************/
1800/*************************************/
1801
1802/* CMND_ON 0x4 (100)*/
1bd5374d 1803int cmnd_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1804{
1805 int ret = BP_NOT_CAP;
1806
1807 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1808 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
1809 return 0;
1810 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1811 write_data(pbpctl_dev, CMND_ON);
1812 else
1813 data_pulse(pbpctl_dev, CMND_ON);
1814 ret = 0;
1815 }
1816 return ret;
1817}
1818
1819/* CMND_OFF 0x2 (10)*/
1bd5374d 1820int cmnd_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1821{
1822 int ret = BP_NOT_CAP;
1823
1824 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
1825 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1826 write_data_int(pbpctl_dev, CMND_OFF_INT);
1827 msec_delay_bp(CMND_INTERVAL_INT);
1828 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
1829 write_data(pbpctl_dev, CMND_OFF);
1830 else
1831 data_pulse(pbpctl_dev, CMND_OFF);
1832 ret = 0;
1833 };
1834 return ret;
1835}
1836
1837/* BYPASS_ON (0xa)*/
1bd5374d 1838int bypass_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1839{
1840 int ret = BP_NOT_CAP;
1841
1842 if (pbpctl_dev->bp_caps & BP_CAP) {
1843 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1844 write_data_int(pbpctl_dev, BYPASS_ON_INT);
1845 msec_delay_bp(BYPASS_DELAY_INT);
1846 pbpctl_dev->bp_status_un = 0;
1847 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1848 write_data(pbpctl_dev, BYPASS_ON);
1849 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1850 msec_delay_bp(LATCH_DELAY);
1851 } else
1852 data_pulse(pbpctl_dev, BYPASS_ON);
1853 ret = 0;
1854 };
1855 return ret;
1856}
1857
1858/* BYPASS_OFF (0x8 111)*/
1bd5374d 1859int bypass_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1860{
1861 int ret = BP_NOT_CAP;
1862
1863 if (pbpctl_dev->bp_caps & BP_CAP) {
1864 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
1865 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
1866 msec_delay_bp(BYPASS_DELAY_INT);
1867 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
1868 msec_delay_bp(BYPASS_DELAY_INT);
1869 pbpctl_dev->bp_status_un = 0;
1870 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
1871 write_data(pbpctl_dev, BYPASS_OFF);
1872 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
1873 msec_delay_bp(LATCH_DELAY);
1874 } else
1875 data_pulse(pbpctl_dev, BYPASS_OFF);
1876 ret = 0;
1877 }
1878 return ret;
1879}
1880
1881/* TAP_OFF (0x9)*/
1bd5374d 1882int tap_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1883{
1884 int ret = BP_NOT_CAP;
1885 if ((pbpctl_dev->bp_caps & TAP_CAP)
1886 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1887 write_data(pbpctl_dev, TAP_OFF);
1888 msec_delay_bp(LATCH_DELAY);
1889 ret = 0;
1890 };
1891 return ret;
1892}
1893
1894/* TAP_ON (0xb)*/
1bd5374d 1895int tap_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1896{
1897 int ret = BP_NOT_CAP;
1898 if ((pbpctl_dev->bp_caps & TAP_CAP)
1899 && (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)) {
1900 write_data(pbpctl_dev, TAP_ON);
1901 msec_delay_bp(LATCH_DELAY);
1902 ret = 0;
1903 };
1904 return ret;
1905}
1906
1907/* DISC_OFF (0x9)*/
1bd5374d 1908int disc_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1909{
1910 int ret = 0;
1911 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1912 write_data(pbpctl_dev, DISC_OFF);
1913 msec_delay_bp(LATCH_DELAY);
1914 } else
1915 ret = BP_NOT_CAP;
1916 return ret;
1917}
1918
1919/* DISC_ON (0xb)*/
1bd5374d 1920int disc_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1921{
1922 int ret = 0;
1923 if ((pbpctl_dev->bp_caps & DISC_CAP) && (pbpctl_dev->bp_ext_ver >= 0x8)) {
1924 write_data(pbpctl_dev, /*DISC_ON */ 0x85);
1925 msec_delay_bp(LATCH_DELAY);
1926 } else
1927 ret = BP_NOT_CAP;
1928 return ret;
1929}
1930
1931/* DISC_PORT_ON */
1bd5374d 1932int disc_port_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1933{
1934 int ret = 0;
1935 bpctl_dev_t *pbpctl_dev_m;
1936
1937 if ((is_bypass_fn(pbpctl_dev)) == 1)
1938 pbpctl_dev_m = pbpctl_dev;
1939 else
1940 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1941 if (pbpctl_dev_m == NULL)
1942 return BP_NOT_CAP;
1943
1944 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
1945 if (is_bypass_fn(pbpctl_dev) == 1) {
1946
1947 write_data(pbpctl_dev_m, TX_DISA);
1948 } else {
1949
1950 write_data(pbpctl_dev_m, TX_DISB);
1951 }
1952
1953 msec_delay_bp(LATCH_DELAY);
1954
1955 }
1956 return ret;
1957}
1958
1959/* DISC_PORT_OFF */
1bd5374d 1960int disc_port_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1961{
1962 int ret = 0;
1963 bpctl_dev_t *pbpctl_dev_m;
1964
1965 if ((is_bypass_fn(pbpctl_dev)) == 1)
1966 pbpctl_dev_m = pbpctl_dev;
1967 else
1968 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
1969 if (pbpctl_dev_m == NULL)
1970 return BP_NOT_CAP;
1971
1972 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
1973 if (is_bypass_fn(pbpctl_dev) == 1)
1974 write_data(pbpctl_dev_m, TX_ENA);
1975 else
1976 write_data(pbpctl_dev_m, TX_ENB);
1977
1978 msec_delay_bp(LATCH_DELAY);
1979
1980 }
1981 return ret;
1982}
1983
1984/*TWO_PORT_LINK_HW_EN (0xe)*/
1bd5374d 1985int tpl_hw_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 1986{
1987 int ret = 0, ctrl = 0;
1988 bpctl_dev_t *pbpctl_dev_b = NULL;
1989
1990 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
1991 return BP_NOT_CAP;
1992
1993 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
1994 cmnd_on(pbpctl_dev);
1995 write_data(pbpctl_dev, TPL2_ON);
1996 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
1997 cmnd_off(pbpctl_dev);
1998 return ret;
1999 }
2000
2001 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2002 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2003 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2004 ((ctrl | BPCTLI_CTRL_SWDPIO0) &
2005 ~BPCTLI_CTRL_SWDPIN0));
2006 } else
2007 ret = BP_NOT_CAP;
2008 return ret;
2009}
2010
2011/*TWO_PORT_LINK_HW_DIS (0xc)*/
1bd5374d 2012int tpl_hw_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2013{
2014 int ret = 0, ctrl = 0;
2015 bpctl_dev_t *pbpctl_dev_b = NULL;
2016
2017 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
2018 return BP_NOT_CAP;
2019 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
2020 cmnd_on(pbpctl_dev);
2021 write_data(pbpctl_dev, TPL2_OFF);
2022 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2023 cmnd_off(pbpctl_dev);
2024 return ret;
2025 }
2026 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
2027 ctrl = BPCTL_READ_REG(pbpctl_dev_b, CTRL);
2028 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL,
2029 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2030 BPCTLI_CTRL_SWDPIN0));
2031 } else
2032 ret = BP_NOT_CAP;
2033 return ret;
2034}
2035
2036/* WDT_OFF (0x6 110)*/
1bd5374d 2037int wdt_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2038{
2039 int ret = BP_NOT_CAP;
2040
2041 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2042 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2043 bypass_off(pbpctl_dev);
2044 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2045 write_data(pbpctl_dev, WDT_OFF);
2046 else
2047 data_pulse(pbpctl_dev, WDT_OFF);
2048 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
2049 ret = 0;
2050 };
2051 return ret;
2052}
2053
2054/* WDT_ON (0x10)*/
2055
2056/***Global***/
2057static unsigned int
2058 wdt_val_array[] = { 1000, 1500, 2000, 3000, 4000, 8000, 16000, 32000, 0 };
2059
1bd5374d 2060int wdt_on(bpctl_dev_t *pbpctl_dev, unsigned int timeout)
7040e556
D		 2061{
2062
2063 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2064 unsigned int pulse = 0, temp_value = 0, temp_cnt = 0;
2065 pbpctl_dev->wdt_status = 0;
2066
2067 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2068 for (; wdt_val_array[temp_cnt]; temp_cnt++)
2069 if (timeout <= wdt_val_array[temp_cnt])
2070 break;
2071
2072 if (!wdt_val_array[temp_cnt])
2073 temp_cnt--;
2074
2075 timeout = wdt_val_array[temp_cnt];
2076 temp_cnt += 0x7;
2077
2078 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2079 msec_delay_bp(BYPASS_DELAY_INT);
2080 pbpctl_dev->bp_status_un = 0;
2081 write_data_int(pbpctl_dev, temp_cnt);
2082 pbpctl_dev->bypass_wdt_on_time = jiffies;
2083 msec_delay_bp(CMND_INTERVAL_INT);
2084 pbpctl_dev->bypass_timer_interval = timeout;
2085 } else {
2086 timeout =
2087 (timeout <
2088 TIMEOUT_UNIT ? TIMEOUT_UNIT : (timeout >
2089 WDT_TIMEOUT_MAX ?
2090 WDT_TIMEOUT_MAX :
2091 timeout));
2092 temp_value = timeout / 100;
2093 while ((temp_value >>= 1))
2094 temp_cnt++;
2095 if (timeout > ((1 << temp_cnt) * 100))
2096 temp_cnt++;
2097 pbpctl_dev->bypass_wdt_on_time = jiffies;
2098 pulse = (WDT_ON | temp_cnt);
2099 if (pbpctl_dev->bp_ext_ver == OLD_IF_VER)
2100 data_pulse(pbpctl_dev, pulse);
2101 else
2102 write_data(pbpctl_dev, pulse);
2103 pbpctl_dev->bypass_timer_interval =
2104 (1 << temp_cnt) * 100;
2105 }
2106 pbpctl_dev->wdt_status = WDT_STATUS_EN;
2107 return 0;
2108 }
2109 return BP_NOT_CAP;
2110}
2111
1bd5374d 2112void bp75_put_hw_semaphore_generic(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2113{
2114 u32 swsm;
2115
2116 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2117
2118 swsm &= ~(BPCTLI_SWSM_SMBI | BPCTLI_SWSM_SWESMBI);
2119
2120 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm);
2121}
2122
1bd5374d 2123s32 bp75_get_hw_semaphore_generic(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2124{
2125 u32 swsm;
2126 s32 ret_val = 0;
2127 s32 timeout = 8192 + 1;
2128 s32 i = 0;
2129
2130 /* Get the SW semaphore */
2131 while (i < timeout) {
2132 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2133 if (!(swsm & BPCTLI_SWSM_SMBI))
2134 break;
2135
2136 usec_delay(50);
2137 i++;
2138 }
2139
2140 if (i == timeout) {
2141 printk
2142 ("bpctl_mod: Driver can't access device - SMBI bit is set.\n");
2143 ret_val = -1;
2144 goto out;
2145 }
2146
2147 /* Get the FW semaphore. */
2148 for (i = 0; i < timeout; i++) {
2149 swsm = BPCTL_READ_REG(pbpctl_dev, SWSM);
2150 BPCTL_WRITE_REG(pbpctl_dev, SWSM, swsm | BPCTLI_SWSM_SWESMBI);
2151
2152 /* Semaphore acquired if bit latched */
2153 if (BPCTL_READ_REG(pbpctl_dev, SWSM) & BPCTLI_SWSM_SWESMBI)
2154 break;
2155
2156 usec_delay(50);
2157 }
2158
2159 if (i == timeout) {
2160 /* Release semaphores */
2161 bp75_put_hw_semaphore_generic(pbpctl_dev);
2162 printk("bpctl_mod: Driver can't access the NVM\n");
2163 ret_val = -1;
2164 goto out;
2165 }
2166
2167 out:
2168 return ret_val;
2169}
2170
1bd5374d 2171static void bp75_release_phy(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2172{
2173 u16 mask = BPCTLI_SWFW_PHY0_SM;
2174 u32 swfw_sync;
2175
2176 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2177 mask = BPCTLI_SWFW_PHY1_SM;
2178
2179 while (bp75_get_hw_semaphore_generic(pbpctl_dev) != 0) ;
2180 /* Empty */
2181
2182 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2183 swfw_sync &= ~mask;
2184 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2185
2186 bp75_put_hw_semaphore_generic(pbpctl_dev);
2187}
2188
1bd5374d 2189static s32 bp75_acquire_phy(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2190{
2191 u16 mask = BPCTLI_SWFW_PHY0_SM;
2192 u32 swfw_sync;
2193 u32 swmask;
2194 u32 fwmask;
2195 s32 ret_val = 0;
2196 s32 i = 0, timeout = 200;
2197
2198 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
2199 mask = BPCTLI_SWFW_PHY1_SM;
2200
2201 swmask = mask;
2202 fwmask = mask << 16;
2203
2204 while (i < timeout) {
2205 if (bp75_get_hw_semaphore_generic(pbpctl_dev)) {
2206 ret_val = -1;
2207 goto out;
2208 }
2209
2210 swfw_sync = BPCTL_READ_REG(pbpctl_dev, SW_FW_SYNC);
2211 if (!(swfw_sync & (fwmask | swmask)))
2212 break;
2213
2214 bp75_put_hw_semaphore_generic(pbpctl_dev);
2215 mdelay(5);
2216 i++;
2217 }
2218
2219 if (i == timeout) {
2220 printk
2221 ("bpctl_mod: Driver can't access resource, SW_FW_SYNC timeout.\n");
2222 ret_val = -1;
2223 goto out;
2224 }
2225
2226 swfw_sync |= swmask;
2227 BPCTL_WRITE_REG(pbpctl_dev, SW_FW_SYNC, swfw_sync);
2228
2229 bp75_put_hw_semaphore_generic(pbpctl_dev);
2230
2231 out:
2232 return ret_val;
2233}
2234
1bd5374d 2235s32 bp75_read_phy_reg_mdic(bpctl_dev_t *pbpctl_dev, u32 offset, u16 *data)
7040e556
D		 2236{
2237 u32 i, mdic = 0;
2238 s32 ret_val = 0;
2239 u32 phy_addr = 1;
2240
2241 mdic = ((offset << BPCTLI_MDIC_REG_SHIFT) |
2242 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_READ));
2243
2244 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2245
2246 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2247 usec_delay(50);
2248 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2249 if (mdic & BPCTLI_MDIC_READY)
2250 break;
2251 }
2252 if (!(mdic & BPCTLI_MDIC_READY)) {
2253 printk("bpctl_mod: MDI Read did not complete\n");
2254 ret_val = -1;
2255 goto out;
2256 }
2257 if (mdic & BPCTLI_MDIC_ERROR) {
2258 printk("bpctl_mod: MDI Error\n");
2259 ret_val = -1;
2260 goto out;
2261 }
2262 *data = (u16) mdic;
2263
2264 out:
2265 return ret_val;
2266}
2267
1bd5374d 2268s32 bp75_write_phy_reg_mdic(bpctl_dev_t *pbpctl_dev, u32 offset, u16 data)
7040e556
D		 2269{
2270 u32 i, mdic = 0;
2271 s32 ret_val = 0;
2272 u32 phy_addr = 1;
2273
2274 mdic = (((u32) data) |
2275 (offset << BPCTLI_MDIC_REG_SHIFT) |
2276 (phy_addr << BPCTLI_MDIC_PHY_SHIFT) | (BPCTLI_MDIC_OP_WRITE));
2277
2278 BPCTL_WRITE_REG(pbpctl_dev, MDIC, mdic);
2279
2280 for (i = 0; i < (BPCTLI_GEN_POLL_TIMEOUT * 3); i++) {
2281 usec_delay(50);
2282 mdic = BPCTL_READ_REG(pbpctl_dev, MDIC);
2283 if (mdic & BPCTLI_MDIC_READY)
2284 break;
2285 }
2286 if (!(mdic & BPCTLI_MDIC_READY)) {
2287 printk("bpctl_mod: MDI Write did not complete\n");
2288 ret_val = -1;
2289 goto out;
2290 }
2291 if (mdic & BPCTLI_MDIC_ERROR) {
2292 printk("bpctl_mod: MDI Error\n");
2293 ret_val = -1;
2294 goto out;
2295 }
2296
2297 out:
2298 return ret_val;
2299}
2300
1bd5374d 2301static s32 bp75_read_phy_reg(bpctl_dev_t *pbpctl_dev, u32 offset, u16 *data)
7040e556
D		 2302{
2303 s32 ret_val = 0;
2304
2305 ret_val = bp75_acquire_phy(pbpctl_dev);
2306 if (ret_val)
2307 goto out;
2308
2309 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2310 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2311 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2312 (u16) offset);
2313 if (ret_val)
2314 goto release;
2315 }
2316
2317 ret_val =
2318 bp75_read_phy_reg_mdic(pbpctl_dev,
2319 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2320
2321 release:
2322 bp75_release_phy(pbpctl_dev);
2323 out:
2324 return ret_val;
2325}
2326
81908e8b 2327static s32 bp75_write_phy_reg(bpctl_dev_t *pbpctl_dev, u32 offset, u16 data)
7040e556
D		 2328{
2329 s32 ret_val = 0;
2330
2331 ret_val = bp75_acquire_phy(pbpctl_dev);
2332 if (ret_val)
2333 goto out;
2334
2335 if (offset > BPCTLI_MAX_PHY_MULTI_PAGE_REG) {
2336 ret_val = bp75_write_phy_reg_mdic(pbpctl_dev,
2337 BPCTLI_IGP01E1000_PHY_PAGE_SELECT,
2338 (u16) offset);
2339 if (ret_val)
2340 goto release;
2341 }
2342
2343 ret_val =
2344 bp75_write_phy_reg_mdic(pbpctl_dev,
2345 BPCTLI_MAX_PHY_REG_ADDRESS & offset, data);
2346
2347 release:
2348 bp75_release_phy(pbpctl_dev);
2349
2350 out:
2351 return ret_val;
2352}
2353
2354/* SET_TX (non-Bypass command :)) */
81908e8b 2355static int set_tx(bpctl_dev_t *pbpctl_dev, int tx_state)
7040e556
D		 2356{
2357 int ret = 0, ctrl = 0;
2358 bpctl_dev_t *pbpctl_dev_m;
2359 if ((is_bypass_fn(pbpctl_dev)) == 1)
2360 pbpctl_dev_m = pbpctl_dev;
2361 else
2362 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2363 if (pbpctl_dev_m == NULL)
2364 return BP_NOT_CAP;
2365 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2366 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2367 if (!tx_state) {
2368 if (pbpctl_dev->bp_540) {
2369 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2370 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2371 (ctrl | BP10G_SDP1_DIR |
2372 BP10G_SDP1_DATA));
2373
2374 } else {
2375 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2376 (ctrl | BPCTLI_CTRL_SDP1_DIR
2377 | BPCTLI_CTRL_SWDPIN1));
2378 }
2379 } else {
2380 if (pbpctl_dev->bp_540) {
2381 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2382 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2383 ((ctrl | BP10G_SDP1_DIR) &
2384 ~BP10G_SDP1_DATA));
2385 } else {
2386 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2387 ((ctrl |
2388 BPCTLI_CTRL_SDP1_DIR) &
2389 ~BPCTLI_CTRL_SWDPIN1));
2390 }
2391 return ret;
2392
2393 }
2394 } else if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
2395 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
2396 if (tx_state) {
2397 uint16_t mii_reg;
2398 if (!
2399 (ret =
2400 bp75_read_phy_reg(pbpctl_dev,
2401 BPCTLI_PHY_CONTROL,
2402 &mii_reg))) {
2403 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN) {
2404 ret =
2405 bp75_write_phy_reg
2406 (pbpctl_dev,
2407 BPCTLI_PHY_CONTROL,
2408 mii_reg &
2409 ~BPCTLI_MII_CR_POWER_DOWN);
2410 }
2411 }
2412 } else {
2413 uint16_t mii_reg;
2414 if (!
2415 (ret =
2416 bp75_read_phy_reg(pbpctl_dev,
2417 BPCTLI_PHY_CONTROL,
2418 &mii_reg))) {
2419
2420 mii_reg |= BPCTLI_MII_CR_POWER_DOWN;
2421 ret =
2422 bp75_write_phy_reg(pbpctl_dev,
2423 BPCTLI_PHY_CONTROL,
2424 mii_reg);
2425 }
2426 }
2427
2428 }
2429 if (pbpctl_dev->bp_fiber5) {
2430 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
2431
2432 } else if (pbpctl_dev->bp_10gb)
2433 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
2434
2435 else if (!pbpctl_dev->bp_10g)
2436 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2437 else
7040e556
D		 2438 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2439
2440 if (!tx_state)
2441 if (pbpctl_dev->bp_10g9) {
2442 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2443 (ctrl | BP10G_SDP3_DATA |
2444 BP10G_SDP3_DIR));
2445
2446 } else if (pbpctl_dev->bp_fiber5) {
2447 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2448 (ctrl |
2449 BPCTLI_CTRL_EXT_SDP6_DIR |
2450 BPCTLI_CTRL_EXT_SDP6_DATA));
2451
2452 } else if (pbpctl_dev->bp_10gb) {
2453 if ((pbpctl_dev->func == 1)
2454 || (pbpctl_dev->func == 3))
2455 BP10GB_WRITE_REG(pbpctl_dev,
2456 MISC_REG_GPIO,
2457 (ctrl |
2458 BP10GB_GPIO0_SET_P1) &
2459 ~(BP10GB_GPIO0_CLR_P1 |
2460 BP10GB_GPIO0_OE_P1));
2461 else
2462 BP10GB_WRITE_REG(pbpctl_dev,
2463 MISC_REG_GPIO,
2464 (ctrl |
2465 BP10GB_GPIO0_OE_P0 |
2466 BP10GB_GPIO0_SET_P0));
2467
2468 } else if (pbpctl_dev->bp_i80) {
2469 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2470 (ctrl | BPCTLI_CTRL_SDP1_DIR
2471 | BPCTLI_CTRL_SWDPIN1));
2472
2473 } else if (pbpctl_dev->bp_540) {
2474 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2475 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2476 (ctrl | BP10G_SDP1_DIR |
2477 BP10G_SDP1_DATA));
2478
2479 }
2480
2481 else if (!pbpctl_dev->bp_10g)
2482 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2483 (ctrl | BPCTLI_CTRL_SWDPIO0 |
2484 BPCTLI_CTRL_SWDPIN0));
2485
2486 else
7040e556
D		 2487 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2488 (ctrl | BP10G_SDP0_DATA |
2489 BP10G_SDP0_DIR));
2490
2491 else {
2492 if (pbpctl_dev->bp_10g9) {
2493 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2494 ((ctrl | BP10G_SDP3_DIR) &
2495 ~BP10G_SDP3_DATA));
2496
2497 } else if (pbpctl_dev->bp_fiber5) {
2498 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL_EXT,
2499 ((ctrl |
2500 BPCTLI_CTRL_EXT_SDP6_DIR) &
2501 ~BPCTLI_CTRL_EXT_SDP6_DATA));
2502
2503 } else if (pbpctl_dev->bp_10gb) {
2504 if ((bpctl_dev_arr->func == 1)
2505 || (bpctl_dev_arr->func == 3))
2506 BP10GB_WRITE_REG(pbpctl_dev,
2507 MISC_REG_GPIO,
2508 (ctrl |
2509 BP10GB_GPIO0_CLR_P1) &
2510 ~(BP10GB_GPIO0_SET_P1 |
2511 BP10GB_GPIO0_OE_P1));
2512 else
2513 BP10GB_WRITE_REG(pbpctl_dev,
2514 MISC_REG_GPIO,
2515 (ctrl |
2516 BP10GB_GPIO0_OE_P0 |
2517 BP10GB_GPIO0_CLR_P0));
2518
2519 } else if (pbpctl_dev->bp_i80) {
2520 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2521 ((ctrl |
2522 BPCTLI_CTRL_SDP1_DIR) &
2523 ~BPCTLI_CTRL_SWDPIN1));
2524 } else if (pbpctl_dev->bp_540) {
2525 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
2526 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2527 ((ctrl | BP10G_SDP1_DIR) &
2528 ~BP10G_SDP1_DATA));
2529 }
2530
2531 else if (!pbpctl_dev->bp_10g) {
2532 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2533 ((ctrl | BPCTLI_CTRL_SWDPIO0)
2534 & ~BPCTLI_CTRL_SWDPIN0));
2535 if (!PEGF_IF_SERIES(pbpctl_dev->subdevice)) {
2536 BPCTL_BP_WRITE_REG(pbpctl_dev, CTRL,
2537 (ctrl &
2538 ~
2539 (BPCTLI_CTRL_SDP0_DATA
2540 |
2541 BPCTLI_CTRL_SDP0_DIR)));
2542 }
2543 } else
7040e556
D		 2544 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2545 ((ctrl | BP10G_SDP0_DIR) &
2546 ~BP10G_SDP0_DATA));
2547
2548 }
2549
2550 } else
2551 ret = BP_NOT_CAP;
2552 return ret;
2553
2554}
2555
2556/* SET_FORCE_LINK (non-Bypass command :)) */
81908e8b 2557static int set_bp_force_link(bpctl_dev_t *pbpctl_dev, int tx_state)
7040e556
D		 2558{
2559 int ret = 0, ctrl = 0;
2560
2561 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
2562
2563 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
2564
2565 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
2566 if (!tx_state)
2567 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2568 ctrl & ~BP10G_SDP1_DIR);
2569 else
2570 BP10G_WRITE_REG(pbpctl_dev, ESDP,
2571 ((ctrl | BP10G_SDP1_DIR) &
2572 ~BP10G_SDP1_DATA));
2573 return ret;
2574 }
2575
2576 }
2577 return BP_NOT_CAP;
2578}
2579
2580/*RESET_CONT 0x20 */
81908e8b 2581int reset_cont(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2582{
2583 int ret = BP_NOT_CAP;
2584
2585 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
2586 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2587 return BP_NOT_CAP;
2588 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2589 write_data(pbpctl_dev, RESET_CONT);
2590 else
2591 data_pulse(pbpctl_dev, RESET_CONT);
2592 ret = 0;
2593 };
2594 return ret;
2595}
2596
2597/*DIS_BYPASS_CAP 0x22 */
81908e8b 2598int dis_bypass_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2599{
2600
2601 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2602 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2603 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2604 msec_delay_bp(BYPASS_DELAY_INT);
2605 } else {
2606 write_data(pbpctl_dev, BYPASS_OFF);
2607 msec_delay_bp(LATCH_DELAY);
2608 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2609 msec_delay_bp(BYPASS_CAP_DELAY);
2610 }
2611 return 0;
2612 }
2613 return BP_NOT_CAP;
2614}
2615
2616/*EN_BYPASS_CAP 0x24 */
81908e8b 2617int en_bypass_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2618{
2619 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2620 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2621 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2622 msec_delay_bp(BYPASS_DELAY_INT);
2623 } else {
2624 write_data(pbpctl_dev, EN_BYPASS_CAP);
2625 msec_delay_bp(BYPASS_CAP_DELAY);
2626 }
2627 return 0;
2628 }
2629 return BP_NOT_CAP;
2630}
2631
2632/* BYPASS_STATE_PWRON 0x26*/
81908e8b 2633int bypass_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2634{
2635 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2636 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2637 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2638 msec_delay_bp(DFLT_PWRON_DELAY);
2639 else
2640 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2641 return 0;
2642 }
2643 return BP_NOT_CAP;
2644}
2645
2646/* NORMAL_STATE_PWRON 0x28*/
81908e8b 2647int normal_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2648{
2649 if ((pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP)
2650 || (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)) {
2651 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2652 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2653 msec_delay_bp(DFLT_PWRON_DELAY);
2654 else
2655 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2656 return 0;
2657 }
2658 return BP_NOT_CAP;
2659}
2660
2661/* BYPASS_STATE_PWROFF 0x27*/
81908e8b 2662int bypass_state_pwroff(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2663{
2664 if (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP) {
2665 write_data(pbpctl_dev, BYPASS_STATE_PWROFF);
2666 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2667 return 0;
2668 }
2669 return BP_NOT_CAP;
2670}
2671
2672/* NORMAL_STATE_PWROFF 0x29*/
81908e8b 2673int normal_state_pwroff(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2674{
2675 if ((pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
2676 write_data(pbpctl_dev, NORMAL_STATE_PWROFF);
2677 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2678 return 0;
2679 }
2680 return BP_NOT_CAP;
2681}
2682
2683/*TAP_STATE_PWRON 0x2a*/
81908e8b 2684int tap_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2685{
2686 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2687 write_data(pbpctl_dev, TAP_STATE_PWRON);
2688 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2689 return 0;
2690 }
2691 return BP_NOT_CAP;
2692}
2693
2694/*DIS_TAP_CAP 0x2c*/
81908e8b 2695int dis_tap_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2696{
2697 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2698 write_data(pbpctl_dev, DIS_TAP_CAP);
2699 msec_delay_bp(BYPASS_CAP_DELAY);
2700 return 0;
2701 }
2702 return BP_NOT_CAP;
2703}
2704
2705/*EN_TAP_CAP 0x2e*/
81908e8b 2706int en_tap_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2707{
2708 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2709 write_data(pbpctl_dev, EN_TAP_CAP);
2710 msec_delay_bp(BYPASS_CAP_DELAY);
2711 return 0;
2712 }
2713 return BP_NOT_CAP;
2714}
2715
2716/*DISC_STATE_PWRON 0x2a*/
81908e8b 2717int disc_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2718{
2719 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
2720 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2721 write_data(pbpctl_dev, DISC_STATE_PWRON);
2722 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2723 return BP_OK;
2724 }
2725 }
2726 return BP_NOT_CAP;
2727}
2728
2729/*DIS_DISC_CAP 0x2c*/
81908e8b 2730int dis_disc_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2731{
2732 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2733 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2734 write_data(pbpctl_dev, DIS_DISC_CAP);
2735 msec_delay_bp(BYPASS_CAP_DELAY);
2736 return BP_OK;
2737 }
2738 }
2739 return BP_NOT_CAP;
2740}
2741
2742/*DISC_STATE_PWRON 0x2a*/
81908e8b 2743int disc_port_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2744{
2745 int ret = 0;
2746 bpctl_dev_t *pbpctl_dev_m;
2747
2748 return BP_NOT_CAP;
2749
2750 if ((is_bypass_fn(pbpctl_dev)) == 1)
2751 pbpctl_dev_m = pbpctl_dev;
2752 else
2753 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2754 if (pbpctl_dev_m == NULL)
2755 return BP_NOT_CAP;
2756
2757 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2758 if (is_bypass_fn(pbpctl_dev) == 1)
2759 write_data(pbpctl_dev_m, TX_DISA_PWRUP);
2760 else
2761 write_data(pbpctl_dev_m, TX_DISB_PWRUP);
2762
2763 msec_delay_bp(LATCH_DELAY);
2764
2765 }
2766 return ret;
2767}
2768
81908e8b 2769int normal_port_state_pwron(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2770{
2771 int ret = 0;
2772 bpctl_dev_t *pbpctl_dev_m;
2773 return BP_NOT_CAP;
2774
2775 if ((is_bypass_fn(pbpctl_dev)) == 1)
2776 pbpctl_dev_m = pbpctl_dev;
2777 else
2778 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
2779 if (pbpctl_dev_m == NULL)
2780 return BP_NOT_CAP;
2781
2782 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
2783 if (is_bypass_fn(pbpctl_dev) == 1)
2784 write_data(pbpctl_dev_m, TX_ENA_PWRUP);
2785 else
2786 write_data(pbpctl_dev_m, TX_ENB_PWRUP);
2787
2788 msec_delay_bp(LATCH_DELAY);
2789
2790 }
2791 return ret;
2792}
2793
2794/*EN_TAP_CAP 0x2e*/
81908e8b 2795int en_disc_cap(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2796{
2797 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2798 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2799 write_data(pbpctl_dev, EN_DISC_CAP);
2800 msec_delay_bp(BYPASS_CAP_DELAY);
2801 return BP_OK;
2802 }
2803 }
2804 return BP_NOT_CAP;
2805}
2806
81908e8b 2807int std_nic_on(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2808{
2809
2810 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2811
2812 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2813 write_data_int(pbpctl_dev, DIS_BYPASS_CAP_INT);
2814 msec_delay_bp(BYPASS_DELAY_INT);
2815 pbpctl_dev->bp_status_un = 0;
2816 return BP_OK;
2817 }
2818
2819 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2820 write_data(pbpctl_dev, STD_NIC_ON);
2821 msec_delay_bp(BYPASS_CAP_DELAY);
2822 return BP_OK;
2823
2824 }
2825
2826 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2827 wdt_off(pbpctl_dev);
2828
2829 if (pbpctl_dev->bp_caps & BP_CAP) {
2830 write_data(pbpctl_dev, BYPASS_OFF);
2831 msec_delay_bp(LATCH_DELAY);
2832 }
2833
2834 if (pbpctl_dev->bp_caps & TAP_CAP) {
2835 write_data(pbpctl_dev, TAP_OFF);
2836 msec_delay_bp(LATCH_DELAY);
2837 }
2838
2839 write_data(pbpctl_dev, NORMAL_STATE_PWRON);
2840 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
2841 msec_delay_bp(DFLT_PWRON_DELAY);
2842 else
2843 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2844
2845 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2846 write_data(pbpctl_dev, DIS_BYPASS_CAP);
2847 msec_delay_bp(BYPASS_CAP_DELAY);
2848 }
2849
2850 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2851 write_data(pbpctl_dev, DIS_TAP_CAP);
2852 msec_delay_bp(BYPASS_CAP_DELAY);
2853
2854 }
2855 return 0;
2856 }
2857 }
2858 return BP_NOT_CAP;
2859}
2860
81908e8b 2861int std_nic_off(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2862{
2863
2864 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
2865 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
2866 write_data_int(pbpctl_dev, PWROFF_BYPASS_ON_INT);
2867 msec_delay_bp(BYPASS_DELAY_INT);
2868 return BP_OK;
2869 }
2870 if (pbpctl_dev->bp_ext_ver >= 0x8) {
2871 write_data(pbpctl_dev, STD_NIC_OFF);
2872 msec_delay_bp(BYPASS_CAP_DELAY);
2873 return BP_OK;
2874
2875 }
2876
2877 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
2878
2879 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
2880 write_data(pbpctl_dev, TAP_STATE_PWRON);
2881 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
2882 }
2883
2884 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
2885 write_data(pbpctl_dev, BYPASS_STATE_PWRON);
2886 if (pbpctl_dev->bp_ext_ver > PXG2BPI_VER)
2887 msec_delay_bp(LATCH_DELAY +
2888 EEPROM_WR_DELAY);
2889 else
2890 msec_delay_bp(DFLT_PWRON_DELAY);
2891 }
2892
2893 if (pbpctl_dev->bp_caps & TAP_DIS_CAP) {
2894 write_data(pbpctl_dev, EN_TAP_CAP);
2895 msec_delay_bp(BYPASS_CAP_DELAY);
2896 }
2897 if (pbpctl_dev->bp_caps & DISC_DIS_CAP) {
2898 write_data(pbpctl_dev, EN_DISC_CAP);
2899 msec_delay_bp(BYPASS_CAP_DELAY);
2900 }
2901
2902 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
2903 write_data(pbpctl_dev, EN_BYPASS_CAP);
2904 msec_delay_bp(BYPASS_CAP_DELAY);
2905 }
2906
2907 return 0;
2908 }
2909 }
2910 return BP_NOT_CAP;
2911}
2912
81908e8b 2913int wdt_time_left(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2914{
2915
687bcca0 2916 /* unsigned long curr_time=((long long)(jiffies*1000))/HZ, delta_time=0,wdt_on_time=((long long)(pbpctl_dev->bypass_wdt_on_time*1000))/HZ; */
7040e556
D		 2917 unsigned long curr_time = jiffies, delta_time = 0, wdt_on_time =
2918 pbpctl_dev->bypass_wdt_on_time, delta_time_msec = 0;
2919 int time_left = 0;
2920
2921 switch (pbpctl_dev->wdt_status) {
2922 case WDT_STATUS_DIS:
2923 time_left = 0;
2924 break;
2925 case WDT_STATUS_EN:
2926 delta_time =
2927 (curr_time >=
2928 wdt_on_time) ? (curr_time - wdt_on_time) : (~wdt_on_time +
2929 curr_time);
2930 delta_time_msec = jiffies_to_msecs(delta_time);
2931 time_left = pbpctl_dev->bypass_timer_interval - delta_time_msec;
2932 if (time_left < 0) {
2933 time_left = -1;
2934 pbpctl_dev->wdt_status = WDT_STATUS_EXP;
2935 }
2936 break;
2937 case WDT_STATUS_EXP:
2938 time_left = -1;
2939 break;
2940 }
2941
2942 return time_left;
2943}
2944
81908e8b 2945static int wdt_timer(bpctl_dev_t *pbpctl_dev, int *time_left)
7040e556
D		 2946{
2947 int ret = 0;
2948 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
2949 {
2950 if (pbpctl_dev->wdt_status == WDT_STATUS_UNKNOWN)
2951 ret = BP_NOT_CAP;
2952 else
2953 *time_left = wdt_time_left(pbpctl_dev);
2954 }
2955
2956 } else
2957 ret = BP_NOT_CAP;
2958 return ret;
2959}
2960
81908e8b 2961static int wdt_timer_reload(bpctl_dev_t *pbpctl_dev)
7040e556
D		 2962{
2963
2964 int ret = 0;
2965
2966 if ((pbpctl_dev->bp_caps & WD_CTL_CAP) &&
2967 (pbpctl_dev->wdt_status != WDT_STATUS_UNKNOWN)) {
2968 if (pbpctl_dev->wdt_status == WDT_STATUS_DIS)
2969 return 0;
2970 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER)
2971 ret = wdt_pulse(pbpctl_dev);
2972 else if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
2973 ret = wdt_pulse_int(pbpctl_dev);
2974 else
2975 ret = send_wdt_pulse(pbpctl_dev);
687bcca0
DC		 2976 /* if (ret==-1)
2977 mod_timer(&pbpctl_dev->bp_timer, jiffies+1);*/
7040e556
D		 2978 return 1;
2979 }
2980 return BP_NOT_CAP;
2981}
2982
2983static void wd_reset_timer(unsigned long param)
2984{
2985 bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
2986#ifdef BP_SELF_TEST
2987 struct sk_buff *skb_tmp;
2988#endif
2989
2990 if ((pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) &&
2991 ((atomic_read(&pbpctl_dev->wdt_busy)) == 1)) {
2992 mod_timer(&pbpctl_dev->bp_timer, jiffies + 1);
2993 return;
2994 }
2995#ifdef BP_SELF_TEST
2996
2997 if (pbpctl_dev->bp_self_test_flag == 1) {
2998 skb_tmp = dev_alloc_skb(BPTEST_DATA_LEN + 2);
2999 if ((skb_tmp) && (pbpctl_dev->ndev) && (pbpctl_dev->bp_tx_data)) {
3000 memcpy(skb_put(skb_tmp, BPTEST_DATA_LEN),
3001 pbpctl_dev->bp_tx_data, BPTEST_DATA_LEN);
3002 skb_tmp->dev = pbpctl_dev->ndev;
3003 skb_tmp->protocol =
3004 eth_type_trans(skb_tmp, pbpctl_dev->ndev);
3005 skb_tmp->ip_summed = CHECKSUM_UNNECESSARY;
3006 netif_receive_skb(skb_tmp);
3007 goto bp_timer_reload;
3008 return;
3009 }
3010 }
3011#endif
3012
3013 wdt_timer_reload(pbpctl_dev);
3014#ifdef BP_SELF_TEST
3015 bp_timer_reload:
3016#endif
3017 if (pbpctl_dev->reset_time) {
3018 mod_timer(&pbpctl_dev->bp_timer,
3019 jiffies + (HZ * pbpctl_dev->reset_time) / 1000);
3020 }
3021}
3022
7040e556 3023/*WAIT_AT_PWRUP 0x80 */
81908e8b 3024int bp_wait_at_pwup_en(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3025{
3026
3027 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3028 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3029 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_EN);
3030 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3031
3032 return BP_OK;
3033 }
3034 }
3035 return BP_NOT_CAP;
3036}
3037
3038/*DIS_WAIT_AT_PWRUP 0x81 */
81908e8b 3039int bp_wait_at_pwup_dis(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3040{
3041
3042 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3043
3044 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3045 write_data(pbpctl_dev, BP_WAIT_AT_PWUP_DIS);
3046 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3047
3048 return BP_OK;
3049 }
3050 }
3051 return BP_NOT_CAP;
3052}
3053
3054/*EN_HW_RESET 0x82 */
3055
81908e8b 3056int bp_hw_reset_en(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3057{
3058
3059 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3060 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3061 write_data(pbpctl_dev, BP_HW_RESET_EN);
3062 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3063
3064 return BP_OK;
3065 }
3066 }
3067 return BP_NOT_CAP;
3068}
3069
3070/*DIS_HW_RESET 0x83 */
3071
81908e8b 3072int bp_hw_reset_dis(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3073{
3074
3075 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3076 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3077 write_data(pbpctl_dev, BP_HW_RESET_DIS);
3078 msec_delay_bp(LATCH_DELAY + EEPROM_WR_DELAY);
3079
3080 return BP_OK;
3081 }
3082 }
3083 return BP_NOT_CAP;
3084}
3085
7040e556 3086
81908e8b 3087int wdt_exp_mode(bpctl_dev_t *pbpctl_dev, int mode)
7040e556
D		 3088{
3089 uint32_t status_reg = 0, status_reg1 = 0;
3090
3091 if ((pbpctl_dev->bp_caps & (TAP_STATUS_CAP | DISC_CAP)) &&
3092 (pbpctl_dev->bp_caps & BP_CAP)) {
3093 if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3094
3095 if ((pbpctl_dev->bp_ext_ver >= 0x8) &&
3096 (mode == 2) && (pbpctl_dev->bp_caps & DISC_CAP)) {
3097 status_reg1 =
3098 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3099 if (!(status_reg1 & WDTE_DISC_BPN_MASK))
3100 write_reg(pbpctl_dev,
3101 status_reg1 |
3102 WDTE_DISC_BPN_MASK,
3103 STATUS_DISC_REG_ADDR);
3104 return BP_OK;
3105 }
3106 }
3107 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3108
3109 if ((mode == 0) && (pbpctl_dev->bp_caps & BP_CAP)) {
3110 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3111 status_reg1 =
3112 read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3113 if (status_reg1 & WDTE_DISC_BPN_MASK)
3114 write_reg(pbpctl_dev,
3115 status_reg1 &
3116 ~WDTE_DISC_BPN_MASK,
3117 STATUS_DISC_REG_ADDR);
3118 }
3119 if (status_reg & WDTE_TAP_BPN_MASK)
3120 write_reg(pbpctl_dev,
3121 status_reg & ~WDTE_TAP_BPN_MASK,
3122 STATUS_TAP_REG_ADDR);
3123 return BP_OK;
3124
3125 } else if ((mode == 1) && (pbpctl_dev->bp_caps & TAP_CAP)) {
3126 if (!(status_reg & WDTE_TAP_BPN_MASK))
3127 write_reg(pbpctl_dev,
3128 status_reg | WDTE_TAP_BPN_MASK,
3129 STATUS_TAP_REG_ADDR);
3130 /*else return BP_NOT_CAP; */
3131 return BP_OK;
3132 }
3133
3134 }
3135 return BP_NOT_CAP;
3136}
3137
81908e8b 3138int bypass_fw_ver(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3139{
3140 if (is_bypass_fn(pbpctl_dev))
7935c80c 3141 return read_reg(pbpctl_dev, VER_REG_ADDR);
7040e556
D		 3142 else
3143 return BP_NOT_CAP;
3144}
3145
81908e8b 3146int bypass_sign_check(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3147{
3148
3149 if (is_bypass_fn(pbpctl_dev))
3150 return (((read_reg(pbpctl_dev, PIC_SIGN_REG_ADDR)) ==
3151 PIC_SIGN_VALUE) ? 1 : 0);
3152 else
3153 return BP_NOT_CAP;
3154}
3155
81908e8b 3156static int tx_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3157{
3158 uint32_t ctrl = 0;
3159 bpctl_dev_t *pbpctl_dev_m;
3160 if ((is_bypass_fn(pbpctl_dev)) == 1)
3161 pbpctl_dev_m = pbpctl_dev;
3162 else
3163 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3164 if (pbpctl_dev_m == NULL)
3165 return BP_NOT_CAP;
3166 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3167
3168 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3169 if (pbpctl_dev->bp_i80)
3170 return ((ctrl & BPCTLI_CTRL_SWDPIN1) != 0 ? 0 : 1);
3171 if (pbpctl_dev->bp_540) {
3172 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3173
3174 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3175 }
3176
3177 }
3178
3179 if (pbpctl_dev->bp_caps & TX_CTL_CAP) {
3180 if (PEG5_IF_SERIES(pbpctl_dev->subdevice)) {
3181 uint16_t mii_reg;
3182 if (!
3183 (bp75_read_phy_reg
3184 (pbpctl_dev, BPCTLI_PHY_CONTROL, &mii_reg))) {
3185 if (mii_reg & BPCTLI_MII_CR_POWER_DOWN)
3186 return 0;
3187
3188 else
3189 return 1;
3190 }
3191 return -1;
3192 }
3193
3194 if (pbpctl_dev->bp_10g9) {
3195 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3196 BP10G_SDP3_DATA) != 0 ? 0 : 1);
3197
3198 } else if (pbpctl_dev->bp_fiber5) {
3199 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
3200 if (ctrl & BPCTLI_CTRL_EXT_SDP6_DATA)
3201 return 0;
3202 return 1;
3203 } else if (pbpctl_dev->bp_10gb) {
3204 ctrl = BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3205 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3206 (ctrl | BP10GB_GPIO0_OE_P1) &
3207 ~(BP10GB_GPIO0_SET_P1 |
3208 BP10GB_GPIO0_CLR_P1));
3209
3210 if ((pbpctl_dev->func == 1) || (pbpctl_dev->func == 3))
3211 return (((BP10GB_READ_REG
3212 (pbpctl_dev,
3213 MISC_REG_GPIO)) & BP10GB_GPIO0_P1) !=
3214 0 ? 0 : 1);
3215 else
3216 return (((BP10GB_READ_REG
3217 (pbpctl_dev,
3218 MISC_REG_GPIO)) & BP10GB_GPIO0_P0) !=
3219 0 ? 0 : 1);
3220 }
3221
3222 if (!pbpctl_dev->bp_10g) {
3223
3224 ctrl = BPCTL_READ_REG(pbpctl_dev, CTRL);
3225 if (pbpctl_dev->bp_i80)
3226 return ((ctrl & BPCTLI_CTRL_SWDPIN1) !=
3227 0 ? 0 : 1);
3228 if (pbpctl_dev->bp_540) {
3229 ctrl = BP10G_READ_REG(pbpctl_dev, ESDP);
3230
3231 return ((ctrl & BP10G_SDP1_DATA) != 0 ? 0 : 1);
3232 }
3233
3234 return ((ctrl & BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3235 } else
3236 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3237 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3238
3239 }
3240 return BP_NOT_CAP;
3241}
3242
81908e8b 3243static int bp_force_link_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3244{
3245
3246 if (DBI_IF_SERIES(pbpctl_dev->subdevice)) {
3247
3248 if ((pbpctl_dev->bp_10g) || (pbpctl_dev->bp_10g9)) {
3249 return ((BP10G_READ_REG(pbpctl_dev, ESDP) &
3250 BP10G_SDP1_DIR) != 0 ? 1 : 0);
3251
3252 }
3253 }
3254 return BP_NOT_CAP;
3255}
3256
81908e8b 3257int bypass_from_last_read(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3258{
3259 uint32_t ctrl_ext = 0;
3260 bpctl_dev_t *pbpctl_dev_b = NULL;
3261
3262 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3263 && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3264 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3265 BPCTL_BP_WRITE_REG(pbpctl_dev_b, CTRL_EXT,
3266 (ctrl_ext & ~BPCTLI_CTRL_EXT_SDP7_DIR));
3267 ctrl_ext = BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT);
3268 if (ctrl_ext & BPCTLI_CTRL_EXT_SDP7_DATA)
3269 return 0;
3270 return 1;
3271 } else
3272 return BP_NOT_CAP;
3273}
3274
0920af72 3275int bypass_status_clear(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3276{
3277 bpctl_dev_t *pbpctl_dev_b = NULL;
3278
3279 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3280 && (pbpctl_dev_b = get_status_port_fn(pbpctl_dev))) {
3281
3282 send_bypass_clear_pulse(pbpctl_dev_b, 1);
3283 return 0;
3284 } else
3285 return BP_NOT_CAP;
3286}
3287
0920af72 3288int bypass_flag_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3289{
3290
3291 if ((pbpctl_dev->bp_caps & BP_CAP)) {
3292 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3293 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3294 BYPASS_FLAG_MASK) ==
3295 BYPASS_FLAG_MASK) ? 1 : 0);
3296 }
3297 }
3298 return BP_NOT_CAP;
3299}
3300
0920af72 3301int bypass_flag_status_clear(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3302{
3303
3304 if (pbpctl_dev->bp_caps & BP_CAP) {
3305 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3306 uint32_t status_reg = 0;
3307 status_reg = read_reg(pbpctl_dev, STATUS_REG_ADDR);
3308 write_reg(pbpctl_dev, status_reg & ~BYPASS_FLAG_MASK,
3309 STATUS_REG_ADDR);
3310 return 0;
3311 }
3312 }
3313 return BP_NOT_CAP;
3314}
3315
0920af72 3316int bypass_change_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3317{
3318 int ret = BP_NOT_CAP;
3319
3320 if (pbpctl_dev->bp_caps & BP_STATUS_CHANGE_CAP) {
3321 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3322 ret = bypass_flag_status(pbpctl_dev);
3323 bypass_flag_status_clear(pbpctl_dev);
3324 } else if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3325 ret = bypass_flag_status(pbpctl_dev);
3326 bypass_flag_status_clear(pbpctl_dev);
3327 } else {
3328 ret = bypass_from_last_read(pbpctl_dev);
3329 bypass_status_clear(pbpctl_dev);
3330 }
3331 }
3332 return ret;
3333}
3334
0920af72 3335int bypass_off_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3336{
3337
3338 if (pbpctl_dev->bp_caps & BP_CAP) {
3339 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3340 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3341 BYPASS_OFF_MASK) == BYPASS_OFF_MASK) ? 1 : 0);
3342 }
3343 }
3344 return BP_NOT_CAP;
3345}
3346
0920af72 3347static int bypass_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3348{
3349 u32 ctrl_ext = 0;
3350 if (pbpctl_dev->bp_caps & BP_CAP) {
3351
3352 bpctl_dev_t *pbpctl_dev_b = NULL;
3353
3354 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3355 return BP_NOT_CAP;
3356
3357 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
3358
3359 if (!pbpctl_dev->bp_status_un)
3360 return (((BPCTL_READ_REG
3361 (pbpctl_dev_b,
3362 CTRL_EXT)) &
3363 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3364 0 ? 1 : 0);
3365 else
3366 return BP_NOT_CAP;
3367 }
3368 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3369
7040e556
D		 3370 if (pbpctl_dev->bp_10g9) {
3371 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3372 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3373 (ctrl_ext | BP10G_I2C_CLK_OUT));
7040e556
D		 3374 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3375 BP10G_I2C_CLK_IN) != 0 ? 0 : 1);
3376
3377 } else if (pbpctl_dev->bp_540) {
3378 return (((BP10G_READ_REG(pbpctl_dev_b, ESDP)) &
3379 BP10G_SDP0_DATA) != 0 ? 0 : 1);
3380 }
3381
3382 else if ((pbpctl_dev->bp_fiber5)
3383 || (pbpctl_dev->bp_i80)) {
3384 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3385 BPCTLI_CTRL_SWDPIN0) != 0 ? 0 : 1);
3386 } else if (pbpctl_dev->bp_10gb) {
3387 ctrl_ext =
3388 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3389 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3390 (ctrl_ext | BP10GB_GPIO3_OE_P0)
3391 & ~(BP10GB_GPIO3_SET_P0 |
3392 BP10GB_GPIO3_CLR_P0));
3393
3394 return (((BP10GB_READ_REG
3395 (pbpctl_dev,
3396 MISC_REG_GPIO)) & BP10GB_GPIO3_P0) !=
3397 0 ? 0 : 1);
3398 }
3399
3400 else if (!pbpctl_dev->bp_10g)
3401 return (((BPCTL_READ_REG
3402 (pbpctl_dev_b,
3403 CTRL_EXT)) &
3404 BPCTLI_CTRL_EXT_SDP7_DATA) !=
3405 0 ? 0 : 1);
3406
3407 else {
3408 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3409 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3410 (ctrl_ext |
3411 BP10G_SDP7_DATA_OUT));
7040e556
D		 3412 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3413 BP10G_SDP7_DATA_IN) != 0 ? 0 : 1);
3414 }
3415
3416 } else if (pbpctl_dev->media_type == bp_copper) {
3417
3418 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3419 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3420 } else {
3421 if ((bypass_status_clear(pbpctl_dev)) >= 0)
7935c80c 3422 return bypass_from_last_read(pbpctl_dev);
7040e556
D		 3423 }
3424
3425 }
3426 return BP_NOT_CAP;
3427}
3428
0920af72 3429int default_pwron_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3430{
3431
3432 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3433 if (pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP) {
3434 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3435 return ((((read_reg
3436 (pbpctl_dev,
3437 STATUS_REG_ADDR)) & DFLT_PWRON_MASK)
3438 == DFLT_PWRON_MASK) ? 0 : 1);
3439 }
3440 } /*else if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3441 (pbpctl_dev->bp_caps&BP_PWUP_ON_CAP))
3442 return 1; */
3443 }
3444 return BP_NOT_CAP;
3445}
3446
0920af72 3447static int default_pwroff_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3448{
3449
3450 /*if ((!pbpctl_dev->bp_caps&BP_DIS_CAP)&&
3451 (pbpctl_dev->bp_caps&BP_PWOFF_ON_CAP))
3452 return 1; */
3453 if ((pbpctl_dev->bp_caps & SW_CTL_CAP)
3454 && (pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP)) {
3455 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3456 DFLT_PWROFF_MASK) == DFLT_PWROFF_MASK) ? 0 : 1);
3457 }
3458 return BP_NOT_CAP;
3459}
3460
0920af72 3461int dis_bypass_cap_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3462{
3463
3464 if (pbpctl_dev->bp_caps & BP_DIS_CAP) {
3465 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3466 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3467 DIS_BYPASS_CAP_MASK) ==
3468 DIS_BYPASS_CAP_MASK) ? 1 : 0);
3469 }
3470 }
3471 return BP_NOT_CAP;
3472}
3473
0920af72 3474int cmd_en_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3475{
3476
3477 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3478 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3479 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3480 CMND_EN_MASK) == CMND_EN_MASK) ? 1 : 0);
3481 }
3482 }
3483 return BP_NOT_CAP;
3484}
3485
0920af72 3486int wdt_en_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3487{
3488
3489 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3490 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3491 return ((((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3492 WDT_EN_MASK) == WDT_EN_MASK) ? 1 : 0);
3493 }
3494 }
3495 return BP_NOT_CAP;
3496}
3497
0920af72 3498int wdt_programmed(bpctl_dev_t *pbpctl_dev, int *timeout)
7040e556
D		 3499{
3500 int ret = 0;
3501 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3502 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3503 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
3504 WDT_EN_MASK) {
3505 u8 wdt_val;
3506 wdt_val = read_reg(pbpctl_dev, WDT_REG_ADDR);
3507 *timeout = (1 << wdt_val) * 100;
3508 } else
3509 *timeout = 0;
3510 } else {
3511 int curr_wdt_status = pbpctl_dev->wdt_status;
3512 if (curr_wdt_status == WDT_STATUS_UNKNOWN)
3513 *timeout = -1;
3514 else
3515 *timeout =
3516 curr_wdt_status ==
3517 0 ? 0 : pbpctl_dev->bypass_timer_interval;
3518 };
3519 } else
3520 ret = BP_NOT_CAP;
3521 return ret;
3522}
3523
0920af72 3524int bypass_support(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3525{
3526 int ret = 0;
3527
3528 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3529 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3530 ret =
3531 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3532 BYPASS_SUPPORT_MASK) ==
3533 BYPASS_SUPPORT_MASK) ? 1 : 0);
3534 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3535 ret = 1;
3536 } else
3537 ret = BP_NOT_CAP;
3538 return ret;
3539}
3540
0920af72 3541int tap_support(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3542{
3543 int ret = 0;
3544
3545 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3546 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3547 ret =
3548 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3549 TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) ? 1 : 0);
3550 } else if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
3551 ret = 0;
3552 } else
3553 ret = BP_NOT_CAP;
3554 return ret;
3555}
3556
0920af72 3557int normal_support(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3558{
3559 int ret = BP_NOT_CAP;
3560
3561 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3562 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3563 ret =
3564 ((((read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR)) &
3565 NORMAL_UNSUPPORT_MASK) ==
3566 NORMAL_UNSUPPORT_MASK) ? 0 : 1);
3567 } else
3568 ret = 1;
3569 };
3570 return ret;
3571}
3572
0920af72 3573int get_bp_prod_caps(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3574{
3575 if ((pbpctl_dev->bp_caps & SW_CTL_CAP) &&
3576 (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER))
7935c80c 3577 return read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
7040e556
D		 3578 return BP_NOT_CAP;
3579
3580}
3581
0920af72 3582int tap_flag_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3583{
3584
3585 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3586 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3587 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3588 TAP_FLAG_MASK) == TAP_FLAG_MASK) ? 1 : 0);
3589
3590 }
3591 return BP_NOT_CAP;
3592}
3593
0920af72 3594int tap_flag_status_clear(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3595{
3596 uint32_t status_reg = 0;
3597 if (pbpctl_dev->bp_caps & TAP_STATUS_CAP) {
3598 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3599 status_reg = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3600 write_reg(pbpctl_dev, status_reg & ~TAP_FLAG_MASK,
3601 STATUS_TAP_REG_ADDR);
3602 return 0;
3603 }
3604 }
3605 return BP_NOT_CAP;
3606}
3607
0920af72 3608int tap_change_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3609{
3610 int ret = BP_NOT_CAP;
3611 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
3612 if (pbpctl_dev->bp_caps & TAP_CAP) {
3613 if (pbpctl_dev->bp_caps & BP_CAP) {
3614 ret = tap_flag_status(pbpctl_dev);
3615 tap_flag_status_clear(pbpctl_dev);
3616 } else {
3617 ret = bypass_from_last_read(pbpctl_dev);
3618 bypass_status_clear(pbpctl_dev);
3619 }
3620 }
3621 }
3622 return ret;
3623}
3624
0920af72 3625int tap_off_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3626{
3627 if (pbpctl_dev->bp_caps & TAP_CAP) {
3628 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3629 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3630 TAP_OFF_MASK) == TAP_OFF_MASK) ? 1 : 0);
3631 }
3632 return BP_NOT_CAP;
3633}
3634
0920af72 3635int tap_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3636{
3637 u32 ctrl_ext = 0;
3638
3639 if (pbpctl_dev->bp_caps & TAP_CAP) {
3640 bpctl_dev_t *pbpctl_dev_b = NULL;
3641
3642 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3643 return BP_NOT_CAP;
3644
3645 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3646 if (!pbpctl_dev->bp_10g)
3647 return (((BPCTL_READ_REG
3648 (pbpctl_dev_b,
3649 CTRL_EXT)) &
3650 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3651 0 ? 0 : 1);
3652 else {
3653 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3654 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3655 (ctrl_ext |
3656 BP10G_SDP6_DATA_OUT));
7040e556
D		 3657 return ((BP10G_READ_REG(pbpctl_dev_b, EODSDP) &
3658 BP10G_SDP6_DATA_IN) != 0 ? 0 : 1);
3659 }
3660
3661 } else if (pbpctl_dev->media_type == bp_copper)
3662 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3663 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3664 else {
3665 if ((bypass_status_clear(pbpctl_dev)) >= 0)
7935c80c 3666 return bypass_from_last_read(pbpctl_dev);
7040e556
D		 3667 }
3668
3669 }
3670 return BP_NOT_CAP;
3671}
3672
0920af72 3673int default_pwron_tap_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3674{
3675 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3676 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3677 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3678 DFLT_PWRON_TAP_MASK) ==
3679 DFLT_PWRON_TAP_MASK) ? 1 : 0);
3680 }
3681 return BP_NOT_CAP;
3682}
3683
0920af72 3684int dis_tap_cap_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3685{
3686 if (pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP) {
3687 if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER)
3688 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3689 DIS_TAP_CAP_MASK) ==
3690 DIS_TAP_CAP_MASK) ? 1 : 0);
3691 }
3692 return BP_NOT_CAP;
3693}
3694
0920af72 3695int disc_flag_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3696{
3697
3698 if (pbpctl_dev->bp_caps & DISC_CAP) {
3699 if (pbpctl_dev->bp_ext_ver >= 0x8)
3700 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3701 DISC_FLAG_MASK) == DISC_FLAG_MASK) ? 1 : 0);
3702
3703 }
3704 return BP_NOT_CAP;
3705}
3706
0920af72 3707int disc_flag_status_clear(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3708{
3709 uint32_t status_reg = 0;
3710 if (pbpctl_dev->bp_caps & DISC_CAP) {
3711 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3712 status_reg = read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR);
3713 write_reg(pbpctl_dev, status_reg & ~DISC_FLAG_MASK,
3714 STATUS_DISC_REG_ADDR);
3715 return BP_OK;
3716 }
3717 }
3718 return BP_NOT_CAP;
3719}
3720
0920af72 3721int disc_change_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3722{
3723 int ret = BP_NOT_CAP;
3724 if (pbpctl_dev->bp_caps & DISC_CAP) {
3725 ret = disc_flag_status(pbpctl_dev);
3726 disc_flag_status_clear(pbpctl_dev);
3727 return ret;
3728 }
3729 return BP_NOT_CAP;
3730}
3731
0920af72 3732int disc_off_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3733{
3734 bpctl_dev_t *pbpctl_dev_b = NULL;
3735 u32 ctrl_ext = 0;
3736
3737 if (pbpctl_dev->bp_caps & DISC_CAP) {
3738 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3739 return BP_NOT_CAP;
3740 if (DISCF_IF_SERIES(pbpctl_dev->subdevice))
3741 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3742 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3743
3744 if (pbpctl_dev->bp_i80) {
7040e556
D		 3745 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL_EXT)) &
3746 BPCTLI_CTRL_EXT_SDP6_DATA) != 0 ? 1 : 0);
3747
3748 }
3749 if (pbpctl_dev->bp_540) {
3750 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, ESDP);
7040e556
D		 3751 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3752 BP10G_SDP2_DATA) != 0 ? 1 : 0);
3753
3754 }
7040e556
D		 3755 if (pbpctl_dev->media_type == bp_copper) {
3756
3757#if 0
3758 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3759 DISC_OFF_MASK) == DISC_OFF_MASK) ? 1 : 0);
3760#endif
3761 if (!pbpctl_dev->bp_10g)
3762 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3763 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3764 else
7040e556
D		 3765 return ((BP10G_READ_REG(pbpctl_dev_b, ESDP) &
3766 BP10G_SDP1_DATA) != 0 ? 1 : 0);
3767
3768 } else {
3769
3770 if (pbpctl_dev->bp_10g9) {
3771 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, I2CCTL);
3772 BP10G_WRITE_REG(pbpctl_dev_b, I2CCTL,
3773 (ctrl_ext |
3774 BP10G_I2C_DATA_OUT));
7040e556
D		 3775 return ((BP10G_READ_REG(pbpctl_dev_b, I2CCTL) &
3776 BP10G_I2C_DATA_IN) != 0 ? 1 : 0);
3777
3778 } else if (pbpctl_dev->bp_fiber5) {
3779 return (((BPCTL_READ_REG(pbpctl_dev_b, CTRL)) &
3780 BPCTLI_CTRL_SWDPIN1) != 0 ? 1 : 0);
3781 } else if (pbpctl_dev->bp_10gb) {
3782 ctrl_ext =
3783 BP10GB_READ_REG(pbpctl_dev, MISC_REG_GPIO);
3784 BP10GB_WRITE_REG(pbpctl_dev, MISC_REG_GPIO,
3785 (ctrl_ext | BP10GB_GPIO3_OE_P1)
3786 & ~(BP10GB_GPIO3_SET_P1 |
3787 BP10GB_GPIO3_CLR_P1));
3788
3789 return (((BP10GB_READ_REG
3790 (pbpctl_dev,
3791 MISC_REG_GPIO)) & BP10GB_GPIO3_P1) !=
3792 0 ? 1 : 0);
3793 }
3794 if (!pbpctl_dev->bp_10g) {
3795
3796 return (((BPCTL_READ_REG
3797 (pbpctl_dev_b,
3798 CTRL_EXT)) &
3799 BPCTLI_CTRL_EXT_SDP6_DATA) !=
3800 0 ? 1 : 0);
3801 } else {
3802 ctrl_ext = BP10G_READ_REG(pbpctl_dev_b, EODSDP);
3803 BP10G_WRITE_REG(pbpctl_dev_b, EODSDP,
3804 (ctrl_ext |
3805 BP10G_SDP6_DATA_OUT));
7040e556
D		 3806 return (((BP10G_READ_REG(pbpctl_dev_b, EODSDP))
3807 & BP10G_SDP6_DATA_IN) != 0 ? 1 : 0);
3808 }
3809
3810 }
3811 }
3812 return BP_NOT_CAP;
3813}
3814
0920af72 3815static int disc_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3816{
3817 int ctrl = 0;
3818 if (pbpctl_dev->bp_caps & DISC_CAP) {
3819
3820 if ((ctrl = disc_off_status(pbpctl_dev)) < 0)
3821 return ctrl;
3822 return ((ctrl == 0) ? 1 : 0);
3823
3824 }
3825 return BP_NOT_CAP;
3826}
3827
0920af72 3828int default_pwron_disc_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3829{
3830 if (pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP) {
3831 if (pbpctl_dev->bp_ext_ver >= 0x8)
3832 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3833 DFLT_PWRON_DISC_MASK) ==
3834 DFLT_PWRON_DISC_MASK) ? 1 : 0);
3835 }
3836 return BP_NOT_CAP;
3837}
3838
0920af72 3839int dis_disc_cap_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3840{
3841 if (pbpctl_dev->bp_caps & DIS_DISC_CAP) {
3842 if (pbpctl_dev->bp_ext_ver >= 0x8)
3843 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3844 DIS_DISC_CAP_MASK) ==
3845 DIS_DISC_CAP_MASK) ? 1 : 0);
3846 }
3847 return BP_NOT_CAP;
3848}
3849
0920af72 3850int disc_port_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3851{
3852 int ret = BP_NOT_CAP;
3853 bpctl_dev_t *pbpctl_dev_m;
3854
3855 if ((is_bypass_fn(pbpctl_dev)) == 1)
3856 pbpctl_dev_m = pbpctl_dev;
3857 else
3858 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3859 if (pbpctl_dev_m == NULL)
3860 return BP_NOT_CAP;
3861
3862 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3863 if (is_bypass_fn(pbpctl_dev) == 1) {
3864 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3865 TX_DISA_MASK) == TX_DISA_MASK) ? 1 : 0);
3866 } else
3867 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3868 TX_DISB_MASK) == TX_DISB_MASK) ? 1 : 0);
3869
3870 }
3871 return ret;
3872}
3873
0920af72 3874int default_pwron_disc_port_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3875{
3876 int ret = BP_NOT_CAP;
3877 bpctl_dev_t *pbpctl_dev_m;
3878
3879 if ((is_bypass_fn(pbpctl_dev)) == 1)
3880 pbpctl_dev_m = pbpctl_dev;
3881 else
3882 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
3883 if (pbpctl_dev_m == NULL)
3884 return BP_NOT_CAP;
3885
3886 if (pbpctl_dev_m->bp_caps_ex & DISC_PORT_CAP_EX) {
3887 if (is_bypass_fn(pbpctl_dev) == 1)
3888 return ret;
687bcca0 3889 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
7040e556
D		 3890 else
3891 return ret;
687bcca0 3892 /* return((((read_reg(pbpctl_dev,STATUS_TAP_REG_ADDR)) & TX_DISA_MASK)==TX_DISA_MASK)?1:0); */
7040e556
D		 3893
3894 }
3895 return ret;
3896}
3897
0920af72 3898int wdt_exp_mode_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3899{
3900 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
3901 if (pbpctl_dev->bp_ext_ver <= PXG2BPI_VER)
3902 return 0; /* bypass mode */
3903 else if (pbpctl_dev->bp_ext_ver == PXG2TBPI_VER)
3904 return 1; /* tap mode */
3905 else if (pbpctl_dev->bp_ext_ver >= PXE2TBPI_VER) {
3906 if (pbpctl_dev->bp_ext_ver >= 0x8) {
3907 if (((read_reg
3908 (pbpctl_dev,
3909 STATUS_DISC_REG_ADDR)) &
3910 WDTE_DISC_BPN_MASK) == WDTE_DISC_BPN_MASK)
3911 return 2;
3912 }
3913 return ((((read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR)) &
3914 WDTE_TAP_BPN_MASK) ==
3915 WDTE_TAP_BPN_MASK) ? 1 : 0);
3916 }
3917 }
3918 return BP_NOT_CAP;
3919}
3920
9f7a6f33 3921int tpl2_flag_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3922{
3923
3924 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX) {
3925 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3926 TPL2_FLAG_MASK) == TPL2_FLAG_MASK) ? 1 : 0);
3927
3928 }
3929 return BP_NOT_CAP;
3930}
3931
9f7a6f33 3932int tpl_hw_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3933{
3934 bpctl_dev_t *pbpctl_dev_b = NULL;
3935
3936 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
3937 return BP_NOT_CAP;
3938
3939 if (TPL_IF_SERIES(pbpctl_dev->subdevice))
3940 return (((BPCTL_READ_REG(pbpctl_dev, CTRL)) &
3941 BPCTLI_CTRL_SWDPIN0) != 0 ? 1 : 0);
3942 return BP_NOT_CAP;
3943}
3944
7040e556 3945
9f7a6f33 3946int bp_wait_at_pwup_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3947{
3948 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3949 if (pbpctl_dev->bp_ext_ver >= 0x8)
3950 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3951 WAIT_AT_PWUP_MASK) ==
3952 WAIT_AT_PWUP_MASK) ? 1 : 0);
3953 }
3954 return BP_NOT_CAP;
3955}
3956
9f7a6f33 3957int bp_hw_reset_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3958{
3959
3960 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
3961
3962 if (pbpctl_dev->bp_ext_ver >= 0x8)
3963 return ((((read_reg(pbpctl_dev, CONT_CONFIG_REG_ADDR)) &
3964 EN_HW_RESET_MASK) ==
3965 EN_HW_RESET_MASK) ? 1 : 0);
3966 }
3967 return BP_NOT_CAP;
3968}
3969
7040e556 3970
9f7a6f33 3971int std_nic_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 3972{
3973 int status_val = 0;
3974
3975 if (pbpctl_dev->bp_caps & STD_NIC_CAP) {
3976 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
3977 return BP_NOT_CAP;
3978 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
3979 return ((((read_reg(pbpctl_dev, STATUS_DISC_REG_ADDR)) &
3980 STD_NIC_ON_MASK) == STD_NIC_ON_MASK) ? 1 : 0);
3981 }
3982
3983 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
3984 if (pbpctl_dev->bp_caps & BP_CAP) {
3985 status_val =
3986 read_reg(pbpctl_dev, STATUS_REG_ADDR);
3987 if (((!(status_val & WDT_EN_MASK))
3988 && ((status_val & STD_NIC_MASK) ==
3989 STD_NIC_MASK)))
3990 status_val = 1;
3991 else
3992 return 0;
3993 }
3994 if (pbpctl_dev->bp_caps & TAP_CAP) {
3995 status_val =
3996 read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
3997 if ((status_val & STD_NIC_TAP_MASK) ==
3998 STD_NIC_TAP_MASK)
3999 status_val = 1;
4000 else
4001 return 0;
4002 }
4003 if (pbpctl_dev->bp_caps & TAP_CAP) {
4004 if ((disc_off_status(pbpctl_dev)))
4005 status_val = 1;
4006 else
4007 return 0;
4008 }
4009
4010 return status_val;
4011 }
4012 }
4013 return BP_NOT_CAP;
4014}
4015
4016/******************************************************/
4017/**************SW_INIT*********************************/
4018/******************************************************/
9f7a6f33 4019void bypass_caps_init(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4020{
4021 u_int32_t ctrl_ext = 0;
4022 bpctl_dev_t *pbpctl_dev_m = NULL;
4023
4024#ifdef BYPASS_DEBUG
4025 int ret = 0;
4026 if (!(INTEL_IF_SERIES(adapter->bp_device_block.subdevice))) {
4027 ret = read_reg(pbpctl_dev, VER_REG_ADDR);
4028 printk("VER_REG reg1=%x\n", ret);
4029 ret = read_reg(pbpctl_dev, PRODUCT_CAP_REG_ADDR);
4030 printk("PRODUCT_CAP reg=%x\n", ret);
4031 ret = read_reg(pbpctl_dev, STATUS_TAP_REG_ADDR);
4032 printk("STATUS_TAP reg1=%x\n", ret);
4033 ret = read_reg(pbpctl_dev, 0x7);
4034 printk("SIG_REG reg1=%x\n", ret);
4035 ret = read_reg(pbpctl_dev, STATUS_REG_ADDR);
4036 printk("STATUS_REG_ADDR=%x\n", ret);
4037 ret = read_reg(pbpctl_dev, WDT_REG_ADDR);
4038 printk("WDT_REG_ADDR=%x\n", ret);
4039 ret = read_reg(pbpctl_dev, TMRL_REG_ADDR);
4040 printk("TMRL_REG_ADDR=%x\n", ret);
4041 ret = read_reg(pbpctl_dev, TMRH_REG_ADDR);
4042 printk("TMRH_REG_ADDR=%x\n", ret);
4043 }
4044#endif
4045 if ((pbpctl_dev->bp_fiber5) || (pbpctl_dev->bp_10g9)) {
4046 pbpctl_dev->media_type = bp_fiber;
4047 } else if (pbpctl_dev->bp_10gb) {
4048 if (BP10GB_CX4_SERIES(pbpctl_dev->subdevice))
4049 pbpctl_dev->media_type = bp_cx4;
4050 else
4051 pbpctl_dev->media_type = bp_fiber;
4052
4053 }
4054
4055 else if (pbpctl_dev->bp_540)
4056 pbpctl_dev->media_type = bp_none;
4057 else if (!pbpctl_dev->bp_10g) {
4058
4059 ctrl_ext = BPCTL_READ_REG(pbpctl_dev, CTRL_EXT);
4060 if ((ctrl_ext & BPCTLI_CTRL_EXT_LINK_MODE_MASK) == 0x0)
4061 pbpctl_dev->media_type = bp_copper;
4062 else
4063 pbpctl_dev->media_type = bp_fiber;
4064
687bcca0 4065 } else {
7040e556
D		 4066 if (BP10G_CX4_SERIES(pbpctl_dev->subdevice))
4067 pbpctl_dev->media_type = bp_cx4;
4068 else
4069 pbpctl_dev->media_type = bp_fiber;
4070 }
4071
7040e556
D		 4072 if (is_bypass_fn(pbpctl_dev)) {
4073
4074 pbpctl_dev->bp_caps |= BP_PWOFF_ON_CAP;
4075 if (pbpctl_dev->media_type == bp_fiber)
4076 pbpctl_dev->bp_caps |=
4077 (TX_CTL_CAP | TX_STATUS_CAP | TPL_CAP);
4078
4079 if (TPL_IF_SERIES(pbpctl_dev->subdevice)) {
4080 pbpctl_dev->bp_caps |= TPL_CAP;
4081 }
4082
4083 if (INTEL_IF_SERIES(pbpctl_dev->subdevice)) {
4084 pbpctl_dev->bp_caps |=
4085 (BP_CAP | BP_STATUS_CAP | SW_CTL_CAP |
4086 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWOFF_OFF_CAP
4087 | WD_CTL_CAP | WD_STATUS_CAP | STD_NIC_CAP |
4088 WD_TIMEOUT_CAP);
4089
4090 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4091 return;
4092 }
4093
4094 if ((pbpctl_dev->bp_fw_ver == 0xff) &&
4095 OLD_IF_SERIES(pbpctl_dev->subdevice)) {
4096
4097 pbpctl_dev->bp_caps |=
4098 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4099 SW_CTL_CAP | BP_PWUP_ON_CAP | WD_CTL_CAP |
4100 WD_STATUS_CAP | WD_TIMEOUT_CAP);
4101
4102 pbpctl_dev->bp_ext_ver = OLD_IF_VER;
4103 return;
4104 }
4105
4106 else {
4107 switch (pbpctl_dev->bp_fw_ver) {
4108 case BP_FW_VER_A0:
4109 case BP_FW_VER_A1:{
4110 pbpctl_dev->bp_ext_ver =
4111 (pbpctl_dev->
4112 bp_fw_ver & EXT_VER_MASK);
4113 break;
4114 }
4115 default:{
4116 if ((bypass_sign_check(pbpctl_dev)) !=
4117 1) {
4118 pbpctl_dev->bp_caps = 0;
4119 return;
4120 }
4121 pbpctl_dev->bp_ext_ver =
4122 (pbpctl_dev->
4123 bp_fw_ver & EXT_VER_MASK);
4124 }
4125 }
4126 }
4127
4128 if (pbpctl_dev->bp_ext_ver == PXG2BPI_VER)
4129 pbpctl_dev->bp_caps |=
4130 (BP_CAP | BP_STATUS_CAP | BP_STATUS_CHANGE_CAP |
4131 SW_CTL_CAP | BP_DIS_CAP | BP_DIS_STATUS_CAP |
4132 BP_PWUP_ON_CAP | BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP
4133 | WD_CTL_CAP | STD_NIC_CAP | WD_STATUS_CAP |
4134 WD_TIMEOUT_CAP);
4135 else if (pbpctl_dev->bp_ext_ver >= PXG2TBPI_VER) {
4136 int cap_reg;
4137
4138 pbpctl_dev->bp_caps |=
4139 (SW_CTL_CAP | WD_CTL_CAP | WD_STATUS_CAP |
4140 WD_TIMEOUT_CAP);
4141 cap_reg = get_bp_prod_caps(pbpctl_dev);
4142
4143 if ((cap_reg & NORMAL_UNSUPPORT_MASK) ==
4144 NORMAL_UNSUPPORT_MASK)
4145 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4146 else
4147 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4148
4149 if ((normal_support(pbpctl_dev)) == 1)
4150
4151 pbpctl_dev->bp_caps |= STD_NIC_CAP;
4152
4153 else
4154 pbpctl_dev->bp_caps |= NIC_CAP_NEG;
4155 if ((cap_reg & BYPASS_SUPPORT_MASK) ==
4156 BYPASS_SUPPORT_MASK) {
4157 pbpctl_dev->bp_caps |=
4158 (BP_CAP | BP_STATUS_CAP |
4159 BP_STATUS_CHANGE_CAP | BP_DIS_CAP |
4160 BP_DIS_STATUS_CAP | BP_PWUP_ON_CAP |
4161 BP_PWUP_OFF_CAP | BP_PWUP_CTL_CAP);
4162 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER7)
4163 pbpctl_dev->bp_caps |=
4164 BP_PWOFF_ON_CAP | BP_PWOFF_OFF_CAP |
4165 BP_PWOFF_CTL_CAP;
4166 }
4167 if ((cap_reg & TAP_SUPPORT_MASK) == TAP_SUPPORT_MASK) {
4168 pbpctl_dev->bp_caps |=
4169 (TAP_CAP | TAP_STATUS_CAP |
4170 TAP_STATUS_CHANGE_CAP | TAP_DIS_CAP |
4171 TAP_DIS_STATUS_CAP | TAP_PWUP_ON_CAP |
4172 TAP_PWUP_OFF_CAP | TAP_PWUP_CTL_CAP);
4173 }
4174 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER8) {
4175 if ((cap_reg & DISC_SUPPORT_MASK) ==
4176 DISC_SUPPORT_MASK)
4177 pbpctl_dev->bp_caps |=
4178 (DISC_CAP | DISC_DIS_CAP |
4179 DISC_PWUP_CTL_CAP);
4180 if ((cap_reg & TPL2_SUPPORT_MASK) ==
4181 TPL2_SUPPORT_MASK) {
4182 pbpctl_dev->bp_caps_ex |= TPL2_CAP_EX;
4183 pbpctl_dev->bp_caps |= TPL_CAP;
4184 pbpctl_dev->bp_tpl_flag =
4185 tpl2_flag_status(pbpctl_dev);
4186 }
4187
4188 }
4189
4190 if (pbpctl_dev->bp_ext_ver >= BP_FW_EXT_VER9) {
4191 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4192 DISC_PORT_SUPPORT_MASK) {
4193 pbpctl_dev->bp_caps_ex |=
4194 DISC_PORT_CAP_EX;
4195 pbpctl_dev->bp_caps |=
4196 (TX_CTL_CAP | TX_STATUS_CAP);
4197 }
4198
4199 }
4200
4201 }
4202 if (pbpctl_dev->bp_ext_ver >= PXG2BPI_VER) {
4203 if ((read_reg(pbpctl_dev, STATUS_REG_ADDR)) &
4204 WDT_EN_MASK)
4205 pbpctl_dev->wdt_status = WDT_STATUS_EN;
4206 else
4207 pbpctl_dev->wdt_status = WDT_STATUS_DIS;
4208 }
4209
4210 } else if ((P2BPFI_IF_SERIES(pbpctl_dev->subdevice)) ||
4211 (PEGF5_IF_SERIES(pbpctl_dev->subdevice)) ||
4212 (PEGF80_IF_SERIES(pbpctl_dev->subdevice)) ||
4213 (BP10G9_IF_SERIES(pbpctl_dev->subdevice))) {
4214 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4215 }
4216 if ((pbpctl_dev->subdevice & 0xa00) == 0xa00)
4217 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4218 if (PEG5_IF_SERIES(pbpctl_dev->subdevice))
4219 pbpctl_dev->bp_caps |= (TX_CTL_CAP | TX_STATUS_CAP);
4220
4221 if (BP10GB_IF_SERIES(pbpctl_dev->subdevice)) {
4222 pbpctl_dev->bp_caps &= ~(TX_CTL_CAP | TX_STATUS_CAP);
4223 }
4224 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4225 if (pbpctl_dev_m != NULL) {
4226 int cap_reg = 0;
4227 if (pbpctl_dev_m->bp_ext_ver >= 0x9) {
4228 cap_reg = get_bp_prod_caps(pbpctl_dev_m);
4229 if ((cap_reg & DISC_PORT_SUPPORT_MASK) ==
4230 DISC_PORT_SUPPORT_MASK)
4231 pbpctl_dev->bp_caps |=
4232 (TX_CTL_CAP | TX_STATUS_CAP);
4233 pbpctl_dev->bp_caps_ex |= DISC_PORT_CAP_EX;
4234 }
4235 }
4236}
4237
9f7a6f33 4238int bypass_off_init(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4239{
4240 int ret = 0;
4241
4242 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4243 return ret;
4244 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
7935c80c 4245 return dis_bypass_cap(pbpctl_dev);
7040e556
D		 4246 wdt_off(pbpctl_dev);
4247 if (pbpctl_dev->bp_caps & BP_CAP)
4248 bypass_off(pbpctl_dev);
4249 if (pbpctl_dev->bp_caps & TAP_CAP)
4250 tap_off(pbpctl_dev);
4251 cmnd_off(pbpctl_dev);
4252 return 0;
4253}
4254
9f7a6f33 4255void remove_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4256{
4257#ifdef BP_SELF_TEST
4258 bpctl_dev_t *pbpctl_dev_sl = NULL;
4259#endif
4260
4261 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4262
4263 del_timer_sync(&pbpctl_dev->bp_timer);
4264#ifdef BP_SELF_TEST
4265 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
7040e556
D		 4266 if (pbpctl_dev_sl && (pbpctl_dev_sl->ndev)) {
4267 if ((pbpctl_dev_sl->ndev->netdev_ops)
4268 && (pbpctl_dev_sl->old_ops)) {
4269 rtnl_lock();
4270 pbpctl_dev_sl->ndev->netdev_ops =
4271 pbpctl_dev_sl->old_ops;
4272 pbpctl_dev_sl->old_ops = NULL;
4273
4274 rtnl_unlock();
4275
4276 }
4277
4278 }
7040e556
D		 4279#endif
4280 }
4281
4282}
4283
9f7a6f33 4284int init_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4285{
4286 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4287 init_timer(&pbpctl_dev->bp_timer);
4288 pbpctl_dev->bp_timer.function = &wd_reset_timer;
4289 pbpctl_dev->bp_timer.data = (unsigned long)pbpctl_dev;
4290 return 1;
4291 }
4292 return BP_NOT_CAP;
4293}
4294
4295#ifdef BP_SELF_TEST
4296int bp_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
4297{
4298 bpctl_dev_t *pbpctl_dev = NULL, *pbpctl_dev_m = NULL;
4299 int idx_dev = 0;
4300 struct ethhdr *eth = (struct ethhdr *)skb->data;
4301
4302 for (idx_dev = 0;
4303 ((bpctl_dev_arr[idx_dev].ndev != NULL) && (idx_dev < device_num));
4304 idx_dev++) {
4305 if (bpctl_dev_arr[idx_dev].ndev == dev) {
4306 pbpctl_dev = &bpctl_dev_arr[idx_dev];
4307 break;
4308 }
4309 }
4310 if (!pbpctl_dev)
4311 return 1;
4312 if ((htons(ETH_P_BPTEST) == eth->h_proto)) {
4313
4314 pbpctl_dev_m = get_master_port_fn(pbpctl_dev);
4315 if (pbpctl_dev_m) {
4316
4317 if (bypass_status(pbpctl_dev_m)) {
4318 cmnd_on(pbpctl_dev_m);
4319 bypass_off(pbpctl_dev_m);
4320 cmnd_off(pbpctl_dev_m);
4321 }
4322 wdt_timer_reload(pbpctl_dev_m);
4323 }
4324 dev_kfree_skb_irq(skb);
4325 return 0;
4326 }
7935c80c 4327 return pbpctl_dev->hard_start_xmit_save(skb, dev);
7040e556
D		 4328}
4329#endif
4330
9f7a6f33 4331int set_bypass_wd_auto(bpctl_dev_t *pbpctl_dev, unsigned int param)
7040e556
D		 4332{
4333 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4334 if (pbpctl_dev->reset_time != param) {
4335 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4336 pbpctl_dev->reset_time =
4337 (param <
4338 WDT_AUTO_MIN_INT) ? WDT_AUTO_MIN_INT :
4339 param;
4340 else
4341 pbpctl_dev->reset_time = param;
4342 if (param)
4343 mod_timer(&pbpctl_dev->bp_timer, jiffies);
4344 }
4345 return 0;
4346 }
4347 return BP_NOT_CAP;
4348}
4349
9f7a6f33 4350int get_bypass_wd_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4351{
4352
4353 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4354 return pbpctl_dev->reset_time;
4355 }
4356 return BP_NOT_CAP;
4357}
4358
4359#ifdef BP_SELF_TEST
4360
9f7a6f33 4361int set_bp_self_test(bpctl_dev_t *pbpctl_dev, unsigned int param)
7040e556
D		 4362{
4363 bpctl_dev_t *pbpctl_dev_sl = NULL;
4364
4365 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4366 pbpctl_dev->bp_self_test_flag = param == 0 ? 0 : 1;
4367 pbpctl_dev_sl = get_status_port_fn(pbpctl_dev);
7040e556 4368
7040e556
D		 4369 if ((pbpctl_dev_sl->ndev) && (pbpctl_dev_sl->ndev->netdev_ops)) {
4370 rtnl_lock();
4371 if (pbpctl_dev->bp_self_test_flag == 1) {
4372
4373 pbpctl_dev_sl->old_ops =
4374 pbpctl_dev_sl->ndev->netdev_ops;
4375 pbpctl_dev_sl->new_ops =
4376 *pbpctl_dev_sl->old_ops;
4377 pbpctl_dev_sl->new_ops.ndo_start_xmit =
4378 bp_hard_start_xmit;
4379 pbpctl_dev_sl->ndev->netdev_ops =
4380 &pbpctl_dev_sl->new_ops;
4381
4382 } else if (pbpctl_dev_sl->old_ops) {
4383 pbpctl_dev_sl->ndev->netdev_ops =
4384 pbpctl_dev_sl->old_ops;
4385 pbpctl_dev_sl->old_ops = NULL;
4386 }
4387 rtnl_unlock();
4388 }
7040e556
D		 4389
4390 set_bypass_wd_auto(pbpctl_dev, param);
4391 return 0;
4392 }
4393 return BP_NOT_CAP;
4394}
4395
9f7a6f33 4396int get_bp_self_test(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4397{
4398
4399 if (pbpctl_dev->bp_caps & WD_CTL_CAP) {
4400 if (pbpctl_dev->bp_self_test_flag == 1)
4401 return pbpctl_dev->reset_time;
4402 else
4403 return 0;
4404 }
4405 return BP_NOT_CAP;
4406}
4407
4408#endif
4409
4410/**************************************************************/
4411/************************* API ********************************/
4412/**************************************************************/
4413
9f7a6f33 4414int is_bypass_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4415{
4416 if (!pbpctl_dev)
4417 return -1;
4418
4419 return (((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) ? 1 : 0);
4420}
4421
9f7a6f33 4422int set_bypass_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
7040e556
D		 4423{
4424 int ret = 0;
4425
4426 if (!(pbpctl_dev->bp_caps & BP_CAP))
4427 return BP_NOT_CAP;
4428 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4429 return ret;
4430 if (!bypass_mode)
4431 ret = bypass_off(pbpctl_dev);
4432 else
4433 ret = bypass_on(pbpctl_dev);
4434 cmnd_off(pbpctl_dev);
4435
4436 return ret;
4437}
4438
9f7a6f33 4439int get_bypass_fn(bpctl_dev_t *pbpctl_dev)
7040e556 4440{
7935c80c 4441 return bypass_status(pbpctl_dev);
7040e556
D		 4442}
4443
9f7a6f33 4444int get_bypass_change_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4445{
4446 if (!pbpctl_dev)
4447 return -1;
4448
7935c80c 4449 return bypass_change_status(pbpctl_dev);
7040e556
D		 4450}
4451
9f7a6f33 4452int set_dis_bypass_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
7040e556
D		 4453{
4454 int ret = 0;
4455 if (!pbpctl_dev)
4456 return -1;
4457
4458 if (!(pbpctl_dev->bp_caps & BP_DIS_CAP))
4459 return BP_NOT_CAP;
4460 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4461 return ret;
4462 if (dis_param)
4463 ret = dis_bypass_cap(pbpctl_dev);
4464 else
4465 ret = en_bypass_cap(pbpctl_dev);
4466 cmnd_off(pbpctl_dev);
4467 return ret;
4468}
4469
9f7a6f33 4470int get_dis_bypass_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4471{
4472 if (!pbpctl_dev)
4473 return -1;
4474
7935c80c 4475 return dis_bypass_cap_status(pbpctl_dev);
7040e556
D		 4476}
4477
9f7a6f33 4478int set_bypass_pwoff_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
7040e556
D		 4479{
4480 int ret = 0;
4481 if (!pbpctl_dev)
4482 return -1;
4483
4484 if (!(pbpctl_dev->bp_caps & BP_PWOFF_CTL_CAP))
4485 return BP_NOT_CAP;
4486 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4487 return ret;
4488 if (bypass_mode)
4489 ret = bypass_state_pwroff(pbpctl_dev);
4490 else
4491 ret = normal_state_pwroff(pbpctl_dev);
4492 cmnd_off(pbpctl_dev);
4493 return ret;
4494}
4495
9f7a6f33 4496int get_bypass_pwoff_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4497{
4498 if (!pbpctl_dev)
4499 return -1;
4500
7935c80c 4501 return default_pwroff_status(pbpctl_dev);
7040e556
D		 4502}
4503
9f7a6f33 4504int set_bypass_pwup_fn(bpctl_dev_t *pbpctl_dev, int bypass_mode)
7040e556
D		 4505{
4506 int ret = 0;
4507 if (!pbpctl_dev)
4508 return -1;
4509
4510 if (!(pbpctl_dev->bp_caps & BP_PWUP_CTL_CAP))
4511 return BP_NOT_CAP;
4512 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4513 return ret;
4514 if (bypass_mode)
4515 ret = bypass_state_pwron(pbpctl_dev);
4516 else
4517 ret = normal_state_pwron(pbpctl_dev);
4518 cmnd_off(pbpctl_dev);
4519 return ret;
4520}
4521
9f7a6f33 4522int get_bypass_pwup_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4523{
4524 if (!pbpctl_dev)
4525 return -1;
4526
7935c80c 4527 return default_pwron_status(pbpctl_dev);
7040e556
D		 4528}
4529
9f7a6f33 4530int set_bypass_wd_fn(bpctl_dev_t *pbpctl_dev, int timeout)
7040e556
D		 4531{
4532 int ret = 0;
4533 if (!pbpctl_dev)
4534 return -1;
4535
4536 if (!(pbpctl_dev->bp_caps & WD_CTL_CAP))
4537 return BP_NOT_CAP;
4538
4539 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4540 return ret;
4541 if (!timeout)
4542 ret = wdt_off(pbpctl_dev);
4543 else {
4544 wdt_on(pbpctl_dev, timeout);
4545 ret = pbpctl_dev->bypass_timer_interval;
4546 }
4547 cmnd_off(pbpctl_dev);
4548 return ret;
4549}
4550
9f7a6f33 4551int get_bypass_wd_fn(bpctl_dev_t *pbpctl_dev, int *timeout)
7040e556
D		 4552{
4553 if (!pbpctl_dev)
4554 return -1;
4555
4556 return wdt_programmed(pbpctl_dev, timeout);
4557}
4558
9f7a6f33 4559int get_wd_expire_time_fn(bpctl_dev_t *pbpctl_dev, int *time_left)
7040e556
D		 4560{
4561 if (!pbpctl_dev)
4562 return -1;
4563
7935c80c 4564 return wdt_timer(pbpctl_dev, time_left);
7040e556
D		 4565}
4566
9f7a6f33 4567int reset_bypass_wd_timer_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4568{
4569 if (!pbpctl_dev)
4570 return -1;
4571
7935c80c 4572 return wdt_timer_reload(pbpctl_dev);
7040e556
D		 4573}
4574
9f7a6f33 4575int get_wd_set_caps_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4576{
4577 int bp_status = 0;
4578
4579 unsigned int step_value = TIMEOUT_MAX_STEP + 1, bit_cnt = 0;
4580 if (!pbpctl_dev)
4581 return -1;
4582
4583 if (INTEL_IF_SERIES(pbpctl_dev->subdevice))
4584 return BP_NOT_CAP;
4585
4586 while ((step_value >>= 1))
4587 bit_cnt++;
4588
4589 if (is_bypass_fn(pbpctl_dev)) {
4590 bp_status =
4591 WD_STEP_COUNT_MASK(bit_cnt) | WDT_STEP_TIME |
4592 WD_MIN_TIME_MASK(TIMEOUT_UNIT / 100);
4593 } else
4594 return -1;
4595
4596 return bp_status;
4597}
4598
9f7a6f33 4599int set_std_nic_fn(bpctl_dev_t *pbpctl_dev, int nic_mode)
7040e556
D		 4600{
4601 int ret = 0;
4602 if (!pbpctl_dev)
4603 return -1;
4604
4605 if (!(pbpctl_dev->bp_caps & STD_NIC_CAP))
4606 return BP_NOT_CAP;
4607
4608 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4609 return ret;
4610 if (nic_mode)
4611 ret = std_nic_on(pbpctl_dev);
4612 else
4613 ret = std_nic_off(pbpctl_dev);
4614 cmnd_off(pbpctl_dev);
4615 return ret;
4616}
4617
9f7a6f33 4618int get_std_nic_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4619{
4620 if (!pbpctl_dev)
4621 return -1;
4622
7935c80c 4623 return std_nic_status(pbpctl_dev);
7040e556
D		 4624}
4625
9f7a6f33 4626int set_tap_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
7040e556
D		 4627{
4628 if (!pbpctl_dev)
4629 return -1;
4630
4631 if ((pbpctl_dev->bp_caps & TAP_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4632 if (!tap_mode)
4633 tap_off(pbpctl_dev);
4634 else
4635 tap_on(pbpctl_dev);
4636 cmnd_off(pbpctl_dev);
4637 return 0;
4638 }
4639 return BP_NOT_CAP;
4640}
4641
9f7a6f33 4642int get_tap_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4643{
4644 if (!pbpctl_dev)
4645 return -1;
4646
7935c80c 4647 return tap_status(pbpctl_dev);
7040e556
D		 4648}
4649
9f7a6f33 4650int set_tap_pwup_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
7040e556
D		 4651{
4652 int ret = 0;
4653 if (!pbpctl_dev)
4654 return -1;
4655
4656 if ((pbpctl_dev->bp_caps & TAP_PWUP_CTL_CAP)
4657 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4658 if (tap_mode)
4659 ret = tap_state_pwron(pbpctl_dev);
4660 else
4661 ret = normal_state_pwron(pbpctl_dev);
4662 cmnd_off(pbpctl_dev);
4663 } else
4664 ret = BP_NOT_CAP;
4665 return ret;
4666}
4667
9f7a6f33 4668int get_tap_pwup_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4669{
4670 int ret = 0;
4671 if (!pbpctl_dev)
4672 return -1;
4673
4674 if ((ret = default_pwron_tap_status(pbpctl_dev)) < 0)
4675 return ret;
4676 return ((ret == 0) ? 1 : 0);
4677}
4678
9f7a6f33 4679int get_tap_change_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4680{
4681 if (!pbpctl_dev)
4682 return -1;
4683
7935c80c 4684 return tap_change_status(pbpctl_dev);
7040e556
D		 4685}
4686
9f7a6f33 4687int set_dis_tap_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
7040e556
D		 4688{
4689 int ret = 0;
4690 if (!pbpctl_dev)
4691 return -1;
4692
4693 if ((pbpctl_dev->bp_caps & TAP_DIS_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4694 if (dis_param)
4695 ret = dis_tap_cap(pbpctl_dev);
4696 else
4697 ret = en_tap_cap(pbpctl_dev);
4698 cmnd_off(pbpctl_dev);
4699 return ret;
4700 } else
4701 return BP_NOT_CAP;
4702}
4703
9f7a6f33 4704int get_dis_tap_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4705{
4706 if (!pbpctl_dev)
4707 return -1;
4708
7935c80c 4709 return dis_tap_cap_status(pbpctl_dev);
7040e556
D		 4710}
4711
9f7a6f33 4712int set_disc_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
7040e556
D		 4713{
4714 if (!pbpctl_dev)
4715 return -1;
4716
4717 if ((pbpctl_dev->bp_caps & DISC_CAP) && ((cmnd_on(pbpctl_dev)) >= 0)) {
4718 if (!disc_mode)
4719 disc_off(pbpctl_dev);
4720 else
4721 disc_on(pbpctl_dev);
4722 cmnd_off(pbpctl_dev);
4723
4724 return BP_OK;
4725 }
4726 return BP_NOT_CAP;
4727}
4728
9f7a6f33 4729int get_disc_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4730{
4731 int ret = 0;
4732 if (!pbpctl_dev)
4733 return -1;
4734
4735 ret = disc_status(pbpctl_dev);
4736
4737 return ret;
4738}
4739
9f7a6f33 4740int set_disc_pwup_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
7040e556
D		 4741{
4742 int ret = 0;
4743 if (!pbpctl_dev)
4744 return -1;
4745
4746 if ((pbpctl_dev->bp_caps & DISC_PWUP_CTL_CAP)
4747 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4748 if (disc_mode)
4749 ret = disc_state_pwron(pbpctl_dev);
4750 else
4751 ret = normal_state_pwron(pbpctl_dev);
4752 cmnd_off(pbpctl_dev);
4753 } else
4754 ret = BP_NOT_CAP;
4755 return ret;
4756}
4757
9f7a6f33 4758int get_disc_pwup_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4759{
4760 int ret = 0;
4761 if (!pbpctl_dev)
4762 return -1;
4763
4764 ret = default_pwron_disc_status(pbpctl_dev);
4765 return (ret == 0 ? 1 : (ret < 0 ? BP_NOT_CAP : 0));
4766}
4767
7c014321 4768int get_disc_change_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4769{
4770 int ret = 0;
4771 if (!pbpctl_dev)
4772 return -1;
4773
4774 ret = disc_change_status(pbpctl_dev);
4775 return ret;
4776}
4777
7c014321 4778int set_dis_disc_fn(bpctl_dev_t *pbpctl_dev, int dis_param)
7040e556
D		 4779{
4780 int ret = 0;
4781 if (!pbpctl_dev)
4782 return -1;
4783
4784 if ((pbpctl_dev->bp_caps & DISC_DIS_CAP)
4785 && ((cmnd_on(pbpctl_dev)) >= 0)) {
4786 if (dis_param)
4787 ret = dis_disc_cap(pbpctl_dev);
4788 else
4789 ret = en_disc_cap(pbpctl_dev);
4790 cmnd_off(pbpctl_dev);
4791 return ret;
4792 } else
4793 return BP_NOT_CAP;
4794}
4795
7c014321 4796int get_dis_disc_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4797{
4798 int ret = 0;
4799 if (!pbpctl_dev)
4800 return -1;
4801
4802 ret = dis_disc_cap_status(pbpctl_dev);
4803
4804 return ret;
4805}
4806
7c014321 4807int set_disc_port_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
7040e556
D		 4808{
4809 int ret = BP_NOT_CAP;
4810 if (!pbpctl_dev)
4811 return -1;
4812
4813 if (!disc_mode)
4814 ret = disc_port_off(pbpctl_dev);
4815 else
4816 ret = disc_port_on(pbpctl_dev);
4817
4818 return ret;
4819}
4820
7c014321 4821int get_disc_port_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4822{
4823 if (!pbpctl_dev)
4824 return -1;
4825
7935c80c 4826 return disc_port_status(pbpctl_dev);
7040e556
D		 4827}
4828
7c014321 4829int set_disc_port_pwup_fn(bpctl_dev_t *pbpctl_dev, int disc_mode)
7040e556
D		 4830{
4831 int ret = BP_NOT_CAP;
4832 if (!pbpctl_dev)
4833 return -1;
4834
4835 if (!disc_mode)
4836 ret = normal_port_state_pwron(pbpctl_dev);
4837 else
4838 ret = disc_port_state_pwron(pbpctl_dev);
4839
4840 return ret;
4841}
4842
7c014321 4843int get_disc_port_pwup_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4844{
4845 int ret = 0;
4846 if (!pbpctl_dev)
4847 return -1;
4848
4849 if ((ret = default_pwron_disc_port_status(pbpctl_dev)) < 0)
4850 return ret;
4851 return ((ret == 0) ? 1 : 0);
4852}
4853
7c014321 4854int get_wd_exp_mode_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4855{
4856 if (!pbpctl_dev)
4857 return -1;
4858
7935c80c 4859 return wdt_exp_mode_status(pbpctl_dev);
7040e556
D		 4860}
4861
7c014321 4862int set_wd_exp_mode_fn(bpctl_dev_t *pbpctl_dev, int param)
7040e556
D		 4863{
4864 if (!pbpctl_dev)
4865 return -1;
4866
7935c80c 4867 return wdt_exp_mode(pbpctl_dev, param);
7040e556
D		 4868}
4869
7c014321 4870int reset_cont_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4871{
4872 int ret = 0;
4873 if (!pbpctl_dev)
4874 return -1;
4875
4876 if ((ret = cmnd_on(pbpctl_dev)) < 0)
4877 return ret;
7935c80c 4878 return reset_cont(pbpctl_dev);
7040e556
D		 4879}
4880
7c014321 4881int set_tx_fn(bpctl_dev_t *pbpctl_dev, int tx_state)
7040e556
D		 4882{
4883
4884 bpctl_dev_t *pbpctl_dev_b = NULL;
4885 if (!pbpctl_dev)
4886 return -1;
4887
4888 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
4889 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
4890 if ((pbpctl_dev->bp_tpl_flag))
4891 return BP_NOT_CAP;
4892 } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
4893 if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
4894 (pbpctl_dev_b->bp_tpl_flag))
4895 return BP_NOT_CAP;
4896 }
7935c80c 4897 return set_tx(pbpctl_dev, tx_state);
7040e556
D		 4898}
4899
4900int set_bp_force_link_fn(int dev_num, int tx_state)
4901{
4902 static bpctl_dev_t *bpctl_dev_curr;
4903
4904 if ((dev_num < 0) || (dev_num > device_num)
4905 || (bpctl_dev_arr[dev_num].pdev == NULL))
4906 return -1;
4907 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
4908
7935c80c 4909 return set_bp_force_link(bpctl_dev_curr, tx_state);
7040e556
D		 4910}
4911
7c014321 4912int set_wd_autoreset_fn(bpctl_dev_t *pbpctl_dev, int param)
7040e556
D		 4913{
4914 if (!pbpctl_dev)
4915 return -1;
4916
7935c80c 4917 return set_bypass_wd_auto(pbpctl_dev, param);
7040e556
D		 4918}
4919
7c014321 4920int get_wd_autoreset_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4921{
4922 if (!pbpctl_dev)
4923 return -1;
4924
7935c80c 4925 return get_bypass_wd_auto(pbpctl_dev);
7040e556
D		 4926}
4927
4928#ifdef BP_SELF_TEST
7c014321 4929int set_bp_self_test_fn(bpctl_dev_t *pbpctl_dev, int param)
7040e556
D		 4930{
4931 if (!pbpctl_dev)
4932 return -1;
4933
7935c80c 4934 return set_bp_self_test(pbpctl_dev, param);
7040e556
D		 4935}
4936
7c014321 4937int get_bp_self_test_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4938{
4939 if (!pbpctl_dev)
4940 return -1;
4941
7935c80c 4942 return get_bp_self_test(pbpctl_dev);
7040e556
D		 4943}
4944
4945#endif
4946
7c014321 4947int get_bypass_caps_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4948{
4949 if (!pbpctl_dev)
4950 return -1;
4951
7935c80c 4952 return pbpctl_dev->bp_caps;
7040e556
D		 4953
4954}
4955
7c014321 4956int get_bypass_slave_fn(bpctl_dev_t *pbpctl_dev, bpctl_dev_t **pbpctl_dev_out)
7040e556
D		 4957{
4958 int idx_dev = 0;
4959 if (!pbpctl_dev)
4960 return -1;
4961
4962 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2)) {
4963 for (idx_dev = 0;
4964 ((bpctl_dev_arr[idx_dev].pdev != NULL)
4965 && (idx_dev < device_num)); idx_dev++) {
4966 if ((bpctl_dev_arr[idx_dev].bus == pbpctl_dev->bus)
4967 && (bpctl_dev_arr[idx_dev].slot ==
4968 pbpctl_dev->slot)) {
4969 if ((pbpctl_dev->func == 0)
4970 && (bpctl_dev_arr[idx_dev].func == 1)) {
4971 *pbpctl_dev_out =
4972 &bpctl_dev_arr[idx_dev];
4973 return 1;
4974 }
4975 if ((pbpctl_dev->func == 2) &&
4976 (bpctl_dev_arr[idx_dev].func == 3)) {
4977 *pbpctl_dev_out =
4978 &bpctl_dev_arr[idx_dev];
4979 return 1;
4980 }
4981 }
4982 }
4983 return -1;
4984 } else
4985 return 0;
4986}
4987
7c014321 4988int is_bypass(bpctl_dev_t *pbpctl_dev)
7040e556
D		 4989{
4990 if (!pbpctl_dev)
4991 return -1;
4992
4993 if ((pbpctl_dev->func == 0) || (pbpctl_dev->func == 2))
4994 return 1;
4995 else
4996 return 0;
4997}
4998
7c014321 4999int get_tx_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5000{
5001 bpctl_dev_t *pbpctl_dev_b = NULL;
5002 if (!pbpctl_dev)
5003 return -1;
5004
5005 if ((pbpctl_dev->bp_caps & TPL_CAP) &&
5006 (pbpctl_dev->bp_caps & SW_CTL_CAP)) {
5007 if ((pbpctl_dev->bp_tpl_flag))
5008 return BP_NOT_CAP;
5009 } else if ((pbpctl_dev_b = get_master_port_fn(pbpctl_dev))) {
5010 if ((pbpctl_dev_b->bp_caps & TPL_CAP) &&
5011 (pbpctl_dev_b->bp_tpl_flag))
5012 return BP_NOT_CAP;
5013 }
7935c80c 5014 return tx_status(pbpctl_dev);
7040e556
D		 5015}
5016
5017int get_bp_force_link_fn(int dev_num)
5018{
5019 static bpctl_dev_t *bpctl_dev_curr;
5020
5021 if ((dev_num < 0) || (dev_num > device_num)
5022 || (bpctl_dev_arr[dev_num].pdev == NULL))
5023 return -1;
5024 bpctl_dev_curr = &bpctl_dev_arr[dev_num];
5025
7935c80c 5026 return bp_force_link_status(bpctl_dev_curr);
7040e556
D		 5027}
5028
7c014321 5029static int get_bypass_link_status(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5030{
5031 if (!pbpctl_dev)
5032 return -1;
5033
5034 if (pbpctl_dev->media_type == bp_fiber)
5035 return ((BPCTL_READ_REG(pbpctl_dev, CTRL) &
5036 BPCTLI_CTRL_SWDPIN1));
5037 else
5038 return ((BPCTL_READ_REG(pbpctl_dev, STATUS) &
5039 BPCTLI_STATUS_LU));
5040
5041}
5042
5043static void bp_tpl_timer_fn(unsigned long param)
5044{
5045 bpctl_dev_t *pbpctl_dev = (bpctl_dev_t *) param;
5046 uint32_t link1, link2;
5047 bpctl_dev_t *pbpctl_dev_b = NULL;
5048
5049 if (!(pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5050 return;
5051
5052 if (!pbpctl_dev->bp_tpl_flag) {
5053 set_tx(pbpctl_dev_b, 1);
5054 set_tx(pbpctl_dev, 1);
5055 return;
5056 }
5057 link1 = get_bypass_link_status(pbpctl_dev);
5058
5059 link2 = get_bypass_link_status(pbpctl_dev_b);
5060 if ((link1) && (tx_status(pbpctl_dev))) {
5061 if ((!link2) && (tx_status(pbpctl_dev_b))) {
5062 set_tx(pbpctl_dev, 0);
5063 } else if (!tx_status(pbpctl_dev_b)) {
5064 set_tx(pbpctl_dev_b, 1);
5065 }
5066 } else if ((!link1) && (tx_status(pbpctl_dev))) {
5067 if ((link2) && (tx_status(pbpctl_dev_b))) {
5068 set_tx(pbpctl_dev_b, 0);
5069 }
5070 } else if ((link1) && (!tx_status(pbpctl_dev))) {
5071 if ((link2) && (tx_status(pbpctl_dev_b))) {
5072 set_tx(pbpctl_dev, 1);
5073 }
5074 } else if ((!link1) && (!tx_status(pbpctl_dev))) {
5075 if ((link2) && (tx_status(pbpctl_dev_b))) {
5076 set_tx(pbpctl_dev, 1);
5077 }
5078 }
5079
5080 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + BP_LINK_MON_DELAY * HZ);
5081}
5082
7c014321 5083void remove_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5084{
5085 bpctl_dev_t *pbpctl_dev_b = NULL;
5086 if (!pbpctl_dev)
5087 return;
5088 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5089
5090 if (pbpctl_dev->bp_caps & TPL_CAP) {
5091 del_timer_sync(&pbpctl_dev->bp_tpl_timer);
5092 pbpctl_dev->bp_tpl_flag = 0;
5093 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5094 if (pbpctl_dev_b)
5095 set_tx(pbpctl_dev_b, 1);
5096 set_tx(pbpctl_dev, 1);
5097 }
5098 return;
5099}
5100
7c014321 5101int init_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5102{
5103 if (!pbpctl_dev)
5104 return -1;
5105 if (pbpctl_dev->bp_caps & TPL_CAP) {
5106 init_timer(&pbpctl_dev->bp_tpl_timer);
5107 pbpctl_dev->bp_tpl_timer.function = &bp_tpl_timer_fn;
5108 pbpctl_dev->bp_tpl_timer.data = (unsigned long)pbpctl_dev;
5109 return BP_OK;
5110 }
5111 return BP_NOT_CAP;
5112}
5113
7c014321 5114int set_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev, unsigned int param)
7040e556
D		 5115{
5116 if (!pbpctl_dev)
5117 return -1;
5118 if (pbpctl_dev->bp_caps & TPL_CAP) {
5119 if ((param) && (!pbpctl_dev->bp_tpl_flag)) {
5120 pbpctl_dev->bp_tpl_flag = param;
5121 mod_timer(&pbpctl_dev->bp_tpl_timer, jiffies + 1);
5122 return BP_OK;
5123 };
5124 if ((!param) && (pbpctl_dev->bp_tpl_flag))
5125 remove_bypass_tpl_auto(pbpctl_dev);
5126
5127 return BP_OK;
5128 }
5129 return BP_NOT_CAP;
5130}
5131
7c014321 5132int get_bypass_tpl_auto(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5133{
5134 if (!pbpctl_dev)
5135 return -1;
5136 if (pbpctl_dev->bp_caps & TPL_CAP) {
5137 return pbpctl_dev->bp_tpl_flag;
5138 }
5139 return BP_NOT_CAP;
5140}
5141
7c014321 5142int set_tpl_fn(bpctl_dev_t *pbpctl_dev, int tpl_mode)
7040e556
D		 5143{
5144
5145 bpctl_dev_t *pbpctl_dev_b = NULL;
5146 if (!pbpctl_dev)
5147 return -1;
5148
5149 pbpctl_dev_b = get_status_port_fn(pbpctl_dev);
5150
5151 if (pbpctl_dev->bp_caps & TPL_CAP) {
5152 if (tpl_mode) {
5153 if ((pbpctl_dev_b = get_status_port_fn(pbpctl_dev)))
5154 set_tx(pbpctl_dev_b, 1);
5155 set_tx(pbpctl_dev, 1);
5156 }
5157 if ((TPL_IF_SERIES(pbpctl_dev->subdevice)) ||
5158 (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)) {
5159 pbpctl_dev->bp_tpl_flag = tpl_mode;
5160 if (!tpl_mode)
5161 tpl_hw_off(pbpctl_dev);
5162 else
5163 tpl_hw_on(pbpctl_dev);
5164 } else
5165 set_bypass_tpl_auto(pbpctl_dev, tpl_mode);
5166 return 0;
5167 }
5168 return BP_NOT_CAP;
5169}
5170
7c014321 5171int get_tpl_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5172{
5173 int ret = BP_NOT_CAP;
5174 if (!pbpctl_dev)
5175 return -1;
5176
5177 if (pbpctl_dev->bp_caps & TPL_CAP) {
5178 if (pbpctl_dev->bp_caps_ex & TPL2_CAP_EX)
7935c80c 5179 return tpl2_flag_status(pbpctl_dev);
7040e556
D		 5180 ret = pbpctl_dev->bp_tpl_flag;
5181 }
5182 return ret;
5183}
5184
7c014321 5185int set_bp_wait_at_pwup_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
7040e556
D		 5186{
5187 if (!pbpctl_dev)
5188 return -1;
5189
5190 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
687bcca0 5191 /* bp_lock(pbp_device_block); */
7040e556
D		 5192 cmnd_on(pbpctl_dev);
5193 if (!tap_mode)
5194 bp_wait_at_pwup_dis(pbpctl_dev);
5195 else
5196 bp_wait_at_pwup_en(pbpctl_dev);
5197 cmnd_off(pbpctl_dev);
5198
687bcca0 5199 /* bp_unlock(pbp_device_block); */
7040e556
D		 5200 return BP_OK;
5201 }
5202 return BP_NOT_CAP;
5203}
5204
7c014321 5205int get_bp_wait_at_pwup_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5206{
5207 int ret = 0;
5208 if (!pbpctl_dev)
5209 return -1;
5210
687bcca0 5211 /* bp_lock(pbp_device_block); */
7040e556 5212 ret = bp_wait_at_pwup_status(pbpctl_dev);
687bcca0 5213 /* bp_unlock(pbp_device_block); */
7040e556
D		 5214
5215 return ret;
5216}
5217
7c014321 5218int set_bp_hw_reset_fn(bpctl_dev_t *pbpctl_dev, int tap_mode)
7040e556
D		 5219{
5220 if (!pbpctl_dev)
5221 return -1;
5222
5223 if (pbpctl_dev->bp_caps & SW_CTL_CAP) {
687bcca0 5224 /* bp_lock(pbp_device_block); */
7040e556
D		 5225 cmnd_on(pbpctl_dev);
5226
5227 if (!tap_mode)
5228 bp_hw_reset_dis(pbpctl_dev);
5229 else
5230 bp_hw_reset_en(pbpctl_dev);
5231 cmnd_off(pbpctl_dev);
687bcca0 5232 /* bp_unlock(pbp_device_block); */
7040e556
D		 5233 return BP_OK;
5234 }
5235 return BP_NOT_CAP;
5236}
5237
7c014321 5238int get_bp_hw_reset_fn(bpctl_dev_t *pbpctl_dev)
7040e556
D		 5239{
5240 int ret = 0;
5241 if (!pbpctl_dev)
5242 return -1;
5243
687bcca0 5244 /* bp_lock(pbp_device_block); */
7040e556
D		 5245 ret = bp_hw_reset_status(pbpctl_dev);
5246
687bcca0 5247 /* bp_unlock(pbp_device_block); */
7040e556
D		 5248
5249 return ret;
5250}
5251
7040e556 5252
7c014321 5253int get_bypass_info_fn(bpctl_dev_t *pbpctl_dev, char *dev_name,
7040e556
D		 5254 char *add_param)
5255{
5256 if (!pbpctl_dev)
5257 return -1;
5258 if (!is_bypass_fn(pbpctl_dev))
5259 return -1;
5260 strcpy(dev_name, pbpctl_dev->name);
5261 *add_param = pbpctl_dev->bp_fw_ver;
5262 return 0;
5263}
5264
5265int get_dev_idx_bsf(int bus, int slot, int func)
5266{
5267 int idx_dev = 0;
7040e556
D		 5268 for (idx_dev = 0;
5269 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5270 idx_dev++) {
5271 if ((bus == bpctl_dev_arr[idx_dev].bus)
5272 && (slot == bpctl_dev_arr[idx_dev].slot)
5273 && (func == bpctl_dev_arr[idx_dev].func))
5274
5275 return idx_dev;
5276 }
5277 return -1;
5278}
5279
5280static void str_low(char *str)
5281{
5282 int i;
5283
5284 for (i = 0; i < strlen(str); i++)
5285 if ((str[i] >= 65) && (str[i] <= 90))
5286 str[i] += 32;
5287}
5288
5289static unsigned long str_to_hex(char *p)
5290{
5291 unsigned long hex = 0;
5292 unsigned long length = strlen(p), shift = 0;
5293 unsigned char dig = 0;
5294
5295 str_low(p);
5296 length = strlen(p);
5297
5298 if (length == 0)
5299 return 0;
5300
5301 do {
5302 dig = p[--length];
5303 dig = dig < 'a' ? (dig - '0') : (dig - 'a' + 0xa);
5304 hex |= (dig << shift);
5305 shift += 4;
5306 } while (length);
5307 return hex;
5308}
5309
5310static int get_dev_idx(int ifindex)
5311{
5312 int idx_dev = 0;
5313
5314 for (idx_dev = 0;
5315 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5316 idx_dev++) {
5317 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5318 return idx_dev;
5319 }
5320
5321 return -1;
5322}
5323
5324static bpctl_dev_t *get_dev_idx_p(int ifindex)
5325{
5326 int idx_dev = 0;
5327
5328 for (idx_dev = 0;
5329 ((bpctl_dev_arr[idx_dev].pdev != NULL) && (idx_dev < device_num));
5330 idx_dev++) {
5331 if (ifindex == bpctl_dev_arr[idx_dev].ifindex)
5332 return &bpctl_dev_arr[idx_dev];
5333 }
5334
5335 return NULL;
5336}
5337
5338static void if_scan_init(void)
5339{
5340 int idx_dev = 0;
5341 struct net_device *dev;
5342 int ifindex;
687bcca0
DC		 5343 /* rcu_read_lock(); */
5344 /* rtnl_lock(); */
5345 /* rcu_read_lock(); */
3e4cce9d
CW		 5346
5347 for_each_netdev(&init_net, dev) {
7040e556
D		 5348
5349 struct ethtool_drvinfo drvinfo;
7040e556
D		 5350 char cbuf[32];
5351 char *buf = NULL;
5352 char res[10];
5353 int i = 0;
5354 int bus = 0, slot = 0, func = 0;
5355 ifindex = dev->ifindex;
5356
5357 memset(res, 0, 10);
5358 memset(&drvinfo, 0, sizeof(struct ethtool_drvinfo));
5359
5360 if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
5361 memset(&drvinfo, 0, sizeof(drvinfo));
5362 dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
5363 } else
5364 continue;
7040e556
D		 5365 if (!strcmp(drvinfo.bus_info, "N/A"))
5366 continue;
5367 memcpy(&cbuf, drvinfo.bus_info, 32);
5368 buf = &cbuf[0];
5369
7040e556
D		 5370 while (*buf++ != ':') ;
5371 for (i = 0; i < 10; i++, buf++) {
5372 if (*buf == ':')
5373 break;
5374 res[i] = *buf;
5375
5376 }
5377 buf++;
5378 bus = str_to_hex(res);
5379 memset(res, 0, 10);
5380
5381 for (i = 0; i < 10; i++, buf++) {
5382 if (*buf == '.')
5383 break;
5384 res[i] = *buf;
5385
5386 }
5387 buf++;
5388 slot = str_to_hex(res);
5389 func = str_to_hex(buf);
5390 idx_dev = get_dev_idx_bsf(bus, slot, func);
5391
5392 if (idx_dev != -1) {
5393
5394 bpctl_dev_arr[idx_dev].ifindex = ifindex;
5395 bpctl_dev_arr[idx_dev].ndev = dev;
5396
5397 }
5398
5399 }
687bcca0
DC		 5400 /* rtnl_unlock(); */
5401 /* rcu_read_unlock(); */
7040e556
D		 5402
5403}
5404
3e4cce9d 5405static long device_ioctl(struct file *file, /* see include/linux/fs.h */
7040e556
D		 5406 unsigned int ioctl_num, /* number and param for ioctl */
5407 unsigned long ioctl_param)
7040e556
D		 5408{
5409 struct bpctl_cmd bpctl_cmd;
5410 int dev_idx = 0;
5411 bpctl_dev_t *pbpctl_dev_out;
5412 void __user *argp = (void __user *)ioctl_param;
5413 int ret = 0;
5414 unsigned long flags;
5415
5416 static bpctl_dev_t *pbpctl_dev;
5417
687bcca0 5418 /* lock_kernel(); */
7040e556 5419 lock_bpctl();
687bcca0
DC		 5420 /* local_irq_save(flags); */
5421 /* if(!spin_trylock_irqsave(&bpvm_lock)){
7040e556 5422 local_irq_restore(flags);
687bcca0
DC		 5423 unlock_bpctl();
5424 unlock_kernel();
7040e556
D		 5425 return -1;
5426 } */
687bcca0 5427 /* spin_lock_irqsave(&bpvm_lock, flags); */
7040e556
D		 5428
5429/*
5430* Switch according to the ioctl called
5431*/
5432 if (ioctl_num == IOCTL_TX_MSG(IF_SCAN)) {
5433 if_scan_init();
5434 ret = SUCCESS;
5435 goto bp_exit;
5436 }
5437 if (copy_from_user(&bpctl_cmd, argp, sizeof(struct bpctl_cmd))) {
5438
5439 ret = -EFAULT;
5440 goto bp_exit;
5441 }
5442
5443 if (ioctl_num == IOCTL_TX_MSG(GET_DEV_NUM)) {
5444 bpctl_cmd.out_param[0] = device_num;
5445 if (copy_to_user
5446 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
5447 ret = -EFAULT;
5448 goto bp_exit;
5449 }
5450 ret = SUCCESS;
5451 goto bp_exit;
5452
5453 }
687bcca0
DC		 5454 /* lock_bpctl(); */
5455 /* preempt_disable(); */
7040e556
D		 5456 local_irq_save(flags);
5457 if (!spin_trylock(&bpvm_lock)) {
5458 local_irq_restore(flags);
5459 unlock_bpctl();
7040e556
D		 5460 return -1;
5461 }
687bcca0
DC		 5462
5463/* preempt_disable();
5464 rcu_read_lock();
5465 spin_lock_irqsave(&bpvm_lock, flags);
5466*/
7040e556
D		 5467 if ((bpctl_cmd.in_param[5]) ||
5468 (bpctl_cmd.in_param[6]) || (bpctl_cmd.in_param[7]))
5469 dev_idx = get_dev_idx_bsf(bpctl_cmd.in_param[5],
5470 bpctl_cmd.in_param[6],
5471 bpctl_cmd.in_param[7]);
5472 else if (bpctl_cmd.in_param[1] == 0)
5473 dev_idx = bpctl_cmd.in_param[0];
5474 else
5475 dev_idx = get_dev_idx(bpctl_cmd.in_param[1]);
5476
5477 if (dev_idx < 0 || dev_idx > device_num) {
687bcca0
DC		 5478 /* unlock_bpctl();
5479 preempt_enable(); */
7040e556 5480 ret = -EOPNOTSUPP;
687bcca0
DC		 5481 /* preempt_enable();
5482 rcu_read_unlock(); */
7040e556
D		 5483 spin_unlock_irqrestore(&bpvm_lock, flags);
5484 goto bp_exit;
5485 }
5486
5487 bpctl_cmd.out_param[0] = bpctl_dev_arr[dev_idx].bus;
5488 bpctl_cmd.out_param[1] = bpctl_dev_arr[dev_idx].slot;
5489 bpctl_cmd.out_param[2] = bpctl_dev_arr[dev_idx].func;
5490 bpctl_cmd.out_param[3] = bpctl_dev_arr[dev_idx].ifindex;
5491
5492 if ((bpctl_dev_arr[dev_idx].bp_10gb)
5493 && (!(bpctl_dev_arr[dev_idx].ifindex))) {
5494 printk("Please load network driver for %s adapter!\n",
5495 bpctl_dev_arr[dev_idx].name);
5496 bpctl_cmd.status = -1;
5497 ret = SUCCESS;
687bcca0
DC		 5498 /* preempt_enable(); */
5499 /* rcu_read_unlock(); */
7040e556
D		 5500 spin_unlock_irqrestore(&bpvm_lock, flags);
5501 goto bp_exit;
5502
5503 }
5504 if ((bpctl_dev_arr[dev_idx].bp_10gb) && (bpctl_dev_arr[dev_idx].ndev)) {
5505 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5506 if (!(bpctl_dev_arr[dev_idx].ndev->flags & IFF_UP)) {
5507 printk
5508 ("Please bring up network interfaces for %s adapter!\n",
5509 bpctl_dev_arr[dev_idx].name);
5510 bpctl_cmd.status = -1;
5511 ret = SUCCESS;
687bcca0
DC		 5512 /* preempt_enable(); */
5513 /* rcu_read_unlock(); */
7040e556
D		 5514 spin_unlock_irqrestore(&bpvm_lock, flags);
5515 goto bp_exit;
5516 }
5517
5518 }
5519 }
5520
5521 if ((dev_idx < 0) || (dev_idx > device_num)
5522 || (bpctl_dev_arr[dev_idx].pdev == NULL)) {
5523 bpctl_cmd.status = -1;
5524 goto bpcmd_exit;
5525 }
5526
5527 pbpctl_dev = &bpctl_dev_arr[dev_idx];
5528
5529 switch (ioctl_num) {
5530 case IOCTL_TX_MSG(SET_BYPASS_PWOFF):
5531 bpctl_cmd.status =
5532 set_bypass_pwoff_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5533 break;
5534
5535 case IOCTL_TX_MSG(GET_BYPASS_PWOFF):
5536 bpctl_cmd.status = get_bypass_pwoff_fn(pbpctl_dev);
5537 break;
5538
5539 case IOCTL_TX_MSG(SET_BYPASS_PWUP):
5540 bpctl_cmd.status =
5541 set_bypass_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5542 break;
5543
5544 case IOCTL_TX_MSG(GET_BYPASS_PWUP):
5545 bpctl_cmd.status = get_bypass_pwup_fn(pbpctl_dev);
5546 break;
5547
5548 case IOCTL_TX_MSG(SET_BYPASS_WD):
5549 bpctl_cmd.status =
5550 set_bypass_wd_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5551 break;
5552
5553 case IOCTL_TX_MSG(GET_BYPASS_WD):
5554 bpctl_cmd.status =
5555 get_bypass_wd_fn(pbpctl_dev, (int *)&(bpctl_cmd.data[0]));
5556 break;
5557
5558 case IOCTL_TX_MSG(GET_WD_EXPIRE_TIME):
5559 bpctl_cmd.status =
5560 get_wd_expire_time_fn(pbpctl_dev,
5561 (int *)&(bpctl_cmd.data[0]));
5562 break;
5563
5564 case IOCTL_TX_MSG(RESET_BYPASS_WD_TIMER):
5565 bpctl_cmd.status = reset_bypass_wd_timer_fn(pbpctl_dev);
5566 break;
5567
5568 case IOCTL_TX_MSG(GET_WD_SET_CAPS):
5569 bpctl_cmd.status = get_wd_set_caps_fn(pbpctl_dev);
5570 break;
5571
5572 case IOCTL_TX_MSG(SET_STD_NIC):
5573 bpctl_cmd.status =
5574 set_std_nic_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5575 break;
5576
5577 case IOCTL_TX_MSG(GET_STD_NIC):
5578 bpctl_cmd.status = get_std_nic_fn(pbpctl_dev);
5579 break;
5580
5581 case IOCTL_TX_MSG(SET_TAP):
5582 bpctl_cmd.status =
5583 set_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5584 break;
5585
5586 case IOCTL_TX_MSG(GET_TAP):
5587 bpctl_cmd.status = get_tap_fn(pbpctl_dev);
5588 break;
5589
5590 case IOCTL_TX_MSG(GET_TAP_CHANGE):
5591 bpctl_cmd.status = get_tap_change_fn(pbpctl_dev);
5592 break;
5593
5594 case IOCTL_TX_MSG(SET_DIS_TAP):
5595 bpctl_cmd.status =
5596 set_dis_tap_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5597 break;
5598
5599 case IOCTL_TX_MSG(GET_DIS_TAP):
5600 bpctl_cmd.status = get_dis_tap_fn(pbpctl_dev);
5601 break;
5602
5603 case IOCTL_TX_MSG(SET_TAP_PWUP):
5604 bpctl_cmd.status =
5605 set_tap_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5606 break;
5607
5608 case IOCTL_TX_MSG(GET_TAP_PWUP):
5609 bpctl_cmd.status = get_tap_pwup_fn(pbpctl_dev);
5610 break;
5611
5612 case IOCTL_TX_MSG(SET_WD_EXP_MODE):
5613 bpctl_cmd.status =
5614 set_wd_exp_mode_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5615 break;
5616
5617 case IOCTL_TX_MSG(GET_WD_EXP_MODE):
5618 bpctl_cmd.status = get_wd_exp_mode_fn(pbpctl_dev);
5619 break;
5620
5621 case IOCTL_TX_MSG(GET_DIS_BYPASS):
5622 bpctl_cmd.status = get_dis_bypass_fn(pbpctl_dev);
5623 break;
5624
5625 case IOCTL_TX_MSG(SET_DIS_BYPASS):
5626 bpctl_cmd.status =
5627 set_dis_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5628 break;
5629
5630 case IOCTL_TX_MSG(GET_BYPASS_CHANGE):
5631 bpctl_cmd.status = get_bypass_change_fn(pbpctl_dev);
5632 break;
5633
5634 case IOCTL_TX_MSG(GET_BYPASS):
5635 bpctl_cmd.status = get_bypass_fn(pbpctl_dev);
5636 break;
5637
5638 case IOCTL_TX_MSG(SET_BYPASS):
5639 bpctl_cmd.status =
5640 set_bypass_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5641 break;
5642
5643 case IOCTL_TX_MSG(GET_BYPASS_CAPS):
5644 bpctl_cmd.status = get_bypass_caps_fn(pbpctl_dev);
5645 /*preempt_enable(); */
687bcca0 5646 /*rcu_read_unlock();*/
7040e556
D		 5647 spin_unlock_irqrestore(&bpvm_lock, flags);
5648 if (copy_to_user
5649 (argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd))) {
687bcca0
DC		 5650 /*unlock_bpctl(); */
5651 /*preempt_enable(); */
7040e556
D		 5652 ret = -EFAULT;
5653 goto bp_exit;
5654 }
5655 goto bp_exit;
5656
5657 case IOCTL_TX_MSG(GET_BYPASS_SLAVE):
5658 bpctl_cmd.status =
5659 get_bypass_slave_fn(pbpctl_dev, &pbpctl_dev_out);
5660 if (bpctl_cmd.status == 1) {
5661 bpctl_cmd.out_param[4] = pbpctl_dev_out->bus;
5662 bpctl_cmd.out_param[5] = pbpctl_dev_out->slot;
5663 bpctl_cmd.out_param[6] = pbpctl_dev_out->func;
5664 bpctl_cmd.out_param[7] = pbpctl_dev_out->ifindex;
5665 }
5666 break;
5667
5668 case IOCTL_TX_MSG(IS_BYPASS):
5669 bpctl_cmd.status = is_bypass(pbpctl_dev);
5670 break;
5671 case IOCTL_TX_MSG(SET_TX):
5672 bpctl_cmd.status = set_tx_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5673 break;
5674 case IOCTL_TX_MSG(GET_TX):
5675 bpctl_cmd.status = get_tx_fn(pbpctl_dev);
5676 break;
5677 case IOCTL_TX_MSG(SET_WD_AUTORESET):
5678 bpctl_cmd.status =
5679 set_wd_autoreset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5680
5681 break;
5682 case IOCTL_TX_MSG(GET_WD_AUTORESET):
5683
5684 bpctl_cmd.status = get_wd_autoreset_fn(pbpctl_dev);
5685 break;
5686 case IOCTL_TX_MSG(SET_DISC):
5687 bpctl_cmd.status =
5688 set_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5689 break;
5690 case IOCTL_TX_MSG(GET_DISC):
5691 bpctl_cmd.status = get_disc_fn(pbpctl_dev);
5692 break;
5693 case IOCTL_TX_MSG(GET_DISC_CHANGE):
5694 bpctl_cmd.status = get_disc_change_fn(pbpctl_dev);
5695 break;
5696 case IOCTL_TX_MSG(SET_DIS_DISC):
5697 bpctl_cmd.status =
5698 set_dis_disc_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5699 break;
5700 case IOCTL_TX_MSG(GET_DIS_DISC):
5701 bpctl_cmd.status = get_dis_disc_fn(pbpctl_dev);
5702 break;
5703 case IOCTL_TX_MSG(SET_DISC_PWUP):
5704 bpctl_cmd.status =
5705 set_disc_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5706 break;
5707 case IOCTL_TX_MSG(GET_DISC_PWUP):
5708 bpctl_cmd.status = get_disc_pwup_fn(pbpctl_dev);
5709 break;
5710
5711 case IOCTL_TX_MSG(GET_BYPASS_INFO):
5712
5713 bpctl_cmd.status =
5714 get_bypass_info_fn(pbpctl_dev, (char *)&bpctl_cmd.data,
5715 (char *)&bpctl_cmd.out_param[4]);
5716 break;
5717
5718 case IOCTL_TX_MSG(SET_TPL):
5719 bpctl_cmd.status =
5720 set_tpl_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5721 break;
5722
5723 case IOCTL_TX_MSG(GET_TPL):
5724 bpctl_cmd.status = get_tpl_fn(pbpctl_dev);
5725 break;
7040e556
D		 5726 case IOCTL_TX_MSG(SET_BP_WAIT_AT_PWUP):
5727 bpctl_cmd.status =
5728 set_bp_wait_at_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5729 break;
5730
5731 case IOCTL_TX_MSG(GET_BP_WAIT_AT_PWUP):
5732 bpctl_cmd.status = get_bp_wait_at_pwup_fn(pbpctl_dev);
5733 break;
5734 case IOCTL_TX_MSG(SET_BP_HW_RESET):
5735 bpctl_cmd.status =
5736 set_bp_hw_reset_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5737 break;
5738
5739 case IOCTL_TX_MSG(GET_BP_HW_RESET):
5740 bpctl_cmd.status = get_bp_hw_reset_fn(pbpctl_dev);
5741 break;
7040e556
D		 5742#ifdef BP_SELF_TEST
5743 case IOCTL_TX_MSG(SET_BP_SELF_TEST):
5744 bpctl_cmd.status =
5745 set_bp_self_test_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5746
5747 break;
5748 case IOCTL_TX_MSG(GET_BP_SELF_TEST):
5749 bpctl_cmd.status = get_bp_self_test_fn(pbpctl_dev);
5750 break;
5751
5752#endif
5753#if 0
5754 case IOCTL_TX_MSG(SET_DISC_PORT):
5755 bpctl_cmd.status =
5756 set_disc_port_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5757 break;
5758
5759 case IOCTL_TX_MSG(GET_DISC_PORT):
5760 bpctl_cmd.status = get_disc_port_fn(pbpctl_dev);
5761 break;
5762
5763 case IOCTL_TX_MSG(SET_DISC_PORT_PWUP):
5764 bpctl_cmd.status =
5765 set_disc_port_pwup_fn(pbpctl_dev, bpctl_cmd.in_param[2]);
5766 break;
5767
5768 case IOCTL_TX_MSG(GET_DISC_PORT_PWUP):
5769 bpctl_cmd.status = get_disc_port_pwup_fn(pbpctl_dev);
5770 break;
5771#endif
5772 case IOCTL_TX_MSG(SET_BP_FORCE_LINK):
5773 bpctl_cmd.status =
5774 set_bp_force_link_fn(dev_idx, bpctl_cmd.in_param[2]);
5775 break;
5776
5777 case IOCTL_TX_MSG(GET_BP_FORCE_LINK):
5778 bpctl_cmd.status = get_bp_force_link_fn(dev_idx);
5779 break;
5780
5781 default:
687bcca0 5782 /* unlock_bpctl(); */
7040e556
D		 5783
5784 ret = -EOPNOTSUPP;
687bcca0
DC		 5785 /* preempt_enable(); */
5786 /* rcu_read_unlock();*/
7040e556
D		 5787 spin_unlock_irqrestore(&bpvm_lock, flags);
5788 goto bp_exit;
5789 }
687bcca0
DC		 5790 /* unlock_bpctl(); */
5791 /* preempt_enable(); */
7040e556 5792 bpcmd_exit:
687bcca0 5793 /* rcu_read_unlock(); */
7040e556
D		 5794 spin_unlock_irqrestore(&bpvm_lock, flags);
5795 if (copy_to_user(argp, (void *)&bpctl_cmd, sizeof(struct bpctl_cmd)))
5796 ret = -EFAULT;
5797 ret = SUCCESS;
5798 bp_exit:
687bcca0 5799 /* unlock_kernel(); */
687bcca0 5800 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
7040e556 5801 unlock_bpctl();
687bcca0 5802 /* unlock_kernel(); */
7040e556
D		 5803 return ret;
5804}
5805
5806struct file_operations Fops = {
5807 .owner = THIS_MODULE,
7040e556 5808 .unlocked_ioctl = device_ioctl,
7040e556
D		 5809 .open = device_open,
5810 .release = device_release, /* a.k.a. close */
5811};
5812
5813#ifndef PCI_DEVICE
5814#define PCI_DEVICE(vend,dev) \
5815 .vendor = (vend), .device = (dev), \
5816 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
5817#endif
5818
5819#define SILICOM_E1000BP_ETHERNET_DEVICE(device_id) {\
5820 PCI_DEVICE(SILICOM_VID, device_id)}
5821
5822typedef enum {
5823 PXG2BPFI,
5824 PXG2BPFIL,
5825 PXG2BPFILX,
5826 PXG2BPFILLX,
5827 PXGBPI,
5828 PXGBPIG,
5829 PXG2TBFI,
5830 PXG4BPI,
5831 PXG4BPFI,
5832 PEG4BPI,
5833 PEG2BPI,
5834 PEG4BPIN,
5835 PEG2BPFI,
5836 PEG2BPFILX,
5837 PMCXG2BPFI,
5838 PMCXG2BPFIN,
5839 PEG4BPII,
5840 PEG4BPFII,
5841 PXG4BPFILX,
5842 PMCXG2BPIN,
5843 PMCXG4BPIN,
5844 PXG2BISC1,
5845 PEG2TBFI,
5846 PXG2TBI,
5847 PXG4BPFID,
5848 PEG4BPFI,
5849 PEG4BPIPT,
5850 PXG6BPI,
5851 PEG4BPIL,
5852 PMCXG2BPIN2,
5853 PMCXG4BPIN2,
5854 PMCX2BPI,
5855 PEG2BPFID,
5856 PEG2BPFIDLX,
5857 PMCX4BPI,
5858 MEG2BPFILN,
5859 MEG2BPFINX,
5860 PEG4BPFILX,
5861 PE10G2BPISR,
5862 PE10G2BPILR,
5863 MHIO8AD,
5864 PE10G2BPICX4,
5865 PEG2BPI5,
5866 PEG6BPI,
5867 PEG4BPFI5,
5868 PEG4BPFI5LX,
5869 MEG2BPFILXLN,
5870 PEG2BPIX1,
5871 MEG2BPFILXNX,
5872 XE10G2BPIT,
5873 XE10G2BPICX4,
5874 XE10G2BPISR,
5875 XE10G2BPILR,
5876 PEG4BPIIO,
5877 XE10G2BPIXR,
5878 PE10GDBISR,
5879 PE10GDBILR,
5880 PEG2BISC6,
5881 PEG6BPIFC,
5882 PE10G2BPTCX4,
5883 PE10G2BPTSR,
5884 PE10G2BPTLR,
5885 PE10G2BPTT,
5886 PEG4BPI6,
5887 PEG4BPFI6,
5888 PEG4BPFI6LX,
5889 PEG4BPFI6ZX,
5890 PEG2BPI6,
5891 PEG2BPFI6,
5892 PEG2BPFI6LX,
5893 PEG2BPFI6ZX,
5894 PEG2BPFI6FLXM,
5895 PEG4BPI6FC,
5896 PEG4BPFI6FC,
5897 PEG4BPFI6FCLX,
5898 PEG4BPFI6FCZX,
5899 PEG6BPI6,
5900 PEG2BPI6SC6,
5901 MEG2BPI6,
5902 XEG2BPI6,
5903 MEG4BPI6,
5904 PEG2BPFI5,
5905 PEG2BPFI5LX,
5906 PXEG4BPFI,
5907 M1EG2BPI6,
5908 M1EG2BPFI6,
5909 M1EG2BPFI6LX,
5910 M1EG2BPFI6ZX,
5911 M1EG4BPI6,
5912 M1EG4BPFI6,
5913 M1EG4BPFI6LX,
5914 M1EG4BPFI6ZX,
5915 M1EG6BPI6,
5916 M1E2G4BPi80,
5917 M1E2G4BPFi80,
5918 M1E2G4BPFi80LX,
5919 M1E2G4BPFi80ZX,
5920 PE210G2SPI9,
5921 M1E10G2BPI9CX4,
5922 M1E10G2BPI9SR,
5923 M1E10G2BPI9LR,
5924 M1E10G2BPI9T,
5925 PE210G2BPI9CX4,
5926 PE210G2BPI9SR,
5927 PE210G2BPI9LR,
5928 PE210G2BPI9T,
5929 M2EG2BPFI6,
5930 M2EG2BPFI6LX,
5931 M2EG2BPFI6ZX,
5932 M2EG4BPI6,
5933 M2EG4BPFI6,
5934 M2EG4BPFI6LX,
5935 M2EG4BPFI6ZX,
5936 M2EG6BPI6,
5937 PEG2DBI6,
5938 PEG2DBFI6,
5939 PEG2DBFI6LX,
5940 PEG2DBFI6ZX,
5941 PE2G4BPi80,
5942 PE2G4BPFi80,
5943 PE2G4BPFi80LX,
5944 PE2G4BPFi80ZX,
5945 PE2G4BPi80L,
5946 M6E2G8BPi80A,
5947
5948 PE2G2BPi35,
5949 PAC1200BPi35,
5950 PE2G2BPFi35,
5951 PE2G2BPFi35LX,
5952 PE2G2BPFi35ZX,
5953 PE2G4BPi35,
5954 PE2G4BPi35L,
5955 PE2G4BPFi35,
5956 PE2G4BPFi35LX,
5957 PE2G4BPFi35ZX,
5958
5959 PE2G6BPi35,
5960 PE2G6BPi35CX,
5961
5962 PE2G2BPi80,
5963 PE2G2BPFi80,
5964 PE2G2BPFi80LX,
5965 PE2G2BPFi80ZX,
5966 M2E10G2BPI9CX4,
5967 M2E10G2BPI9SR,
5968 M2E10G2BPI9LR,
5969 M2E10G2BPI9T,
5970 M6E2G8BPi80,
5971 PE210G2DBi9SR,
5972 PE210G2DBi9SRRB,
5973 PE210G2DBi9LR,
5974 PE210G2DBi9LRRB,
5975 PE310G4DBi940SR,
5976 PE310G4BPi9T,
5977 PE310G4BPi9SR,
5978 PE310G4BPi9LR,
5979 PE210G2BPi40,
5980} board_t;
5981
5982typedef struct _bpmod_info_t {
5983 unsigned int vendor;
5984 unsigned int device;
5985 unsigned int subvendor;
5986 unsigned int subdevice;
5987 unsigned int index;
5988 char *bp_name;
5989
5990} bpmod_info_t;
5991
5992typedef struct _dev_desc {
5993 char *name;
5994} dev_desc_t;
5995
5996dev_desc_t dev_desc[] = {
5997 {"Silicom Bypass PXG2BPFI-SD series adapter"},
5998 {"Silicom Bypass PXG2BPFIL-SD series adapter"},
5999 {"Silicom Bypass PXG2BPFILX-SD series adapter"},
6000 {"Silicom Bypass PXG2BPFILLX-SD series adapter"},
6001 {"Silicom Bypass PXG2BPI-SD series adapter"},
6002 {"Silicom Bypass PXG2BPIG-SD series adapter"},
6003 {"Silicom Bypass PXG2TBFI-SD series adapter"},
6004 {"Silicom Bypass PXG4BPI-SD series adapter"},
6005 {"Silicom Bypass PXG4BPFI-SD series adapter"},
6006 {"Silicom Bypass PEG4BPI-SD series adapter"},
6007 {"Silicom Bypass PEG2BPI-SD series adapter"},
6008 {"Silicom Bypass PEG4BPIN-SD series adapter"},
6009 {"Silicom Bypass PEG2BPFI-SD series adapter"},
6010 {"Silicom Bypass PEG2BPFI-LX-SD series adapter"},
6011 {"Silicom Bypass PMCX2BPFI-SD series adapter"},
6012 {"Silicom Bypass PMCX2BPFI-N series adapter"},
6013 {"Intel Bypass PEG2BPII series adapter"},
6014 {"Intel Bypass PEG2BPFII series adapter"},
6015 {"Silicom Bypass PXG4BPFILX-SD series adapter"},
6016 {"Silicom Bypass PMCX2BPI-N series adapter"},
6017 {"Silicom Bypass PMCX4BPI-N series adapter"},
6018 {"Silicom Bypass PXG2BISC1-SD series adapter"},
6019 {"Silicom Bypass PEG2TBFI-SD series adapter"},
6020 {"Silicom Bypass PXG2TBI-SD series adapter"},
6021 {"Silicom Bypass PXG4BPFID-SD series adapter"},
6022 {"Silicom Bypass PEG4BPFI-SD series adapter"},
6023 {"Silicom Bypass PEG4BPIPT-SD series adapter"},
6024 {"Silicom Bypass PXG6BPI-SD series adapter"},
6025 {"Silicom Bypass PEG4BPIL-SD series adapter"},
6026 {"Silicom Bypass PMCX2BPI-N2 series adapter"},
6027 {"Silicom Bypass PMCX4BPI-N2 series adapter"},
6028 {"Silicom Bypass PMCX2BPI-SD series adapter"},
6029 {"Silicom Bypass PEG2BPFID-SD series adapter"},
6030 {"Silicom Bypass PEG2BPFIDLX-SD series adapter"},
6031 {"Silicom Bypass PMCX4BPI-SD series adapter"},
6032 {"Silicom Bypass MEG2BPFILN-SD series adapter"},
6033 {"Silicom Bypass MEG2BPFINX-SD series adapter"},
6034 {"Silicom Bypass PEG4BPFILX-SD series adapter"},
6035 {"Silicom Bypass PE10G2BPISR-SD series adapter"},
6036 {"Silicom Bypass PE10G2BPILR-SD series adapter"},
6037 {"Silicom Bypass MHIO8AD-SD series adapter"},
6038 {"Silicom Bypass PE10G2BPICX4-SD series adapter"},
6039 {"Silicom Bypass PEG2BPI5-SD series adapter"},
6040 {"Silicom Bypass PEG6BPI5-SD series adapter"},
6041 {"Silicom Bypass PEG4BPFI5-SD series adapter"},
6042 {"Silicom Bypass PEG4BPFI5LX-SD series adapter"},
6043 {"Silicom Bypass MEG2BPFILXLN-SD series adapter"},
6044 {"Silicom Bypass PEG2BPIX1-SD series adapter"},
6045 {"Silicom Bypass MEG2BPFILXNX-SD series adapter"},
6046 {"Silicom Bypass XE10G2BPIT-SD series adapter"},
6047 {"Silicom Bypass XE10G2BPICX4-SD series adapter"},
6048 {"Silicom Bypass XE10G2BPISR-SD series adapter"},
6049 {"Silicom Bypass XE10G2BPILR-SD series adapter"},
6050 {"Intel Bypass PEG2BPFII0 series adapter"},
6051 {"Silicom Bypass XE10G2BPIXR series adapter"},
6052 {"Silicom Bypass PE10G2DBISR series adapter"},
6053 {"Silicom Bypass PEG2BI5SC6 series adapter"},
6054 {"Silicom Bypass PEG6BPI5FC series adapter"},
6055
6056 {"Silicom Bypass PE10G2BPTCX4 series adapter"},
6057 {"Silicom Bypass PE10G2BPTSR series adapter"},
6058 {"Silicom Bypass PE10G2BPTLR series adapter"},
6059 {"Silicom Bypass PE10G2BPTT series adapter"},
6060 {"Silicom Bypass PEG4BPI6 series adapter"},
6061 {"Silicom Bypass PEG4BPFI6 series adapter"},
6062 {"Silicom Bypass PEG4BPFI6LX series adapter"},
6063 {"Silicom Bypass PEG4BPFI6ZX series adapter"},
6064 {"Silicom Bypass PEG2BPI6 series adapter"},
6065 {"Silicom Bypass PEG2BPFI6 series adapter"},
6066 {"Silicom Bypass PEG2BPFI6LX series adapter"},
6067 {"Silicom Bypass PEG2BPFI6ZX series adapter"},
6068 {"Silicom Bypass PEG2BPFI6FLXM series adapter"},
6069 {"Silicom Bypass PEG4BPI6FC series adapter"},
6070 {"Silicom Bypass PEG4BPFI6FC series adapter"},
6071 {"Silicom Bypass PEG4BPFI6FCLX series adapter"},
6072 {"Silicom Bypass PEG4BPFI6FCZX series adapter"},
6073 {"Silicom Bypass PEG6BPI6 series adapter"},
6074 {"Silicom Bypass PEG2BPI6SC6 series adapter"},
6075 {"Silicom Bypass MEG2BPI6 series adapter"},
6076 {"Silicom Bypass XEG2BPI6 series adapter"},
6077 {"Silicom Bypass MEG4BPI6 series adapter"},
6078 {"Silicom Bypass PEG2BPFI5-SD series adapter"},
6079 {"Silicom Bypass PEG2BPFI5LX-SD series adapter"},
6080 {"Silicom Bypass PXEG4BPFI-SD series adapter"},
6081 {"Silicom Bypass MxEG2BPI6 series adapter"},
6082 {"Silicom Bypass MxEG2BPFI6 series adapter"},
6083 {"Silicom Bypass MxEG2BPFI6LX series adapter"},
6084 {"Silicom Bypass MxEG2BPFI6ZX series adapter"},
6085 {"Silicom Bypass MxEG4BPI6 series adapter"},
6086 {"Silicom Bypass MxEG4BPFI6 series adapter"},
6087 {"Silicom Bypass MxEG4BPFI6LX series adapter"},
6088 {"Silicom Bypass MxEG4BPFI6ZX series adapter"},
6089 {"Silicom Bypass MxEG6BPI6 series adapter"},
6090 {"Silicom Bypass MxE2G4BPi80 series adapter"},
6091 {"Silicom Bypass MxE2G4BPFi80 series adapter"},
6092 {"Silicom Bypass MxE2G4BPFi80LX series adapter"},
6093 {"Silicom Bypass MxE2G4BPFi80ZX series adapter"},
6094
6095 {"Silicom Bypass PE210G2SPI9 series adapter"},
6096
6097 {"Silicom Bypass MxE210G2BPI9CX4 series adapter"},
6098 {"Silicom Bypass MxE210G2BPI9SR series adapter"},
6099 {"Silicom Bypass MxE210G2BPI9LR series adapter"},
6100 {"Silicom Bypass MxE210G2BPI9T series adapter"},
6101
6102 {"Silicom Bypass PE210G2BPI9CX4 series adapter"},
6103 {"Silicom Bypass PE210G2BPI9SR series adapter"},
6104 {"Silicom Bypass PE210G2BPI9LR series adapter"},
6105 {"Silicom Bypass PE210G2BPI9T series adapter"},
6106
6107 {"Silicom Bypass M2EG2BPFI6 series adapter"},
6108 {"Silicom Bypass M2EG2BPFI6LX series adapter"},
6109 {"Silicom Bypass M2EG2BPFI6ZX series adapter"},
6110 {"Silicom Bypass M2EG4BPI6 series adapter"},
6111 {"Silicom Bypass M2EG4BPFI6 series adapter"},
6112 {"Silicom Bypass M2EG4BPFI6LX series adapter"},
6113 {"Silicom Bypass M2EG4BPFI6ZX series adapter"},
6114 {"Silicom Bypass M2EG6BPI6 series adapter"},
6115
6116 {"Silicom Bypass PEG2DBI6 series adapter"},
6117 {"Silicom Bypass PEG2DBFI6 series adapter"},
6118 {"Silicom Bypass PEG2DBFI6LX series adapter"},
6119 {"Silicom Bypass PEG2DBFI6ZX series adapter"},
6120
6121 {"Silicom Bypass PE2G4BPi80 series adapter"},
6122 {"Silicom Bypass PE2G4BPFi80 series adapter"},
6123 {"Silicom Bypass PE2G4BPFi80LX series adapter"},
6124 {"Silicom Bypass PE2G4BPFi80ZX series adapter"},
6125
6126 {"Silicom Bypass PE2G4BPi80L series adapter"},
6127 {"Silicom Bypass MxE2G8BPi80A series adapter"},
6128
6129 {"Silicom Bypass PE2G2BPi35 series adapter"},
6130 {"Silicom Bypass PAC1200BPi35 series adapter"},
6131 {"Silicom Bypass PE2G2BPFi35 series adapter"},
6132 {"Silicom Bypass PE2G2BPFi35LX series adapter"},
6133 {"Silicom Bypass PE2G2BPFi35ZX series adapter"},
6134
6135 {"Silicom Bypass PE2G4BPi35 series adapter"},
6136 {"Silicom Bypass PE2G4BPi35L series adapter"},
6137 {"Silicom Bypass PE2G4BPFi35 series adapter"},
6138 {"Silicom Bypass PE2G4BPFi35LX series adapter"},
6139 {"Silicom Bypass PE2G4BPFi35ZX series adapter"},
6140
6141 {"Silicom Bypass PE2G6BPi35 series adapter"},
6142 {"Silicom Bypass PE2G6BPi35CX series adapter"},
6143
6144 {"Silicom Bypass PE2G2BPi80 series adapter"},
6145 {"Silicom Bypass PE2G2BPFi80 series adapter"},
6146 {"Silicom Bypass PE2G2BPFi80LX series adapter"},
6147 {"Silicom Bypass PE2G2BPFi80ZX series adapter"},
6148
6149 {"Silicom Bypass M2E10G2BPI9CX4 series adapter"},
6150 {"Silicom Bypass M2E10G2BPI9SR series adapter"},
6151 {"Silicom Bypass M2E10G2BPI9LR series adapter"},
6152 {"Silicom Bypass M2E10G2BPI9T series adapter"},
6153 {"Silicom Bypass MxE2G8BPi80 series adapter"},
6154 {"Silicom Bypass PE210G2DBi9SR series adapter"},
6155 {"Silicom Bypass PE210G2DBi9SRRB series adapter"},
6156 {"Silicom Bypass PE210G2DBi9LR series adapter"},
6157 {"Silicom Bypass PE210G2DBi9LRRB series adapter"},
6158 {"Silicom Bypass PE310G4DBi9-SR series adapter"},
6159 {"Silicom Bypass PE310G4BPi9T series adapter"},
6160 {"Silicom Bypass PE310G4BPi9SR series adapter"},
6161 {"Silicom Bypass PE310G4BPi9LR series adapter"},
6162 {"Silicom Bypass PE210G2BPi40T series adapter"},
6163 {0},
6164};
6165
6166static bpmod_info_t tx_ctl_pci_tbl[] = {
6167 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFI_SSID, PXG2BPFI,
6168 "PXG2BPFI-SD"},
6169 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFIL_SSID, PXG2BPFIL,
6170 "PXG2BPFIL-SD"},
6171 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILX_SSID, PXG2BPFILX,
6172 "PXG2BPFILX-SD"},
6173 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2BPFILLX_SSID, PXG2BPFILLX,
6174 "PXG2BPFILLXSD"},
6175 {0x8086, 0x1010, SILICOM_SVID, SILICOM_PXGBPI_SSID, PXGBPI,
6176 "PXG2BPI-SD"},
6177 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXGBPIG_SSID, PXGBPIG,
6178 "PXG2BPIG-SD"},
6179 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG2TBFI_SSID, PXG2TBFI,
6180 "PXG2TBFI-SD"},
6181 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6182 "PXG4BPI-SD"},
6183 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6184 "PXG4BPFI-SD"},
6185 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFILX_SSID, PXG4BPFILX,
6186 "PXG4BPFILX-SD"},
6187 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PEG4BPI_SSID, PEG4BPI,
6188 "PEXG4BPI-SD"},
6189 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPI_SSID, PEG2BPI,
6190 "PEG2BPI-SD"},
6191 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIN_SSID, PEG4BPIN,
6192 "PEG4BPI-SD"},
6193 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFI_SSID, PEG2BPFI,
6194 "PEG2BPFI-SD"},
6195 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFILX_SSID, PEG2BPFILX,
6196 "PEG2BPFILX-SD"},
6197 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PMCXG2BPFI_SSID, PMCXG2BPFI,
6198 "PMCX2BPFI-SD"},
6199 {0x8086, 0x107a, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPFIN_SSID,
6200 PMCXG2BPFIN, "PMCX2BPFI-N"},
6201 {0x8086, INTEL_PEG4BPII_PID, 0x8086, INTEL_PEG4BPII_SSID, PEG4BPII,
6202 "PEG4BPII"},
6203 {0x8086, INTEL_PEG4BPIIO_PID, 0x8086, INTEL_PEG4BPIIO_SSID, PEG4BPIIO,
6204 "PEG4BPII0"},
6205 {0x8086, INTEL_PEG4BPFII_PID, 0x8086, INTEL_PEG4BPFII_SSID, PEG4BPFII,
6206 "PEG4BPFII"},
6207 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN_SSID,
6208 PMCXG2BPIN, "PMCX2BPI-N"},
6209 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN_SSID,
6210 PMCXG4BPIN, "PMCX4BPI-N"},
6211 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6212 "PXG2BISC1-SD"},
6213 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2TBFI_SSID, PEG2TBFI,
6214 "PEG2TBFI-SD"},
6215 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6216 "PXG2TBI-SD"},
6217 {0x8086, 0x107a, SILICOM_SVID, SILICOM_PXG4BPFID_SSID, PXG4BPFID,
6218 "PXG4BPFID-SD"},
6219 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6220 "PEG4BPFI-SD"},
6221 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG4BPIPT_SSID, PEG4BPIPT,
6222 "PEG4BPIPT-SD"},
6223 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PXG6BPI_SSID, PXG6BPI,
6224 "PXG6BPI-SD"},
6225 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6226 SILICOM_PEG4BPIL_SSID /*PCI_ANY_ID */ , PEG4BPIL, "PEG4BPIL-SD"},
6227 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG2BPIN2_SSID,
6228 PMCXG2BPIN2, "PMCX2BPI-N2"},
6229 {0x8086, 0x1079, NOKIA_PMCXG2BPFIN_SVID, NOKIA_PMCXG4BPIN2_SSID,
6230 PMCXG4BPIN2, "PMCX4BPI-N2"},
6231 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX2BPI_SSID, PMCX2BPI,
6232 "PMCX2BPI-SD"},
6233 {0x8086, 0x1079, SILICOM_SVID, SILICOM_PMCX4BPI_SSID, PMCX4BPI,
6234 "PMCX4BPI-SD"},
6235 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFID_SSID, PEG2BPFID,
6236 "PEG2BPFID-SD"},
6237 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG2BPFIDLX_SSID, PEG2BPFIDLX,
6238 "PEG2BPFIDLXSD"},
6239 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILN_SSID, MEG2BPFILN,
6240 "MEG2BPFILN-SD"},
6241 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFINX_SSID, MEG2BPFINX,
6242 "MEG2BPFINX-SD"},
6243 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PEG4BPFILX_SSID, PEG4BPFILX,
6244 "PEG4BPFILX-SD"},
6245 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPISR_SSID,
6246 PE10G2BPISR, "PE10G2BPISR"},
6247 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPILR_SSID,
6248 PE10G2BPILR, "PE10G2BPILR"},
6249 {0x8086, 0x10a9, SILICOM_SVID, SILICOM_MHIO8AD_SSID, MHIO8AD,
6250 "MHIO8AD-SD"},
6251 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_PE10G2BPICX4_SSID,
6252 PE10G2BPISR, "PE10G2BPICX4"},
6253 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6254 SILICOM_PEG2BPI5_SSID /*PCI_ANY_ID */ , PEG2BPI5, "PEG2BPI5-SD"},
6255 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6256 SILICOM_PEG6BPI_SSID /*PCI_ANY_ID */ , PEG6BPI, "PEG6BPI5"},
6257 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG4BPFI5_SSID,
6258 PEG4BPFI5, "PEG4BPFI5"},
6259 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6260 SILICOM_PEG4BPFI5LX_SSID, PEG4BPFI5LX, "PEG4BPFI5LX"},
6261 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXLN_SSID, MEG2BPFILXLN,
6262 "MEG2BPFILXLN"},
6263 {0x8086, 0x105e, SILICOM_SVID, SILICOM_PEG2BPIX1_SSID, PEG2BPIX1,
6264 "PEG2BPIX1-SD"},
6265 {0x8086, 0x105f, SILICOM_SVID, SILICOM_MEG2BPFILXNX_SSID, MEG2BPFILXNX,
6266 "MEG2BPFILXNX"},
6267 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPIT_SSID, XE10G2BPIT,
6268 "XE10G2BPIT"},
6269 {0x8086, PCI_ANY_ID, SILICOM_SVID, SILICOM_XE10G2BPICX4_SSID,
6270 XE10G2BPICX4, "XE10G2BPICX4"},
6271 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPISR_SSID, XE10G2BPISR,
6272 "XE10G2BPISR"},
6273 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_XE10G2BPILR_SSID, XE10G2BPILR,
6274 "XE10G2BPILR"},
6275 {0x8086, 0x10C6, NOKIA_XE10G2BPIXR_SVID, NOKIA_XE10G2BPIXR_SSID,
6276 XE10G2BPIXR, "XE10G2BPIXR"},
6277 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBISR_SSID, PE10GDBISR,
6278 "PE10G2DBISR"},
6279 {0x8086, 0x10C6, SILICOM_SVID, SILICOM_PE10GDBILR_SSID, PE10GDBILR,
6280 "PE10G2DBILR"},
6281 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6282 SILICOM_PEG2BISC6_SSID /*PCI_ANY_ID */ , PEG2BISC6, "PEG2BI5SC6"},
6283 {0x8086, 0x10a7, SILICOM_SVID /*PCI_ANY_ID */ ,
6284 SILICOM_PEG6BPIFC_SSID /*PCI_ANY_ID */ , PEG6BPIFC, "PEG6BPI5FC"},
6285
6286 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6287 SILICOM_PE10G2BPTCX4_SSID, PE10G2BPTCX4, "PE10G2BPTCX4"},
6288 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6289 SILICOM_PE10G2BPTSR_SSID, PE10G2BPTSR, "PE10G2BPTSR"},
6290 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6291 SILICOM_PE10G2BPTLR_SSID, PE10G2BPTLR, "PE10G2BPTLR"},
6292 {BROADCOM_VID, BROADCOM_PE10G2_PID, SILICOM_SVID,
6293 SILICOM_PE10G2BPTT_SSID, PE10G2BPTT, "PE10G2BPTT"},
6294
687bcca0 6295 /* {BROADCOM_VID, BROADCOM_PE10G2_PID, PCI_ANY_ID, PCI_ANY_ID, PE10G2BPTCX4, "PE10G2BPTCX4"}, */
7040e556
D		 6296
6297 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6298 SILICOM_PEG4BPI6_SSID /*PCI_ANY_ID */ , PEG4BPI6, "PEG4BPI6"},
6299 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6300 SILICOM_PEG4BPFI6_SSID /*PCI_ANY_ID */ , PEG4BPFI6, "PEG4BPFI6"},
6301 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6302 SILICOM_PEG4BPFI6LX_SSID /*PCI_ANY_ID */ , PEG4BPFI6LX, "PEG4BPFI6LX"},
6303 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6304 SILICOM_PEG4BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6ZX, "PEG4BPFI6ZX"},
6305 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6306 SILICOM_PEG2BPI6_SSID /*PCI_ANY_ID */ , PEG2BPI6, "PEG2BPI6"},
6307 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6308 SILICOM_PEG2BPFI6_SSID /*PCI_ANY_ID */ , PEG2BPFI6, "PEG2BPFI6"},
6309 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6310 SILICOM_PEG2BPFI6LX_SSID /*PCI_ANY_ID */ , PEG2BPFI6LX, "PEG2BPFI6LX"},
6311 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6312 SILICOM_PEG2BPFI6ZX_SSID /*PCI_ANY_ID */ , PEG2BPFI6ZX, "PEG2BPFI6ZX"},
6313 {0x8086, 0x10e7, SILICOM_SVID /*PCI_ANY_ID */ ,
6314 SILICOM_PEG2BPFI6FLXM_SSID /*PCI_ANY_ID */ , PEG2BPFI6FLXM,
6315 "PEG2BPFI6FLXM"},
6316 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6317 SILICOM_PEG4BPI6FC_SSID /*PCI_ANY_ID */ , PEG4BPI6FC, "PEG4BPI6FC"},
6318 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6319 SILICOM_PEG4BPFI6FC_SSID /*PCI_ANY_ID */ , PEG4BPFI6FC, "PEG4BPFI6FC"},
6320 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6321 SILICOM_PEG4BPFI6FCLX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCLX,
6322 "PEG4BPFI6FCLX"},
6323 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6324 SILICOM_PEG4BPFI6FCZX_SSID /*PCI_ANY_ID */ , PEG4BPFI6FCZX,
6325 "PEG4BPFI6FCZX"},
6326 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6327 SILICOM_PEG6BPI6_SSID /*PCI_ANY_ID */ , PEG6BPI6, "PEG6BPI6"},
6328 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6329 SILICOM_PEG2BPI6SC6_SSID /*PCI_ANY_ID */ , PEG2BPI6SC6,
6330 "PEG6BPI62SC6"},
6331 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6332 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6333 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6334 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6335 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6336 SILICOM_MEG4BPI6_SSID /*PCI_ANY_ID */ , MEG4BPI6, "MEG4BPI6"},
6337
6338 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ , SILICOM_PEG2BPFI5_SSID,
6339 PEG2BPFI5, "PEG2BPFI5"},
6340 {0x8086, 0x10a9, SILICOM_SVID /*PCI_ANY_ID */ ,
6341 SILICOM_PEG2BPFI5LX_SSID, PEG2BPFI5LX, "PEG2BPFI5LX"},
6342
6343 {0x8086, 0x105f, SILICOM_SVID, SILICOM_PXEG4BPFI_SSID, PXEG4BPFI,
6344 "PXEG4BPFI-SD"},
6345
6346 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6347 SILICOM_M1EG2BPI6_SSID /*PCI_ANY_ID */ , M1EG2BPI6, "MxEG2BPI6"},
6348
6349 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6350 SILICOM_M1EG2BPFI6_SSID /*PCI_ANY_ID */ , M1EG2BPFI6, "MxEG2BPFI6"},
6351 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6352 SILICOM_M1EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6LX,
6353 "MxEG2BPFI6LX"},
6354 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6355 SILICOM_M1EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG2BPFI6ZX,
6356 "MxEG2BPFI6ZX"},
6357
6358 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6359 SILICOM_M1EG4BPI6_SSID /*PCI_ANY_ID */ , M1EG4BPI6, "MxEG4BPI6"},
6360
6361 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6362 SILICOM_M1EG4BPFI6_SSID /*PCI_ANY_ID */ , M1EG4BPFI6, "MxEG4BPFI6"},
6363 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6364 SILICOM_M1EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6LX,
6365 "MxEG4BPFI6LX"},
6366 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6367 SILICOM_M1EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M1EG4BPFI6ZX,
6368 "MxEG4BPFI6ZX"},
6369
6370 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6371 SILICOM_M1EG6BPI6_SSID /*PCI_ANY_ID */ , M1EG6BPI6, "MxEG6BPI6"},
6372
6373 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6374 SILICOM_M1E2G4BPi80_SSID /*PCI_ANY_ID */ , M1E2G4BPi80, "MxE2G4BPi80"},
6375 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6376 SILICOM_M1E2G4BPFi80_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80,
6377 "MxE2G4BPFi80"},
6378 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6379 SILICOM_M1E2G4BPFi80LX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80LX,
6380 "MxE2G4BPFi80LX"},
6381 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6382 SILICOM_M1E2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , M1E2G4BPFi80ZX,
6383 "MxE2G4BPFi80ZX"},
6384
6385 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6386 SILICOM_M2EG2BPFI6_SSID /*PCI_ANY_ID */ , M2EG2BPFI6, "M2EG2BPFI6"},
6387 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6388 SILICOM_M2EG2BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6LX,
6389 "M2EG2BPFI6LX"},
6390 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6391 SILICOM_M2EG2BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG2BPFI6ZX,
6392 "M2EG2BPFI6ZX"},
6393
6394 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6395 SILICOM_M2EG4BPI6_SSID /*PCI_ANY_ID */ , M2EG4BPI6, "M2EG4BPI6"},
6396
6397 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6398 SILICOM_M2EG4BPFI6_SSID /*PCI_ANY_ID */ , M2EG4BPFI6, "M2EG4BPFI6"},
6399 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6400 SILICOM_M2EG4BPFI6LX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6LX,
6401 "M2EG4BPFI6LX"},
6402 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6403 SILICOM_M2EG4BPFI6ZX_SSID /*PCI_ANY_ID */ , M2EG4BPFI6ZX,
6404 "M2EG4BPFI6ZX"},
6405
6406 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6407 SILICOM_M2EG6BPI6_SSID /*PCI_ANY_ID */ , M2EG6BPI6, "M2EG6BPI6"},
6408
6409 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6410 SILICOM_PEG2DBI6_SSID /*PCI_ANY_ID */ , PEG2DBI6, "PEG2DBI6"},
6411 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6412 SILICOM_PEG2DBFI6_SSID /*PCI_ANY_ID */ , PEG2DBFI6, "PEG2DBFI6"},
6413 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6414 SILICOM_PEG2DBFI6LX_SSID /*PCI_ANY_ID */ , PEG2DBFI6LX, "PEG2DBFI6LX"},
6415 {0x8086, 0x10e6, SILICOM_SVID /*PCI_ANY_ID */ ,
6416 SILICOM_PEG2DBFI6ZX_SSID /*PCI_ANY_ID */ , PEG2DBFI6ZX, "PEG2DBFI6ZX"},
6417
6418 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6419 SILICOM_PE210G2DBi9SR_SSID, PE210G2DBi9SR, "PE210G2DBi9SR"},
7040e556
D		 6420 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6421 SILICOM_PE210G2DBi9LR_SSID, PE210G2DBi9LR, "PE210G2DBi9LR"},
7040e556
D		 6422 {0x8086, 0x10F9, SILICOM_SVID /*PCI_ANY_ID */ ,
6423 SILICOM_PE310G4DBi940SR_SSID, PE310G4DBi940SR, "PE310G4DBi9SR"},
6424
6425 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6426 SILICOM_PE310G4BPi9T_SSID, PE310G4BPi9T, "PE310G4BPi9T"},
6427 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6428 SILICOM_PE310G4BPi9SR_SSID, PE310G4BPi9SR, "PE310G4BPi9SR"},
6429 {0x8086, 0x10Fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6430 SILICOM_PE310G4BPi9LR_SSID, PE310G4BPi9LR, "PE310G4BPi9LR"},
6431
6432 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6433 SILICOM_PE2G4BPi80_SSID /*PCI_ANY_ID */ , PE2G4BPi80, "PE2G4BPi80"},
6434 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6435 SILICOM_PE2G4BPFi80_SSID /*PCI_ANY_ID */ , PE2G4BPFi80, "PE2G4BPFi80"},
6436 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6437 SILICOM_PE2G4BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80LX,
6438 "PE2G4BPFi80LX"},
6439 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6440 SILICOM_PE2G4BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi80ZX,
6441 "PE2G4BPFi80ZX"},
6442
6443 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6444 SILICOM_PE2G4BPi80L_SSID /*PCI_ANY_ID */ , PE2G4BPi80L, "PE2G4BPi80L"},
6445
6446 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6447 SILICOM_M6E2G8BPi80A_SSID /*PCI_ANY_ID */ , M6E2G8BPi80A,
6448 "MxE2G8BPi80A"},
6449
6450 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6451 SILICOM_PE2G2BPi35_SSID /*PCI_ANY_ID */ , PE2G2BPi35, "PE2G2BPi35"},
6452 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6453 SILICOM_PAC1200BPi35_SSID /*PCI_ANY_ID */ , PAC1200BPi35,
6454 "PAC1200BPi35"},
6455
6456 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6457 SILICOM_PE2G2BPFi35_SSID /*PCI_ANY_ID */ , PE2G2BPFi35, "PE2G2BPFi35"},
6458 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6459 SILICOM_PE2G2BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35LX,
6460 "PE2G2BPFi35LX"},
6461 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6462 SILICOM_PE2G2BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi35ZX,
6463 "PE2G2BPFi35ZX"},
6464
6465 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6466 SILICOM_PE2G4BPi35_SSID /*PCI_ANY_ID */ , PE2G4BPi35, "PE2G4BPi35"},
6467
6468 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6469 SILICOM_PE2G4BPi35L_SSID /*PCI_ANY_ID */ , PE2G4BPi35L, "PE2G4BPi35L"},
6470
6471 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6472 SILICOM_PE2G4BPFi35_SSID /*PCI_ANY_ID */ , PE2G4BPFi35, "PE2G4BPFi35"},
6473 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6474 SILICOM_PE2G4BPFi35LX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35LX,
6475 "PE2G4BPFi35LX"},
6476 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6477 SILICOM_PE2G4BPFi35ZX_SSID /*PCI_ANY_ID */ , PE2G4BPFi35ZX,
6478 "PE2G4BPFi35ZX"},
6479
6480 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6481 SILICOM_PE2G6BPi35_SSID /*PCI_ANY_ID */ , PE2G6BPi35, "PE2G6BPi35"},
6482
7040e556
D		 6483
6484 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa0, PE2G6BPi35CX,
6485 "PE2G6BPi35CX"},
6486 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa1, PE2G6BPi35CX,
6487 "PE2G6BPi35CX"},
6488 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa2, PE2G6BPi35CX,
6489 "PE2G6BPi35CX"},
6490 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa3, PE2G6BPi35CX,
6491 "PE2G6BPi35CX"},
6492 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa4, PE2G6BPi35CX,
6493 "PE2G6BPi35CX"},
6494 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa5, PE2G6BPi35CX,
6495 "PE2G6BPi35CX"},
6496 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa6, PE2G6BPi35CX,
6497 "PE2G6BPi35CX"},
6498 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa7, PE2G6BPi35CX,
6499 "PE2G6BPi35CX"},
6500 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa8, PE2G6BPi35CX,
6501 "PE2G6BPi35CX"},
6502 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaa9, PE2G6BPi35CX,
6503 "PE2G6BPi35CX"},
6504 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaa, PE2G6BPi35CX,
6505 "PE2G6BPi35CX"},
6506 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaab, PE2G6BPi35CX,
6507 "PE2G6BPi35CX"},
6508 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaac, PE2G6BPi35CX,
6509 "PE2G6BPi35CX"},
6510 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaad, PE2G6BPi35CX,
6511 "PE2G6BPi35CX"},
6512 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaae, PE2G6BPi35CX,
6513 "PE2G6BPi35CX"},
6514 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaaf, PE2G6BPi35CX,
6515 "PE2G6BPi35CX"},
6516 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab0, PE2G6BPi35CX,
6517 "PE2G6BPi35CX"},
6518 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab1, PE2G6BPi35CX,
6519 "PE2G6BPi35CX"},
6520 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab2, PE2G6BPi35CX,
6521 "PE2G6BPi35CX"},
6522 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab3, PE2G6BPi35CX,
6523 "PE2G6BPi35CX"},
6524 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab4, PE2G6BPi35CX,
6525 "PE2G6BPi35CX"},
6526 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab5, PE2G6BPi35CX,
6527 "PE2G6BPi35CX"},
6528 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab6, PE2G6BPi35CX,
6529 "PE2G6BPi35CX"},
6530 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab7, PE2G6BPi35CX,
6531 "PE2G6BPi35CX"},
6532 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab8, PE2G6BPi35CX,
6533 "PE2G6BPi35CX"},
6534 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xab9, PE2G6BPi35CX,
6535 "PE2G6BPi35CX"},
6536 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xaba, PE2G6BPi35CX,
6537 "PE2G6BPi35CX"},
6538 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabb, PE2G6BPi35CX,
6539 "PE2G6BPi35CX"},
6540 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabc, PE2G6BPi35CX,
6541 "PE2G6BPi35CX"},
6542 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabd, PE2G6BPi35CX,
6543 "PE2G6BPi35CX"},
6544 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabe, PE2G6BPi35CX,
6545 "PE2G6BPi35CX"},
6546 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ , 0xabf, PE2G6BPi35CX,
6547 "PE2G6BPi35CX"},
6548
6549 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6550 SILICOM_PE2G2BPi80_SSID /*PCI_ANY_ID */ , PE2G2BPi80, "PE2G2BPi80"},
6551 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6552 SILICOM_PE2G2BPFi80_SSID /*PCI_ANY_ID */ , PE2G2BPFi80, "PE2G2BPFi80"},
6553 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6554 SILICOM_PE2G2BPFi80LX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80LX,
6555 "PE2G2BPFi80LX"},
6556 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6557 SILICOM_PE2G2BPFi80ZX_SSID /*PCI_ANY_ID */ , PE2G2BPFi80ZX,
6558 "PE2G2BPFi80ZX"},
6559
6560 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6561 SILICOM_MEG2BPI6_SSID /*PCI_ANY_ID */ , MEG2BPI6, "MEG2BPI6"},
6562 {0x8086, 0x10c9, SILICOM_SVID /*PCI_ANY_ID */ ,
6563 SILICOM_XEG2BPI6_SSID /*PCI_ANY_ID */ , XEG2BPI6, "XEG2BPI6"},
6564
6565#if 0
6566 {0x8086, 0x10fb, 0x8086, INTEL_PE210G2SPI9_SSID, PE210G2SPI9,
6567 "PE210G2SPI9"},
6568#endif
6569 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6570 SILICOM_M1E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M1E10G2BPI9CX4,
6571 "MxE210G2BPI9CX4"},
6572 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6573 SILICOM_M1E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9SR,
6574 "MxE210G2BPI9SR"},
6575 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6576 SILICOM_M1E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M1E10G2BPI9LR,
6577 "MxE210G2BPI9LR"},
6578 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6579 SILICOM_M1E10G2BPI9T_SSID /*PCI_ANY_ID */ , M1E10G2BPI9T,
6580 "MxE210G2BPI9T"},
6581
6582 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6583 SILICOM_M2E10G2BPI9CX4_SSID /*PCI_ANY_ID */ , M2E10G2BPI9CX4,
6584 "M2E10G2BPI9CX4"},
6585 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6586 SILICOM_M2E10G2BPI9SR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9SR,
6587 "M2E10G2BPI9SR"},
6588 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6589 SILICOM_M2E10G2BPI9LR_SSID /*PCI_ANY_ID */ , M2E10G2BPI9LR,
6590 "M2E10G2BPI9LR"},
6591 {0x8086, 0x10fb, SILICOM_SVID /*PCI_ANY_ID */ ,
6592 SILICOM_M2E10G2BPI9T_SSID /*PCI_ANY_ID */ , M2E10G2BPI9T,
6593 "M2E10G2BPI9T"},
6594
6595 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9CX4_SSID,
6596 PE210G2BPI9CX4, "PE210G2BPI9CX4"},
6597 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9SR_SSID,
6598 PE210G2BPI9SR, "PE210G2BPI9SR"},
6599 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9LR_SSID,
6600 PE210G2BPI9LR, "PE210G2BPI9LR"},
6601 {0x8086, 0x10fb, SILICOM_SVID, SILICOM_PE210G2BPI9T_SSID, PE210G2BPI9T,
6602 "PE210G2BPI9T"},
6603
6604#if 0
6605 {0x1374, 0x2c, SILICOM_SVID, SILICOM_PXG4BPI_SSID, PXG4BPI,
6606 "PXG4BPI-SD"},
6607
6608 {0x1374, 0x2d, SILICOM_SVID, SILICOM_PXG4BPFI_SSID, PXG4BPFI,
6609 "PXG4BPFI-SD"},
6610
6611 {0x1374, 0x3f, SILICOM_SVID, SILICOM_PXG2TBI_SSID, PXG2TBI,
6612 "PXG2TBI-SD"},
6613
6614 {0x1374, 0x3d, SILICOM_SVID, SILICOM_PXG2BISC1_SSID, PXG2BISC1,
6615 "PXG2BISC1-SD"},
6616
6617 {0x1374, 0x40, SILICOM_SVID, SILICOM_PEG4BPFI_SSID, PEG4BPFI,
6618 "PEG4BPFI-SD"},
6619
6620#ifdef BP_SELF_TEST
6621 {0x1374, 0x28, SILICOM_SVID, 0x28, PXGBPI, "PXG2BPI-SD"},
6622#endif
6623#endif
6624 {0x8086, PCI_ANY_ID, SILICOM_SVID /*PCI_ANY_ID */ ,
6625 SILICOM_M6E2G8BPi80_SSID /*PCI_ANY_ID */ , M6E2G8BPi80, "MxE2G8BPi80"},
6626 {0x8086, 0x1528, SILICOM_SVID /*PCI_ANY_ID */ ,
6627 SILICOM_PE210G2BPi40_SSID /*PCI_ANY_ID */ , PE210G2BPi40,
6628 "PE210G2BPi40T"},
6629
6630 /* required last entry */
6631 {0,}
6632};
6633
bdcecec3
AV		 6634static void find_fw(bpctl_dev_t *dev)
6635{
6636 unsigned long mmio_start, mmio_len;
6637 struct pci_dev *pdev1 = dev->pdev;
6638
6639 if ((OLD_IF_SERIES(dev->subdevice)) ||
6640 (INTEL_IF_SERIES(dev->subdevice)))
6641 dev->bp_fw_ver = 0xff;
6642 else
6643 dev->bp_fw_ver = bypass_fw_ver(dev);
6644
6645 if (dev->bp_10gb == 1 && dev->bp_fw_ver == 0xff) {
6646 int cnt = 100;
6647 while (cnt--) {
6648 iounmap((void *)dev->mem_map);
6649 mmio_start = pci_resource_start(pdev1, 0);
6650 mmio_len = pci_resource_len(pdev1, 0);
6651
6652 dev->mem_map = (unsigned long)
6653 ioremap(mmio_start, mmio_len);
6654
6655 dev->bp_fw_ver = bypass_fw_ver(dev);
6656 if (dev-> bp_fw_ver == 0xa8)
6657 break;
6658 }
6659 }
6660 /* dev->bp_fw_ver=0xa8; */
6661 printk("firmware version: 0x%x\n", dev->bp_fw_ver);
6662}
6663
6664static int init_one(bpctl_dev_t *dev, bpmod_info_t *info, struct pci_dev *pdev1)
6665{
6666 unsigned long mmio_start, mmio_len;
6667
6668 dev->pdev = pdev1;
6669 mmio_start = pci_resource_start(pdev1, 0);
6670 mmio_len = pci_resource_len(pdev1, 0);
6671
6672 dev->desc = dev_desc[info->index].name;
6673 dev->name = info->bp_name;
6674 dev->device = info->device;
6675 dev->vendor = info->vendor;
6676 dev->subdevice = info->subdevice;
6677 dev->subvendor = info->subvendor;
6678 dev->func = PCI_FUNC(pdev1->devfn);
6679 dev->slot = PCI_SLOT(pdev1->devfn);
6680 dev->bus = pdev1->bus->number;
6681 dev->mem_map = (unsigned long)ioremap(mmio_start, mmio_len);
6682#ifdef BP_SYNC_FLAG
6683 spin_lock_init(&dev->bypass_wr_lock);
6684#endif
6685 if (BP10G9_IF_SERIES(dev->subdevice))
6686 dev->bp_10g9 = 1;
6687 if (BP10G_IF_SERIES(dev->subdevice))
6688 dev->bp_10g = 1;
6689 if (PEG540_IF_SERIES(dev->subdevice))
6690 dev->bp_540 = 1;
6691 if (PEGF5_IF_SERIES(dev->subdevice))
6692 dev->bp_fiber5 = 1;
6693 if (PEG80_IF_SERIES(dev->subdevice))
6694 dev->bp_i80 = 1;
6695 if (PEGF80_IF_SERIES(dev->subdevice))
6696 dev->bp_i80 = 1;
6697 if ((dev->subdevice & 0xa00) == 0xa00)
6698 dev->bp_i80 = 1;
6699 if (BP10GB_IF_SERIES(dev->subdevice)) {
6700 if (dev->ifindex == 0) {
6701 unregister_chrdev(major_num, DEVICE_NAME);
6702 printk("Please load network driver for %s adapter!\n",
6703 dev->name);
6704 return -1;
6705 }
6706
6707 if (dev->ndev && !(dev->ndev->flags & IFF_UP)) {
6708 unregister_chrdev(major_num, DEVICE_NAME);
6709 printk("Please bring up network interfaces for %s adapter!\n",
6710 dev->name);
6711 return -1;
6712 }
6713 dev->bp_10gb = 1;
6714 }
6715
6716 if (!dev->bp_10g9) {
6717 if (is_bypass_fn(dev)) {
6718 printk(KERN_INFO "%s found, ",
6719 dev->name);
6720 find_fw(dev);
6721 }
6722 dev->wdt_status = WDT_STATUS_UNKNOWN;
6723 dev->reset_time = 0;
6724 atomic_set(&dev->wdt_busy, 0);
6725 dev->bp_status_un = 1;
6726
6727 bypass_caps_init(dev);
6728
6729 init_bypass_wd_auto(dev);
6730 init_bypass_tpl_auto(dev);
6731 if (NOKIA_SERIES(dev->subdevice))
6732 reset_cont(dev);
6733 }
6734#ifdef BP_SELF_TEST
6735 if ((dev->bp_tx_data = kzalloc(BPTEST_DATA_LEN, GFP_KERNEL))) {
6736 memset(dev->bp_tx_data, 0xff, 6);
6737 memset(dev->bp_tx_data + 6, 0x0, 1);
6738 memset(dev->bp_tx_data + 7, 0xaa, 5);
6739 *(__be16 *)(dev->bp_tx_data + 12) = htons(ETH_P_BPTEST);
6740 } else
6741 printk("bp_ctl: Memory allocation error!\n");
6742#endif
6743 return 0;
6744}
6745
7040e556
D		 6746/*
6747* Initialize the module - Register the character device
6748*/
6749
6750static int __init bypass_init_module(void)
6751{
6752 int ret_val, idx, idx_dev = 0;
6753 struct pci_dev *pdev1 = NULL;
bdcecec3 6754 bpctl_dev_t *dev;
7040e556
D		 6755
6756 printk(BP_MOD_DESCR " v" BP_MOD_VER "\n");
6757 ret_val = register_chrdev(major_num, DEVICE_NAME, &Fops);
6758 if (ret_val < 0) {
6759 printk("%s failed with %d\n", DEVICE_NAME, ret_val);
6760 return ret_val;
6761 }
6762 major_num = ret_val; /* dynamic */
6763 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6764 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6765 tx_ctl_pci_tbl[idx].device,
6766 tx_ctl_pci_tbl[idx].subvendor,
6767 tx_ctl_pci_tbl[idx].subdevice,
6768 pdev1))) {
6769
6770 device_num++;
6771 }
6772 }
6773 if (!device_num) {
6774 printk("No such device\n");
6775 unregister_chrdev(major_num, DEVICE_NAME);
6776 return -1;
6777 }
6778
6779 bpctl_dev_arr = kmalloc((device_num) * sizeof(bpctl_dev_t), GFP_KERNEL);
6780
6781 if (!bpctl_dev_arr) {
6782 printk("Allocation error\n");
6783 unregister_chrdev(major_num, DEVICE_NAME);
6784 return -1;
6785 }
6786 memset(bpctl_dev_arr, 0, ((device_num) * sizeof(bpctl_dev_t)));
6787
6788 pdev1 = NULL;
bdcecec3 6789 dev = bpctl_dev_arr;
7040e556
D		 6790 for (idx = 0; tx_ctl_pci_tbl[idx].vendor; idx++) {
6791 while ((pdev1 = pci_get_subsys(tx_ctl_pci_tbl[idx].vendor,
6792 tx_ctl_pci_tbl[idx].device,
6793 tx_ctl_pci_tbl[idx].subvendor,
6794 tx_ctl_pci_tbl[idx].subdevice,
6795 pdev1))) {
bdcecec3
AV		 6796 if (init_one(dev, &tx_ctl_pci_tbl[idx], pdev1) < 0)
6797 return -1;
6798 dev++;
7040e556
D		 6799 }
6800 }
6801 if_scan_init();
6802
6803 sema_init(&bpctl_sema, 1);
6804 spin_lock_init(&bpvm_lock);
6805 {
6806
6807 bpctl_dev_t *pbpctl_dev_c = NULL;
bdcecec3
AV		 6808 for (idx_dev = 0, dev = bpctl_dev_arr;
6809 idx_dev < device_num && dev->pdev;
6810 idx_dev++, dev++) {
6811 if (dev->bp_10g9) {
6812 pbpctl_dev_c = get_status_port_fn(dev);
6813 if (is_bypass_fn(dev)) {
7040e556 6814 printk(KERN_INFO "%s found, ",
bdcecec3
AV		 6815 dev->name);
6816 dev->bp_fw_ver = bypass_fw_ver(dev);
7040e556 6817 printk("firmware version: 0x%x\n",
bdcecec3 6818 dev->bp_fw_ver);
7040e556 6819 }
bdcecec3
AV		 6820 dev->wdt_status = WDT_STATUS_UNKNOWN;
6821 dev->reset_time = 0;
6822 atomic_set(&dev->wdt_busy, 0);
6823 dev->bp_status_un = 1;
7040e556 6824
bdcecec3 6825 bypass_caps_init(dev);
7040e556 6826
bdcecec3
AV		 6827 init_bypass_wd_auto(dev);
6828 init_bypass_tpl_auto(dev);
7040e556
D		 6829
6830 }
6831
6832 }
6833 }
6834
7040e556
D		 6835 register_netdevice_notifier(&bp_notifier_block);
6836#ifdef BP_PROC_SUPPORT
6837 {
6838 int i = 0;
687bcca0
DC		 6839 /* unsigned long flags; */
6840 /* rcu_read_lock(); */
7040e556
D		 6841 bp_proc_create();
6842 for (i = 0; i < device_num; i++) {
6843 if (bpctl_dev_arr[i].ifindex) {
687bcca0 6844 /* spin_lock_irqsave(&bpvm_lock, flags); */
7040e556
D		 6845 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
6846 bypass_proc_create_dev_sd(&bpctl_dev_arr[i]);
687bcca0 6847 /* spin_unlock_irqrestore(&bpvm_lock, flags); */
7040e556
D		 6848 }
6849
6850 }
687bcca0 6851 /* rcu_read_unlock(); */
7040e556
D		 6852 }
6853#endif
6854
7040e556
D		 6855 return 0;
6856}
6857
6858/*
6859* Cleanup - unregister the appropriate file from /proc
6860*/
6861static void __exit bypass_cleanup_module(void)
6862{
6863 int i;
7040e556
D		 6864 unregister_netdevice_notifier(&bp_notifier_block);
6865
7040e556 6866 for (i = 0; i < device_num; i++) {
687bcca0 6867 /* unsigned long flags; */
7040e556 6868#ifdef BP_PROC_SUPPORT
687bcca0
DC		 6869/* spin_lock_irqsave(&bpvm_lock, flags);
6870 rcu_read_lock(); */
7040e556 6871 bypass_proc_remove_dev_sd(&bpctl_dev_arr[i]);
687bcca0
DC		 6872/* spin_unlock_irqrestore(&bpvm_lock, flags);
6873 rcu_read_unlock(); */
7040e556
D		 6874#endif
6875 remove_bypass_wd_auto(&bpctl_dev_arr[i]);
6876 bpctl_dev_arr[i].reset_time = 0;
6877
6878 remove_bypass_tpl_auto(&bpctl_dev_arr[i]);
6879 }
6880
6881 /* unmap all devices */
6882 for (i = 0; i < device_num; i++) {
6883#ifdef BP_SELF_TEST
6884 if (bpctl_dev_arr[i].bp_tx_data)
6885 kfree(bpctl_dev_arr[i].bp_tx_data);
6886#endif
6887 iounmap((void *)(bpctl_dev_arr[i].mem_map));
6888 }
6889
6890 /* free all devices space */
6891 if (bpctl_dev_arr)
6892 kfree(bpctl_dev_arr);
6893
6894/*
6895* Unregister the device
6896*/
7040e556 6897 unregister_chrdev(major_num, DEVICE_NAME);
7040e556
D		 6898}
6899
6900module_init(bypass_init_module);
6901module_exit(bypass_cleanup_module);
6902
6903int is_bypass_sd(int ifindex)
6904{
7935c80c 6905 return is_bypass(get_dev_idx_p(ifindex));
7040e556
D		 6906}
6907
6908int set_bypass_sd(int ifindex, int bypass_mode)
6909{
6910
7935c80c 6911 return set_bypass_fn(get_dev_idx_p(ifindex), bypass_mode);
7040e556
D		 6912}
6913
6914int get_bypass_sd(int ifindex)
6915{
6916
7935c80c 6917 return get_bypass_fn(get_dev_idx_p(ifindex));
7040e556
D		 6918}
6919
6920int get_bypass_change_sd(int ifindex)
6921{
6922
7935c80c 6923 return get_bypass_change_fn(get_dev_idx_p(ifindex));
7040e556
D		 6924}
6925
6926int set_dis_bypass_sd(int ifindex, int dis_param)
6927{
7935c80c 6928 return set_dis_bypass_fn(get_dev_idx_p(ifindex), dis_param);
7040e556
D		 6929}
6930
6931int get_dis_bypass_sd(int ifindex)
6932{
6933
7935c80c 6934 return get_dis_bypass_fn(get_dev_idx_p(ifindex));
7040e556
D		 6935}
6936
6937int set_bypass_pwoff_sd(int ifindex, int bypass_mode)
6938{
7935c80c 6939 return set_bypass_pwoff_fn(get_dev_idx_p(ifindex), bypass_mode);
7040e556
D		 6940
6941}
6942
6943int get_bypass_pwoff_sd(int ifindex)
6944{
7935c80c 6945 return get_bypass_pwoff_fn(get_dev_idx_p(ifindex));
7040e556
D		 6946
6947}
6948
6949int set_bypass_pwup_sd(int ifindex, int bypass_mode)
6950{
7935c80c 6951 return set_bypass_pwup_fn(get_dev_idx_p(ifindex), bypass_mode);
7040e556
D		 6952
6953}
6954
6955int get_bypass_pwup_sd(int ifindex)
6956{
7935c80c 6957 return get_bypass_pwup_fn(get_dev_idx_p(ifindex));
7040e556
D		 6958
6959}
6960
6961int set_bypass_wd_sd(int if_index, int ms_timeout, int *ms_timeout_set)
6962{
6963 if ((is_bypass(get_dev_idx_p(if_index))) <= 0)
6964 return BP_NOT_CAP;
6965 *ms_timeout_set = set_bypass_wd_fn(get_dev_idx_p(if_index), ms_timeout);
6966 return 0;
6967}
6968
6969int get_bypass_wd_sd(int ifindex, int *timeout)
6970{
7935c80c 6971 return get_bypass_wd_fn(get_dev_idx_p(ifindex), timeout);
7040e556
D		 6972
6973}
6974
6975int get_wd_expire_time_sd(int ifindex, int *time_left)
6976{
7935c80c 6977 return get_wd_expire_time_fn(get_dev_idx_p(ifindex), time_left);
7040e556
D		 6978}
6979
6980int reset_bypass_wd_timer_sd(int ifindex)
6981{
7935c80c 6982 return reset_bypass_wd_timer_fn(get_dev_idx_p(ifindex));
7040e556
D		 6983
6984}
6985
6986int get_wd_set_caps_sd(int ifindex)
6987{
7935c80c 6988 return get_wd_set_caps_fn(get_dev_idx_p(ifindex));
7040e556
D		 6989
6990}
6991
6992int set_std_nic_sd(int ifindex, int nic_mode)
6993{
7935c80c 6994 return set_std_nic_fn(get_dev_idx_p(ifindex), nic_mode);
7040e556
D		 6995
6996}
6997
6998int get_std_nic_sd(int ifindex)
6999{
7935c80c 7000 return get_std_nic_fn(get_dev_idx_p(ifindex));
7040e556
D		 7001
7002}
7003
7004int set_tap_sd(int ifindex, int tap_mode)
7005{
7935c80c 7006 return set_tap_fn(get_dev_idx_p(ifindex), tap_mode);
7040e556
D		 7007
7008}
7009
7010int get_tap_sd(int ifindex)
7011{
7935c80c 7012 return get_tap_fn(get_dev_idx_p(ifindex));
7040e556
D		 7013
7014}
7015
7016int set_tap_pwup_sd(int ifindex, int tap_mode)
7017{
7935c80c 7018 return set_tap_pwup_fn(get_dev_idx_p(ifindex), tap_mode);
7040e556
D		 7019
7020}
7021
7022int get_tap_pwup_sd(int ifindex)
7023{
7935c80c 7024 return get_tap_pwup_fn(get_dev_idx_p(ifindex));
7040e556
D		 7025
7026}
7027
7028int get_tap_change_sd(int ifindex)
7029{
7935c80c 7030 return get_tap_change_fn(get_dev_idx_p(ifindex));
7040e556
D		 7031
7032}
7033
7034int set_dis_tap_sd(int ifindex, int dis_param)
7035{
7935c80c 7036 return set_dis_tap_fn(get_dev_idx_p(ifindex), dis_param);
7040e556
D		 7037
7038}
7039
7040int get_dis_tap_sd(int ifindex)
7041{
7935c80c 7042 return get_dis_tap_fn(get_dev_idx_p(ifindex));
7040e556
D		 7043
7044}
7045
7046int set_bp_disc_sd(int ifindex, int disc_mode)
7047{
7935c80c 7048 return set_disc_fn(get_dev_idx_p(ifindex), disc_mode);
7040e556
D		 7049
7050}
7051
7052int get_bp_disc_sd(int ifindex)
7053{
7935c80c 7054 return get_disc_fn(get_dev_idx_p(ifindex));
7040e556
D		 7055
7056}
7057
7058int set_bp_disc_pwup_sd(int ifindex, int disc_mode)
7059{
7935c80c 7060 return set_disc_pwup_fn(get_dev_idx_p(ifindex), disc_mode);
7040e556
D		 7061
7062}
7063
7064int get_bp_disc_pwup_sd(int ifindex)
7065{
7935c80c 7066 return get_disc_pwup_fn(get_dev_idx_p(ifindex));
7040e556
D		 7067
7068}
7069
7070int get_bp_disc_change_sd(int ifindex)
7071{
7935c80c 7072 return get_disc_change_fn(get_dev_idx_p(ifindex));
7040e556
D		 7073
7074}
7075
7076int set_bp_dis_disc_sd(int ifindex, int dis_param)
7077{
7935c80c 7078 return set_dis_disc_fn(get_dev_idx_p(ifindex), dis_param);
7040e556
D		 7079
7080}
7081
7082int get_bp_dis_disc_sd(int ifindex)
7083{
7935c80c 7084 return get_dis_disc_fn(get_dev_idx_p(ifindex));
7040e556
D		 7085
7086}
7087
7088int get_wd_exp_mode_sd(int ifindex)
7089{
7935c80c 7090 return get_wd_exp_mode_fn(get_dev_idx_p(ifindex));
7040e556
D		 7091}
7092
7093int set_wd_exp_mode_sd(int ifindex, int param)
7094{
7935c80c 7095 return set_wd_exp_mode_fn(get_dev_idx_p(ifindex), param);
7040e556
D		 7096
7097}
7098
7099int reset_cont_sd(int ifindex)
7100{
7935c80c 7101 return reset_cont_fn(get_dev_idx_p(ifindex));
7040e556
D		 7102
7103}
7104
7105int set_tx_sd(int ifindex, int tx_state)
7106{
7935c80c 7107 return set_tx_fn(get_dev_idx_p(ifindex), tx_state);
7040e556
D		 7108
7109}
7110
7111int set_tpl_sd(int ifindex, int tpl_state)
7112{
7935c80c 7113 return set_tpl_fn(get_dev_idx_p(ifindex), tpl_state);
7040e556
D		 7114
7115}
7116
7117int set_bp_hw_reset_sd(int ifindex, int status)
7118{
7935c80c 7119 return set_bp_hw_reset_fn(get_dev_idx_p(ifindex), status);
7040e556
D		 7120
7121}
7122
7123int set_wd_autoreset_sd(int ifindex, int param)
7124{
7935c80c 7125 return set_wd_autoreset_fn(get_dev_idx_p(ifindex), param);
7040e556
D		 7126
7127}
7128
7129int get_wd_autoreset_sd(int ifindex)
7130{
7935c80c 7131 return get_wd_autoreset_fn(get_dev_idx_p(ifindex));
7040e556
D		 7132
7133}
7134
7135int get_bypass_caps_sd(int ifindex)
7136{
7935c80c 7137 return get_bypass_caps_fn(get_dev_idx_p(ifindex));
7040e556
D		 7138}
7139
7140int get_bypass_slave_sd(int ifindex)
7141{
7142 bpctl_dev_t *pbpctl_dev_out;
7143 int ret = get_bypass_slave_fn(get_dev_idx_p(ifindex), &pbpctl_dev_out);
7144 if (ret == 1)
7935c80c 7145 return pbpctl_dev_out->ifindex;
7040e556
D		 7146 return -1;
7147
7148}
7149
7150int get_tx_sd(int ifindex)
7151{
7935c80c 7152 return get_tx_fn(get_dev_idx_p(ifindex));
7040e556
D		 7153
7154}
7155
7156int get_tpl_sd(int ifindex)
7157{
7935c80c 7158 return get_tpl_fn(get_dev_idx_p(ifindex));
7040e556
D		 7159
7160}
7161
7162int get_bp_hw_reset_sd(int ifindex)
7163{
7935c80c 7164 return get_bp_hw_reset_fn(get_dev_idx_p(ifindex));
7040e556
D		 7165
7166}
7167
7168int get_bypass_info_sd(int ifindex, struct bp_info *bp_info)
7169{
7935c80c 7170 return get_bypass_info_fn(get_dev_idx_p(ifindex), bp_info->prod_name, &bp_info->fw_ver);
7040e556
D		 7171}
7172
7173int bp_if_scan_sd(void)
7174{
7175 if_scan_init();
7176 return 0;
7177}
7178
7179EXPORT_SYMBOL_NOVERS(is_bypass_sd);
7180EXPORT_SYMBOL_NOVERS(get_bypass_slave_sd);
7181EXPORT_SYMBOL_NOVERS(get_bypass_caps_sd);
7182EXPORT_SYMBOL_NOVERS(get_wd_set_caps_sd);
7183EXPORT_SYMBOL_NOVERS(set_bypass_sd);
7184EXPORT_SYMBOL_NOVERS(get_bypass_sd);
7185EXPORT_SYMBOL_NOVERS(get_bypass_change_sd);
7186EXPORT_SYMBOL_NOVERS(set_dis_bypass_sd);
7187EXPORT_SYMBOL_NOVERS(get_dis_bypass_sd);
7188EXPORT_SYMBOL_NOVERS(set_bypass_pwoff_sd);
7189EXPORT_SYMBOL_NOVERS(get_bypass_pwoff_sd);
7190EXPORT_SYMBOL_NOVERS(set_bypass_pwup_sd);
7191EXPORT_SYMBOL_NOVERS(get_bypass_pwup_sd);
7192EXPORT_SYMBOL_NOVERS(set_bypass_wd_sd);
7193EXPORT_SYMBOL_NOVERS(get_bypass_wd_sd);
7194EXPORT_SYMBOL_NOVERS(get_wd_expire_time_sd);
7195EXPORT_SYMBOL_NOVERS(reset_bypass_wd_timer_sd);
7196EXPORT_SYMBOL_NOVERS(set_std_nic_sd);
7197EXPORT_SYMBOL_NOVERS(get_std_nic_sd);
7198EXPORT_SYMBOL_NOVERS(set_tx_sd);
7199EXPORT_SYMBOL_NOVERS(get_tx_sd);
7200EXPORT_SYMBOL_NOVERS(set_tpl_sd);
7201EXPORT_SYMBOL_NOVERS(get_tpl_sd);
7202EXPORT_SYMBOL_NOVERS(set_bp_hw_reset_sd);
7203EXPORT_SYMBOL_NOVERS(get_bp_hw_reset_sd);
7204EXPORT_SYMBOL_NOVERS(set_tap_sd);
7205EXPORT_SYMBOL_NOVERS(get_tap_sd);
7206EXPORT_SYMBOL_NOVERS(get_tap_change_sd);
7207EXPORT_SYMBOL_NOVERS(set_dis_tap_sd);
7208EXPORT_SYMBOL_NOVERS(get_dis_tap_sd);
7209EXPORT_SYMBOL_NOVERS(set_tap_pwup_sd);
7210EXPORT_SYMBOL_NOVERS(get_tap_pwup_sd);
7211EXPORT_SYMBOL_NOVERS(set_wd_exp_mode_sd);
7212EXPORT_SYMBOL_NOVERS(get_wd_exp_mode_sd);
7213EXPORT_SYMBOL_NOVERS(set_wd_autoreset_sd);
7214EXPORT_SYMBOL_NOVERS(get_wd_autoreset_sd);
7215EXPORT_SYMBOL_NOVERS(set_bp_disc_sd);
7216EXPORT_SYMBOL_NOVERS(get_bp_disc_sd);
7217EXPORT_SYMBOL_NOVERS(get_bp_disc_change_sd);
7218EXPORT_SYMBOL_NOVERS(set_bp_dis_disc_sd);
7219EXPORT_SYMBOL_NOVERS(get_bp_dis_disc_sd);
7220EXPORT_SYMBOL_NOVERS(set_bp_disc_pwup_sd);
7221EXPORT_SYMBOL_NOVERS(get_bp_disc_pwup_sd);
7222EXPORT_SYMBOL_NOVERS(get_bypass_info_sd);
7223EXPORT_SYMBOL_NOVERS(bp_if_scan_sd);
7224
7225#define BP_PROC_DIR "bypass"
7226
7040e556
D		 7227static struct proc_dir_entry *bp_procfs_dir;
7228
7040e556
D		 7229int bp_proc_create(void)
7230{
a01b0c57 7231 bp_procfs_dir = proc_mkdir(BP_PROC_DIR, init_net.proc_net);
7040e556
D		 7232 if (bp_procfs_dir == (struct proc_dir_entry *)0) {
7233 printk(KERN_DEBUG
7234 "Could not create procfs nicinfo directory %s\n",
7235 BP_PROC_DIR);
7236 return -1;
7237 }
7238 return 0;
7239}
7240
a01b0c57
AV		 7241static int procfs_add(char *proc_name, const struct file_operations *fops,
7242 bpctl_dev_t *dev)
7040e556 7243{
a01b0c57
AV		 7244 struct bypass_pfs_sd *pfs = &dev->bypass_pfs_set;
7245 if (!proc_create_data(proc_name, 0644, pfs->bypass_entry, fops, dev))
7040e556 7246 return -1;
7040e556 7247 return 0;
7040e556
D		 7248}
7249
a01b0c57
AV		 7250#define RO_FOPS(name) \
7251static int name##_open(struct inode *inode, struct file *file) \
7252{ \
d9dda78b 7253 return single_open(file, show_##name, PDE_DATA(inode));\
a01b0c57
AV		 7254} \
7255static const struct file_operations name##_ops = { \
7256 .open = name##_open, \
7257 .read = seq_read, \
7258 .llseek = seq_lseek, \
7259 .release = single_release, \
7260};
7040e556 7261
a01b0c57
AV		 7262#define RW_FOPS(name) \
7263static int name##_open(struct inode *inode, struct file *file) \
7264{ \
d9dda78b 7265 return single_open(file, show_##name, PDE_DATA(inode));\
a01b0c57
AV		 7266} \
7267static const struct file_operations name##_ops = { \
7268 .open = name##_open, \
7269 .read = seq_read, \
7270 .write = name##_write, \
7271 .llseek = seq_lseek, \
7272 .release = single_release, \
7273};
7040e556 7274
a01b0c57 7275static int show_bypass_info(struct seq_file *m, void *v)
7040e556 7276{
a01b0c57 7277 bpctl_dev_t *dev = m->private;
7040e556 7278
a01b0c57
AV		 7279 seq_printf(m, "Name\t\t\t%s\n", dev->name);
7280 seq_printf(m, "Firmware version\t0x%x\n", dev->bp_fw_ver);
7281 return 0;
7040e556 7282}
a01b0c57 7283RO_FOPS(bypass_info)
7040e556 7284
a01b0c57 7285static int show_bypass_slave(struct seq_file *m, void *v)
7040e556 7286{
a01b0c57
AV		 7287 bpctl_dev_t *dev = m->private;
7288 bpctl_dev_t *slave = get_status_port_fn(dev);
7289 if (!slave)
7290 slave = dev;
7291 if (!slave)
7292 seq_printf(m, "fail\n");
7293 else if (slave->ndev)
7294 seq_printf(m, "%s\n", slave->ndev->name);
7295 return 0;
7296}
7297RO_FOPS(bypass_slave)
7040e556 7298
a01b0c57
AV		 7299static int show_bypass_caps(struct seq_file *m, void *v)
7300{
7301 bpctl_dev_t *dev = m->private;
7302 int ret = get_bypass_caps_fn(dev);
7040e556 7303 if (ret == BP_NOT_CAP)
a01b0c57 7304 seq_printf(m, "-1\n");
7040e556 7305 else
a01b0c57
AV		 7306 seq_printf(m, "0x%x\n", ret);
7307 return 0;
7040e556 7308}
a01b0c57 7309RO_FOPS(bypass_caps)
7040e556 7310
a01b0c57 7311static int show_wd_set_caps(struct seq_file *m, void *v)
7040e556 7312{
a01b0c57
AV		 7313 bpctl_dev_t *dev = m->private;
7314 int ret = get_wd_set_caps_fn(dev);
7040e556 7315 if (ret == BP_NOT_CAP)
a01b0c57 7316 seq_printf(m, "-1\n");
7040e556 7317 else
a01b0c57
AV		 7318 seq_printf(m, "0x%x\n", ret);
7319 return 0;
7040e556 7320}
a01b0c57 7321RO_FOPS(wd_set_caps)
7040e556 7322
7e1be8a5 7323static int user_on_off(const void __user *buffer, size_t count)
7040e556
D		 7324{
7325
7326 char kbuf[256];
7e1be8a5 7327 int length = 0;
7040e556
D		 7328
7329 if (count > (sizeof(kbuf) - 1))
7330 return -1;
7331
7e1be8a5 7332 if (copy_from_user(&kbuf, buffer, count))
7040e556 7333 return -1;
7040e556
D		 7334
7335 kbuf[count] = '\0';
7336 length = strlen(kbuf);
7337 if (kbuf[length - 1] == '\n')
7338 kbuf[--length] = '\0';
7339
7340 if (strcmp(kbuf, "on") == 0)
7e1be8a5
AV		 7341 return 1;
7342 if (strcmp(kbuf, "off") == 0)
7343 return 0;
7344 return 0;
7345}
7040e556 7346
a01b0c57
AV		 7347static ssize_t bypass_write(struct file *file, const char __user *buffer,
7348 size_t count, loff_t *pos)
7e1be8a5 7349{
7e1be8a5
AV		 7350 int bypass_param = user_on_off(buffer, count);
7351 if (bypass_param < 0)
7352 return -1;
7040e556 7353
d9dda78b 7354 set_bypass_fn(PDE_DATA(file_inode(file)), bypass_param);
7040e556
D		 7355 return count;
7356}
a01b0c57 7357static int show_bypass(struct seq_file *m, void *v)
7040e556 7358{
a01b0c57
AV		 7359 bpctl_dev_t *dev = m->private;
7360 int ret = get_bypass_fn(dev);
7361 if (ret == BP_NOT_CAP)
7362 seq_printf(m, "fail\n");
7363 else if (ret == 1)
7364 seq_printf(m, "on\n");
7365 else if (ret == 0)
7366 seq_printf(m, "off\n");
7367 return 0;
7040e556 7368}
a01b0c57 7369RW_FOPS(bypass)
7040e556 7370
a01b0c57
AV		 7371static ssize_t tap_write(struct file *file, const char __user *buffer,
7372 size_t count, loff_t *pos)
7040e556 7373{
7e1be8a5
AV		 7374 int tap_param = user_on_off(buffer, count);
7375 if (tap_param < 0)
7040e556
D		 7376 return -1;
7377
d9dda78b 7378 set_tap_fn(PDE_DATA(file_inode(file)), tap_param);
7040e556
D		 7379 return count;
7380}
a01b0c57 7381static int show_tap(struct seq_file *m, void *v)
7040e556 7382{
a01b0c57
AV		 7383 bpctl_dev_t *dev = m->private;
7384 int ret = get_tap_fn(dev);
7040e556 7385 if (ret == BP_NOT_CAP)
a01b0c57 7386 seq_printf(m, "fail\n");
7040e556 7387 else if (ret == 1)
a01b0c57 7388 seq_printf(m, "on\n");
7040e556 7389 else if (ret == 0)
a01b0c57
AV		 7390 seq_printf(m, "off\n");
7391 return 0;
7040e556 7392}
a01b0c57 7393RW_FOPS(tap)
7040e556 7394
a01b0c57
AV		 7395static ssize_t disc_write(struct file *file, const char __user *buffer,
7396 size_t count, loff_t *pos)
7040e556 7397{
a01b0c57
AV		 7398 int tap_param = user_on_off(buffer, count);
7399 if (tap_param < 0)
7400 return -1;
7040e556 7401
d9dda78b 7402 set_disc_fn(PDE_DATA(file_inode(file)), tap_param);
a01b0c57 7403 return count;
7040e556 7404}
a01b0c57 7405static int show_disc(struct seq_file *m, void *v)
7040e556 7406{
a01b0c57
AV		 7407 bpctl_dev_t *dev = m->private;
7408 int ret = get_disc_fn(dev);
7040e556 7409 if (ret == BP_NOT_CAP)
a01b0c57 7410 seq_printf(m, "fail\n");
7040e556 7411 else if (ret == 1)
a01b0c57 7412 seq_printf(m, "on\n");
7040e556 7413 else if (ret == 0)
a01b0c57
AV		 7414 seq_printf(m, "off\n");
7415 return 0;
7040e556 7416}
a01b0c57 7417RW_FOPS(disc)
7040e556 7418
a01b0c57 7419static int show_bypass_change(struct seq_file *m, void *v)
7040e556 7420{
a01b0c57
AV		 7421 bpctl_dev_t *dev = m->private;
7422 int ret = get_bypass_change_fn(dev);
7040e556 7423 if (ret == 1)
a01b0c57 7424 seq_printf(m, "on\n");
7040e556 7425 else if (ret == 0)
a01b0c57 7426 seq_printf(m, "off\n");
7040e556 7427 else
a01b0c57
AV		 7428 seq_printf(m, "fail\n");
7429 return 0;
7040e556 7430}
a01b0c57 7431RO_FOPS(bypass_change)
7040e556 7432
a01b0c57 7433static int show_tap_change(struct seq_file *m, void *v)
7040e556 7434{
a01b0c57
AV		 7435 bpctl_dev_t *dev = m->private;
7436 int ret = get_tap_change_fn(dev);
7040e556 7437 if (ret == 1)
a01b0c57 7438 seq_printf(m, "on\n");
7040e556 7439 else if (ret == 0)
a01b0c57 7440 seq_printf(m, "off\n");
7040e556 7441 else
a01b0c57
AV		 7442 seq_printf(m, "fail\n");
7443 return 0;
7040e556 7444}
a01b0c57 7445RO_FOPS(tap_change)
7040e556 7446
a01b0c57 7447static int show_disc_change(struct seq_file *m, void *v)
7040e556 7448{
a01b0c57
AV		 7449 bpctl_dev_t *dev = m->private;
7450 int ret = get_disc_change_fn(dev);
7040e556 7451 if (ret == 1)
a01b0c57 7452 seq_printf(m, "on\n");
7040e556 7453 else if (ret == 0)
a01b0c57 7454 seq_printf(m, "off\n");
7040e556 7455 else
a01b0c57
AV		 7456 seq_printf(m, "fail\n");
7457 return 0;
7040e556 7458}
a01b0c57 7459RO_FOPS(disc_change)
7040e556 7460
a01b0c57
AV		 7461static ssize_t bypass_wd_write(struct file *file, const char __user *buffer,
7462 size_t count, loff_t *pos)
7040e556 7463{
d9dda78b 7464 bpctl_dev_t *dev = PDE_DATA(file_inode(file));
82e6bb03 7465 int timeout;
a01b0c57 7466 int ret = kstrtoint_from_user(buffer, count, 10, &timeout);
82e6bb03
DC		 7467 if (ret)
7468 return ret;
a01b0c57 7469 set_bypass_wd_fn(dev, timeout);
7040e556
D		 7470 return count;
7471}
a01b0c57 7472static int show_bypass_wd(struct seq_file *m, void *v)
7040e556 7473{
a01b0c57
AV		 7474 bpctl_dev_t *dev = m->private;
7475 int ret = 0, timeout = 0;
7040e556 7476
a01b0c57 7477 ret = get_bypass_wd_fn(dev, &timeout);
7040e556 7478 if (ret == BP_NOT_CAP)
a01b0c57 7479 seq_printf(m, "fail\n");
7040e556 7480 else if (timeout == -1)
a01b0c57 7481 seq_printf(m, "unknown\n");
7040e556 7482 else if (timeout == 0)
a01b0c57 7483 seq_printf(m, "disable\n");
7040e556 7484 else
a01b0c57
AV		 7485 seq_printf(m, "%d\n", timeout);
7486 return 0;
7040e556 7487}
a01b0c57 7488RW_FOPS(bypass_wd)
7040e556 7489
a01b0c57 7490static int show_wd_expire_time(struct seq_file *m, void *v)
7040e556 7491{
a01b0c57
AV		 7492 bpctl_dev_t *dev = m->private;
7493 int ret = 0, timeout = 0;
7494 ret = get_wd_expire_time_fn(dev, &timeout);
7040e556 7495 if (ret == BP_NOT_CAP)
a01b0c57 7496 seq_printf(m, "fail\n");
7040e556 7497 else if (timeout == -1)
a01b0c57 7498 seq_printf(m, "expire\n");
7040e556 7499 else if (timeout == 0)
a01b0c57 7500 seq_printf(m, "disable\n");
7040e556 7501 else
a01b0c57
AV		 7502 seq_printf(m, "%d\n", timeout);
7503 return 0;
7040e556 7504}
a01b0c57 7505RO_FOPS(wd_expire_time)
7040e556 7506
a01b0c57
AV		 7507static ssize_t tpl_write(struct file *file, const char __user *buffer,
7508 size_t count, loff_t *pos)
7040e556 7509{
d9dda78b 7510 bpctl_dev_t *dev = PDE_DATA(file_inode(file));
a01b0c57
AV		 7511 int tpl_param = user_on_off(buffer, count);
7512 if (tpl_param < 0)
7513 return -1;
7040e556 7514
a01b0c57
AV		 7515 set_tpl_fn(dev, tpl_param);
7516 return count;
7517}
7518static int show_tpl(struct seq_file *m, void *v)
7519{
7520 bpctl_dev_t *dev = m->private;
7521 int ret = get_tpl_fn(dev);
7040e556 7522 if (ret == BP_NOT_CAP)
a01b0c57 7523 seq_printf(m, "fail\n");
7040e556 7524 else if (ret == 1)
a01b0c57 7525 seq_printf(m, "on\n");
7040e556 7526 else if (ret == 0)
a01b0c57
AV		 7527 seq_printf(m, "off\n");
7528 return 0;
7040e556 7529}
a01b0c57 7530RW_FOPS(tpl)
7040e556
D		 7531
7532#ifdef PMC_FIX_FLAG
a01b0c57
AV		 7533static ssize_t wait_at_pwup_write(struct file *file, const char __user *buffer,
7534 size_t count, loff_t *pos)
7040e556 7535{
d9dda78b 7536 bpctl_dev_t *dev = PDE_DATA(file_inode(file));
a01b0c57
AV		 7537 int tpl_param = user_on_off(buffer, count);
7538 if (tpl_param < 0)
7539 return -1;
7040e556 7540
a01b0c57
AV		 7541 set_bp_wait_at_pwup_fn(dev, tpl_param);
7542 return count;
7543}
7544static int show_wait_at_pwup(struct seq_file *m, void *v)
7545{
7546 bpctl_dev_t *dev = m->private;
7547 int ret = get_bp_wait_at_pwup_fn(dev);
7040e556 7548 if (ret == BP_NOT_CAP)
a01b0c57 7549 seq_printf(m, "fail\n");
7040e556 7550 else if (ret == 1)
a01b0c57 7551 seq_printf(m, "on\n");
7040e556 7552 else if (ret == 0)
a01b0c57
AV		 7553 seq_printf(m, "off\n");
7554 return 0;
7040e556 7555}
a01b0c57 7556RW_FOPS(wait_at_pwup)
7040e556 7557
a01b0c57
AV		 7558static ssize_t hw_reset_write(struct file *file, const char __user *buffer,
7559 size_t count, loff_t *pos)
7040e556 7560{
d9dda78b 7561 bpctl_dev_t *dev = PDE_DATA(file_inode(file));
a01b0c57
AV		 7562 int tpl_param = user_on_off(buffer, count);
7563 if (tpl_param < 0)
7564 return -1;
7040e556 7565
a01b0c57
AV		 7566 set_bp_hw_reset_fn(dev, tpl_param);
7567 return count;
7568}
7569static int show_hw_reset(struct seq_file *m, void *v)
7570{
7571 bpctl_dev_t *dev = m->private;
7572 int ret = get_bp_hw_reset_fn(dev);
7040e556 7573 if (ret == BP_NOT_CAP)
a01b0c57 7574 seq_printf(m, "fail\n");
7040e556 7575 else if (ret == 1)
a01b0c57 7576 seq_printf(m, "on\n");
7040e556 7577 else if (ret == 0)
a01b0c57
AV		 7578 seq_printf(m, "off\n");
7579 return 0;
7040e556 7580}
a01b0c57 7581RW_FOPS(hw_reset)
7040e556
D		 7582
7583#endif /*PMC_WAIT_FLAG */
7584
a01b0c57 7585static int show_reset_bypass_wd(struct seq_file *m, void *v)
7040e556 7586{
a01b0c57
AV		 7587 bpctl_dev_t *dev = m->private;
7588 int ret = reset_bypass_wd_timer_fn(dev);
7040e556 7589 if (ret == BP_NOT_CAP)
a01b0c57 7590 seq_printf(m, "fail\n");
7040e556 7591 else if (ret == 0)
a01b0c57 7592 seq_printf(m, "disable\n");
7040e556 7593 else if (ret == 1)
a01b0c57
AV		 7594 seq_printf(m, "success\n");
7595 return 0;
7040e556 7596}
a01b0c57 7597RO_FOPS(reset_bypass_wd)
7040e556 7598
a01b0c57
AV		 7599static ssize_t dis_bypass_write(struct file *file, const char __user *buffer,
7600 size_t count, loff_t *pos)
7040e556 7601{
7e1be8a5
AV		 7602 int bypass_param = user_on_off(buffer, count);
7603 if (bypass_param < 0)
e4c536b7
DC		 7604 return -EINVAL;
7605
d9dda78b 7606 set_dis_bypass_fn(PDE_DATA(file_inode(file)), bypass_param);
7040e556
D		 7607 return count;
7608}
a01b0c57 7609static int show_dis_bypass(struct seq_file *m, void *v)
7040e556 7610{
a01b0c57
AV		 7611 bpctl_dev_t *dev = m->private;
7612 int ret = get_dis_bypass_fn(dev);
7613 if (ret == BP_NOT_CAP)
7614 seq_printf(m, "fail\n");
7615 else if (ret == 0)
7616 seq_printf(m, "off\n");
7617 else
7618 seq_printf(m, "on\n");
7619 return 0;
7040e556 7620}
a01b0c57 7621RW_FOPS(dis_bypass)
7040e556 7622
a01b0c57
AV		 7623static ssize_t dis_tap_write(struct file *file, const char __user *buffer,
7624 size_t count, loff_t *pos)
7040e556 7625{
7e1be8a5
AV		 7626 int tap_param = user_on_off(buffer, count);
7627 if (tap_param < 0)
e4c536b7
DC		 7628 return -EINVAL;
7629
d9dda78b 7630 set_dis_tap_fn(PDE_DATA(file_inode(file)), tap_param);
7040e556
D		 7631 return count;
7632}
a01b0c57 7633static int show_dis_tap(struct seq_file *m, void *v)
7040e556 7634{
a01b0c57
AV		 7635 bpctl_dev_t *dev = m->private;
7636 int ret = get_dis_tap_fn(dev);
7040e556 7637 if (ret == BP_NOT_CAP)
a01b0c57 7638 seq_printf(m, "fail\n");
7040e556 7639 else if (ret == 0)
a01b0c57 7640 seq_printf(m, "off\n");
7040e556 7641 else
a01b0c57
AV		 7642 seq_printf(m, "on\n");
7643 return 0;
7040e556 7644}
a01b0c57 7645RW_FOPS(dis_tap)
7040e556 7646
a01b0c57
AV		 7647static ssize_t dis_disc_write(struct file *file, const char __user *buffer,
7648 size_t count, loff_t *pos)
7040e556 7649{
a01b0c57
AV		 7650 int tap_param = user_on_off(buffer, count);
7651 if (tap_param < 0)
7652 return -EINVAL;
7040e556 7653
d9dda78b 7654 set_dis_disc_fn(PDE_DATA(file_inode(file)), tap_param);
a01b0c57 7655 return count;
7040e556 7656}
a01b0c57 7657static int show_dis_disc(struct seq_file *m, void *v)
7040e556 7658{
a01b0c57
AV		 7659 bpctl_dev_t *dev = m->private;
7660 int ret = get_dis_disc_fn(dev);
7040e556 7661 if (ret == BP_NOT_CAP)
a01b0c57 7662 seq_printf(m, "fail\n");
7040e556 7663 else if (ret == 0)
a01b0c57 7664 seq_printf(m, "off\n");
7040e556 7665 else
a01b0c57
AV		 7666 seq_printf(m, "on\n");
7667 return 0;
7040e556 7668}
a01b0c57 7669RW_FOPS(dis_disc)
7040e556 7670
a01b0c57
AV		 7671static ssize_t bypass_pwup_write(struct file *file, const char __user *buffer,
7672 size_t count, loff_t *pos)
7040e556 7673{
7e1be8a5
AV		 7674 int bypass_param = user_on_off(buffer, count);
7675 if (bypass_param < 0)
e4c536b7
DC		 7676 return -EINVAL;
7677
d9dda78b 7678 set_bypass_pwup_fn(PDE_DATA(file_inode(file)), bypass_param);
7040e556
D		 7679 return count;
7680}
a01b0c57
AV		 7681static int show_bypass_pwup(struct seq_file *m, void *v)
7682{
7683 bpctl_dev_t *dev = m->private;
7684 int ret = get_bypass_pwup_fn(dev);
7685 if (ret == BP_NOT_CAP)
7686 seq_printf(m, "fail\n");
7687 else if (ret == 0)
7688 seq_printf(m, "off\n");
7689 else
7690 seq_printf(m, "on\n");
7691 return 0;
7692}
7693RW_FOPS(bypass_pwup)
7040e556 7694
a01b0c57
AV		 7695static ssize_t bypass_pwoff_write(struct file *file, const char __user *buffer,
7696 size_t count, loff_t *pos)
7040e556 7697{
7e1be8a5
AV		 7698 int bypass_param = user_on_off(buffer, count);
7699 if (bypass_param < 0)
e4c536b7
DC		 7700 return -EINVAL;
7701
d9dda78b 7702 set_bypass_pwoff_fn(PDE_DATA(file_inode(file)), bypass_param);
7040e556
D		 7703 return count;
7704}
a01b0c57 7705static int show_bypass_pwoff(struct seq_file *m, void *v)
7040e556 7706{
a01b0c57
AV		 7707 bpctl_dev_t *dev = m->private;
7708 int ret = get_bypass_pwoff_fn(dev);
7709 if (ret == BP_NOT_CAP)
7710 seq_printf(m, "fail\n");
7711 else if (ret == 0)
7712 seq_printf(m, "off\n");
7713 else
7714 seq_printf(m, "on\n");
7715 return 0;
7040e556 7716}
a01b0c57 7717RW_FOPS(bypass_pwoff)
7040e556 7718
a01b0c57
AV		 7719static ssize_t tap_pwup_write(struct file *file, const char __user *buffer,
7720 size_t count, loff_t *pos)
7040e556 7721{
7e1be8a5
AV		 7722 int tap_param = user_on_off(buffer, count);
7723 if (tap_param < 0)
e4c536b7
DC		 7724 return -EINVAL;
7725
d9dda78b 7726 set_tap_pwup_fn(PDE_DATA(file_inode(file)), tap_param);
7040e556
D		 7727 return count;
7728}
a01b0c57 7729static int show_tap_pwup(struct seq_file *m, void *v)
7040e556 7730{
a01b0c57
AV		 7731 bpctl_dev_t *dev = m->private;
7732 int ret = get_tap_pwup_fn(dev);
7040e556 7733 if (ret == BP_NOT_CAP)
a01b0c57 7734 seq_printf(m, "fail\n");
7040e556 7735 else if (ret == 0)
a01b0c57 7736 seq_printf(m, "off\n");
7040e556 7737 else
a01b0c57
AV		 7738 seq_printf(m, "on\n");
7739 return 0;
7040e556 7740}
a01b0c57 7741RW_FOPS(tap_pwup)
7040e556 7742
a01b0c57
AV		 7743static ssize_t disc_pwup_write(struct file *file, const char __user *buffer,
7744 size_t count, loff_t *pos)
7040e556 7745{
a01b0c57
AV		 7746 int tap_param = user_on_off(buffer, count);
7747 if (tap_param < 0)
7748 return -EINVAL;
7040e556 7749
d9dda78b 7750 set_disc_pwup_fn(PDE_DATA(file_inode(file)), tap_param);
a01b0c57 7751 return count;
7040e556 7752}
a01b0c57 7753static int show_disc_pwup(struct seq_file *m, void *v)
7040e556 7754{
a01b0c57
AV		 7755 bpctl_dev_t *dev = m->private;
7756 int ret = get_disc_pwup_fn(dev);
7040e556 7757 if (ret == BP_NOT_CAP)
a01b0c57 7758 seq_printf(m, "fail\n");
7040e556 7759 else if (ret == 0)
a01b0c57 7760 seq_printf(m, "off\n");
7040e556 7761 else
a01b0c57
AV		 7762 seq_printf(m, "on\n");
7763 return 0;
7040e556 7764}
a01b0c57 7765RW_FOPS(disc_pwup)
7040e556 7766
a01b0c57
AV		 7767static ssize_t std_nic_write(struct file *file, const char __user *buffer,
7768 size_t count, loff_t *pos)
7040e556 7769{
7e1be8a5
AV		 7770 int bypass_param = user_on_off(buffer, count);
7771 if (bypass_param < 0)
e4c536b7
DC		 7772 return -EINVAL;
7773
d9dda78b 7774 set_std_nic_fn(PDE_DATA(file_inode(file)), bypass_param);
7040e556
D		 7775 return count;
7776}
a01b0c57 7777static int show_std_nic(struct seq_file *m, void *v)
7040e556 7778{
a01b0c57
AV		 7779 bpctl_dev_t *dev = m->private;
7780 int ret = get_std_nic_fn(dev);
7040e556 7781 if (ret == BP_NOT_CAP)
a01b0c57 7782 seq_printf(m, "fail\n");
7040e556 7783 else if (ret == 0)
a01b0c57 7784 seq_printf(m, "off\n");
7040e556 7785 else
a01b0c57
AV		 7786 seq_printf(m, "on\n");
7787 return 0;
7040e556 7788}
a01b0c57 7789RW_FOPS(std_nic)
7040e556 7790
a01b0c57
AV		 7791static ssize_t wd_exp_mode_write(struct file *file, const char __user *buffer,
7792 size_t count, loff_t *pos)
7040e556 7793{
7040e556 7794 char kbuf[256];
7040e556
D		 7795 int bypass_param = 0, length = 0;
7796
7797 if (count > (sizeof(kbuf) - 1))
7798 return -1;
7799
a01b0c57 7800 if (copy_from_user(&kbuf, buffer, count))
7040e556 7801 return -1;
7040e556
D		 7802
7803 kbuf[count] = '\0';
7804 length = strlen(kbuf);
7805 if (kbuf[length - 1] == '\n')
7806 kbuf[--length] = '\0';
7807
7808 if (strcmp(kbuf, "tap") == 0)
7809 bypass_param = 1;
7810 else if (strcmp(kbuf, "bypass") == 0)
7811 bypass_param = 0;
7812 else if (strcmp(kbuf, "disc") == 0)
7813 bypass_param = 2;
7814
d9dda78b 7815 set_wd_exp_mode_fn(PDE_DATA(file_inode(file)), bypass_param);
7040e556
D		 7816
7817 return count;
7818}
a01b0c57 7819static int show_wd_exp_mode(struct seq_file *m, void *v)
7040e556 7820{
a01b0c57
AV		 7821 bpctl_dev_t *dev = m->private;
7822 int ret = get_wd_exp_mode_fn(dev);
7823 if (ret == 1)
7824 seq_printf(m, "tap\n");
7825 else if (ret == 0)
7826 seq_printf(m, "bypass\n");
7827 else if (ret == 2)
7828 seq_printf(m, "disc\n");
7040e556 7829 else
a01b0c57
AV		 7830 seq_printf(m, "fail\n");
7831 return 0;
7040e556 7832}
a01b0c57 7833RW_FOPS(wd_exp_mode)
7040e556 7834
a01b0c57
AV		 7835static ssize_t wd_autoreset_write(struct file *file, const char __user *buffer,
7836 size_t count, loff_t *pos)
7040e556 7837{
82e6bb03 7838 int timeout;
a01b0c57 7839 int ret = kstrtoint_from_user(buffer, count, 10, &timeout);
82e6bb03
DC		 7840 if (ret)
7841 return ret;
d9dda78b 7842 set_wd_autoreset_fn(PDE_DATA(file_inode(file)), timeout);
7040e556
D		 7843 return count;
7844}
a01b0c57 7845static int show_wd_autoreset(struct seq_file *m, void *v)
7040e556 7846{
a01b0c57
AV		 7847 bpctl_dev_t *dev = m->private;
7848 int ret = get_wd_autoreset_fn(dev);
7849 if (ret >= 0)
7850 seq_printf(m, "%d\n", ret);
7851 else
7852 seq_printf(m, "fail\n");
7853 return 0;
7040e556 7854}
a01b0c57 7855RW_FOPS(wd_autoreset)
7040e556 7856
7c014321 7857int bypass_proc_create_dev_sd(bpctl_dev_t *pbp_device_block)
7040e556
D		 7858{
7859 struct bypass_pfs_sd *current_pfs = &(pbp_device_block->bypass_pfs_set);
7860 static struct proc_dir_entry *procfs_dir = NULL;
7861 int ret = 0;
7862
7863 if (!pbp_device_block->ndev)
7864 return -1;
7865 sprintf(current_pfs->dir_name, "bypass_%s",
7866 pbp_device_block->ndev->name);
7867
7868 if (!bp_procfs_dir)
7869 return -1;
7870
7871 /* create device proc dir */
a01b0c57
AV		 7872 procfs_dir = proc_mkdir(current_pfs->dir_name, bp_procfs_dir);
7873 if (!procfs_dir) {
7040e556
D		 7874 printk(KERN_DEBUG "Could not create procfs directory %s\n",
7875 current_pfs->dir_name);
7876 return -1;
7877 }
7878 current_pfs->bypass_entry = procfs_dir;
7879
a01b0c57
AV		 7880#define ENTRY(x) ret |= procfs_add(#x, &x##_ops, pbp_device_block)
7881 ENTRY(bypass_info);
7040e556 7882 if (pbp_device_block->bp_caps & SW_CTL_CAP) {
7040e556 7883 /* Create set param proc's */
a01b0c57
AV		 7884 ENTRY(bypass_slave);
7885 ENTRY(bypass_caps);
7886 ENTRY(wd_set_caps);
7887 ENTRY(bypass_wd);
7888 ENTRY(wd_expire_time);
7889 ENTRY(reset_bypass_wd);
7890 ENTRY(std_nic);
7040e556 7891 if (pbp_device_block->bp_caps & BP_CAP) {
a01b0c57
AV		 7892 ENTRY(bypass);
7893 ENTRY(dis_bypass);
7894 ENTRY(bypass_pwup);
7895 ENTRY(bypass_pwoff);
7896 ENTRY(bypass_change);
7040e556 7897 }
7040e556 7898 if (pbp_device_block->bp_caps & TAP_CAP) {
a01b0c57
AV		 7899 ENTRY(tap);
7900 ENTRY(dis_tap);
7901 ENTRY(tap_pwup);
7902 ENTRY(tap_change);
7040e556
D		 7903 }
7904 if (pbp_device_block->bp_caps & DISC_CAP) {
a01b0c57
AV		 7905 ENTRY(disc);
7906 ENTRY(dis_disc);
7907 ENTRY(disc_pwup);
7908 ENTRY(disc_change);
7040e556
D		 7909 }
7910
a01b0c57
AV		 7911 ENTRY(wd_exp_mode);
7912 ENTRY(wd_autoreset);
7913 ENTRY(tpl);
7040e556 7914#ifdef PMC_FIX_FLAG
a01b0c57
AV		 7915 ENTRY(wait_at_pwup);
7916 ENTRY(hw_reset);
7040e556 7917#endif
7040e556 7918 }
a01b0c57 7919#undef ENTRY
7040e556
D		 7920 if (ret < 0)
7921 printk(KERN_DEBUG "Create proc entry failed\n");
7922
7923 return ret;
7924}
7925
7c014321 7926int bypass_proc_remove_dev_sd(bpctl_dev_t *pbp_device_block)
7040e556
D		 7927{
7928
7929 struct bypass_pfs_sd *current_pfs = &pbp_device_block->bypass_pfs_set;
a01b0c57 7930 remove_proc_subtree(current_pfs->dir_name, bp_procfs_dir);
7040e556 7931 current_pfs->bypass_entry = NULL;
7040e556
D		 7932 return 0;
7933}
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