]>
Commit | Line | Data |
---|---|---|
60479690 MW |
1 | /* |
2 | * Support for the Tundra Universe I/II VME-PCI Bridge Chips | |
3 | * | |
66bd8db5 MW |
4 | * Author: Martyn Welch <martyn.welch@ge.com> |
5 | * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. | |
60479690 MW |
6 | * |
7 | * Based on work by Tom Armistead and Ajit Prem | |
8 | * Copyright 2004 Motorola Inc. | |
9 | * | |
10 | * Derived from ca91c042.c by Michael Wyrick | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License as published by the | |
14 | * Free Software Foundation; either version 2 of the License, or (at your | |
15 | * option) any later version. | |
16 | */ | |
17 | ||
60479690 MW |
18 | #include <linux/module.h> |
19 | #include <linux/mm.h> | |
20 | #include <linux/types.h> | |
21 | #include <linux/errno.h> | |
60479690 MW |
22 | #include <linux/pci.h> |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/poll.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/spinlock.h> | |
6af783c8 | 27 | #include <linux/sched.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
7946328f MW |
29 | #include <linux/time.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/uaccess.h> | |
60479690 MW |
32 | |
33 | #include "../vme.h" | |
34 | #include "../vme_bridge.h" | |
35 | #include "vme_ca91cx42.h" | |
36 | ||
3d0f8bc7 MW |
37 | static int __init ca91cx42_init(void); |
38 | static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *); | |
39 | static void ca91cx42_remove(struct pci_dev *); | |
40 | static void __exit ca91cx42_exit(void); | |
60479690 | 41 | |
12b2d5c0 MW |
42 | /* Module parameters */ |
43 | static int geoid; | |
44 | ||
3d0f8bc7 | 45 | static char driver_name[] = "vme_ca91cx42"; |
60479690 | 46 | |
13ac58da | 47 | static const struct pci_device_id ca91cx42_ids[] = { |
3d0f8bc7 MW |
48 | { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) }, |
49 | { }, | |
60479690 MW |
50 | }; |
51 | ||
3d0f8bc7 MW |
52 | static struct pci_driver ca91cx42_driver = { |
53 | .name = driver_name, | |
54 | .id_table = ca91cx42_ids, | |
55 | .probe = ca91cx42_probe, | |
56 | .remove = ca91cx42_remove, | |
60479690 MW |
57 | }; |
58 | ||
29848ac9 | 59 | static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge) |
60479690 | 60 | { |
29848ac9 | 61 | wake_up(&(bridge->dma_queue)); |
60479690 | 62 | |
3d0f8bc7 MW |
63 | return CA91CX42_LINT_DMA; |
64 | } | |
60479690 | 65 | |
29848ac9 | 66 | static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat) |
3d0f8bc7 MW |
67 | { |
68 | int i; | |
69 | u32 serviced = 0; | |
60479690 | 70 | |
3d0f8bc7 MW |
71 | for (i = 0; i < 4; i++) { |
72 | if (stat & CA91CX42_LINT_LM[i]) { | |
73 | /* We only enable interrupts if the callback is set */ | |
29848ac9 | 74 | bridge->lm_callback[i](i); |
3d0f8bc7 | 75 | serviced |= CA91CX42_LINT_LM[i]; |
60479690 | 76 | } |
60479690 | 77 | } |
60479690 | 78 | |
3d0f8bc7 MW |
79 | return serviced; |
80 | } | |
60479690 | 81 | |
3d0f8bc7 | 82 | /* XXX This needs to be split into 4 queues */ |
29848ac9 | 83 | static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask) |
3d0f8bc7 | 84 | { |
29848ac9 | 85 | wake_up(&(bridge->mbox_queue)); |
60479690 | 86 | |
3d0f8bc7 MW |
87 | return CA91CX42_LINT_MBOX; |
88 | } | |
60479690 | 89 | |
29848ac9 | 90 | static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) |
3d0f8bc7 | 91 | { |
29848ac9 | 92 | wake_up(&(bridge->iack_queue)); |
60479690 | 93 | |
3d0f8bc7 | 94 | return CA91CX42_LINT_SW_IACK; |
60479690 MW |
95 | } |
96 | ||
48d9356e | 97 | static u32 ca91cx42_VERR_irqhandler(struct vme_bridge *ca91cx42_bridge) |
60479690 MW |
98 | { |
99 | int val; | |
48d9356e MW |
100 | struct ca91cx42_driver *bridge; |
101 | ||
102 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 103 | |
29848ac9 | 104 | val = ioread32(bridge->base + DGCS); |
60479690 MW |
105 | |
106 | if (!(val & 0x00000800)) { | |
48d9356e MW |
107 | dev_err(ca91cx42_bridge->parent, "ca91cx42_VERR_irqhandler DMA " |
108 | "Read Error DGCS=%08X\n", val); | |
60479690 | 109 | } |
3d0f8bc7 MW |
110 | |
111 | return CA91CX42_LINT_VERR; | |
60479690 MW |
112 | } |
113 | ||
48d9356e | 114 | static u32 ca91cx42_LERR_irqhandler(struct vme_bridge *ca91cx42_bridge) |
60479690 MW |
115 | { |
116 | int val; | |
48d9356e | 117 | struct ca91cx42_driver *bridge; |
60479690 | 118 | |
48d9356e | 119 | bridge = ca91cx42_bridge->driver_priv; |
60479690 | 120 | |
48d9356e | 121 | val = ioread32(bridge->base + DGCS); |
60479690 | 122 | |
48d9356e MW |
123 | if (!(val & 0x00000800)) |
124 | dev_err(ca91cx42_bridge->parent, "ca91cx42_LERR_irqhandler DMA " | |
125 | "Read Error DGCS=%08X\n", val); | |
60479690 | 126 | |
3d0f8bc7 | 127 | return CA91CX42_LINT_LERR; |
60479690 MW |
128 | } |
129 | ||
3d0f8bc7 | 130 | |
29848ac9 MW |
131 | static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge, |
132 | int stat) | |
60479690 | 133 | { |
3d0f8bc7 | 134 | int vec, i, serviced = 0; |
29848ac9 MW |
135 | struct ca91cx42_driver *bridge; |
136 | ||
137 | bridge = ca91cx42_bridge->driver_priv; | |
138 | ||
60479690 MW |
139 | |
140 | for (i = 7; i > 0; i--) { | |
3d0f8bc7 | 141 | if (stat & (1 << i)) { |
29848ac9 | 142 | vec = ioread32(bridge->base + |
3d0f8bc7 MW |
143 | CA91CX42_V_STATID[i]) & 0xff; |
144 | ||
c813f592 | 145 | vme_irq_handler(ca91cx42_bridge, i, vec); |
3d0f8bc7 MW |
146 | |
147 | serviced |= (1 << i); | |
60479690 MW |
148 | } |
149 | } | |
3d0f8bc7 MW |
150 | |
151 | return serviced; | |
60479690 MW |
152 | } |
153 | ||
29848ac9 | 154 | static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr) |
60479690 | 155 | { |
3d0f8bc7 | 156 | u32 stat, enable, serviced = 0; |
29848ac9 MW |
157 | struct vme_bridge *ca91cx42_bridge; |
158 | struct ca91cx42_driver *bridge; | |
60479690 | 159 | |
29848ac9 | 160 | ca91cx42_bridge = ptr; |
60479690 | 161 | |
29848ac9 MW |
162 | bridge = ca91cx42_bridge->driver_priv; |
163 | ||
164 | enable = ioread32(bridge->base + LINT_EN); | |
165 | stat = ioread32(bridge->base + LINT_STAT); | |
60479690 | 166 | |
3d0f8bc7 MW |
167 | /* Only look at unmasked interrupts */ |
168 | stat &= enable; | |
169 | ||
170 | if (unlikely(!stat)) | |
171 | return IRQ_NONE; | |
172 | ||
173 | if (stat & CA91CX42_LINT_DMA) | |
29848ac9 | 174 | serviced |= ca91cx42_DMA_irqhandler(bridge); |
3d0f8bc7 MW |
175 | if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 | |
176 | CA91CX42_LINT_LM3)) | |
29848ac9 | 177 | serviced |= ca91cx42_LM_irqhandler(bridge, stat); |
3d0f8bc7 | 178 | if (stat & CA91CX42_LINT_MBOX) |
29848ac9 | 179 | serviced |= ca91cx42_MB_irqhandler(bridge, stat); |
3d0f8bc7 | 180 | if (stat & CA91CX42_LINT_SW_IACK) |
29848ac9 | 181 | serviced |= ca91cx42_IACK_irqhandler(bridge); |
3d0f8bc7 | 182 | if (stat & CA91CX42_LINT_VERR) |
48d9356e | 183 | serviced |= ca91cx42_VERR_irqhandler(ca91cx42_bridge); |
3d0f8bc7 | 184 | if (stat & CA91CX42_LINT_LERR) |
48d9356e | 185 | serviced |= ca91cx42_LERR_irqhandler(ca91cx42_bridge); |
3d0f8bc7 MW |
186 | if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 | |
187 | CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 | | |
188 | CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 | | |
189 | CA91CX42_LINT_VIRQ7)) | |
29848ac9 | 190 | serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat); |
3d0f8bc7 MW |
191 | |
192 | /* Clear serviced interrupts */ | |
29848ac9 | 193 | iowrite32(stat, bridge->base + LINT_STAT); |
60479690 MW |
194 | |
195 | return IRQ_HANDLED; | |
196 | } | |
197 | ||
29848ac9 | 198 | static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge) |
60479690 | 199 | { |
3d0f8bc7 MW |
200 | int result, tmp; |
201 | struct pci_dev *pdev; | |
29848ac9 MW |
202 | struct ca91cx42_driver *bridge; |
203 | ||
204 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 205 | |
3d0f8bc7 | 206 | /* Need pdev */ |
29848ac9 | 207 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); |
60479690 | 208 | |
3d0f8bc7 | 209 | /* Initialise list for VME bus errors */ |
29848ac9 | 210 | INIT_LIST_HEAD(&(ca91cx42_bridge->vme_errors)); |
60479690 | 211 | |
29848ac9 | 212 | mutex_init(&(ca91cx42_bridge->irq_mtx)); |
c813f592 | 213 | |
3d0f8bc7 MW |
214 | /* Disable interrupts from PCI to VME */ |
215 | iowrite32(0, bridge->base + VINT_EN); | |
60479690 | 216 | |
3d0f8bc7 MW |
217 | /* Disable PCI interrupts */ |
218 | iowrite32(0, bridge->base + LINT_EN); | |
219 | /* Clear Any Pending PCI Interrupts */ | |
220 | iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); | |
60479690 | 221 | |
3d0f8bc7 | 222 | result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED, |
29848ac9 | 223 | driver_name, ca91cx42_bridge); |
3d0f8bc7 MW |
224 | if (result) { |
225 | dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n", | |
226 | pdev->irq); | |
227 | return result; | |
60479690 MW |
228 | } |
229 | ||
3d0f8bc7 MW |
230 | /* Ensure all interrupts are mapped to PCI Interrupt 0 */ |
231 | iowrite32(0, bridge->base + LINT_MAP0); | |
232 | iowrite32(0, bridge->base + LINT_MAP1); | |
233 | iowrite32(0, bridge->base + LINT_MAP2); | |
234 | ||
235 | /* Enable DMA, mailbox & LM Interrupts */ | |
236 | tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 | | |
237 | CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK | | |
238 | CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA; | |
239 | ||
240 | iowrite32(tmp, bridge->base + LINT_EN); | |
60479690 | 241 | |
3d0f8bc7 | 242 | return 0; |
60479690 MW |
243 | } |
244 | ||
29848ac9 MW |
245 | static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge, |
246 | struct pci_dev *pdev) | |
60479690 | 247 | { |
3d0f8bc7 | 248 | /* Disable interrupts from PCI to VME */ |
29848ac9 | 249 | iowrite32(0, bridge->base + VINT_EN); |
60479690 | 250 | |
3d0f8bc7 | 251 | /* Disable PCI interrupts */ |
29848ac9 | 252 | iowrite32(0, bridge->base + LINT_EN); |
3d0f8bc7 | 253 | /* Clear Any Pending PCI Interrupts */ |
29848ac9 | 254 | iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); |
60479690 | 255 | |
3d0f8bc7 MW |
256 | free_irq(pdev->irq, pdev); |
257 | } | |
60479690 | 258 | |
3d0f8bc7 MW |
259 | /* |
260 | * Set up an VME interrupt | |
261 | */ | |
29848ac9 MW |
262 | void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state, |
263 | int sync) | |
c813f592 | 264 | |
3d0f8bc7 | 265 | { |
c813f592 | 266 | struct pci_dev *pdev; |
3d0f8bc7 | 267 | u32 tmp; |
29848ac9 MW |
268 | struct ca91cx42_driver *bridge; |
269 | ||
270 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 271 | |
3d0f8bc7 | 272 | /* Enable IRQ level */ |
29848ac9 | 273 | tmp = ioread32(bridge->base + LINT_EN); |
3d0f8bc7 | 274 | |
c813f592 | 275 | if (state == 0) |
3d0f8bc7 | 276 | tmp &= ~CA91CX42_LINT_VIRQ[level]; |
c813f592 MW |
277 | else |
278 | tmp |= CA91CX42_LINT_VIRQ[level]; | |
60479690 | 279 | |
29848ac9 | 280 | iowrite32(tmp, bridge->base + LINT_EN); |
c813f592 MW |
281 | |
282 | if ((state == 0) && (sync != 0)) { | |
3d0f8bc7 MW |
283 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, |
284 | dev); | |
285 | ||
286 | synchronize_irq(pdev->irq); | |
60479690 | 287 | } |
60479690 MW |
288 | } |
289 | ||
29848ac9 MW |
290 | int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level, |
291 | int statid) | |
60479690 | 292 | { |
3d0f8bc7 | 293 | u32 tmp; |
29848ac9 MW |
294 | struct ca91cx42_driver *bridge; |
295 | ||
296 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 297 | |
3d0f8bc7 MW |
298 | /* Universe can only generate even vectors */ |
299 | if (statid & 1) | |
300 | return -EINVAL; | |
60479690 | 301 | |
29848ac9 | 302 | mutex_lock(&(bridge->vme_int)); |
60479690 | 303 | |
29848ac9 | 304 | tmp = ioread32(bridge->base + VINT_EN); |
60479690 | 305 | |
3d0f8bc7 | 306 | /* Set Status/ID */ |
29848ac9 | 307 | iowrite32(statid << 24, bridge->base + STATID); |
3d0f8bc7 MW |
308 | |
309 | /* Assert VMEbus IRQ */ | |
310 | tmp = tmp | (1 << (level + 24)); | |
29848ac9 | 311 | iowrite32(tmp, bridge->base + VINT_EN); |
60479690 | 312 | |
3d0f8bc7 | 313 | /* Wait for IACK */ |
29848ac9 | 314 | wait_event_interruptible(bridge->iack_queue, 0); |
3d0f8bc7 MW |
315 | |
316 | /* Return interrupt to low state */ | |
29848ac9 | 317 | tmp = ioread32(bridge->base + VINT_EN); |
3d0f8bc7 | 318 | tmp = tmp & ~(1 << (level + 24)); |
29848ac9 | 319 | iowrite32(tmp, bridge->base + VINT_EN); |
3d0f8bc7 | 320 | |
29848ac9 | 321 | mutex_unlock(&(bridge->vme_int)); |
3d0f8bc7 MW |
322 | |
323 | return 0; | |
60479690 MW |
324 | } |
325 | ||
3d0f8bc7 MW |
326 | int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, |
327 | unsigned long long vme_base, unsigned long long size, | |
328 | dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle) | |
60479690 | 329 | { |
21e0cf6d | 330 | unsigned int i, addr = 0, granularity; |
3d0f8bc7 MW |
331 | unsigned int temp_ctl = 0; |
332 | unsigned int vme_bound, pci_offset; | |
48d9356e | 333 | struct vme_bridge *ca91cx42_bridge; |
29848ac9 MW |
334 | struct ca91cx42_driver *bridge; |
335 | ||
48d9356e MW |
336 | ca91cx42_bridge = image->parent; |
337 | ||
338 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 339 | |
3d0f8bc7 | 340 | i = image->number; |
60479690 | 341 | |
3d0f8bc7 MW |
342 | switch (aspace) { |
343 | case VME_A16: | |
344 | addr |= CA91CX42_VSI_CTL_VAS_A16; | |
345 | break; | |
346 | case VME_A24: | |
347 | addr |= CA91CX42_VSI_CTL_VAS_A24; | |
348 | break; | |
349 | case VME_A32: | |
350 | addr |= CA91CX42_VSI_CTL_VAS_A32; | |
351 | break; | |
352 | case VME_USER1: | |
353 | addr |= CA91CX42_VSI_CTL_VAS_USER1; | |
354 | break; | |
355 | case VME_USER2: | |
356 | addr |= CA91CX42_VSI_CTL_VAS_USER2; | |
357 | break; | |
358 | case VME_A64: | |
359 | case VME_CRCSR: | |
360 | case VME_USER3: | |
361 | case VME_USER4: | |
362 | default: | |
48d9356e | 363 | dev_err(ca91cx42_bridge->parent, "Invalid address space\n"); |
3d0f8bc7 MW |
364 | return -EINVAL; |
365 | break; | |
60479690 MW |
366 | } |
367 | ||
3d0f8bc7 MW |
368 | /* |
369 | * Bound address is a valid address for the window, adjust | |
370 | * accordingly | |
371 | */ | |
21e0cf6d | 372 | vme_bound = vme_base + size; |
3d0f8bc7 MW |
373 | pci_offset = pci_base - vme_base; |
374 | ||
3d0f8bc7 MW |
375 | if ((i == 0) || (i == 4)) |
376 | granularity = 0x1000; | |
377 | else | |
378 | granularity = 0x10000; | |
379 | ||
380 | if (vme_base & (granularity - 1)) { | |
48d9356e MW |
381 | dev_err(ca91cx42_bridge->parent, "Invalid VME base " |
382 | "alignment\n"); | |
3d0f8bc7 MW |
383 | return -EINVAL; |
384 | } | |
385 | if (vme_bound & (granularity - 1)) { | |
48d9356e MW |
386 | dev_err(ca91cx42_bridge->parent, "Invalid VME bound " |
387 | "alignment\n"); | |
3d0f8bc7 MW |
388 | return -EINVAL; |
389 | } | |
390 | if (pci_offset & (granularity - 1)) { | |
48d9356e MW |
391 | dev_err(ca91cx42_bridge->parent, "Invalid PCI Offset " |
392 | "alignment\n"); | |
3d0f8bc7 | 393 | return -EINVAL; |
60479690 MW |
394 | } |
395 | ||
3d0f8bc7 | 396 | /* Disable while we are mucking around */ |
29848ac9 | 397 | temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); |
3d0f8bc7 | 398 | temp_ctl &= ~CA91CX42_VSI_CTL_EN; |
29848ac9 | 399 | iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); |
60479690 | 400 | |
3d0f8bc7 | 401 | /* Setup mapping */ |
29848ac9 MW |
402 | iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); |
403 | iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); | |
404 | iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); | |
3d0f8bc7 | 405 | |
3d0f8bc7 MW |
406 | /* Setup address space */ |
407 | temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M; | |
408 | temp_ctl |= addr; | |
409 | ||
410 | /* Setup cycle types */ | |
411 | temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M); | |
412 | if (cycle & VME_SUPER) | |
413 | temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR; | |
414 | if (cycle & VME_USER) | |
415 | temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV; | |
416 | if (cycle & VME_PROG) | |
417 | temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM; | |
418 | if (cycle & VME_DATA) | |
419 | temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA; | |
420 | ||
421 | /* Write ctl reg without enable */ | |
29848ac9 | 422 | iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); |
3d0f8bc7 MW |
423 | |
424 | if (enabled) | |
425 | temp_ctl |= CA91CX42_VSI_CTL_EN; | |
426 | ||
29848ac9 | 427 | iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); |
3d0f8bc7 MW |
428 | |
429 | return 0; | |
60479690 MW |
430 | } |
431 | ||
3d0f8bc7 MW |
432 | int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled, |
433 | unsigned long long *vme_base, unsigned long long *size, | |
434 | dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle) | |
60479690 | 435 | { |
3d0f8bc7 MW |
436 | unsigned int i, granularity = 0, ctl = 0; |
437 | unsigned long long vme_bound, pci_offset; | |
29848ac9 MW |
438 | struct ca91cx42_driver *bridge; |
439 | ||
440 | bridge = image->parent->driver_priv; | |
3d0f8bc7 MW |
441 | |
442 | i = image->number; | |
60479690 | 443 | |
3d0f8bc7 MW |
444 | if ((i == 0) || (i == 4)) |
445 | granularity = 0x1000; | |
446 | else | |
447 | granularity = 0x10000; | |
448 | ||
449 | /* Read Registers */ | |
29848ac9 | 450 | ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); |
3d0f8bc7 | 451 | |
29848ac9 MW |
452 | *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]); |
453 | vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]); | |
454 | pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]); | |
3d0f8bc7 MW |
455 | |
456 | *pci_base = (dma_addr_t)vme_base + pci_offset; | |
457 | *size = (unsigned long long)((vme_bound - *vme_base) + granularity); | |
458 | ||
459 | *enabled = 0; | |
460 | *aspace = 0; | |
461 | *cycle = 0; | |
462 | ||
463 | if (ctl & CA91CX42_VSI_CTL_EN) | |
464 | *enabled = 1; | |
465 | ||
466 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16) | |
467 | *aspace = VME_A16; | |
468 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24) | |
469 | *aspace = VME_A24; | |
470 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32) | |
471 | *aspace = VME_A32; | |
472 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1) | |
473 | *aspace = VME_USER1; | |
474 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2) | |
475 | *aspace = VME_USER2; | |
476 | ||
477 | if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR) | |
478 | *cycle |= VME_SUPER; | |
479 | if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV) | |
480 | *cycle |= VME_USER; | |
481 | if (ctl & CA91CX42_VSI_CTL_PGM_PGM) | |
482 | *cycle |= VME_PROG; | |
483 | if (ctl & CA91CX42_VSI_CTL_PGM_DATA) | |
484 | *cycle |= VME_DATA; | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
489 | /* | |
490 | * Allocate and map PCI Resource | |
491 | */ | |
492 | static int ca91cx42_alloc_resource(struct vme_master_resource *image, | |
493 | unsigned long long size) | |
494 | { | |
495 | unsigned long long existing_size; | |
496 | int retval = 0; | |
497 | struct pci_dev *pdev; | |
29848ac9 MW |
498 | struct vme_bridge *ca91cx42_bridge; |
499 | ||
500 | ca91cx42_bridge = image->parent; | |
3d0f8bc7 MW |
501 | |
502 | /* Find pci_dev container of dev */ | |
503 | if (ca91cx42_bridge->parent == NULL) { | |
48d9356e | 504 | dev_err(ca91cx42_bridge->parent, "Dev entry NULL\n"); |
3d0f8bc7 MW |
505 | return -EINVAL; |
506 | } | |
507 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); | |
508 | ||
8fafb476 MW |
509 | existing_size = (unsigned long long)(image->bus_resource.end - |
510 | image->bus_resource.start); | |
3d0f8bc7 MW |
511 | |
512 | /* If the existing size is OK, return */ | |
513 | if (existing_size == (size - 1)) | |
514 | return 0; | |
515 | ||
516 | if (existing_size != 0) { | |
517 | iounmap(image->kern_base); | |
518 | image->kern_base = NULL; | |
8fafb476 MW |
519 | if (image->bus_resource.name != NULL) |
520 | kfree(image->bus_resource.name); | |
521 | release_resource(&(image->bus_resource)); | |
522 | memset(&(image->bus_resource), 0, sizeof(struct resource)); | |
3d0f8bc7 MW |
523 | } |
524 | ||
8fafb476 | 525 | if (image->bus_resource.name == NULL) { |
0aa3f139 | 526 | image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC); |
8fafb476 | 527 | if (image->bus_resource.name == NULL) { |
48d9356e MW |
528 | dev_err(ca91cx42_bridge->parent, "Unable to allocate " |
529 | "memory for resource name\n"); | |
3d0f8bc7 MW |
530 | retval = -ENOMEM; |
531 | goto err_name; | |
532 | } | |
60479690 | 533 | } |
3d0f8bc7 | 534 | |
8fafb476 | 535 | sprintf((char *)image->bus_resource.name, "%s.%d", |
3d0f8bc7 MW |
536 | ca91cx42_bridge->name, image->number); |
537 | ||
8fafb476 MW |
538 | image->bus_resource.start = 0; |
539 | image->bus_resource.end = (unsigned long)size; | |
540 | image->bus_resource.flags = IORESOURCE_MEM; | |
3d0f8bc7 MW |
541 | |
542 | retval = pci_bus_alloc_resource(pdev->bus, | |
8fafb476 | 543 | &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, |
3d0f8bc7 MW |
544 | 0, NULL, NULL); |
545 | if (retval) { | |
48d9356e MW |
546 | dev_err(ca91cx42_bridge->parent, "Failed to allocate mem " |
547 | "resource for window %d size 0x%lx start 0x%lx\n", | |
3d0f8bc7 | 548 | image->number, (unsigned long)size, |
8fafb476 | 549 | (unsigned long)image->bus_resource.start); |
3d0f8bc7 | 550 | goto err_resource; |
60479690 | 551 | } |
3d0f8bc7 MW |
552 | |
553 | image->kern_base = ioremap_nocache( | |
8fafb476 | 554 | image->bus_resource.start, size); |
3d0f8bc7 | 555 | if (image->kern_base == NULL) { |
48d9356e | 556 | dev_err(ca91cx42_bridge->parent, "Failed to remap resource\n"); |
3d0f8bc7 MW |
557 | retval = -ENOMEM; |
558 | goto err_remap; | |
60479690 MW |
559 | } |
560 | ||
3d0f8bc7 MW |
561 | return 0; |
562 | ||
563 | iounmap(image->kern_base); | |
564 | image->kern_base = NULL; | |
565 | err_remap: | |
8fafb476 | 566 | release_resource(&(image->bus_resource)); |
3d0f8bc7 | 567 | err_resource: |
8fafb476 MW |
568 | kfree(image->bus_resource.name); |
569 | memset(&(image->bus_resource), 0, sizeof(struct resource)); | |
3d0f8bc7 MW |
570 | err_name: |
571 | return retval; | |
572 | } | |
573 | ||
574 | /* | |
4860ab74 MW |
575 | * Free and unmap PCI Resource |
576 | */ | |
3d0f8bc7 MW |
577 | static void ca91cx42_free_resource(struct vme_master_resource *image) |
578 | { | |
579 | iounmap(image->kern_base); | |
580 | image->kern_base = NULL; | |
8fafb476 MW |
581 | release_resource(&(image->bus_resource)); |
582 | kfree(image->bus_resource.name); | |
583 | memset(&(image->bus_resource), 0, sizeof(struct resource)); | |
3d0f8bc7 MW |
584 | } |
585 | ||
586 | ||
587 | int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |
588 | unsigned long long vme_base, unsigned long long size, | |
589 | vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) | |
590 | { | |
591 | int retval = 0; | |
21e0cf6d | 592 | unsigned int i, granularity = 0; |
3d0f8bc7 MW |
593 | unsigned int temp_ctl = 0; |
594 | unsigned long long pci_bound, vme_offset, pci_base; | |
48d9356e | 595 | struct vme_bridge *ca91cx42_bridge; |
29848ac9 MW |
596 | struct ca91cx42_driver *bridge; |
597 | ||
48d9356e MW |
598 | ca91cx42_bridge = image->parent; |
599 | ||
600 | bridge = ca91cx42_bridge->driver_priv; | |
3d0f8bc7 | 601 | |
21e0cf6d MW |
602 | i = image->number; |
603 | ||
604 | if ((i == 0) || (i == 4)) | |
605 | granularity = 0x1000; | |
606 | else | |
607 | granularity = 0x10000; | |
608 | ||
3d0f8bc7 | 609 | /* Verify input data */ |
21e0cf6d | 610 | if (vme_base & (granularity - 1)) { |
48d9356e MW |
611 | dev_err(ca91cx42_bridge->parent, "Invalid VME Window " |
612 | "alignment\n"); | |
3d0f8bc7 MW |
613 | retval = -EINVAL; |
614 | goto err_window; | |
615 | } | |
21e0cf6d | 616 | if (size & (granularity - 1)) { |
48d9356e MW |
617 | dev_err(ca91cx42_bridge->parent, "Invalid VME Window " |
618 | "alignment\n"); | |
3d0f8bc7 MW |
619 | retval = -EINVAL; |
620 | goto err_window; | |
621 | } | |
622 | ||
623 | spin_lock(&(image->lock)); | |
624 | ||
3d0f8bc7 MW |
625 | /* |
626 | * Let's allocate the resource here rather than further up the stack as | |
627 | * it avoids pushing loads of bus dependant stuff up the stack | |
628 | */ | |
629 | retval = ca91cx42_alloc_resource(image, size); | |
630 | if (retval) { | |
631 | spin_unlock(&(image->lock)); | |
48d9356e MW |
632 | dev_err(ca91cx42_bridge->parent, "Unable to allocate memory " |
633 | "for resource name\n"); | |
3d0f8bc7 MW |
634 | retval = -ENOMEM; |
635 | goto err_res; | |
636 | } | |
637 | ||
8fafb476 | 638 | pci_base = (unsigned long long)image->bus_resource.start; |
3d0f8bc7 MW |
639 | |
640 | /* | |
641 | * Bound address is a valid address for the window, adjust | |
642 | * according to window granularity. | |
643 | */ | |
21e0cf6d | 644 | pci_bound = pci_base + size; |
3d0f8bc7 MW |
645 | vme_offset = vme_base - pci_base; |
646 | ||
3d0f8bc7 | 647 | /* Disable while we are mucking around */ |
29848ac9 | 648 | temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); |
3d0f8bc7 | 649 | temp_ctl &= ~CA91CX42_LSI_CTL_EN; |
29848ac9 | 650 | iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); |
3d0f8bc7 | 651 | |
3d0f8bc7 MW |
652 | /* Setup cycle types */ |
653 | temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M; | |
654 | if (cycle & VME_BLT) | |
655 | temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT; | |
656 | if (cycle & VME_MBLT) | |
657 | temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT; | |
658 | ||
659 | /* Setup data width */ | |
660 | temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M; | |
661 | switch (dwidth) { | |
662 | case VME_D8: | |
663 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D8; | |
664 | break; | |
665 | case VME_D16: | |
666 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D16; | |
667 | break; | |
668 | case VME_D32: | |
669 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D32; | |
670 | break; | |
671 | case VME_D64: | |
672 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D64; | |
673 | break; | |
674 | default: | |
675 | spin_unlock(&(image->lock)); | |
48d9356e | 676 | dev_err(ca91cx42_bridge->parent, "Invalid data width\n"); |
3d0f8bc7 MW |
677 | retval = -EINVAL; |
678 | goto err_dwidth; | |
679 | break; | |
60479690 | 680 | } |
3d0f8bc7 MW |
681 | |
682 | /* Setup address space */ | |
683 | temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M; | |
684 | switch (aspace) { | |
60479690 | 685 | case VME_A16: |
3d0f8bc7 | 686 | temp_ctl |= CA91CX42_LSI_CTL_VAS_A16; |
60479690 MW |
687 | break; |
688 | case VME_A24: | |
3d0f8bc7 | 689 | temp_ctl |= CA91CX42_LSI_CTL_VAS_A24; |
60479690 MW |
690 | break; |
691 | case VME_A32: | |
3d0f8bc7 MW |
692 | temp_ctl |= CA91CX42_LSI_CTL_VAS_A32; |
693 | break; | |
694 | case VME_CRCSR: | |
695 | temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR; | |
60479690 MW |
696 | break; |
697 | case VME_USER1: | |
3d0f8bc7 | 698 | temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1; |
60479690 MW |
699 | break; |
700 | case VME_USER2: | |
3d0f8bc7 MW |
701 | temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2; |
702 | break; | |
703 | case VME_A64: | |
704 | case VME_USER3: | |
705 | case VME_USER4: | |
706 | default: | |
707 | spin_unlock(&(image->lock)); | |
48d9356e | 708 | dev_err(ca91cx42_bridge->parent, "Invalid address space\n"); |
3d0f8bc7 MW |
709 | retval = -EINVAL; |
710 | goto err_aspace; | |
60479690 MW |
711 | break; |
712 | } | |
713 | ||
3d0f8bc7 MW |
714 | temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M); |
715 | if (cycle & VME_SUPER) | |
716 | temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR; | |
717 | if (cycle & VME_PROG) | |
718 | temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM; | |
60479690 | 719 | |
3d0f8bc7 | 720 | /* Setup mapping */ |
29848ac9 MW |
721 | iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]); |
722 | iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]); | |
723 | iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]); | |
3d0f8bc7 MW |
724 | |
725 | /* Write ctl reg without enable */ | |
29848ac9 | 726 | iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); |
3d0f8bc7 MW |
727 | |
728 | if (enabled) | |
729 | temp_ctl |= CA91CX42_LSI_CTL_EN; | |
730 | ||
29848ac9 | 731 | iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); |
3d0f8bc7 MW |
732 | |
733 | spin_unlock(&(image->lock)); | |
734 | return 0; | |
735 | ||
736 | err_aspace: | |
737 | err_dwidth: | |
738 | ca91cx42_free_resource(image); | |
739 | err_res: | |
740 | err_window: | |
741 | return retval; | |
742 | } | |
743 | ||
744 | int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled, | |
745 | unsigned long long *vme_base, unsigned long long *size, | |
746 | vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) | |
747 | { | |
748 | unsigned int i, ctl; | |
749 | unsigned long long pci_base, pci_bound, vme_offset; | |
29848ac9 MW |
750 | struct ca91cx42_driver *bridge; |
751 | ||
752 | bridge = image->parent->driver_priv; | |
3d0f8bc7 MW |
753 | |
754 | i = image->number; | |
755 | ||
29848ac9 | 756 | ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); |
3d0f8bc7 | 757 | |
29848ac9 MW |
758 | pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]); |
759 | vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]); | |
760 | pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]); | |
3d0f8bc7 MW |
761 | |
762 | *vme_base = pci_base + vme_offset; | |
21e0cf6d | 763 | *size = (unsigned long long)(pci_bound - pci_base); |
3d0f8bc7 MW |
764 | |
765 | *enabled = 0; | |
766 | *aspace = 0; | |
767 | *cycle = 0; | |
768 | *dwidth = 0; | |
769 | ||
770 | if (ctl & CA91CX42_LSI_CTL_EN) | |
771 | *enabled = 1; | |
772 | ||
773 | /* Setup address space */ | |
774 | switch (ctl & CA91CX42_LSI_CTL_VAS_M) { | |
775 | case CA91CX42_LSI_CTL_VAS_A16: | |
776 | *aspace = VME_A16; | |
777 | break; | |
778 | case CA91CX42_LSI_CTL_VAS_A24: | |
779 | *aspace = VME_A24; | |
780 | break; | |
781 | case CA91CX42_LSI_CTL_VAS_A32: | |
782 | *aspace = VME_A32; | |
783 | break; | |
784 | case CA91CX42_LSI_CTL_VAS_CRCSR: | |
785 | *aspace = VME_CRCSR; | |
786 | break; | |
787 | case CA91CX42_LSI_CTL_VAS_USER1: | |
788 | *aspace = VME_USER1; | |
789 | break; | |
790 | case CA91CX42_LSI_CTL_VAS_USER2: | |
791 | *aspace = VME_USER2; | |
792 | break; | |
793 | } | |
794 | ||
795 | /* XXX Not sure howto check for MBLT */ | |
796 | /* Setup cycle types */ | |
797 | if (ctl & CA91CX42_LSI_CTL_VCT_BLT) | |
798 | *cycle |= VME_BLT; | |
799 | else | |
800 | *cycle |= VME_SCT; | |
801 | ||
802 | if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR) | |
803 | *cycle |= VME_SUPER; | |
804 | else | |
805 | *cycle |= VME_USER; | |
806 | ||
807 | if (ctl & CA91CX42_LSI_CTL_PGM_PGM) | |
808 | *cycle = VME_PROG; | |
809 | else | |
810 | *cycle = VME_DATA; | |
811 | ||
812 | /* Setup data width */ | |
813 | switch (ctl & CA91CX42_LSI_CTL_VDW_M) { | |
814 | case CA91CX42_LSI_CTL_VDW_D8: | |
815 | *dwidth = VME_D8; | |
816 | break; | |
817 | case CA91CX42_LSI_CTL_VDW_D16: | |
818 | *dwidth = VME_D16; | |
819 | break; | |
820 | case CA91CX42_LSI_CTL_VDW_D32: | |
821 | *dwidth = VME_D32; | |
822 | break; | |
823 | case CA91CX42_LSI_CTL_VDW_D64: | |
824 | *dwidth = VME_D64; | |
825 | break; | |
826 | } | |
827 | ||
3d0f8bc7 MW |
828 | return 0; |
829 | } | |
830 | ||
831 | int ca91cx42_master_get(struct vme_master_resource *image, int *enabled, | |
832 | unsigned long long *vme_base, unsigned long long *size, | |
833 | vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) | |
834 | { | |
835 | int retval; | |
836 | ||
837 | spin_lock(&(image->lock)); | |
838 | ||
839 | retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace, | |
840 | cycle, dwidth); | |
841 | ||
842 | spin_unlock(&(image->lock)); | |
843 | ||
844 | return retval; | |
845 | } | |
846 | ||
847 | ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf, | |
848 | size_t count, loff_t offset) | |
849 | { | |
21e0cf6d | 850 | ssize_t retval; |
60479690 | 851 | |
3d0f8bc7 | 852 | spin_lock(&(image->lock)); |
60479690 | 853 | |
3d0f8bc7 MW |
854 | memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count); |
855 | retval = count; | |
60479690 | 856 | |
3d0f8bc7 MW |
857 | spin_unlock(&(image->lock)); |
858 | ||
859 | return retval; | |
60479690 MW |
860 | } |
861 | ||
3d0f8bc7 MW |
862 | ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf, |
863 | size_t count, loff_t offset) | |
60479690 | 864 | { |
3d0f8bc7 | 865 | int retval = 0; |
60479690 | 866 | |
3d0f8bc7 | 867 | spin_lock(&(image->lock)); |
60479690 | 868 | |
3d0f8bc7 MW |
869 | memcpy_toio(image->kern_base + offset, buf, (unsigned int)count); |
870 | retval = count; | |
871 | ||
872 | spin_unlock(&(image->lock)); | |
873 | ||
874 | return retval; | |
60479690 MW |
875 | } |
876 | ||
04e10e15 MW |
877 | unsigned int ca91cx42_master_rmw(struct vme_master_resource *image, |
878 | unsigned int mask, unsigned int compare, unsigned int swap, | |
879 | loff_t offset) | |
880 | { | |
881 | u32 pci_addr, result; | |
882 | int i; | |
883 | struct ca91cx42_driver *bridge; | |
884 | struct device *dev; | |
885 | ||
886 | bridge = image->parent->driver_priv; | |
887 | dev = image->parent->parent; | |
888 | ||
889 | /* Find the PCI address that maps to the desired VME address */ | |
890 | i = image->number; | |
891 | ||
892 | /* Locking as we can only do one of these at a time */ | |
893 | mutex_lock(&(bridge->vme_rmw)); | |
894 | ||
895 | /* Lock image */ | |
896 | spin_lock(&(image->lock)); | |
897 | ||
898 | pci_addr = (u32)image->kern_base + offset; | |
899 | ||
900 | /* Address must be 4-byte aligned */ | |
901 | if (pci_addr & 0x3) { | |
902 | dev_err(dev, "RMW Address not 4-byte aligned\n"); | |
7c0ace54 JL |
903 | result = -EINVAL; |
904 | goto out; | |
04e10e15 MW |
905 | } |
906 | ||
907 | /* Ensure RMW Disabled whilst configuring */ | |
908 | iowrite32(0, bridge->base + SCYC_CTL); | |
909 | ||
910 | /* Configure registers */ | |
911 | iowrite32(mask, bridge->base + SCYC_EN); | |
912 | iowrite32(compare, bridge->base + SCYC_CMP); | |
913 | iowrite32(swap, bridge->base + SCYC_SWP); | |
914 | iowrite32(pci_addr, bridge->base + SCYC_ADDR); | |
915 | ||
916 | /* Enable RMW */ | |
917 | iowrite32(CA91CX42_SCYC_CTL_CYC_RMW, bridge->base + SCYC_CTL); | |
918 | ||
919 | /* Kick process off with a read to the required address. */ | |
920 | result = ioread32(image->kern_base + offset); | |
921 | ||
922 | /* Disable RMW */ | |
923 | iowrite32(0, bridge->base + SCYC_CTL); | |
924 | ||
7c0ace54 | 925 | out: |
04e10e15 MW |
926 | spin_unlock(&(image->lock)); |
927 | ||
928 | mutex_unlock(&(bridge->vme_rmw)); | |
929 | ||
930 | return result; | |
931 | } | |
932 | ||
4860ab74 MW |
933 | int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, |
934 | struct vme_dma_attr *dest, size_t count) | |
935 | { | |
936 | struct ca91cx42_dma_entry *entry, *prev; | |
937 | struct vme_dma_pci *pci_attr; | |
938 | struct vme_dma_vme *vme_attr; | |
939 | dma_addr_t desc_ptr; | |
940 | int retval = 0; | |
48d9356e MW |
941 | struct device *dev; |
942 | ||
943 | dev = list->parent->parent->parent; | |
4860ab74 MW |
944 | |
945 | /* XXX descriptor must be aligned on 64-bit boundaries */ | |
32414878 | 946 | entry = kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL); |
4860ab74 | 947 | if (entry == NULL) { |
48d9356e | 948 | dev_err(dev, "Failed to allocate memory for dma resource " |
4860ab74 MW |
949 | "structure\n"); |
950 | retval = -ENOMEM; | |
951 | goto err_mem; | |
952 | } | |
953 | ||
954 | /* Test descriptor alignment */ | |
955 | if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) { | |
48d9356e | 956 | dev_err(dev, "Descriptor not aligned to 16 byte boundary as " |
4860ab74 MW |
957 | "required: %p\n", &(entry->descriptor)); |
958 | retval = -EINVAL; | |
959 | goto err_align; | |
960 | } | |
961 | ||
962 | memset(&(entry->descriptor), 0, sizeof(struct ca91cx42_dma_descriptor)); | |
963 | ||
964 | if (dest->type == VME_DMA_VME) { | |
965 | entry->descriptor.dctl |= CA91CX42_DCTL_L2V; | |
feffce47 KV |
966 | vme_attr = dest->private; |
967 | pci_attr = src->private; | |
4860ab74 | 968 | } else { |
feffce47 KV |
969 | vme_attr = src->private; |
970 | pci_attr = dest->private; | |
4860ab74 MW |
971 | } |
972 | ||
973 | /* Check we can do fullfill required attributes */ | |
974 | if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 | | |
975 | VME_USER2)) != 0) { | |
976 | ||
48d9356e | 977 | dev_err(dev, "Unsupported cycle type\n"); |
4860ab74 MW |
978 | retval = -EINVAL; |
979 | goto err_aspace; | |
980 | } | |
981 | ||
982 | if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER | | |
983 | VME_PROG | VME_DATA)) != 0) { | |
984 | ||
48d9356e | 985 | dev_err(dev, "Unsupported cycle type\n"); |
4860ab74 MW |
986 | retval = -EINVAL; |
987 | goto err_cycle; | |
988 | } | |
989 | ||
990 | /* Check to see if we can fullfill source and destination */ | |
991 | if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) || | |
992 | ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) { | |
993 | ||
48d9356e | 994 | dev_err(dev, "Cannot perform transfer with this " |
4860ab74 MW |
995 | "source-destination combination\n"); |
996 | retval = -EINVAL; | |
997 | goto err_direct; | |
998 | } | |
999 | ||
1000 | /* Setup cycle types */ | |
1001 | if (vme_attr->cycle & VME_BLT) | |
1002 | entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT; | |
1003 | ||
1004 | /* Setup data width */ | |
1005 | switch (vme_attr->dwidth) { | |
1006 | case VME_D8: | |
1007 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8; | |
1008 | break; | |
1009 | case VME_D16: | |
1010 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16; | |
1011 | break; | |
1012 | case VME_D32: | |
1013 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32; | |
1014 | break; | |
1015 | case VME_D64: | |
1016 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64; | |
1017 | break; | |
1018 | default: | |
48d9356e | 1019 | dev_err(dev, "Invalid data width\n"); |
4860ab74 MW |
1020 | return -EINVAL; |
1021 | } | |
1022 | ||
1023 | /* Setup address space */ | |
1024 | switch (vme_attr->aspace) { | |
1025 | case VME_A16: | |
1026 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16; | |
1027 | break; | |
1028 | case VME_A24: | |
1029 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24; | |
1030 | break; | |
1031 | case VME_A32: | |
1032 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32; | |
1033 | break; | |
1034 | case VME_USER1: | |
1035 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1; | |
1036 | break; | |
1037 | case VME_USER2: | |
1038 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2; | |
1039 | break; | |
1040 | default: | |
48d9356e | 1041 | dev_err(dev, "Invalid address space\n"); |
4860ab74 MW |
1042 | return -EINVAL; |
1043 | break; | |
1044 | } | |
1045 | ||
1046 | if (vme_attr->cycle & VME_SUPER) | |
1047 | entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR; | |
1048 | if (vme_attr->cycle & VME_PROG) | |
1049 | entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM; | |
1050 | ||
1051 | entry->descriptor.dtbc = count; | |
1052 | entry->descriptor.dla = pci_attr->address; | |
1053 | entry->descriptor.dva = vme_attr->address; | |
1054 | entry->descriptor.dcpp = CA91CX42_DCPP_NULL; | |
1055 | ||
1056 | /* Add to list */ | |
1057 | list_add_tail(&(entry->list), &(list->entries)); | |
1058 | ||
1059 | /* Fill out previous descriptors "Next Address" */ | |
1060 | if (entry->list.prev != &(list->entries)) { | |
1061 | prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry, | |
1062 | list); | |
1063 | /* We need the bus address for the pointer */ | |
1064 | desc_ptr = virt_to_bus(&(entry->descriptor)); | |
1065 | prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M; | |
1066 | } | |
1067 | ||
1068 | return 0; | |
1069 | ||
1070 | err_cycle: | |
1071 | err_aspace: | |
1072 | err_direct: | |
1073 | err_align: | |
1074 | kfree(entry); | |
1075 | err_mem: | |
1076 | return retval; | |
1077 | } | |
1078 | ||
1079 | static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge) | |
1080 | { | |
1081 | u32 tmp; | |
1082 | struct ca91cx42_driver *bridge; | |
1083 | ||
1084 | bridge = ca91cx42_bridge->driver_priv; | |
1085 | ||
1086 | tmp = ioread32(bridge->base + DGCS); | |
1087 | ||
1088 | if (tmp & CA91CX42_DGCS_ACT) | |
1089 | return 0; | |
1090 | else | |
1091 | return 1; | |
1092 | } | |
1093 | ||
1094 | int ca91cx42_dma_list_exec(struct vme_dma_list *list) | |
1095 | { | |
1096 | struct vme_dma_resource *ctrlr; | |
1097 | struct ca91cx42_dma_entry *entry; | |
1098 | int retval = 0; | |
1099 | dma_addr_t bus_addr; | |
1100 | u32 val; | |
48d9356e | 1101 | struct device *dev; |
4860ab74 MW |
1102 | struct ca91cx42_driver *bridge; |
1103 | ||
1104 | ctrlr = list->parent; | |
1105 | ||
1106 | bridge = ctrlr->parent->driver_priv; | |
48d9356e | 1107 | dev = ctrlr->parent->parent; |
4860ab74 MW |
1108 | |
1109 | mutex_lock(&(ctrlr->mtx)); | |
1110 | ||
1111 | if (!(list_empty(&(ctrlr->running)))) { | |
1112 | /* | |
1113 | * XXX We have an active DMA transfer and currently haven't | |
1114 | * sorted out the mechanism for "pending" DMA transfers. | |
1115 | * Return busy. | |
1116 | */ | |
1117 | /* Need to add to pending here */ | |
1118 | mutex_unlock(&(ctrlr->mtx)); | |
1119 | return -EBUSY; | |
1120 | } else { | |
1121 | list_add(&(list->list), &(ctrlr->running)); | |
1122 | } | |
1123 | ||
1124 | /* Get first bus address and write into registers */ | |
1125 | entry = list_first_entry(&(list->entries), struct ca91cx42_dma_entry, | |
1126 | list); | |
1127 | ||
1128 | bus_addr = virt_to_bus(&(entry->descriptor)); | |
1129 | ||
1130 | mutex_unlock(&(ctrlr->mtx)); | |
1131 | ||
1132 | iowrite32(0, bridge->base + DTBC); | |
1133 | iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); | |
1134 | ||
1135 | /* Start the operation */ | |
1136 | val = ioread32(bridge->base + DGCS); | |
1137 | ||
1138 | /* XXX Could set VMEbus On and Off Counters here */ | |
1139 | val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M); | |
1140 | ||
1141 | val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT | | |
1142 | CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR | | |
1143 | CA91CX42_DGCS_PERR); | |
1144 | ||
1145 | iowrite32(val, bridge->base + DGCS); | |
1146 | ||
1147 | val |= CA91CX42_DGCS_GO; | |
1148 | ||
1149 | iowrite32(val, bridge->base + DGCS); | |
1150 | ||
1151 | wait_event_interruptible(bridge->dma_queue, | |
1152 | ca91cx42_dma_busy(ctrlr->parent)); | |
1153 | ||
1154 | /* | |
1155 | * Read status register, this register is valid until we kick off a | |
1156 | * new transfer. | |
1157 | */ | |
1158 | val = ioread32(bridge->base + DGCS); | |
1159 | ||
1160 | if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR | | |
1161 | CA91CX42_DGCS_PERR)) { | |
1162 | ||
48d9356e | 1163 | dev_err(dev, "ca91c042: DMA Error. DGCS=%08X\n", val); |
4860ab74 MW |
1164 | val = ioread32(bridge->base + DCTL); |
1165 | } | |
1166 | ||
1167 | /* Remove list from running list */ | |
1168 | mutex_lock(&(ctrlr->mtx)); | |
1169 | list_del(&(list->list)); | |
1170 | mutex_unlock(&(ctrlr->mtx)); | |
1171 | ||
1172 | return retval; | |
1173 | ||
1174 | } | |
1175 | ||
1176 | int ca91cx42_dma_list_empty(struct vme_dma_list *list) | |
1177 | { | |
1178 | struct list_head *pos, *temp; | |
1179 | struct ca91cx42_dma_entry *entry; | |
1180 | ||
1181 | /* detach and free each entry */ | |
1182 | list_for_each_safe(pos, temp, &(list->entries)) { | |
1183 | list_del(pos); | |
1184 | entry = list_entry(pos, struct ca91cx42_dma_entry, list); | |
1185 | kfree(entry); | |
1186 | } | |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
2b82beb8 MW |
1191 | /* |
1192 | * All 4 location monitors reside at the same base - this is therefore a | |
1193 | * system wide configuration. | |
1194 | * | |
1195 | * This does not enable the LM monitor - that should be done when the first | |
1196 | * callback is attached and disabled when the last callback is removed. | |
1197 | */ | |
1198 | int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, | |
1199 | vme_address_t aspace, vme_cycle_t cycle) | |
1200 | { | |
1201 | u32 temp_base, lm_ctl = 0; | |
1202 | int i; | |
1203 | struct ca91cx42_driver *bridge; | |
1204 | struct device *dev; | |
1205 | ||
1206 | bridge = lm->parent->driver_priv; | |
1207 | dev = lm->parent->parent; | |
1208 | ||
1209 | /* Check the alignment of the location monitor */ | |
1210 | temp_base = (u32)lm_base; | |
1211 | if (temp_base & 0xffff) { | |
1212 | dev_err(dev, "Location monitor must be aligned to 64KB " | |
1213 | "boundary"); | |
1214 | return -EINVAL; | |
1215 | } | |
1216 | ||
1217 | mutex_lock(&(lm->mtx)); | |
1218 | ||
1219 | /* If we already have a callback attached, we can't move it! */ | |
1220 | for (i = 0; i < lm->monitors; i++) { | |
1221 | if (bridge->lm_callback[i] != NULL) { | |
1222 | mutex_unlock(&(lm->mtx)); | |
1223 | dev_err(dev, "Location monitor callback attached, " | |
1224 | "can't reset\n"); | |
1225 | return -EBUSY; | |
1226 | } | |
1227 | } | |
1228 | ||
1229 | switch (aspace) { | |
1230 | case VME_A16: | |
1231 | lm_ctl |= CA91CX42_LM_CTL_AS_A16; | |
1232 | break; | |
1233 | case VME_A24: | |
1234 | lm_ctl |= CA91CX42_LM_CTL_AS_A24; | |
1235 | break; | |
1236 | case VME_A32: | |
1237 | lm_ctl |= CA91CX42_LM_CTL_AS_A32; | |
1238 | break; | |
1239 | default: | |
1240 | mutex_unlock(&(lm->mtx)); | |
1241 | dev_err(dev, "Invalid address space\n"); | |
1242 | return -EINVAL; | |
1243 | break; | |
1244 | } | |
1245 | ||
1246 | if (cycle & VME_SUPER) | |
1247 | lm_ctl |= CA91CX42_LM_CTL_SUPR; | |
1248 | if (cycle & VME_USER) | |
1249 | lm_ctl |= CA91CX42_LM_CTL_NPRIV; | |
1250 | if (cycle & VME_PROG) | |
1251 | lm_ctl |= CA91CX42_LM_CTL_PGM; | |
1252 | if (cycle & VME_DATA) | |
1253 | lm_ctl |= CA91CX42_LM_CTL_DATA; | |
1254 | ||
1255 | iowrite32(lm_base, bridge->base + LM_BS); | |
1256 | iowrite32(lm_ctl, bridge->base + LM_CTL); | |
1257 | ||
1258 | mutex_unlock(&(lm->mtx)); | |
1259 | ||
1260 | return 0; | |
1261 | } | |
1262 | ||
1263 | /* Get configuration of the callback monitor and return whether it is enabled | |
1264 | * or disabled. | |
1265 | */ | |
1266 | int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base, | |
1267 | vme_address_t *aspace, vme_cycle_t *cycle) | |
1268 | { | |
1269 | u32 lm_ctl, enabled = 0; | |
1270 | struct ca91cx42_driver *bridge; | |
1271 | ||
1272 | bridge = lm->parent->driver_priv; | |
1273 | ||
1274 | mutex_lock(&(lm->mtx)); | |
1275 | ||
1276 | *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); | |
1277 | lm_ctl = ioread32(bridge->base + LM_CTL); | |
1278 | ||
1279 | if (lm_ctl & CA91CX42_LM_CTL_EN) | |
1280 | enabled = 1; | |
1281 | ||
1282 | if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16) | |
1283 | *aspace = VME_A16; | |
1284 | if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24) | |
1285 | *aspace = VME_A24; | |
1286 | if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32) | |
1287 | *aspace = VME_A32; | |
1288 | ||
1289 | *cycle = 0; | |
1290 | if (lm_ctl & CA91CX42_LM_CTL_SUPR) | |
1291 | *cycle |= VME_SUPER; | |
1292 | if (lm_ctl & CA91CX42_LM_CTL_NPRIV) | |
1293 | *cycle |= VME_USER; | |
1294 | if (lm_ctl & CA91CX42_LM_CTL_PGM) | |
1295 | *cycle |= VME_PROG; | |
1296 | if (lm_ctl & CA91CX42_LM_CTL_DATA) | |
1297 | *cycle |= VME_DATA; | |
1298 | ||
1299 | mutex_unlock(&(lm->mtx)); | |
1300 | ||
1301 | return enabled; | |
1302 | } | |
1303 | ||
1304 | /* | |
1305 | * Attach a callback to a specific location monitor. | |
1306 | * | |
1307 | * Callback will be passed the monitor triggered. | |
1308 | */ | |
1309 | int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor, | |
1310 | void (*callback)(int)) | |
1311 | { | |
1312 | u32 lm_ctl, tmp; | |
1313 | struct ca91cx42_driver *bridge; | |
1314 | struct device *dev; | |
1315 | ||
1316 | bridge = lm->parent->driver_priv; | |
1317 | dev = lm->parent->parent; | |
1318 | ||
1319 | mutex_lock(&(lm->mtx)); | |
1320 | ||
1321 | /* Ensure that the location monitor is configured - need PGM or DATA */ | |
1322 | lm_ctl = ioread32(bridge->base + LM_CTL); | |
1323 | if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) { | |
1324 | mutex_unlock(&(lm->mtx)); | |
1325 | dev_err(dev, "Location monitor not properly configured\n"); | |
1326 | return -EINVAL; | |
1327 | } | |
1328 | ||
1329 | /* Check that a callback isn't already attached */ | |
1330 | if (bridge->lm_callback[monitor] != NULL) { | |
1331 | mutex_unlock(&(lm->mtx)); | |
1332 | dev_err(dev, "Existing callback attached\n"); | |
1333 | return -EBUSY; | |
1334 | } | |
1335 | ||
1336 | /* Attach callback */ | |
1337 | bridge->lm_callback[monitor] = callback; | |
1338 | ||
1339 | /* Enable Location Monitor interrupt */ | |
1340 | tmp = ioread32(bridge->base + LINT_EN); | |
1341 | tmp |= CA91CX42_LINT_LM[monitor]; | |
1342 | iowrite32(tmp, bridge->base + LINT_EN); | |
1343 | ||
1344 | /* Ensure that global Location Monitor Enable set */ | |
1345 | if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) { | |
1346 | lm_ctl |= CA91CX42_LM_CTL_EN; | |
1347 | iowrite32(lm_ctl, bridge->base + LM_CTL); | |
1348 | } | |
1349 | ||
1350 | mutex_unlock(&(lm->mtx)); | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
1355 | /* | |
1356 | * Detach a callback function forn a specific location monitor. | |
1357 | */ | |
1358 | int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor) | |
1359 | { | |
1360 | u32 tmp; | |
1361 | struct ca91cx42_driver *bridge; | |
1362 | ||
1363 | bridge = lm->parent->driver_priv; | |
1364 | ||
1365 | mutex_lock(&(lm->mtx)); | |
1366 | ||
1367 | /* Disable Location Monitor and ensure previous interrupts are clear */ | |
1368 | tmp = ioread32(bridge->base + LINT_EN); | |
1369 | tmp &= ~CA91CX42_LINT_LM[monitor]; | |
1370 | iowrite32(tmp, bridge->base + LINT_EN); | |
1371 | ||
1372 | iowrite32(CA91CX42_LINT_LM[monitor], | |
1373 | bridge->base + LINT_STAT); | |
1374 | ||
1375 | /* Detach callback */ | |
1376 | bridge->lm_callback[monitor] = NULL; | |
1377 | ||
1378 | /* If all location monitors disabled, disable global Location Monitor */ | |
1379 | if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 | | |
1380 | CA91CX42_LINT_LM3)) == 0) { | |
1381 | tmp = ioread32(bridge->base + LM_CTL); | |
1382 | tmp &= ~CA91CX42_LM_CTL_EN; | |
1383 | iowrite32(tmp, bridge->base + LM_CTL); | |
1384 | } | |
1385 | ||
1386 | mutex_unlock(&(lm->mtx)); | |
1387 | ||
1388 | return 0; | |
1389 | } | |
1390 | ||
29848ac9 | 1391 | int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge) |
60479690 | 1392 | { |
3d0f8bc7 | 1393 | u32 slot = 0; |
29848ac9 MW |
1394 | struct ca91cx42_driver *bridge; |
1395 | ||
1396 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 1397 | |
12b2d5c0 | 1398 | if (!geoid) { |
29848ac9 | 1399 | slot = ioread32(bridge->base + VCSR_BS); |
12b2d5c0 MW |
1400 | slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27); |
1401 | } else | |
1402 | slot = geoid; | |
1403 | ||
3d0f8bc7 MW |
1404 | return (int)slot; |
1405 | ||
1406 | } | |
1407 | ||
1408 | static int __init ca91cx42_init(void) | |
1409 | { | |
1410 | return pci_register_driver(&ca91cx42_driver); | |
1411 | } | |
1412 | ||
1413 | /* | |
1414 | * Configure CR/CSR space | |
1415 | * | |
1416 | * Access to the CR/CSR can be configured at power-up. The location of the | |
1417 | * CR/CSR registers in the CR/CSR address space is determined by the boards | |
1418 | * Auto-ID or Geographic address. This function ensures that the window is | |
1419 | * enabled at an offset consistent with the boards geopgraphic address. | |
1420 | */ | |
29848ac9 MW |
1421 | static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge, |
1422 | struct pci_dev *pdev) | |
3d0f8bc7 MW |
1423 | { |
1424 | unsigned int crcsr_addr; | |
1425 | int tmp, slot; | |
29848ac9 MW |
1426 | struct ca91cx42_driver *bridge; |
1427 | ||
1428 | bridge = ca91cx42_bridge->driver_priv; | |
3d0f8bc7 | 1429 | |
29848ac9 | 1430 | slot = ca91cx42_slot_get(ca91cx42_bridge); |
25331ba2 MW |
1431 | |
1432 | /* Write CSR Base Address if slot ID is supplied as a module param */ | |
1433 | if (geoid) | |
1434 | iowrite32(geoid << 27, bridge->base + VCSR_BS); | |
1435 | ||
3d0f8bc7 MW |
1436 | dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot); |
1437 | if (slot == 0) { | |
1438 | dev_err(&pdev->dev, "Slot number is unset, not configuring " | |
1439 | "CR/CSR space\n"); | |
1440 | return -EINVAL; | |
60479690 | 1441 | } |
3d0f8bc7 MW |
1442 | |
1443 | /* Allocate mem for CR/CSR image */ | |
29848ac9 MW |
1444 | bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, |
1445 | &(bridge->crcsr_bus)); | |
1446 | if (bridge->crcsr_kernel == NULL) { | |
3d0f8bc7 MW |
1447 | dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR " |
1448 | "image\n"); | |
1449 | return -ENOMEM; | |
60479690 MW |
1450 | } |
1451 | ||
29848ac9 | 1452 | memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE); |
60479690 | 1453 | |
3d0f8bc7 | 1454 | crcsr_addr = slot * (512 * 1024); |
29848ac9 | 1455 | iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO); |
60479690 | 1456 | |
29848ac9 | 1457 | tmp = ioread32(bridge->base + VCSR_CTL); |
3d0f8bc7 | 1458 | tmp |= CA91CX42_VCSR_CTL_EN; |
29848ac9 | 1459 | iowrite32(tmp, bridge->base + VCSR_CTL); |
60479690 | 1460 | |
3d0f8bc7 | 1461 | return 0; |
60479690 MW |
1462 | } |
1463 | ||
29848ac9 MW |
1464 | static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge, |
1465 | struct pci_dev *pdev) | |
60479690 | 1466 | { |
3d0f8bc7 | 1467 | u32 tmp; |
29848ac9 MW |
1468 | struct ca91cx42_driver *bridge; |
1469 | ||
1470 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 1471 | |
3d0f8bc7 | 1472 | /* Turn off CR/CSR space */ |
29848ac9 | 1473 | tmp = ioread32(bridge->base + VCSR_CTL); |
3d0f8bc7 | 1474 | tmp &= ~CA91CX42_VCSR_CTL_EN; |
29848ac9 | 1475 | iowrite32(tmp, bridge->base + VCSR_CTL); |
60479690 | 1476 | |
3d0f8bc7 | 1477 | /* Free image */ |
29848ac9 | 1478 | iowrite32(0, bridge->base + VCSR_TO); |
60479690 | 1479 | |
29848ac9 MW |
1480 | pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, |
1481 | bridge->crcsr_bus); | |
3d0f8bc7 | 1482 | } |
60479690 | 1483 | |
3d0f8bc7 MW |
1484 | static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
1485 | { | |
1486 | int retval, i; | |
1487 | u32 data; | |
1488 | struct list_head *pos = NULL; | |
29848ac9 MW |
1489 | struct vme_bridge *ca91cx42_bridge; |
1490 | struct ca91cx42_driver *ca91cx42_device; | |
3d0f8bc7 MW |
1491 | struct vme_master_resource *master_image; |
1492 | struct vme_slave_resource *slave_image; | |
3d0f8bc7 | 1493 | struct vme_dma_resource *dma_ctrlr; |
3d0f8bc7 MW |
1494 | struct vme_lm_resource *lm; |
1495 | ||
1496 | /* We want to support more than one of each bridge so we need to | |
1497 | * dynamically allocate the bridge structure | |
1498 | */ | |
7a6cb0d5 | 1499 | ca91cx42_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL); |
3d0f8bc7 MW |
1500 | |
1501 | if (ca91cx42_bridge == NULL) { | |
1502 | dev_err(&pdev->dev, "Failed to allocate memory for device " | |
1503 | "structure\n"); | |
1504 | retval = -ENOMEM; | |
1505 | goto err_struct; | |
1506 | } | |
1507 | ||
7a6cb0d5 | 1508 | ca91cx42_device = kzalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL); |
29848ac9 MW |
1509 | |
1510 | if (ca91cx42_device == NULL) { | |
1511 | dev_err(&pdev->dev, "Failed to allocate memory for device " | |
1512 | "structure\n"); | |
1513 | retval = -ENOMEM; | |
1514 | goto err_driver; | |
1515 | } | |
1516 | ||
29848ac9 MW |
1517 | ca91cx42_bridge->driver_priv = ca91cx42_device; |
1518 | ||
3d0f8bc7 MW |
1519 | /* Enable the device */ |
1520 | retval = pci_enable_device(pdev); | |
1521 | if (retval) { | |
1522 | dev_err(&pdev->dev, "Unable to enable device\n"); | |
1523 | goto err_enable; | |
1524 | } | |
1525 | ||
1526 | /* Map Registers */ | |
1527 | retval = pci_request_regions(pdev, driver_name); | |
1528 | if (retval) { | |
1529 | dev_err(&pdev->dev, "Unable to reserve resources\n"); | |
1530 | goto err_resource; | |
1531 | } | |
1532 | ||
1533 | /* map registers in BAR 0 */ | |
29848ac9 | 1534 | ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0), |
3d0f8bc7 | 1535 | 4096); |
29848ac9 | 1536 | if (!ca91cx42_device->base) { |
3d0f8bc7 MW |
1537 | dev_err(&pdev->dev, "Unable to remap CRG region\n"); |
1538 | retval = -EIO; | |
1539 | goto err_remap; | |
1540 | } | |
1541 | ||
1542 | /* Check to see if the mapping worked out */ | |
29848ac9 | 1543 | data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF; |
3d0f8bc7 MW |
1544 | if (data != PCI_VENDOR_ID_TUNDRA) { |
1545 | dev_err(&pdev->dev, "PCI_ID check failed\n"); | |
1546 | retval = -EIO; | |
1547 | goto err_test; | |
1548 | } | |
1549 | ||
1550 | /* Initialize wait queues & mutual exclusion flags */ | |
29848ac9 MW |
1551 | init_waitqueue_head(&(ca91cx42_device->dma_queue)); |
1552 | init_waitqueue_head(&(ca91cx42_device->iack_queue)); | |
1553 | mutex_init(&(ca91cx42_device->vme_int)); | |
1554 | mutex_init(&(ca91cx42_device->vme_rmw)); | |
3d0f8bc7 MW |
1555 | |
1556 | ca91cx42_bridge->parent = &(pdev->dev); | |
1557 | strcpy(ca91cx42_bridge->name, driver_name); | |
1558 | ||
1559 | /* Setup IRQ */ | |
1560 | retval = ca91cx42_irq_init(ca91cx42_bridge); | |
1561 | if (retval != 0) { | |
1562 | dev_err(&pdev->dev, "Chip Initialization failed.\n"); | |
1563 | goto err_irq; | |
1564 | } | |
1565 | ||
1566 | /* Add master windows to list */ | |
1567 | INIT_LIST_HEAD(&(ca91cx42_bridge->master_resources)); | |
1568 | for (i = 0; i < CA91C142_MAX_MASTER; i++) { | |
1569 | master_image = kmalloc(sizeof(struct vme_master_resource), | |
1570 | GFP_KERNEL); | |
1571 | if (master_image == NULL) { | |
1572 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
1573 | "master resource structure\n"); | |
1574 | retval = -ENOMEM; | |
1575 | goto err_master; | |
1576 | } | |
1577 | master_image->parent = ca91cx42_bridge; | |
1578 | spin_lock_init(&(master_image->lock)); | |
1579 | master_image->locked = 0; | |
1580 | master_image->number = i; | |
1581 | master_image->address_attr = VME_A16 | VME_A24 | VME_A32 | | |
1582 | VME_CRCSR | VME_USER1 | VME_USER2; | |
1583 | master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | | |
1584 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; | |
1585 | master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64; | |
8fafb476 | 1586 | memset(&(master_image->bus_resource), 0, |
3d0f8bc7 MW |
1587 | sizeof(struct resource)); |
1588 | master_image->kern_base = NULL; | |
1589 | list_add_tail(&(master_image->list), | |
1590 | &(ca91cx42_bridge->master_resources)); | |
1591 | } | |
1592 | ||
1593 | /* Add slave windows to list */ | |
1594 | INIT_LIST_HEAD(&(ca91cx42_bridge->slave_resources)); | |
1595 | for (i = 0; i < CA91C142_MAX_SLAVE; i++) { | |
1596 | slave_image = kmalloc(sizeof(struct vme_slave_resource), | |
1597 | GFP_KERNEL); | |
1598 | if (slave_image == NULL) { | |
1599 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
1600 | "slave resource structure\n"); | |
1601 | retval = -ENOMEM; | |
1602 | goto err_slave; | |
1603 | } | |
1604 | slave_image->parent = ca91cx42_bridge; | |
1605 | mutex_init(&(slave_image->mtx)); | |
1606 | slave_image->locked = 0; | |
1607 | slave_image->number = i; | |
1608 | slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 | | |
1609 | VME_USER2; | |
1610 | ||
1611 | /* Only windows 0 and 4 support A16 */ | |
1612 | if (i == 0 || i == 4) | |
1613 | slave_image->address_attr |= VME_A16; | |
1614 | ||
1615 | slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | | |
1616 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; | |
1617 | list_add_tail(&(slave_image->list), | |
1618 | &(ca91cx42_bridge->slave_resources)); | |
1619 | } | |
4860ab74 | 1620 | |
3d0f8bc7 MW |
1621 | /* Add dma engines to list */ |
1622 | INIT_LIST_HEAD(&(ca91cx42_bridge->dma_resources)); | |
1623 | for (i = 0; i < CA91C142_MAX_DMA; i++) { | |
1624 | dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource), | |
1625 | GFP_KERNEL); | |
1626 | if (dma_ctrlr == NULL) { | |
1627 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
1628 | "dma resource structure\n"); | |
1629 | retval = -ENOMEM; | |
1630 | goto err_dma; | |
1631 | } | |
1632 | dma_ctrlr->parent = ca91cx42_bridge; | |
1633 | mutex_init(&(dma_ctrlr->mtx)); | |
1634 | dma_ctrlr->locked = 0; | |
1635 | dma_ctrlr->number = i; | |
4f723df4 MW |
1636 | dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | |
1637 | VME_DMA_MEM_TO_VME; | |
3d0f8bc7 MW |
1638 | INIT_LIST_HEAD(&(dma_ctrlr->pending)); |
1639 | INIT_LIST_HEAD(&(dma_ctrlr->running)); | |
1640 | list_add_tail(&(dma_ctrlr->list), | |
1641 | &(ca91cx42_bridge->dma_resources)); | |
1642 | } | |
4860ab74 | 1643 | |
3d0f8bc7 MW |
1644 | /* Add location monitor to list */ |
1645 | INIT_LIST_HEAD(&(ca91cx42_bridge->lm_resources)); | |
1646 | lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL); | |
1647 | if (lm == NULL) { | |
1648 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
1649 | "location monitor resource structure\n"); | |
1650 | retval = -ENOMEM; | |
1651 | goto err_lm; | |
1652 | } | |
1653 | lm->parent = ca91cx42_bridge; | |
1654 | mutex_init(&(lm->mtx)); | |
1655 | lm->locked = 0; | |
1656 | lm->number = 1; | |
1657 | lm->monitors = 4; | |
1658 | list_add_tail(&(lm->list), &(ca91cx42_bridge->lm_resources)); | |
1659 | ||
1660 | ca91cx42_bridge->slave_get = ca91cx42_slave_get; | |
1661 | ca91cx42_bridge->slave_set = ca91cx42_slave_set; | |
1662 | ca91cx42_bridge->master_get = ca91cx42_master_get; | |
1663 | ca91cx42_bridge->master_set = ca91cx42_master_set; | |
1664 | ca91cx42_bridge->master_read = ca91cx42_master_read; | |
1665 | ca91cx42_bridge->master_write = ca91cx42_master_write; | |
3d0f8bc7 MW |
1666 | ca91cx42_bridge->master_rmw = ca91cx42_master_rmw; |
1667 | ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add; | |
1668 | ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec; | |
1669 | ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty; | |
c813f592 MW |
1670 | ca91cx42_bridge->irq_set = ca91cx42_irq_set; |
1671 | ca91cx42_bridge->irq_generate = ca91cx42_irq_generate; | |
3d0f8bc7 MW |
1672 | ca91cx42_bridge->lm_set = ca91cx42_lm_set; |
1673 | ca91cx42_bridge->lm_get = ca91cx42_lm_get; | |
1674 | ca91cx42_bridge->lm_attach = ca91cx42_lm_attach; | |
1675 | ca91cx42_bridge->lm_detach = ca91cx42_lm_detach; | |
3d0f8bc7 MW |
1676 | ca91cx42_bridge->slot_get = ca91cx42_slot_get; |
1677 | ||
29848ac9 | 1678 | data = ioread32(ca91cx42_device->base + MISC_CTL); |
3d0f8bc7 MW |
1679 | dev_info(&pdev->dev, "Board is%s the VME system controller\n", |
1680 | (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not"); | |
29848ac9 MW |
1681 | dev_info(&pdev->dev, "Slot ID is %d\n", |
1682 | ca91cx42_slot_get(ca91cx42_bridge)); | |
3d0f8bc7 | 1683 | |
7946328f | 1684 | if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev)) |
3d0f8bc7 | 1685 | dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); |
60479690 | 1686 | |
3d0f8bc7 MW |
1687 | /* Need to save ca91cx42_bridge pointer locally in link list for use in |
1688 | * ca91cx42_remove() | |
1689 | */ | |
1690 | retval = vme_register_bridge(ca91cx42_bridge); | |
1691 | if (retval != 0) { | |
1692 | dev_err(&pdev->dev, "Chip Registration failed.\n"); | |
1693 | goto err_reg; | |
1694 | } | |
1695 | ||
29848ac9 MW |
1696 | pci_set_drvdata(pdev, ca91cx42_bridge); |
1697 | ||
3d0f8bc7 MW |
1698 | return 0; |
1699 | ||
1700 | vme_unregister_bridge(ca91cx42_bridge); | |
1701 | err_reg: | |
29848ac9 | 1702 | ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); |
3d0f8bc7 MW |
1703 | err_lm: |
1704 | /* resources are stored in link list */ | |
1705 | list_for_each(pos, &(ca91cx42_bridge->lm_resources)) { | |
1706 | lm = list_entry(pos, struct vme_lm_resource, list); | |
1707 | list_del(pos); | |
1708 | kfree(lm); | |
1709 | } | |
3d0f8bc7 MW |
1710 | err_dma: |
1711 | /* resources are stored in link list */ | |
1712 | list_for_each(pos, &(ca91cx42_bridge->dma_resources)) { | |
1713 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); | |
1714 | list_del(pos); | |
1715 | kfree(dma_ctrlr); | |
60479690 | 1716 | } |
3d0f8bc7 MW |
1717 | err_slave: |
1718 | /* resources are stored in link list */ | |
1719 | list_for_each(pos, &(ca91cx42_bridge->slave_resources)) { | |
1720 | slave_image = list_entry(pos, struct vme_slave_resource, list); | |
1721 | list_del(pos); | |
1722 | kfree(slave_image); | |
1723 | } | |
1724 | err_master: | |
1725 | /* resources are stored in link list */ | |
1726 | list_for_each(pos, &(ca91cx42_bridge->master_resources)) { | |
1727 | master_image = list_entry(pos, struct vme_master_resource, | |
1728 | list); | |
1729 | list_del(pos); | |
1730 | kfree(master_image); | |
1731 | } | |
1732 | ||
29848ac9 | 1733 | ca91cx42_irq_exit(ca91cx42_device, pdev); |
3d0f8bc7 MW |
1734 | err_irq: |
1735 | err_test: | |
29848ac9 | 1736 | iounmap(ca91cx42_device->base); |
3d0f8bc7 MW |
1737 | err_remap: |
1738 | pci_release_regions(pdev); | |
1739 | err_resource: | |
1740 | pci_disable_device(pdev); | |
1741 | err_enable: | |
29848ac9 MW |
1742 | kfree(ca91cx42_device); |
1743 | err_driver: | |
3d0f8bc7 MW |
1744 | kfree(ca91cx42_bridge); |
1745 | err_struct: | |
1746 | return retval; | |
60479690 | 1747 | |
60479690 MW |
1748 | } |
1749 | ||
3d0f8bc7 | 1750 | void ca91cx42_remove(struct pci_dev *pdev) |
60479690 | 1751 | { |
3d0f8bc7 MW |
1752 | struct list_head *pos = NULL; |
1753 | struct vme_master_resource *master_image; | |
1754 | struct vme_slave_resource *slave_image; | |
1755 | struct vme_dma_resource *dma_ctrlr; | |
1756 | struct vme_lm_resource *lm; | |
29848ac9 MW |
1757 | struct ca91cx42_driver *bridge; |
1758 | struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev); | |
1759 | ||
1760 | bridge = ca91cx42_bridge->driver_priv; | |
1761 | ||
60479690 | 1762 | |
3d0f8bc7 | 1763 | /* Turn off Ints */ |
29848ac9 | 1764 | iowrite32(0, bridge->base + LINT_EN); |
3d0f8bc7 MW |
1765 | |
1766 | /* Turn off the windows */ | |
29848ac9 MW |
1767 | iowrite32(0x00800000, bridge->base + LSI0_CTL); |
1768 | iowrite32(0x00800000, bridge->base + LSI1_CTL); | |
1769 | iowrite32(0x00800000, bridge->base + LSI2_CTL); | |
1770 | iowrite32(0x00800000, bridge->base + LSI3_CTL); | |
1771 | iowrite32(0x00800000, bridge->base + LSI4_CTL); | |
1772 | iowrite32(0x00800000, bridge->base + LSI5_CTL); | |
1773 | iowrite32(0x00800000, bridge->base + LSI6_CTL); | |
1774 | iowrite32(0x00800000, bridge->base + LSI7_CTL); | |
1775 | iowrite32(0x00F00000, bridge->base + VSI0_CTL); | |
1776 | iowrite32(0x00F00000, bridge->base + VSI1_CTL); | |
1777 | iowrite32(0x00F00000, bridge->base + VSI2_CTL); | |
1778 | iowrite32(0x00F00000, bridge->base + VSI3_CTL); | |
1779 | iowrite32(0x00F00000, bridge->base + VSI4_CTL); | |
1780 | iowrite32(0x00F00000, bridge->base + VSI5_CTL); | |
1781 | iowrite32(0x00F00000, bridge->base + VSI6_CTL); | |
1782 | iowrite32(0x00F00000, bridge->base + VSI7_CTL); | |
3d0f8bc7 MW |
1783 | |
1784 | vme_unregister_bridge(ca91cx42_bridge); | |
bb9ea89e MW |
1785 | |
1786 | ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); | |
1787 | ||
3d0f8bc7 MW |
1788 | /* resources are stored in link list */ |
1789 | list_for_each(pos, &(ca91cx42_bridge->lm_resources)) { | |
1790 | lm = list_entry(pos, struct vme_lm_resource, list); | |
1791 | list_del(pos); | |
1792 | kfree(lm); | |
60479690 | 1793 | } |
3d0f8bc7 MW |
1794 | |
1795 | /* resources are stored in link list */ | |
1796 | list_for_each(pos, &(ca91cx42_bridge->dma_resources)) { | |
1797 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); | |
1798 | list_del(pos); | |
1799 | kfree(dma_ctrlr); | |
60479690 MW |
1800 | } |
1801 | ||
3d0f8bc7 MW |
1802 | /* resources are stored in link list */ |
1803 | list_for_each(pos, &(ca91cx42_bridge->slave_resources)) { | |
1804 | slave_image = list_entry(pos, struct vme_slave_resource, list); | |
1805 | list_del(pos); | |
1806 | kfree(slave_image); | |
1807 | } | |
60479690 | 1808 | |
3d0f8bc7 MW |
1809 | /* resources are stored in link list */ |
1810 | list_for_each(pos, &(ca91cx42_bridge->master_resources)) { | |
1811 | master_image = list_entry(pos, struct vme_master_resource, | |
1812 | list); | |
1813 | list_del(pos); | |
1814 | kfree(master_image); | |
1815 | } | |
60479690 | 1816 | |
29848ac9 | 1817 | ca91cx42_irq_exit(bridge, pdev); |
60479690 | 1818 | |
29848ac9 | 1819 | iounmap(bridge->base); |
60479690 | 1820 | |
3d0f8bc7 | 1821 | pci_release_regions(pdev); |
60479690 | 1822 | |
3d0f8bc7 MW |
1823 | pci_disable_device(pdev); |
1824 | ||
1825 | kfree(ca91cx42_bridge); | |
60479690 MW |
1826 | } |
1827 | ||
3d0f8bc7 | 1828 | static void __exit ca91cx42_exit(void) |
60479690 | 1829 | { |
3d0f8bc7 MW |
1830 | pci_unregister_driver(&ca91cx42_driver); |
1831 | } | |
60479690 | 1832 | |
12b2d5c0 MW |
1833 | MODULE_PARM_DESC(geoid, "Override geographical addressing"); |
1834 | module_param(geoid, int, 0); | |
1835 | ||
3d0f8bc7 MW |
1836 | MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge"); |
1837 | MODULE_LICENSE("GPL"); | |
60479690 | 1838 | |
3d0f8bc7 MW |
1839 | module_init(ca91cx42_init); |
1840 | module_exit(ca91cx42_exit); |