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60479690 MW |
1 | /* |
2 | * Support for the Tundra Universe I/II VME-PCI Bridge Chips | |
3 | * | |
66bd8db5 MW |
4 | * Author: Martyn Welch <martyn.welch@ge.com> |
5 | * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. | |
60479690 MW |
6 | * |
7 | * Based on work by Tom Armistead and Ajit Prem | |
8 | * Copyright 2004 Motorola Inc. | |
9 | * | |
10 | * Derived from ca91c042.c by Michael Wyrick | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify it | |
13 | * under the terms of the GNU General Public License as published by the | |
14 | * Free Software Foundation; either version 2 of the License, or (at your | |
15 | * option) any later version. | |
16 | */ | |
17 | ||
60479690 MW |
18 | #include <linux/module.h> |
19 | #include <linux/mm.h> | |
20 | #include <linux/types.h> | |
21 | #include <linux/errno.h> | |
60479690 MW |
22 | #include <linux/pci.h> |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/poll.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/spinlock.h> | |
6af783c8 | 27 | #include <linux/sched.h> |
60479690 MW |
28 | #include <asm/time.h> |
29 | #include <asm/io.h> | |
30 | #include <asm/uaccess.h> | |
31 | ||
32 | #include "../vme.h" | |
33 | #include "../vme_bridge.h" | |
34 | #include "vme_ca91cx42.h" | |
35 | ||
3d0f8bc7 MW |
36 | static int __init ca91cx42_init(void); |
37 | static int ca91cx42_probe(struct pci_dev *, const struct pci_device_id *); | |
38 | static void ca91cx42_remove(struct pci_dev *); | |
39 | static void __exit ca91cx42_exit(void); | |
60479690 | 40 | |
12b2d5c0 MW |
41 | /* Module parameters */ |
42 | static int geoid; | |
43 | ||
3d0f8bc7 | 44 | static char driver_name[] = "vme_ca91cx42"; |
60479690 | 45 | |
13ac58da | 46 | static const struct pci_device_id ca91cx42_ids[] = { |
3d0f8bc7 MW |
47 | { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_CA91C142) }, |
48 | { }, | |
60479690 MW |
49 | }; |
50 | ||
3d0f8bc7 MW |
51 | static struct pci_driver ca91cx42_driver = { |
52 | .name = driver_name, | |
53 | .id_table = ca91cx42_ids, | |
54 | .probe = ca91cx42_probe, | |
55 | .remove = ca91cx42_remove, | |
60479690 MW |
56 | }; |
57 | ||
29848ac9 | 58 | static u32 ca91cx42_DMA_irqhandler(struct ca91cx42_driver *bridge) |
60479690 | 59 | { |
29848ac9 | 60 | wake_up(&(bridge->dma_queue)); |
60479690 | 61 | |
3d0f8bc7 MW |
62 | return CA91CX42_LINT_DMA; |
63 | } | |
60479690 | 64 | |
29848ac9 | 65 | static u32 ca91cx42_LM_irqhandler(struct ca91cx42_driver *bridge, u32 stat) |
3d0f8bc7 MW |
66 | { |
67 | int i; | |
68 | u32 serviced = 0; | |
60479690 | 69 | |
3d0f8bc7 MW |
70 | for (i = 0; i < 4; i++) { |
71 | if (stat & CA91CX42_LINT_LM[i]) { | |
72 | /* We only enable interrupts if the callback is set */ | |
29848ac9 | 73 | bridge->lm_callback[i](i); |
3d0f8bc7 | 74 | serviced |= CA91CX42_LINT_LM[i]; |
60479690 | 75 | } |
60479690 | 76 | } |
60479690 | 77 | |
3d0f8bc7 MW |
78 | return serviced; |
79 | } | |
60479690 | 80 | |
3d0f8bc7 | 81 | /* XXX This needs to be split into 4 queues */ |
29848ac9 | 82 | static u32 ca91cx42_MB_irqhandler(struct ca91cx42_driver *bridge, int mbox_mask) |
3d0f8bc7 | 83 | { |
29848ac9 | 84 | wake_up(&(bridge->mbox_queue)); |
60479690 | 85 | |
3d0f8bc7 MW |
86 | return CA91CX42_LINT_MBOX; |
87 | } | |
60479690 | 88 | |
29848ac9 | 89 | static u32 ca91cx42_IACK_irqhandler(struct ca91cx42_driver *bridge) |
3d0f8bc7 | 90 | { |
29848ac9 | 91 | wake_up(&(bridge->iack_queue)); |
60479690 | 92 | |
3d0f8bc7 | 93 | return CA91CX42_LINT_SW_IACK; |
60479690 MW |
94 | } |
95 | ||
3d0f8bc7 MW |
96 | #if 0 |
97 | int ca91cx42_bus_error_chk(int clrflag) | |
60479690 MW |
98 | { |
99 | int tmp; | |
29848ac9 | 100 | tmp = ioread32(bridge->base + PCI_COMMAND); |
3d0f8bc7 | 101 | if (tmp & 0x08000000) { /* S_TA is Set */ |
60479690 | 102 | if (clrflag) |
3d0f8bc7 | 103 | iowrite32(tmp | 0x08000000, |
29848ac9 | 104 | bridge->base + PCI_COMMAND); |
3d0f8bc7 | 105 | return 1; |
60479690 | 106 | } |
3d0f8bc7 | 107 | return 0; |
60479690 | 108 | } |
3d0f8bc7 | 109 | #endif |
60479690 | 110 | |
29848ac9 | 111 | static u32 ca91cx42_VERR_irqhandler(struct ca91cx42_driver *bridge) |
60479690 MW |
112 | { |
113 | int val; | |
114 | ||
29848ac9 | 115 | val = ioread32(bridge->base + DGCS); |
60479690 MW |
116 | |
117 | if (!(val & 0x00000800)) { | |
3d0f8bc7 MW |
118 | printk(KERN_ERR "ca91c042: ca91cx42_VERR_irqhandler DMA Read " |
119 | "Error DGCS=%08X\n", val); | |
60479690 | 120 | } |
3d0f8bc7 MW |
121 | |
122 | return CA91CX42_LINT_VERR; | |
60479690 MW |
123 | } |
124 | ||
29848ac9 | 125 | static u32 ca91cx42_LERR_irqhandler(struct ca91cx42_driver *bridge) |
60479690 MW |
126 | { |
127 | int val; | |
128 | ||
29848ac9 | 129 | val = ioread32(bridge->base + DGCS); |
60479690 MW |
130 | |
131 | if (!(val & 0x00000800)) { | |
3d0f8bc7 MW |
132 | printk(KERN_ERR "ca91c042: ca91cx42_LERR_irqhandler DMA Read " |
133 | "Error DGCS=%08X\n", val); | |
60479690 | 134 | |
60479690 | 135 | } |
60479690 | 136 | |
3d0f8bc7 | 137 | return CA91CX42_LINT_LERR; |
60479690 MW |
138 | } |
139 | ||
3d0f8bc7 | 140 | |
29848ac9 MW |
141 | static u32 ca91cx42_VIRQ_irqhandler(struct vme_bridge *ca91cx42_bridge, |
142 | int stat) | |
60479690 | 143 | { |
3d0f8bc7 | 144 | int vec, i, serviced = 0; |
29848ac9 MW |
145 | struct ca91cx42_driver *bridge; |
146 | ||
147 | bridge = ca91cx42_bridge->driver_priv; | |
148 | ||
60479690 MW |
149 | |
150 | for (i = 7; i > 0; i--) { | |
3d0f8bc7 | 151 | if (stat & (1 << i)) { |
29848ac9 | 152 | vec = ioread32(bridge->base + |
3d0f8bc7 MW |
153 | CA91CX42_V_STATID[i]) & 0xff; |
154 | ||
c813f592 | 155 | vme_irq_handler(ca91cx42_bridge, i, vec); |
3d0f8bc7 MW |
156 | |
157 | serviced |= (1 << i); | |
60479690 MW |
158 | } |
159 | } | |
3d0f8bc7 MW |
160 | |
161 | return serviced; | |
60479690 MW |
162 | } |
163 | ||
29848ac9 | 164 | static irqreturn_t ca91cx42_irqhandler(int irq, void *ptr) |
60479690 | 165 | { |
3d0f8bc7 | 166 | u32 stat, enable, serviced = 0; |
29848ac9 MW |
167 | struct vme_bridge *ca91cx42_bridge; |
168 | struct ca91cx42_driver *bridge; | |
60479690 | 169 | |
29848ac9 | 170 | ca91cx42_bridge = ptr; |
60479690 | 171 | |
29848ac9 MW |
172 | bridge = ca91cx42_bridge->driver_priv; |
173 | ||
174 | enable = ioread32(bridge->base + LINT_EN); | |
175 | stat = ioread32(bridge->base + LINT_STAT); | |
60479690 | 176 | |
3d0f8bc7 MW |
177 | /* Only look at unmasked interrupts */ |
178 | stat &= enable; | |
179 | ||
180 | if (unlikely(!stat)) | |
181 | return IRQ_NONE; | |
182 | ||
183 | if (stat & CA91CX42_LINT_DMA) | |
29848ac9 | 184 | serviced |= ca91cx42_DMA_irqhandler(bridge); |
3d0f8bc7 MW |
185 | if (stat & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 | |
186 | CA91CX42_LINT_LM3)) | |
29848ac9 | 187 | serviced |= ca91cx42_LM_irqhandler(bridge, stat); |
3d0f8bc7 | 188 | if (stat & CA91CX42_LINT_MBOX) |
29848ac9 | 189 | serviced |= ca91cx42_MB_irqhandler(bridge, stat); |
3d0f8bc7 | 190 | if (stat & CA91CX42_LINT_SW_IACK) |
29848ac9 | 191 | serviced |= ca91cx42_IACK_irqhandler(bridge); |
3d0f8bc7 | 192 | if (stat & CA91CX42_LINT_VERR) |
29848ac9 | 193 | serviced |= ca91cx42_VERR_irqhandler(bridge); |
3d0f8bc7 | 194 | if (stat & CA91CX42_LINT_LERR) |
29848ac9 | 195 | serviced |= ca91cx42_LERR_irqhandler(bridge); |
3d0f8bc7 MW |
196 | if (stat & (CA91CX42_LINT_VIRQ1 | CA91CX42_LINT_VIRQ2 | |
197 | CA91CX42_LINT_VIRQ3 | CA91CX42_LINT_VIRQ4 | | |
198 | CA91CX42_LINT_VIRQ5 | CA91CX42_LINT_VIRQ6 | | |
199 | CA91CX42_LINT_VIRQ7)) | |
29848ac9 | 200 | serviced |= ca91cx42_VIRQ_irqhandler(ca91cx42_bridge, stat); |
3d0f8bc7 MW |
201 | |
202 | /* Clear serviced interrupts */ | |
29848ac9 | 203 | iowrite32(stat, bridge->base + LINT_STAT); |
60479690 MW |
204 | |
205 | return IRQ_HANDLED; | |
206 | } | |
207 | ||
29848ac9 | 208 | static int ca91cx42_irq_init(struct vme_bridge *ca91cx42_bridge) |
60479690 | 209 | { |
3d0f8bc7 MW |
210 | int result, tmp; |
211 | struct pci_dev *pdev; | |
29848ac9 MW |
212 | struct ca91cx42_driver *bridge; |
213 | ||
214 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 215 | |
3d0f8bc7 | 216 | /* Need pdev */ |
29848ac9 | 217 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); |
60479690 | 218 | |
3d0f8bc7 | 219 | /* Initialise list for VME bus errors */ |
29848ac9 | 220 | INIT_LIST_HEAD(&(ca91cx42_bridge->vme_errors)); |
60479690 | 221 | |
29848ac9 | 222 | mutex_init(&(ca91cx42_bridge->irq_mtx)); |
c813f592 | 223 | |
3d0f8bc7 MW |
224 | /* Disable interrupts from PCI to VME */ |
225 | iowrite32(0, bridge->base + VINT_EN); | |
60479690 | 226 | |
3d0f8bc7 MW |
227 | /* Disable PCI interrupts */ |
228 | iowrite32(0, bridge->base + LINT_EN); | |
229 | /* Clear Any Pending PCI Interrupts */ | |
230 | iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); | |
60479690 | 231 | |
3d0f8bc7 | 232 | result = request_irq(pdev->irq, ca91cx42_irqhandler, IRQF_SHARED, |
29848ac9 | 233 | driver_name, ca91cx42_bridge); |
3d0f8bc7 MW |
234 | if (result) { |
235 | dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n", | |
236 | pdev->irq); | |
237 | return result; | |
60479690 MW |
238 | } |
239 | ||
3d0f8bc7 MW |
240 | /* Ensure all interrupts are mapped to PCI Interrupt 0 */ |
241 | iowrite32(0, bridge->base + LINT_MAP0); | |
242 | iowrite32(0, bridge->base + LINT_MAP1); | |
243 | iowrite32(0, bridge->base + LINT_MAP2); | |
244 | ||
245 | /* Enable DMA, mailbox & LM Interrupts */ | |
246 | tmp = CA91CX42_LINT_MBOX3 | CA91CX42_LINT_MBOX2 | CA91CX42_LINT_MBOX1 | | |
247 | CA91CX42_LINT_MBOX0 | CA91CX42_LINT_SW_IACK | | |
248 | CA91CX42_LINT_VERR | CA91CX42_LINT_LERR | CA91CX42_LINT_DMA; | |
249 | ||
250 | iowrite32(tmp, bridge->base + LINT_EN); | |
60479690 | 251 | |
3d0f8bc7 | 252 | return 0; |
60479690 MW |
253 | } |
254 | ||
29848ac9 MW |
255 | static void ca91cx42_irq_exit(struct ca91cx42_driver *bridge, |
256 | struct pci_dev *pdev) | |
60479690 | 257 | { |
3d0f8bc7 | 258 | /* Disable interrupts from PCI to VME */ |
29848ac9 | 259 | iowrite32(0, bridge->base + VINT_EN); |
60479690 | 260 | |
3d0f8bc7 | 261 | /* Disable PCI interrupts */ |
29848ac9 | 262 | iowrite32(0, bridge->base + LINT_EN); |
3d0f8bc7 | 263 | /* Clear Any Pending PCI Interrupts */ |
29848ac9 | 264 | iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); |
60479690 | 265 | |
3d0f8bc7 MW |
266 | free_irq(pdev->irq, pdev); |
267 | } | |
60479690 | 268 | |
3d0f8bc7 MW |
269 | /* |
270 | * Set up an VME interrupt | |
271 | */ | |
29848ac9 MW |
272 | void ca91cx42_irq_set(struct vme_bridge *ca91cx42_bridge, int level, int state, |
273 | int sync) | |
c813f592 | 274 | |
3d0f8bc7 | 275 | { |
c813f592 | 276 | struct pci_dev *pdev; |
3d0f8bc7 | 277 | u32 tmp; |
29848ac9 MW |
278 | struct ca91cx42_driver *bridge; |
279 | ||
280 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 281 | |
3d0f8bc7 | 282 | /* Enable IRQ level */ |
29848ac9 | 283 | tmp = ioread32(bridge->base + LINT_EN); |
3d0f8bc7 | 284 | |
c813f592 | 285 | if (state == 0) |
3d0f8bc7 | 286 | tmp &= ~CA91CX42_LINT_VIRQ[level]; |
c813f592 MW |
287 | else |
288 | tmp |= CA91CX42_LINT_VIRQ[level]; | |
60479690 | 289 | |
29848ac9 | 290 | iowrite32(tmp, bridge->base + LINT_EN); |
c813f592 MW |
291 | |
292 | if ((state == 0) && (sync != 0)) { | |
3d0f8bc7 MW |
293 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, |
294 | dev); | |
295 | ||
296 | synchronize_irq(pdev->irq); | |
60479690 | 297 | } |
60479690 MW |
298 | } |
299 | ||
29848ac9 MW |
300 | int ca91cx42_irq_generate(struct vme_bridge *ca91cx42_bridge, int level, |
301 | int statid) | |
60479690 | 302 | { |
3d0f8bc7 | 303 | u32 tmp; |
29848ac9 MW |
304 | struct ca91cx42_driver *bridge; |
305 | ||
306 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 307 | |
3d0f8bc7 MW |
308 | /* Universe can only generate even vectors */ |
309 | if (statid & 1) | |
310 | return -EINVAL; | |
60479690 | 311 | |
29848ac9 | 312 | mutex_lock(&(bridge->vme_int)); |
60479690 | 313 | |
29848ac9 | 314 | tmp = ioread32(bridge->base + VINT_EN); |
60479690 | 315 | |
3d0f8bc7 | 316 | /* Set Status/ID */ |
29848ac9 | 317 | iowrite32(statid << 24, bridge->base + STATID); |
3d0f8bc7 MW |
318 | |
319 | /* Assert VMEbus IRQ */ | |
320 | tmp = tmp | (1 << (level + 24)); | |
29848ac9 | 321 | iowrite32(tmp, bridge->base + VINT_EN); |
60479690 | 322 | |
3d0f8bc7 | 323 | /* Wait for IACK */ |
29848ac9 | 324 | wait_event_interruptible(bridge->iack_queue, 0); |
3d0f8bc7 MW |
325 | |
326 | /* Return interrupt to low state */ | |
29848ac9 | 327 | tmp = ioread32(bridge->base + VINT_EN); |
3d0f8bc7 | 328 | tmp = tmp & ~(1 << (level + 24)); |
29848ac9 | 329 | iowrite32(tmp, bridge->base + VINT_EN); |
3d0f8bc7 | 330 | |
29848ac9 | 331 | mutex_unlock(&(bridge->vme_int)); |
3d0f8bc7 MW |
332 | |
333 | return 0; | |
60479690 MW |
334 | } |
335 | ||
3d0f8bc7 MW |
336 | int ca91cx42_slave_set(struct vme_slave_resource *image, int enabled, |
337 | unsigned long long vme_base, unsigned long long size, | |
338 | dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle) | |
60479690 | 339 | { |
21e0cf6d | 340 | unsigned int i, addr = 0, granularity; |
3d0f8bc7 MW |
341 | unsigned int temp_ctl = 0; |
342 | unsigned int vme_bound, pci_offset; | |
29848ac9 MW |
343 | struct ca91cx42_driver *bridge; |
344 | ||
345 | bridge = image->parent->driver_priv; | |
60479690 | 346 | |
3d0f8bc7 | 347 | i = image->number; |
60479690 | 348 | |
3d0f8bc7 MW |
349 | switch (aspace) { |
350 | case VME_A16: | |
351 | addr |= CA91CX42_VSI_CTL_VAS_A16; | |
352 | break; | |
353 | case VME_A24: | |
354 | addr |= CA91CX42_VSI_CTL_VAS_A24; | |
355 | break; | |
356 | case VME_A32: | |
357 | addr |= CA91CX42_VSI_CTL_VAS_A32; | |
358 | break; | |
359 | case VME_USER1: | |
360 | addr |= CA91CX42_VSI_CTL_VAS_USER1; | |
361 | break; | |
362 | case VME_USER2: | |
363 | addr |= CA91CX42_VSI_CTL_VAS_USER2; | |
364 | break; | |
365 | case VME_A64: | |
366 | case VME_CRCSR: | |
367 | case VME_USER3: | |
368 | case VME_USER4: | |
369 | default: | |
370 | printk(KERN_ERR "Invalid address space\n"); | |
371 | return -EINVAL; | |
372 | break; | |
60479690 MW |
373 | } |
374 | ||
3d0f8bc7 MW |
375 | /* |
376 | * Bound address is a valid address for the window, adjust | |
377 | * accordingly | |
378 | */ | |
21e0cf6d | 379 | vme_bound = vme_base + size; |
3d0f8bc7 MW |
380 | pci_offset = pci_base - vme_base; |
381 | ||
382 | /* XXX Need to check that vme_base, vme_bound and pci_offset aren't | |
383 | * too big for registers | |
384 | */ | |
385 | ||
386 | if ((i == 0) || (i == 4)) | |
387 | granularity = 0x1000; | |
388 | else | |
389 | granularity = 0x10000; | |
390 | ||
391 | if (vme_base & (granularity - 1)) { | |
392 | printk(KERN_ERR "Invalid VME base alignment\n"); | |
393 | return -EINVAL; | |
394 | } | |
395 | if (vme_bound & (granularity - 1)) { | |
396 | printk(KERN_ERR "Invalid VME bound alignment\n"); | |
397 | return -EINVAL; | |
398 | } | |
399 | if (pci_offset & (granularity - 1)) { | |
400 | printk(KERN_ERR "Invalid PCI Offset alignment\n"); | |
401 | return -EINVAL; | |
60479690 MW |
402 | } |
403 | ||
3d0f8bc7 | 404 | /* Disable while we are mucking around */ |
29848ac9 | 405 | temp_ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); |
3d0f8bc7 | 406 | temp_ctl &= ~CA91CX42_VSI_CTL_EN; |
29848ac9 | 407 | iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); |
60479690 | 408 | |
3d0f8bc7 | 409 | /* Setup mapping */ |
29848ac9 MW |
410 | iowrite32(vme_base, bridge->base + CA91CX42_VSI_BS[i]); |
411 | iowrite32(vme_bound, bridge->base + CA91CX42_VSI_BD[i]); | |
412 | iowrite32(pci_offset, bridge->base + CA91CX42_VSI_TO[i]); | |
3d0f8bc7 MW |
413 | |
414 | /* XXX Prefetch stuff currently unsupported */ | |
415 | #if 0 | |
416 | if (vmeIn->wrPostEnable) | |
417 | temp_ctl |= CA91CX42_VSI_CTL_PWEN; | |
418 | if (vmeIn->prefetchEnable) | |
419 | temp_ctl |= CA91CX42_VSI_CTL_PREN; | |
420 | if (vmeIn->rmwLock) | |
421 | temp_ctl |= CA91CX42_VSI_CTL_LLRMW; | |
422 | if (vmeIn->data64BitCapable) | |
423 | temp_ctl |= CA91CX42_VSI_CTL_LD64EN; | |
424 | #endif | |
425 | ||
426 | /* Setup address space */ | |
427 | temp_ctl &= ~CA91CX42_VSI_CTL_VAS_M; | |
428 | temp_ctl |= addr; | |
429 | ||
430 | /* Setup cycle types */ | |
431 | temp_ctl &= ~(CA91CX42_VSI_CTL_PGM_M | CA91CX42_VSI_CTL_SUPER_M); | |
432 | if (cycle & VME_SUPER) | |
433 | temp_ctl |= CA91CX42_VSI_CTL_SUPER_SUPR; | |
434 | if (cycle & VME_USER) | |
435 | temp_ctl |= CA91CX42_VSI_CTL_SUPER_NPRIV; | |
436 | if (cycle & VME_PROG) | |
437 | temp_ctl |= CA91CX42_VSI_CTL_PGM_PGM; | |
438 | if (cycle & VME_DATA) | |
439 | temp_ctl |= CA91CX42_VSI_CTL_PGM_DATA; | |
440 | ||
441 | /* Write ctl reg without enable */ | |
29848ac9 | 442 | iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); |
3d0f8bc7 MW |
443 | |
444 | if (enabled) | |
445 | temp_ctl |= CA91CX42_VSI_CTL_EN; | |
446 | ||
29848ac9 | 447 | iowrite32(temp_ctl, bridge->base + CA91CX42_VSI_CTL[i]); |
3d0f8bc7 MW |
448 | |
449 | return 0; | |
60479690 MW |
450 | } |
451 | ||
3d0f8bc7 MW |
452 | int ca91cx42_slave_get(struct vme_slave_resource *image, int *enabled, |
453 | unsigned long long *vme_base, unsigned long long *size, | |
454 | dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle) | |
60479690 | 455 | { |
3d0f8bc7 MW |
456 | unsigned int i, granularity = 0, ctl = 0; |
457 | unsigned long long vme_bound, pci_offset; | |
29848ac9 MW |
458 | struct ca91cx42_driver *bridge; |
459 | ||
460 | bridge = image->parent->driver_priv; | |
3d0f8bc7 MW |
461 | |
462 | i = image->number; | |
60479690 | 463 | |
3d0f8bc7 MW |
464 | if ((i == 0) || (i == 4)) |
465 | granularity = 0x1000; | |
466 | else | |
467 | granularity = 0x10000; | |
468 | ||
469 | /* Read Registers */ | |
29848ac9 | 470 | ctl = ioread32(bridge->base + CA91CX42_VSI_CTL[i]); |
3d0f8bc7 | 471 | |
29848ac9 MW |
472 | *vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]); |
473 | vme_bound = ioread32(bridge->base + CA91CX42_VSI_BD[i]); | |
474 | pci_offset = ioread32(bridge->base + CA91CX42_VSI_TO[i]); | |
3d0f8bc7 MW |
475 | |
476 | *pci_base = (dma_addr_t)vme_base + pci_offset; | |
477 | *size = (unsigned long long)((vme_bound - *vme_base) + granularity); | |
478 | ||
479 | *enabled = 0; | |
480 | *aspace = 0; | |
481 | *cycle = 0; | |
482 | ||
483 | if (ctl & CA91CX42_VSI_CTL_EN) | |
484 | *enabled = 1; | |
485 | ||
486 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A16) | |
487 | *aspace = VME_A16; | |
488 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A24) | |
489 | *aspace = VME_A24; | |
490 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_A32) | |
491 | *aspace = VME_A32; | |
492 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER1) | |
493 | *aspace = VME_USER1; | |
494 | if ((ctl & CA91CX42_VSI_CTL_VAS_M) == CA91CX42_VSI_CTL_VAS_USER2) | |
495 | *aspace = VME_USER2; | |
496 | ||
497 | if (ctl & CA91CX42_VSI_CTL_SUPER_SUPR) | |
498 | *cycle |= VME_SUPER; | |
499 | if (ctl & CA91CX42_VSI_CTL_SUPER_NPRIV) | |
500 | *cycle |= VME_USER; | |
501 | if (ctl & CA91CX42_VSI_CTL_PGM_PGM) | |
502 | *cycle |= VME_PROG; | |
503 | if (ctl & CA91CX42_VSI_CTL_PGM_DATA) | |
504 | *cycle |= VME_DATA; | |
505 | ||
506 | return 0; | |
507 | } | |
508 | ||
509 | /* | |
510 | * Allocate and map PCI Resource | |
511 | */ | |
512 | static int ca91cx42_alloc_resource(struct vme_master_resource *image, | |
513 | unsigned long long size) | |
514 | { | |
515 | unsigned long long existing_size; | |
516 | int retval = 0; | |
517 | struct pci_dev *pdev; | |
29848ac9 MW |
518 | struct vme_bridge *ca91cx42_bridge; |
519 | ||
520 | ca91cx42_bridge = image->parent; | |
3d0f8bc7 MW |
521 | |
522 | /* Find pci_dev container of dev */ | |
523 | if (ca91cx42_bridge->parent == NULL) { | |
524 | printk(KERN_ERR "Dev entry NULL\n"); | |
525 | return -EINVAL; | |
526 | } | |
527 | pdev = container_of(ca91cx42_bridge->parent, struct pci_dev, dev); | |
528 | ||
8fafb476 MW |
529 | existing_size = (unsigned long long)(image->bus_resource.end - |
530 | image->bus_resource.start); | |
3d0f8bc7 MW |
531 | |
532 | /* If the existing size is OK, return */ | |
533 | if (existing_size == (size - 1)) | |
534 | return 0; | |
535 | ||
536 | if (existing_size != 0) { | |
537 | iounmap(image->kern_base); | |
538 | image->kern_base = NULL; | |
8fafb476 MW |
539 | if (image->bus_resource.name != NULL) |
540 | kfree(image->bus_resource.name); | |
541 | release_resource(&(image->bus_resource)); | |
542 | memset(&(image->bus_resource), 0, sizeof(struct resource)); | |
3d0f8bc7 MW |
543 | } |
544 | ||
8fafb476 MW |
545 | if (image->bus_resource.name == NULL) { |
546 | image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL); | |
547 | if (image->bus_resource.name == NULL) { | |
3d0f8bc7 MW |
548 | printk(KERN_ERR "Unable to allocate memory for resource" |
549 | " name\n"); | |
550 | retval = -ENOMEM; | |
551 | goto err_name; | |
552 | } | |
60479690 | 553 | } |
3d0f8bc7 | 554 | |
8fafb476 | 555 | sprintf((char *)image->bus_resource.name, "%s.%d", |
3d0f8bc7 MW |
556 | ca91cx42_bridge->name, image->number); |
557 | ||
8fafb476 MW |
558 | image->bus_resource.start = 0; |
559 | image->bus_resource.end = (unsigned long)size; | |
560 | image->bus_resource.flags = IORESOURCE_MEM; | |
3d0f8bc7 MW |
561 | |
562 | retval = pci_bus_alloc_resource(pdev->bus, | |
8fafb476 | 563 | &(image->bus_resource), size, size, PCIBIOS_MIN_MEM, |
3d0f8bc7 MW |
564 | 0, NULL, NULL); |
565 | if (retval) { | |
566 | printk(KERN_ERR "Failed to allocate mem resource for " | |
567 | "window %d size 0x%lx start 0x%lx\n", | |
568 | image->number, (unsigned long)size, | |
8fafb476 | 569 | (unsigned long)image->bus_resource.start); |
3d0f8bc7 | 570 | goto err_resource; |
60479690 | 571 | } |
3d0f8bc7 MW |
572 | |
573 | image->kern_base = ioremap_nocache( | |
8fafb476 | 574 | image->bus_resource.start, size); |
3d0f8bc7 MW |
575 | if (image->kern_base == NULL) { |
576 | printk(KERN_ERR "Failed to remap resource\n"); | |
577 | retval = -ENOMEM; | |
578 | goto err_remap; | |
60479690 MW |
579 | } |
580 | ||
3d0f8bc7 MW |
581 | return 0; |
582 | ||
583 | iounmap(image->kern_base); | |
584 | image->kern_base = NULL; | |
585 | err_remap: | |
8fafb476 | 586 | release_resource(&(image->bus_resource)); |
3d0f8bc7 | 587 | err_resource: |
8fafb476 MW |
588 | kfree(image->bus_resource.name); |
589 | memset(&(image->bus_resource), 0, sizeof(struct resource)); | |
3d0f8bc7 MW |
590 | err_name: |
591 | return retval; | |
592 | } | |
593 | ||
594 | /* | |
4860ab74 MW |
595 | * Free and unmap PCI Resource |
596 | */ | |
3d0f8bc7 MW |
597 | static void ca91cx42_free_resource(struct vme_master_resource *image) |
598 | { | |
599 | iounmap(image->kern_base); | |
600 | image->kern_base = NULL; | |
8fafb476 MW |
601 | release_resource(&(image->bus_resource)); |
602 | kfree(image->bus_resource.name); | |
603 | memset(&(image->bus_resource), 0, sizeof(struct resource)); | |
3d0f8bc7 MW |
604 | } |
605 | ||
606 | ||
607 | int ca91cx42_master_set(struct vme_master_resource *image, int enabled, | |
608 | unsigned long long vme_base, unsigned long long size, | |
609 | vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth) | |
610 | { | |
611 | int retval = 0; | |
21e0cf6d | 612 | unsigned int i, granularity = 0; |
3d0f8bc7 MW |
613 | unsigned int temp_ctl = 0; |
614 | unsigned long long pci_bound, vme_offset, pci_base; | |
29848ac9 MW |
615 | struct ca91cx42_driver *bridge; |
616 | ||
617 | bridge = image->parent->driver_priv; | |
3d0f8bc7 | 618 | |
21e0cf6d MW |
619 | i = image->number; |
620 | ||
621 | if ((i == 0) || (i == 4)) | |
622 | granularity = 0x1000; | |
623 | else | |
624 | granularity = 0x10000; | |
625 | ||
3d0f8bc7 | 626 | /* Verify input data */ |
21e0cf6d | 627 | if (vme_base & (granularity - 1)) { |
3d0f8bc7 MW |
628 | printk(KERN_ERR "Invalid VME Window alignment\n"); |
629 | retval = -EINVAL; | |
630 | goto err_window; | |
631 | } | |
21e0cf6d | 632 | if (size & (granularity - 1)) { |
3d0f8bc7 MW |
633 | printk(KERN_ERR "Invalid VME Window alignment\n"); |
634 | retval = -EINVAL; | |
635 | goto err_window; | |
636 | } | |
637 | ||
638 | spin_lock(&(image->lock)); | |
639 | ||
640 | /* XXX We should do this much later, so that we can exit without | |
641 | * needing to redo the mapping... | |
642 | */ | |
643 | /* | |
644 | * Let's allocate the resource here rather than further up the stack as | |
645 | * it avoids pushing loads of bus dependant stuff up the stack | |
646 | */ | |
647 | retval = ca91cx42_alloc_resource(image, size); | |
648 | if (retval) { | |
649 | spin_unlock(&(image->lock)); | |
650 | printk(KERN_ERR "Unable to allocate memory for resource " | |
651 | "name\n"); | |
652 | retval = -ENOMEM; | |
653 | goto err_res; | |
654 | } | |
655 | ||
8fafb476 | 656 | pci_base = (unsigned long long)image->bus_resource.start; |
3d0f8bc7 MW |
657 | |
658 | /* | |
659 | * Bound address is a valid address for the window, adjust | |
660 | * according to window granularity. | |
661 | */ | |
21e0cf6d | 662 | pci_bound = pci_base + size; |
3d0f8bc7 MW |
663 | vme_offset = vme_base - pci_base; |
664 | ||
3d0f8bc7 | 665 | /* Disable while we are mucking around */ |
29848ac9 | 666 | temp_ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); |
3d0f8bc7 | 667 | temp_ctl &= ~CA91CX42_LSI_CTL_EN; |
29848ac9 | 668 | iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); |
3d0f8bc7 MW |
669 | |
670 | /* XXX Prefetch stuff currently unsupported */ | |
671 | #if 0 | |
672 | if (vmeOut->wrPostEnable) | |
673 | temp_ctl |= 0x40000000; | |
674 | #endif | |
675 | ||
676 | /* Setup cycle types */ | |
677 | temp_ctl &= ~CA91CX42_LSI_CTL_VCT_M; | |
678 | if (cycle & VME_BLT) | |
679 | temp_ctl |= CA91CX42_LSI_CTL_VCT_BLT; | |
680 | if (cycle & VME_MBLT) | |
681 | temp_ctl |= CA91CX42_LSI_CTL_VCT_MBLT; | |
682 | ||
683 | /* Setup data width */ | |
684 | temp_ctl &= ~CA91CX42_LSI_CTL_VDW_M; | |
685 | switch (dwidth) { | |
686 | case VME_D8: | |
687 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D8; | |
688 | break; | |
689 | case VME_D16: | |
690 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D16; | |
691 | break; | |
692 | case VME_D32: | |
693 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D32; | |
694 | break; | |
695 | case VME_D64: | |
696 | temp_ctl |= CA91CX42_LSI_CTL_VDW_D64; | |
697 | break; | |
698 | default: | |
699 | spin_unlock(&(image->lock)); | |
700 | printk(KERN_ERR "Invalid data width\n"); | |
701 | retval = -EINVAL; | |
702 | goto err_dwidth; | |
703 | break; | |
60479690 | 704 | } |
3d0f8bc7 MW |
705 | |
706 | /* Setup address space */ | |
707 | temp_ctl &= ~CA91CX42_LSI_CTL_VAS_M; | |
708 | switch (aspace) { | |
60479690 | 709 | case VME_A16: |
3d0f8bc7 | 710 | temp_ctl |= CA91CX42_LSI_CTL_VAS_A16; |
60479690 MW |
711 | break; |
712 | case VME_A24: | |
3d0f8bc7 | 713 | temp_ctl |= CA91CX42_LSI_CTL_VAS_A24; |
60479690 MW |
714 | break; |
715 | case VME_A32: | |
3d0f8bc7 MW |
716 | temp_ctl |= CA91CX42_LSI_CTL_VAS_A32; |
717 | break; | |
718 | case VME_CRCSR: | |
719 | temp_ctl |= CA91CX42_LSI_CTL_VAS_CRCSR; | |
60479690 MW |
720 | break; |
721 | case VME_USER1: | |
3d0f8bc7 | 722 | temp_ctl |= CA91CX42_LSI_CTL_VAS_USER1; |
60479690 MW |
723 | break; |
724 | case VME_USER2: | |
3d0f8bc7 MW |
725 | temp_ctl |= CA91CX42_LSI_CTL_VAS_USER2; |
726 | break; | |
727 | case VME_A64: | |
728 | case VME_USER3: | |
729 | case VME_USER4: | |
730 | default: | |
731 | spin_unlock(&(image->lock)); | |
732 | printk(KERN_ERR "Invalid address space\n"); | |
733 | retval = -EINVAL; | |
734 | goto err_aspace; | |
60479690 MW |
735 | break; |
736 | } | |
737 | ||
3d0f8bc7 MW |
738 | temp_ctl &= ~(CA91CX42_LSI_CTL_PGM_M | CA91CX42_LSI_CTL_SUPER_M); |
739 | if (cycle & VME_SUPER) | |
740 | temp_ctl |= CA91CX42_LSI_CTL_SUPER_SUPR; | |
741 | if (cycle & VME_PROG) | |
742 | temp_ctl |= CA91CX42_LSI_CTL_PGM_PGM; | |
60479690 | 743 | |
3d0f8bc7 | 744 | /* Setup mapping */ |
29848ac9 MW |
745 | iowrite32(pci_base, bridge->base + CA91CX42_LSI_BS[i]); |
746 | iowrite32(pci_bound, bridge->base + CA91CX42_LSI_BD[i]); | |
747 | iowrite32(vme_offset, bridge->base + CA91CX42_LSI_TO[i]); | |
3d0f8bc7 MW |
748 | |
749 | /* Write ctl reg without enable */ | |
29848ac9 | 750 | iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); |
3d0f8bc7 MW |
751 | |
752 | if (enabled) | |
753 | temp_ctl |= CA91CX42_LSI_CTL_EN; | |
754 | ||
29848ac9 | 755 | iowrite32(temp_ctl, bridge->base + CA91CX42_LSI_CTL[i]); |
3d0f8bc7 MW |
756 | |
757 | spin_unlock(&(image->lock)); | |
758 | return 0; | |
759 | ||
760 | err_aspace: | |
761 | err_dwidth: | |
762 | ca91cx42_free_resource(image); | |
763 | err_res: | |
764 | err_window: | |
765 | return retval; | |
766 | } | |
767 | ||
768 | int __ca91cx42_master_get(struct vme_master_resource *image, int *enabled, | |
769 | unsigned long long *vme_base, unsigned long long *size, | |
770 | vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) | |
771 | { | |
772 | unsigned int i, ctl; | |
773 | unsigned long long pci_base, pci_bound, vme_offset; | |
29848ac9 MW |
774 | struct ca91cx42_driver *bridge; |
775 | ||
776 | bridge = image->parent->driver_priv; | |
3d0f8bc7 MW |
777 | |
778 | i = image->number; | |
779 | ||
29848ac9 | 780 | ctl = ioread32(bridge->base + CA91CX42_LSI_CTL[i]); |
3d0f8bc7 | 781 | |
29848ac9 MW |
782 | pci_base = ioread32(bridge->base + CA91CX42_LSI_BS[i]); |
783 | vme_offset = ioread32(bridge->base + CA91CX42_LSI_TO[i]); | |
784 | pci_bound = ioread32(bridge->base + CA91CX42_LSI_BD[i]); | |
3d0f8bc7 MW |
785 | |
786 | *vme_base = pci_base + vme_offset; | |
21e0cf6d | 787 | *size = (unsigned long long)(pci_bound - pci_base); |
3d0f8bc7 MW |
788 | |
789 | *enabled = 0; | |
790 | *aspace = 0; | |
791 | *cycle = 0; | |
792 | *dwidth = 0; | |
793 | ||
794 | if (ctl & CA91CX42_LSI_CTL_EN) | |
795 | *enabled = 1; | |
796 | ||
797 | /* Setup address space */ | |
798 | switch (ctl & CA91CX42_LSI_CTL_VAS_M) { | |
799 | case CA91CX42_LSI_CTL_VAS_A16: | |
800 | *aspace = VME_A16; | |
801 | break; | |
802 | case CA91CX42_LSI_CTL_VAS_A24: | |
803 | *aspace = VME_A24; | |
804 | break; | |
805 | case CA91CX42_LSI_CTL_VAS_A32: | |
806 | *aspace = VME_A32; | |
807 | break; | |
808 | case CA91CX42_LSI_CTL_VAS_CRCSR: | |
809 | *aspace = VME_CRCSR; | |
810 | break; | |
811 | case CA91CX42_LSI_CTL_VAS_USER1: | |
812 | *aspace = VME_USER1; | |
813 | break; | |
814 | case CA91CX42_LSI_CTL_VAS_USER2: | |
815 | *aspace = VME_USER2; | |
816 | break; | |
817 | } | |
818 | ||
819 | /* XXX Not sure howto check for MBLT */ | |
820 | /* Setup cycle types */ | |
821 | if (ctl & CA91CX42_LSI_CTL_VCT_BLT) | |
822 | *cycle |= VME_BLT; | |
823 | else | |
824 | *cycle |= VME_SCT; | |
825 | ||
826 | if (ctl & CA91CX42_LSI_CTL_SUPER_SUPR) | |
827 | *cycle |= VME_SUPER; | |
828 | else | |
829 | *cycle |= VME_USER; | |
830 | ||
831 | if (ctl & CA91CX42_LSI_CTL_PGM_PGM) | |
832 | *cycle = VME_PROG; | |
833 | else | |
834 | *cycle = VME_DATA; | |
835 | ||
836 | /* Setup data width */ | |
837 | switch (ctl & CA91CX42_LSI_CTL_VDW_M) { | |
838 | case CA91CX42_LSI_CTL_VDW_D8: | |
839 | *dwidth = VME_D8; | |
840 | break; | |
841 | case CA91CX42_LSI_CTL_VDW_D16: | |
842 | *dwidth = VME_D16; | |
843 | break; | |
844 | case CA91CX42_LSI_CTL_VDW_D32: | |
845 | *dwidth = VME_D32; | |
846 | break; | |
847 | case CA91CX42_LSI_CTL_VDW_D64: | |
848 | *dwidth = VME_D64; | |
849 | break; | |
850 | } | |
851 | ||
852 | /* XXX Prefetch stuff currently unsupported */ | |
853 | #if 0 | |
854 | if (ctl & 0x40000000) | |
855 | vmeOut->wrPostEnable = 1; | |
856 | #endif | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
861 | int ca91cx42_master_get(struct vme_master_resource *image, int *enabled, | |
862 | unsigned long long *vme_base, unsigned long long *size, | |
863 | vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth) | |
864 | { | |
865 | int retval; | |
866 | ||
867 | spin_lock(&(image->lock)); | |
868 | ||
869 | retval = __ca91cx42_master_get(image, enabled, vme_base, size, aspace, | |
870 | cycle, dwidth); | |
871 | ||
872 | spin_unlock(&(image->lock)); | |
873 | ||
874 | return retval; | |
875 | } | |
876 | ||
877 | ssize_t ca91cx42_master_read(struct vme_master_resource *image, void *buf, | |
878 | size_t count, loff_t offset) | |
879 | { | |
21e0cf6d | 880 | ssize_t retval; |
60479690 | 881 | |
3d0f8bc7 | 882 | spin_lock(&(image->lock)); |
60479690 | 883 | |
3d0f8bc7 MW |
884 | memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count); |
885 | retval = count; | |
60479690 | 886 | |
3d0f8bc7 MW |
887 | spin_unlock(&(image->lock)); |
888 | ||
889 | return retval; | |
60479690 MW |
890 | } |
891 | ||
3d0f8bc7 MW |
892 | ssize_t ca91cx42_master_write(struct vme_master_resource *image, void *buf, |
893 | size_t count, loff_t offset) | |
60479690 | 894 | { |
3d0f8bc7 | 895 | int retval = 0; |
60479690 | 896 | |
3d0f8bc7 | 897 | spin_lock(&(image->lock)); |
60479690 | 898 | |
3d0f8bc7 MW |
899 | memcpy_toio(image->kern_base + offset, buf, (unsigned int)count); |
900 | retval = count; | |
901 | ||
902 | spin_unlock(&(image->lock)); | |
903 | ||
904 | return retval; | |
60479690 MW |
905 | } |
906 | ||
4860ab74 MW |
907 | int ca91cx42_dma_list_add(struct vme_dma_list *list, struct vme_dma_attr *src, |
908 | struct vme_dma_attr *dest, size_t count) | |
909 | { | |
910 | struct ca91cx42_dma_entry *entry, *prev; | |
911 | struct vme_dma_pci *pci_attr; | |
912 | struct vme_dma_vme *vme_attr; | |
913 | dma_addr_t desc_ptr; | |
914 | int retval = 0; | |
915 | ||
916 | /* XXX descriptor must be aligned on 64-bit boundaries */ | |
917 | entry = (struct ca91cx42_dma_entry *) | |
918 | kmalloc(sizeof(struct ca91cx42_dma_entry), GFP_KERNEL); | |
919 | if (entry == NULL) { | |
920 | printk(KERN_ERR "Failed to allocate memory for dma resource " | |
921 | "structure\n"); | |
922 | retval = -ENOMEM; | |
923 | goto err_mem; | |
924 | } | |
925 | ||
926 | /* Test descriptor alignment */ | |
927 | if ((unsigned long)&(entry->descriptor) & CA91CX42_DCPP_M) { | |
928 | printk("Descriptor not aligned to 16 byte boundary as " | |
929 | "required: %p\n", &(entry->descriptor)); | |
930 | retval = -EINVAL; | |
931 | goto err_align; | |
932 | } | |
933 | ||
934 | memset(&(entry->descriptor), 0, sizeof(struct ca91cx42_dma_descriptor)); | |
935 | ||
936 | if (dest->type == VME_DMA_VME) { | |
937 | entry->descriptor.dctl |= CA91CX42_DCTL_L2V; | |
938 | vme_attr = (struct vme_dma_vme *)dest->private; | |
939 | pci_attr = (struct vme_dma_pci *)src->private; | |
940 | } else { | |
941 | vme_attr = (struct vme_dma_vme *)src->private; | |
942 | pci_attr = (struct vme_dma_pci *)dest->private; | |
943 | } | |
944 | ||
945 | /* Check we can do fullfill required attributes */ | |
946 | if ((vme_attr->aspace & ~(VME_A16 | VME_A24 | VME_A32 | VME_USER1 | | |
947 | VME_USER2)) != 0) { | |
948 | ||
949 | printk(KERN_ERR "Unsupported cycle type\n"); | |
950 | retval = -EINVAL; | |
951 | goto err_aspace; | |
952 | } | |
953 | ||
954 | if ((vme_attr->cycle & ~(VME_SCT | VME_BLT | VME_SUPER | VME_USER | | |
955 | VME_PROG | VME_DATA)) != 0) { | |
956 | ||
957 | printk(KERN_ERR "Unsupported cycle type\n"); | |
958 | retval = -EINVAL; | |
959 | goto err_cycle; | |
960 | } | |
961 | ||
962 | /* Check to see if we can fullfill source and destination */ | |
963 | if (!(((src->type == VME_DMA_PCI) && (dest->type == VME_DMA_VME)) || | |
964 | ((src->type == VME_DMA_VME) && (dest->type == VME_DMA_PCI)))) { | |
965 | ||
966 | printk(KERN_ERR "Cannot perform transfer with this " | |
967 | "source-destination combination\n"); | |
968 | retval = -EINVAL; | |
969 | goto err_direct; | |
970 | } | |
971 | ||
972 | /* Setup cycle types */ | |
973 | if (vme_attr->cycle & VME_BLT) | |
974 | entry->descriptor.dctl |= CA91CX42_DCTL_VCT_BLT; | |
975 | ||
976 | /* Setup data width */ | |
977 | switch (vme_attr->dwidth) { | |
978 | case VME_D8: | |
979 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D8; | |
980 | break; | |
981 | case VME_D16: | |
982 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D16; | |
983 | break; | |
984 | case VME_D32: | |
985 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D32; | |
986 | break; | |
987 | case VME_D64: | |
988 | entry->descriptor.dctl |= CA91CX42_DCTL_VDW_D64; | |
989 | break; | |
990 | default: | |
991 | printk(KERN_ERR "Invalid data width\n"); | |
992 | return -EINVAL; | |
993 | } | |
994 | ||
995 | /* Setup address space */ | |
996 | switch (vme_attr->aspace) { | |
997 | case VME_A16: | |
998 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A16; | |
999 | break; | |
1000 | case VME_A24: | |
1001 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A24; | |
1002 | break; | |
1003 | case VME_A32: | |
1004 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_A32; | |
1005 | break; | |
1006 | case VME_USER1: | |
1007 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER1; | |
1008 | break; | |
1009 | case VME_USER2: | |
1010 | entry->descriptor.dctl |= CA91CX42_DCTL_VAS_USER2; | |
1011 | break; | |
1012 | default: | |
1013 | printk(KERN_ERR "Invalid address space\n"); | |
1014 | return -EINVAL; | |
1015 | break; | |
1016 | } | |
1017 | ||
1018 | if (vme_attr->cycle & VME_SUPER) | |
1019 | entry->descriptor.dctl |= CA91CX42_DCTL_SUPER_SUPR; | |
1020 | if (vme_attr->cycle & VME_PROG) | |
1021 | entry->descriptor.dctl |= CA91CX42_DCTL_PGM_PGM; | |
1022 | ||
1023 | entry->descriptor.dtbc = count; | |
1024 | entry->descriptor.dla = pci_attr->address; | |
1025 | entry->descriptor.dva = vme_attr->address; | |
1026 | entry->descriptor.dcpp = CA91CX42_DCPP_NULL; | |
1027 | ||
1028 | /* Add to list */ | |
1029 | list_add_tail(&(entry->list), &(list->entries)); | |
1030 | ||
1031 | /* Fill out previous descriptors "Next Address" */ | |
1032 | if (entry->list.prev != &(list->entries)) { | |
1033 | prev = list_entry(entry->list.prev, struct ca91cx42_dma_entry, | |
1034 | list); | |
1035 | /* We need the bus address for the pointer */ | |
1036 | desc_ptr = virt_to_bus(&(entry->descriptor)); | |
1037 | prev->descriptor.dcpp = desc_ptr & ~CA91CX42_DCPP_M; | |
1038 | } | |
1039 | ||
1040 | return 0; | |
1041 | ||
1042 | err_cycle: | |
1043 | err_aspace: | |
1044 | err_direct: | |
1045 | err_align: | |
1046 | kfree(entry); | |
1047 | err_mem: | |
1048 | return retval; | |
1049 | } | |
1050 | ||
1051 | static int ca91cx42_dma_busy(struct vme_bridge *ca91cx42_bridge) | |
1052 | { | |
1053 | u32 tmp; | |
1054 | struct ca91cx42_driver *bridge; | |
1055 | ||
1056 | bridge = ca91cx42_bridge->driver_priv; | |
1057 | ||
1058 | tmp = ioread32(bridge->base + DGCS); | |
1059 | ||
1060 | if (tmp & CA91CX42_DGCS_ACT) | |
1061 | return 0; | |
1062 | else | |
1063 | return 1; | |
1064 | } | |
1065 | ||
1066 | int ca91cx42_dma_list_exec(struct vme_dma_list *list) | |
1067 | { | |
1068 | struct vme_dma_resource *ctrlr; | |
1069 | struct ca91cx42_dma_entry *entry; | |
1070 | int retval = 0; | |
1071 | dma_addr_t bus_addr; | |
1072 | u32 val; | |
1073 | ||
1074 | struct ca91cx42_driver *bridge; | |
1075 | ||
1076 | ctrlr = list->parent; | |
1077 | ||
1078 | bridge = ctrlr->parent->driver_priv; | |
1079 | ||
1080 | mutex_lock(&(ctrlr->mtx)); | |
1081 | ||
1082 | if (!(list_empty(&(ctrlr->running)))) { | |
1083 | /* | |
1084 | * XXX We have an active DMA transfer and currently haven't | |
1085 | * sorted out the mechanism for "pending" DMA transfers. | |
1086 | * Return busy. | |
1087 | */ | |
1088 | /* Need to add to pending here */ | |
1089 | mutex_unlock(&(ctrlr->mtx)); | |
1090 | return -EBUSY; | |
1091 | } else { | |
1092 | list_add(&(list->list), &(ctrlr->running)); | |
1093 | } | |
1094 | ||
1095 | /* Get first bus address and write into registers */ | |
1096 | entry = list_first_entry(&(list->entries), struct ca91cx42_dma_entry, | |
1097 | list); | |
1098 | ||
1099 | bus_addr = virt_to_bus(&(entry->descriptor)); | |
1100 | ||
1101 | mutex_unlock(&(ctrlr->mtx)); | |
1102 | ||
1103 | iowrite32(0, bridge->base + DTBC); | |
1104 | iowrite32(bus_addr & ~CA91CX42_DCPP_M, bridge->base + DCPP); | |
1105 | ||
1106 | /* Start the operation */ | |
1107 | val = ioread32(bridge->base + DGCS); | |
1108 | ||
1109 | /* XXX Could set VMEbus On and Off Counters here */ | |
1110 | val &= (CA91CX42_DGCS_VON_M | CA91CX42_DGCS_VOFF_M); | |
1111 | ||
1112 | val |= (CA91CX42_DGCS_CHAIN | CA91CX42_DGCS_STOP | CA91CX42_DGCS_HALT | | |
1113 | CA91CX42_DGCS_DONE | CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR | | |
1114 | CA91CX42_DGCS_PERR); | |
1115 | ||
1116 | iowrite32(val, bridge->base + DGCS); | |
1117 | ||
1118 | val |= CA91CX42_DGCS_GO; | |
1119 | ||
1120 | iowrite32(val, bridge->base + DGCS); | |
1121 | ||
1122 | wait_event_interruptible(bridge->dma_queue, | |
1123 | ca91cx42_dma_busy(ctrlr->parent)); | |
1124 | ||
1125 | /* | |
1126 | * Read status register, this register is valid until we kick off a | |
1127 | * new transfer. | |
1128 | */ | |
1129 | val = ioread32(bridge->base + DGCS); | |
1130 | ||
1131 | if (val & (CA91CX42_DGCS_LERR | CA91CX42_DGCS_VERR | | |
1132 | CA91CX42_DGCS_PERR)) { | |
1133 | ||
1134 | printk(KERN_ERR "ca91c042: DMA Error. DGCS=%08X\n", val); | |
1135 | val = ioread32(bridge->base + DCTL); | |
1136 | } | |
1137 | ||
1138 | /* Remove list from running list */ | |
1139 | mutex_lock(&(ctrlr->mtx)); | |
1140 | list_del(&(list->list)); | |
1141 | mutex_unlock(&(ctrlr->mtx)); | |
1142 | ||
1143 | return retval; | |
1144 | ||
1145 | } | |
1146 | ||
1147 | int ca91cx42_dma_list_empty(struct vme_dma_list *list) | |
1148 | { | |
1149 | struct list_head *pos, *temp; | |
1150 | struct ca91cx42_dma_entry *entry; | |
1151 | ||
1152 | /* detach and free each entry */ | |
1153 | list_for_each_safe(pos, temp, &(list->entries)) { | |
1154 | list_del(pos); | |
1155 | entry = list_entry(pos, struct ca91cx42_dma_entry, list); | |
1156 | kfree(entry); | |
1157 | } | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | ||
2b82beb8 MW |
1162 | /* |
1163 | * All 4 location monitors reside at the same base - this is therefore a | |
1164 | * system wide configuration. | |
1165 | * | |
1166 | * This does not enable the LM monitor - that should be done when the first | |
1167 | * callback is attached and disabled when the last callback is removed. | |
1168 | */ | |
1169 | int ca91cx42_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, | |
1170 | vme_address_t aspace, vme_cycle_t cycle) | |
1171 | { | |
1172 | u32 temp_base, lm_ctl = 0; | |
1173 | int i; | |
1174 | struct ca91cx42_driver *bridge; | |
1175 | struct device *dev; | |
1176 | ||
1177 | bridge = lm->parent->driver_priv; | |
1178 | dev = lm->parent->parent; | |
1179 | ||
1180 | /* Check the alignment of the location monitor */ | |
1181 | temp_base = (u32)lm_base; | |
1182 | if (temp_base & 0xffff) { | |
1183 | dev_err(dev, "Location monitor must be aligned to 64KB " | |
1184 | "boundary"); | |
1185 | return -EINVAL; | |
1186 | } | |
1187 | ||
1188 | mutex_lock(&(lm->mtx)); | |
1189 | ||
1190 | /* If we already have a callback attached, we can't move it! */ | |
1191 | for (i = 0; i < lm->monitors; i++) { | |
1192 | if (bridge->lm_callback[i] != NULL) { | |
1193 | mutex_unlock(&(lm->mtx)); | |
1194 | dev_err(dev, "Location monitor callback attached, " | |
1195 | "can't reset\n"); | |
1196 | return -EBUSY; | |
1197 | } | |
1198 | } | |
1199 | ||
1200 | switch (aspace) { | |
1201 | case VME_A16: | |
1202 | lm_ctl |= CA91CX42_LM_CTL_AS_A16; | |
1203 | break; | |
1204 | case VME_A24: | |
1205 | lm_ctl |= CA91CX42_LM_CTL_AS_A24; | |
1206 | break; | |
1207 | case VME_A32: | |
1208 | lm_ctl |= CA91CX42_LM_CTL_AS_A32; | |
1209 | break; | |
1210 | default: | |
1211 | mutex_unlock(&(lm->mtx)); | |
1212 | dev_err(dev, "Invalid address space\n"); | |
1213 | return -EINVAL; | |
1214 | break; | |
1215 | } | |
1216 | ||
1217 | if (cycle & VME_SUPER) | |
1218 | lm_ctl |= CA91CX42_LM_CTL_SUPR; | |
1219 | if (cycle & VME_USER) | |
1220 | lm_ctl |= CA91CX42_LM_CTL_NPRIV; | |
1221 | if (cycle & VME_PROG) | |
1222 | lm_ctl |= CA91CX42_LM_CTL_PGM; | |
1223 | if (cycle & VME_DATA) | |
1224 | lm_ctl |= CA91CX42_LM_CTL_DATA; | |
1225 | ||
1226 | iowrite32(lm_base, bridge->base + LM_BS); | |
1227 | iowrite32(lm_ctl, bridge->base + LM_CTL); | |
1228 | ||
1229 | mutex_unlock(&(lm->mtx)); | |
1230 | ||
1231 | return 0; | |
1232 | } | |
1233 | ||
1234 | /* Get configuration of the callback monitor and return whether it is enabled | |
1235 | * or disabled. | |
1236 | */ | |
1237 | int ca91cx42_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base, | |
1238 | vme_address_t *aspace, vme_cycle_t *cycle) | |
1239 | { | |
1240 | u32 lm_ctl, enabled = 0; | |
1241 | struct ca91cx42_driver *bridge; | |
1242 | ||
1243 | bridge = lm->parent->driver_priv; | |
1244 | ||
1245 | mutex_lock(&(lm->mtx)); | |
1246 | ||
1247 | *lm_base = (unsigned long long)ioread32(bridge->base + LM_BS); | |
1248 | lm_ctl = ioread32(bridge->base + LM_CTL); | |
1249 | ||
1250 | if (lm_ctl & CA91CX42_LM_CTL_EN) | |
1251 | enabled = 1; | |
1252 | ||
1253 | if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A16) | |
1254 | *aspace = VME_A16; | |
1255 | if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A24) | |
1256 | *aspace = VME_A24; | |
1257 | if ((lm_ctl & CA91CX42_LM_CTL_AS_M) == CA91CX42_LM_CTL_AS_A32) | |
1258 | *aspace = VME_A32; | |
1259 | ||
1260 | *cycle = 0; | |
1261 | if (lm_ctl & CA91CX42_LM_CTL_SUPR) | |
1262 | *cycle |= VME_SUPER; | |
1263 | if (lm_ctl & CA91CX42_LM_CTL_NPRIV) | |
1264 | *cycle |= VME_USER; | |
1265 | if (lm_ctl & CA91CX42_LM_CTL_PGM) | |
1266 | *cycle |= VME_PROG; | |
1267 | if (lm_ctl & CA91CX42_LM_CTL_DATA) | |
1268 | *cycle |= VME_DATA; | |
1269 | ||
1270 | mutex_unlock(&(lm->mtx)); | |
1271 | ||
1272 | return enabled; | |
1273 | } | |
1274 | ||
1275 | /* | |
1276 | * Attach a callback to a specific location monitor. | |
1277 | * | |
1278 | * Callback will be passed the monitor triggered. | |
1279 | */ | |
1280 | int ca91cx42_lm_attach(struct vme_lm_resource *lm, int monitor, | |
1281 | void (*callback)(int)) | |
1282 | { | |
1283 | u32 lm_ctl, tmp; | |
1284 | struct ca91cx42_driver *bridge; | |
1285 | struct device *dev; | |
1286 | ||
1287 | bridge = lm->parent->driver_priv; | |
1288 | dev = lm->parent->parent; | |
1289 | ||
1290 | mutex_lock(&(lm->mtx)); | |
1291 | ||
1292 | /* Ensure that the location monitor is configured - need PGM or DATA */ | |
1293 | lm_ctl = ioread32(bridge->base + LM_CTL); | |
1294 | if ((lm_ctl & (CA91CX42_LM_CTL_PGM | CA91CX42_LM_CTL_DATA)) == 0) { | |
1295 | mutex_unlock(&(lm->mtx)); | |
1296 | dev_err(dev, "Location monitor not properly configured\n"); | |
1297 | return -EINVAL; | |
1298 | } | |
1299 | ||
1300 | /* Check that a callback isn't already attached */ | |
1301 | if (bridge->lm_callback[monitor] != NULL) { | |
1302 | mutex_unlock(&(lm->mtx)); | |
1303 | dev_err(dev, "Existing callback attached\n"); | |
1304 | return -EBUSY; | |
1305 | } | |
1306 | ||
1307 | /* Attach callback */ | |
1308 | bridge->lm_callback[monitor] = callback; | |
1309 | ||
1310 | /* Enable Location Monitor interrupt */ | |
1311 | tmp = ioread32(bridge->base + LINT_EN); | |
1312 | tmp |= CA91CX42_LINT_LM[monitor]; | |
1313 | iowrite32(tmp, bridge->base + LINT_EN); | |
1314 | ||
1315 | /* Ensure that global Location Monitor Enable set */ | |
1316 | if ((lm_ctl & CA91CX42_LM_CTL_EN) == 0) { | |
1317 | lm_ctl |= CA91CX42_LM_CTL_EN; | |
1318 | iowrite32(lm_ctl, bridge->base + LM_CTL); | |
1319 | } | |
1320 | ||
1321 | mutex_unlock(&(lm->mtx)); | |
1322 | ||
1323 | return 0; | |
1324 | } | |
1325 | ||
1326 | /* | |
1327 | * Detach a callback function forn a specific location monitor. | |
1328 | */ | |
1329 | int ca91cx42_lm_detach(struct vme_lm_resource *lm, int monitor) | |
1330 | { | |
1331 | u32 tmp; | |
1332 | struct ca91cx42_driver *bridge; | |
1333 | ||
1334 | bridge = lm->parent->driver_priv; | |
1335 | ||
1336 | mutex_lock(&(lm->mtx)); | |
1337 | ||
1338 | /* Disable Location Monitor and ensure previous interrupts are clear */ | |
1339 | tmp = ioread32(bridge->base + LINT_EN); | |
1340 | tmp &= ~CA91CX42_LINT_LM[monitor]; | |
1341 | iowrite32(tmp, bridge->base + LINT_EN); | |
1342 | ||
1343 | iowrite32(CA91CX42_LINT_LM[monitor], | |
1344 | bridge->base + LINT_STAT); | |
1345 | ||
1346 | /* Detach callback */ | |
1347 | bridge->lm_callback[monitor] = NULL; | |
1348 | ||
1349 | /* If all location monitors disabled, disable global Location Monitor */ | |
1350 | if ((tmp & (CA91CX42_LINT_LM0 | CA91CX42_LINT_LM1 | CA91CX42_LINT_LM2 | | |
1351 | CA91CX42_LINT_LM3)) == 0) { | |
1352 | tmp = ioread32(bridge->base + LM_CTL); | |
1353 | tmp &= ~CA91CX42_LM_CTL_EN; | |
1354 | iowrite32(tmp, bridge->base + LM_CTL); | |
1355 | } | |
1356 | ||
1357 | mutex_unlock(&(lm->mtx)); | |
1358 | ||
1359 | return 0; | |
1360 | } | |
1361 | ||
29848ac9 | 1362 | int ca91cx42_slot_get(struct vme_bridge *ca91cx42_bridge) |
60479690 | 1363 | { |
3d0f8bc7 | 1364 | u32 slot = 0; |
29848ac9 MW |
1365 | struct ca91cx42_driver *bridge; |
1366 | ||
1367 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 1368 | |
12b2d5c0 | 1369 | if (!geoid) { |
29848ac9 | 1370 | slot = ioread32(bridge->base + VCSR_BS); |
12b2d5c0 MW |
1371 | slot = ((slot & CA91CX42_VCSR_BS_SLOT_M) >> 27); |
1372 | } else | |
1373 | slot = geoid; | |
1374 | ||
3d0f8bc7 MW |
1375 | return (int)slot; |
1376 | ||
1377 | } | |
1378 | ||
1379 | static int __init ca91cx42_init(void) | |
1380 | { | |
1381 | return pci_register_driver(&ca91cx42_driver); | |
1382 | } | |
1383 | ||
1384 | /* | |
1385 | * Configure CR/CSR space | |
1386 | * | |
1387 | * Access to the CR/CSR can be configured at power-up. The location of the | |
1388 | * CR/CSR registers in the CR/CSR address space is determined by the boards | |
1389 | * Auto-ID or Geographic address. This function ensures that the window is | |
1390 | * enabled at an offset consistent with the boards geopgraphic address. | |
1391 | */ | |
29848ac9 MW |
1392 | static int ca91cx42_crcsr_init(struct vme_bridge *ca91cx42_bridge, |
1393 | struct pci_dev *pdev) | |
3d0f8bc7 MW |
1394 | { |
1395 | unsigned int crcsr_addr; | |
1396 | int tmp, slot; | |
29848ac9 MW |
1397 | struct ca91cx42_driver *bridge; |
1398 | ||
1399 | bridge = ca91cx42_bridge->driver_priv; | |
3d0f8bc7 MW |
1400 | |
1401 | /* XXX We may need to set this somehow as the Universe II does not support | |
1402 | * geographical addressing. | |
1403 | */ | |
1404 | #if 0 | |
1405 | if (vme_slotnum != -1) | |
29848ac9 | 1406 | iowrite32(vme_slotnum << 27, bridge->base + VCSR_BS); |
3d0f8bc7 | 1407 | #endif |
29848ac9 | 1408 | slot = ca91cx42_slot_get(ca91cx42_bridge); |
3d0f8bc7 MW |
1409 | dev_info(&pdev->dev, "CR/CSR Offset: %d\n", slot); |
1410 | if (slot == 0) { | |
1411 | dev_err(&pdev->dev, "Slot number is unset, not configuring " | |
1412 | "CR/CSR space\n"); | |
1413 | return -EINVAL; | |
60479690 | 1414 | } |
3d0f8bc7 MW |
1415 | |
1416 | /* Allocate mem for CR/CSR image */ | |
29848ac9 MW |
1417 | bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, |
1418 | &(bridge->crcsr_bus)); | |
1419 | if (bridge->crcsr_kernel == NULL) { | |
3d0f8bc7 MW |
1420 | dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR " |
1421 | "image\n"); | |
1422 | return -ENOMEM; | |
60479690 MW |
1423 | } |
1424 | ||
29848ac9 | 1425 | memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE); |
60479690 | 1426 | |
3d0f8bc7 | 1427 | crcsr_addr = slot * (512 * 1024); |
29848ac9 | 1428 | iowrite32(bridge->crcsr_bus - crcsr_addr, bridge->base + VCSR_TO); |
60479690 | 1429 | |
29848ac9 | 1430 | tmp = ioread32(bridge->base + VCSR_CTL); |
3d0f8bc7 | 1431 | tmp |= CA91CX42_VCSR_CTL_EN; |
29848ac9 | 1432 | iowrite32(tmp, bridge->base + VCSR_CTL); |
60479690 | 1433 | |
3d0f8bc7 | 1434 | return 0; |
60479690 MW |
1435 | } |
1436 | ||
29848ac9 MW |
1437 | static void ca91cx42_crcsr_exit(struct vme_bridge *ca91cx42_bridge, |
1438 | struct pci_dev *pdev) | |
60479690 | 1439 | { |
3d0f8bc7 | 1440 | u32 tmp; |
29848ac9 MW |
1441 | struct ca91cx42_driver *bridge; |
1442 | ||
1443 | bridge = ca91cx42_bridge->driver_priv; | |
60479690 | 1444 | |
3d0f8bc7 | 1445 | /* Turn off CR/CSR space */ |
29848ac9 | 1446 | tmp = ioread32(bridge->base + VCSR_CTL); |
3d0f8bc7 | 1447 | tmp &= ~CA91CX42_VCSR_CTL_EN; |
29848ac9 | 1448 | iowrite32(tmp, bridge->base + VCSR_CTL); |
60479690 | 1449 | |
3d0f8bc7 | 1450 | /* Free image */ |
29848ac9 | 1451 | iowrite32(0, bridge->base + VCSR_TO); |
60479690 | 1452 | |
29848ac9 MW |
1453 | pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, |
1454 | bridge->crcsr_bus); | |
3d0f8bc7 | 1455 | } |
60479690 | 1456 | |
3d0f8bc7 MW |
1457 | static int ca91cx42_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
1458 | { | |
1459 | int retval, i; | |
1460 | u32 data; | |
1461 | struct list_head *pos = NULL; | |
29848ac9 MW |
1462 | struct vme_bridge *ca91cx42_bridge; |
1463 | struct ca91cx42_driver *ca91cx42_device; | |
3d0f8bc7 MW |
1464 | struct vme_master_resource *master_image; |
1465 | struct vme_slave_resource *slave_image; | |
3d0f8bc7 | 1466 | struct vme_dma_resource *dma_ctrlr; |
3d0f8bc7 MW |
1467 | struct vme_lm_resource *lm; |
1468 | ||
1469 | /* We want to support more than one of each bridge so we need to | |
1470 | * dynamically allocate the bridge structure | |
1471 | */ | |
1472 | ca91cx42_bridge = kmalloc(sizeof(struct vme_bridge), GFP_KERNEL); | |
1473 | ||
1474 | if (ca91cx42_bridge == NULL) { | |
1475 | dev_err(&pdev->dev, "Failed to allocate memory for device " | |
1476 | "structure\n"); | |
1477 | retval = -ENOMEM; | |
1478 | goto err_struct; | |
1479 | } | |
1480 | ||
1481 | memset(ca91cx42_bridge, 0, sizeof(struct vme_bridge)); | |
1482 | ||
29848ac9 MW |
1483 | ca91cx42_device = kmalloc(sizeof(struct ca91cx42_driver), GFP_KERNEL); |
1484 | ||
1485 | if (ca91cx42_device == NULL) { | |
1486 | dev_err(&pdev->dev, "Failed to allocate memory for device " | |
1487 | "structure\n"); | |
1488 | retval = -ENOMEM; | |
1489 | goto err_driver; | |
1490 | } | |
1491 | ||
1492 | memset(ca91cx42_device, 0, sizeof(struct ca91cx42_driver)); | |
1493 | ||
1494 | ca91cx42_bridge->driver_priv = ca91cx42_device; | |
1495 | ||
3d0f8bc7 MW |
1496 | /* Enable the device */ |
1497 | retval = pci_enable_device(pdev); | |
1498 | if (retval) { | |
1499 | dev_err(&pdev->dev, "Unable to enable device\n"); | |
1500 | goto err_enable; | |
1501 | } | |
1502 | ||
1503 | /* Map Registers */ | |
1504 | retval = pci_request_regions(pdev, driver_name); | |
1505 | if (retval) { | |
1506 | dev_err(&pdev->dev, "Unable to reserve resources\n"); | |
1507 | goto err_resource; | |
1508 | } | |
1509 | ||
1510 | /* map registers in BAR 0 */ | |
29848ac9 | 1511 | ca91cx42_device->base = ioremap_nocache(pci_resource_start(pdev, 0), |
3d0f8bc7 | 1512 | 4096); |
29848ac9 | 1513 | if (!ca91cx42_device->base) { |
3d0f8bc7 MW |
1514 | dev_err(&pdev->dev, "Unable to remap CRG region\n"); |
1515 | retval = -EIO; | |
1516 | goto err_remap; | |
1517 | } | |
1518 | ||
1519 | /* Check to see if the mapping worked out */ | |
29848ac9 | 1520 | data = ioread32(ca91cx42_device->base + CA91CX42_PCI_ID) & 0x0000FFFF; |
3d0f8bc7 MW |
1521 | if (data != PCI_VENDOR_ID_TUNDRA) { |
1522 | dev_err(&pdev->dev, "PCI_ID check failed\n"); | |
1523 | retval = -EIO; | |
1524 | goto err_test; | |
1525 | } | |
1526 | ||
1527 | /* Initialize wait queues & mutual exclusion flags */ | |
29848ac9 MW |
1528 | init_waitqueue_head(&(ca91cx42_device->dma_queue)); |
1529 | init_waitqueue_head(&(ca91cx42_device->iack_queue)); | |
1530 | mutex_init(&(ca91cx42_device->vme_int)); | |
1531 | mutex_init(&(ca91cx42_device->vme_rmw)); | |
3d0f8bc7 MW |
1532 | |
1533 | ca91cx42_bridge->parent = &(pdev->dev); | |
1534 | strcpy(ca91cx42_bridge->name, driver_name); | |
1535 | ||
1536 | /* Setup IRQ */ | |
1537 | retval = ca91cx42_irq_init(ca91cx42_bridge); | |
1538 | if (retval != 0) { | |
1539 | dev_err(&pdev->dev, "Chip Initialization failed.\n"); | |
1540 | goto err_irq; | |
1541 | } | |
1542 | ||
1543 | /* Add master windows to list */ | |
1544 | INIT_LIST_HEAD(&(ca91cx42_bridge->master_resources)); | |
1545 | for (i = 0; i < CA91C142_MAX_MASTER; i++) { | |
1546 | master_image = kmalloc(sizeof(struct vme_master_resource), | |
1547 | GFP_KERNEL); | |
1548 | if (master_image == NULL) { | |
1549 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
1550 | "master resource structure\n"); | |
1551 | retval = -ENOMEM; | |
1552 | goto err_master; | |
1553 | } | |
1554 | master_image->parent = ca91cx42_bridge; | |
1555 | spin_lock_init(&(master_image->lock)); | |
1556 | master_image->locked = 0; | |
1557 | master_image->number = i; | |
1558 | master_image->address_attr = VME_A16 | VME_A24 | VME_A32 | | |
1559 | VME_CRCSR | VME_USER1 | VME_USER2; | |
1560 | master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | | |
1561 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; | |
1562 | master_image->width_attr = VME_D8 | VME_D16 | VME_D32 | VME_D64; | |
8fafb476 | 1563 | memset(&(master_image->bus_resource), 0, |
3d0f8bc7 MW |
1564 | sizeof(struct resource)); |
1565 | master_image->kern_base = NULL; | |
1566 | list_add_tail(&(master_image->list), | |
1567 | &(ca91cx42_bridge->master_resources)); | |
1568 | } | |
1569 | ||
1570 | /* Add slave windows to list */ | |
1571 | INIT_LIST_HEAD(&(ca91cx42_bridge->slave_resources)); | |
1572 | for (i = 0; i < CA91C142_MAX_SLAVE; i++) { | |
1573 | slave_image = kmalloc(sizeof(struct vme_slave_resource), | |
1574 | GFP_KERNEL); | |
1575 | if (slave_image == NULL) { | |
1576 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
1577 | "slave resource structure\n"); | |
1578 | retval = -ENOMEM; | |
1579 | goto err_slave; | |
1580 | } | |
1581 | slave_image->parent = ca91cx42_bridge; | |
1582 | mutex_init(&(slave_image->mtx)); | |
1583 | slave_image->locked = 0; | |
1584 | slave_image->number = i; | |
1585 | slave_image->address_attr = VME_A24 | VME_A32 | VME_USER1 | | |
1586 | VME_USER2; | |
1587 | ||
1588 | /* Only windows 0 and 4 support A16 */ | |
1589 | if (i == 0 || i == 4) | |
1590 | slave_image->address_attr |= VME_A16; | |
1591 | ||
1592 | slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | | |
1593 | VME_SUPER | VME_USER | VME_PROG | VME_DATA; | |
1594 | list_add_tail(&(slave_image->list), | |
1595 | &(ca91cx42_bridge->slave_resources)); | |
1596 | } | |
4860ab74 | 1597 | |
3d0f8bc7 MW |
1598 | /* Add dma engines to list */ |
1599 | INIT_LIST_HEAD(&(ca91cx42_bridge->dma_resources)); | |
1600 | for (i = 0; i < CA91C142_MAX_DMA; i++) { | |
1601 | dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource), | |
1602 | GFP_KERNEL); | |
1603 | if (dma_ctrlr == NULL) { | |
1604 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
1605 | "dma resource structure\n"); | |
1606 | retval = -ENOMEM; | |
1607 | goto err_dma; | |
1608 | } | |
1609 | dma_ctrlr->parent = ca91cx42_bridge; | |
1610 | mutex_init(&(dma_ctrlr->mtx)); | |
1611 | dma_ctrlr->locked = 0; | |
1612 | dma_ctrlr->number = i; | |
4f723df4 MW |
1613 | dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | |
1614 | VME_DMA_MEM_TO_VME; | |
3d0f8bc7 MW |
1615 | INIT_LIST_HEAD(&(dma_ctrlr->pending)); |
1616 | INIT_LIST_HEAD(&(dma_ctrlr->running)); | |
1617 | list_add_tail(&(dma_ctrlr->list), | |
1618 | &(ca91cx42_bridge->dma_resources)); | |
1619 | } | |
4860ab74 | 1620 | |
3d0f8bc7 MW |
1621 | /* Add location monitor to list */ |
1622 | INIT_LIST_HEAD(&(ca91cx42_bridge->lm_resources)); | |
1623 | lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL); | |
1624 | if (lm == NULL) { | |
1625 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
1626 | "location monitor resource structure\n"); | |
1627 | retval = -ENOMEM; | |
1628 | goto err_lm; | |
1629 | } | |
1630 | lm->parent = ca91cx42_bridge; | |
1631 | mutex_init(&(lm->mtx)); | |
1632 | lm->locked = 0; | |
1633 | lm->number = 1; | |
1634 | lm->monitors = 4; | |
1635 | list_add_tail(&(lm->list), &(ca91cx42_bridge->lm_resources)); | |
1636 | ||
1637 | ca91cx42_bridge->slave_get = ca91cx42_slave_get; | |
1638 | ca91cx42_bridge->slave_set = ca91cx42_slave_set; | |
1639 | ca91cx42_bridge->master_get = ca91cx42_master_get; | |
1640 | ca91cx42_bridge->master_set = ca91cx42_master_set; | |
1641 | ca91cx42_bridge->master_read = ca91cx42_master_read; | |
1642 | ca91cx42_bridge->master_write = ca91cx42_master_write; | |
1643 | #if 0 | |
1644 | ca91cx42_bridge->master_rmw = ca91cx42_master_rmw; | |
4860ab74 | 1645 | #endif |
3d0f8bc7 MW |
1646 | ca91cx42_bridge->dma_list_add = ca91cx42_dma_list_add; |
1647 | ca91cx42_bridge->dma_list_exec = ca91cx42_dma_list_exec; | |
1648 | ca91cx42_bridge->dma_list_empty = ca91cx42_dma_list_empty; | |
c813f592 MW |
1649 | ca91cx42_bridge->irq_set = ca91cx42_irq_set; |
1650 | ca91cx42_bridge->irq_generate = ca91cx42_irq_generate; | |
3d0f8bc7 MW |
1651 | ca91cx42_bridge->lm_set = ca91cx42_lm_set; |
1652 | ca91cx42_bridge->lm_get = ca91cx42_lm_get; | |
1653 | ca91cx42_bridge->lm_attach = ca91cx42_lm_attach; | |
1654 | ca91cx42_bridge->lm_detach = ca91cx42_lm_detach; | |
3d0f8bc7 MW |
1655 | ca91cx42_bridge->slot_get = ca91cx42_slot_get; |
1656 | ||
29848ac9 | 1657 | data = ioread32(ca91cx42_device->base + MISC_CTL); |
3d0f8bc7 MW |
1658 | dev_info(&pdev->dev, "Board is%s the VME system controller\n", |
1659 | (data & CA91CX42_MISC_CTL_SYSCON) ? "" : " not"); | |
29848ac9 MW |
1660 | dev_info(&pdev->dev, "Slot ID is %d\n", |
1661 | ca91cx42_slot_get(ca91cx42_bridge)); | |
3d0f8bc7 | 1662 | |
29848ac9 | 1663 | if (ca91cx42_crcsr_init(ca91cx42_bridge, pdev)) { |
3d0f8bc7 MW |
1664 | dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); |
1665 | retval = -EINVAL; | |
1666 | #if 0 | |
1667 | goto err_crcsr; | |
1668 | #endif | |
60479690 | 1669 | } |
60479690 | 1670 | |
3d0f8bc7 MW |
1671 | /* Need to save ca91cx42_bridge pointer locally in link list for use in |
1672 | * ca91cx42_remove() | |
1673 | */ | |
1674 | retval = vme_register_bridge(ca91cx42_bridge); | |
1675 | if (retval != 0) { | |
1676 | dev_err(&pdev->dev, "Chip Registration failed.\n"); | |
1677 | goto err_reg; | |
1678 | } | |
1679 | ||
29848ac9 MW |
1680 | pci_set_drvdata(pdev, ca91cx42_bridge); |
1681 | ||
3d0f8bc7 MW |
1682 | return 0; |
1683 | ||
1684 | vme_unregister_bridge(ca91cx42_bridge); | |
1685 | err_reg: | |
29848ac9 | 1686 | ca91cx42_crcsr_exit(ca91cx42_bridge, pdev); |
70d7aa88 | 1687 | #if 0 |
3d0f8bc7 | 1688 | err_crcsr: |
70d7aa88 | 1689 | #endif |
3d0f8bc7 MW |
1690 | err_lm: |
1691 | /* resources are stored in link list */ | |
1692 | list_for_each(pos, &(ca91cx42_bridge->lm_resources)) { | |
1693 | lm = list_entry(pos, struct vme_lm_resource, list); | |
1694 | list_del(pos); | |
1695 | kfree(lm); | |
1696 | } | |
3d0f8bc7 MW |
1697 | err_dma: |
1698 | /* resources are stored in link list */ | |
1699 | list_for_each(pos, &(ca91cx42_bridge->dma_resources)) { | |
1700 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); | |
1701 | list_del(pos); | |
1702 | kfree(dma_ctrlr); | |
60479690 | 1703 | } |
3d0f8bc7 MW |
1704 | err_slave: |
1705 | /* resources are stored in link list */ | |
1706 | list_for_each(pos, &(ca91cx42_bridge->slave_resources)) { | |
1707 | slave_image = list_entry(pos, struct vme_slave_resource, list); | |
1708 | list_del(pos); | |
1709 | kfree(slave_image); | |
1710 | } | |
1711 | err_master: | |
1712 | /* resources are stored in link list */ | |
1713 | list_for_each(pos, &(ca91cx42_bridge->master_resources)) { | |
1714 | master_image = list_entry(pos, struct vme_master_resource, | |
1715 | list); | |
1716 | list_del(pos); | |
1717 | kfree(master_image); | |
1718 | } | |
1719 | ||
29848ac9 | 1720 | ca91cx42_irq_exit(ca91cx42_device, pdev); |
3d0f8bc7 MW |
1721 | err_irq: |
1722 | err_test: | |
29848ac9 | 1723 | iounmap(ca91cx42_device->base); |
3d0f8bc7 MW |
1724 | err_remap: |
1725 | pci_release_regions(pdev); | |
1726 | err_resource: | |
1727 | pci_disable_device(pdev); | |
1728 | err_enable: | |
29848ac9 MW |
1729 | kfree(ca91cx42_device); |
1730 | err_driver: | |
3d0f8bc7 MW |
1731 | kfree(ca91cx42_bridge); |
1732 | err_struct: | |
1733 | return retval; | |
60479690 | 1734 | |
60479690 MW |
1735 | } |
1736 | ||
3d0f8bc7 | 1737 | void ca91cx42_remove(struct pci_dev *pdev) |
60479690 | 1738 | { |
3d0f8bc7 MW |
1739 | struct list_head *pos = NULL; |
1740 | struct vme_master_resource *master_image; | |
1741 | struct vme_slave_resource *slave_image; | |
1742 | struct vme_dma_resource *dma_ctrlr; | |
1743 | struct vme_lm_resource *lm; | |
29848ac9 MW |
1744 | struct ca91cx42_driver *bridge; |
1745 | struct vme_bridge *ca91cx42_bridge = pci_get_drvdata(pdev); | |
1746 | ||
1747 | bridge = ca91cx42_bridge->driver_priv; | |
1748 | ||
60479690 | 1749 | |
3d0f8bc7 | 1750 | /* Turn off Ints */ |
29848ac9 | 1751 | iowrite32(0, bridge->base + LINT_EN); |
3d0f8bc7 MW |
1752 | |
1753 | /* Turn off the windows */ | |
29848ac9 MW |
1754 | iowrite32(0x00800000, bridge->base + LSI0_CTL); |
1755 | iowrite32(0x00800000, bridge->base + LSI1_CTL); | |
1756 | iowrite32(0x00800000, bridge->base + LSI2_CTL); | |
1757 | iowrite32(0x00800000, bridge->base + LSI3_CTL); | |
1758 | iowrite32(0x00800000, bridge->base + LSI4_CTL); | |
1759 | iowrite32(0x00800000, bridge->base + LSI5_CTL); | |
1760 | iowrite32(0x00800000, bridge->base + LSI6_CTL); | |
1761 | iowrite32(0x00800000, bridge->base + LSI7_CTL); | |
1762 | iowrite32(0x00F00000, bridge->base + VSI0_CTL); | |
1763 | iowrite32(0x00F00000, bridge->base + VSI1_CTL); | |
1764 | iowrite32(0x00F00000, bridge->base + VSI2_CTL); | |
1765 | iowrite32(0x00F00000, bridge->base + VSI3_CTL); | |
1766 | iowrite32(0x00F00000, bridge->base + VSI4_CTL); | |
1767 | iowrite32(0x00F00000, bridge->base + VSI5_CTL); | |
1768 | iowrite32(0x00F00000, bridge->base + VSI6_CTL); | |
1769 | iowrite32(0x00F00000, bridge->base + VSI7_CTL); | |
3d0f8bc7 MW |
1770 | |
1771 | vme_unregister_bridge(ca91cx42_bridge); | |
1772 | #if 0 | |
1773 | ca91cx42_crcsr_exit(pdev); | |
1774 | #endif | |
1775 | /* resources are stored in link list */ | |
1776 | list_for_each(pos, &(ca91cx42_bridge->lm_resources)) { | |
1777 | lm = list_entry(pos, struct vme_lm_resource, list); | |
1778 | list_del(pos); | |
1779 | kfree(lm); | |
60479690 | 1780 | } |
3d0f8bc7 MW |
1781 | |
1782 | /* resources are stored in link list */ | |
1783 | list_for_each(pos, &(ca91cx42_bridge->dma_resources)) { | |
1784 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); | |
1785 | list_del(pos); | |
1786 | kfree(dma_ctrlr); | |
60479690 MW |
1787 | } |
1788 | ||
3d0f8bc7 MW |
1789 | /* resources are stored in link list */ |
1790 | list_for_each(pos, &(ca91cx42_bridge->slave_resources)) { | |
1791 | slave_image = list_entry(pos, struct vme_slave_resource, list); | |
1792 | list_del(pos); | |
1793 | kfree(slave_image); | |
1794 | } | |
60479690 | 1795 | |
3d0f8bc7 MW |
1796 | /* resources are stored in link list */ |
1797 | list_for_each(pos, &(ca91cx42_bridge->master_resources)) { | |
1798 | master_image = list_entry(pos, struct vme_master_resource, | |
1799 | list); | |
1800 | list_del(pos); | |
1801 | kfree(master_image); | |
1802 | } | |
60479690 | 1803 | |
29848ac9 | 1804 | ca91cx42_irq_exit(bridge, pdev); |
60479690 | 1805 | |
29848ac9 | 1806 | iounmap(bridge->base); |
60479690 | 1807 | |
3d0f8bc7 | 1808 | pci_release_regions(pdev); |
60479690 | 1809 | |
3d0f8bc7 MW |
1810 | pci_disable_device(pdev); |
1811 | ||
1812 | kfree(ca91cx42_bridge); | |
60479690 MW |
1813 | } |
1814 | ||
3d0f8bc7 | 1815 | static void __exit ca91cx42_exit(void) |
60479690 | 1816 | { |
3d0f8bc7 MW |
1817 | pci_unregister_driver(&ca91cx42_driver); |
1818 | } | |
60479690 | 1819 | |
12b2d5c0 MW |
1820 | MODULE_PARM_DESC(geoid, "Override geographical addressing"); |
1821 | module_param(geoid, int, 0); | |
1822 | ||
3d0f8bc7 MW |
1823 | MODULE_DESCRIPTION("VME driver for the Tundra Universe II VME bridge"); |
1824 | MODULE_LICENSE("GPL"); | |
60479690 | 1825 | |
3d0f8bc7 MW |
1826 | module_init(ca91cx42_init); |
1827 | module_exit(ca91cx42_exit); | |
60479690 | 1828 | |
3d0f8bc7 MW |
1829 | /*---------------------------------------------------------------------------- |
1830 | * STAGING | |
1831 | *--------------------------------------------------------------------------*/ | |
1832 | ||
1833 | #if 0 | |
60479690 | 1834 | |
3d0f8bc7 | 1835 | int ca91cx42_master_rmw(vmeRmwCfg_t *vmeRmw) |
60479690 MW |
1836 | { |
1837 | int temp_ctl = 0; | |
1838 | int tempBS = 0; | |
1839 | int tempBD = 0; | |
1840 | int tempTO = 0; | |
1841 | int vmeBS = 0; | |
1842 | int vmeBD = 0; | |
1843 | int *rmw_pci_data_ptr = NULL; | |
1844 | int *vaDataPtr = NULL; | |
1845 | int i; | |
1846 | vmeOutWindowCfg_t vmeOut; | |
1847 | if (vmeRmw->maxAttempts < 1) { | |
3d0f8bc7 | 1848 | return -EINVAL; |
60479690 MW |
1849 | } |
1850 | if (vmeRmw->targetAddrU) { | |
3d0f8bc7 | 1851 | return -EINVAL; |
60479690 | 1852 | } |
3d0f8bc7 | 1853 | /* Find the PCI address that maps to the desired VME address */ |
60479690 | 1854 | for (i = 0; i < 8; i++) { |
29848ac9 | 1855 | temp_ctl = ioread32(bridge->base + |
3d0f8bc7 | 1856 | CA91CX42_LSI_CTL[i]); |
60479690 MW |
1857 | if ((temp_ctl & 0x80000000) == 0) { |
1858 | continue; | |
1859 | } | |
1860 | memset(&vmeOut, 0, sizeof(vmeOut)); | |
1861 | vmeOut.windowNbr = i; | |
3d0f8bc7 | 1862 | ca91cx42_get_out_bound(&vmeOut); |
60479690 MW |
1863 | if (vmeOut.addrSpace != vmeRmw->addrSpace) { |
1864 | continue; | |
1865 | } | |
29848ac9 MW |
1866 | tempBS = ioread32(bridge->base + CA91CX42_LSI_BS[i]); |
1867 | tempBD = ioread32(bridge->base + CA91CX42_LSI_BD[i]); | |
1868 | tempTO = ioread32(bridge->base + CA91CX42_LSI_TO[i]); | |
60479690 MW |
1869 | vmeBS = tempBS + tempTO; |
1870 | vmeBD = tempBD + tempTO; | |
1871 | if ((vmeRmw->targetAddr >= vmeBS) && | |
1872 | (vmeRmw->targetAddr < vmeBD)) { | |
1873 | rmw_pci_data_ptr = | |
1874 | (int *)(tempBS + (vmeRmw->targetAddr - vmeBS)); | |
1875 | vaDataPtr = | |
1876 | (int *)(out_image_va[i] + | |
1877 | (vmeRmw->targetAddr - vmeBS)); | |
1878 | break; | |
1879 | } | |
1880 | } | |
1881 | ||
3d0f8bc7 | 1882 | /* If no window - fail. */ |
60479690 | 1883 | if (rmw_pci_data_ptr == NULL) { |
3d0f8bc7 MW |
1884 | return -EINVAL; |
1885 | } | |
1886 | /* Setup the RMW registers. */ | |
29848ac9 MW |
1887 | iowrite32(0, bridge->base + SCYC_CTL); |
1888 | iowrite32(SWIZZLE(vmeRmw->enableMask), bridge->base + SCYC_EN); | |
1889 | iowrite32(SWIZZLE(vmeRmw->compareData), bridge->base + | |
3d0f8bc7 | 1890 | SCYC_CMP); |
29848ac9 MW |
1891 | iowrite32(SWIZZLE(vmeRmw->swapData), bridge->base + SCYC_SWP); |
1892 | iowrite32((int)rmw_pci_data_ptr, bridge->base + SCYC_ADDR); | |
1893 | iowrite32(1, bridge->base + SCYC_CTL); | |
3d0f8bc7 MW |
1894 | |
1895 | /* Run the RMW cycle until either success or max attempts. */ | |
60479690 MW |
1896 | vmeRmw->numAttempts = 1; |
1897 | while (vmeRmw->numAttempts <= vmeRmw->maxAttempts) { | |
1898 | ||
3d0f8bc7 | 1899 | if ((ioread32(vaDataPtr) & vmeRmw->enableMask) == |
60479690 MW |
1900 | (vmeRmw->swapData & vmeRmw->enableMask)) { |
1901 | ||
29848ac9 | 1902 | iowrite32(0, bridge->base + SCYC_CTL); |
60479690 MW |
1903 | break; |
1904 | ||
1905 | } | |
1906 | vmeRmw->numAttempts++; | |
1907 | } | |
1908 | ||
3d0f8bc7 | 1909 | /* If no success, set num Attempts to be greater than max attempts */ |
60479690 MW |
1910 | if (vmeRmw->numAttempts > vmeRmw->maxAttempts) { |
1911 | vmeRmw->numAttempts = vmeRmw->maxAttempts + 1; | |
1912 | } | |
1913 | ||
3d0f8bc7 | 1914 | return 0; |
60479690 MW |
1915 | } |
1916 | ||
3d0f8bc7 MW |
1917 | int ca91cx42_set_arbiter(vmeArbiterCfg_t *vmeArb) |
1918 | { | |
1919 | int temp_ctl = 0; | |
1920 | int vbto = 0; | |
60479690 | 1921 | |
29848ac9 | 1922 | temp_ctl = ioread32(bridge->base + MISC_CTL); |
3d0f8bc7 | 1923 | temp_ctl &= 0x00FFFFFF; |
60479690 | 1924 | |
3d0f8bc7 MW |
1925 | if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) { |
1926 | vbto = 7; | |
1927 | } else if (vmeArb->globalTimeoutTimer > 1024) { | |
1928 | return -EINVAL; | |
1929 | } else if (vmeArb->globalTimeoutTimer == 0) { | |
1930 | vbto = 0; | |
60479690 | 1931 | } else { |
3d0f8bc7 MW |
1932 | vbto = 1; |
1933 | while ((16 * (1 << (vbto - 1))) < vmeArb->globalTimeoutTimer) | |
1934 | vbto += 1; | |
60479690 | 1935 | } |
3d0f8bc7 MW |
1936 | temp_ctl |= (vbto << 28); |
1937 | ||
1938 | if (vmeArb->arbiterMode == VME_PRIORITY_MODE) | |
1939 | temp_ctl |= 1 << 26; | |
1940 | ||
1941 | if (vmeArb->arbiterTimeoutFlag) | |
1942 | temp_ctl |= 2 << 24; | |
1943 | ||
29848ac9 | 1944 | iowrite32(temp_ctl, bridge->base + MISC_CTL); |
3d0f8bc7 MW |
1945 | return 0; |
1946 | } | |
1947 | ||
1948 | int ca91cx42_get_arbiter(vmeArbiterCfg_t *vmeArb) | |
1949 | { | |
1950 | int temp_ctl = 0; | |
1951 | int vbto = 0; | |
1952 | ||
29848ac9 | 1953 | temp_ctl = ioread32(bridge->base + MISC_CTL); |
3d0f8bc7 MW |
1954 | |
1955 | vbto = (temp_ctl >> 28) & 0xF; | |
1956 | if (vbto != 0) | |
1957 | vmeArb->globalTimeoutTimer = (16 * (1 << (vbto - 1))); | |
1958 | ||
1959 | if (temp_ctl & (1 << 26)) | |
1960 | vmeArb->arbiterMode = VME_PRIORITY_MODE; | |
1961 | else | |
1962 | vmeArb->arbiterMode = VME_R_ROBIN_MODE; | |
1963 | ||
1964 | if (temp_ctl & (3 << 24)) | |
1965 | vmeArb->arbiterTimeoutFlag = 1; | |
1966 | ||
1967 | return 0; | |
1968 | } | |
1969 | ||
1970 | int ca91cx42_set_requestor(vmeRequesterCfg_t *vmeReq) | |
1971 | { | |
1972 | int temp_ctl = 0; | |
1973 | ||
29848ac9 | 1974 | temp_ctl = ioread32(bridge->base + MAST_CTL); |
3d0f8bc7 MW |
1975 | temp_ctl &= 0xFF0FFFFF; |
1976 | ||
1977 | if (vmeReq->releaseMode == 1) | |
1978 | temp_ctl |= (1 << 20); | |
1979 | ||
1980 | if (vmeReq->fairMode == 1) | |
1981 | temp_ctl |= (1 << 21); | |
1982 | ||
1983 | temp_ctl |= (vmeReq->requestLevel << 22); | |
1984 | ||
29848ac9 | 1985 | iowrite32(temp_ctl, bridge->base + MAST_CTL); |
3d0f8bc7 MW |
1986 | return 0; |
1987 | } | |
1988 | ||
1989 | int ca91cx42_get_requestor(vmeRequesterCfg_t *vmeReq) | |
1990 | { | |
1991 | int temp_ctl = 0; | |
1992 | ||
29848ac9 | 1993 | temp_ctl = ioread32(bridge->base + MAST_CTL); |
3d0f8bc7 MW |
1994 | |
1995 | if (temp_ctl & (1 << 20)) | |
1996 | vmeReq->releaseMode = 1; | |
1997 | ||
1998 | if (temp_ctl & (1 << 21)) | |
1999 | vmeReq->fairMode = 1; | |
2000 | ||
2001 | vmeReq->requestLevel = (temp_ctl & 0xC00000) >> 22; | |
2002 | ||
2003 | return 0; | |
60479690 | 2004 | } |
3d0f8bc7 MW |
2005 | |
2006 | ||
2007 | #endif |