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d22b8ed9 MW |
1 | /* |
2 | * Support for the Tundra TSI148 VME-PCI Bridge Chip | |
3 | * | |
66bd8db5 MW |
4 | * Author: Martyn Welch <martyn.welch@ge.com> |
5 | * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc. | |
d22b8ed9 MW |
6 | * |
7 | * Based on work by Tom Armistead and Ajit Prem | |
8 | * Copyright 2004 Motorola Inc. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License as published by the | |
12 | * Free Software Foundation; either version 2 of the License, or (at your | |
13 | * option) any later version. | |
14 | */ | |
15 | ||
d22b8ed9 MW |
16 | #include <linux/module.h> |
17 | #include <linux/moduleparam.h> | |
18 | #include <linux/mm.h> | |
19 | #include <linux/types.h> | |
20 | #include <linux/errno.h> | |
21 | #include <linux/proc_fs.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/poll.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/spinlock.h> | |
6af783c8 | 27 | #include <linux/sched.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
7946328f MW |
29 | #include <linux/time.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/uaccess.h> | |
d22b8ed9 MW |
32 | |
33 | #include "../vme.h" | |
34 | #include "../vme_bridge.h" | |
35 | #include "vme_tsi148.h" | |
36 | ||
37 | static int __init tsi148_init(void); | |
38 | static int tsi148_probe(struct pci_dev *, const struct pci_device_id *); | |
39 | static void tsi148_remove(struct pci_dev *); | |
40 | static void __exit tsi148_exit(void); | |
41 | ||
42 | ||
29848ac9 | 43 | /* Module parameter */ |
90ab5ee9 | 44 | static bool err_chk; |
638f199d | 45 | static int geoid; |
d22b8ed9 | 46 | |
584721ca | 47 | static const char driver_name[] = "vme_tsi148"; |
d22b8ed9 | 48 | |
270b64bb | 49 | static DEFINE_PCI_DEVICE_TABLE(tsi148_ids) = { |
d22b8ed9 MW |
50 | { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) }, |
51 | { }, | |
52 | }; | |
53 | ||
54 | static struct pci_driver tsi148_driver = { | |
55 | .name = driver_name, | |
56 | .id_table = tsi148_ids, | |
57 | .probe = tsi148_probe, | |
58 | .remove = tsi148_remove, | |
59 | }; | |
60 | ||
61 | static void reg_join(unsigned int high, unsigned int low, | |
62 | unsigned long long *variable) | |
63 | { | |
64 | *variable = (unsigned long long)high << 32; | |
65 | *variable |= (unsigned long long)low; | |
66 | } | |
67 | ||
68 | static void reg_split(unsigned long long variable, unsigned int *high, | |
69 | unsigned int *low) | |
70 | { | |
71 | *low = (unsigned int)variable & 0xFFFFFFFF; | |
72 | *high = (unsigned int)(variable >> 32); | |
73 | } | |
74 | ||
75 | /* | |
76 | * Wakes up DMA queue. | |
77 | */ | |
29848ac9 MW |
78 | static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge, |
79 | int channel_mask) | |
d22b8ed9 MW |
80 | { |
81 | u32 serviced = 0; | |
82 | ||
83 | if (channel_mask & TSI148_LCSR_INTS_DMA0S) { | |
886953e9 | 84 | wake_up(&bridge->dma_queue[0]); |
d22b8ed9 MW |
85 | serviced |= TSI148_LCSR_INTC_DMA0C; |
86 | } | |
87 | if (channel_mask & TSI148_LCSR_INTS_DMA1S) { | |
886953e9 | 88 | wake_up(&bridge->dma_queue[1]); |
d22b8ed9 MW |
89 | serviced |= TSI148_LCSR_INTC_DMA1C; |
90 | } | |
91 | ||
92 | return serviced; | |
93 | } | |
94 | ||
95 | /* | |
96 | * Wake up location monitor queue | |
97 | */ | |
29848ac9 | 98 | static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat) |
d22b8ed9 MW |
99 | { |
100 | int i; | |
101 | u32 serviced = 0; | |
102 | ||
103 | for (i = 0; i < 4; i++) { | |
7946328f | 104 | if (stat & TSI148_LCSR_INTS_LMS[i]) { |
d22b8ed9 | 105 | /* We only enable interrupts if the callback is set */ |
29848ac9 | 106 | bridge->lm_callback[i](i); |
d22b8ed9 MW |
107 | serviced |= TSI148_LCSR_INTC_LMC[i]; |
108 | } | |
109 | } | |
110 | ||
111 | return serviced; | |
112 | } | |
113 | ||
114 | /* | |
115 | * Wake up mail box queue. | |
116 | * | |
117 | * XXX This functionality is not exposed up though API. | |
118 | */ | |
48d9356e | 119 | static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat) |
d22b8ed9 MW |
120 | { |
121 | int i; | |
122 | u32 val; | |
123 | u32 serviced = 0; | |
48d9356e MW |
124 | struct tsi148_driver *bridge; |
125 | ||
126 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 MW |
127 | |
128 | for (i = 0; i < 4; i++) { | |
7946328f | 129 | if (stat & TSI148_LCSR_INTS_MBS[i]) { |
29848ac9 | 130 | val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]); |
48d9356e MW |
131 | dev_err(tsi148_bridge->parent, "VME Mailbox %d received" |
132 | ": 0x%x\n", i, val); | |
d22b8ed9 MW |
133 | serviced |= TSI148_LCSR_INTC_MBC[i]; |
134 | } | |
135 | } | |
136 | ||
137 | return serviced; | |
138 | } | |
139 | ||
140 | /* | |
141 | * Display error & status message when PERR (PCI) exception interrupt occurs. | |
142 | */ | |
48d9356e | 143 | static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge) |
d22b8ed9 | 144 | { |
48d9356e MW |
145 | struct tsi148_driver *bridge; |
146 | ||
147 | bridge = tsi148_bridge->driver_priv; | |
148 | ||
149 | dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, " | |
150 | "attributes: %08x\n", | |
29848ac9 MW |
151 | ioread32be(bridge->base + TSI148_LCSR_EDPAU), |
152 | ioread32be(bridge->base + TSI148_LCSR_EDPAL), | |
48d9356e MW |
153 | ioread32be(bridge->base + TSI148_LCSR_EDPAT)); |
154 | ||
155 | dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split " | |
156 | "completion reg: %08x\n", | |
29848ac9 | 157 | ioread32be(bridge->base + TSI148_LCSR_EDPXA), |
48d9356e | 158 | ioread32be(bridge->base + TSI148_LCSR_EDPXS)); |
d22b8ed9 | 159 | |
29848ac9 | 160 | iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT); |
d22b8ed9 MW |
161 | |
162 | return TSI148_LCSR_INTC_PERRC; | |
163 | } | |
164 | ||
165 | /* | |
166 | * Save address and status when VME error interrupt occurs. | |
167 | */ | |
29848ac9 | 168 | static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge) |
d22b8ed9 MW |
169 | { |
170 | unsigned int error_addr_high, error_addr_low; | |
171 | unsigned long long error_addr; | |
172 | u32 error_attrib; | |
173 | struct vme_bus_error *error; | |
29848ac9 MW |
174 | struct tsi148_driver *bridge; |
175 | ||
176 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 177 | |
29848ac9 MW |
178 | error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU); |
179 | error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL); | |
180 | error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT); | |
d22b8ed9 MW |
181 | |
182 | reg_join(error_addr_high, error_addr_low, &error_addr); | |
183 | ||
184 | /* Check for exception register overflow (we have lost error data) */ | |
7946328f | 185 | if (error_attrib & TSI148_LCSR_VEAT_VEOF) { |
48d9356e MW |
186 | dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow " |
187 | "Occurred\n"); | |
d22b8ed9 MW |
188 | } |
189 | ||
7946328f | 190 | error = kmalloc(sizeof(struct vme_bus_error), GFP_ATOMIC); |
d22b8ed9 MW |
191 | if (error) { |
192 | error->address = error_addr; | |
193 | error->attributes = error_attrib; | |
886953e9 | 194 | list_add_tail(&error->list, &tsi148_bridge->vme_errors); |
d22b8ed9 | 195 | } else { |
48d9356e MW |
196 | dev_err(tsi148_bridge->parent, "Unable to alloc memory for " |
197 | "VMEbus Error reporting\n"); | |
198 | dev_err(tsi148_bridge->parent, "VME Bus Error at address: " | |
199 | "0x%llx, attributes: %08x\n", error_addr, error_attrib); | |
d22b8ed9 MW |
200 | } |
201 | ||
202 | /* Clear Status */ | |
29848ac9 | 203 | iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT); |
d22b8ed9 MW |
204 | |
205 | return TSI148_LCSR_INTC_VERRC; | |
206 | } | |
207 | ||
208 | /* | |
209 | * Wake up IACK queue. | |
210 | */ | |
29848ac9 | 211 | static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge) |
d22b8ed9 | 212 | { |
886953e9 | 213 | wake_up(&bridge->iack_queue); |
d22b8ed9 MW |
214 | |
215 | return TSI148_LCSR_INTC_IACKC; | |
216 | } | |
217 | ||
218 | /* | |
219 | * Calling VME bus interrupt callback if provided. | |
220 | */ | |
29848ac9 MW |
221 | static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge, |
222 | u32 stat) | |
d22b8ed9 MW |
223 | { |
224 | int vec, i, serviced = 0; | |
29848ac9 MW |
225 | struct tsi148_driver *bridge; |
226 | ||
227 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 MW |
228 | |
229 | for (i = 7; i > 0; i--) { | |
230 | if (stat & (1 << i)) { | |
231 | /* | |
7946328f MW |
232 | * Note: Even though the registers are defined as |
233 | * 32-bits in the spec, we only want to issue 8-bit | |
234 | * IACK cycles on the bus, read from offset 3. | |
d22b8ed9 | 235 | */ |
29848ac9 | 236 | vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3); |
d22b8ed9 | 237 | |
c813f592 | 238 | vme_irq_handler(tsi148_bridge, i, vec); |
d22b8ed9 MW |
239 | |
240 | serviced |= (1 << i); | |
241 | } | |
242 | } | |
243 | ||
244 | return serviced; | |
245 | } | |
246 | ||
247 | /* | |
248 | * Top level interrupt handler. Clears appropriate interrupt status bits and | |
249 | * then calls appropriate sub handler(s). | |
250 | */ | |
29848ac9 | 251 | static irqreturn_t tsi148_irqhandler(int irq, void *ptr) |
d22b8ed9 MW |
252 | { |
253 | u32 stat, enable, serviced = 0; | |
29848ac9 MW |
254 | struct vme_bridge *tsi148_bridge; |
255 | struct tsi148_driver *bridge; | |
256 | ||
257 | tsi148_bridge = ptr; | |
258 | ||
259 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 MW |
260 | |
261 | /* Determine which interrupts are unmasked and set */ | |
29848ac9 MW |
262 | enable = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
263 | stat = ioread32be(bridge->base + TSI148_LCSR_INTS); | |
d22b8ed9 MW |
264 | |
265 | /* Only look at unmasked interrupts */ | |
266 | stat &= enable; | |
267 | ||
7946328f | 268 | if (unlikely(!stat)) |
d22b8ed9 | 269 | return IRQ_NONE; |
d22b8ed9 MW |
270 | |
271 | /* Call subhandlers as appropriate */ | |
272 | /* DMA irqs */ | |
273 | if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S)) | |
29848ac9 | 274 | serviced |= tsi148_DMA_irqhandler(bridge, stat); |
d22b8ed9 MW |
275 | |
276 | /* Location monitor irqs */ | |
277 | if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S | | |
278 | TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S)) | |
29848ac9 | 279 | serviced |= tsi148_LM_irqhandler(bridge, stat); |
d22b8ed9 MW |
280 | |
281 | /* Mail box irqs */ | |
282 | if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S | | |
283 | TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S)) | |
48d9356e | 284 | serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat); |
d22b8ed9 MW |
285 | |
286 | /* PCI bus error */ | |
287 | if (stat & TSI148_LCSR_INTS_PERRS) | |
48d9356e | 288 | serviced |= tsi148_PERR_irqhandler(tsi148_bridge); |
d22b8ed9 MW |
289 | |
290 | /* VME bus error */ | |
291 | if (stat & TSI148_LCSR_INTS_VERRS) | |
29848ac9 | 292 | serviced |= tsi148_VERR_irqhandler(tsi148_bridge); |
d22b8ed9 MW |
293 | |
294 | /* IACK irq */ | |
295 | if (stat & TSI148_LCSR_INTS_IACKS) | |
29848ac9 | 296 | serviced |= tsi148_IACK_irqhandler(bridge); |
d22b8ed9 MW |
297 | |
298 | /* VME bus irqs */ | |
299 | if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S | | |
300 | TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S | | |
301 | TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S | | |
302 | TSI148_LCSR_INTS_IRQ1S)) | |
29848ac9 | 303 | serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat); |
d22b8ed9 MW |
304 | |
305 | /* Clear serviced interrupts */ | |
29848ac9 | 306 | iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC); |
d22b8ed9 MW |
307 | |
308 | return IRQ_HANDLED; | |
309 | } | |
310 | ||
29848ac9 | 311 | static int tsi148_irq_init(struct vme_bridge *tsi148_bridge) |
d22b8ed9 MW |
312 | { |
313 | int result; | |
314 | unsigned int tmp; | |
315 | struct pci_dev *pdev; | |
29848ac9 MW |
316 | struct tsi148_driver *bridge; |
317 | ||
318 | pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev); | |
d22b8ed9 | 319 | |
29848ac9 | 320 | bridge = tsi148_bridge->driver_priv; |
d22b8ed9 MW |
321 | |
322 | /* Initialise list for VME bus errors */ | |
886953e9 | 323 | INIT_LIST_HEAD(&tsi148_bridge->vme_errors); |
d22b8ed9 | 324 | |
886953e9 | 325 | mutex_init(&tsi148_bridge->irq_mtx); |
c813f592 | 326 | |
d22b8ed9 MW |
327 | result = request_irq(pdev->irq, |
328 | tsi148_irqhandler, | |
329 | IRQF_SHARED, | |
29848ac9 | 330 | driver_name, tsi148_bridge); |
d22b8ed9 | 331 | if (result) { |
48d9356e MW |
332 | dev_err(tsi148_bridge->parent, "Can't get assigned pci irq " |
333 | "vector %02X\n", pdev->irq); | |
d22b8ed9 MW |
334 | return result; |
335 | } | |
336 | ||
337 | /* Enable and unmask interrupts */ | |
338 | tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO | | |
339 | TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO | | |
340 | TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO | | |
341 | TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO | | |
342 | TSI148_LCSR_INTEO_IACKEO; | |
343 | ||
29848ac9 | 344 | /* This leaves the following interrupts masked. |
d22b8ed9 MW |
345 | * TSI148_LCSR_INTEO_VIEEO |
346 | * TSI148_LCSR_INTEO_SYSFLEO | |
347 | * TSI148_LCSR_INTEO_ACFLEO | |
348 | */ | |
349 | ||
350 | /* Don't enable Location Monitor interrupts here - they will be | |
351 | * enabled when the location monitors are properly configured and | |
352 | * a callback has been attached. | |
353 | * TSI148_LCSR_INTEO_LM0EO | |
354 | * TSI148_LCSR_INTEO_LM1EO | |
355 | * TSI148_LCSR_INTEO_LM2EO | |
356 | * TSI148_LCSR_INTEO_LM3EO | |
357 | */ | |
358 | ||
359 | /* Don't enable VME interrupts until we add a handler, else the board | |
360 | * will respond to it and we don't want that unless it knows how to | |
361 | * properly deal with it. | |
362 | * TSI148_LCSR_INTEO_IRQ7EO | |
363 | * TSI148_LCSR_INTEO_IRQ6EO | |
364 | * TSI148_LCSR_INTEO_IRQ5EO | |
365 | * TSI148_LCSR_INTEO_IRQ4EO | |
366 | * TSI148_LCSR_INTEO_IRQ3EO | |
367 | * TSI148_LCSR_INTEO_IRQ2EO | |
368 | * TSI148_LCSR_INTEO_IRQ1EO | |
369 | */ | |
370 | ||
371 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); | |
372 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
a82ad05e EC |
377 | static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge, |
378 | struct pci_dev *pdev) | |
d22b8ed9 | 379 | { |
a82ad05e EC |
380 | struct tsi148_driver *bridge = tsi148_bridge->driver_priv; |
381 | ||
d22b8ed9 | 382 | /* Turn off interrupts */ |
29848ac9 MW |
383 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO); |
384 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN); | |
d22b8ed9 MW |
385 | |
386 | /* Clear all interrupts */ | |
29848ac9 | 387 | iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC); |
d22b8ed9 MW |
388 | |
389 | /* Detach interrupt handler */ | |
a82ad05e | 390 | free_irq(pdev->irq, tsi148_bridge); |
d22b8ed9 MW |
391 | } |
392 | ||
393 | /* | |
394 | * Check to see if an IACk has been received, return true (1) or false (0). | |
395 | */ | |
5ade6c4d | 396 | static int tsi148_iack_received(struct tsi148_driver *bridge) |
d22b8ed9 MW |
397 | { |
398 | u32 tmp; | |
399 | ||
29848ac9 | 400 | tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); |
d22b8ed9 MW |
401 | |
402 | if (tmp & TSI148_LCSR_VICR_IRQS) | |
403 | return 0; | |
404 | else | |
405 | return 1; | |
406 | } | |
407 | ||
408 | /* | |
c813f592 | 409 | * Configure VME interrupt |
d22b8ed9 | 410 | */ |
5ade6c4d | 411 | static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level, |
29848ac9 | 412 | int state, int sync) |
d22b8ed9 | 413 | { |
75155020 | 414 | struct pci_dev *pdev; |
c813f592 | 415 | u32 tmp; |
29848ac9 MW |
416 | struct tsi148_driver *bridge; |
417 | ||
418 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 419 | |
c813f592 MW |
420 | /* We need to do the ordering differently for enabling and disabling */ |
421 | if (state == 0) { | |
29848ac9 | 422 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
d22b8ed9 | 423 | tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1]; |
29848ac9 | 424 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); |
df455175 | 425 | |
29848ac9 | 426 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
df455175 | 427 | tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1]; |
29848ac9 | 428 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
75155020 | 429 | |
c813f592 MW |
430 | if (sync != 0) { |
431 | pdev = container_of(tsi148_bridge->parent, | |
432 | struct pci_dev, dev); | |
75155020 | 433 | |
c813f592 MW |
434 | synchronize_irq(pdev->irq); |
435 | } | |
436 | } else { | |
29848ac9 | 437 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
c813f592 | 438 | tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1]; |
29848ac9 | 439 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
df455175 | 440 | |
29848ac9 | 441 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
c813f592 | 442 | tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1]; |
29848ac9 | 443 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); |
c813f592 | 444 | } |
d22b8ed9 MW |
445 | } |
446 | ||
447 | /* | |
448 | * Generate a VME bus interrupt at the requested level & vector. Wait for | |
449 | * interrupt to be acked. | |
d22b8ed9 | 450 | */ |
5ade6c4d EC |
451 | static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level, |
452 | int statid) | |
d22b8ed9 MW |
453 | { |
454 | u32 tmp; | |
29848ac9 MW |
455 | struct tsi148_driver *bridge; |
456 | ||
457 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 458 | |
886953e9 | 459 | mutex_lock(&bridge->vme_int); |
d22b8ed9 MW |
460 | |
461 | /* Read VICR register */ | |
29848ac9 | 462 | tmp = ioread32be(bridge->base + TSI148_LCSR_VICR); |
d22b8ed9 MW |
463 | |
464 | /* Set Status/ID */ | |
465 | tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) | | |
466 | (statid & TSI148_LCSR_VICR_STID_M); | |
29848ac9 | 467 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); |
d22b8ed9 MW |
468 | |
469 | /* Assert VMEbus IRQ */ | |
470 | tmp = tmp | TSI148_LCSR_VICR_IRQL[level]; | |
29848ac9 | 471 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR); |
d22b8ed9 MW |
472 | |
473 | /* XXX Consider implementing a timeout? */ | |
29848ac9 MW |
474 | wait_event_interruptible(bridge->iack_queue, |
475 | tsi148_iack_received(bridge)); | |
d22b8ed9 | 476 | |
886953e9 | 477 | mutex_unlock(&bridge->vme_int); |
d22b8ed9 MW |
478 | |
479 | return 0; | |
480 | } | |
481 | ||
482 | /* | |
483 | * Find the first error in this address range | |
484 | */ | |
29848ac9 | 485 | static struct vme_bus_error *tsi148_find_error(struct vme_bridge *tsi148_bridge, |
6af04b06 | 486 | u32 aspace, unsigned long long address, size_t count) |
d22b8ed9 MW |
487 | { |
488 | struct list_head *err_pos; | |
489 | struct vme_bus_error *vme_err, *valid = NULL; | |
490 | unsigned long long bound; | |
491 | ||
492 | bound = address + count; | |
493 | ||
494 | /* | |
495 | * XXX We are currently not looking at the address space when parsing | |
496 | * for errors. This is because parsing the Address Modifier Codes | |
497 | * is going to be quite resource intensive to do properly. We | |
498 | * should be OK just looking at the addresses and this is certainly | |
499 | * much better than what we had before. | |
500 | */ | |
501 | err_pos = NULL; | |
502 | /* Iterate through errors */ | |
886953e9 | 503 | list_for_each(err_pos, &tsi148_bridge->vme_errors) { |
d22b8ed9 | 504 | vme_err = list_entry(err_pos, struct vme_bus_error, list); |
7946328f MW |
505 | if ((vme_err->address >= address) && |
506 | (vme_err->address < bound)) { | |
507 | ||
d22b8ed9 MW |
508 | valid = vme_err; |
509 | break; | |
510 | } | |
511 | } | |
512 | ||
513 | return valid; | |
514 | } | |
515 | ||
516 | /* | |
517 | * Clear errors in the provided address range. | |
518 | */ | |
29848ac9 | 519 | static void tsi148_clear_errors(struct vme_bridge *tsi148_bridge, |
6af04b06 | 520 | u32 aspace, unsigned long long address, size_t count) |
d22b8ed9 MW |
521 | { |
522 | struct list_head *err_pos, *temp; | |
523 | struct vme_bus_error *vme_err; | |
524 | unsigned long long bound; | |
525 | ||
526 | bound = address + count; | |
527 | ||
528 | /* | |
529 | * XXX We are currently not looking at the address space when parsing | |
530 | * for errors. This is because parsing the Address Modifier Codes | |
531 | * is going to be quite resource intensive to do properly. We | |
532 | * should be OK just looking at the addresses and this is certainly | |
533 | * much better than what we had before. | |
534 | */ | |
535 | err_pos = NULL; | |
536 | /* Iterate through errors */ | |
886953e9 | 537 | list_for_each_safe(err_pos, temp, &tsi148_bridge->vme_errors) { |
d22b8ed9 MW |
538 | vme_err = list_entry(err_pos, struct vme_bus_error, list); |
539 | ||
7946328f MW |
540 | if ((vme_err->address >= address) && |
541 | (vme_err->address < bound)) { | |
542 | ||
d22b8ed9 MW |
543 | list_del(err_pos); |
544 | kfree(vme_err); | |
545 | } | |
546 | } | |
547 | } | |
548 | ||
549 | /* | |
550 | * Initialize a slave window with the requested attributes. | |
551 | */ | |
5ade6c4d | 552 | static int tsi148_slave_set(struct vme_slave_resource *image, int enabled, |
d22b8ed9 | 553 | unsigned long long vme_base, unsigned long long size, |
6af04b06 | 554 | dma_addr_t pci_base, u32 aspace, u32 cycle) |
d22b8ed9 MW |
555 | { |
556 | unsigned int i, addr = 0, granularity = 0; | |
557 | unsigned int temp_ctl = 0; | |
558 | unsigned int vme_base_low, vme_base_high; | |
559 | unsigned int vme_bound_low, vme_bound_high; | |
560 | unsigned int pci_offset_low, pci_offset_high; | |
561 | unsigned long long vme_bound, pci_offset; | |
48d9356e | 562 | struct vme_bridge *tsi148_bridge; |
29848ac9 MW |
563 | struct tsi148_driver *bridge; |
564 | ||
48d9356e MW |
565 | tsi148_bridge = image->parent; |
566 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 567 | |
d22b8ed9 MW |
568 | i = image->number; |
569 | ||
570 | switch (aspace) { | |
571 | case VME_A16: | |
572 | granularity = 0x10; | |
573 | addr |= TSI148_LCSR_ITAT_AS_A16; | |
574 | break; | |
575 | case VME_A24: | |
576 | granularity = 0x1000; | |
577 | addr |= TSI148_LCSR_ITAT_AS_A24; | |
578 | break; | |
579 | case VME_A32: | |
580 | granularity = 0x10000; | |
581 | addr |= TSI148_LCSR_ITAT_AS_A32; | |
582 | break; | |
583 | case VME_A64: | |
584 | granularity = 0x10000; | |
585 | addr |= TSI148_LCSR_ITAT_AS_A64; | |
586 | break; | |
587 | case VME_CRCSR: | |
588 | case VME_USER1: | |
589 | case VME_USER2: | |
590 | case VME_USER3: | |
591 | case VME_USER4: | |
592 | default: | |
48d9356e | 593 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
d22b8ed9 MW |
594 | return -EINVAL; |
595 | break; | |
596 | } | |
597 | ||
598 | /* Convert 64-bit variables to 2x 32-bit variables */ | |
599 | reg_split(vme_base, &vme_base_high, &vme_base_low); | |
600 | ||
601 | /* | |
602 | * Bound address is a valid address for the window, adjust | |
603 | * accordingly | |
604 | */ | |
605 | vme_bound = vme_base + size - granularity; | |
606 | reg_split(vme_bound, &vme_bound_high, &vme_bound_low); | |
607 | pci_offset = (unsigned long long)pci_base - vme_base; | |
608 | reg_split(pci_offset, &pci_offset_high, &pci_offset_low); | |
609 | ||
610 | if (vme_base_low & (granularity - 1)) { | |
48d9356e | 611 | dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n"); |
d22b8ed9 MW |
612 | return -EINVAL; |
613 | } | |
614 | if (vme_bound_low & (granularity - 1)) { | |
48d9356e | 615 | dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n"); |
d22b8ed9 MW |
616 | return -EINVAL; |
617 | } | |
618 | if (pci_offset_low & (granularity - 1)) { | |
48d9356e MW |
619 | dev_err(tsi148_bridge->parent, "Invalid PCI Offset " |
620 | "alignment\n"); | |
d22b8ed9 MW |
621 | return -EINVAL; |
622 | } | |
623 | ||
d22b8ed9 | 624 | /* Disable while we are mucking around */ |
29848ac9 | 625 | temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
626 | TSI148_LCSR_OFFSET_ITAT); |
627 | temp_ctl &= ~TSI148_LCSR_ITAT_EN; | |
29848ac9 | 628 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
629 | TSI148_LCSR_OFFSET_ITAT); |
630 | ||
631 | /* Setup mapping */ | |
29848ac9 | 632 | iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 633 | TSI148_LCSR_OFFSET_ITSAU); |
29848ac9 | 634 | iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 635 | TSI148_LCSR_OFFSET_ITSAL); |
29848ac9 | 636 | iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 637 | TSI148_LCSR_OFFSET_ITEAU); |
29848ac9 | 638 | iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 639 | TSI148_LCSR_OFFSET_ITEAL); |
29848ac9 | 640 | iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 641 | TSI148_LCSR_OFFSET_ITOFU); |
29848ac9 | 642 | iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
643 | TSI148_LCSR_OFFSET_ITOFL); |
644 | ||
d22b8ed9 MW |
645 | /* Setup 2eSST speeds */ |
646 | temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M; | |
647 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { | |
648 | case VME_2eSST160: | |
649 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160; | |
650 | break; | |
651 | case VME_2eSST267: | |
652 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267; | |
653 | break; | |
654 | case VME_2eSST320: | |
655 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320; | |
656 | break; | |
657 | } | |
658 | ||
659 | /* Setup cycle types */ | |
660 | temp_ctl &= ~(0x1F << 7); | |
661 | if (cycle & VME_BLT) | |
662 | temp_ctl |= TSI148_LCSR_ITAT_BLT; | |
663 | if (cycle & VME_MBLT) | |
664 | temp_ctl |= TSI148_LCSR_ITAT_MBLT; | |
665 | if (cycle & VME_2eVME) | |
666 | temp_ctl |= TSI148_LCSR_ITAT_2eVME; | |
667 | if (cycle & VME_2eSST) | |
668 | temp_ctl |= TSI148_LCSR_ITAT_2eSST; | |
669 | if (cycle & VME_2eSSTB) | |
670 | temp_ctl |= TSI148_LCSR_ITAT_2eSSTB; | |
671 | ||
672 | /* Setup address space */ | |
673 | temp_ctl &= ~TSI148_LCSR_ITAT_AS_M; | |
674 | temp_ctl |= addr; | |
675 | ||
676 | temp_ctl &= ~0xF; | |
677 | if (cycle & VME_SUPER) | |
678 | temp_ctl |= TSI148_LCSR_ITAT_SUPR ; | |
679 | if (cycle & VME_USER) | |
680 | temp_ctl |= TSI148_LCSR_ITAT_NPRIV; | |
681 | if (cycle & VME_PROG) | |
682 | temp_ctl |= TSI148_LCSR_ITAT_PGM; | |
683 | if (cycle & VME_DATA) | |
684 | temp_ctl |= TSI148_LCSR_ITAT_DATA; | |
685 | ||
686 | /* Write ctl reg without enable */ | |
29848ac9 | 687 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
688 | TSI148_LCSR_OFFSET_ITAT); |
689 | ||
690 | if (enabled) | |
691 | temp_ctl |= TSI148_LCSR_ITAT_EN; | |
692 | ||
29848ac9 | 693 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
694 | TSI148_LCSR_OFFSET_ITAT); |
695 | ||
696 | return 0; | |
697 | } | |
698 | ||
699 | /* | |
700 | * Get slave window configuration. | |
d22b8ed9 | 701 | */ |
5ade6c4d | 702 | static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled, |
d22b8ed9 | 703 | unsigned long long *vme_base, unsigned long long *size, |
6af04b06 | 704 | dma_addr_t *pci_base, u32 *aspace, u32 *cycle) |
d22b8ed9 MW |
705 | { |
706 | unsigned int i, granularity = 0, ctl = 0; | |
707 | unsigned int vme_base_low, vme_base_high; | |
708 | unsigned int vme_bound_low, vme_bound_high; | |
709 | unsigned int pci_offset_low, pci_offset_high; | |
710 | unsigned long long vme_bound, pci_offset; | |
29848ac9 | 711 | struct tsi148_driver *bridge; |
d22b8ed9 | 712 | |
29848ac9 | 713 | bridge = image->parent->driver_priv; |
d22b8ed9 MW |
714 | |
715 | i = image->number; | |
716 | ||
717 | /* Read registers */ | |
29848ac9 | 718 | ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
719 | TSI148_LCSR_OFFSET_ITAT); |
720 | ||
29848ac9 | 721 | vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 722 | TSI148_LCSR_OFFSET_ITSAU); |
29848ac9 | 723 | vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 724 | TSI148_LCSR_OFFSET_ITSAL); |
29848ac9 | 725 | vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 726 | TSI148_LCSR_OFFSET_ITEAU); |
29848ac9 | 727 | vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 728 | TSI148_LCSR_OFFSET_ITEAL); |
29848ac9 | 729 | pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 730 | TSI148_LCSR_OFFSET_ITOFU); |
29848ac9 | 731 | pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 MW |
732 | TSI148_LCSR_OFFSET_ITOFL); |
733 | ||
734 | /* Convert 64-bit variables to 2x 32-bit variables */ | |
735 | reg_join(vme_base_high, vme_base_low, vme_base); | |
736 | reg_join(vme_bound_high, vme_bound_low, &vme_bound); | |
737 | reg_join(pci_offset_high, pci_offset_low, &pci_offset); | |
738 | ||
739 | *pci_base = (dma_addr_t)vme_base + pci_offset; | |
740 | ||
741 | *enabled = 0; | |
742 | *aspace = 0; | |
743 | *cycle = 0; | |
744 | ||
745 | if (ctl & TSI148_LCSR_ITAT_EN) | |
746 | *enabled = 1; | |
747 | ||
748 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) { | |
749 | granularity = 0x10; | |
750 | *aspace |= VME_A16; | |
751 | } | |
752 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) { | |
753 | granularity = 0x1000; | |
754 | *aspace |= VME_A24; | |
755 | } | |
756 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) { | |
757 | granularity = 0x10000; | |
758 | *aspace |= VME_A32; | |
759 | } | |
760 | if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) { | |
761 | granularity = 0x10000; | |
762 | *aspace |= VME_A64; | |
763 | } | |
764 | ||
765 | /* Need granularity before we set the size */ | |
766 | *size = (unsigned long long)((vme_bound - *vme_base) + granularity); | |
767 | ||
768 | ||
769 | if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160) | |
770 | *cycle |= VME_2eSST160; | |
771 | if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267) | |
772 | *cycle |= VME_2eSST267; | |
773 | if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320) | |
774 | *cycle |= VME_2eSST320; | |
775 | ||
776 | if (ctl & TSI148_LCSR_ITAT_BLT) | |
777 | *cycle |= VME_BLT; | |
778 | if (ctl & TSI148_LCSR_ITAT_MBLT) | |
779 | *cycle |= VME_MBLT; | |
780 | if (ctl & TSI148_LCSR_ITAT_2eVME) | |
781 | *cycle |= VME_2eVME; | |
782 | if (ctl & TSI148_LCSR_ITAT_2eSST) | |
783 | *cycle |= VME_2eSST; | |
784 | if (ctl & TSI148_LCSR_ITAT_2eSSTB) | |
785 | *cycle |= VME_2eSSTB; | |
786 | ||
787 | if (ctl & TSI148_LCSR_ITAT_SUPR) | |
788 | *cycle |= VME_SUPER; | |
789 | if (ctl & TSI148_LCSR_ITAT_NPRIV) | |
790 | *cycle |= VME_USER; | |
791 | if (ctl & TSI148_LCSR_ITAT_PGM) | |
792 | *cycle |= VME_PROG; | |
793 | if (ctl & TSI148_LCSR_ITAT_DATA) | |
794 | *cycle |= VME_DATA; | |
795 | ||
796 | return 0; | |
797 | } | |
798 | ||
799 | /* | |
800 | * Allocate and map PCI Resource | |
801 | */ | |
802 | static int tsi148_alloc_resource(struct vme_master_resource *image, | |
803 | unsigned long long size) | |
804 | { | |
805 | unsigned long long existing_size; | |
806 | int retval = 0; | |
807 | struct pci_dev *pdev; | |
29848ac9 MW |
808 | struct vme_bridge *tsi148_bridge; |
809 | ||
810 | tsi148_bridge = image->parent; | |
d22b8ed9 | 811 | |
48d9356e | 812 | pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev); |
d22b8ed9 | 813 | |
8fafb476 MW |
814 | existing_size = (unsigned long long)(image->bus_resource.end - |
815 | image->bus_resource.start); | |
d22b8ed9 MW |
816 | |
817 | /* If the existing size is OK, return */ | |
59c22904 | 818 | if ((size != 0) && (existing_size == (size - 1))) |
d22b8ed9 MW |
819 | return 0; |
820 | ||
821 | if (existing_size != 0) { | |
822 | iounmap(image->kern_base); | |
823 | image->kern_base = NULL; | |
794a8946 | 824 | kfree(image->bus_resource.name); |
886953e9 EC |
825 | release_resource(&image->bus_resource); |
826 | memset(&image->bus_resource, 0, sizeof(struct resource)); | |
d22b8ed9 MW |
827 | } |
828 | ||
59c22904 | 829 | /* Exit here if size is zero */ |
7946328f | 830 | if (size == 0) |
59c22904 | 831 | return 0; |
59c22904 | 832 | |
8fafb476 | 833 | if (image->bus_resource.name == NULL) { |
0aa3f139 | 834 | image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC); |
8fafb476 | 835 | if (image->bus_resource.name == NULL) { |
48d9356e MW |
836 | dev_err(tsi148_bridge->parent, "Unable to allocate " |
837 | "memory for resource name\n"); | |
d22b8ed9 MW |
838 | retval = -ENOMEM; |
839 | goto err_name; | |
840 | } | |
841 | } | |
842 | ||
8fafb476 | 843 | sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name, |
d22b8ed9 MW |
844 | image->number); |
845 | ||
8fafb476 MW |
846 | image->bus_resource.start = 0; |
847 | image->bus_resource.end = (unsigned long)size; | |
848 | image->bus_resource.flags = IORESOURCE_MEM; | |
d22b8ed9 MW |
849 | |
850 | retval = pci_bus_alloc_resource(pdev->bus, | |
886953e9 | 851 | &image->bus_resource, size, size, PCIBIOS_MIN_MEM, |
d22b8ed9 MW |
852 | 0, NULL, NULL); |
853 | if (retval) { | |
48d9356e MW |
854 | dev_err(tsi148_bridge->parent, "Failed to allocate mem " |
855 | "resource for window %d size 0x%lx start 0x%lx\n", | |
d22b8ed9 | 856 | image->number, (unsigned long)size, |
8fafb476 | 857 | (unsigned long)image->bus_resource.start); |
d22b8ed9 MW |
858 | goto err_resource; |
859 | } | |
860 | ||
861 | image->kern_base = ioremap_nocache( | |
8fafb476 | 862 | image->bus_resource.start, size); |
d22b8ed9 | 863 | if (image->kern_base == NULL) { |
48d9356e | 864 | dev_err(tsi148_bridge->parent, "Failed to remap resource\n"); |
d22b8ed9 MW |
865 | retval = -ENOMEM; |
866 | goto err_remap; | |
867 | } | |
868 | ||
869 | return 0; | |
870 | ||
d22b8ed9 | 871 | err_remap: |
886953e9 | 872 | release_resource(&image->bus_resource); |
d22b8ed9 | 873 | err_resource: |
8fafb476 | 874 | kfree(image->bus_resource.name); |
886953e9 | 875 | memset(&image->bus_resource, 0, sizeof(struct resource)); |
d22b8ed9 MW |
876 | err_name: |
877 | return retval; | |
878 | } | |
879 | ||
880 | /* | |
881 | * Free and unmap PCI Resource | |
882 | */ | |
883 | static void tsi148_free_resource(struct vme_master_resource *image) | |
884 | { | |
885 | iounmap(image->kern_base); | |
886 | image->kern_base = NULL; | |
886953e9 | 887 | release_resource(&image->bus_resource); |
8fafb476 | 888 | kfree(image->bus_resource.name); |
886953e9 | 889 | memset(&image->bus_resource, 0, sizeof(struct resource)); |
d22b8ed9 MW |
890 | } |
891 | ||
892 | /* | |
893 | * Set the attributes of an outbound window. | |
894 | */ | |
5ade6c4d | 895 | static int tsi148_master_set(struct vme_master_resource *image, int enabled, |
6af04b06 MW |
896 | unsigned long long vme_base, unsigned long long size, u32 aspace, |
897 | u32 cycle, u32 dwidth) | |
d22b8ed9 MW |
898 | { |
899 | int retval = 0; | |
900 | unsigned int i; | |
901 | unsigned int temp_ctl = 0; | |
902 | unsigned int pci_base_low, pci_base_high; | |
903 | unsigned int pci_bound_low, pci_bound_high; | |
904 | unsigned int vme_offset_low, vme_offset_high; | |
905 | unsigned long long pci_bound, vme_offset, pci_base; | |
48d9356e | 906 | struct vme_bridge *tsi148_bridge; |
29848ac9 MW |
907 | struct tsi148_driver *bridge; |
908 | ||
48d9356e MW |
909 | tsi148_bridge = image->parent; |
910 | ||
911 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 MW |
912 | |
913 | /* Verify input data */ | |
914 | if (vme_base & 0xFFFF) { | |
48d9356e MW |
915 | dev_err(tsi148_bridge->parent, "Invalid VME Window " |
916 | "alignment\n"); | |
d22b8ed9 MW |
917 | retval = -EINVAL; |
918 | goto err_window; | |
919 | } | |
59c22904 MW |
920 | |
921 | if ((size == 0) && (enabled != 0)) { | |
48d9356e MW |
922 | dev_err(tsi148_bridge->parent, "Size must be non-zero for " |
923 | "enabled windows\n"); | |
d22b8ed9 MW |
924 | retval = -EINVAL; |
925 | goto err_window; | |
926 | } | |
927 | ||
886953e9 | 928 | spin_lock(&image->lock); |
d22b8ed9 MW |
929 | |
930 | /* Let's allocate the resource here rather than further up the stack as | |
25985edc | 931 | * it avoids pushing loads of bus dependent stuff up the stack. If size |
59c22904 | 932 | * is zero, any existing resource will be freed. |
d22b8ed9 MW |
933 | */ |
934 | retval = tsi148_alloc_resource(image, size); | |
935 | if (retval) { | |
886953e9 | 936 | spin_unlock(&image->lock); |
48d9356e | 937 | dev_err(tsi148_bridge->parent, "Unable to allocate memory for " |
59c22904 | 938 | "resource\n"); |
d22b8ed9 MW |
939 | goto err_res; |
940 | } | |
941 | ||
59c22904 MW |
942 | if (size == 0) { |
943 | pci_base = 0; | |
944 | pci_bound = 0; | |
945 | vme_offset = 0; | |
946 | } else { | |
8fafb476 | 947 | pci_base = (unsigned long long)image->bus_resource.start; |
59c22904 MW |
948 | |
949 | /* | |
950 | * Bound address is a valid address for the window, adjust | |
951 | * according to window granularity. | |
952 | */ | |
953 | pci_bound = pci_base + (size - 0x10000); | |
954 | vme_offset = vme_base - pci_base; | |
955 | } | |
d22b8ed9 MW |
956 | |
957 | /* Convert 64-bit variables to 2x 32-bit variables */ | |
958 | reg_split(pci_base, &pci_base_high, &pci_base_low); | |
959 | reg_split(pci_bound, &pci_bound_high, &pci_bound_low); | |
960 | reg_split(vme_offset, &vme_offset_high, &vme_offset_low); | |
961 | ||
962 | if (pci_base_low & 0xFFFF) { | |
886953e9 | 963 | spin_unlock(&image->lock); |
48d9356e | 964 | dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n"); |
d22b8ed9 MW |
965 | retval = -EINVAL; |
966 | goto err_gran; | |
967 | } | |
968 | if (pci_bound_low & 0xFFFF) { | |
886953e9 | 969 | spin_unlock(&image->lock); |
48d9356e | 970 | dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n"); |
d22b8ed9 MW |
971 | retval = -EINVAL; |
972 | goto err_gran; | |
973 | } | |
974 | if (vme_offset_low & 0xFFFF) { | |
886953e9 | 975 | spin_unlock(&image->lock); |
48d9356e MW |
976 | dev_err(tsi148_bridge->parent, "Invalid VME Offset " |
977 | "alignment\n"); | |
d22b8ed9 MW |
978 | retval = -EINVAL; |
979 | goto err_gran; | |
980 | } | |
981 | ||
982 | i = image->number; | |
983 | ||
984 | /* Disable while we are mucking around */ | |
29848ac9 | 985 | temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
986 | TSI148_LCSR_OFFSET_OTAT); |
987 | temp_ctl &= ~TSI148_LCSR_OTAT_EN; | |
29848ac9 | 988 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
989 | TSI148_LCSR_OFFSET_OTAT); |
990 | ||
d22b8ed9 MW |
991 | /* Setup 2eSST speeds */ |
992 | temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M; | |
993 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { | |
994 | case VME_2eSST160: | |
995 | temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160; | |
996 | break; | |
997 | case VME_2eSST267: | |
998 | temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267; | |
999 | break; | |
1000 | case VME_2eSST320: | |
1001 | temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320; | |
1002 | break; | |
1003 | } | |
1004 | ||
1005 | /* Setup cycle types */ | |
1006 | if (cycle & VME_BLT) { | |
1007 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; | |
1008 | temp_ctl |= TSI148_LCSR_OTAT_TM_BLT; | |
1009 | } | |
1010 | if (cycle & VME_MBLT) { | |
1011 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; | |
1012 | temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT; | |
1013 | } | |
1014 | if (cycle & VME_2eVME) { | |
1015 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; | |
1016 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME; | |
1017 | } | |
1018 | if (cycle & VME_2eSST) { | |
1019 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; | |
1020 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST; | |
1021 | } | |
1022 | if (cycle & VME_2eSSTB) { | |
48d9356e MW |
1023 | dev_warn(tsi148_bridge->parent, "Currently not setting " |
1024 | "Broadcast Select Registers\n"); | |
d22b8ed9 MW |
1025 | temp_ctl &= ~TSI148_LCSR_OTAT_TM_M; |
1026 | temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB; | |
1027 | } | |
1028 | ||
1029 | /* Setup data width */ | |
1030 | temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M; | |
1031 | switch (dwidth) { | |
1032 | case VME_D16: | |
1033 | temp_ctl |= TSI148_LCSR_OTAT_DBW_16; | |
1034 | break; | |
1035 | case VME_D32: | |
1036 | temp_ctl |= TSI148_LCSR_OTAT_DBW_32; | |
1037 | break; | |
1038 | default: | |
886953e9 | 1039 | spin_unlock(&image->lock); |
48d9356e | 1040 | dev_err(tsi148_bridge->parent, "Invalid data width\n"); |
d22b8ed9 MW |
1041 | retval = -EINVAL; |
1042 | goto err_dwidth; | |
1043 | } | |
1044 | ||
1045 | /* Setup address space */ | |
1046 | temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M; | |
1047 | switch (aspace) { | |
1048 | case VME_A16: | |
1049 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16; | |
1050 | break; | |
1051 | case VME_A24: | |
1052 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24; | |
1053 | break; | |
1054 | case VME_A32: | |
1055 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32; | |
1056 | break; | |
1057 | case VME_A64: | |
1058 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64; | |
1059 | break; | |
1060 | case VME_CRCSR: | |
1061 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR; | |
1062 | break; | |
1063 | case VME_USER1: | |
1064 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1; | |
1065 | break; | |
1066 | case VME_USER2: | |
1067 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2; | |
1068 | break; | |
1069 | case VME_USER3: | |
1070 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3; | |
1071 | break; | |
1072 | case VME_USER4: | |
1073 | temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4; | |
1074 | break; | |
1075 | default: | |
886953e9 | 1076 | spin_unlock(&image->lock); |
48d9356e | 1077 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
d22b8ed9 MW |
1078 | retval = -EINVAL; |
1079 | goto err_aspace; | |
1080 | break; | |
1081 | } | |
1082 | ||
1083 | temp_ctl &= ~(3<<4); | |
1084 | if (cycle & VME_SUPER) | |
1085 | temp_ctl |= TSI148_LCSR_OTAT_SUP; | |
1086 | if (cycle & VME_PROG) | |
1087 | temp_ctl |= TSI148_LCSR_OTAT_PGM; | |
1088 | ||
1089 | /* Setup mapping */ | |
29848ac9 | 1090 | iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1091 | TSI148_LCSR_OFFSET_OTSAU); |
29848ac9 | 1092 | iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1093 | TSI148_LCSR_OFFSET_OTSAL); |
29848ac9 | 1094 | iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1095 | TSI148_LCSR_OFFSET_OTEAU); |
29848ac9 | 1096 | iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1097 | TSI148_LCSR_OFFSET_OTEAL); |
29848ac9 | 1098 | iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1099 | TSI148_LCSR_OFFSET_OTOFU); |
29848ac9 | 1100 | iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1101 | TSI148_LCSR_OFFSET_OTOFL); |
1102 | ||
d22b8ed9 | 1103 | /* Write ctl reg without enable */ |
29848ac9 | 1104 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1105 | TSI148_LCSR_OFFSET_OTAT); |
1106 | ||
1107 | if (enabled) | |
1108 | temp_ctl |= TSI148_LCSR_OTAT_EN; | |
1109 | ||
29848ac9 | 1110 | iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1111 | TSI148_LCSR_OFFSET_OTAT); |
1112 | ||
886953e9 | 1113 | spin_unlock(&image->lock); |
d22b8ed9 MW |
1114 | return 0; |
1115 | ||
1116 | err_aspace: | |
1117 | err_dwidth: | |
1118 | err_gran: | |
1119 | tsi148_free_resource(image); | |
1120 | err_res: | |
1121 | err_window: | |
1122 | return retval; | |
1123 | ||
1124 | } | |
1125 | ||
1126 | /* | |
1127 | * Set the attributes of an outbound window. | |
1128 | * | |
1129 | * XXX Not parsing prefetch information. | |
1130 | */ | |
5ade6c4d | 1131 | static int __tsi148_master_get(struct vme_master_resource *image, int *enabled, |
6af04b06 MW |
1132 | unsigned long long *vme_base, unsigned long long *size, u32 *aspace, |
1133 | u32 *cycle, u32 *dwidth) | |
d22b8ed9 MW |
1134 | { |
1135 | unsigned int i, ctl; | |
1136 | unsigned int pci_base_low, pci_base_high; | |
1137 | unsigned int pci_bound_low, pci_bound_high; | |
1138 | unsigned int vme_offset_low, vme_offset_high; | |
1139 | ||
1140 | unsigned long long pci_base, pci_bound, vme_offset; | |
29848ac9 MW |
1141 | struct tsi148_driver *bridge; |
1142 | ||
1143 | bridge = image->parent->driver_priv; | |
d22b8ed9 MW |
1144 | |
1145 | i = image->number; | |
1146 | ||
29848ac9 | 1147 | ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1148 | TSI148_LCSR_OFFSET_OTAT); |
1149 | ||
29848ac9 | 1150 | pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1151 | TSI148_LCSR_OFFSET_OTSAU); |
29848ac9 | 1152 | pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1153 | TSI148_LCSR_OFFSET_OTSAL); |
29848ac9 | 1154 | pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1155 | TSI148_LCSR_OFFSET_OTEAU); |
29848ac9 | 1156 | pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1157 | TSI148_LCSR_OFFSET_OTEAL); |
29848ac9 | 1158 | vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1159 | TSI148_LCSR_OFFSET_OTOFU); |
29848ac9 | 1160 | vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1161 | TSI148_LCSR_OFFSET_OTOFL); |
1162 | ||
1163 | /* Convert 64-bit variables to 2x 32-bit variables */ | |
1164 | reg_join(pci_base_high, pci_base_low, &pci_base); | |
1165 | reg_join(pci_bound_high, pci_bound_low, &pci_bound); | |
1166 | reg_join(vme_offset_high, vme_offset_low, &vme_offset); | |
1167 | ||
1168 | *vme_base = pci_base + vme_offset; | |
1169 | *size = (unsigned long long)(pci_bound - pci_base) + 0x10000; | |
1170 | ||
1171 | *enabled = 0; | |
1172 | *aspace = 0; | |
1173 | *cycle = 0; | |
1174 | *dwidth = 0; | |
1175 | ||
1176 | if (ctl & TSI148_LCSR_OTAT_EN) | |
1177 | *enabled = 1; | |
1178 | ||
1179 | /* Setup address space */ | |
1180 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16) | |
1181 | *aspace |= VME_A16; | |
1182 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24) | |
1183 | *aspace |= VME_A24; | |
1184 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32) | |
1185 | *aspace |= VME_A32; | |
1186 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64) | |
1187 | *aspace |= VME_A64; | |
1188 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR) | |
1189 | *aspace |= VME_CRCSR; | |
1190 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1) | |
1191 | *aspace |= VME_USER1; | |
1192 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2) | |
1193 | *aspace |= VME_USER2; | |
1194 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3) | |
1195 | *aspace |= VME_USER3; | |
1196 | if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4) | |
1197 | *aspace |= VME_USER4; | |
1198 | ||
1199 | /* Setup 2eSST speeds */ | |
1200 | if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160) | |
1201 | *cycle |= VME_2eSST160; | |
1202 | if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267) | |
1203 | *cycle |= VME_2eSST267; | |
1204 | if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320) | |
1205 | *cycle |= VME_2eSST320; | |
1206 | ||
1207 | /* Setup cycle types */ | |
7946328f | 1208 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT) |
d22b8ed9 | 1209 | *cycle |= VME_SCT; |
7946328f | 1210 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT) |
d22b8ed9 | 1211 | *cycle |= VME_BLT; |
7946328f | 1212 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT) |
d22b8ed9 | 1213 | *cycle |= VME_MBLT; |
7946328f | 1214 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME) |
d22b8ed9 | 1215 | *cycle |= VME_2eVME; |
7946328f | 1216 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST) |
d22b8ed9 | 1217 | *cycle |= VME_2eSST; |
7946328f | 1218 | if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB) |
d22b8ed9 MW |
1219 | *cycle |= VME_2eSSTB; |
1220 | ||
1221 | if (ctl & TSI148_LCSR_OTAT_SUP) | |
1222 | *cycle |= VME_SUPER; | |
1223 | else | |
1224 | *cycle |= VME_USER; | |
1225 | ||
1226 | if (ctl & TSI148_LCSR_OTAT_PGM) | |
1227 | *cycle |= VME_PROG; | |
1228 | else | |
1229 | *cycle |= VME_DATA; | |
1230 | ||
1231 | /* Setup data width */ | |
1232 | if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16) | |
1233 | *dwidth = VME_D16; | |
1234 | if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32) | |
1235 | *dwidth = VME_D32; | |
1236 | ||
1237 | return 0; | |
1238 | } | |
1239 | ||
1240 | ||
5ade6c4d | 1241 | static int tsi148_master_get(struct vme_master_resource *image, int *enabled, |
6af04b06 MW |
1242 | unsigned long long *vme_base, unsigned long long *size, u32 *aspace, |
1243 | u32 *cycle, u32 *dwidth) | |
d22b8ed9 MW |
1244 | { |
1245 | int retval; | |
1246 | ||
886953e9 | 1247 | spin_lock(&image->lock); |
d22b8ed9 MW |
1248 | |
1249 | retval = __tsi148_master_get(image, enabled, vme_base, size, aspace, | |
1250 | cycle, dwidth); | |
1251 | ||
886953e9 | 1252 | spin_unlock(&image->lock); |
d22b8ed9 MW |
1253 | |
1254 | return retval; | |
1255 | } | |
1256 | ||
5ade6c4d | 1257 | static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf, |
d22b8ed9 MW |
1258 | size_t count, loff_t offset) |
1259 | { | |
1260 | int retval, enabled; | |
1261 | unsigned long long vme_base, size; | |
6af04b06 | 1262 | u32 aspace, cycle, dwidth; |
d22b8ed9 | 1263 | struct vme_bus_error *vme_err = NULL; |
29848ac9 MW |
1264 | struct vme_bridge *tsi148_bridge; |
1265 | ||
1266 | tsi148_bridge = image->parent; | |
d22b8ed9 | 1267 | |
886953e9 | 1268 | spin_lock(&image->lock); |
d22b8ed9 MW |
1269 | |
1270 | memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count); | |
1271 | retval = count; | |
1272 | ||
1273 | if (!err_chk) | |
1274 | goto skip_chk; | |
1275 | ||
1276 | __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle, | |
1277 | &dwidth); | |
1278 | ||
29848ac9 MW |
1279 | vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, |
1280 | count); | |
7946328f | 1281 | if (vme_err != NULL) { |
d22b8ed9 MW |
1282 | dev_err(image->parent->parent, "First VME read error detected " |
1283 | "an at address 0x%llx\n", vme_err->address); | |
1284 | retval = vme_err->address - (vme_base + offset); | |
1285 | /* Clear down save errors in this address range */ | |
29848ac9 MW |
1286 | tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, |
1287 | count); | |
d22b8ed9 MW |
1288 | } |
1289 | ||
1290 | skip_chk: | |
886953e9 | 1291 | spin_unlock(&image->lock); |
d22b8ed9 MW |
1292 | |
1293 | return retval; | |
1294 | } | |
1295 | ||
1296 | ||
5ade6c4d | 1297 | static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf, |
d22b8ed9 MW |
1298 | size_t count, loff_t offset) |
1299 | { | |
1300 | int retval = 0, enabled; | |
1301 | unsigned long long vme_base, size; | |
6af04b06 | 1302 | u32 aspace, cycle, dwidth; |
d22b8ed9 MW |
1303 | |
1304 | struct vme_bus_error *vme_err = NULL; | |
29848ac9 MW |
1305 | struct vme_bridge *tsi148_bridge; |
1306 | struct tsi148_driver *bridge; | |
1307 | ||
1308 | tsi148_bridge = image->parent; | |
1309 | ||
1310 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 1311 | |
886953e9 | 1312 | spin_lock(&image->lock); |
d22b8ed9 MW |
1313 | |
1314 | memcpy_toio(image->kern_base + offset, buf, (unsigned int)count); | |
1315 | retval = count; | |
1316 | ||
1317 | /* | |
1318 | * Writes are posted. We need to do a read on the VME bus to flush out | |
25985edc | 1319 | * all of the writes before we check for errors. We can't guarantee |
d22b8ed9 MW |
1320 | * that reading the data we have just written is safe. It is believed |
1321 | * that there isn't any read, write re-ordering, so we can read any | |
1322 | * location in VME space, so lets read the Device ID from the tsi148's | |
1323 | * own registers as mapped into CR/CSR space. | |
1324 | * | |
1325 | * We check for saved errors in the written address range/space. | |
1326 | */ | |
1327 | ||
1328 | if (!err_chk) | |
1329 | goto skip_chk; | |
1330 | ||
1331 | /* | |
1332 | * Get window info first, to maximise the time that the buffers may | |
1333 | * fluch on their own | |
1334 | */ | |
1335 | __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle, | |
1336 | &dwidth); | |
1337 | ||
29848ac9 | 1338 | ioread16(bridge->flush_image->kern_base + 0x7F000); |
d22b8ed9 | 1339 | |
29848ac9 MW |
1340 | vme_err = tsi148_find_error(tsi148_bridge, aspace, vme_base + offset, |
1341 | count); | |
7946328f | 1342 | if (vme_err != NULL) { |
48d9356e MW |
1343 | dev_warn(tsi148_bridge->parent, "First VME write error detected" |
1344 | " an at address 0x%llx\n", vme_err->address); | |
d22b8ed9 MW |
1345 | retval = vme_err->address - (vme_base + offset); |
1346 | /* Clear down save errors in this address range */ | |
29848ac9 MW |
1347 | tsi148_clear_errors(tsi148_bridge, aspace, vme_base + offset, |
1348 | count); | |
d22b8ed9 MW |
1349 | } |
1350 | ||
1351 | skip_chk: | |
886953e9 | 1352 | spin_unlock(&image->lock); |
d22b8ed9 MW |
1353 | |
1354 | return retval; | |
1355 | } | |
1356 | ||
1357 | /* | |
1358 | * Perform an RMW cycle on the VME bus. | |
1359 | * | |
1360 | * Requires a previously configured master window, returns final value. | |
1361 | */ | |
5ade6c4d | 1362 | static unsigned int tsi148_master_rmw(struct vme_master_resource *image, |
d22b8ed9 MW |
1363 | unsigned int mask, unsigned int compare, unsigned int swap, |
1364 | loff_t offset) | |
1365 | { | |
1366 | unsigned long long pci_addr; | |
1367 | unsigned int pci_addr_high, pci_addr_low; | |
1368 | u32 tmp, result; | |
1369 | int i; | |
29848ac9 | 1370 | struct tsi148_driver *bridge; |
d22b8ed9 | 1371 | |
29848ac9 | 1372 | bridge = image->parent->driver_priv; |
d22b8ed9 MW |
1373 | |
1374 | /* Find the PCI address that maps to the desired VME address */ | |
1375 | i = image->number; | |
1376 | ||
1377 | /* Locking as we can only do one of these at a time */ | |
886953e9 | 1378 | mutex_lock(&bridge->vme_rmw); |
d22b8ed9 MW |
1379 | |
1380 | /* Lock image */ | |
886953e9 | 1381 | spin_lock(&image->lock); |
d22b8ed9 | 1382 | |
29848ac9 | 1383 | pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 | 1384 | TSI148_LCSR_OFFSET_OTSAU); |
29848ac9 | 1385 | pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
1386 | TSI148_LCSR_OFFSET_OTSAL); |
1387 | ||
1388 | reg_join(pci_addr_high, pci_addr_low, &pci_addr); | |
1389 | reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low); | |
1390 | ||
1391 | /* Configure registers */ | |
29848ac9 MW |
1392 | iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN); |
1393 | iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC); | |
1394 | iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS); | |
1395 | iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU); | |
1396 | iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL); | |
d22b8ed9 MW |
1397 | |
1398 | /* Enable RMW */ | |
29848ac9 | 1399 | tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); |
d22b8ed9 | 1400 | tmp |= TSI148_LCSR_VMCTRL_RMWEN; |
29848ac9 | 1401 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); |
d22b8ed9 MW |
1402 | |
1403 | /* Kick process off with a read to the required address. */ | |
1404 | result = ioread32be(image->kern_base + offset); | |
1405 | ||
1406 | /* Disable RMW */ | |
29848ac9 | 1407 | tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL); |
d22b8ed9 | 1408 | tmp &= ~TSI148_LCSR_VMCTRL_RMWEN; |
29848ac9 | 1409 | iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL); |
d22b8ed9 | 1410 | |
886953e9 | 1411 | spin_unlock(&image->lock); |
d22b8ed9 | 1412 | |
886953e9 | 1413 | mutex_unlock(&bridge->vme_rmw); |
d22b8ed9 MW |
1414 | |
1415 | return result; | |
1416 | } | |
1417 | ||
48d9356e | 1418 | static int tsi148_dma_set_vme_src_attributes(struct device *dev, u32 *attr, |
6af04b06 | 1419 | u32 aspace, u32 cycle, u32 dwidth) |
d22b8ed9 MW |
1420 | { |
1421 | /* Setup 2eSST speeds */ | |
1422 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { | |
1423 | case VME_2eSST160: | |
1424 | *attr |= TSI148_LCSR_DSAT_2eSSTM_160; | |
1425 | break; | |
1426 | case VME_2eSST267: | |
1427 | *attr |= TSI148_LCSR_DSAT_2eSSTM_267; | |
1428 | break; | |
1429 | case VME_2eSST320: | |
1430 | *attr |= TSI148_LCSR_DSAT_2eSSTM_320; | |
1431 | break; | |
1432 | } | |
1433 | ||
1434 | /* Setup cycle types */ | |
7946328f | 1435 | if (cycle & VME_SCT) |
d22b8ed9 | 1436 | *attr |= TSI148_LCSR_DSAT_TM_SCT; |
7946328f MW |
1437 | |
1438 | if (cycle & VME_BLT) | |
d22b8ed9 | 1439 | *attr |= TSI148_LCSR_DSAT_TM_BLT; |
7946328f MW |
1440 | |
1441 | if (cycle & VME_MBLT) | |
d22b8ed9 | 1442 | *attr |= TSI148_LCSR_DSAT_TM_MBLT; |
7946328f MW |
1443 | |
1444 | if (cycle & VME_2eVME) | |
d22b8ed9 | 1445 | *attr |= TSI148_LCSR_DSAT_TM_2eVME; |
7946328f MW |
1446 | |
1447 | if (cycle & VME_2eSST) | |
d22b8ed9 | 1448 | *attr |= TSI148_LCSR_DSAT_TM_2eSST; |
7946328f | 1449 | |
d22b8ed9 | 1450 | if (cycle & VME_2eSSTB) { |
48d9356e MW |
1451 | dev_err(dev, "Currently not setting Broadcast Select " |
1452 | "Registers\n"); | |
d22b8ed9 MW |
1453 | *attr |= TSI148_LCSR_DSAT_TM_2eSSTB; |
1454 | } | |
1455 | ||
1456 | /* Setup data width */ | |
1457 | switch (dwidth) { | |
1458 | case VME_D16: | |
1459 | *attr |= TSI148_LCSR_DSAT_DBW_16; | |
1460 | break; | |
1461 | case VME_D32: | |
1462 | *attr |= TSI148_LCSR_DSAT_DBW_32; | |
1463 | break; | |
1464 | default: | |
48d9356e | 1465 | dev_err(dev, "Invalid data width\n"); |
d22b8ed9 MW |
1466 | return -EINVAL; |
1467 | } | |
1468 | ||
1469 | /* Setup address space */ | |
1470 | switch (aspace) { | |
1471 | case VME_A16: | |
1472 | *attr |= TSI148_LCSR_DSAT_AMODE_A16; | |
1473 | break; | |
1474 | case VME_A24: | |
1475 | *attr |= TSI148_LCSR_DSAT_AMODE_A24; | |
1476 | break; | |
1477 | case VME_A32: | |
1478 | *attr |= TSI148_LCSR_DSAT_AMODE_A32; | |
1479 | break; | |
1480 | case VME_A64: | |
1481 | *attr |= TSI148_LCSR_DSAT_AMODE_A64; | |
1482 | break; | |
1483 | case VME_CRCSR: | |
1484 | *attr |= TSI148_LCSR_DSAT_AMODE_CRCSR; | |
1485 | break; | |
1486 | case VME_USER1: | |
1487 | *attr |= TSI148_LCSR_DSAT_AMODE_USER1; | |
1488 | break; | |
1489 | case VME_USER2: | |
1490 | *attr |= TSI148_LCSR_DSAT_AMODE_USER2; | |
1491 | break; | |
1492 | case VME_USER3: | |
1493 | *attr |= TSI148_LCSR_DSAT_AMODE_USER3; | |
1494 | break; | |
1495 | case VME_USER4: | |
1496 | *attr |= TSI148_LCSR_DSAT_AMODE_USER4; | |
1497 | break; | |
1498 | default: | |
48d9356e | 1499 | dev_err(dev, "Invalid address space\n"); |
d22b8ed9 MW |
1500 | return -EINVAL; |
1501 | break; | |
1502 | } | |
1503 | ||
1504 | if (cycle & VME_SUPER) | |
1505 | *attr |= TSI148_LCSR_DSAT_SUP; | |
1506 | if (cycle & VME_PROG) | |
1507 | *attr |= TSI148_LCSR_DSAT_PGM; | |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
48d9356e | 1512 | static int tsi148_dma_set_vme_dest_attributes(struct device *dev, u32 *attr, |
6af04b06 | 1513 | u32 aspace, u32 cycle, u32 dwidth) |
d22b8ed9 MW |
1514 | { |
1515 | /* Setup 2eSST speeds */ | |
1516 | switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) { | |
1517 | case VME_2eSST160: | |
1518 | *attr |= TSI148_LCSR_DDAT_2eSSTM_160; | |
1519 | break; | |
1520 | case VME_2eSST267: | |
1521 | *attr |= TSI148_LCSR_DDAT_2eSSTM_267; | |
1522 | break; | |
1523 | case VME_2eSST320: | |
1524 | *attr |= TSI148_LCSR_DDAT_2eSSTM_320; | |
1525 | break; | |
1526 | } | |
1527 | ||
1528 | /* Setup cycle types */ | |
7946328f | 1529 | if (cycle & VME_SCT) |
d22b8ed9 | 1530 | *attr |= TSI148_LCSR_DDAT_TM_SCT; |
7946328f MW |
1531 | |
1532 | if (cycle & VME_BLT) | |
d22b8ed9 | 1533 | *attr |= TSI148_LCSR_DDAT_TM_BLT; |
7946328f MW |
1534 | |
1535 | if (cycle & VME_MBLT) | |
d22b8ed9 | 1536 | *attr |= TSI148_LCSR_DDAT_TM_MBLT; |
7946328f MW |
1537 | |
1538 | if (cycle & VME_2eVME) | |
d22b8ed9 | 1539 | *attr |= TSI148_LCSR_DDAT_TM_2eVME; |
7946328f MW |
1540 | |
1541 | if (cycle & VME_2eSST) | |
d22b8ed9 | 1542 | *attr |= TSI148_LCSR_DDAT_TM_2eSST; |
7946328f | 1543 | |
d22b8ed9 | 1544 | if (cycle & VME_2eSSTB) { |
48d9356e MW |
1545 | dev_err(dev, "Currently not setting Broadcast Select " |
1546 | "Registers\n"); | |
d22b8ed9 MW |
1547 | *attr |= TSI148_LCSR_DDAT_TM_2eSSTB; |
1548 | } | |
1549 | ||
1550 | /* Setup data width */ | |
1551 | switch (dwidth) { | |
1552 | case VME_D16: | |
1553 | *attr |= TSI148_LCSR_DDAT_DBW_16; | |
1554 | break; | |
1555 | case VME_D32: | |
1556 | *attr |= TSI148_LCSR_DDAT_DBW_32; | |
1557 | break; | |
1558 | default: | |
48d9356e | 1559 | dev_err(dev, "Invalid data width\n"); |
d22b8ed9 MW |
1560 | return -EINVAL; |
1561 | } | |
1562 | ||
1563 | /* Setup address space */ | |
1564 | switch (aspace) { | |
1565 | case VME_A16: | |
1566 | *attr |= TSI148_LCSR_DDAT_AMODE_A16; | |
1567 | break; | |
1568 | case VME_A24: | |
1569 | *attr |= TSI148_LCSR_DDAT_AMODE_A24; | |
1570 | break; | |
1571 | case VME_A32: | |
1572 | *attr |= TSI148_LCSR_DDAT_AMODE_A32; | |
1573 | break; | |
1574 | case VME_A64: | |
1575 | *attr |= TSI148_LCSR_DDAT_AMODE_A64; | |
1576 | break; | |
1577 | case VME_CRCSR: | |
1578 | *attr |= TSI148_LCSR_DDAT_AMODE_CRCSR; | |
1579 | break; | |
1580 | case VME_USER1: | |
1581 | *attr |= TSI148_LCSR_DDAT_AMODE_USER1; | |
1582 | break; | |
1583 | case VME_USER2: | |
1584 | *attr |= TSI148_LCSR_DDAT_AMODE_USER2; | |
1585 | break; | |
1586 | case VME_USER3: | |
1587 | *attr |= TSI148_LCSR_DDAT_AMODE_USER3; | |
1588 | break; | |
1589 | case VME_USER4: | |
1590 | *attr |= TSI148_LCSR_DDAT_AMODE_USER4; | |
1591 | break; | |
1592 | default: | |
48d9356e | 1593 | dev_err(dev, "Invalid address space\n"); |
d22b8ed9 MW |
1594 | return -EINVAL; |
1595 | break; | |
1596 | } | |
1597 | ||
1598 | if (cycle & VME_SUPER) | |
1599 | *attr |= TSI148_LCSR_DDAT_SUP; | |
1600 | if (cycle & VME_PROG) | |
1601 | *attr |= TSI148_LCSR_DDAT_PGM; | |
1602 | ||
1603 | return 0; | |
1604 | } | |
1605 | ||
1606 | /* | |
1607 | * Add a link list descriptor to the list | |
d22b8ed9 | 1608 | */ |
5ade6c4d EC |
1609 | static int tsi148_dma_list_add(struct vme_dma_list *list, |
1610 | struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count) | |
d22b8ed9 MW |
1611 | { |
1612 | struct tsi148_dma_entry *entry, *prev; | |
1613 | u32 address_high, address_low; | |
1614 | struct vme_dma_pattern *pattern_attr; | |
1615 | struct vme_dma_pci *pci_attr; | |
1616 | struct vme_dma_vme *vme_attr; | |
d22b8ed9 | 1617 | int retval = 0; |
48d9356e MW |
1618 | struct vme_bridge *tsi148_bridge; |
1619 | ||
1620 | tsi148_bridge = list->parent->parent; | |
d22b8ed9 | 1621 | |
bb9ea89e | 1622 | /* Descriptor must be aligned on 64-bit boundaries */ |
7946328f | 1623 | entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL); |
d22b8ed9 | 1624 | if (entry == NULL) { |
48d9356e MW |
1625 | dev_err(tsi148_bridge->parent, "Failed to allocate memory for " |
1626 | "dma resource structure\n"); | |
d22b8ed9 MW |
1627 | retval = -ENOMEM; |
1628 | goto err_mem; | |
1629 | } | |
1630 | ||
1631 | /* Test descriptor alignment */ | |
886953e9 | 1632 | if ((unsigned long)&entry->descriptor & 0x7) { |
48d9356e MW |
1633 | dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 " |
1634 | "byte boundary as required: %p\n", | |
886953e9 | 1635 | &entry->descriptor); |
d22b8ed9 MW |
1636 | retval = -EINVAL; |
1637 | goto err_align; | |
1638 | } | |
1639 | ||
1640 | /* Given we are going to fill out the structure, we probably don't | |
1641 | * need to zero it, but better safe than sorry for now. | |
1642 | */ | |
886953e9 | 1643 | memset(&entry->descriptor, 0, sizeof(struct tsi148_dma_descriptor)); |
d22b8ed9 MW |
1644 | |
1645 | /* Fill out source part */ | |
1646 | switch (src->type) { | |
1647 | case VME_DMA_PATTERN: | |
c4d82fbb | 1648 | pattern_attr = src->private; |
d22b8ed9 MW |
1649 | |
1650 | entry->descriptor.dsal = pattern_attr->pattern; | |
1651 | entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT; | |
1652 | /* Default behaviour is 32 bit pattern */ | |
7946328f | 1653 | if (pattern_attr->type & VME_DMA_PATTERN_BYTE) |
d22b8ed9 | 1654 | entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ; |
7946328f | 1655 | |
d22b8ed9 | 1656 | /* It seems that the default behaviour is to increment */ |
7946328f | 1657 | if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) |
d22b8ed9 | 1658 | entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN; |
7946328f | 1659 | |
d22b8ed9 MW |
1660 | break; |
1661 | case VME_DMA_PCI: | |
c4d82fbb | 1662 | pci_attr = src->private; |
d22b8ed9 MW |
1663 | |
1664 | reg_split((unsigned long long)pci_attr->address, &address_high, | |
1665 | &address_low); | |
1666 | entry->descriptor.dsau = address_high; | |
1667 | entry->descriptor.dsal = address_low; | |
1668 | entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI; | |
1669 | break; | |
1670 | case VME_DMA_VME: | |
c4d82fbb | 1671 | vme_attr = src->private; |
d22b8ed9 MW |
1672 | |
1673 | reg_split((unsigned long long)vme_attr->address, &address_high, | |
1674 | &address_low); | |
1675 | entry->descriptor.dsau = address_high; | |
1676 | entry->descriptor.dsal = address_low; | |
1677 | entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME; | |
1678 | ||
1679 | retval = tsi148_dma_set_vme_src_attributes( | |
886953e9 | 1680 | tsi148_bridge->parent, &entry->descriptor.dsat, |
48d9356e | 1681 | vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); |
7946328f | 1682 | if (retval < 0) |
d22b8ed9 MW |
1683 | goto err_source; |
1684 | break; | |
1685 | default: | |
48d9356e | 1686 | dev_err(tsi148_bridge->parent, "Invalid source type\n"); |
d22b8ed9 MW |
1687 | retval = -EINVAL; |
1688 | goto err_source; | |
1689 | break; | |
1690 | } | |
1691 | ||
1692 | /* Assume last link - this will be over-written by adding another */ | |
1693 | entry->descriptor.dnlau = 0; | |
1694 | entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA; | |
1695 | ||
1696 | ||
1697 | /* Fill out destination part */ | |
1698 | switch (dest->type) { | |
1699 | case VME_DMA_PCI: | |
c4d82fbb | 1700 | pci_attr = dest->private; |
d22b8ed9 MW |
1701 | |
1702 | reg_split((unsigned long long)pci_attr->address, &address_high, | |
1703 | &address_low); | |
1704 | entry->descriptor.ddau = address_high; | |
1705 | entry->descriptor.ddal = address_low; | |
1706 | entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI; | |
1707 | break; | |
1708 | case VME_DMA_VME: | |
c4d82fbb | 1709 | vme_attr = dest->private; |
d22b8ed9 MW |
1710 | |
1711 | reg_split((unsigned long long)vme_attr->address, &address_high, | |
1712 | &address_low); | |
1713 | entry->descriptor.ddau = address_high; | |
1714 | entry->descriptor.ddal = address_low; | |
1715 | entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME; | |
1716 | ||
1717 | retval = tsi148_dma_set_vme_dest_attributes( | |
886953e9 | 1718 | tsi148_bridge->parent, &entry->descriptor.ddat, |
48d9356e | 1719 | vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth); |
7946328f | 1720 | if (retval < 0) |
d22b8ed9 MW |
1721 | goto err_dest; |
1722 | break; | |
1723 | default: | |
48d9356e | 1724 | dev_err(tsi148_bridge->parent, "Invalid destination type\n"); |
d22b8ed9 MW |
1725 | retval = -EINVAL; |
1726 | goto err_dest; | |
1727 | break; | |
1728 | } | |
1729 | ||
1730 | /* Fill out count */ | |
1731 | entry->descriptor.dcnt = (u32)count; | |
1732 | ||
1733 | /* Add to list */ | |
886953e9 | 1734 | list_add_tail(&entry->list, &list->entries); |
d22b8ed9 MW |
1735 | |
1736 | /* Fill out previous descriptors "Next Address" */ | |
886953e9 | 1737 | if (entry->list.prev != &list->entries) { |
d22b8ed9 MW |
1738 | prev = list_entry(entry->list.prev, struct tsi148_dma_entry, |
1739 | list); | |
1740 | /* We need the bus address for the pointer */ | |
3abc48ae MW |
1741 | entry->dma_handle = dma_map_single(tsi148_bridge->parent, |
1742 | &entry->descriptor, | |
1743 | sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE); | |
1744 | ||
1745 | reg_split((unsigned long long)entry->dma_handle, | |
1746 | &prev->descriptor.dnlau, &prev->descriptor.dnlal); | |
d22b8ed9 MW |
1747 | } |
1748 | ||
1749 | return 0; | |
1750 | ||
1751 | err_dest: | |
1752 | err_source: | |
1753 | err_align: | |
1754 | kfree(entry); | |
1755 | err_mem: | |
1756 | return retval; | |
1757 | } | |
1758 | ||
1759 | /* | |
1760 | * Check to see if the provided DMA channel is busy. | |
1761 | */ | |
29848ac9 | 1762 | static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel) |
d22b8ed9 MW |
1763 | { |
1764 | u32 tmp; | |
29848ac9 MW |
1765 | struct tsi148_driver *bridge; |
1766 | ||
1767 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 1768 | |
29848ac9 | 1769 | tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + |
d22b8ed9 MW |
1770 | TSI148_LCSR_OFFSET_DSTA); |
1771 | ||
1772 | if (tmp & TSI148_LCSR_DSTA_BSY) | |
1773 | return 0; | |
1774 | else | |
1775 | return 1; | |
1776 | ||
1777 | } | |
1778 | ||
1779 | /* | |
1780 | * Execute a previously generated link list | |
1781 | * | |
1782 | * XXX Need to provide control register configuration. | |
1783 | */ | |
5ade6c4d | 1784 | static int tsi148_dma_list_exec(struct vme_dma_list *list) |
d22b8ed9 MW |
1785 | { |
1786 | struct vme_dma_resource *ctrlr; | |
1787 | int channel, retval = 0; | |
1788 | struct tsi148_dma_entry *entry; | |
d22b8ed9 MW |
1789 | u32 bus_addr_high, bus_addr_low; |
1790 | u32 val, dctlreg = 0; | |
48d9356e | 1791 | struct vme_bridge *tsi148_bridge; |
29848ac9 | 1792 | struct tsi148_driver *bridge; |
d22b8ed9 MW |
1793 | |
1794 | ctrlr = list->parent; | |
1795 | ||
48d9356e MW |
1796 | tsi148_bridge = ctrlr->parent; |
1797 | ||
1798 | bridge = tsi148_bridge->driver_priv; | |
29848ac9 | 1799 | |
886953e9 | 1800 | mutex_lock(&ctrlr->mtx); |
d22b8ed9 MW |
1801 | |
1802 | channel = ctrlr->number; | |
1803 | ||
886953e9 | 1804 | if (!list_empty(&ctrlr->running)) { |
d22b8ed9 MW |
1805 | /* |
1806 | * XXX We have an active DMA transfer and currently haven't | |
1807 | * sorted out the mechanism for "pending" DMA transfers. | |
1808 | * Return busy. | |
1809 | */ | |
1810 | /* Need to add to pending here */ | |
886953e9 | 1811 | mutex_unlock(&ctrlr->mtx); |
d22b8ed9 MW |
1812 | return -EBUSY; |
1813 | } else { | |
886953e9 | 1814 | list_add(&list->list, &ctrlr->running); |
d22b8ed9 | 1815 | } |
d22b8ed9 MW |
1816 | |
1817 | /* Get first bus address and write into registers */ | |
886953e9 | 1818 | entry = list_first_entry(&list->entries, struct tsi148_dma_entry, |
d22b8ed9 MW |
1819 | list); |
1820 | ||
3abc48ae MW |
1821 | entry->dma_handle = dma_map_single(tsi148_bridge->parent, |
1822 | &entry->descriptor, | |
1823 | sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE); | |
d22b8ed9 | 1824 | |
886953e9 | 1825 | mutex_unlock(&ctrlr->mtx); |
d22b8ed9 | 1826 | |
3abc48ae | 1827 | reg_split(entry->dma_handle, &bus_addr_high, &bus_addr_low); |
d22b8ed9 | 1828 | |
29848ac9 | 1829 | iowrite32be(bus_addr_high, bridge->base + |
d22b8ed9 | 1830 | TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU); |
29848ac9 | 1831 | iowrite32be(bus_addr_low, bridge->base + |
d22b8ed9 MW |
1832 | TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL); |
1833 | ||
1834 | /* Start the operation */ | |
29848ac9 | 1835 | iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base + |
d22b8ed9 MW |
1836 | TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL); |
1837 | ||
29848ac9 MW |
1838 | wait_event_interruptible(bridge->dma_queue[channel], |
1839 | tsi148_dma_busy(ctrlr->parent, channel)); | |
d22b8ed9 MW |
1840 | /* |
1841 | * Read status register, this register is valid until we kick off a | |
1842 | * new transfer. | |
1843 | */ | |
29848ac9 | 1844 | val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] + |
d22b8ed9 MW |
1845 | TSI148_LCSR_OFFSET_DSTA); |
1846 | ||
1847 | if (val & TSI148_LCSR_DSTA_VBE) { | |
48d9356e | 1848 | dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val); |
d22b8ed9 MW |
1849 | retval = -EIO; |
1850 | } | |
1851 | ||
1852 | /* Remove list from running list */ | |
886953e9 EC |
1853 | mutex_lock(&ctrlr->mtx); |
1854 | list_del(&list->list); | |
1855 | mutex_unlock(&ctrlr->mtx); | |
d22b8ed9 MW |
1856 | |
1857 | return retval; | |
1858 | } | |
1859 | ||
1860 | /* | |
1861 | * Clean up a previously generated link list | |
1862 | * | |
1863 | * We have a separate function, don't assume that the chain can't be reused. | |
1864 | */ | |
5ade6c4d | 1865 | static int tsi148_dma_list_empty(struct vme_dma_list *list) |
d22b8ed9 MW |
1866 | { |
1867 | struct list_head *pos, *temp; | |
7946328f | 1868 | struct tsi148_dma_entry *entry; |
d22b8ed9 | 1869 | |
3abc48ae MW |
1870 | struct vme_bridge *tsi148_bridge = list->parent->parent; |
1871 | ||
d22b8ed9 | 1872 | /* detach and free each entry */ |
886953e9 | 1873 | list_for_each_safe(pos, temp, &list->entries) { |
d22b8ed9 MW |
1874 | list_del(pos); |
1875 | entry = list_entry(pos, struct tsi148_dma_entry, list); | |
3abc48ae MW |
1876 | |
1877 | dma_unmap_single(tsi148_bridge->parent, entry->dma_handle, | |
1878 | sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE); | |
d22b8ed9 MW |
1879 | kfree(entry); |
1880 | } | |
1881 | ||
7946328f | 1882 | return 0; |
d22b8ed9 MW |
1883 | } |
1884 | ||
1885 | /* | |
1886 | * All 4 location monitors reside at the same base - this is therefore a | |
1887 | * system wide configuration. | |
1888 | * | |
1889 | * This does not enable the LM monitor - that should be done when the first | |
1890 | * callback is attached and disabled when the last callback is removed. | |
1891 | */ | |
5ade6c4d | 1892 | static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base, |
6af04b06 | 1893 | u32 aspace, u32 cycle) |
d22b8ed9 MW |
1894 | { |
1895 | u32 lm_base_high, lm_base_low, lm_ctl = 0; | |
1896 | int i; | |
48d9356e | 1897 | struct vme_bridge *tsi148_bridge; |
29848ac9 MW |
1898 | struct tsi148_driver *bridge; |
1899 | ||
48d9356e MW |
1900 | tsi148_bridge = lm->parent; |
1901 | ||
1902 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 1903 | |
886953e9 | 1904 | mutex_lock(&lm->mtx); |
d22b8ed9 MW |
1905 | |
1906 | /* If we already have a callback attached, we can't move it! */ | |
42fb5031 | 1907 | for (i = 0; i < lm->monitors; i++) { |
29848ac9 | 1908 | if (bridge->lm_callback[i] != NULL) { |
886953e9 | 1909 | mutex_unlock(&lm->mtx); |
48d9356e MW |
1910 | dev_err(tsi148_bridge->parent, "Location monitor " |
1911 | "callback attached, can't reset\n"); | |
d22b8ed9 MW |
1912 | return -EBUSY; |
1913 | } | |
1914 | } | |
1915 | ||
1916 | switch (aspace) { | |
1917 | case VME_A16: | |
1918 | lm_ctl |= TSI148_LCSR_LMAT_AS_A16; | |
1919 | break; | |
1920 | case VME_A24: | |
1921 | lm_ctl |= TSI148_LCSR_LMAT_AS_A24; | |
1922 | break; | |
1923 | case VME_A32: | |
1924 | lm_ctl |= TSI148_LCSR_LMAT_AS_A32; | |
1925 | break; | |
1926 | case VME_A64: | |
1927 | lm_ctl |= TSI148_LCSR_LMAT_AS_A64; | |
1928 | break; | |
1929 | default: | |
886953e9 | 1930 | mutex_unlock(&lm->mtx); |
48d9356e | 1931 | dev_err(tsi148_bridge->parent, "Invalid address space\n"); |
d22b8ed9 MW |
1932 | return -EINVAL; |
1933 | break; | |
1934 | } | |
1935 | ||
1936 | if (cycle & VME_SUPER) | |
1937 | lm_ctl |= TSI148_LCSR_LMAT_SUPR ; | |
1938 | if (cycle & VME_USER) | |
1939 | lm_ctl |= TSI148_LCSR_LMAT_NPRIV; | |
1940 | if (cycle & VME_PROG) | |
1941 | lm_ctl |= TSI148_LCSR_LMAT_PGM; | |
1942 | if (cycle & VME_DATA) | |
1943 | lm_ctl |= TSI148_LCSR_LMAT_DATA; | |
1944 | ||
1945 | reg_split(lm_base, &lm_base_high, &lm_base_low); | |
1946 | ||
29848ac9 MW |
1947 | iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU); |
1948 | iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL); | |
1949 | iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); | |
d22b8ed9 | 1950 | |
886953e9 | 1951 | mutex_unlock(&lm->mtx); |
d22b8ed9 MW |
1952 | |
1953 | return 0; | |
1954 | } | |
1955 | ||
1956 | /* Get configuration of the callback monitor and return whether it is enabled | |
1957 | * or disabled. | |
1958 | */ | |
5ade6c4d | 1959 | static int tsi148_lm_get(struct vme_lm_resource *lm, |
6af04b06 | 1960 | unsigned long long *lm_base, u32 *aspace, u32 *cycle) |
d22b8ed9 MW |
1961 | { |
1962 | u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0; | |
29848ac9 MW |
1963 | struct tsi148_driver *bridge; |
1964 | ||
1965 | bridge = lm->parent->driver_priv; | |
d22b8ed9 | 1966 | |
886953e9 | 1967 | mutex_lock(&lm->mtx); |
d22b8ed9 | 1968 | |
29848ac9 MW |
1969 | lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU); |
1970 | lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL); | |
1971 | lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); | |
d22b8ed9 MW |
1972 | |
1973 | reg_join(lm_base_high, lm_base_low, lm_base); | |
1974 | ||
1975 | if (lm_ctl & TSI148_LCSR_LMAT_EN) | |
1976 | enabled = 1; | |
1977 | ||
7946328f | 1978 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16) |
d22b8ed9 | 1979 | *aspace |= VME_A16; |
7946328f MW |
1980 | |
1981 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24) | |
d22b8ed9 | 1982 | *aspace |= VME_A24; |
7946328f MW |
1983 | |
1984 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32) | |
d22b8ed9 | 1985 | *aspace |= VME_A32; |
7946328f MW |
1986 | |
1987 | if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64) | |
d22b8ed9 | 1988 | *aspace |= VME_A64; |
7946328f | 1989 | |
d22b8ed9 MW |
1990 | |
1991 | if (lm_ctl & TSI148_LCSR_LMAT_SUPR) | |
1992 | *cycle |= VME_SUPER; | |
1993 | if (lm_ctl & TSI148_LCSR_LMAT_NPRIV) | |
1994 | *cycle |= VME_USER; | |
1995 | if (lm_ctl & TSI148_LCSR_LMAT_PGM) | |
1996 | *cycle |= VME_PROG; | |
1997 | if (lm_ctl & TSI148_LCSR_LMAT_DATA) | |
1998 | *cycle |= VME_DATA; | |
1999 | ||
886953e9 | 2000 | mutex_unlock(&lm->mtx); |
d22b8ed9 MW |
2001 | |
2002 | return enabled; | |
2003 | } | |
2004 | ||
2005 | /* | |
2006 | * Attach a callback to a specific location monitor. | |
2007 | * | |
2008 | * Callback will be passed the monitor triggered. | |
2009 | */ | |
5ade6c4d | 2010 | static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor, |
42fb5031 | 2011 | void (*callback)(int)) |
d22b8ed9 MW |
2012 | { |
2013 | u32 lm_ctl, tmp; | |
48d9356e | 2014 | struct vme_bridge *tsi148_bridge; |
29848ac9 MW |
2015 | struct tsi148_driver *bridge; |
2016 | ||
48d9356e MW |
2017 | tsi148_bridge = lm->parent; |
2018 | ||
2019 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 2020 | |
886953e9 | 2021 | mutex_lock(&lm->mtx); |
d22b8ed9 MW |
2022 | |
2023 | /* Ensure that the location monitor is configured - need PGM or DATA */ | |
29848ac9 | 2024 | lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT); |
d22b8ed9 | 2025 | if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) { |
886953e9 | 2026 | mutex_unlock(&lm->mtx); |
48d9356e MW |
2027 | dev_err(tsi148_bridge->parent, "Location monitor not properly " |
2028 | "configured\n"); | |
d22b8ed9 MW |
2029 | return -EINVAL; |
2030 | } | |
2031 | ||
2032 | /* Check that a callback isn't already attached */ | |
29848ac9 | 2033 | if (bridge->lm_callback[monitor] != NULL) { |
886953e9 | 2034 | mutex_unlock(&lm->mtx); |
48d9356e | 2035 | dev_err(tsi148_bridge->parent, "Existing callback attached\n"); |
d22b8ed9 MW |
2036 | return -EBUSY; |
2037 | } | |
2038 | ||
2039 | /* Attach callback */ | |
29848ac9 | 2040 | bridge->lm_callback[monitor] = callback; |
d22b8ed9 MW |
2041 | |
2042 | /* Enable Location Monitor interrupt */ | |
29848ac9 | 2043 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
d22b8ed9 | 2044 | tmp |= TSI148_LCSR_INTEN_LMEN[monitor]; |
29848ac9 | 2045 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN); |
d22b8ed9 | 2046 | |
29848ac9 | 2047 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
d22b8ed9 | 2048 | tmp |= TSI148_LCSR_INTEO_LMEO[monitor]; |
29848ac9 | 2049 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
d22b8ed9 MW |
2050 | |
2051 | /* Ensure that global Location Monitor Enable set */ | |
2052 | if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) { | |
2053 | lm_ctl |= TSI148_LCSR_LMAT_EN; | |
29848ac9 | 2054 | iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT); |
d22b8ed9 MW |
2055 | } |
2056 | ||
886953e9 | 2057 | mutex_unlock(&lm->mtx); |
d22b8ed9 MW |
2058 | |
2059 | return 0; | |
2060 | } | |
2061 | ||
2062 | /* | |
2063 | * Detach a callback function forn a specific location monitor. | |
2064 | */ | |
5ade6c4d | 2065 | static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor) |
d22b8ed9 MW |
2066 | { |
2067 | u32 lm_en, tmp; | |
29848ac9 MW |
2068 | struct tsi148_driver *bridge; |
2069 | ||
2070 | bridge = lm->parent->driver_priv; | |
d22b8ed9 | 2071 | |
886953e9 | 2072 | mutex_lock(&lm->mtx); |
d22b8ed9 MW |
2073 | |
2074 | /* Disable Location Monitor and ensure previous interrupts are clear */ | |
29848ac9 | 2075 | lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN); |
d22b8ed9 | 2076 | lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor]; |
29848ac9 | 2077 | iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN); |
d22b8ed9 | 2078 | |
29848ac9 | 2079 | tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO); |
d22b8ed9 | 2080 | tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor]; |
29848ac9 | 2081 | iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO); |
d22b8ed9 MW |
2082 | |
2083 | iowrite32be(TSI148_LCSR_INTC_LMC[monitor], | |
29848ac9 | 2084 | bridge->base + TSI148_LCSR_INTC); |
d22b8ed9 MW |
2085 | |
2086 | /* Detach callback */ | |
29848ac9 | 2087 | bridge->lm_callback[monitor] = NULL; |
d22b8ed9 MW |
2088 | |
2089 | /* If all location monitors disabled, disable global Location Monitor */ | |
2090 | if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S | | |
2091 | TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) { | |
29848ac9 | 2092 | tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT); |
d22b8ed9 | 2093 | tmp &= ~TSI148_LCSR_LMAT_EN; |
29848ac9 | 2094 | iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT); |
d22b8ed9 MW |
2095 | } |
2096 | ||
886953e9 | 2097 | mutex_unlock(&lm->mtx); |
d22b8ed9 MW |
2098 | |
2099 | return 0; | |
2100 | } | |
2101 | ||
2102 | /* | |
2103 | * Determine Geographical Addressing | |
2104 | */ | |
5ade6c4d | 2105 | static int tsi148_slot_get(struct vme_bridge *tsi148_bridge) |
d22b8ed9 | 2106 | { |
7946328f | 2107 | u32 slot = 0; |
29848ac9 MW |
2108 | struct tsi148_driver *bridge; |
2109 | ||
2110 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 2111 | |
638f199d | 2112 | if (!geoid) { |
29848ac9 | 2113 | slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT); |
638f199d MW |
2114 | slot = slot & TSI148_LCSR_VSTAT_GA_M; |
2115 | } else | |
2116 | slot = geoid; | |
2117 | ||
d22b8ed9 MW |
2118 | return (int)slot; |
2119 | } | |
2120 | ||
7f58f025 MV |
2121 | void *tsi148_alloc_consistent(struct device *parent, size_t size, |
2122 | dma_addr_t *dma) | |
2123 | { | |
2124 | struct pci_dev *pdev; | |
2125 | ||
2126 | /* Find pci_dev container of dev */ | |
2127 | pdev = container_of(parent, struct pci_dev, dev); | |
2128 | ||
2129 | return pci_alloc_consistent(pdev, size, dma); | |
2130 | } | |
2131 | ||
2132 | void tsi148_free_consistent(struct device *parent, size_t size, void *vaddr, | |
2133 | dma_addr_t dma) | |
2134 | { | |
2135 | struct pci_dev *pdev; | |
2136 | ||
2137 | /* Find pci_dev container of dev */ | |
2138 | pdev = container_of(parent, struct pci_dev, dev); | |
2139 | ||
2140 | pci_free_consistent(pdev, size, vaddr, dma); | |
2141 | } | |
2142 | ||
d22b8ed9 MW |
2143 | static int __init tsi148_init(void) |
2144 | { | |
2145 | return pci_register_driver(&tsi148_driver); | |
2146 | } | |
2147 | ||
2148 | /* | |
2149 | * Configure CR/CSR space | |
2150 | * | |
2151 | * Access to the CR/CSR can be configured at power-up. The location of the | |
2152 | * CR/CSR registers in the CR/CSR address space is determined by the boards | |
2153 | * Auto-ID or Geographic address. This function ensures that the window is | |
2154 | * enabled at an offset consistent with the boards geopgraphic address. | |
2155 | * | |
2156 | * Each board has a 512kB window, with the highest 4kB being used for the | |
2157 | * boards registers, this means there is a fix length 508kB window which must | |
2158 | * be mapped onto PCI memory. | |
2159 | */ | |
29848ac9 MW |
2160 | static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge, |
2161 | struct pci_dev *pdev) | |
d22b8ed9 MW |
2162 | { |
2163 | u32 cbar, crat, vstat; | |
2164 | u32 crcsr_bus_high, crcsr_bus_low; | |
2165 | int retval; | |
29848ac9 MW |
2166 | struct tsi148_driver *bridge; |
2167 | ||
2168 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 MW |
2169 | |
2170 | /* Allocate mem for CR/CSR image */ | |
29848ac9 | 2171 | bridge->crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE, |
886953e9 | 2172 | &bridge->crcsr_bus); |
29848ac9 | 2173 | if (bridge->crcsr_kernel == NULL) { |
48d9356e MW |
2174 | dev_err(tsi148_bridge->parent, "Failed to allocate memory for " |
2175 | "CR/CSR image\n"); | |
d22b8ed9 MW |
2176 | return -ENOMEM; |
2177 | } | |
2178 | ||
29848ac9 | 2179 | memset(bridge->crcsr_kernel, 0, VME_CRCSR_BUF_SIZE); |
d22b8ed9 | 2180 | |
29848ac9 | 2181 | reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low); |
d22b8ed9 | 2182 | |
29848ac9 MW |
2183 | iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU); |
2184 | iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL); | |
d22b8ed9 MW |
2185 | |
2186 | /* Ensure that the CR/CSR is configured at the correct offset */ | |
29848ac9 | 2187 | cbar = ioread32be(bridge->base + TSI148_CBAR); |
d22b8ed9 MW |
2188 | cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3; |
2189 | ||
29848ac9 | 2190 | vstat = tsi148_slot_get(tsi148_bridge); |
d22b8ed9 MW |
2191 | |
2192 | if (cbar != vstat) { | |
638f199d | 2193 | cbar = vstat; |
48d9356e | 2194 | dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n"); |
29848ac9 | 2195 | iowrite32be(cbar<<3, bridge->base + TSI148_CBAR); |
d22b8ed9 | 2196 | } |
48d9356e | 2197 | dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar); |
d22b8ed9 | 2198 | |
29848ac9 | 2199 | crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); |
d22b8ed9 | 2200 | if (crat & TSI148_LCSR_CRAT_EN) { |
48d9356e | 2201 | dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n"); |
d22b8ed9 | 2202 | iowrite32be(crat | TSI148_LCSR_CRAT_EN, |
29848ac9 | 2203 | bridge->base + TSI148_LCSR_CRAT); |
d22b8ed9 | 2204 | } else |
48d9356e | 2205 | dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n"); |
d22b8ed9 MW |
2206 | |
2207 | /* If we want flushed, error-checked writes, set up a window | |
2208 | * over the CR/CSR registers. We read from here to safely flush | |
2209 | * through VME writes. | |
2210 | */ | |
7946328f | 2211 | if (err_chk) { |
29848ac9 MW |
2212 | retval = tsi148_master_set(bridge->flush_image, 1, |
2213 | (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT, | |
2214 | VME_D16); | |
d22b8ed9 | 2215 | if (retval) |
48d9356e MW |
2216 | dev_err(tsi148_bridge->parent, "Configuring flush image" |
2217 | " failed\n"); | |
d22b8ed9 MW |
2218 | } |
2219 | ||
2220 | return 0; | |
2221 | ||
2222 | } | |
2223 | ||
29848ac9 MW |
2224 | static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge, |
2225 | struct pci_dev *pdev) | |
d22b8ed9 MW |
2226 | { |
2227 | u32 crat; | |
29848ac9 MW |
2228 | struct tsi148_driver *bridge; |
2229 | ||
2230 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 MW |
2231 | |
2232 | /* Turn off CR/CSR space */ | |
29848ac9 | 2233 | crat = ioread32be(bridge->base + TSI148_LCSR_CRAT); |
d22b8ed9 | 2234 | iowrite32be(crat & ~TSI148_LCSR_CRAT_EN, |
29848ac9 | 2235 | bridge->base + TSI148_LCSR_CRAT); |
d22b8ed9 MW |
2236 | |
2237 | /* Free image */ | |
29848ac9 MW |
2238 | iowrite32be(0, bridge->base + TSI148_LCSR_CROU); |
2239 | iowrite32be(0, bridge->base + TSI148_LCSR_CROL); | |
d22b8ed9 | 2240 | |
29848ac9 MW |
2241 | pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel, |
2242 | bridge->crcsr_bus); | |
d22b8ed9 MW |
2243 | } |
2244 | ||
2245 | static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
2246 | { | |
2247 | int retval, i, master_num; | |
2248 | u32 data; | |
2249 | struct list_head *pos = NULL; | |
29848ac9 MW |
2250 | struct vme_bridge *tsi148_bridge; |
2251 | struct tsi148_driver *tsi148_device; | |
d22b8ed9 MW |
2252 | struct vme_master_resource *master_image; |
2253 | struct vme_slave_resource *slave_image; | |
2254 | struct vme_dma_resource *dma_ctrlr; | |
42fb5031 | 2255 | struct vme_lm_resource *lm; |
d22b8ed9 MW |
2256 | |
2257 | /* If we want to support more than one of each bridge, we need to | |
2258 | * dynamically generate this so we get one per device | |
2259 | */ | |
7a6cb0d5 | 2260 | tsi148_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL); |
d22b8ed9 MW |
2261 | if (tsi148_bridge == NULL) { |
2262 | dev_err(&pdev->dev, "Failed to allocate memory for device " | |
2263 | "structure\n"); | |
2264 | retval = -ENOMEM; | |
2265 | goto err_struct; | |
2266 | } | |
2267 | ||
7a6cb0d5 | 2268 | tsi148_device = kzalloc(sizeof(struct tsi148_driver), GFP_KERNEL); |
29848ac9 MW |
2269 | if (tsi148_device == NULL) { |
2270 | dev_err(&pdev->dev, "Failed to allocate memory for device " | |
2271 | "structure\n"); | |
2272 | retval = -ENOMEM; | |
2273 | goto err_driver; | |
2274 | } | |
2275 | ||
29848ac9 MW |
2276 | tsi148_bridge->driver_priv = tsi148_device; |
2277 | ||
d22b8ed9 MW |
2278 | /* Enable the device */ |
2279 | retval = pci_enable_device(pdev); | |
2280 | if (retval) { | |
2281 | dev_err(&pdev->dev, "Unable to enable device\n"); | |
2282 | goto err_enable; | |
2283 | } | |
2284 | ||
2285 | /* Map Registers */ | |
2286 | retval = pci_request_regions(pdev, driver_name); | |
2287 | if (retval) { | |
2288 | dev_err(&pdev->dev, "Unable to reserve resources\n"); | |
2289 | goto err_resource; | |
2290 | } | |
2291 | ||
2292 | /* map registers in BAR 0 */ | |
29848ac9 MW |
2293 | tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0), |
2294 | 4096); | |
2295 | if (!tsi148_device->base) { | |
d22b8ed9 MW |
2296 | dev_err(&pdev->dev, "Unable to remap CRG region\n"); |
2297 | retval = -EIO; | |
2298 | goto err_remap; | |
2299 | } | |
2300 | ||
2301 | /* Check to see if the mapping worked out */ | |
29848ac9 | 2302 | data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF; |
d22b8ed9 MW |
2303 | if (data != PCI_VENDOR_ID_TUNDRA) { |
2304 | dev_err(&pdev->dev, "CRG region check failed\n"); | |
2305 | retval = -EIO; | |
2306 | goto err_test; | |
2307 | } | |
2308 | ||
2309 | /* Initialize wait queues & mutual exclusion flags */ | |
886953e9 EC |
2310 | init_waitqueue_head(&tsi148_device->dma_queue[0]); |
2311 | init_waitqueue_head(&tsi148_device->dma_queue[1]); | |
2312 | init_waitqueue_head(&tsi148_device->iack_queue); | |
2313 | mutex_init(&tsi148_device->vme_int); | |
2314 | mutex_init(&tsi148_device->vme_rmw); | |
d22b8ed9 | 2315 | |
886953e9 | 2316 | tsi148_bridge->parent = &pdev->dev; |
d22b8ed9 MW |
2317 | strcpy(tsi148_bridge->name, driver_name); |
2318 | ||
2319 | /* Setup IRQ */ | |
2320 | retval = tsi148_irq_init(tsi148_bridge); | |
2321 | if (retval != 0) { | |
2322 | dev_err(&pdev->dev, "Chip Initialization failed.\n"); | |
2323 | goto err_irq; | |
2324 | } | |
2325 | ||
2326 | /* If we are going to flush writes, we need to read from the VME bus. | |
2327 | * We need to do this safely, thus we read the devices own CR/CSR | |
2328 | * register. To do this we must set up a window in CR/CSR space and | |
2329 | * hence have one less master window resource available. | |
2330 | */ | |
2331 | master_num = TSI148_MAX_MASTER; | |
7946328f | 2332 | if (err_chk) { |
d22b8ed9 | 2333 | master_num--; |
29848ac9 | 2334 | |
32414878 | 2335 | tsi148_device->flush_image = |
29848ac9 MW |
2336 | kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL); |
2337 | if (tsi148_device->flush_image == NULL) { | |
d22b8ed9 MW |
2338 | dev_err(&pdev->dev, "Failed to allocate memory for " |
2339 | "flush resource structure\n"); | |
2340 | retval = -ENOMEM; | |
2341 | goto err_master; | |
2342 | } | |
29848ac9 | 2343 | tsi148_device->flush_image->parent = tsi148_bridge; |
886953e9 | 2344 | spin_lock_init(&tsi148_device->flush_image->lock); |
29848ac9 MW |
2345 | tsi148_device->flush_image->locked = 1; |
2346 | tsi148_device->flush_image->number = master_num; | |
2347 | tsi148_device->flush_image->address_attr = VME_A16 | VME_A24 | | |
2348 | VME_A32 | VME_A64; | |
2349 | tsi148_device->flush_image->cycle_attr = VME_SCT | VME_BLT | | |
2350 | VME_MBLT | VME_2eVME | VME_2eSST | VME_2eSSTB | | |
2351 | VME_2eSST160 | VME_2eSST267 | VME_2eSST320 | VME_SUPER | | |
2352 | VME_USER | VME_PROG | VME_DATA; | |
2353 | tsi148_device->flush_image->width_attr = VME_D16 | VME_D32; | |
886953e9 | 2354 | memset(&tsi148_device->flush_image->bus_resource, 0, |
d22b8ed9 | 2355 | sizeof(struct resource)); |
29848ac9 | 2356 | tsi148_device->flush_image->kern_base = NULL; |
d22b8ed9 MW |
2357 | } |
2358 | ||
2359 | /* Add master windows to list */ | |
886953e9 | 2360 | INIT_LIST_HEAD(&tsi148_bridge->master_resources); |
d22b8ed9 | 2361 | for (i = 0; i < master_num; i++) { |
7946328f MW |
2362 | master_image = kmalloc(sizeof(struct vme_master_resource), |
2363 | GFP_KERNEL); | |
d22b8ed9 MW |
2364 | if (master_image == NULL) { |
2365 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
2366 | "master resource structure\n"); | |
2367 | retval = -ENOMEM; | |
2368 | goto err_master; | |
2369 | } | |
2370 | master_image->parent = tsi148_bridge; | |
886953e9 | 2371 | spin_lock_init(&master_image->lock); |
d22b8ed9 MW |
2372 | master_image->locked = 0; |
2373 | master_image->number = i; | |
2374 | master_image->address_attr = VME_A16 | VME_A24 | VME_A32 | | |
2375 | VME_A64; | |
2376 | master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | | |
2377 | VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 | | |
2378 | VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | | |
2379 | VME_PROG | VME_DATA; | |
2380 | master_image->width_attr = VME_D16 | VME_D32; | |
886953e9 | 2381 | memset(&master_image->bus_resource, 0, |
d22b8ed9 MW |
2382 | sizeof(struct resource)); |
2383 | master_image->kern_base = NULL; | |
886953e9 EC |
2384 | list_add_tail(&master_image->list, |
2385 | &tsi148_bridge->master_resources); | |
d22b8ed9 MW |
2386 | } |
2387 | ||
2388 | /* Add slave windows to list */ | |
886953e9 | 2389 | INIT_LIST_HEAD(&tsi148_bridge->slave_resources); |
d22b8ed9 | 2390 | for (i = 0; i < TSI148_MAX_SLAVE; i++) { |
7946328f MW |
2391 | slave_image = kmalloc(sizeof(struct vme_slave_resource), |
2392 | GFP_KERNEL); | |
d22b8ed9 MW |
2393 | if (slave_image == NULL) { |
2394 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
2395 | "slave resource structure\n"); | |
2396 | retval = -ENOMEM; | |
2397 | goto err_slave; | |
2398 | } | |
2399 | slave_image->parent = tsi148_bridge; | |
886953e9 | 2400 | mutex_init(&slave_image->mtx); |
d22b8ed9 MW |
2401 | slave_image->locked = 0; |
2402 | slave_image->number = i; | |
2403 | slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 | | |
2404 | VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 | | |
2405 | VME_USER3 | VME_USER4; | |
2406 | slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT | | |
2407 | VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 | | |
2408 | VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER | | |
2409 | VME_PROG | VME_DATA; | |
886953e9 EC |
2410 | list_add_tail(&slave_image->list, |
2411 | &tsi148_bridge->slave_resources); | |
d22b8ed9 MW |
2412 | } |
2413 | ||
2414 | /* Add dma engines to list */ | |
886953e9 | 2415 | INIT_LIST_HEAD(&tsi148_bridge->dma_resources); |
d22b8ed9 | 2416 | for (i = 0; i < TSI148_MAX_DMA; i++) { |
7946328f MW |
2417 | dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource), |
2418 | GFP_KERNEL); | |
d22b8ed9 MW |
2419 | if (dma_ctrlr == NULL) { |
2420 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
2421 | "dma resource structure\n"); | |
2422 | retval = -ENOMEM; | |
2423 | goto err_dma; | |
2424 | } | |
2425 | dma_ctrlr->parent = tsi148_bridge; | |
886953e9 | 2426 | mutex_init(&dma_ctrlr->mtx); |
d22b8ed9 MW |
2427 | dma_ctrlr->locked = 0; |
2428 | dma_ctrlr->number = i; | |
4f723df4 MW |
2429 | dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM | |
2430 | VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME | | |
2431 | VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME | | |
2432 | VME_DMA_PATTERN_TO_MEM; | |
886953e9 EC |
2433 | INIT_LIST_HEAD(&dma_ctrlr->pending); |
2434 | INIT_LIST_HEAD(&dma_ctrlr->running); | |
2435 | list_add_tail(&dma_ctrlr->list, | |
2436 | &tsi148_bridge->dma_resources); | |
d22b8ed9 MW |
2437 | } |
2438 | ||
42fb5031 | 2439 | /* Add location monitor to list */ |
886953e9 | 2440 | INIT_LIST_HEAD(&tsi148_bridge->lm_resources); |
42fb5031 MW |
2441 | lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL); |
2442 | if (lm == NULL) { | |
2443 | dev_err(&pdev->dev, "Failed to allocate memory for " | |
2444 | "location monitor resource structure\n"); | |
2445 | retval = -ENOMEM; | |
2446 | goto err_lm; | |
2447 | } | |
2448 | lm->parent = tsi148_bridge; | |
886953e9 | 2449 | mutex_init(&lm->mtx); |
42fb5031 MW |
2450 | lm->locked = 0; |
2451 | lm->number = 1; | |
2452 | lm->monitors = 4; | |
886953e9 | 2453 | list_add_tail(&lm->list, &tsi148_bridge->lm_resources); |
42fb5031 | 2454 | |
d22b8ed9 MW |
2455 | tsi148_bridge->slave_get = tsi148_slave_get; |
2456 | tsi148_bridge->slave_set = tsi148_slave_set; | |
2457 | tsi148_bridge->master_get = tsi148_master_get; | |
2458 | tsi148_bridge->master_set = tsi148_master_set; | |
2459 | tsi148_bridge->master_read = tsi148_master_read; | |
2460 | tsi148_bridge->master_write = tsi148_master_write; | |
2461 | tsi148_bridge->master_rmw = tsi148_master_rmw; | |
2462 | tsi148_bridge->dma_list_add = tsi148_dma_list_add; | |
2463 | tsi148_bridge->dma_list_exec = tsi148_dma_list_exec; | |
2464 | tsi148_bridge->dma_list_empty = tsi148_dma_list_empty; | |
c813f592 MW |
2465 | tsi148_bridge->irq_set = tsi148_irq_set; |
2466 | tsi148_bridge->irq_generate = tsi148_irq_generate; | |
d22b8ed9 MW |
2467 | tsi148_bridge->lm_set = tsi148_lm_set; |
2468 | tsi148_bridge->lm_get = tsi148_lm_get; | |
2469 | tsi148_bridge->lm_attach = tsi148_lm_attach; | |
2470 | tsi148_bridge->lm_detach = tsi148_lm_detach; | |
2471 | tsi148_bridge->slot_get = tsi148_slot_get; | |
7f58f025 MV |
2472 | tsi148_bridge->alloc_consistent = tsi148_alloc_consistent; |
2473 | tsi148_bridge->free_consistent = tsi148_free_consistent; | |
d22b8ed9 | 2474 | |
29848ac9 | 2475 | data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); |
d22b8ed9 | 2476 | dev_info(&pdev->dev, "Board is%s the VME system controller\n", |
7946328f | 2477 | (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not"); |
29848ac9 | 2478 | if (!geoid) |
638f199d MW |
2479 | dev_info(&pdev->dev, "VME geographical address is %d\n", |
2480 | data & TSI148_LCSR_VSTAT_GA_M); | |
29848ac9 | 2481 | else |
638f199d MW |
2482 | dev_info(&pdev->dev, "VME geographical address is set to %d\n", |
2483 | geoid); | |
29848ac9 | 2484 | |
d22b8ed9 MW |
2485 | dev_info(&pdev->dev, "VME Write and flush and error check is %s\n", |
2486 | err_chk ? "enabled" : "disabled"); | |
2487 | ||
4839737b | 2488 | if (tsi148_crcsr_init(tsi148_bridge, pdev)) { |
d22b8ed9 MW |
2489 | dev_err(&pdev->dev, "CR/CSR configuration failed.\n"); |
2490 | goto err_crcsr; | |
4839737b | 2491 | } |
d22b8ed9 | 2492 | |
d22b8ed9 MW |
2493 | retval = vme_register_bridge(tsi148_bridge); |
2494 | if (retval != 0) { | |
2495 | dev_err(&pdev->dev, "Chip Registration failed.\n"); | |
2496 | goto err_reg; | |
2497 | } | |
2498 | ||
29848ac9 MW |
2499 | pci_set_drvdata(pdev, tsi148_bridge); |
2500 | ||
d22b8ed9 | 2501 | /* Clear VME bus "board fail", and "power-up reset" lines */ |
29848ac9 | 2502 | data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT); |
d22b8ed9 MW |
2503 | data &= ~TSI148_LCSR_VSTAT_BRDFL; |
2504 | data |= TSI148_LCSR_VSTAT_CPURST; | |
29848ac9 | 2505 | iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT); |
d22b8ed9 MW |
2506 | |
2507 | return 0; | |
2508 | ||
d22b8ed9 | 2509 | err_reg: |
29848ac9 | 2510 | tsi148_crcsr_exit(tsi148_bridge, pdev); |
d22b8ed9 | 2511 | err_crcsr: |
42fb5031 MW |
2512 | err_lm: |
2513 | /* resources are stored in link list */ | |
886953e9 | 2514 | list_for_each(pos, &tsi148_bridge->lm_resources) { |
42fb5031 MW |
2515 | lm = list_entry(pos, struct vme_lm_resource, list); |
2516 | list_del(pos); | |
2517 | kfree(lm); | |
2518 | } | |
d22b8ed9 MW |
2519 | err_dma: |
2520 | /* resources are stored in link list */ | |
886953e9 | 2521 | list_for_each(pos, &tsi148_bridge->dma_resources) { |
d22b8ed9 MW |
2522 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); |
2523 | list_del(pos); | |
2524 | kfree(dma_ctrlr); | |
2525 | } | |
2526 | err_slave: | |
2527 | /* resources are stored in link list */ | |
886953e9 | 2528 | list_for_each(pos, &tsi148_bridge->slave_resources) { |
d22b8ed9 MW |
2529 | slave_image = list_entry(pos, struct vme_slave_resource, list); |
2530 | list_del(pos); | |
2531 | kfree(slave_image); | |
2532 | } | |
2533 | err_master: | |
2534 | /* resources are stored in link list */ | |
886953e9 | 2535 | list_for_each(pos, &tsi148_bridge->master_resources) { |
7946328f MW |
2536 | master_image = list_entry(pos, struct vme_master_resource, |
2537 | list); | |
d22b8ed9 MW |
2538 | list_del(pos); |
2539 | kfree(master_image); | |
2540 | } | |
2541 | ||
a82ad05e | 2542 | tsi148_irq_exit(tsi148_bridge, pdev); |
d22b8ed9 MW |
2543 | err_irq: |
2544 | err_test: | |
29848ac9 | 2545 | iounmap(tsi148_device->base); |
d22b8ed9 MW |
2546 | err_remap: |
2547 | pci_release_regions(pdev); | |
2548 | err_resource: | |
2549 | pci_disable_device(pdev); | |
2550 | err_enable: | |
29848ac9 MW |
2551 | kfree(tsi148_device); |
2552 | err_driver: | |
d22b8ed9 MW |
2553 | kfree(tsi148_bridge); |
2554 | err_struct: | |
2555 | return retval; | |
2556 | ||
2557 | } | |
2558 | ||
2559 | static void tsi148_remove(struct pci_dev *pdev) | |
2560 | { | |
2561 | struct list_head *pos = NULL; | |
b558ba2f | 2562 | struct list_head *tmplist; |
d22b8ed9 MW |
2563 | struct vme_master_resource *master_image; |
2564 | struct vme_slave_resource *slave_image; | |
2565 | struct vme_dma_resource *dma_ctrlr; | |
2566 | int i; | |
29848ac9 MW |
2567 | struct tsi148_driver *bridge; |
2568 | struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev); | |
2569 | ||
2570 | bridge = tsi148_bridge->driver_priv; | |
d22b8ed9 | 2571 | |
d22b8ed9 | 2572 | |
29848ac9 | 2573 | dev_dbg(&pdev->dev, "Driver is being unloaded.\n"); |
d22b8ed9 MW |
2574 | |
2575 | /* | |
2576 | * Shutdown all inbound and outbound windows. | |
2577 | */ | |
2578 | for (i = 0; i < 8; i++) { | |
29848ac9 | 2579 | iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] + |
d22b8ed9 | 2580 | TSI148_LCSR_OFFSET_ITAT); |
29848ac9 | 2581 | iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] + |
d22b8ed9 MW |
2582 | TSI148_LCSR_OFFSET_OTAT); |
2583 | } | |
2584 | ||
2585 | /* | |
2586 | * Shutdown Location monitor. | |
2587 | */ | |
29848ac9 | 2588 | iowrite32be(0, bridge->base + TSI148_LCSR_LMAT); |
d22b8ed9 MW |
2589 | |
2590 | /* | |
2591 | * Shutdown CRG map. | |
2592 | */ | |
29848ac9 | 2593 | iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT); |
d22b8ed9 MW |
2594 | |
2595 | /* | |
2596 | * Clear error status. | |
2597 | */ | |
29848ac9 MW |
2598 | iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT); |
2599 | iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT); | |
2600 | iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT); | |
d22b8ed9 MW |
2601 | |
2602 | /* | |
2603 | * Remove VIRQ interrupt (if any) | |
2604 | */ | |
29848ac9 MW |
2605 | if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800) |
2606 | iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR); | |
d22b8ed9 | 2607 | |
d22b8ed9 MW |
2608 | /* |
2609 | * Map all Interrupts to PCI INTA | |
2610 | */ | |
29848ac9 MW |
2611 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1); |
2612 | iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2); | |
d22b8ed9 | 2613 | |
a82ad05e | 2614 | tsi148_irq_exit(tsi148_bridge, pdev); |
d22b8ed9 MW |
2615 | |
2616 | vme_unregister_bridge(tsi148_bridge); | |
2617 | ||
29848ac9 | 2618 | tsi148_crcsr_exit(tsi148_bridge, pdev); |
d22b8ed9 MW |
2619 | |
2620 | /* resources are stored in link list */ | |
b558ba2f | 2621 | list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) { |
d22b8ed9 MW |
2622 | dma_ctrlr = list_entry(pos, struct vme_dma_resource, list); |
2623 | list_del(pos); | |
2624 | kfree(dma_ctrlr); | |
2625 | } | |
2626 | ||
2627 | /* resources are stored in link list */ | |
b558ba2f | 2628 | list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) { |
d22b8ed9 MW |
2629 | slave_image = list_entry(pos, struct vme_slave_resource, list); |
2630 | list_del(pos); | |
2631 | kfree(slave_image); | |
2632 | } | |
2633 | ||
2634 | /* resources are stored in link list */ | |
b558ba2f | 2635 | list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) { |
638f199d MW |
2636 | master_image = list_entry(pos, struct vme_master_resource, |
2637 | list); | |
d22b8ed9 MW |
2638 | list_del(pos); |
2639 | kfree(master_image); | |
2640 | } | |
2641 | ||
29848ac9 | 2642 | iounmap(bridge->base); |
d22b8ed9 MW |
2643 | |
2644 | pci_release_regions(pdev); | |
2645 | ||
2646 | pci_disable_device(pdev); | |
2647 | ||
29848ac9 MW |
2648 | kfree(tsi148_bridge->driver_priv); |
2649 | ||
d22b8ed9 MW |
2650 | kfree(tsi148_bridge); |
2651 | } | |
2652 | ||
2653 | static void __exit tsi148_exit(void) | |
2654 | { | |
2655 | pci_unregister_driver(&tsi148_driver); | |
d22b8ed9 MW |
2656 | } |
2657 | ||
2658 | MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes"); | |
2659 | module_param(err_chk, bool, 0); | |
2660 | ||
638f199d MW |
2661 | MODULE_PARM_DESC(geoid, "Override geographical addressing"); |
2662 | module_param(geoid, int, 0); | |
2663 | ||
d22b8ed9 MW |
2664 | MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge"); |
2665 | MODULE_LICENSE("GPL"); | |
2666 | ||
2667 | module_init(tsi148_init); | |
2668 | module_exit(tsi148_exit); |