]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - drivers/staging/vme/bridges/vme_tsi148.c
projects / mirror_ubuntu-eoan-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
staging: vme: correct array overflow
[mirror_ubuntu-eoan-kernel.git] / drivers / staging / vme / bridges / vme_tsi148.c
CommitLineData
d22b8ed9
MW		 1/*
2 * Support for the Tundra TSI148 VME-PCI Bridge Chip
3 *
4 * Author: Martyn Welch <martyn.welch@gefanuc.com>
5 * Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
d22b8ed9
MW		 16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/mm.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/proc_fs.h>
22#include <linux/pci.h>
23#include <linux/poll.h>
24#include <linux/dma-mapping.h>
25#include <linux/interrupt.h>
26#include <linux/spinlock.h>
6af783c8 27#include <linux/sched.h>
d22b8ed9
MW		 28#include <asm/time.h>
29#include <asm/io.h>
30#include <asm/uaccess.h>
31
32#include "../vme.h"
33#include "../vme_bridge.h"
34#include "vme_tsi148.h"
35
36static int __init tsi148_init(void);
37static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
38static void tsi148_remove(struct pci_dev *);
39static void __exit tsi148_exit(void);
40
41
42int tsi148_slave_set(struct vme_slave_resource *, int, unsigned long long,
43 unsigned long long, dma_addr_t, vme_address_t, vme_cycle_t);
44int tsi148_slave_get(struct vme_slave_resource *, int *, unsigned long long *,
45 unsigned long long *, dma_addr_t *, vme_address_t *, vme_cycle_t *);
46
47int tsi148_master_get(struct vme_master_resource *, int *, unsigned long long *,
48 unsigned long long *, vme_address_t *, vme_cycle_t *, vme_width_t *);
49int tsi148_master_set(struct vme_master_resource *, int, unsigned long long,
50 unsigned long long, vme_address_t, vme_cycle_t, vme_width_t);
51ssize_t tsi148_master_read(struct vme_master_resource *, void *, size_t,
52 loff_t);
53ssize_t tsi148_master_write(struct vme_master_resource *, void *, size_t,
54 loff_t);
55unsigned int tsi148_master_rmw(struct vme_master_resource *, unsigned int,
56 unsigned int, unsigned int, loff_t);
57int tsi148_dma_list_add (struct vme_dma_list *, struct vme_dma_attr *,
58 struct vme_dma_attr *, size_t);
59int tsi148_dma_list_exec(struct vme_dma_list *);
60int tsi148_dma_list_empty(struct vme_dma_list *);
61int tsi148_generate_irq(int, int);
d22b8ed9
MW		 62int tsi148_slot_get(void);
63
64/* Modue parameter */
65int err_chk = 0;
66
67/* XXX These should all be in a per device structure */
68struct vme_bridge *tsi148_bridge;
69wait_queue_head_t dma_queue[2];
70wait_queue_head_t iack_queue;
71void (*lm_callback[4])(int); /* Called in interrupt handler, be careful! */
72void *crcsr_kernel;
73dma_addr_t crcsr_bus;
74struct vme_master_resource *flush_image;
400822fe
MW		 75struct mutex vme_rmw; /* Only one RMW cycle at a time */
76struct mutex vme_int; /*
d22b8ed9
MW		 77 * Only one VME interrupt can be
78 * generated at a time, provide locking
79 */
400822fe 80struct mutex vme_irq; /* Locking for VME irq callback configuration */
d22b8ed9
MW		 81
82
83static char driver_name[] = "vme_tsi148";
84
85static struct pci_device_id tsi148_ids[] = {
86 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
87 { },
88};
89
90static struct pci_driver tsi148_driver = {
91 .name = driver_name,
92 .id_table = tsi148_ids,
93 .probe = tsi148_probe,
94 .remove = tsi148_remove,
95};
96
97static void reg_join(unsigned int high, unsigned int low,
98 unsigned long long *variable)
99{
100 *variable = (unsigned long long)high << 32;
101 *variable |= (unsigned long long)low;
102}
103
104static void reg_split(unsigned long long variable, unsigned int *high,
105 unsigned int *low)
106{
107 *low = (unsigned int)variable & 0xFFFFFFFF;
108 *high = (unsigned int)(variable >> 32);
109}
110
111/*
112 * Wakes up DMA queue.
113 */
114static u32 tsi148_DMA_irqhandler(int channel_mask)
115{
116 u32 serviced = 0;
117
118 if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
119 wake_up(&dma_queue[0]);
120 serviced |= TSI148_LCSR_INTC_DMA0C;
121 }
122 if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
123 wake_up(&dma_queue[1]);
124 serviced |= TSI148_LCSR_INTC_DMA1C;
125 }
126
127 return serviced;
128}
129
130/*
131 * Wake up location monitor queue
132 */
133static u32 tsi148_LM_irqhandler(u32 stat)
134{
135 int i;
136 u32 serviced = 0;
137
138 for (i = 0; i < 4; i++) {
139 if(stat & TSI148_LCSR_INTS_LMS[i]) {
140 /* We only enable interrupts if the callback is set */
141 lm_callback[i](i);
142 serviced |= TSI148_LCSR_INTC_LMC[i];
143 }
144 }
145
146 return serviced;
147}
148
149/*
150 * Wake up mail box queue.
151 *
152 * XXX This functionality is not exposed up though API.
153 */
154static u32 tsi148_MB_irqhandler(u32 stat)
155{
156 int i;
157 u32 val;
158 u32 serviced = 0;
159
160 for (i = 0; i < 4; i++) {
161 if(stat & TSI148_LCSR_INTS_MBS[i]) {
162 val = ioread32be(tsi148_bridge->base +
163 TSI148_GCSR_MBOX[i]);
164 printk("VME Mailbox %d received: 0x%x\n", i, val);
165 serviced |= TSI148_LCSR_INTC_MBC[i];
166 }
167 }
168
169 return serviced;
170}
171
172/*
173 * Display error & status message when PERR (PCI) exception interrupt occurs.
174 */
175static u32 tsi148_PERR_irqhandler(void)
176{
177 printk(KERN_ERR
178 "PCI Exception at address: 0x%08x:%08x, attributes: %08x\n",
179 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAU),
180 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAL),
181 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPAT)
182 );
183 printk(KERN_ERR
184 "PCI-X attribute reg: %08x, PCI-X split completion reg: %08x\n",
185 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXA),
186 ioread32be(tsi148_bridge->base + TSI148_LCSR_EDPXS)
187 );
188
189 iowrite32be(TSI148_LCSR_EDPAT_EDPCL,
190 tsi148_bridge->base + TSI148_LCSR_EDPAT);
191
192 return TSI148_LCSR_INTC_PERRC;
193}
194
195/*
196 * Save address and status when VME error interrupt occurs.
197 */
198static u32 tsi148_VERR_irqhandler(void)
199{
200 unsigned int error_addr_high, error_addr_low;
201 unsigned long long error_addr;
202 u32 error_attrib;
203 struct vme_bus_error *error;
204
205 error_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAU);
206 error_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAL);
207 error_attrib = ioread32be(tsi148_bridge->base + TSI148_LCSR_VEAT);
208
209 reg_join(error_addr_high, error_addr_low, &error_addr);
210
211 /* Check for exception register overflow (we have lost error data) */
212 if(error_attrib & TSI148_LCSR_VEAT_VEOF) {
213 printk(KERN_ERR "VME Bus Exception Overflow Occurred\n");
214 }
215
216 error = (struct vme_bus_error *)kmalloc(sizeof (struct vme_bus_error),
217 GFP_ATOMIC);
218 if (error) {
219 error->address = error_addr;
220 error->attributes = error_attrib;
221 list_add_tail(&(error->list), &(tsi148_bridge->vme_errors));
222 } else {
223 printk(KERN_ERR
224 "Unable to alloc memory for VMEbus Error reporting\n");
225 printk(KERN_ERR
226 "VME Bus Error at address: 0x%llx, attributes: %08x\n",
227 error_addr, error_attrib);
228 }
229
230 /* Clear Status */
231 iowrite32be(TSI148_LCSR_VEAT_VESCL,
232 tsi148_bridge->base + TSI148_LCSR_VEAT);
233
234 return TSI148_LCSR_INTC_VERRC;
235}
236
237/*
238 * Wake up IACK queue.
239 */
240static u32 tsi148_IACK_irqhandler(void)
241{
242 printk("tsi148_IACK_irqhandler\n");
243 wake_up(&iack_queue);
244
245 return TSI148_LCSR_INTC_IACKC;
246}
247
248/*
249 * Calling VME bus interrupt callback if provided.
250 */
251static u32 tsi148_VIRQ_irqhandler(u32 stat)
252{
253 int vec, i, serviced = 0;
254 void (*call)(int, int, void *);
255 void *priv_data;
256
257 for (i = 7; i > 0; i--) {
258 if (stat & (1 << i)) {
259 /*
260 * Note: Even though the registers are defined
261 * as 32-bits in the spec, we only want to issue
262 * 8-bit IACK cycles on the bus, read from offset
263 * 3.
264 */
265 vec = ioread8(tsi148_bridge->base +
266 TSI148_LCSR_VIACK[i] + 3);
267
268 call = tsi148_bridge->irq[i - 1].callback[vec].func;
269 priv_data =
270 tsi148_bridge->irq[i-1].callback[vec].priv_data;
271
272 if (call != NULL)
273 call(i, vec, priv_data);
274 else
275 printk("Spurilous VME interrupt, level:%x, "
276 "vector:%x\n", i, vec);
277
278 serviced |= (1 << i);
279 }
280 }
281
282 return serviced;
283}
284
285/*
286 * Top level interrupt handler. Clears appropriate interrupt status bits and
287 * then calls appropriate sub handler(s).
288 */
289static irqreturn_t tsi148_irqhandler(int irq, void *dev_id)
290{
291 u32 stat, enable, serviced = 0;
292
293 /* Determine which interrupts are unmasked and set */
294 enable = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
295 stat = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTS);
296
297 /* Only look at unmasked interrupts */
298 stat &= enable;
299
300 if (unlikely(!stat)) {
301 return IRQ_NONE;
302 }
303
304 /* Call subhandlers as appropriate */
305 /* DMA irqs */
306 if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
307 serviced |= tsi148_DMA_irqhandler(stat);
308
309 /* Location monitor irqs */
310 if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
311 TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
312 serviced |= tsi148_LM_irqhandler(stat);
313
314 /* Mail box irqs */
315 if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
316 TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
317 serviced |= tsi148_MB_irqhandler(stat);
318
319 /* PCI bus error */
320 if (stat & TSI148_LCSR_INTS_PERRS)
321 serviced |= tsi148_PERR_irqhandler();
322
323 /* VME bus error */
324 if (stat & TSI148_LCSR_INTS_VERRS)
325 serviced |= tsi148_VERR_irqhandler();
326
327 /* IACK irq */
328 if (stat & TSI148_LCSR_INTS_IACKS)
329 serviced |= tsi148_IACK_irqhandler();
330
331 /* VME bus irqs */
332 if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
333 TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
334 TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
335 TSI148_LCSR_INTS_IRQ1S))
336 serviced |= tsi148_VIRQ_irqhandler(stat);
337
338 /* Clear serviced interrupts */
339 iowrite32be(serviced, tsi148_bridge->base + TSI148_LCSR_INTC);
340
341 return IRQ_HANDLED;
342}
343
344static int tsi148_irq_init(struct vme_bridge *bridge)
345{
346 int result;
347 unsigned int tmp;
348 struct pci_dev *pdev;
349
350 /* Need pdev */
351 pdev = container_of(bridge->parent, struct pci_dev, dev);
352
353 /* Initialise list for VME bus errors */
354 INIT_LIST_HEAD(&(bridge->vme_errors));
355
356 result = request_irq(pdev->irq,
357 tsi148_irqhandler,
358 IRQF_SHARED,
359 driver_name, pdev);
360 if (result) {
361 dev_err(&pdev->dev, "Can't get assigned pci irq vector %02X\n",
362 pdev->irq);
363 return result;
364 }
365
366 /* Enable and unmask interrupts */
367 tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
368 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
369 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
370 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
371 TSI148_LCSR_INTEO_IACKEO;
372
373 /* XXX This leaves the following interrupts masked.
374 * TSI148_LCSR_INTEO_VIEEO
375 * TSI148_LCSR_INTEO_SYSFLEO
376 * TSI148_LCSR_INTEO_ACFLEO
377 */
378
379 /* Don't enable Location Monitor interrupts here - they will be
380 * enabled when the location monitors are properly configured and
381 * a callback has been attached.
382 * TSI148_LCSR_INTEO_LM0EO
383 * TSI148_LCSR_INTEO_LM1EO
384 * TSI148_LCSR_INTEO_LM2EO
385 * TSI148_LCSR_INTEO_LM3EO
386 */
387
388 /* Don't enable VME interrupts until we add a handler, else the board
389 * will respond to it and we don't want that unless it knows how to
390 * properly deal with it.
391 * TSI148_LCSR_INTEO_IRQ7EO
392 * TSI148_LCSR_INTEO_IRQ6EO
393 * TSI148_LCSR_INTEO_IRQ5EO
394 * TSI148_LCSR_INTEO_IRQ4EO
395 * TSI148_LCSR_INTEO_IRQ3EO
396 * TSI148_LCSR_INTEO_IRQ2EO
397 * TSI148_LCSR_INTEO_IRQ1EO
398 */
399
400 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
401 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
402
403 return 0;
404}
405
406static void tsi148_irq_exit(struct pci_dev *pdev)
407{
408 /* Turn off interrupts */
409 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEO);
410 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEN);
411
412 /* Clear all interrupts */
413 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTC);
414
415 /* Detach interrupt handler */
416 free_irq(pdev->irq, pdev);
417}
418
419/*
420 * Check to see if an IACk has been received, return true (1) or false (0).
421 */
422int tsi148_iack_received(void)
423{
424 u32 tmp;
425
426 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR);
427
428 if (tmp & TSI148_LCSR_VICR_IRQS)
429 return 0;
430 else
431 return 1;
432}
433
434/*
435 * Set up an VME interrupt
436 */
437int tsi148_request_irq(int level, int statid,
438 void (*callback)(int level, int vector, void *priv_data),
439 void *priv_data)
440{
441 u32 tmp;
442
400822fe 443 mutex_lock(&(vme_irq));
d22b8ed9
MW		 444
445 if(tsi148_bridge->irq[level - 1].callback[statid].func) {
400822fe 446 mutex_unlock(&(vme_irq));
d22b8ed9
MW		 447 printk("VME Interrupt already taken\n");
448 return -EBUSY;
449 }
450
451
452 tsi148_bridge->irq[level - 1].count++;
453 tsi148_bridge->irq[level - 1].callback[statid].priv_data = priv_data;
454 tsi148_bridge->irq[level - 1].callback[statid].func = callback;
455
456 /* Enable IRQ level */
457 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
458 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
459 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
460
461 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
462 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
463 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
464
400822fe 465 mutex_unlock(&(vme_irq));
d22b8ed9
MW		 466
467 return 0;
468}
469
470/*
471 * Free VME interrupt
472 */
473void tsi148_free_irq(int level, int statid)
474{
475 u32 tmp;
75155020 476 struct pci_dev *pdev;
d22b8ed9 477
400822fe 478 mutex_lock(&(vme_irq));
d22b8ed9 479
d22b8ed9
MW		 480 tsi148_bridge->irq[level - 1].count--;
481
df455175 482 /* Disable IRQ level if no more interrupts attached at this level*/
d22b8ed9 483 if (tsi148_bridge->irq[level - 1].count == 0) {
d22b8ed9
MW		 484 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
485 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
486 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
df455175
MW		 487
488 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
489 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
490 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
75155020
MW		 491
492 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
493
494 synchronize_irq(pdev->irq);
d22b8ed9
MW		 495 }
496
df455175
MW		 497 tsi148_bridge->irq[level - 1].callback[statid].func = NULL;
498 tsi148_bridge->irq[level - 1].callback[statid].priv_data = NULL;
499
400822fe 500 mutex_unlock(&(vme_irq));
d22b8ed9
MW		 501}
502
503/*
504 * Generate a VME bus interrupt at the requested level & vector. Wait for
505 * interrupt to be acked.
d22b8ed9
MW		 506 */
507int tsi148_generate_irq(int level, int statid)
508{
509 u32 tmp;
510
400822fe 511 mutex_lock(&(vme_int));
d22b8ed9
MW		 512
513 /* Read VICR register */
514 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR);
515
516 /* Set Status/ID */
517 tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
518 (statid & TSI148_LCSR_VICR_STID_M);
519 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR);
520
521 /* Assert VMEbus IRQ */
522 tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
523 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VICR);
524
525 /* XXX Consider implementing a timeout? */
526 wait_event_interruptible(iack_queue, tsi148_iack_received());
527
400822fe 528 mutex_unlock(&(vme_int));
d22b8ed9
MW		 529
530 return 0;
531}
532
533/*
534 * Find the first error in this address range
535 */
536static struct vme_bus_error *tsi148_find_error(vme_address_t aspace,
537 unsigned long long address, size_t count)
538{
539 struct list_head *err_pos;
540 struct vme_bus_error *vme_err, *valid = NULL;
541 unsigned long long bound;
542
543 bound = address + count;
544
545 /*
546 * XXX We are currently not looking at the address space when parsing
547 * for errors. This is because parsing the Address Modifier Codes
548 * is going to be quite resource intensive to do properly. We
549 * should be OK just looking at the addresses and this is certainly
550 * much better than what we had before.
551 */
552 err_pos = NULL;
553 /* Iterate through errors */
554 list_for_each(err_pos, &(tsi148_bridge->vme_errors)) {
555 vme_err = list_entry(err_pos, struct vme_bus_error, list);
556 if((vme_err->address >= address) && (vme_err->address < bound)){
557 valid = vme_err;
558 break;
559 }
560 }
561
562 return valid;
563}
564
565/*
566 * Clear errors in the provided address range.
567 */
568static void tsi148_clear_errors(vme_address_t aspace,
569 unsigned long long address, size_t count)
570{
571 struct list_head *err_pos, *temp;
572 struct vme_bus_error *vme_err;
573 unsigned long long bound;
574
575 bound = address + count;
576
577 /*
578 * XXX We are currently not looking at the address space when parsing
579 * for errors. This is because parsing the Address Modifier Codes
580 * is going to be quite resource intensive to do properly. We
581 * should be OK just looking at the addresses and this is certainly
582 * much better than what we had before.
583 */
584 err_pos = NULL;
585 /* Iterate through errors */
586 list_for_each_safe(err_pos, temp, &(tsi148_bridge->vme_errors)) {
587 vme_err = list_entry(err_pos, struct vme_bus_error, list);
588
589 if((vme_err->address >= address) && (vme_err->address < bound)){
590 list_del(err_pos);
591 kfree(vme_err);
592 }
593 }
594}
595
596/*
597 * Initialize a slave window with the requested attributes.
598 */
599int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
600 unsigned long long vme_base, unsigned long long size,
601 dma_addr_t pci_base, vme_address_t aspace, vme_cycle_t cycle)
602{
603 unsigned int i, addr = 0, granularity = 0;
604 unsigned int temp_ctl = 0;
605 unsigned int vme_base_low, vme_base_high;
606 unsigned int vme_bound_low, vme_bound_high;
607 unsigned int pci_offset_low, pci_offset_high;
608 unsigned long long vme_bound, pci_offset;
609
610#if 0
611 printk("Set slave image %d to:\n", image->number);
612 printk("\tEnabled: %s\n", (enabled == 1)? "yes" : "no");
613 printk("\tVME Base:0x%llx\n", vme_base);
614 printk("\tWindow Size:0x%llx\n", size);
615 printk("\tPCI Base:0x%lx\n", (unsigned long)pci_base);
616 printk("\tAddress Space:0x%x\n", aspace);
617 printk("\tTransfer Cycle Properties:0x%x\n", cycle);
618#endif
619
620 i = image->number;
621
622 switch (aspace) {
623 case VME_A16:
624 granularity = 0x10;
625 addr |= TSI148_LCSR_ITAT_AS_A16;
626 break;
627 case VME_A24:
628 granularity = 0x1000;
629 addr |= TSI148_LCSR_ITAT_AS_A24;
630 break;
631 case VME_A32:
632 granularity = 0x10000;
633 addr |= TSI148_LCSR_ITAT_AS_A32;
634 break;
635 case VME_A64:
636 granularity = 0x10000;
637 addr |= TSI148_LCSR_ITAT_AS_A64;
638 break;
639 case VME_CRCSR:
640 case VME_USER1:
641 case VME_USER2:
642 case VME_USER3:
643 case VME_USER4:
644 default:
645 printk("Invalid address space\n");
646 return -EINVAL;
647 break;
648 }
649
650 /* Convert 64-bit variables to 2x 32-bit variables */
651 reg_split(vme_base, &vme_base_high, &vme_base_low);
652
653 /*
654 * Bound address is a valid address for the window, adjust
655 * accordingly
656 */
657 vme_bound = vme_base + size - granularity;
658 reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
659 pci_offset = (unsigned long long)pci_base - vme_base;
660 reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
661
662 if (vme_base_low & (granularity - 1)) {
663 printk("Invalid VME base alignment\n");
664 return -EINVAL;
665 }
666 if (vme_bound_low & (granularity - 1)) {
667 printk("Invalid VME bound alignment\n");
668 return -EINVAL;
669 }
670 if (pci_offset_low & (granularity - 1)) {
671 printk("Invalid PCI Offset alignment\n");
672 return -EINVAL;
673 }
674
675#if 0
676 printk("\tVME Bound:0x%llx\n", vme_bound);
677 printk("\tPCI Offset:0x%llx\n", pci_offset);
678#endif
679
680 /* Disable while we are mucking around */
681 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
682 TSI148_LCSR_OFFSET_ITAT);
683 temp_ctl &= ~TSI148_LCSR_ITAT_EN;
684 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
685 TSI148_LCSR_OFFSET_ITAT);
686
687 /* Setup mapping */
688 iowrite32be(vme_base_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
689 TSI148_LCSR_OFFSET_ITSAU);
690 iowrite32be(vme_base_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
691 TSI148_LCSR_OFFSET_ITSAL);
692 iowrite32be(vme_bound_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
693 TSI148_LCSR_OFFSET_ITEAU);
694 iowrite32be(vme_bound_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
695 TSI148_LCSR_OFFSET_ITEAL);
696 iowrite32be(pci_offset_high, tsi148_bridge->base + TSI148_LCSR_IT[i] +
697 TSI148_LCSR_OFFSET_ITOFU);
698 iowrite32be(pci_offset_low, tsi148_bridge->base + TSI148_LCSR_IT[i] +
699 TSI148_LCSR_OFFSET_ITOFL);
700
701/* XXX Prefetch stuff currently unsupported */
702#if 0
703
704 for (x = 0; x < 4; x++) {
705 if ((64 << x) >= vmeIn->prefetchSize) {
706 break;
707 }
708 }
709 if (x == 4)
710 x--;
711 temp_ctl |= (x << 16);
712
713 if (vmeIn->prefetchThreshold)
714 if (vmeIn->prefetchThreshold)
715 temp_ctl |= 0x40000;
716#endif
717
718 /* Setup 2eSST speeds */
719 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
720 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
721 case VME_2eSST160:
722 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
723 break;
724 case VME_2eSST267:
725 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
726 break;
727 case VME_2eSST320:
728 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
729 break;
730 }
731
732 /* Setup cycle types */
733 temp_ctl &= ~(0x1F << 7);
734 if (cycle & VME_BLT)
735 temp_ctl |= TSI148_LCSR_ITAT_BLT;
736 if (cycle & VME_MBLT)
737 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
738 if (cycle & VME_2eVME)
739 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
740 if (cycle & VME_2eSST)
741 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
742 if (cycle & VME_2eSSTB)
743 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
744
745 /* Setup address space */
746 temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
747 temp_ctl |= addr;
748
749 temp_ctl &= ~0xF;
750 if (cycle & VME_SUPER)
751 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
752 if (cycle & VME_USER)
753 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
754 if (cycle & VME_PROG)
755 temp_ctl |= TSI148_LCSR_ITAT_PGM;
756 if (cycle & VME_DATA)
757 temp_ctl |= TSI148_LCSR_ITAT_DATA;
758
759 /* Write ctl reg without enable */
760 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
761 TSI148_LCSR_OFFSET_ITAT);
762
763 if (enabled)
764 temp_ctl |= TSI148_LCSR_ITAT_EN;
765
766 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_IT[i] +
767 TSI148_LCSR_OFFSET_ITAT);
768
769 return 0;
770}
771
772/*
773 * Get slave window configuration.
774 *
775 * XXX Prefetch currently unsupported.
776 */
777int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
778 unsigned long long *vme_base, unsigned long long *size,
779 dma_addr_t *pci_base, vme_address_t *aspace, vme_cycle_t *cycle)
780{
781 unsigned int i, granularity = 0, ctl = 0;
782 unsigned int vme_base_low, vme_base_high;
783 unsigned int vme_bound_low, vme_bound_high;
784 unsigned int pci_offset_low, pci_offset_high;
785 unsigned long long vme_bound, pci_offset;
786
787
788 i = image->number;
789
790 /* Read registers */
791 ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
792 TSI148_LCSR_OFFSET_ITAT);
793
794 vme_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
795 TSI148_LCSR_OFFSET_ITSAU);
796 vme_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
797 TSI148_LCSR_OFFSET_ITSAL);
798 vme_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
799 TSI148_LCSR_OFFSET_ITEAU);
800 vme_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
801 TSI148_LCSR_OFFSET_ITEAL);
802 pci_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
803 TSI148_LCSR_OFFSET_ITOFU);
804 pci_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_IT[i] +
805 TSI148_LCSR_OFFSET_ITOFL);
806
807 /* Convert 64-bit variables to 2x 32-bit variables */
808 reg_join(vme_base_high, vme_base_low, vme_base);
809 reg_join(vme_bound_high, vme_bound_low, &vme_bound);
810 reg_join(pci_offset_high, pci_offset_low, &pci_offset);
811
812 *pci_base = (dma_addr_t)vme_base + pci_offset;
813
814 *enabled = 0;
815 *aspace = 0;
816 *cycle = 0;
817
818 if (ctl & TSI148_LCSR_ITAT_EN)
819 *enabled = 1;
820
821 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
822 granularity = 0x10;
823 *aspace |= VME_A16;
824 }
825 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
826 granularity = 0x1000;
827 *aspace |= VME_A24;
828 }
829 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
830 granularity = 0x10000;
831 *aspace |= VME_A32;
832 }
833 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
834 granularity = 0x10000;
835 *aspace |= VME_A64;
836 }
837
838 /* Need granularity before we set the size */
839 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
840
841
842 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
843 *cycle |= VME_2eSST160;
844 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
845 *cycle |= VME_2eSST267;
846 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
847 *cycle |= VME_2eSST320;
848
849 if (ctl & TSI148_LCSR_ITAT_BLT)
850 *cycle |= VME_BLT;
851 if (ctl & TSI148_LCSR_ITAT_MBLT)
852 *cycle |= VME_MBLT;
853 if (ctl & TSI148_LCSR_ITAT_2eVME)
854 *cycle |= VME_2eVME;
855 if (ctl & TSI148_LCSR_ITAT_2eSST)
856 *cycle |= VME_2eSST;
857 if (ctl & TSI148_LCSR_ITAT_2eSSTB)
858 *cycle |= VME_2eSSTB;
859
860 if (ctl & TSI148_LCSR_ITAT_SUPR)
861 *cycle |= VME_SUPER;
862 if (ctl & TSI148_LCSR_ITAT_NPRIV)
863 *cycle |= VME_USER;
864 if (ctl & TSI148_LCSR_ITAT_PGM)
865 *cycle |= VME_PROG;
866 if (ctl & TSI148_LCSR_ITAT_DATA)
867 *cycle |= VME_DATA;
868
869 return 0;
870}
871
872/*
873 * Allocate and map PCI Resource
874 */
875static int tsi148_alloc_resource(struct vme_master_resource *image,
876 unsigned long long size)
877{
878 unsigned long long existing_size;
879 int retval = 0;
880 struct pci_dev *pdev;
881
882 /* Find pci_dev container of dev */
883 if (tsi148_bridge->parent == NULL) {
884 printk("Dev entry NULL\n");
885 return -EINVAL;
886 }
887 pdev = container_of(tsi148_bridge->parent, struct pci_dev, dev);
888
889 existing_size = (unsigned long long)(image->pci_resource.end -
890 image->pci_resource.start);
891
892 /* If the existing size is OK, return */
893 if (existing_size == (size - 1))
894 return 0;
895
896 if (existing_size != 0) {
897 iounmap(image->kern_base);
898 image->kern_base = NULL;
899 if (image->pci_resource.name != NULL)
900 kfree(image->pci_resource.name);
901 release_resource(&(image->pci_resource));
902 memset(&(image->pci_resource), 0, sizeof(struct resource));
903 }
904
905 if (image->pci_resource.name == NULL) {
906 image->pci_resource.name = kmalloc(VMENAMSIZ+3, GFP_KERNEL);
907 if (image->pci_resource.name == NULL) {
908 printk(KERN_ERR "Unable to allocate memory for resource"
909 " name\n");
910 retval = -ENOMEM;
911 goto err_name;
912 }
913 }
914
915 sprintf((char *)image->pci_resource.name, "%s.%d", tsi148_bridge->name,
916 image->number);
917
918 image->pci_resource.start = 0;
919 image->pci_resource.end = (unsigned long)size;
920 image->pci_resource.flags = IORESOURCE_MEM;
921
922 retval = pci_bus_alloc_resource(pdev->bus,
923 &(image->pci_resource), size, size, PCIBIOS_MIN_MEM,
924 0, NULL, NULL);
925 if (retval) {
926 printk(KERN_ERR "Failed to allocate mem resource for "
927 "window %d size 0x%lx start 0x%lx\n",
928 image->number, (unsigned long)size,
929 (unsigned long)image->pci_resource.start);
930 goto err_resource;
931 }
932
933 image->kern_base = ioremap_nocache(
934 image->pci_resource.start, size);
935 if (image->kern_base == NULL) {
936 printk(KERN_ERR "Failed to remap resource\n");
937 retval = -ENOMEM;
938 goto err_remap;
939 }
940
941 return 0;
942
943 iounmap(image->kern_base);
944 image->kern_base = NULL;
945err_remap:
946 release_resource(&(image->pci_resource));
947err_resource:
948 kfree(image->pci_resource.name);
949 memset(&(image->pci_resource), 0, sizeof(struct resource));
950err_name:
951 return retval;
952}
953
954/*
955 * Free and unmap PCI Resource
956 */
957static void tsi148_free_resource(struct vme_master_resource *image)
958{
959 iounmap(image->kern_base);
960 image->kern_base = NULL;
961 release_resource(&(image->pci_resource));
962 kfree(image->pci_resource.name);
963 memset(&(image->pci_resource), 0, sizeof(struct resource));
964}
965
966/*
967 * Set the attributes of an outbound window.
968 */
969int tsi148_master_set( struct vme_master_resource *image, int enabled,
970 unsigned long long vme_base, unsigned long long size,
971 vme_address_t aspace, vme_cycle_t cycle, vme_width_t dwidth)
972{
973 int retval = 0;
974 unsigned int i;
975 unsigned int temp_ctl = 0;
976 unsigned int pci_base_low, pci_base_high;
977 unsigned int pci_bound_low, pci_bound_high;
978 unsigned int vme_offset_low, vme_offset_high;
979 unsigned long long pci_bound, vme_offset, pci_base;
980
981 /* Verify input data */
982 if (vme_base & 0xFFFF) {
983 printk("Invalid VME Window alignment\n");
984 retval = -EINVAL;
985 goto err_window;
986 }
987 if (size < 0x10000) {
988 printk("Invalid VME Window size\n");
989 retval = -EINVAL;
990 goto err_window;
991 }
992
993 spin_lock(&(image->lock));
994
995 /* Let's allocate the resource here rather than further up the stack as
996 * it avoids pushing loads of bus dependant stuff up the stack
997 */
998 retval = tsi148_alloc_resource(image, size);
999 if (retval) {
1000 spin_unlock(&(image->lock));
1001 printk(KERN_ERR "Unable to allocate memory for resource "
1002 "name\n");
1003 retval = -ENOMEM;
1004 goto err_res;
1005 }
1006
1007 pci_base = (unsigned long long)image->pci_resource.start;
1008
1009
1010 /*
1011 * Bound address is a valid address for the window, adjust
1012 * according to window granularity.
1013 */
1014 pci_bound = pci_base + (size - 0x10000);
1015 vme_offset = vme_base - pci_base;
1016
1017 /* Convert 64-bit variables to 2x 32-bit variables */
1018 reg_split(pci_base, &pci_base_high, &pci_base_low);
1019 reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
1020 reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
1021
1022 if (pci_base_low & 0xFFFF) {
1023 spin_unlock(&(image->lock));
1024 printk("Invalid PCI base alignment\n");
1025 retval = -EINVAL;
1026 goto err_gran;
1027 }
1028 if (pci_bound_low & 0xFFFF) {
1029 spin_unlock(&(image->lock));
1030 printk("Invalid PCI bound alignment\n");
1031 retval = -EINVAL;
1032 goto err_gran;
1033 }
1034 if (vme_offset_low & 0xFFFF) {
1035 spin_unlock(&(image->lock));
1036 printk("Invalid VME Offset alignment\n");
1037 retval = -EINVAL;
1038 goto err_gran;
1039 }
1040
1041 i = image->number;
1042
1043 /* Disable while we are mucking around */
1044 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1045 TSI148_LCSR_OFFSET_OTAT);
1046 temp_ctl &= ~TSI148_LCSR_OTAT_EN;
1047 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1048 TSI148_LCSR_OFFSET_OTAT);
1049
1050/* XXX Prefetch stuff currently unsupported */
1051#if 0
1052 if (vmeOut->prefetchEnable) {
1053 temp_ctl |= 0x40000;
1054 for (x = 0; x < 4; x++) {
1055 if ((2 << x) >= vmeOut->prefetchSize)
1056 break;
1057 }
1058 if (x == 4)
1059 x = 3;
1060 temp_ctl |= (x << 16);
1061 }
1062#endif
1063
1064 /* Setup 2eSST speeds */
1065 temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
1066 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1067 case VME_2eSST160:
1068 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
1069 break;
1070 case VME_2eSST267:
1071 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
1072 break;
1073 case VME_2eSST320:
1074 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
1075 break;
1076 }
1077
1078 /* Setup cycle types */
1079 if (cycle & VME_BLT) {
1080 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1081 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
1082 }
1083 if (cycle & VME_MBLT) {
1084 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1085 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
1086 }
1087 if (cycle & VME_2eVME) {
1088 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1089 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
1090 }
1091 if (cycle & VME_2eSST) {
1092 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1093 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
1094 }
1095 if (cycle & VME_2eSSTB) {
1096 printk("Currently not setting Broadcast Select Registers\n");
1097 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
1098 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
1099 }
1100
1101 /* Setup data width */
1102 temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
1103 switch (dwidth) {
1104 case VME_D16:
1105 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
1106 break;
1107 case VME_D32:
1108 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
1109 break;
1110 default:
1111 spin_unlock(&(image->lock));
1112 printk("Invalid data width\n");
1113 retval = -EINVAL;
1114 goto err_dwidth;
1115 }
1116
1117 /* Setup address space */
1118 temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
1119 switch (aspace) {
1120 case VME_A16:
1121 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
1122 break;
1123 case VME_A24:
1124 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
1125 break;
1126 case VME_A32:
1127 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
1128 break;
1129 case VME_A64:
1130 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
1131 break;
1132 case VME_CRCSR:
1133 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
1134 break;
1135 case VME_USER1:
1136 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
1137 break;
1138 case VME_USER2:
1139 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
1140 break;
1141 case VME_USER3:
1142 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
1143 break;
1144 case VME_USER4:
1145 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
1146 break;
1147 default:
1148 spin_unlock(&(image->lock));
1149 printk("Invalid address space\n");
1150 retval = -EINVAL;
1151 goto err_aspace;
1152 break;
1153 }
1154
1155 temp_ctl &= ~(3<<4);
1156 if (cycle & VME_SUPER)
1157 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1158 if (cycle & VME_PROG)
1159 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1160
1161 /* Setup mapping */
1162 iowrite32be(pci_base_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1163 TSI148_LCSR_OFFSET_OTSAU);
1164 iowrite32be(pci_base_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1165 TSI148_LCSR_OFFSET_OTSAL);
1166 iowrite32be(pci_bound_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1167 TSI148_LCSR_OFFSET_OTEAU);
1168 iowrite32be(pci_bound_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1169 TSI148_LCSR_OFFSET_OTEAL);
1170 iowrite32be(vme_offset_high, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1171 TSI148_LCSR_OFFSET_OTOFU);
1172 iowrite32be(vme_offset_low, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1173 TSI148_LCSR_OFFSET_OTOFL);
1174
1175/* XXX We need to deal with OTBS */
1176#if 0
1177 iowrite32be(vmeOut->bcastSelect2esst, tsi148_bridge->base +
1178 TSI148_LCSR_OT[i] + TSI148_LCSR_OFFSET_OTBS);
1179#endif
1180
1181 /* Write ctl reg without enable */
1182 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1183 TSI148_LCSR_OFFSET_OTAT);
1184
1185 if (enabled)
1186 temp_ctl |= TSI148_LCSR_OTAT_EN;
1187
1188 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_OT[i] +
1189 TSI148_LCSR_OFFSET_OTAT);
1190
1191 spin_unlock(&(image->lock));
1192 return 0;
1193
1194err_aspace:
1195err_dwidth:
1196err_gran:
1197 tsi148_free_resource(image);
1198err_res:
1199err_window:
1200 return retval;
1201
1202}
1203
1204/*
1205 * Set the attributes of an outbound window.
1206 *
1207 * XXX Not parsing prefetch information.
1208 */
1209int __tsi148_master_get( struct vme_master_resource *image, int *enabled,
1210 unsigned long long *vme_base, unsigned long long *size,
1211 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1212{
1213 unsigned int i, ctl;
1214 unsigned int pci_base_low, pci_base_high;
1215 unsigned int pci_bound_low, pci_bound_high;
1216 unsigned int vme_offset_low, vme_offset_high;
1217
1218 unsigned long long pci_base, pci_bound, vme_offset;
1219
1220 i = image->number;
1221
1222 ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1223 TSI148_LCSR_OFFSET_OTAT);
1224
1225 pci_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1226 TSI148_LCSR_OFFSET_OTSAU);
1227 pci_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1228 TSI148_LCSR_OFFSET_OTSAL);
1229 pci_bound_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1230 TSI148_LCSR_OFFSET_OTEAU);
1231 pci_bound_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1232 TSI148_LCSR_OFFSET_OTEAL);
1233 vme_offset_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1234 TSI148_LCSR_OFFSET_OTOFU);
1235 vme_offset_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1236 TSI148_LCSR_OFFSET_OTOFL);
1237
1238 /* Convert 64-bit variables to 2x 32-bit variables */
1239 reg_join(pci_base_high, pci_base_low, &pci_base);
1240 reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1241 reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1242
1243 *vme_base = pci_base + vme_offset;
1244 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1245
1246 *enabled = 0;
1247 *aspace = 0;
1248 *cycle = 0;
1249 *dwidth = 0;
1250
1251 if (ctl & TSI148_LCSR_OTAT_EN)
1252 *enabled = 1;
1253
1254 /* Setup address space */
1255 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1256 *aspace |= VME_A16;
1257 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1258 *aspace |= VME_A24;
1259 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1260 *aspace |= VME_A32;
1261 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1262 *aspace |= VME_A64;
1263 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1264 *aspace |= VME_CRCSR;
1265 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1266 *aspace |= VME_USER1;
1267 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1268 *aspace |= VME_USER2;
1269 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1270 *aspace |= VME_USER3;
1271 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1272 *aspace |= VME_USER4;
1273
1274 /* Setup 2eSST speeds */
1275 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1276 *cycle |= VME_2eSST160;
1277 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1278 *cycle |= VME_2eSST267;
1279 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1280 *cycle |= VME_2eSST320;
1281
1282 /* Setup cycle types */
1283 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_SCT)
1284 *cycle |= VME_SCT;
1285 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_BLT)
1286 *cycle |= VME_BLT;
1287 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_MBLT)
1288 *cycle |= VME_MBLT;
1289 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eVME)
1290 *cycle |= VME_2eVME;
1291 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSST)
1292 *cycle |= VME_2eSST;
1293 if ((ctl & TSI148_LCSR_OTAT_TM_M ) == TSI148_LCSR_OTAT_TM_2eSSTB)
1294 *cycle |= VME_2eSSTB;
1295
1296 if (ctl & TSI148_LCSR_OTAT_SUP)
1297 *cycle |= VME_SUPER;
1298 else
1299 *cycle |= VME_USER;
1300
1301 if (ctl & TSI148_LCSR_OTAT_PGM)
1302 *cycle |= VME_PROG;
1303 else
1304 *cycle |= VME_DATA;
1305
1306 /* Setup data width */
1307 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1308 *dwidth = VME_D16;
1309 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1310 *dwidth = VME_D32;
1311
1312 return 0;
1313}
1314
1315
1316int tsi148_master_get( struct vme_master_resource *image, int *enabled,
1317 unsigned long long *vme_base, unsigned long long *size,
1318 vme_address_t *aspace, vme_cycle_t *cycle, vme_width_t *dwidth)
1319{
1320 int retval;
1321
1322 spin_lock(&(image->lock));
1323
1324 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1325 cycle, dwidth);
1326
1327 spin_unlock(&(image->lock));
1328
1329 return retval;
1330}
1331
1332ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
1333 size_t count, loff_t offset)
1334{
1335 int retval, enabled;
1336 unsigned long long vme_base, size;
1337 vme_address_t aspace;
1338 vme_cycle_t cycle;
1339 vme_width_t dwidth;
1340 struct vme_bus_error *vme_err = NULL;
1341
1342 spin_lock(&(image->lock));
1343
1344 memcpy_fromio(buf, image->kern_base + offset, (unsigned int)count);
1345 retval = count;
1346
1347 if (!err_chk)
1348 goto skip_chk;
1349
1350 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1351 &dwidth);
1352
1353 vme_err = tsi148_find_error(aspace, vme_base + offset, count);
1354 if(vme_err != NULL) {
1355 dev_err(image->parent->parent, "First VME read error detected "
1356 "an at address 0x%llx\n", vme_err->address);
1357 retval = vme_err->address - (vme_base + offset);
1358 /* Clear down save errors in this address range */
1359 tsi148_clear_errors(aspace, vme_base + offset, count);
1360 }
1361
1362skip_chk:
1363 spin_unlock(&(image->lock));
1364
1365 return retval;
1366}
1367
1368
400822fe 1369/* XXX We need to change vme_master_resource->mtx to a spinlock so that read
d22b8ed9
MW		 1370 * and write functions can be used in an interrupt context
1371 */
1372ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
1373 size_t count, loff_t offset)
1374{
1375 int retval = 0, enabled;
1376 unsigned long long vme_base, size;
1377 vme_address_t aspace;
1378 vme_cycle_t cycle;
1379 vme_width_t dwidth;
1380
1381 struct vme_bus_error *vme_err = NULL;
1382
1383 spin_lock(&(image->lock));
1384
1385 memcpy_toio(image->kern_base + offset, buf, (unsigned int)count);
1386 retval = count;
1387
1388 /*
1389 * Writes are posted. We need to do a read on the VME bus to flush out
1390 * all of the writes before we check for errors. We can't guarentee
1391 * that reading the data we have just written is safe. It is believed
1392 * that there isn't any read, write re-ordering, so we can read any
1393 * location in VME space, so lets read the Device ID from the tsi148's
1394 * own registers as mapped into CR/CSR space.
1395 *
1396 * We check for saved errors in the written address range/space.
1397 */
1398
1399 if (!err_chk)
1400 goto skip_chk;
1401
1402 /*
1403 * Get window info first, to maximise the time that the buffers may
1404 * fluch on their own
1405 */
1406 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace, &cycle,
1407 &dwidth);
1408
1409 ioread16(flush_image->kern_base + 0x7F000);
1410
1411 vme_err = tsi148_find_error(aspace, vme_base + offset, count);
1412 if(vme_err != NULL) {
1413 printk("First VME write error detected an at address 0x%llx\n",
1414 vme_err->address);
1415 retval = vme_err->address - (vme_base + offset);
1416 /* Clear down save errors in this address range */
1417 tsi148_clear_errors(aspace, vme_base + offset, count);
1418 }
1419
1420skip_chk:
1421 spin_unlock(&(image->lock));
1422
1423 return retval;
1424}
1425
1426/*
1427 * Perform an RMW cycle on the VME bus.
1428 *
1429 * Requires a previously configured master window, returns final value.
1430 */
1431unsigned int tsi148_master_rmw(struct vme_master_resource *image,
1432 unsigned int mask, unsigned int compare, unsigned int swap,
1433 loff_t offset)
1434{
1435 unsigned long long pci_addr;
1436 unsigned int pci_addr_high, pci_addr_low;
1437 u32 tmp, result;
1438 int i;
1439
1440
1441 /* Find the PCI address that maps to the desired VME address */
1442 i = image->number;
1443
1444 /* Locking as we can only do one of these at a time */
400822fe 1445 mutex_lock(&(vme_rmw));
d22b8ed9
MW		 1446
1447 /* Lock image */
1448 spin_lock(&(image->lock));
1449
1450 pci_addr_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1451 TSI148_LCSR_OFFSET_OTSAU);
1452 pci_addr_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_OT[i] +
1453 TSI148_LCSR_OFFSET_OTSAL);
1454
1455 reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1456 reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1457
1458 /* Configure registers */
1459 iowrite32be(mask, tsi148_bridge->base + TSI148_LCSR_RMWEN);
1460 iowrite32be(compare, tsi148_bridge->base + TSI148_LCSR_RMWC);
1461 iowrite32be(swap, tsi148_bridge->base + TSI148_LCSR_RMWS);
1462 iowrite32be(pci_addr_high, tsi148_bridge->base + TSI148_LCSR_RMWAU);
1463 iowrite32be(pci_addr_low, tsi148_bridge->base + TSI148_LCSR_RMWAL);
1464
1465 /* Enable RMW */
1466 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1467 tmp |= TSI148_LCSR_VMCTRL_RMWEN;
1468 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1469
1470 /* Kick process off with a read to the required address. */
1471 result = ioread32be(image->kern_base + offset);
1472
1473 /* Disable RMW */
1474 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1475 tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
1476 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
1477
1478 spin_unlock(&(image->lock));
1479
400822fe 1480 mutex_unlock(&(vme_rmw));
d22b8ed9
MW		 1481
1482 return result;
1483}
1484
1485static int tsi148_dma_set_vme_src_attributes (u32 *attr, vme_address_t aspace,
1486 vme_cycle_t cycle, vme_width_t dwidth)
1487{
1488 /* Setup 2eSST speeds */
1489 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1490 case VME_2eSST160:
1491 *attr |= TSI148_LCSR_DSAT_2eSSTM_160;
1492 break;
1493 case VME_2eSST267:
1494 *attr |= TSI148_LCSR_DSAT_2eSSTM_267;
1495 break;
1496 case VME_2eSST320:
1497 *attr |= TSI148_LCSR_DSAT_2eSSTM_320;
1498 break;
1499 }
1500
1501 /* Setup cycle types */
1502 if (cycle & VME_SCT) {
1503 *attr |= TSI148_LCSR_DSAT_TM_SCT;
1504 }
1505 if (cycle & VME_BLT) {
1506 *attr |= TSI148_LCSR_DSAT_TM_BLT;
1507 }
1508 if (cycle & VME_MBLT) {
1509 *attr |= TSI148_LCSR_DSAT_TM_MBLT;
1510 }
1511 if (cycle & VME_2eVME) {
1512 *attr |= TSI148_LCSR_DSAT_TM_2eVME;
1513 }
1514 if (cycle & VME_2eSST) {
1515 *attr |= TSI148_LCSR_DSAT_TM_2eSST;
1516 }
1517 if (cycle & VME_2eSSTB) {
1518 printk("Currently not setting Broadcast Select Registers\n");
1519 *attr |= TSI148_LCSR_DSAT_TM_2eSSTB;
1520 }
1521
1522 /* Setup data width */
1523 switch (dwidth) {
1524 case VME_D16:
1525 *attr |= TSI148_LCSR_DSAT_DBW_16;
1526 break;
1527 case VME_D32:
1528 *attr |= TSI148_LCSR_DSAT_DBW_32;
1529 break;
1530 default:
1531 printk("Invalid data width\n");
1532 return -EINVAL;
1533 }
1534
1535 /* Setup address space */
1536 switch (aspace) {
1537 case VME_A16:
1538 *attr |= TSI148_LCSR_DSAT_AMODE_A16;
1539 break;
1540 case VME_A24:
1541 *attr |= TSI148_LCSR_DSAT_AMODE_A24;
1542 break;
1543 case VME_A32:
1544 *attr |= TSI148_LCSR_DSAT_AMODE_A32;
1545 break;
1546 case VME_A64:
1547 *attr |= TSI148_LCSR_DSAT_AMODE_A64;
1548 break;
1549 case VME_CRCSR:
1550 *attr |= TSI148_LCSR_DSAT_AMODE_CRCSR;
1551 break;
1552 case VME_USER1:
1553 *attr |= TSI148_LCSR_DSAT_AMODE_USER1;
1554 break;
1555 case VME_USER2:
1556 *attr |= TSI148_LCSR_DSAT_AMODE_USER2;
1557 break;
1558 case VME_USER3:
1559 *attr |= TSI148_LCSR_DSAT_AMODE_USER3;
1560 break;
1561 case VME_USER4:
1562 *attr |= TSI148_LCSR_DSAT_AMODE_USER4;
1563 break;
1564 default:
1565 printk("Invalid address space\n");
1566 return -EINVAL;
1567 break;
1568 }
1569
1570 if (cycle & VME_SUPER)
1571 *attr |= TSI148_LCSR_DSAT_SUP;
1572 if (cycle & VME_PROG)
1573 *attr |= TSI148_LCSR_DSAT_PGM;
1574
1575 return 0;
1576}
1577
1578static int tsi148_dma_set_vme_dest_attributes(u32 *attr, vme_address_t aspace,
1579 vme_cycle_t cycle, vme_width_t dwidth)
1580{
1581 /* Setup 2eSST speeds */
1582 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1583 case VME_2eSST160:
1584 *attr |= TSI148_LCSR_DDAT_2eSSTM_160;
1585 break;
1586 case VME_2eSST267:
1587 *attr |= TSI148_LCSR_DDAT_2eSSTM_267;
1588 break;
1589 case VME_2eSST320:
1590 *attr |= TSI148_LCSR_DDAT_2eSSTM_320;
1591 break;
1592 }
1593
1594 /* Setup cycle types */
1595 if (cycle & VME_SCT) {
1596 *attr |= TSI148_LCSR_DDAT_TM_SCT;
1597 }
1598 if (cycle & VME_BLT) {
1599 *attr |= TSI148_LCSR_DDAT_TM_BLT;
1600 }
1601 if (cycle & VME_MBLT) {
1602 *attr |= TSI148_LCSR_DDAT_TM_MBLT;
1603 }
1604 if (cycle & VME_2eVME) {
1605 *attr |= TSI148_LCSR_DDAT_TM_2eVME;
1606 }
1607 if (cycle & VME_2eSST) {
1608 *attr |= TSI148_LCSR_DDAT_TM_2eSST;
1609 }
1610 if (cycle & VME_2eSSTB) {
1611 printk("Currently not setting Broadcast Select Registers\n");
1612 *attr |= TSI148_LCSR_DDAT_TM_2eSSTB;
1613 }
1614
1615 /* Setup data width */
1616 switch (dwidth) {
1617 case VME_D16:
1618 *attr |= TSI148_LCSR_DDAT_DBW_16;
1619 break;
1620 case VME_D32:
1621 *attr |= TSI148_LCSR_DDAT_DBW_32;
1622 break;
1623 default:
1624 printk("Invalid data width\n");
1625 return -EINVAL;
1626 }
1627
1628 /* Setup address space */
1629 switch (aspace) {
1630 case VME_A16:
1631 *attr |= TSI148_LCSR_DDAT_AMODE_A16;
1632 break;
1633 case VME_A24:
1634 *attr |= TSI148_LCSR_DDAT_AMODE_A24;
1635 break;
1636 case VME_A32:
1637 *attr |= TSI148_LCSR_DDAT_AMODE_A32;
1638 break;
1639 case VME_A64:
1640 *attr |= TSI148_LCSR_DDAT_AMODE_A64;
1641 break;
1642 case VME_CRCSR:
1643 *attr |= TSI148_LCSR_DDAT_AMODE_CRCSR;
1644 break;
1645 case VME_USER1:
1646 *attr |= TSI148_LCSR_DDAT_AMODE_USER1;
1647 break;
1648 case VME_USER2:
1649 *attr |= TSI148_LCSR_DDAT_AMODE_USER2;
1650 break;
1651 case VME_USER3:
1652 *attr |= TSI148_LCSR_DDAT_AMODE_USER3;
1653 break;
1654 case VME_USER4:
1655 *attr |= TSI148_LCSR_DDAT_AMODE_USER4;
1656 break;
1657 default:
1658 printk("Invalid address space\n");
1659 return -EINVAL;
1660 break;
1661 }
1662
1663 if (cycle & VME_SUPER)
1664 *attr |= TSI148_LCSR_DDAT_SUP;
1665 if (cycle & VME_PROG)
1666 *attr |= TSI148_LCSR_DDAT_PGM;
1667
1668 return 0;
1669}
1670
1671/*
1672 * Add a link list descriptor to the list
1673 *
1674 * XXX Need to handle 2eSST Broadcast select bits
1675 */
1676int tsi148_dma_list_add (struct vme_dma_list *list, struct vme_dma_attr *src,
1677 struct vme_dma_attr *dest, size_t count)
1678{
1679 struct tsi148_dma_entry *entry, *prev;
1680 u32 address_high, address_low;
1681 struct vme_dma_pattern *pattern_attr;
1682 struct vme_dma_pci *pci_attr;
1683 struct vme_dma_vme *vme_attr;
1684 dma_addr_t desc_ptr;
1685 int retval = 0;
1686
1687 /* XXX descriptor must be aligned on 64-bit boundaries */
1688 entry = (struct tsi148_dma_entry *)kmalloc(
1689 sizeof(struct tsi148_dma_entry), GFP_KERNEL);
1690 if (entry == NULL) {
1691 printk("Failed to allocate memory for dma resource "
1692 "structure\n");
1693 retval = -ENOMEM;
1694 goto err_mem;
1695 }
1696
1697 /* Test descriptor alignment */
1698 if ((unsigned long)&(entry->descriptor) & 0x7) {
1699 printk("Descriptor not aligned to 8 byte boundary as "
1700 "required: %p\n", &(entry->descriptor));
1701 retval = -EINVAL;
1702 goto err_align;
1703 }
1704
1705 /* Given we are going to fill out the structure, we probably don't
1706 * need to zero it, but better safe than sorry for now.
1707 */
1708 memset(&(entry->descriptor), 0, sizeof(struct tsi148_dma_descriptor));
1709
1710 /* Fill out source part */
1711 switch (src->type) {
1712 case VME_DMA_PATTERN:
1713 pattern_attr = (struct vme_dma_pattern *)src->private;
1714
1715 entry->descriptor.dsal = pattern_attr->pattern;
1716 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PAT;
1717 /* Default behaviour is 32 bit pattern */
1718 if (pattern_attr->type & VME_DMA_PATTERN_BYTE) {
1719 entry->descriptor.dsat |= TSI148_LCSR_DSAT_PSZ;
1720 }
1721 /* It seems that the default behaviour is to increment */
1722 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0) {
1723 entry->descriptor.dsat |= TSI148_LCSR_DSAT_NIN;
1724 }
1725 break;
1726 case VME_DMA_PCI:
1727 pci_attr = (struct vme_dma_pci *)src->private;
1728
1729 reg_split((unsigned long long)pci_attr->address, &address_high,
1730 &address_low);
1731 entry->descriptor.dsau = address_high;
1732 entry->descriptor.dsal = address_low;
1733 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_PCI;
1734 break;
1735 case VME_DMA_VME:
1736 vme_attr = (struct vme_dma_vme *)src->private;
1737
1738 reg_split((unsigned long long)vme_attr->address, &address_high,
1739 &address_low);
1740 entry->descriptor.dsau = address_high;
1741 entry->descriptor.dsal = address_low;
1742 entry->descriptor.dsat = TSI148_LCSR_DSAT_TYP_VME;
1743
1744 retval = tsi148_dma_set_vme_src_attributes(
1745 &(entry->descriptor.dsat), vme_attr->aspace,
1746 vme_attr->cycle, vme_attr->dwidth);
1747 if(retval < 0 )
1748 goto err_source;
1749 break;
1750 default:
1751 printk("Invalid source type\n");
1752 retval = -EINVAL;
1753 goto err_source;
1754 break;
1755 }
1756
1757 /* Assume last link - this will be over-written by adding another */
1758 entry->descriptor.dnlau = 0;
1759 entry->descriptor.dnlal = TSI148_LCSR_DNLAL_LLA;
1760
1761
1762 /* Fill out destination part */
1763 switch (dest->type) {
1764 case VME_DMA_PCI:
1765 pci_attr = (struct vme_dma_pci *)dest->private;
1766
1767 reg_split((unsigned long long)pci_attr->address, &address_high,
1768 &address_low);
1769 entry->descriptor.ddau = address_high;
1770 entry->descriptor.ddal = address_low;
1771 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_PCI;
1772 break;
1773 case VME_DMA_VME:
1774 vme_attr = (struct vme_dma_vme *)dest->private;
1775
1776 reg_split((unsigned long long)vme_attr->address, &address_high,
1777 &address_low);
1778 entry->descriptor.ddau = address_high;
1779 entry->descriptor.ddal = address_low;
1780 entry->descriptor.ddat = TSI148_LCSR_DDAT_TYP_VME;
1781
1782 retval = tsi148_dma_set_vme_dest_attributes(
1783 &(entry->descriptor.ddat), vme_attr->aspace,
1784 vme_attr->cycle, vme_attr->dwidth);
1785 if(retval < 0 )
1786 goto err_dest;
1787 break;
1788 default:
1789 printk("Invalid destination type\n");
1790 retval = -EINVAL;
1791 goto err_dest;
1792 break;
1793 }
1794
1795 /* Fill out count */
1796 entry->descriptor.dcnt = (u32)count;
1797
1798 /* Add to list */
1799 list_add_tail(&(entry->list), &(list->entries));
1800
1801 /* Fill out previous descriptors "Next Address" */
1802 if(entry->list.prev != &(list->entries)){
1803 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1804 list);
1805 /* We need the bus address for the pointer */
1806 desc_ptr = virt_to_bus(&(entry->descriptor));
1807 reg_split(desc_ptr, &(prev->descriptor.dnlau),
1808 &(prev->descriptor.dnlal));
1809 }
1810
1811 return 0;
1812
1813err_dest:
1814err_source:
1815err_align:
1816 kfree(entry);
1817err_mem:
1818 return retval;
1819}
1820
1821/*
1822 * Check to see if the provided DMA channel is busy.
1823 */
1824static int tsi148_dma_busy(int channel)
1825{
1826 u32 tmp;
1827
1828 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
1829 TSI148_LCSR_OFFSET_DSTA);
1830
1831 if (tmp & TSI148_LCSR_DSTA_BSY)
1832 return 0;
1833 else
1834 return 1;
1835
1836}
1837
1838/*
1839 * Execute a previously generated link list
1840 *
1841 * XXX Need to provide control register configuration.
1842 */
1843int tsi148_dma_list_exec(struct vme_dma_list *list)
1844{
1845 struct vme_dma_resource *ctrlr;
1846 int channel, retval = 0;
1847 struct tsi148_dma_entry *entry;
1848 dma_addr_t bus_addr;
1849 u32 bus_addr_high, bus_addr_low;
1850 u32 val, dctlreg = 0;
1851#if 0
1852 int x;
1853#endif
1854
1855 ctrlr = list->parent;
1856
400822fe 1857 mutex_lock(&(ctrlr->mtx));
d22b8ed9
MW		 1858
1859 channel = ctrlr->number;
1860
1861 if (! list_empty(&(ctrlr->running))) {
1862 /*
1863 * XXX We have an active DMA transfer and currently haven't
1864 * sorted out the mechanism for "pending" DMA transfers.
1865 * Return busy.
1866 */
1867 /* Need to add to pending here */
400822fe 1868 mutex_unlock(&(ctrlr->mtx));
d22b8ed9
MW		 1869 return -EBUSY;
1870 } else {
1871 list_add(&(list->list), &(ctrlr->running));
1872 }
1873#if 0
1874 /* XXX Still todo */
1875 for (x = 0; x < 8; x++) { /* vme block size */
1876 if ((32 << x) >= vmeDma->maxVmeBlockSize) {
1877 break;
1878 }
1879 }
1880 if (x == 8)
1881 x = 7;
1882 dctlreg |= (x << 12);
1883
1884 for (x = 0; x < 8; x++) { /* pci block size */
1885 if ((32 << x) >= vmeDma->maxPciBlockSize) {
1886 break;
1887 }
1888 }
1889 if (x == 8)
1890 x = 7;
1891 dctlreg |= (x << 4);
1892
1893 if (vmeDma->vmeBackOffTimer) {
1894 for (x = 1; x < 8; x++) { /* vme timer */
1895 if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) {
1896 break;
1897 }
1898 }
1899 if (x == 8)
1900 x = 7;
1901 dctlreg |= (x << 8);
1902 }
1903
1904 if (vmeDma->pciBackOffTimer) {
1905 for (x = 1; x < 8; x++) { /* pci timer */
1906 if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) {
1907 break;
1908 }
1909 }
1910 if (x == 8)
1911 x = 7;
1912 dctlreg |= (x << 0);
1913 }
1914#endif
1915
1916 /* Get first bus address and write into registers */
1917 entry = list_first_entry(&(list->entries), struct tsi148_dma_entry,
1918 list);
1919
1920 bus_addr = virt_to_bus(&(entry->descriptor));
1921
400822fe 1922 mutex_unlock(&(ctrlr->mtx));
d22b8ed9
MW		 1923
1924 reg_split(bus_addr, &bus_addr_high, &bus_addr_low);
1925
1926 iowrite32be(bus_addr_high, tsi148_bridge->base +
1927 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
1928 iowrite32be(bus_addr_low, tsi148_bridge->base +
1929 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1930
1931 /* Start the operation */
1932 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, tsi148_bridge->base +
1933 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1934
1935 wait_event_interruptible(dma_queue[channel], tsi148_dma_busy(channel));
1936 /*
1937 * Read status register, this register is valid until we kick off a
1938 * new transfer.
1939 */
1940 val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
1941 TSI148_LCSR_OFFSET_DSTA);
1942
1943 if (val & TSI148_LCSR_DSTA_VBE) {
1944 printk(KERN_ERR "tsi148: DMA Error. DSTA=%08X\n", val);
1945 retval = -EIO;
1946 }
1947
1948 /* Remove list from running list */
400822fe 1949 mutex_lock(&(ctrlr->mtx));
d22b8ed9 1950 list_del(&(list->list));
400822fe 1951 mutex_unlock(&(ctrlr->mtx));
d22b8ed9
MW		 1952
1953 return retval;
1954}
1955
1956/*
1957 * Clean up a previously generated link list
1958 *
1959 * We have a separate function, don't assume that the chain can't be reused.
1960 */
1961int tsi148_dma_list_empty(struct vme_dma_list *list)
1962{
1963 struct list_head *pos, *temp;
1964 struct tsi148_dma_entry *entry;
1965
1966 /* detach and free each entry */
1967 list_for_each_safe(pos, temp, &(list->entries)) {
1968 list_del(pos);
1969 entry = list_entry(pos, struct tsi148_dma_entry, list);
1970 kfree(entry);
1971 }
1972
1973 return (0);
1974}
1975
1976/*
1977 * All 4 location monitors reside at the same base - this is therefore a
1978 * system wide configuration.
1979 *
1980 * This does not enable the LM monitor - that should be done when the first
1981 * callback is attached and disabled when the last callback is removed.
1982 */
42fb5031
MW		 1983int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
1984 vme_address_t aspace, vme_cycle_t cycle)
d22b8ed9
MW		 1985{
1986 u32 lm_base_high, lm_base_low, lm_ctl = 0;
1987 int i;
1988
42fb5031 1989 mutex_lock(&(lm->mtx));
d22b8ed9
MW		 1990
1991 /* If we already have a callback attached, we can't move it! */
42fb5031 1992 for (i = 0; i < lm->monitors; i++) {
d22b8ed9 1993 if(lm_callback[i] != NULL) {
42fb5031 1994 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 1995 printk("Location monitor callback attached, can't "
1996 "reset\n");
1997 return -EBUSY;
1998 }
1999 }
2000
2001 switch (aspace) {
2002 case VME_A16:
2003 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
2004 break;
2005 case VME_A24:
2006 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
2007 break;
2008 case VME_A32:
2009 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
2010 break;
2011 case VME_A64:
2012 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
2013 break;
2014 default:
42fb5031 2015 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2016 printk("Invalid address space\n");
2017 return -EINVAL;
2018 break;
2019 }
2020
2021 if (cycle & VME_SUPER)
2022 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
2023 if (cycle & VME_USER)
2024 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
2025 if (cycle & VME_PROG)
2026 lm_ctl |= TSI148_LCSR_LMAT_PGM;
2027 if (cycle & VME_DATA)
2028 lm_ctl |= TSI148_LCSR_LMAT_DATA;
2029
2030 reg_split(lm_base, &lm_base_high, &lm_base_low);
2031
2032 iowrite32be(lm_base_high, tsi148_bridge->base + TSI148_LCSR_LMBAU);
2033 iowrite32be(lm_base_low, tsi148_bridge->base + TSI148_LCSR_LMBAL);
2034 iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT);
2035
42fb5031 2036 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2037
2038 return 0;
2039}
2040
2041/* Get configuration of the callback monitor and return whether it is enabled
2042 * or disabled.
2043 */
42fb5031
MW		 2044int tsi148_lm_get(struct vme_lm_resource *lm, unsigned long long *lm_base,
2045 vme_address_t *aspace, vme_cycle_t *cycle)
d22b8ed9
MW		 2046{
2047 u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
2048
42fb5031 2049 mutex_lock(&(lm->mtx));
d22b8ed9
MW		 2050
2051 lm_base_high = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAU);
2052 lm_base_low = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMBAL);
2053 lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2054
2055 reg_join(lm_base_high, lm_base_low, lm_base);
2056
2057 if (lm_ctl & TSI148_LCSR_LMAT_EN)
2058 enabled = 1;
2059
2060 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16) {
2061 *aspace |= VME_A16;
2062 }
2063 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24) {
2064 *aspace |= VME_A24;
2065 }
2066 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32) {
2067 *aspace |= VME_A32;
2068 }
2069 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64) {
2070 *aspace |= VME_A64;
2071 }
2072
2073 if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
2074 *cycle |= VME_SUPER;
2075 if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
2076 *cycle |= VME_USER;
2077 if (lm_ctl & TSI148_LCSR_LMAT_PGM)
2078 *cycle |= VME_PROG;
2079 if (lm_ctl & TSI148_LCSR_LMAT_DATA)
2080 *cycle |= VME_DATA;
2081
42fb5031 2082 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2083
2084 return enabled;
2085}
2086
2087/*
2088 * Attach a callback to a specific location monitor.
2089 *
2090 * Callback will be passed the monitor triggered.
2091 */
42fb5031
MW		 2092int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
2093 void (*callback)(int))
d22b8ed9
MW		 2094{
2095 u32 lm_ctl, tmp;
2096
42fb5031 2097 mutex_lock(&(lm->mtx));
d22b8ed9
MW		 2098
2099 /* Ensure that the location monitor is configured - need PGM or DATA */
2100 lm_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2101 if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
42fb5031 2102 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2103 printk("Location monitor not properly configured\n");
2104 return -EINVAL;
2105 }
2106
2107 /* Check that a callback isn't already attached */
2108 if (lm_callback[monitor] != NULL) {
42fb5031 2109 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2110 printk("Existing callback attached\n");
2111 return -EBUSY;
2112 }
2113
2114 /* Attach callback */
2115 lm_callback[monitor] = callback;
2116
2117 /* Enable Location Monitor interrupt */
2118 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
2119 tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
2120 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEN);
2121
2122 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
2123 tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
2124 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
2125
2126 /* Ensure that global Location Monitor Enable set */
2127 if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2128 lm_ctl |= TSI148_LCSR_LMAT_EN;
2129 iowrite32be(lm_ctl, tsi148_bridge->base + TSI148_LCSR_LMAT);
2130 }
2131
42fb5031 2132 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2133
2134 return 0;
2135}
2136
2137/*
2138 * Detach a callback function forn a specific location monitor.
2139 */
42fb5031 2140int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
d22b8ed9
MW		 2141{
2142 u32 lm_en, tmp;
2143
42fb5031 2144 mutex_lock(&(lm->mtx));
d22b8ed9
MW		 2145
2146 /* Disable Location Monitor and ensure previous interrupts are clear */
2147 lm_en = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEN);
2148 lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
2149 iowrite32be(lm_en, tsi148_bridge->base + TSI148_LCSR_INTEN);
2150
2151 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_INTEO);
2152 tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
2153 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_INTEO);
2154
2155 iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
2156 tsi148_bridge->base + TSI148_LCSR_INTEO);
2157
2158 /* Detach callback */
2159 lm_callback[monitor] = NULL;
2160
2161 /* If all location monitors disabled, disable global Location Monitor */
2162 if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2163 TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
2164 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_LMAT);
2165 tmp &= ~TSI148_LCSR_LMAT_EN;
2166 iowrite32be(tmp, tsi148_bridge->base + TSI148_LCSR_LMAT);
2167 }
2168
42fb5031 2169 mutex_unlock(&(lm->mtx));
d22b8ed9
MW		 2170
2171 return 0;
2172}
2173
2174/*
2175 * Determine Geographical Addressing
2176 */
2177int tsi148_slot_get(void)
2178{
2179 u32 slot = 0;
2180
2181 slot = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2182 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2183 return (int)slot;
2184}
2185
2186static int __init tsi148_init(void)
2187{
2188 return pci_register_driver(&tsi148_driver);
2189}
2190
2191/*
2192 * Configure CR/CSR space
2193 *
2194 * Access to the CR/CSR can be configured at power-up. The location of the
2195 * CR/CSR registers in the CR/CSR address space is determined by the boards
2196 * Auto-ID or Geographic address. This function ensures that the window is
2197 * enabled at an offset consistent with the boards geopgraphic address.
2198 *
2199 * Each board has a 512kB window, with the highest 4kB being used for the
2200 * boards registers, this means there is a fix length 508kB window which must
2201 * be mapped onto PCI memory.
2202 */
2203static int tsi148_crcsr_init(struct pci_dev *pdev)
2204{
2205 u32 cbar, crat, vstat;
2206 u32 crcsr_bus_high, crcsr_bus_low;
2207 int retval;
2208
2209 /* Allocate mem for CR/CSR image */
2210 crcsr_kernel = pci_alloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2211 &crcsr_bus);
2212 if (crcsr_kernel == NULL) {
2213 dev_err(&pdev->dev, "Failed to allocate memory for CR/CSR "
2214 "image\n");
2215 return -ENOMEM;
2216 }
2217
2218 memset(crcsr_kernel, 0, VME_CRCSR_BUF_SIZE);
2219
2220 reg_split(crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
2221
2222 iowrite32be(crcsr_bus_high, tsi148_bridge->base + TSI148_LCSR_CROU);
2223 iowrite32be(crcsr_bus_low, tsi148_bridge->base + TSI148_LCSR_CROL);
2224
2225 /* Ensure that the CR/CSR is configured at the correct offset */
2226 cbar = ioread32be(tsi148_bridge->base + TSI148_CBAR);
2227 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2228
2229 vstat = tsi148_slot_get();
2230
2231 if (cbar != vstat) {
2232 dev_info(&pdev->dev, "Setting CR/CSR offset\n");
2233 iowrite32be(cbar<<3, tsi148_bridge->base + TSI148_CBAR);
2234 }
2235 dev_info(&pdev->dev, "CR/CSR Offset: %d\n", cbar);
2236
2237 crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT);
2238 if (crat & TSI148_LCSR_CRAT_EN) {
2239 dev_info(&pdev->dev, "Enabling CR/CSR space\n");
2240 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
2241 tsi148_bridge->base + TSI148_LCSR_CRAT);
2242 } else
2243 dev_info(&pdev->dev, "CR/CSR already enabled\n");
2244
2245 /* If we want flushed, error-checked writes, set up a window
2246 * over the CR/CSR registers. We read from here to safely flush
2247 * through VME writes.
2248 */
2249 if(err_chk) {
2250 retval = tsi148_master_set(flush_image, 1, (vstat * 0x80000),
2251 0x80000, VME_CRCSR, VME_SCT, VME_D16);
2252 if (retval)
2253 dev_err(&pdev->dev, "Configuring flush image failed\n");
2254 }
2255
2256 return 0;
2257
2258}
2259
2260static void tsi148_crcsr_exit(struct pci_dev *pdev)
2261{
2262 u32 crat;
2263
2264 /* Turn off CR/CSR space */
2265 crat = ioread32be(tsi148_bridge->base + TSI148_LCSR_CRAT);
2266 iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
2267 tsi148_bridge->base + TSI148_LCSR_CRAT);
2268
2269 /* Free image */
2270 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROU);
2271 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CROL);
2272
2273 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, crcsr_kernel, crcsr_bus);
2274}
2275
2276static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2277{
2278 int retval, i, master_num;
2279 u32 data;
2280 struct list_head *pos = NULL;
2281 struct vme_master_resource *master_image;
2282 struct vme_slave_resource *slave_image;
2283 struct vme_dma_resource *dma_ctrlr;
42fb5031 2284 struct vme_lm_resource *lm;
d22b8ed9
MW		 2285
2286 /* If we want to support more than one of each bridge, we need to
2287 * dynamically generate this so we get one per device
2288 */
2289 tsi148_bridge = (struct vme_bridge *)kmalloc(sizeof(struct vme_bridge),
2290 GFP_KERNEL);
2291 if (tsi148_bridge == NULL) {
2292 dev_err(&pdev->dev, "Failed to allocate memory for device "
2293 "structure\n");
2294 retval = -ENOMEM;
2295 goto err_struct;
2296 }
2297
2298 memset(tsi148_bridge, 0, sizeof(struct vme_bridge));
2299
2300 /* Enable the device */
2301 retval = pci_enable_device(pdev);
2302 if (retval) {
2303 dev_err(&pdev->dev, "Unable to enable device\n");
2304 goto err_enable;
2305 }
2306
2307 /* Map Registers */
2308 retval = pci_request_regions(pdev, driver_name);
2309 if (retval) {
2310 dev_err(&pdev->dev, "Unable to reserve resources\n");
2311 goto err_resource;
2312 }
2313
2314 /* map registers in BAR 0 */
2315 tsi148_bridge->base = ioremap_nocache(pci_resource_start(pdev, 0), 4096);
2316 if (!tsi148_bridge->base) {
2317 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2318 retval = -EIO;
2319 goto err_remap;
2320 }
2321
2322 /* Check to see if the mapping worked out */
2323 data = ioread32(tsi148_bridge->base + TSI148_PCFS_ID) & 0x0000FFFF;
2324 if (data != PCI_VENDOR_ID_TUNDRA) {
2325 dev_err(&pdev->dev, "CRG region check failed\n");
2326 retval = -EIO;
2327 goto err_test;
2328 }
2329
2330 /* Initialize wait queues & mutual exclusion flags */
2331 /* XXX These need to be moved to the vme_bridge structure */
2332 init_waitqueue_head(&dma_queue[0]);
2333 init_waitqueue_head(&dma_queue[1]);
2334 init_waitqueue_head(&iack_queue);
400822fe
MW		 2335 mutex_init(&(vme_int));
2336 mutex_init(&(vme_irq));
2337 mutex_init(&(vme_rmw));
d22b8ed9
MW		 2338
2339 tsi148_bridge->parent = &(pdev->dev);
2340 strcpy(tsi148_bridge->name, driver_name);
2341
2342 /* Setup IRQ */
2343 retval = tsi148_irq_init(tsi148_bridge);
2344 if (retval != 0) {
2345 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2346 goto err_irq;
2347 }
2348
2349 /* If we are going to flush writes, we need to read from the VME bus.
2350 * We need to do this safely, thus we read the devices own CR/CSR
2351 * register. To do this we must set up a window in CR/CSR space and
2352 * hence have one less master window resource available.
2353 */
2354 master_num = TSI148_MAX_MASTER;
2355 if(err_chk){
2356 master_num--;
2357 /* XXX */
2358 flush_image = (struct vme_master_resource *)kmalloc(
2359 sizeof(struct vme_master_resource), GFP_KERNEL);
2360 if (flush_image == NULL) {
2361 dev_err(&pdev->dev, "Failed to allocate memory for "
2362 "flush resource structure\n");
2363 retval = -ENOMEM;
2364 goto err_master;
2365 }
2366 flush_image->parent = tsi148_bridge;
2367 spin_lock_init(&(flush_image->lock));
2368 flush_image->locked = 1;
2369 flush_image->number = master_num;
2370 flush_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2371 VME_A64;
2372 flush_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2373 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2374 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2375 VME_PROG | VME_DATA;
2376 flush_image->width_attr = VME_D16 | VME_D32;
2377 memset(&(flush_image->pci_resource), 0,
2378 sizeof(struct resource));
2379 flush_image->kern_base = NULL;
2380 }
2381
2382 /* Add master windows to list */
2383 INIT_LIST_HEAD(&(tsi148_bridge->master_resources));
2384 for (i = 0; i < master_num; i++) {
2385 master_image = (struct vme_master_resource *)kmalloc(
2386 sizeof(struct vme_master_resource), GFP_KERNEL);
2387 if (master_image == NULL) {
2388 dev_err(&pdev->dev, "Failed to allocate memory for "
2389 "master resource structure\n");
2390 retval = -ENOMEM;
2391 goto err_master;
2392 }
2393 master_image->parent = tsi148_bridge;
2394 spin_lock_init(&(master_image->lock));
2395 master_image->locked = 0;
2396 master_image->number = i;
2397 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2398 VME_A64;
2399 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2400 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2401 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2402 VME_PROG | VME_DATA;
2403 master_image->width_attr = VME_D16 | VME_D32;
2404 memset(&(master_image->pci_resource), 0,
2405 sizeof(struct resource));
2406 master_image->kern_base = NULL;
2407 list_add_tail(&(master_image->list),
2408 &(tsi148_bridge->master_resources));
2409 }
2410
2411 /* Add slave windows to list */
2412 INIT_LIST_HEAD(&(tsi148_bridge->slave_resources));
2413 for (i = 0; i < TSI148_MAX_SLAVE; i++) {
2414 slave_image = (struct vme_slave_resource *)kmalloc(
2415 sizeof(struct vme_slave_resource), GFP_KERNEL);
2416 if (slave_image == NULL) {
2417 dev_err(&pdev->dev, "Failed to allocate memory for "
2418 "slave resource structure\n");
2419 retval = -ENOMEM;
2420 goto err_slave;
2421 }
2422 slave_image->parent = tsi148_bridge;
400822fe 2423 mutex_init(&(slave_image->mtx));
d22b8ed9
MW		 2424 slave_image->locked = 0;
2425 slave_image->number = i;
2426 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
2427 VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2428 VME_USER3 | VME_USER4;
2429 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2430 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2431 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2432 VME_PROG | VME_DATA;
2433 list_add_tail(&(slave_image->list),
2434 &(tsi148_bridge->slave_resources));
2435 }
2436
2437 /* Add dma engines to list */
2438 INIT_LIST_HEAD(&(tsi148_bridge->dma_resources));
2439 for (i = 0; i < TSI148_MAX_DMA; i++) {
2440 dma_ctrlr = (struct vme_dma_resource *)kmalloc(
2441 sizeof(struct vme_dma_resource), GFP_KERNEL);
2442 if (dma_ctrlr == NULL) {
2443 dev_err(&pdev->dev, "Failed to allocate memory for "
2444 "dma resource structure\n");
2445 retval = -ENOMEM;
2446 goto err_dma;
2447 }
2448 dma_ctrlr->parent = tsi148_bridge;
400822fe 2449 mutex_init(&(dma_ctrlr->mtx));
d22b8ed9
MW		 2450 dma_ctrlr->locked = 0;
2451 dma_ctrlr->number = i;
2452 INIT_LIST_HEAD(&(dma_ctrlr->pending));
2453 INIT_LIST_HEAD(&(dma_ctrlr->running));
2454 list_add_tail(&(dma_ctrlr->list),
2455 &(tsi148_bridge->dma_resources));
2456 }
2457
42fb5031
MW		 2458 /* Add location monitor to list */
2459 INIT_LIST_HEAD(&(tsi148_bridge->lm_resources));
2460 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
2461 if (lm == NULL) {
2462 dev_err(&pdev->dev, "Failed to allocate memory for "
2463 "location monitor resource structure\n");
2464 retval = -ENOMEM;
2465 goto err_lm;
2466 }
2467 lm->parent = tsi148_bridge;
2468 mutex_init(&(lm->mtx));
2469 lm->locked = 0;
2470 lm->number = 1;
2471 lm->monitors = 4;
2472 list_add_tail(&(lm->list), &(tsi148_bridge->lm_resources));
2473
d22b8ed9
MW		 2474 tsi148_bridge->slave_get = tsi148_slave_get;
2475 tsi148_bridge->slave_set = tsi148_slave_set;
2476 tsi148_bridge->master_get = tsi148_master_get;
2477 tsi148_bridge->master_set = tsi148_master_set;
2478 tsi148_bridge->master_read = tsi148_master_read;
2479 tsi148_bridge->master_write = tsi148_master_write;
2480 tsi148_bridge->master_rmw = tsi148_master_rmw;
2481 tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2482 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2483 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
2484 tsi148_bridge->request_irq = tsi148_request_irq;
2485 tsi148_bridge->free_irq = tsi148_free_irq;
2486 tsi148_bridge->generate_irq = tsi148_generate_irq;
2487 tsi148_bridge->lm_set = tsi148_lm_set;
2488 tsi148_bridge->lm_get = tsi148_lm_get;
2489 tsi148_bridge->lm_attach = tsi148_lm_attach;
2490 tsi148_bridge->lm_detach = tsi148_lm_detach;
2491 tsi148_bridge->slot_get = tsi148_slot_get;
2492
2493 data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2494 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
2495 (data & TSI148_LCSR_VSTAT_SCONS)? "" : " not");
2496 dev_info(&pdev->dev, "VME geographical address is %d\n",
2497 data & TSI148_LCSR_VSTAT_GA_M);
2498 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2499 err_chk ? "enabled" : "disabled");
2500
2501 if(tsi148_crcsr_init(pdev)) {
2502 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2503 goto err_crcsr;
2504
2505 }
2506
2507 /* Need to save tsi148_bridge pointer locally in link list for use in
2508 * tsi148_remove()
2509 */
2510 retval = vme_register_bridge(tsi148_bridge);
2511 if (retval != 0) {
2512 dev_err(&pdev->dev, "Chip Registration failed.\n");
2513 goto err_reg;
2514 }
2515
2516 /* Clear VME bus "board fail", and "power-up reset" lines */
2517 data = ioread32be(tsi148_bridge->base + TSI148_LCSR_VSTAT);
2518 data &= ~TSI148_LCSR_VSTAT_BRDFL;
2519 data |= TSI148_LCSR_VSTAT_CPURST;
2520 iowrite32be(data, tsi148_bridge->base + TSI148_LCSR_VSTAT);
2521
2522 return 0;
2523
2524 vme_unregister_bridge(tsi148_bridge);
2525err_reg:
2526 tsi148_crcsr_exit(pdev);
2527err_crcsr:
42fb5031
MW		 2528err_lm:
2529 /* resources are stored in link list */
2530 list_for_each(pos, &(tsi148_bridge->lm_resources)) {
2531 lm = list_entry(pos, struct vme_lm_resource, list);
2532 list_del(pos);
2533 kfree(lm);
2534 }
d22b8ed9
MW		 2535err_dma:
2536 /* resources are stored in link list */
2537 list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2538 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2539 list_del(pos);
2540 kfree(dma_ctrlr);
2541 }
2542err_slave:
2543 /* resources are stored in link list */
2544 list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2545 slave_image = list_entry(pos, struct vme_slave_resource, list);
2546 list_del(pos);
2547 kfree(slave_image);
2548 }
2549err_master:
2550 /* resources are stored in link list */
2551 list_for_each(pos, &(tsi148_bridge->master_resources)) {
2552 master_image = list_entry(pos, struct vme_master_resource, list);
2553 list_del(pos);
2554 kfree(master_image);
2555 }
2556
2557 tsi148_irq_exit(pdev);
2558err_irq:
2559err_test:
2560 iounmap(tsi148_bridge->base);
2561err_remap:
2562 pci_release_regions(pdev);
2563err_resource:
2564 pci_disable_device(pdev);
2565err_enable:
2566 kfree(tsi148_bridge);
2567err_struct:
2568 return retval;
2569
2570}
2571
2572static void tsi148_remove(struct pci_dev *pdev)
2573{
2574 struct list_head *pos = NULL;
2575 struct vme_master_resource *master_image;
2576 struct vme_slave_resource *slave_image;
2577 struct vme_dma_resource *dma_ctrlr;
2578 int i;
2579
2580 dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
2581
2582 /* XXX We need to find the pdev->dev in the list of vme_bridge->dev's */
2583
2584 /*
2585 * Shutdown all inbound and outbound windows.
2586 */
2587 for (i = 0; i < 8; i++) {
2588 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_IT[i] +
2589 TSI148_LCSR_OFFSET_ITAT);
2590 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_OT[i] +
2591 TSI148_LCSR_OFFSET_OTAT);
2592 }
2593
2594 /*
2595 * Shutdown Location monitor.
2596 */
2597 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_LMAT);
2598
2599 /*
2600 * Shutdown CRG map.
2601 */
2602 iowrite32be(0, tsi148_bridge->base + TSI148_LCSR_CSRAT);
2603
2604 /*
2605 * Clear error status.
2606 */
2607 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_EDPAT);
2608 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_VEAT);
2609 iowrite32be(0x07000700, tsi148_bridge->base + TSI148_LCSR_PSTAT);
2610
2611 /*
2612 * Remove VIRQ interrupt (if any)
2613 */
2614 if (ioread32be(tsi148_bridge->base + TSI148_LCSR_VICR) & 0x800) {
2615 iowrite32be(0x8000, tsi148_bridge->base + TSI148_LCSR_VICR);
2616 }
2617
2618 /*
2619 * Disable and clear all interrupts.
2620 */
2621 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTEO);
2622 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTC);
2623 iowrite32be(0xFFFFFFFF, tsi148_bridge->base + TSI148_LCSR_INTEN);
2624
2625 /*
2626 * Map all Interrupts to PCI INTA
2627 */
2628 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM1);
2629 iowrite32be(0x0, tsi148_bridge->base + TSI148_LCSR_INTM2);
2630
2631 tsi148_irq_exit(pdev);
2632
2633 vme_unregister_bridge(tsi148_bridge);
2634
2635 tsi148_crcsr_exit(pdev);
2636
2637 /* resources are stored in link list */
2638 list_for_each(pos, &(tsi148_bridge->dma_resources)) {
2639 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2640 list_del(pos);
2641 kfree(dma_ctrlr);
2642 }
2643
2644 /* resources are stored in link list */
2645 list_for_each(pos, &(tsi148_bridge->slave_resources)) {
2646 slave_image = list_entry(pos, struct vme_slave_resource, list);
2647 list_del(pos);
2648 kfree(slave_image);
2649 }
2650
2651 /* resources are stored in link list */
2652 list_for_each(pos, &(tsi148_bridge->master_resources)) {
2653 master_image = list_entry(pos, struct vme_master_resource, list);
2654 list_del(pos);
2655 kfree(master_image);
2656 }
2657
2658 tsi148_irq_exit(pdev);
2659
2660 iounmap(tsi148_bridge->base);
2661
2662 pci_release_regions(pdev);
2663
2664 pci_disable_device(pdev);
2665
2666 kfree(tsi148_bridge);
2667}
2668
2669static void __exit tsi148_exit(void)
2670{
2671 pci_unregister_driver(&tsi148_driver);
2672
2673 printk(KERN_DEBUG "Driver removed.\n");
2674}
2675
2676MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2677module_param(err_chk, bool, 0);
2678
2679MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2680MODULE_LICENSE("GPL");
2681
2682module_init(tsi148_init);
2683module_exit(tsi148_exit);
2684
2685/*----------------------------------------------------------------------------
2686 * STAGING
2687 *--------------------------------------------------------------------------*/
2688
2689#if 0
2690/*
2691 * Direct Mode DMA transfer
2692 *
2693 * XXX Not looking at direct mode for now, we can always use link list mode
2694 * with a single entry.
2695 */
2696int tsi148_dma_run(struct vme_dma_resource *resource, struct vme_dma_attr src,
2697 struct vme_dma_attr dest, size_t count)
2698{
2699 u32 dctlreg = 0;
2700 unsigned int tmp;
2701 int val;
2702 int channel, x;
2703 struct vmeDmaPacket *cur_dma;
2704 struct tsi148_dma_descriptor *dmaLL;
2705
2706 /* direct mode */
2707 dctlreg = 0x800000;
2708
2709 for (x = 0; x < 8; x++) { /* vme block size */
2710 if ((32 << x) >= vmeDma->maxVmeBlockSize) {
2711 break;
2712 }
2713 }
2714 if (x == 8)
2715 x = 7;
2716 dctlreg |= (x << 12);
2717
2718 for (x = 0; x < 8; x++) { /* pci block size */
2719 if ((32 << x) >= vmeDma->maxPciBlockSize) {
2720 break;
2721 }
2722 }
2723 if (x == 8)
2724 x = 7;
2725 dctlreg |= (x << 4);
2726
2727 if (vmeDma->vmeBackOffTimer) {
2728 for (x = 1; x < 8; x++) { /* vme timer */
2729 if ((1 << (x - 1)) >= vmeDma->vmeBackOffTimer) {
2730 break;
2731 }
2732 }
2733 if (x == 8)
2734 x = 7;
2735 dctlreg |= (x << 8);
2736 }
2737
2738 if (vmeDma->pciBackOffTimer) {
2739 for (x = 1; x < 8; x++) { /* pci timer */
2740 if ((1 << (x - 1)) >= vmeDma->pciBackOffTimer) {
2741 break;
2742 }
2743 }
2744 if (x == 8)
2745 x = 7;
2746 dctlreg |= (x << 0);
2747 }
2748
2749 /* Program registers for DMA transfer */
2750 iowrite32be(dmaLL->dsau, tsi148_bridge->base +
2751 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAU);
2752 iowrite32be(dmaLL->dsal, tsi148_bridge->base +
2753 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAL);
2754 iowrite32be(dmaLL->ddau, tsi148_bridge->base +
2755 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAU);
2756 iowrite32be(dmaLL->ddal, tsi148_bridge->base +
2757 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAL);
2758 iowrite32be(dmaLL->dsat, tsi148_bridge->base +
2759 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DSAT);
2760 iowrite32be(dmaLL->ddat, tsi148_bridge->base +
2761 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDAT);
2762 iowrite32be(dmaLL->dcnt, tsi148_bridge->base +
2763 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCNT);
2764 iowrite32be(dmaLL->ddbs, tsi148_bridge->base +
2765 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DDBS);
2766
2767 /* Start the operation */
2768 iowrite32be(dctlreg | 0x2000000, tsi148_bridge->base +
2769 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
2770
2771 tmp = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
2772 TSI148_LCSR_OFFSET_DSTA);
2773 wait_event_interruptible(dma_queue[channel], (tmp & 0x1000000) == 0);
2774
2775 /*
2776 * Read status register, we should probably do this in some error
2777 * handler rather than here so that we can be sure we haven't kicked off
2778 * another DMA transfer.
2779 */
2780 val = ioread32be(tsi148_bridge->base + TSI148_LCSR_DMA[channel] +
2781 TSI148_LCSR_OFFSET_DSTA);
2782
2783 vmeDma->vmeDmaStatus = 0;
2784 if (val & 0x10000000) {
2785 printk(KERN_ERR
2786 "DMA Error in DMA_tempe_irqhandler DSTA=%08X\n",
2787 val);
2788 vmeDma->vmeDmaStatus = val;
2789
2790 }
2791 return (0);
2792}
2793#endif
2794
2795#if 0
2796
2797/* Global VME controller information */
2798struct pci_dev *vme_pci_dev;
2799
2800/*
2801 * Set the VME bus arbiter with the requested attributes
2802 */
2803int tempe_set_arbiter(vmeArbiterCfg_t * vmeArb)
2804{
2805 int temp_ctl = 0;
2806 int gto = 0;
2807
2808 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL);
2809 temp_ctl &= 0xFFEFFF00;
2810
2811 if (vmeArb->globalTimeoutTimer == 0xFFFFFFFF) {
2812 gto = 8;
2813 } else if (vmeArb->globalTimeoutTimer > 2048) {
2814 return (-EINVAL);
2815 } else if (vmeArb->globalTimeoutTimer == 0) {
2816 gto = 0;
2817 } else {
2818 gto = 1;
2819 while ((16 * (1 << (gto - 1))) < vmeArb->globalTimeoutTimer) {
2820 gto += 1;
2821 }
2822 }
2823 temp_ctl |= gto;
2824
2825 if (vmeArb->arbiterMode != VME_PRIORITY_MODE) {
2826 temp_ctl |= 1 << 6;
2827 }
2828
2829 if (vmeArb->arbiterTimeoutFlag) {
2830 temp_ctl |= 1 << 7;
2831 }
2832
2833 if (vmeArb->noEarlyReleaseFlag) {
2834 temp_ctl |= 1 << 20;
2835 }
2836 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VCTRL);
2837
2838 return (0);
2839}
2840
2841/*
2842 * Return the attributes of the VME bus arbiter.
2843 */
2844int tempe_get_arbiter(vmeArbiterCfg_t * vmeArb)
2845{
2846 int temp_ctl = 0;
2847 int gto = 0;
2848
2849
2850 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VCTRL);
2851
2852 gto = temp_ctl & 0xF;
2853 if (gto != 0) {
2854 vmeArb->globalTimeoutTimer = (16 * (1 << (gto - 1)));
2855 }
2856
2857 if (temp_ctl & (1 << 6)) {
2858 vmeArb->arbiterMode = VME_R_ROBIN_MODE;
2859 } else {
2860 vmeArb->arbiterMode = VME_PRIORITY_MODE;
2861 }
2862
2863 if (temp_ctl & (1 << 7)) {
2864 vmeArb->arbiterTimeoutFlag = 1;
2865 }
2866
2867 if (temp_ctl & (1 << 20)) {
2868 vmeArb->noEarlyReleaseFlag = 1;
2869 }
2870
2871 return (0);
2872}
2873
2874/*
2875 * Set the VME bus requestor with the requested attributes
2876 */
2877int tempe_set_requestor(vmeRequesterCfg_t * vmeReq)
2878{
2879 int temp_ctl = 0;
2880
2881 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2882 temp_ctl &= 0xFFFF0000;
2883
2884 if (vmeReq->releaseMode == 1) {
2885 temp_ctl |= (1 << 3);
2886 }
2887
2888 if (vmeReq->fairMode == 1) {
2889 temp_ctl |= (1 << 2);
2890 }
2891
2892 temp_ctl |= (vmeReq->timeonTimeoutTimer & 7) << 8;
2893 temp_ctl |= (vmeReq->timeoffTimeoutTimer & 7) << 12;
2894 temp_ctl |= vmeReq->requestLevel;
2895
2896 iowrite32be(temp_ctl, tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2897 return (0);
2898}
2899
2900/*
2901 * Return the attributes of the VME bus requestor
2902 */
2903int tempe_get_requestor(vmeRequesterCfg_t * vmeReq)
2904{
2905 int temp_ctl = 0;
2906
2907 temp_ctl = ioread32be(tsi148_bridge->base + TSI148_LCSR_VMCTRL);
2908
2909 if (temp_ctl & 0x18) {
2910 vmeReq->releaseMode = 1;
2911 }
2912
2913 if (temp_ctl & (1 << 2)) {
2914 vmeReq->fairMode = 1;
2915 }
2916
2917 vmeReq->requestLevel = temp_ctl & 3;
2918 vmeReq->timeonTimeoutTimer = (temp_ctl >> 8) & 7;
2919 vmeReq->timeoffTimeoutTimer = (temp_ctl >> 12) & 7;
2920
2921 return (0);
2922}
2923
2924
2925#endif
Ubuntu Eoan Linux kernel mirror