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Commit | Line | Data |
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c5c77ba1 JK |
1 | /* ////////////////////////////////////////////////////////////////////////// */ |
2 | /* */ | |
3 | /* Copyright (c) Atmel Corporation. All rights reserved. */ | |
4 | /* */ | |
5 | /* Module Name: wilc_wlan.c */ | |
6 | /* */ | |
7 | /* */ | |
8 | /* //////////////////////////////////////////////////////////////////////////// */ | |
9 | ||
10 | #include "wilc_wlan_if.h" | |
60bd1003 | 11 | #include "wilc_wfi_netdevice.h" |
17e8f165 | 12 | #include "wilc_wlan_cfg.h" |
c5c77ba1 JK |
13 | |
14 | /******************************************** | |
15 | * | |
16 | * Global | |
17 | * | |
18 | ********************************************/ | |
c5c77ba1 JK |
19 | extern wilc_hif_func_t hif_sdio; |
20 | extern wilc_hif_func_t hif_spi; | |
fbc2fe16 | 21 | u32 wilc_get_chipid(u8 update); |
c5c77ba1 | 22 | |
c5c77ba1 JK |
23 | |
24 | ||
25 | typedef struct { | |
26 | int quit; | |
27 | ||
28 | /** | |
29 | * input interface functions | |
30 | **/ | |
c5c77ba1 | 31 | wilc_wlan_io_func_t io_func; |
c5c77ba1 JK |
32 | |
33 | /** | |
34 | * host interface functions | |
35 | **/ | |
36 | wilc_hif_func_t hif_func; | |
c5c77ba1 JK |
37 | |
38 | /** | |
39 | * configuration interface functions | |
40 | **/ | |
c5c77ba1 JK |
41 | int cfg_frame_in_use; |
42 | wilc_cfg_frame_t cfg_frame; | |
fbc2fe16 | 43 | u32 cfg_frame_offset; |
c5c77ba1 | 44 | int cfg_seq_no; |
c5c77ba1 JK |
45 | |
46 | /** | |
47 | * RX buffer | |
48 | **/ | |
49 | #ifdef MEMORY_STATIC | |
51e825f7 | 50 | u8 *rx_buffer; |
fbc2fe16 | 51 | u32 rx_buffer_offset; |
c5c77ba1 JK |
52 | #endif |
53 | /** | |
54 | * TX buffer | |
55 | **/ | |
51e825f7 | 56 | u8 *tx_buffer; |
fbc2fe16 | 57 | u32 tx_buffer_offset; |
c5c77ba1 JK |
58 | |
59 | /** | |
60 | * TX queue | |
61 | **/ | |
c5c77ba1 | 62 | |
c5c77ba1 JK |
63 | unsigned long txq_spinlock_flags; |
64 | ||
65 | struct txq_entry_t *txq_head; | |
66 | struct txq_entry_t *txq_tail; | |
67 | int txq_entries; | |
c5c77ba1 JK |
68 | int txq_exit; |
69 | ||
70 | /** | |
71 | * RX queue | |
72 | **/ | |
c5c77ba1 JK |
73 | struct rxq_entry_t *rxq_head; |
74 | struct rxq_entry_t *rxq_tail; | |
75 | int rxq_entries; | |
c5c77ba1 JK |
76 | int rxq_exit; |
77 | ||
78 | ||
79 | } wilc_wlan_dev_t; | |
80 | ||
81 | static wilc_wlan_dev_t g_wlan; | |
82 | ||
9af382bc CL |
83 | static inline void chip_allow_sleep(void); |
84 | static inline void chip_wakeup(void); | |
c5c77ba1 JK |
85 | /******************************************** |
86 | * | |
87 | * Debug | |
88 | * | |
89 | ********************************************/ | |
90 | ||
fbc2fe16 | 91 | static u32 dbgflag = N_INIT | N_ERR | N_INTR | N_TXQ | N_RXQ; |
c5c77ba1 | 92 | |
fbc2fe16 | 93 | static void wilc_debug(u32 flag, char *fmt, ...) |
c5c77ba1 JK |
94 | { |
95 | char buf[256]; | |
96 | va_list args; | |
c5c77ba1 JK |
97 | |
98 | if (flag & dbgflag) { | |
99 | va_start(args, fmt); | |
81053222 | 100 | vsprintf(buf, fmt, args); |
c5c77ba1 JK |
101 | va_end(args); |
102 | ||
ef2b784c | 103 | linux_wlan_dbg(buf); |
c5c77ba1 | 104 | } |
c5c77ba1 JK |
105 | } |
106 | ||
107 | static CHIP_PS_STATE_T genuChipPSstate = CHIP_WAKEDUP; | |
108 | ||
9af382bc | 109 | /*acquire_bus() and release_bus() are made static inline functions*/ |
c5c77ba1 JK |
110 | /*as a temporary workaround to fix a problem of receiving*/ |
111 | /*unknown interrupt from FW*/ | |
9af382bc | 112 | static inline void acquire_bus(BUS_ACQUIRE_T acquire) |
c5c77ba1 JK |
113 | { |
114 | ||
187f1ef1 | 115 | mutex_lock(&g_linux_wlan->hif_cs); |
c5c77ba1 JK |
116 | #ifndef WILC_OPTIMIZE_SLEEP_INT |
117 | if (genuChipPSstate != CHIP_WAKEDUP) | |
118 | #endif | |
119 | { | |
120 | if (acquire == ACQUIRE_AND_WAKEUP) | |
121 | chip_wakeup(); | |
122 | } | |
123 | ||
124 | } | |
9af382bc | 125 | static inline void release_bus(BUS_RELEASE_T release) |
c5c77ba1 JK |
126 | { |
127 | #ifdef WILC_OPTIMIZE_SLEEP_INT | |
128 | if (release == RELEASE_ALLOW_SLEEP) | |
129 | chip_allow_sleep(); | |
130 | #endif | |
187f1ef1 | 131 | mutex_unlock(&g_linux_wlan->hif_cs); |
c5c77ba1 JK |
132 | } |
133 | /******************************************** | |
134 | * | |
135 | * Queue | |
136 | * | |
137 | ********************************************/ | |
138 | ||
139 | static void wilc_wlan_txq_remove(struct txq_entry_t *tqe) | |
140 | { | |
141 | ||
7ee8291a | 142 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 JK |
143 | if (tqe == p->txq_head) { |
144 | ||
145 | p->txq_head = tqe->next; | |
146 | if (p->txq_head) | |
147 | p->txq_head->prev = NULL; | |
148 | ||
149 | ||
150 | } else if (tqe == p->txq_tail) { | |
151 | p->txq_tail = (tqe->prev); | |
152 | if (p->txq_tail) | |
153 | p->txq_tail->next = NULL; | |
154 | } else { | |
155 | tqe->prev->next = tqe->next; | |
156 | tqe->next->prev = tqe->prev; | |
157 | } | |
158 | p->txq_entries -= 1; | |
c5c77ba1 JK |
159 | |
160 | } | |
161 | ||
162 | static struct txq_entry_t *wilc_wlan_txq_remove_from_head(void) | |
163 | { | |
164 | struct txq_entry_t *tqe; | |
7ee8291a | 165 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 | 166 | unsigned long flags; |
8dfaafd6 | 167 | |
85e57567 | 168 | spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 | 169 | if (p->txq_head) { |
c5c77ba1 JK |
170 | tqe = p->txq_head; |
171 | p->txq_head = tqe->next; | |
39823a50 | 172 | if (p->txq_head) |
c5c77ba1 | 173 | p->txq_head->prev = NULL; |
39823a50 | 174 | |
c5c77ba1 JK |
175 | p->txq_entries -= 1; |
176 | ||
c5c77ba1 JK |
177 | |
178 | ||
c5c77ba1 JK |
179 | |
180 | } else { | |
181 | tqe = NULL; | |
182 | } | |
85e57567 | 183 | spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 JK |
184 | return tqe; |
185 | } | |
186 | ||
187 | static void wilc_wlan_txq_add_to_tail(struct txq_entry_t *tqe) | |
188 | { | |
7ee8291a | 189 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 | 190 | unsigned long flags; |
85e57567 | 191 | spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 | 192 | |
c5c77ba1 JK |
193 | if (p->txq_head == NULL) { |
194 | tqe->next = NULL; | |
195 | tqe->prev = NULL; | |
196 | p->txq_head = tqe; | |
197 | p->txq_tail = tqe; | |
c5c77ba1 JK |
198 | } else { |
199 | tqe->next = NULL; | |
200 | tqe->prev = p->txq_tail; | |
201 | p->txq_tail->next = tqe; | |
202 | p->txq_tail = tqe; | |
203 | } | |
204 | p->txq_entries += 1; | |
205 | PRINT_D(TX_DBG, "Number of entries in TxQ = %d\n", p->txq_entries); | |
c5c77ba1 | 206 | |
85e57567 | 207 | spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 JK |
208 | |
209 | /** | |
210 | * wake up TX queue | |
211 | **/ | |
212 | PRINT_D(TX_DBG, "Wake the txq_handling\n"); | |
213 | ||
5cd63633 | 214 | up(&g_linux_wlan->txq_event); |
c5c77ba1 JK |
215 | } |
216 | ||
217 | static int wilc_wlan_txq_add_to_head(struct txq_entry_t *tqe) | |
218 | { | |
7ee8291a | 219 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 | 220 | unsigned long flags; |
b002e20d GL |
221 | if (linux_wlan_lock_timeout(&g_linux_wlan->txq_add_to_head_cs, |
222 | CFG_PKTS_TIMEOUT)) | |
c5c77ba1 JK |
223 | return -1; |
224 | ||
85e57567 | 225 | spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 | 226 | |
c5c77ba1 JK |
227 | if (p->txq_head == NULL) { |
228 | tqe->next = NULL; | |
229 | tqe->prev = NULL; | |
230 | p->txq_head = tqe; | |
231 | p->txq_tail = tqe; | |
232 | } else { | |
233 | tqe->next = p->txq_head; | |
234 | tqe->prev = NULL; | |
235 | p->txq_head->prev = tqe; | |
236 | p->txq_head = tqe; | |
237 | } | |
238 | p->txq_entries += 1; | |
239 | PRINT_D(TX_DBG, "Number of entries in TxQ = %d\n", p->txq_entries); | |
c5c77ba1 | 240 | |
85e57567 | 241 | spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags); |
d5a63a86 | 242 | up(&g_linux_wlan->txq_add_to_head_cs); |
c5c77ba1 JK |
243 | |
244 | ||
245 | /** | |
246 | * wake up TX queue | |
247 | **/ | |
5cd63633 | 248 | up(&g_linux_wlan->txq_event); |
c5c77ba1 | 249 | PRINT_D(TX_DBG, "Wake up the txq_handler\n"); |
c5c77ba1 | 250 | |
c5c77ba1 JK |
251 | return 0; |
252 | ||
253 | } | |
254 | ||
fbc2fe16 | 255 | u32 Statisitcs_totalAcks = 0, Statisitcs_DroppedAcks = 0; |
c5c77ba1 JK |
256 | |
257 | #ifdef TCP_ACK_FILTER | |
258 | struct Ack_session_info; | |
eeb1c062 | 259 | struct Ack_session_info { |
fbc2fe16 CL |
260 | u32 Ack_seq_num; |
261 | u32 Bigger_Ack_num; | |
ec53adfe CL |
262 | u16 src_port; |
263 | u16 dst_port; | |
264 | u16 status; | |
eeb1c062 | 265 | }; |
c5c77ba1 JK |
266 | |
267 | typedef struct { | |
fbc2fe16 CL |
268 | u32 ack_num; |
269 | u32 Session_index; | |
c5c77ba1 | 270 | struct txq_entry_t *txqe; |
c5c77ba1 JK |
271 | } Pending_Acks_info_t /*Ack_info_t*/; |
272 | ||
273 | ||
274 | ||
275 | ||
276 | struct Ack_session_info *Free_head; | |
277 | struct Ack_session_info *Alloc_head; | |
278 | ||
c5c77ba1 JK |
279 | #define NOT_TCP_ACK (-1) |
280 | ||
281 | #define MAX_TCP_SESSION 25 | |
282 | #define MAX_PENDING_ACKS 256 | |
eeb1c062 | 283 | struct Ack_session_info Acks_keep_track_info[2 * MAX_TCP_SESSION]; |
c5c77ba1 JK |
284 | Pending_Acks_info_t Pending_Acks_info[MAX_PENDING_ACKS]; |
285 | ||
fbc2fe16 CL |
286 | u32 PendingAcks_arrBase; |
287 | u32 Opened_TCP_session; | |
288 | u32 Pending_Acks; | |
c5c77ba1 JK |
289 | |
290 | ||
291 | ||
fed16f2c | 292 | static inline int Init_TCP_tracking(void) |
c5c77ba1 JK |
293 | { |
294 | ||
c5c77ba1 JK |
295 | return 0; |
296 | ||
297 | } | |
fed16f2c | 298 | static inline int add_TCP_track_session(u32 src_prt, u32 dst_prt, u32 seq) |
c5c77ba1 JK |
299 | { |
300 | Acks_keep_track_info[Opened_TCP_session].Ack_seq_num = seq; | |
301 | Acks_keep_track_info[Opened_TCP_session].Bigger_Ack_num = 0; | |
302 | Acks_keep_track_info[Opened_TCP_session].src_port = src_prt; | |
303 | Acks_keep_track_info[Opened_TCP_session].dst_port = dst_prt; | |
304 | Opened_TCP_session++; | |
305 | ||
306 | PRINT_D(TCP_ENH, "TCP Session %d to Ack %d\n", Opened_TCP_session, seq); | |
307 | return 0; | |
308 | } | |
309 | ||
fed16f2c | 310 | static inline int Update_TCP_track_session(u32 index, u32 Ack) |
c5c77ba1 JK |
311 | { |
312 | ||
39823a50 | 313 | if (Ack > Acks_keep_track_info[index].Bigger_Ack_num) |
c5c77ba1 | 314 | Acks_keep_track_info[index].Bigger_Ack_num = Ack; |
c5c77ba1 JK |
315 | return 0; |
316 | ||
317 | } | |
fed16f2c | 318 | static inline int add_TCP_Pending_Ack(u32 Ack, u32 Session_index, struct txq_entry_t *txqe) |
c5c77ba1 JK |
319 | { |
320 | Statisitcs_totalAcks++; | |
321 | if (Pending_Acks < MAX_PENDING_ACKS) { | |
322 | Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].ack_num = Ack; | |
323 | Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].txqe = txqe; | |
324 | Pending_Acks_info[PendingAcks_arrBase + Pending_Acks].Session_index = Session_index; | |
325 | txqe->tcp_PendingAck_index = PendingAcks_arrBase + Pending_Acks; | |
326 | Pending_Acks++; | |
327 | ||
328 | } else { | |
329 | ||
330 | } | |
331 | return 0; | |
332 | } | |
fed16f2c | 333 | static inline int remove_TCP_related(void) |
c5c77ba1 | 334 | { |
7ee8291a | 335 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 | 336 | unsigned long flags; |
8dfaafd6 | 337 | |
85e57567 | 338 | spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 | 339 | |
85e57567 | 340 | spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 JK |
341 | return 0; |
342 | } | |
343 | ||
fed16f2c | 344 | static inline int tcp_process(struct txq_entry_t *tqe) |
c5c77ba1 JK |
345 | { |
346 | int ret; | |
51e825f7 CL |
347 | u8 *eth_hdr_ptr; |
348 | u8 *buffer = tqe->buffer; | |
c5c77ba1 JK |
349 | unsigned short h_proto; |
350 | int i; | |
7ee8291a | 351 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 | 352 | unsigned long flags; |
8dfaafd6 | 353 | |
85e57567 | 354 | spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 JK |
355 | |
356 | eth_hdr_ptr = &buffer[0]; | |
357 | h_proto = ntohs(*((unsigned short *)ð_hdr_ptr[12])); | |
358 | if (h_proto == 0x0800) { /* IP */ | |
51e825f7 CL |
359 | u8 *ip_hdr_ptr; |
360 | u8 protocol; | |
c5c77ba1 JK |
361 | |
362 | ip_hdr_ptr = &buffer[ETHERNET_HDR_LEN]; | |
363 | protocol = ip_hdr_ptr[9]; | |
364 | ||
365 | ||
366 | if (protocol == 0x06) { | |
51e825f7 | 367 | u8 *tcp_hdr_ptr; |
fbc2fe16 | 368 | u32 IHL, Total_Length, Data_offset; |
8dfaafd6 | 369 | |
c5c77ba1 JK |
370 | tcp_hdr_ptr = &ip_hdr_ptr[IP_HDR_LEN]; |
371 | IHL = (ip_hdr_ptr[0] & 0xf) << 2; | |
fbc2fe16 CL |
372 | Total_Length = (((u32)ip_hdr_ptr[2]) << 8) + ((u32)ip_hdr_ptr[3]); |
373 | Data_offset = (((u32)tcp_hdr_ptr[12] & 0xf0) >> 2); | |
c5c77ba1 | 374 | if (Total_Length == (IHL + Data_offset)) { /*we want to recognize the clear Acks(packet only carry Ack infos not with data) so data size must be equal zero*/ |
fbc2fe16 | 375 | u32 seq_no, Ack_no; |
8dfaafd6 | 376 | |
fbc2fe16 | 377 | seq_no = (((u32)tcp_hdr_ptr[4]) << 24) + (((u32)tcp_hdr_ptr[5]) << 16) + (((u32)tcp_hdr_ptr[6]) << 8) + ((u32)tcp_hdr_ptr[7]); |
c5c77ba1 | 378 | |
fbc2fe16 | 379 | Ack_no = (((u32)tcp_hdr_ptr[8]) << 24) + (((u32)tcp_hdr_ptr[9]) << 16) + (((u32)tcp_hdr_ptr[10]) << 8) + ((u32)tcp_hdr_ptr[11]); |
c5c77ba1 JK |
380 | |
381 | ||
382 | for (i = 0; i < Opened_TCP_session; i++) { | |
383 | if (Acks_keep_track_info[i].Ack_seq_num == seq_no) { | |
384 | Update_TCP_track_session(i, Ack_no); | |
385 | break; | |
386 | } | |
387 | } | |
39823a50 | 388 | if (i == Opened_TCP_session) |
c5c77ba1 | 389 | add_TCP_track_session(0, 0, seq_no); |
39823a50 | 390 | |
c5c77ba1 JK |
391 | add_TCP_Pending_Ack(Ack_no, i, tqe); |
392 | ||
393 | ||
394 | } | |
395 | ||
396 | } else { | |
397 | ret = 0; | |
398 | } | |
399 | } else { | |
400 | ret = 0; | |
401 | } | |
85e57567 | 402 | spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 JK |
403 | return ret; |
404 | } | |
405 | ||
406 | ||
c029e99c | 407 | static int wilc_wlan_txq_filter_dup_tcp_ack(struct net_device *dev) |
c5c77ba1 | 408 | { |
c029e99c GL |
409 | perInterface_wlan_t *nic; |
410 | struct wilc *wilc; | |
fbc2fe16 CL |
411 | u32 i = 0; |
412 | u32 Dropped = 0; | |
7ee8291a | 413 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 | 414 | |
c029e99c GL |
415 | nic = netdev_priv(dev); |
416 | wilc = nic->wilc; | |
417 | ||
418 | spin_lock_irqsave(&wilc->txq_spinlock, p->txq_spinlock_flags); | |
c5c77ba1 JK |
419 | for (i = PendingAcks_arrBase; i < (PendingAcks_arrBase + Pending_Acks); i++) { |
420 | if (Pending_Acks_info[i].ack_num < Acks_keep_track_info[Pending_Acks_info[i].Session_index].Bigger_Ack_num) { | |
421 | struct txq_entry_t *tqe; | |
8dfaafd6 | 422 | |
17aacd43 | 423 | PRINT_D(TCP_ENH, "DROP ACK: %u\n", Pending_Acks_info[i].ack_num); |
c5c77ba1 JK |
424 | tqe = Pending_Acks_info[i].txqe; |
425 | if (tqe) { | |
426 | wilc_wlan_txq_remove(tqe); | |
427 | Statisitcs_DroppedAcks++; | |
428 | tqe->status = 1; /* mark the packet send */ | |
429 | if (tqe->tx_complete_func) | |
430 | tqe->tx_complete_func(tqe->priv, tqe->status); | |
a18dd630 | 431 | kfree(tqe); |
c5c77ba1 | 432 | Dropped++; |
c5c77ba1 JK |
433 | } |
434 | } | |
435 | } | |
436 | Pending_Acks = 0; | |
437 | Opened_TCP_session = 0; | |
438 | ||
78174ada | 439 | if (PendingAcks_arrBase == 0) |
c5c77ba1 | 440 | PendingAcks_arrBase = MAX_TCP_SESSION; |
78174ada | 441 | else |
c5c77ba1 | 442 | PendingAcks_arrBase = 0; |
c5c77ba1 JK |
443 | |
444 | ||
c029e99c | 445 | spin_unlock_irqrestore(&wilc->txq_spinlock, p->txq_spinlock_flags); |
c5c77ba1 JK |
446 | |
447 | while (Dropped > 0) { | |
448 | /*consume the semaphore count of the removed packet*/ | |
c029e99c | 449 | linux_wlan_lock_timeout(&wilc->txq_event, 1); |
c5c77ba1 JK |
450 | Dropped--; |
451 | } | |
452 | ||
453 | return 1; | |
454 | } | |
455 | #endif | |
456 | ||
72ed4dc7 | 457 | bool EnableTCPAckFilter = false; |
c5c77ba1 | 458 | |
72ed4dc7 | 459 | void Enable_TCP_ACK_Filter(bool value) |
c5c77ba1 JK |
460 | { |
461 | EnableTCPAckFilter = value; | |
462 | } | |
463 | ||
72ed4dc7 | 464 | bool is_TCP_ACK_Filter_Enabled(void) |
c5c77ba1 JK |
465 | { |
466 | return EnableTCPAckFilter; | |
467 | } | |
c5c77ba1 | 468 | |
fbc2fe16 | 469 | static int wilc_wlan_txq_add_cfg_pkt(u8 *buffer, u32 buffer_size) |
c5c77ba1 | 470 | { |
7ee8291a | 471 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 JK |
472 | struct txq_entry_t *tqe; |
473 | ||
474 | PRINT_D(TX_DBG, "Adding config packet ...\n"); | |
475 | if (p->quit) { | |
476 | PRINT_D(TX_DBG, "Return due to clear function\n"); | |
6a3b94f7 | 477 | up(&g_linux_wlan->cfg_event); |
c5c77ba1 JK |
478 | return 0; |
479 | } | |
480 | ||
47c632d8 | 481 | tqe = kmalloc(sizeof(struct txq_entry_t), GFP_ATOMIC); |
c5c77ba1 JK |
482 | if (tqe == NULL) { |
483 | PRINT_ER("Failed to allocate memory\n"); | |
484 | return 0; | |
485 | } | |
486 | ||
487 | tqe->type = WILC_CFG_PKT; | |
488 | tqe->buffer = buffer; | |
489 | tqe->buffer_size = buffer_size; | |
490 | tqe->tx_complete_func = NULL; | |
491 | tqe->priv = NULL; | |
492 | #ifdef TCP_ACK_FILTER | |
493 | tqe->tcp_PendingAck_index = NOT_TCP_ACK; | |
494 | #endif | |
495 | /** | |
496 | * Configuration packet always at the front | |
497 | **/ | |
498 | PRINT_D(TX_DBG, "Adding the config packet at the Queue tail\n"); | |
499 | ||
c5c77ba1 JK |
500 | if (wilc_wlan_txq_add_to_head(tqe)) |
501 | return 0; | |
c5c77ba1 JK |
502 | return 1; |
503 | } | |
504 | ||
8fc84a6f GL |
505 | int wilc_wlan_txq_add_net_pkt(void *priv, u8 *buffer, u32 buffer_size, |
506 | wilc_tx_complete_func_t func) | |
c5c77ba1 | 507 | { |
7ee8291a | 508 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 JK |
509 | struct txq_entry_t *tqe; |
510 | ||
511 | if (p->quit) | |
512 | return 0; | |
513 | ||
47c632d8 | 514 | tqe = kmalloc(sizeof(struct txq_entry_t), GFP_ATOMIC); |
c5c77ba1 JK |
515 | |
516 | if (tqe == NULL) | |
517 | return 0; | |
518 | tqe->type = WILC_NET_PKT; | |
519 | tqe->buffer = buffer; | |
520 | tqe->buffer_size = buffer_size; | |
521 | tqe->tx_complete_func = func; | |
522 | tqe->priv = priv; | |
523 | ||
524 | PRINT_D(TX_DBG, "Adding mgmt packet at the Queue tail\n"); | |
525 | #ifdef TCP_ACK_FILTER | |
526 | tqe->tcp_PendingAck_index = NOT_TCP_ACK; | |
5a66bf20 | 527 | if (is_TCP_ACK_Filter_Enabled()) |
25a84832 | 528 | tcp_process(tqe); |
c5c77ba1 JK |
529 | #endif |
530 | wilc_wlan_txq_add_to_tail(tqe); | |
531 | /*return number of itemes in the queue*/ | |
532 | return p->txq_entries; | |
533 | } | |
fcc6ef92 | 534 | |
fbc2fe16 | 535 | int wilc_wlan_txq_add_mgmt_pkt(void *priv, u8 *buffer, u32 buffer_size, wilc_tx_complete_func_t func) |
c5c77ba1 JK |
536 | { |
537 | ||
7ee8291a | 538 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 JK |
539 | struct txq_entry_t *tqe; |
540 | ||
541 | if (p->quit) | |
542 | return 0; | |
543 | ||
47c632d8 | 544 | tqe = kmalloc(sizeof(struct txq_entry_t), GFP_KERNEL); |
c5c77ba1 JK |
545 | |
546 | if (tqe == NULL) | |
547 | return 0; | |
548 | tqe->type = WILC_MGMT_PKT; | |
549 | tqe->buffer = buffer; | |
550 | tqe->buffer_size = buffer_size; | |
551 | tqe->tx_complete_func = func; | |
552 | tqe->priv = priv; | |
553 | #ifdef TCP_ACK_FILTER | |
554 | tqe->tcp_PendingAck_index = NOT_TCP_ACK; | |
555 | #endif | |
556 | PRINT_D(TX_DBG, "Adding Network packet at the Queue tail\n"); | |
557 | wilc_wlan_txq_add_to_tail(tqe); | |
558 | return 1; | |
559 | } | |
fcc6ef92 | 560 | |
c5c77ba1 JK |
561 | static struct txq_entry_t *wilc_wlan_txq_get_first(void) |
562 | { | |
7ee8291a | 563 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 JK |
564 | struct txq_entry_t *tqe; |
565 | unsigned long flags; | |
566 | ||
85e57567 | 567 | spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 | 568 | |
c5c77ba1 JK |
569 | tqe = p->txq_head; |
570 | ||
85e57567 | 571 | spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 | 572 | |
c5c77ba1 JK |
573 | |
574 | return tqe; | |
575 | } | |
576 | ||
577 | static struct txq_entry_t *wilc_wlan_txq_get_next(struct txq_entry_t *tqe) | |
578 | { | |
c5c77ba1 | 579 | unsigned long flags; |
85e57567 | 580 | spin_lock_irqsave(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 | 581 | |
c5c77ba1 | 582 | tqe = tqe->next; |
85e57567 | 583 | spin_unlock_irqrestore(&g_linux_wlan->txq_spinlock, flags); |
c5c77ba1 | 584 | |
c5c77ba1 JK |
585 | |
586 | return tqe; | |
587 | } | |
588 | ||
d06f362c | 589 | static int wilc_wlan_rxq_add(struct wilc *wilc, struct rxq_entry_t *rqe) |
c5c77ba1 | 590 | { |
7ee8291a | 591 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 JK |
592 | |
593 | if (p->quit) | |
594 | return 0; | |
595 | ||
d06f362c | 596 | mutex_lock(&wilc->rxq_cs); |
c5c77ba1 JK |
597 | if (p->rxq_head == NULL) { |
598 | PRINT_D(RX_DBG, "Add to Queue head\n"); | |
599 | rqe->next = NULL; | |
600 | p->rxq_head = rqe; | |
601 | p->rxq_tail = rqe; | |
602 | } else { | |
603 | PRINT_D(RX_DBG, "Add to Queue tail\n"); | |
604 | p->rxq_tail->next = rqe; | |
605 | rqe->next = NULL; | |
606 | p->rxq_tail = rqe; | |
607 | } | |
608 | p->rxq_entries += 1; | |
609 | PRINT_D(RX_DBG, "Number of queue entries: %d\n", p->rxq_entries); | |
d06f362c | 610 | mutex_unlock(&wilc->rxq_cs); |
c5c77ba1 JK |
611 | return p->rxq_entries; |
612 | } | |
613 | ||
db387635 | 614 | static struct rxq_entry_t *wilc_wlan_rxq_remove(struct wilc *wilc) |
c5c77ba1 | 615 | { |
7ee8291a | 616 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 JK |
617 | |
618 | PRINT_D(RX_DBG, "Getting rxQ element\n"); | |
619 | if (p->rxq_head) { | |
620 | struct rxq_entry_t *rqe; | |
621 | ||
db387635 | 622 | mutex_lock(&wilc->rxq_cs); |
c5c77ba1 JK |
623 | rqe = p->rxq_head; |
624 | p->rxq_head = p->rxq_head->next; | |
625 | p->rxq_entries -= 1; | |
626 | PRINT_D(RX_DBG, "RXQ entries decreased\n"); | |
db387635 | 627 | mutex_unlock(&wilc->rxq_cs); |
c5c77ba1 JK |
628 | return rqe; |
629 | } | |
630 | PRINT_D(RX_DBG, "Nothing to get from Q\n"); | |
631 | return NULL; | |
632 | } | |
633 | ||
634 | ||
635 | /******************************************** | |
636 | * | |
637 | * Power Save handle functions | |
638 | * | |
639 | ********************************************/ | |
640 | ||
641 | ||
642 | ||
643 | #ifdef WILC_OPTIMIZE_SLEEP_INT | |
644 | ||
9af382bc | 645 | static inline void chip_allow_sleep(void) |
c5c77ba1 | 646 | { |
fbc2fe16 | 647 | u32 reg = 0; |
c5c77ba1 JK |
648 | |
649 | /* Clear bit 1 */ | |
650 | g_wlan.hif_func.hif_read_reg(0xf0, ®); | |
651 | ||
ffda203c | 652 | g_wlan.hif_func.hif_write_reg(0xf0, reg & ~BIT(0)); |
c5c77ba1 JK |
653 | } |
654 | ||
9af382bc | 655 | static inline void chip_wakeup(void) |
c5c77ba1 | 656 | { |
fbc2fe16 CL |
657 | u32 reg, clk_status_reg, trials = 0; |
658 | u32 sleep_time; | |
c5c77ba1 JK |
659 | |
660 | if ((g_wlan.io_func.io_type & 0x1) == HIF_SPI) { | |
661 | do { | |
662 | g_wlan.hif_func.hif_read_reg(1, ®); | |
663 | /* Set bit 1 */ | |
ffda203c | 664 | g_wlan.hif_func.hif_write_reg(1, reg | BIT(1)); |
c5c77ba1 JK |
665 | |
666 | /* Clear bit 1*/ | |
ffda203c | 667 | g_wlan.hif_func.hif_write_reg(1, reg & ~BIT(1)); |
c5c77ba1 JK |
668 | |
669 | do { | |
670 | /* Wait for the chip to stabilize*/ | |
80e29c7a | 671 | usleep_range(2 * 1000, 2 * 1000); |
c5c77ba1 JK |
672 | /* Make sure chip is awake. This is an extra step that can be removed */ |
673 | /* later to avoid the bus access overhead */ | |
39823a50 | 674 | if ((wilc_get_chipid(true) == 0)) |
c5c77ba1 | 675 | wilc_debug(N_ERR, "Couldn't read chip id. Wake up failed\n"); |
39823a50 | 676 | |
72ed4dc7 | 677 | } while ((wilc_get_chipid(true) == 0) && ((++trials % 3) == 0)); |
c5c77ba1 | 678 | |
72ed4dc7 | 679 | } while (wilc_get_chipid(true) == 0); |
c5c77ba1 JK |
680 | } else if ((g_wlan.io_func.io_type & 0x1) == HIF_SDIO) { |
681 | g_wlan.hif_func.hif_read_reg(0xf0, ®); | |
682 | do { | |
683 | /* Set bit 1 */ | |
ffda203c | 684 | g_wlan.hif_func.hif_write_reg(0xf0, reg | BIT(0)); |
c5c77ba1 JK |
685 | |
686 | /* Check the clock status */ | |
687 | g_wlan.hif_func.hif_read_reg(0xf1, &clk_status_reg); | |
688 | ||
689 | /* in case of clocks off, wait 2ms, and check it again. */ | |
690 | /* if still off, wait for another 2ms, for a total wait of 6ms. */ | |
691 | /* If still off, redo the wake up sequence */ | |
692 | while (((clk_status_reg & 0x1) == 0) && (((++trials) % 3) == 0)) { | |
693 | /* Wait for the chip to stabilize*/ | |
80e29c7a | 694 | usleep_range(2 * 1000, 2 * 1000); |
c5c77ba1 JK |
695 | |
696 | /* Make sure chip is awake. This is an extra step that can be removed */ | |
697 | /* later to avoid the bus access overhead */ | |
698 | g_wlan.hif_func.hif_read_reg(0xf1, &clk_status_reg); | |
699 | ||
39823a50 | 700 | if ((clk_status_reg & 0x1) == 0) |
c5c77ba1 | 701 | wilc_debug(N_ERR, "clocks still OFF. Wake up failed\n"); |
39823a50 | 702 | |
c5c77ba1 JK |
703 | } |
704 | /* in case of failure, Reset the wakeup bit to introduce a new edge on the next loop */ | |
705 | if ((clk_status_reg & 0x1) == 0) { | |
706 | /* Reset bit 0 */ | |
ffda203c AB |
707 | g_wlan.hif_func.hif_write_reg(0xf0, reg & |
708 | (~BIT(0))); | |
c5c77ba1 JK |
709 | } |
710 | } while ((clk_status_reg & 0x1) == 0); | |
711 | } | |
712 | ||
713 | ||
714 | if (genuChipPSstate == CHIP_SLEEPING_MANUAL) { | |
715 | g_wlan.hif_func.hif_read_reg(0x1C0C, ®); | |
ffda203c | 716 | reg &= ~BIT(0); |
c5c77ba1 JK |
717 | g_wlan.hif_func.hif_write_reg(0x1C0C, reg); |
718 | ||
72ed4dc7 | 719 | if (wilc_get_chipid(false) >= 0x1002b0) { |
c5c77ba1 | 720 | /* Enable PALDO back right after wakeup */ |
fbc2fe16 | 721 | u32 val32; |
8dfaafd6 | 722 | |
c5c77ba1 | 723 | g_wlan.hif_func.hif_read_reg(0x1e1c, &val32); |
ffda203c | 724 | val32 |= BIT(6); |
c5c77ba1 JK |
725 | g_wlan.hif_func.hif_write_reg(0x1e1c, val32); |
726 | ||
727 | g_wlan.hif_func.hif_read_reg(0x1e9c, &val32); | |
ffda203c | 728 | val32 |= BIT(6); |
c5c77ba1 JK |
729 | g_wlan.hif_func.hif_write_reg(0x1e9c, val32); |
730 | } | |
731 | } | |
732 | genuChipPSstate = CHIP_WAKEDUP; | |
733 | } | |
734 | #else | |
9af382bc | 735 | static inline void chip_wakeup(void) |
c5c77ba1 | 736 | { |
fbc2fe16 | 737 | u32 reg, trials = 0; |
8dfaafd6 | 738 | |
c5c77ba1 JK |
739 | do { |
740 | if ((g_wlan.io_func.io_type & 0x1) == HIF_SPI) { | |
741 | g_wlan.hif_func.hif_read_reg(1, ®); | |
742 | /* Make sure bit 1 is 0 before we start. */ | |
ffda203c | 743 | g_wlan.hif_func.hif_write_reg(1, reg & ~BIT(1)); |
c5c77ba1 | 744 | /* Set bit 1 */ |
ffda203c | 745 | g_wlan.hif_func.hif_write_reg(1, reg | BIT(1)); |
c5c77ba1 | 746 | /* Clear bit 1*/ |
ffda203c | 747 | g_wlan.hif_func.hif_write_reg(1, reg & ~BIT(1)); |
c5c77ba1 JK |
748 | } else if ((g_wlan.io_func.io_type & 0x1) == HIF_SDIO) { |
749 | /* Make sure bit 0 is 0 before we start. */ | |
750 | g_wlan.hif_func.hif_read_reg(0xf0, ®); | |
ffda203c | 751 | g_wlan.hif_func.hif_write_reg(0xf0, reg & ~BIT(0)); |
c5c77ba1 | 752 | /* Set bit 1 */ |
ffda203c | 753 | g_wlan.hif_func.hif_write_reg(0xf0, reg | BIT(0)); |
c5c77ba1 | 754 | /* Clear bit 1 */ |
ffda203c | 755 | g_wlan.hif_func.hif_write_reg(0xf0, reg & ~BIT(0)); |
c5c77ba1 JK |
756 | } |
757 | ||
758 | do { | |
759 | /* Wait for the chip to stabilize*/ | |
c5c77ba1 JK |
760 | mdelay(3); |
761 | ||
762 | /* Make sure chip is awake. This is an extra step that can be removed */ | |
763 | /* later to avoid the bus access overhead */ | |
39823a50 | 764 | if ((wilc_get_chipid(true) == 0)) |
c5c77ba1 | 765 | wilc_debug(N_ERR, "Couldn't read chip id. Wake up failed\n"); |
39823a50 | 766 | |
72ed4dc7 | 767 | } while ((wilc_get_chipid(true) == 0) && ((++trials % 3) == 0)); |
c5c77ba1 | 768 | |
72ed4dc7 | 769 | } while (wilc_get_chipid(true) == 0); |
c5c77ba1 JK |
770 | |
771 | if (genuChipPSstate == CHIP_SLEEPING_MANUAL) { | |
772 | g_wlan.hif_func.hif_read_reg(0x1C0C, ®); | |
ffda203c | 773 | reg &= ~BIT(0); |
c5c77ba1 JK |
774 | g_wlan.hif_func.hif_write_reg(0x1C0C, reg); |
775 | ||
72ed4dc7 | 776 | if (wilc_get_chipid(false) >= 0x1002b0) { |
c5c77ba1 | 777 | /* Enable PALDO back right after wakeup */ |
fbc2fe16 | 778 | u32 val32; |
8dfaafd6 | 779 | |
c5c77ba1 | 780 | g_wlan.hif_func.hif_read_reg(0x1e1c, &val32); |
ffda203c | 781 | val32 |= BIT(6); |
c5c77ba1 JK |
782 | g_wlan.hif_func.hif_write_reg(0x1e1c, val32); |
783 | ||
784 | g_wlan.hif_func.hif_read_reg(0x1e9c, &val32); | |
ffda203c | 785 | val32 |= BIT(6); |
c5c77ba1 JK |
786 | g_wlan.hif_func.hif_write_reg(0x1e9c, val32); |
787 | } | |
788 | } | |
789 | genuChipPSstate = CHIP_WAKEDUP; | |
790 | } | |
791 | #endif | |
4e4467fd | 792 | void chip_sleep_manually(u32 u32SleepTime) |
c5c77ba1 | 793 | { |
c5c77ba1 JK |
794 | if (genuChipPSstate != CHIP_WAKEDUP) { |
795 | /* chip is already sleeping. Do nothing */ | |
796 | return; | |
797 | } | |
798 | acquire_bus(ACQUIRE_ONLY); | |
799 | ||
800 | #ifdef WILC_OPTIMIZE_SLEEP_INT | |
801 | chip_allow_sleep(); | |
802 | #endif | |
803 | ||
804 | /* Trigger the manual sleep interrupt */ | |
805 | g_wlan.hif_func.hif_write_reg(0x10a8, 1); | |
806 | ||
807 | genuChipPSstate = CHIP_SLEEPING_MANUAL; | |
808 | release_bus(RELEASE_ONLY); | |
809 | ||
810 | } | |
811 | ||
812 | ||
813 | /******************************************** | |
814 | * | |
815 | * Tx, Rx queue handle functions | |
816 | * | |
817 | ********************************************/ | |
a1332cad | 818 | int wilc_wlan_handle_txq(struct net_device *dev, u32 *pu32TxqCount) |
c5c77ba1 JK |
819 | { |
820 | wilc_wlan_dev_t *p = (wilc_wlan_dev_t *)&g_wlan; | |
821 | int i, entries = 0; | |
fbc2fe16 CL |
822 | u32 sum; |
823 | u32 reg; | |
51e825f7 | 824 | u8 *txb = p->tx_buffer; |
fbc2fe16 | 825 | u32 offset = 0; |
c5c77ba1 JK |
826 | int vmm_sz = 0; |
827 | struct txq_entry_t *tqe; | |
828 | int ret = 0; | |
829 | int counter; | |
830 | int timeout; | |
fbc2fe16 | 831 | u32 vmm_table[WILC_VMM_TBL_SIZE]; |
a1332cad GL |
832 | perInterface_wlan_t *nic; |
833 | struct wilc *wilc; | |
834 | ||
835 | nic = netdev_priv(dev); | |
836 | wilc = nic->wilc; | |
8dfaafd6 | 837 | |
c5c77ba1 JK |
838 | p->txq_exit = 0; |
839 | do { | |
840 | if (p->quit) | |
841 | break; | |
842 | ||
a1332cad | 843 | linux_wlan_lock_timeout(&wilc->txq_add_to_head_cs, |
b002e20d | 844 | CFG_PKTS_TIMEOUT); |
c5c77ba1 | 845 | #ifdef TCP_ACK_FILTER |
c029e99c | 846 | wilc_wlan_txq_filter_dup_tcp_ack(dev); |
c5c77ba1 JK |
847 | #endif |
848 | /** | |
849 | * build the vmm list | |
850 | **/ | |
851 | PRINT_D(TX_DBG, "Getting the head of the TxQ\n"); | |
852 | tqe = wilc_wlan_txq_get_first(); | |
853 | i = 0; | |
854 | sum = 0; | |
855 | do { | |
c5c77ba1 JK |
856 | if ((tqe != NULL) && (i < (WILC_VMM_TBL_SIZE - 1)) /* reserve last entry to 0 */) { |
857 | ||
39823a50 | 858 | if (tqe->type == WILC_CFG_PKT) |
c5c77ba1 | 859 | vmm_sz = ETH_CONFIG_PKT_HDR_OFFSET; |
39823a50 AS |
860 | |
861 | else if (tqe->type == WILC_NET_PKT) | |
c5c77ba1 | 862 | vmm_sz = ETH_ETHERNET_HDR_OFFSET; |
39823a50 AS |
863 | |
864 | else | |
c5c77ba1 | 865 | vmm_sz = HOST_HDR_OFFSET; |
39823a50 | 866 | |
c5c77ba1 JK |
867 | vmm_sz += tqe->buffer_size; |
868 | PRINT_D(TX_DBG, "VMM Size before alignment = %d\n", vmm_sz); | |
869 | if (vmm_sz & 0x3) { /* has to be word aligned */ | |
870 | vmm_sz = (vmm_sz + 4) & ~0x3; | |
871 | } | |
39823a50 | 872 | if ((sum + vmm_sz) > LINUX_TX_SIZE) |
c5c77ba1 | 873 | break; |
39823a50 | 874 | |
c5c77ba1 JK |
875 | PRINT_D(TX_DBG, "VMM Size AFTER alignment = %d\n", vmm_sz); |
876 | vmm_table[i] = vmm_sz / 4; /* table take the word size */ | |
877 | PRINT_D(TX_DBG, "VMMTable entry size = %d\n", vmm_table[i]); | |
878 | ||
879 | if (tqe->type == WILC_CFG_PKT) { | |
ffda203c | 880 | vmm_table[i] |= BIT(10); |
c5c77ba1 JK |
881 | PRINT_D(TX_DBG, "VMMTable entry changed for CFG packet = %d\n", vmm_table[i]); |
882 | } | |
883 | #ifdef BIG_ENDIAN | |
884 | vmm_table[i] = BYTE_SWAP(vmm_table[i]); | |
885 | #endif | |
c5c77ba1 | 886 | |
c5c77ba1 JK |
887 | i++; |
888 | sum += vmm_sz; | |
889 | PRINT_D(TX_DBG, "sum = %d\n", sum); | |
890 | tqe = wilc_wlan_txq_get_next(tqe); | |
891 | } else { | |
892 | break; | |
893 | } | |
894 | } while (1); | |
895 | ||
896 | if (i == 0) { /* nothing in the queue */ | |
897 | PRINT_D(TX_DBG, "Nothing in TX-Q\n"); | |
898 | break; | |
899 | } else { | |
900 | PRINT_D(TX_DBG, "Mark the last entry in VMM table - number of previous entries = %d\n", i); | |
901 | vmm_table[i] = 0x0; /* mark the last element to 0 */ | |
902 | } | |
903 | acquire_bus(ACQUIRE_AND_WAKEUP); | |
904 | counter = 0; | |
905 | do { | |
906 | ||
907 | ret = p->hif_func.hif_read_reg(WILC_HOST_TX_CTRL, ®); | |
908 | if (!ret) { | |
909 | wilc_debug(N_ERR, "[wilc txq]: fail can't read reg vmm_tbl_entry..\n"); | |
910 | break; | |
911 | } | |
912 | ||
913 | if ((reg & 0x1) == 0) { | |
914 | /** | |
915 | * write to vmm table | |
916 | **/ | |
917 | PRINT_D(TX_DBG, "Writing VMM table ... with Size = %d\n", ((i + 1) * 4)); | |
918 | break; | |
919 | } else { | |
920 | counter++; | |
921 | if (counter > 200) { | |
922 | counter = 0; | |
923 | PRINT_D(TX_DBG, "Looping in tx ctrl , forcce quit\n"); | |
924 | ret = p->hif_func.hif_write_reg(WILC_HOST_TX_CTRL, 0); | |
925 | break; | |
926 | } | |
927 | /** | |
928 | * wait for vmm table is ready | |
929 | **/ | |
17aacd43 | 930 | PRINT_WRN(GENERIC_DBG, "[wilc txq]: warn, vmm table not clear yet, wait...\n"); |
c5c77ba1 | 931 | release_bus(RELEASE_ALLOW_SLEEP); |
2b922cbe | 932 | usleep_range(3000, 3000); |
c5c77ba1 JK |
933 | acquire_bus(ACQUIRE_AND_WAKEUP); |
934 | } | |
935 | } while (!p->quit); | |
936 | ||
39823a50 | 937 | if (!ret) |
c5c77ba1 | 938 | goto _end_; |
c5c77ba1 JK |
939 | |
940 | timeout = 200; | |
941 | do { | |
942 | ||
943 | /** | |
944 | * write to vmm table | |
945 | **/ | |
c3ca6372 | 946 | ret = p->hif_func.hif_block_tx(WILC_VMM_TBL_RX_SHADOW_BASE, (u8 *)vmm_table, ((i + 1) * 4)); |
c5c77ba1 JK |
947 | if (!ret) { |
948 | wilc_debug(N_ERR, "ERR block TX of VMM table.\n"); | |
949 | break; | |
950 | } | |
951 | ||
952 | ||
953 | /** | |
954 | * interrupt firmware | |
955 | **/ | |
956 | ret = p->hif_func.hif_write_reg(WILC_HOST_VMM_CTL, 0x2); | |
957 | if (!ret) { | |
958 | wilc_debug(N_ERR, "[wilc txq]: fail can't write reg host_vmm_ctl..\n"); | |
959 | break; | |
960 | } | |
961 | ||
962 | /** | |
963 | * wait for confirm... | |
964 | **/ | |
965 | ||
966 | do { | |
967 | ret = p->hif_func.hif_read_reg(WILC_HOST_VMM_CTL, ®); | |
968 | if (!ret) { | |
969 | wilc_debug(N_ERR, "[wilc txq]: fail can't read reg host_vmm_ctl..\n"); | |
970 | break; | |
971 | } | |
972 | if ((reg >> 2) & 0x1) { | |
973 | /** | |
974 | * Get the entries | |
975 | **/ | |
976 | entries = ((reg >> 3) & 0x3f); | |
c5c77ba1 JK |
977 | break; |
978 | } else { | |
979 | release_bus(RELEASE_ALLOW_SLEEP); | |
2b922cbe | 980 | usleep_range(3000, 3000); |
c5c77ba1 JK |
981 | acquire_bus(ACQUIRE_AND_WAKEUP); |
982 | PRINT_WRN(GENERIC_DBG, "Can't get VMM entery - reg = %2x\n", reg); | |
983 | } | |
984 | } while (--timeout); | |
985 | if (timeout <= 0) { | |
986 | ret = p->hif_func.hif_write_reg(WILC_HOST_VMM_CTL, 0x0); | |
987 | break; | |
988 | } | |
989 | ||
39823a50 | 990 | if (!ret) |
c5c77ba1 | 991 | break; |
c5c77ba1 JK |
992 | |
993 | if (entries == 0) { | |
17aacd43 | 994 | PRINT_WRN(GENERIC_DBG, "[wilc txq]: no more buffer in the chip (reg: %08x), retry later [[ %d, %x ]]\n", reg, i, vmm_table[i - 1]); |
c5c77ba1 JK |
995 | |
996 | /* undo the transaction. */ | |
997 | ret = p->hif_func.hif_read_reg(WILC_HOST_TX_CTRL, ®); | |
998 | if (!ret) { | |
999 | wilc_debug(N_ERR, "[wilc txq]: fail can't read reg WILC_HOST_TX_CTRL..\n"); | |
1000 | break; | |
1001 | } | |
ffda203c | 1002 | reg &= ~BIT(0); |
c5c77ba1 JK |
1003 | ret = p->hif_func.hif_write_reg(WILC_HOST_TX_CTRL, reg); |
1004 | if (!ret) { | |
1005 | wilc_debug(N_ERR, "[wilc txq]: fail can't write reg WILC_HOST_TX_CTRL..\n"); | |
1006 | break; | |
1007 | } | |
1008 | break; | |
1009 | } else { | |
1010 | break; | |
1011 | } | |
1012 | } while (1); | |
1013 | ||
39823a50 | 1014 | if (!ret) |
c5c77ba1 | 1015 | goto _end_; |
39823a50 | 1016 | |
c5c77ba1 JK |
1017 | if (entries == 0) { |
1018 | ret = WILC_TX_ERR_NO_BUF; | |
1019 | goto _end_; | |
1020 | } | |
1021 | ||
1022 | /* since copying data into txb takes some time, then | |
1023 | * allow the bus lock to be released let the RX task go. */ | |
1024 | release_bus(RELEASE_ALLOW_SLEEP); | |
1025 | ||
1026 | /** | |
1027 | * Copy data to the TX buffer | |
1028 | **/ | |
1029 | offset = 0; | |
1030 | i = 0; | |
1031 | do { | |
1032 | tqe = wilc_wlan_txq_remove_from_head(); | |
1033 | if (tqe != NULL && (vmm_table[i] != 0)) { | |
fbc2fe16 | 1034 | u32 header, buffer_offset; |
c5c77ba1 JK |
1035 | |
1036 | #ifdef BIG_ENDIAN | |
1037 | vmm_table[i] = BYTE_SWAP(vmm_table[i]); | |
1038 | #endif | |
1039 | vmm_sz = (vmm_table[i] & 0x3ff); /* in word unit */ | |
1040 | vmm_sz *= 4; | |
1041 | header = (tqe->type << 31) | (tqe->buffer_size << 15) | vmm_sz; | |
78174ada | 1042 | if (tqe->type == WILC_MGMT_PKT) |
ffda203c | 1043 | header |= BIT(30); |
78174ada | 1044 | else |
ffda203c | 1045 | header &= ~BIT(30); |
c5c77ba1 JK |
1046 | |
1047 | #ifdef BIG_ENDIAN | |
1048 | header = BYTE_SWAP(header); | |
1049 | #endif | |
1050 | memcpy(&txb[offset], &header, 4); | |
1051 | if (tqe->type == WILC_CFG_PKT) { | |
1052 | buffer_offset = ETH_CONFIG_PKT_HDR_OFFSET; | |
1053 | } | |
c5c77ba1 JK |
1054 | else if (tqe->type == WILC_NET_PKT) { |
1055 | char *pBSSID = ((struct tx_complete_data *)(tqe->priv))->pBssid; | |
8dfaafd6 | 1056 | |
c5c77ba1 JK |
1057 | buffer_offset = ETH_ETHERNET_HDR_OFFSET; |
1058 | /* copy the bssid at the sart of the buffer */ | |
1059 | memcpy(&txb[offset + 4], pBSSID, 6); | |
1060 | } | |
c5c77ba1 JK |
1061 | else { |
1062 | buffer_offset = HOST_HDR_OFFSET; | |
1063 | } | |
1064 | ||
1065 | memcpy(&txb[offset + buffer_offset], tqe->buffer, tqe->buffer_size); | |
1066 | offset += vmm_sz; | |
1067 | i++; | |
1068 | tqe->status = 1; /* mark the packet send */ | |
1069 | if (tqe->tx_complete_func) | |
1070 | tqe->tx_complete_func(tqe->priv, tqe->status); | |
1071 | #ifdef TCP_ACK_FILTER | |
39823a50 | 1072 | if (tqe->tcp_PendingAck_index != NOT_TCP_ACK) |
c5c77ba1 | 1073 | Pending_Acks_info[tqe->tcp_PendingAck_index].txqe = NULL; |
c5c77ba1 | 1074 | #endif |
a18dd630 | 1075 | kfree(tqe); |
c5c77ba1 JK |
1076 | } else { |
1077 | break; | |
1078 | } | |
1079 | } while (--entries); | |
1080 | ||
1081 | /** | |
1082 | * lock the bus | |
1083 | **/ | |
1084 | acquire_bus(ACQUIRE_AND_WAKEUP); | |
1085 | ||
1086 | ret = p->hif_func.hif_clear_int_ext(ENABLE_TX_VMM); | |
1087 | if (!ret) { | |
1088 | wilc_debug(N_ERR, "[wilc txq]: fail can't start tx VMM ...\n"); | |
1089 | goto _end_; | |
1090 | } | |
1091 | ||
1092 | /** | |
1093 | * transfer | |
1094 | **/ | |
1095 | ret = p->hif_func.hif_block_tx_ext(0, txb, offset); | |
1096 | if (!ret) { | |
1097 | wilc_debug(N_ERR, "[wilc txq]: fail can't block tx ext...\n"); | |
1098 | goto _end_; | |
1099 | } | |
1100 | ||
1101 | _end_: | |
1102 | ||
1103 | release_bus(RELEASE_ALLOW_SLEEP); | |
1104 | if (ret != 1) | |
1105 | break; | |
1106 | } while (0); | |
a1332cad | 1107 | up(&wilc->txq_add_to_head_cs); |
c5c77ba1 JK |
1108 | |
1109 | p->txq_exit = 1; | |
1110 | PRINT_D(TX_DBG, "THREAD: Exiting txq\n"); | |
1111 | /* return tx[]q count */ | |
1112 | *pu32TxqCount = p->txq_entries; | |
1113 | return ret; | |
1114 | } | |
1115 | ||
39ce4d3d | 1116 | static void wilc_wlan_handle_rxq(struct wilc *wilc) |
c5c77ba1 | 1117 | { |
7ee8291a | 1118 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 | 1119 | int offset = 0, size, has_packet = 0; |
51e825f7 | 1120 | u8 *buffer; |
c5c77ba1 JK |
1121 | struct rxq_entry_t *rqe; |
1122 | ||
1123 | p->rxq_exit = 0; | |
1124 | ||
1125 | ||
1126 | ||
1127 | ||
1128 | do { | |
1129 | if (p->quit) { | |
17aacd43 | 1130 | PRINT_D(RX_DBG, "exit 1st do-while due to Clean_UP function\n"); |
39ce4d3d | 1131 | up(&wilc->cfg_event); |
c5c77ba1 JK |
1132 | break; |
1133 | } | |
db387635 | 1134 | rqe = wilc_wlan_rxq_remove(wilc); |
c5c77ba1 JK |
1135 | if (rqe == NULL) { |
1136 | PRINT_D(RX_DBG, "nothing in the queue - exit 1st do-while\n"); | |
1137 | break; | |
1138 | } | |
1139 | buffer = rqe->buffer; | |
1140 | size = rqe->buffer_size; | |
1141 | PRINT_D(RX_DBG, "rxQ entery Size = %d - Address = %p\n", size, buffer); | |
1142 | offset = 0; | |
1143 | ||
1144 | ||
1145 | ||
1146 | do { | |
fbc2fe16 CL |
1147 | u32 header; |
1148 | u32 pkt_len, pkt_offset, tp_len; | |
c5c77ba1 | 1149 | int is_cfg_packet; |
8dfaafd6 | 1150 | |
c5c77ba1 JK |
1151 | PRINT_D(RX_DBG, "In the 2nd do-while\n"); |
1152 | memcpy(&header, &buffer[offset], 4); | |
1153 | #ifdef BIG_ENDIAN | |
1154 | header = BYTE_SWAP(header); | |
1155 | #endif | |
1156 | PRINT_D(RX_DBG, "Header = %04x - Offset = %d\n", header, offset); | |
1157 | ||
1158 | ||
1159 | ||
1160 | is_cfg_packet = (header >> 31) & 0x1; | |
1161 | pkt_offset = (header >> 22) & 0x1ff; | |
1162 | tp_len = (header >> 11) & 0x7ff; | |
1163 | pkt_len = header & 0x7ff; | |
1164 | ||
1165 | if (pkt_len == 0 || tp_len == 0) { | |
1166 | wilc_debug(N_RXQ, "[wilc rxq]: data corrupt, packet len or tp_len is 0 [%d][%d]\n", pkt_len, tp_len); | |
1167 | break; | |
1168 | } | |
1169 | ||
c5c77ba1 JK |
1170 | #define IS_MANAGMEMENT 0x100 |
1171 | #define IS_MANAGMEMENT_CALLBACK 0x080 | |
1172 | #define IS_MGMT_STATUS_SUCCES 0x040 | |
1173 | ||
1174 | ||
1175 | if (pkt_offset & IS_MANAGMEMENT) { | |
1176 | /* reset mgmt indicator bit, to use pkt_offeset in furthur calculations */ | |
1177 | pkt_offset &= ~(IS_MANAGMEMENT | IS_MANAGMEMENT_CALLBACK | IS_MGMT_STATUS_SUCCES); | |
1178 | ||
11f4b2ee | 1179 | WILC_WFI_mgmt_rx(wilc, &buffer[offset + HOST_HDR_OFFSET], pkt_len); |
c5c77ba1 | 1180 | } |
c5c77ba1 | 1181 | else |
c5c77ba1 | 1182 | { |
c5c77ba1 JK |
1183 | |
1184 | if (!is_cfg_packet) { | |
63611670 | 1185 | if (pkt_len > 0) { |
cb1991ac GL |
1186 | frmw_to_linux(wilc, |
1187 | &buffer[offset], | |
63611670 GL |
1188 | pkt_len, |
1189 | pkt_offset); | |
1190 | has_packet = 1; | |
c5c77ba1 JK |
1191 | } |
1192 | } else { | |
1193 | wilc_cfg_rsp_t rsp; | |
1194 | ||
1195 | ||
1196 | ||
30f535a6 | 1197 | wilc_wlan_cfg_indicate_rx(&buffer[pkt_offset + offset], pkt_len, &rsp); |
c5c77ba1 JK |
1198 | if (rsp.type == WILC_CFG_RSP) { |
1199 | /** | |
1200 | * wake up the waiting task... | |
1201 | **/ | |
1202 | PRINT_D(RX_DBG, "p->cfg_seq_no = %d - rsp.seq_no = %d\n", p->cfg_seq_no, rsp.seq_no); | |
39823a50 | 1203 | if (p->cfg_seq_no == rsp.seq_no) |
39ce4d3d | 1204 | up(&wilc->cfg_event); |
c5c77ba1 JK |
1205 | } else if (rsp.type == WILC_CFG_RSP_STATUS) { |
1206 | /** | |
1207 | * Call back to indicate status... | |
1208 | **/ | |
64f2b71b | 1209 | linux_wlan_mac_indicate(wilc, WILC_MAC_INDICATE_STATUS); |
c5c77ba1 JK |
1210 | |
1211 | } else if (rsp.type == WILC_CFG_RSP_SCAN) { | |
64f2b71b | 1212 | linux_wlan_mac_indicate(wilc, WILC_MAC_INDICATE_SCAN); |
c5c77ba1 JK |
1213 | } |
1214 | } | |
1215 | } | |
1216 | offset += tp_len; | |
1217 | if (offset >= size) | |
1218 | break; | |
1219 | } while (1); | |
1220 | ||
1221 | ||
1222 | #ifndef MEMORY_STATIC | |
a18dd630 | 1223 | kfree(buffer); |
c5c77ba1 | 1224 | #endif |
a18dd630 | 1225 | kfree(rqe); |
c5c77ba1 | 1226 | |
39823a50 | 1227 | if (has_packet) |
c0cadaa4 | 1228 | linux_wlan_rx_complete(); |
39823a50 | 1229 | |
c5c77ba1 JK |
1230 | } while (1); |
1231 | ||
1232 | p->rxq_exit = 1; | |
17aacd43 | 1233 | PRINT_D(RX_DBG, "THREAD: Exiting RX thread\n"); |
c5c77ba1 JK |
1234 | } |
1235 | ||
1236 | /******************************************** | |
1237 | * | |
1238 | * Fast DMA Isr | |
1239 | * | |
1240 | ********************************************/ | |
1241 | static void wilc_unknown_isr_ext(void) | |
1242 | { | |
1243 | g_wlan.hif_func.hif_clear_int_ext(0); | |
1244 | } | |
fbc2fe16 | 1245 | static void wilc_pllupdate_isr_ext(u32 int_stats) |
c5c77ba1 JK |
1246 | { |
1247 | ||
1248 | int trials = 10; | |
1249 | ||
1250 | g_wlan.hif_func.hif_clear_int_ext(PLL_INT_CLR); | |
1251 | ||
1252 | /* Waiting for PLL */ | |
c2e4c0f1 | 1253 | mdelay(WILC_PLL_TO); |
c5c77ba1 JK |
1254 | |
1255 | /* poll till read a valid data */ | |
72ed4dc7 | 1256 | while (!(ISWILC1000(wilc_get_chipid(true)) && --trials)) { |
c5c77ba1 | 1257 | PRINT_D(TX_DBG, "PLL update retrying\n"); |
c2e4c0f1 | 1258 | mdelay(1); |
c5c77ba1 JK |
1259 | } |
1260 | } | |
1261 | ||
fbc2fe16 | 1262 | static void wilc_sleeptimer_isr_ext(u32 int_stats1) |
c5c77ba1 JK |
1263 | { |
1264 | g_wlan.hif_func.hif_clear_int_ext(SLEEP_INT_CLR); | |
1265 | #ifndef WILC_OPTIMIZE_SLEEP_INT | |
1266 | genuChipPSstate = CHIP_SLEEPING_AUTO; | |
1267 | #endif | |
1268 | } | |
1269 | ||
3bcd45b6 | 1270 | static void wilc_wlan_handle_isr_ext(struct wilc *wilc, u32 int_status) |
c5c77ba1 | 1271 | { |
7ee8291a | 1272 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 | 1273 | #ifdef MEMORY_STATIC |
fbc2fe16 | 1274 | u32 offset = p->rx_buffer_offset; |
c5c77ba1 | 1275 | #endif |
51e825f7 | 1276 | u8 *buffer = NULL; |
fbc2fe16 CL |
1277 | u32 size; |
1278 | u32 retries = 0; | |
c5c77ba1 JK |
1279 | int ret = 0; |
1280 | struct rxq_entry_t *rqe; | |
1281 | ||
1282 | ||
1283 | /** | |
1284 | * Get the rx size | |
1285 | **/ | |
1286 | ||
1287 | size = ((int_status & 0x7fff) << 2); | |
1288 | ||
1289 | while (!size && retries < 10) { | |
fbc2fe16 | 1290 | u32 time = 0; |
c5c77ba1 JK |
1291 | /*looping more secure*/ |
1292 | /*zero size make a crashe because the dma will not happen and that will block the firmware*/ | |
1293 | wilc_debug(N_ERR, "RX Size equal zero ... Trying to read it again for %d time\n", time++); | |
1294 | p->hif_func.hif_read_size(&size); | |
1295 | size = ((size & 0x7fff) << 2); | |
1296 | retries++; | |
1297 | ||
1298 | } | |
1299 | ||
1300 | if (size > 0) { | |
1301 | #ifdef MEMORY_STATIC | |
03eb7266 | 1302 | if (LINUX_RX_SIZE - offset < size) |
c5c77ba1 JK |
1303 | offset = 0; |
1304 | ||
1305 | if (p->rx_buffer) | |
1306 | buffer = &p->rx_buffer[offset]; | |
1307 | else { | |
1308 | wilc_debug(N_ERR, "[wilc isr]: fail Rx Buffer is NULL...drop the packets (%d)\n", size); | |
1309 | goto _end_; | |
1310 | } | |
1311 | ||
1312 | #else | |
f019b9d9 | 1313 | buffer = kmalloc(size, GFP_KERNEL); |
c5c77ba1 JK |
1314 | if (buffer == NULL) { |
1315 | wilc_debug(N_ERR, "[wilc isr]: fail alloc host memory...drop the packets (%d)\n", size); | |
80e29c7a | 1316 | usleep_range(100 * 1000, 100 * 1000); |
c5c77ba1 JK |
1317 | goto _end_; |
1318 | } | |
1319 | #endif | |
1320 | ||
1321 | /** | |
1322 | * clear the chip's interrupt after getting size some register getting corrupted after clear the interrupt | |
1323 | **/ | |
1324 | p->hif_func.hif_clear_int_ext(DATA_INT_CLR | ENABLE_RX_VMM); | |
1325 | ||
1326 | ||
1327 | /** | |
1328 | * start transfer | |
1329 | **/ | |
1330 | ret = p->hif_func.hif_block_rx_ext(0, buffer, size); | |
1331 | ||
1332 | if (!ret) { | |
1333 | wilc_debug(N_ERR, "[wilc isr]: fail block rx...\n"); | |
1334 | goto _end_; | |
1335 | } | |
1336 | _end_: | |
1337 | ||
1338 | ||
1339 | if (ret) { | |
1340 | #ifdef MEMORY_STATIC | |
1341 | offset += size; | |
1342 | p->rx_buffer_offset = offset; | |
1343 | #endif | |
1344 | /** | |
1345 | * add to rx queue | |
1346 | **/ | |
f019b9d9 | 1347 | rqe = kmalloc(sizeof(struct rxq_entry_t), GFP_KERNEL); |
c5c77ba1 JK |
1348 | if (rqe != NULL) { |
1349 | rqe->buffer = buffer; | |
1350 | rqe->buffer_size = size; | |
1351 | PRINT_D(RX_DBG, "rxq entery Size= %d - Address = %p\n", rqe->buffer_size, rqe->buffer); | |
d06f362c | 1352 | wilc_wlan_rxq_add(wilc, rqe); |
c5c77ba1 JK |
1353 | } |
1354 | } else { | |
1355 | #ifndef MEMORY_STATIC | |
a18dd630 | 1356 | kfree(buffer); |
c5c77ba1 JK |
1357 | #endif |
1358 | } | |
1359 | } | |
39ce4d3d | 1360 | wilc_wlan_handle_rxq(wilc); |
c5c77ba1 JK |
1361 | } |
1362 | ||
50b929e0 | 1363 | void wilc_handle_isr(void *wilc) |
c5c77ba1 | 1364 | { |
fbc2fe16 | 1365 | u32 int_status; |
c5c77ba1 JK |
1366 | |
1367 | acquire_bus(ACQUIRE_AND_WAKEUP); | |
1368 | g_wlan.hif_func.hif_read_int(&int_status); | |
1369 | ||
39823a50 | 1370 | if (int_status & PLL_INT_EXT) |
c5c77ba1 | 1371 | wilc_pllupdate_isr_ext(int_status); |
39823a50 | 1372 | |
c5c77ba1 | 1373 | if (int_status & DATA_INT_EXT) { |
3bcd45b6 | 1374 | wilc_wlan_handle_isr_ext(wilc, int_status); |
c5c77ba1 JK |
1375 | #ifndef WILC_OPTIMIZE_SLEEP_INT |
1376 | /* Chip is up and talking*/ | |
1377 | genuChipPSstate = CHIP_WAKEDUP; | |
1378 | #endif | |
1379 | } | |
39823a50 | 1380 | if (int_status & SLEEP_INT_EXT) |
c5c77ba1 | 1381 | wilc_sleeptimer_isr_ext(int_status); |
c5c77ba1 JK |
1382 | |
1383 | if (!(int_status & (ALL_INT_EXT))) { | |
1384 | #ifdef WILC_SDIO | |
1385 | PRINT_D(TX_DBG, ">> UNKNOWN_INTERRUPT - 0x%08x\n", int_status); | |
1386 | #endif | |
1387 | wilc_unknown_isr_ext(); | |
1388 | } | |
c5c77ba1 JK |
1389 | release_bus(RELEASE_ALLOW_SLEEP); |
1390 | } | |
1391 | ||
1392 | /******************************************** | |
1393 | * | |
1394 | * Firmware download | |
1395 | * | |
1396 | ********************************************/ | |
63d7ab8e | 1397 | int wilc_wlan_firmware_download(const u8 *buffer, u32 buffer_size) |
c5c77ba1 | 1398 | { |
7ee8291a | 1399 | wilc_wlan_dev_t *p = &g_wlan; |
fbc2fe16 CL |
1400 | u32 offset; |
1401 | u32 addr, size, size2, blksz; | |
51e825f7 | 1402 | u8 *dma_buffer; |
c5c77ba1 JK |
1403 | int ret = 0; |
1404 | ||
ffda203c | 1405 | blksz = BIT(12); |
c5c77ba1 JK |
1406 | /* Allocate a DMA coherent buffer. */ |
1407 | ||
f019b9d9 | 1408 | dma_buffer = kmalloc(blksz, GFP_KERNEL); |
c5c77ba1 JK |
1409 | if (dma_buffer == NULL) { |
1410 | /*EIO 5*/ | |
1411 | ret = -5; | |
1412 | PRINT_ER("Can't allocate buffer for firmware download IO error\n "); | |
1413 | goto _fail_1; | |
1414 | } | |
1415 | ||
1416 | PRINT_D(INIT_DBG, "Downloading firmware size = %d ...\n", buffer_size); | |
1417 | /** | |
1418 | * load the firmware | |
1419 | **/ | |
1420 | offset = 0; | |
1421 | do { | |
1422 | memcpy(&addr, &buffer[offset], 4); | |
1423 | memcpy(&size, &buffer[offset + 4], 4); | |
1424 | #ifdef BIG_ENDIAN | |
1425 | addr = BYTE_SWAP(addr); | |
1426 | size = BYTE_SWAP(size); | |
1427 | #endif | |
1428 | acquire_bus(ACQUIRE_ONLY); | |
1429 | offset += 8; | |
1430 | while (((int)size) && (offset < buffer_size)) { | |
78174ada | 1431 | if (size <= blksz) |
c5c77ba1 | 1432 | size2 = size; |
78174ada | 1433 | else |
c5c77ba1 | 1434 | size2 = blksz; |
c5c77ba1 JK |
1435 | /* Copy firmware into a DMA coherent buffer */ |
1436 | memcpy(dma_buffer, &buffer[offset], size2); | |
1437 | ret = p->hif_func.hif_block_tx(addr, dma_buffer, size2); | |
1438 | if (!ret) | |
1439 | break; | |
1440 | ||
1441 | addr += size2; | |
1442 | offset += size2; | |
1443 | size -= size2; | |
1444 | } | |
1445 | release_bus(RELEASE_ONLY); | |
1446 | ||
1447 | if (!ret) { | |
1448 | /*EIO 5*/ | |
1449 | ret = -5; | |
1450 | PRINT_ER("Can't download firmware IO error\n "); | |
1451 | goto _fail_; | |
1452 | } | |
1453 | PRINT_D(INIT_DBG, "Offset = %d\n", offset); | |
1454 | } while (offset < buffer_size); | |
1455 | ||
1456 | _fail_: | |
1457 | ||
a18dd630 | 1458 | kfree(dma_buffer); |
c5c77ba1 JK |
1459 | |
1460 | _fail_1: | |
1461 | ||
1462 | return (ret < 0) ? ret : 0; | |
1463 | } | |
1464 | ||
1465 | /******************************************** | |
1466 | * | |
1467 | * Common | |
1468 | * | |
1469 | ********************************************/ | |
e42563bb | 1470 | int wilc_wlan_start(void) |
c5c77ba1 | 1471 | { |
7ee8291a | 1472 | wilc_wlan_dev_t *p = &g_wlan; |
fbc2fe16 | 1473 | u32 reg = 0; |
c5c77ba1 | 1474 | int ret; |
fbc2fe16 | 1475 | u32 chipid; |
c5c77ba1 JK |
1476 | |
1477 | /** | |
1478 | * Set the host interface | |
1479 | **/ | |
c5c77ba1 JK |
1480 | if (p->io_func.io_type == HIF_SDIO) { |
1481 | reg = 0; | |
ffda203c | 1482 | reg |= BIT(3); /* bug 4456 and 4557 */ |
c5c77ba1 JK |
1483 | } else if (p->io_func.io_type == HIF_SPI) { |
1484 | reg = 1; | |
1485 | } | |
1486 | acquire_bus(ACQUIRE_ONLY); | |
1487 | ret = p->hif_func.hif_write_reg(WILC_VMM_CORE_CFG, reg); | |
1488 | if (!ret) { | |
1489 | wilc_debug(N_ERR, "[wilc start]: fail write reg vmm_core_cfg...\n"); | |
1490 | release_bus(RELEASE_ONLY); | |
1491 | /* EIO 5*/ | |
1492 | ret = -5; | |
1493 | return ret; | |
1494 | } | |
1495 | reg = 0; | |
1496 | #ifdef WILC_SDIO_IRQ_GPIO | |
1497 | reg |= WILC_HAVE_SDIO_IRQ_GPIO; | |
1498 | #endif | |
1499 | ||
1500 | #ifdef WILC_DISABLE_PMU | |
1501 | #else | |
1502 | reg |= WILC_HAVE_USE_PMU; | |
1503 | #endif | |
1504 | ||
1505 | #ifdef WILC_SLEEP_CLK_SRC_XO | |
1506 | reg |= WILC_HAVE_SLEEP_CLK_SRC_XO; | |
1507 | #elif defined WILC_SLEEP_CLK_SRC_RTC | |
1508 | reg |= WILC_HAVE_SLEEP_CLK_SRC_RTC; | |
1509 | #endif | |
1510 | ||
1511 | #ifdef WILC_EXT_PA_INV_TX_RX | |
1512 | reg |= WILC_HAVE_EXT_PA_INV_TX_RX; | |
1513 | #endif | |
1514 | ||
1515 | reg |= WILC_HAVE_LEGACY_RF_SETTINGS; | |
1516 | ||
1517 | ||
c5c77ba1 JK |
1518 | /*Set oscillator frequency*/ |
1519 | #ifdef XTAL_24 | |
1520 | reg |= WILC_HAVE_XTAL_24; | |
1521 | #endif | |
1522 | ||
c5c77ba1 JK |
1523 | /*Enable/Disable GPIO configuration for FW logs*/ |
1524 | #ifdef DISABLE_WILC_UART | |
1525 | reg |= WILC_HAVE_DISABLE_WILC_UART; | |
1526 | #endif | |
1527 | ||
1528 | ret = p->hif_func.hif_write_reg(WILC_GP_REG_1, reg); | |
1529 | if (!ret) { | |
1530 | wilc_debug(N_ERR, "[wilc start]: fail write WILC_GP_REG_1 ...\n"); | |
1531 | release_bus(RELEASE_ONLY); | |
1532 | /* EIO 5*/ | |
1533 | ret = -5; | |
1534 | return ret; | |
1535 | } | |
c5c77ba1 JK |
1536 | |
1537 | /** | |
1538 | * Bus related | |
1539 | **/ | |
1540 | p->hif_func.hif_sync_ext(NUM_INT_EXT); | |
1541 | ||
1542 | ret = p->hif_func.hif_read_reg(0x1000, &chipid); | |
1543 | if (!ret) { | |
1544 | wilc_debug(N_ERR, "[wilc start]: fail read reg 0x1000 ...\n"); | |
1545 | release_bus(RELEASE_ONLY); | |
1546 | /* EIO 5*/ | |
1547 | ret = -5; | |
1548 | return ret; | |
1549 | } | |
1550 | ||
1551 | /** | |
1552 | * Go... | |
1553 | **/ | |
1554 | ||
c5c77ba1 JK |
1555 | |
1556 | p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
ffda203c AB |
1557 | if ((reg & BIT(10)) == BIT(10)) { |
1558 | reg &= ~BIT(10); | |
c5c77ba1 JK |
1559 | p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); |
1560 | p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
1561 | } | |
1562 | ||
ffda203c | 1563 | reg |= BIT(10); |
c5c77ba1 JK |
1564 | ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); |
1565 | p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
1566 | release_bus(RELEASE_ONLY); | |
1567 | ||
1568 | return (ret < 0) ? ret : 0; | |
1569 | } | |
1570 | ||
1571 | void wilc_wlan_global_reset(void) | |
1572 | { | |
1573 | ||
7ee8291a | 1574 | wilc_wlan_dev_t *p = &g_wlan; |
8dfaafd6 | 1575 | |
c5c77ba1 JK |
1576 | acquire_bus(ACQUIRE_AND_WAKEUP); |
1577 | p->hif_func.hif_write_reg(WILC_GLB_RESET_0, 0x0); | |
1578 | release_bus(RELEASE_ONLY); | |
1579 | } | |
8cec741e | 1580 | int wilc_wlan_stop(void) |
c5c77ba1 | 1581 | { |
7ee8291a | 1582 | wilc_wlan_dev_t *p = &g_wlan; |
fbc2fe16 | 1583 | u32 reg = 0; |
c5c77ba1 | 1584 | int ret; |
51e825f7 | 1585 | u8 timeout = 10; |
c5c77ba1 JK |
1586 | /** |
1587 | * TODO: stop the firmware, need a re-download | |
1588 | **/ | |
1589 | acquire_bus(ACQUIRE_AND_WAKEUP); | |
1590 | ||
1591 | ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
1592 | if (!ret) { | |
1593 | PRINT_ER("Error while reading reg\n"); | |
1594 | release_bus(RELEASE_ALLOW_SLEEP); | |
1595 | return ret; | |
1596 | } | |
1597 | ||
ffda203c | 1598 | reg &= ~BIT(10); |
c5c77ba1 JK |
1599 | |
1600 | ||
1601 | ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); | |
1602 | if (!ret) { | |
1603 | PRINT_ER("Error while writing reg\n"); | |
1604 | release_bus(RELEASE_ALLOW_SLEEP); | |
1605 | return ret; | |
1606 | } | |
1607 | ||
1608 | ||
1609 | ||
1610 | do { | |
1611 | ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
1612 | if (!ret) { | |
1613 | PRINT_ER("Error while reading reg\n"); | |
1614 | release_bus(RELEASE_ALLOW_SLEEP); | |
1615 | return ret; | |
1616 | } | |
1617 | PRINT_D(GENERIC_DBG, "Read RESET Reg %x : Retry%d\n", reg, timeout); | |
1618 | /*Workaround to ensure that the chip is actually reset*/ | |
ffda203c | 1619 | if ((reg & BIT(10))) { |
c5c77ba1 | 1620 | PRINT_D(GENERIC_DBG, "Bit 10 not reset : Retry %d\n", timeout); |
ffda203c | 1621 | reg &= ~BIT(10); |
c5c77ba1 JK |
1622 | ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); |
1623 | timeout--; | |
1624 | } else { | |
1625 | PRINT_D(GENERIC_DBG, "Bit 10 reset after : Retry %d\n", timeout); | |
1626 | ret = p->hif_func.hif_read_reg(WILC_GLB_RESET_0, ®); | |
1627 | if (!ret) { | |
1628 | PRINT_ER("Error while reading reg\n"); | |
1629 | release_bus(RELEASE_ALLOW_SLEEP); | |
1630 | return ret; | |
1631 | } | |
1632 | PRINT_D(GENERIC_DBG, "Read RESET Reg %x : Retry%d\n", reg, timeout); | |
1633 | break; | |
1634 | } | |
1635 | ||
1636 | } while (timeout); | |
ffda203c AB |
1637 | reg = (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(8) | BIT(9) | BIT(26) | |
1638 | BIT(29) | BIT(30) | BIT(31)); | |
65ead4ec AB |
1639 | |
1640 | p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); | |
ffda203c | 1641 | reg = (u32)~BIT(10); |
65ead4ec AB |
1642 | |
1643 | ret = p->hif_func.hif_write_reg(WILC_GLB_RESET_0, reg); | |
c5c77ba1 JK |
1644 | |
1645 | release_bus(RELEASE_ALLOW_SLEEP); | |
1646 | ||
1647 | return ret; | |
1648 | } | |
1649 | ||
2de7cbec | 1650 | void wilc_wlan_cleanup(struct net_device *dev) |
c5c77ba1 | 1651 | { |
7ee8291a | 1652 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 JK |
1653 | struct txq_entry_t *tqe; |
1654 | struct rxq_entry_t *rqe; | |
fbc2fe16 | 1655 | u32 reg = 0; |
c5c77ba1 | 1656 | int ret; |
db387635 GL |
1657 | perInterface_wlan_t *nic; |
1658 | struct wilc *wilc; | |
1659 | ||
1660 | nic = netdev_priv(dev); | |
1661 | wilc = nic->wilc; | |
c5c77ba1 JK |
1662 | |
1663 | p->quit = 1; | |
c5c77ba1 JK |
1664 | do { |
1665 | tqe = wilc_wlan_txq_remove_from_head(); | |
1666 | if (tqe == NULL) | |
1667 | break; | |
1668 | if (tqe->tx_complete_func) | |
1669 | tqe->tx_complete_func(tqe->priv, 0); | |
a18dd630 | 1670 | kfree(tqe); |
c5c77ba1 JK |
1671 | } while (1); |
1672 | ||
1673 | do { | |
db387635 | 1674 | rqe = wilc_wlan_rxq_remove(wilc); |
c5c77ba1 JK |
1675 | if (rqe == NULL) |
1676 | break; | |
6a27224f JMC |
1677 | #ifndef MEMORY_STATIC |
1678 | kfree(rqe->buffer); | |
c5c77ba1 | 1679 | #endif |
a18dd630 | 1680 | kfree(rqe); |
c5c77ba1 JK |
1681 | } while (1); |
1682 | ||
1683 | /** | |
1684 | * clean up buffer | |
1685 | **/ | |
1686 | ||
c5c77ba1 | 1687 | #ifdef MEMORY_STATIC |
a18dd630 GKH |
1688 | kfree(p->rx_buffer); |
1689 | p->rx_buffer = NULL; | |
c5c77ba1 | 1690 | #endif |
a18dd630 | 1691 | kfree(p->tx_buffer); |
c5c77ba1 JK |
1692 | |
1693 | acquire_bus(ACQUIRE_AND_WAKEUP); | |
1694 | ||
1695 | ||
1696 | ret = p->hif_func.hif_read_reg(WILC_GP_REG_0, ®); | |
1697 | if (!ret) { | |
1698 | PRINT_ER("Error while reading reg\n"); | |
1699 | release_bus(RELEASE_ALLOW_SLEEP); | |
1700 | } | |
1701 | PRINT_ER("Writing ABORT reg\n"); | |
1702 | ret = p->hif_func.hif_write_reg(WILC_GP_REG_0, (reg | ABORT_INT)); | |
1703 | if (!ret) { | |
1704 | PRINT_ER("Error while writing reg\n"); | |
1705 | release_bus(RELEASE_ALLOW_SLEEP); | |
1706 | } | |
1707 | release_bus(RELEASE_ALLOW_SLEEP); | |
1708 | /** | |
1709 | * io clean up | |
1710 | **/ | |
1711 | p->hif_func.hif_deinit(NULL); | |
1712 | ||
1713 | } | |
1714 | ||
fbc2fe16 | 1715 | static int wilc_wlan_cfg_commit(int type, u32 drvHandler) |
c5c77ba1 | 1716 | { |
7ee8291a | 1717 | wilc_wlan_dev_t *p = &g_wlan; |
c5c77ba1 JK |
1718 | wilc_cfg_frame_t *cfg = &p->cfg_frame; |
1719 | int total_len = p->cfg_frame_offset + 4 + DRIVER_HANDLER_SIZE; | |
1720 | int seq_no = p->cfg_seq_no % 256; | |
4e4467fd | 1721 | int driver_handler = (u32)drvHandler; |
c5c77ba1 JK |
1722 | |
1723 | ||
1724 | /** | |
1725 | * Set up header | |
1726 | **/ | |
1727 | if (type == WILC_CFG_SET) { /* Set */ | |
1728 | cfg->wid_header[0] = 'W'; | |
1729 | } else { /* Query */ | |
1730 | cfg->wid_header[0] = 'Q'; | |
1731 | } | |
1732 | cfg->wid_header[1] = seq_no; /* sequence number */ | |
51e825f7 CL |
1733 | cfg->wid_header[2] = (u8)total_len; |
1734 | cfg->wid_header[3] = (u8)(total_len >> 8); | |
1735 | cfg->wid_header[4] = (u8)driver_handler; | |
1736 | cfg->wid_header[5] = (u8)(driver_handler >> 8); | |
1737 | cfg->wid_header[6] = (u8)(driver_handler >> 16); | |
1738 | cfg->wid_header[7] = (u8)(driver_handler >> 24); | |
c5c77ba1 JK |
1739 | p->cfg_seq_no = seq_no; |
1740 | ||
1741 | /** | |
1742 | * Add to TX queue | |
1743 | **/ | |
1744 | ||
c5c77ba1 JK |
1745 | if (!wilc_wlan_txq_add_cfg_pkt(&cfg->wid_header[0], total_len)) |
1746 | return -1; | |
1747 | ||
1748 | return 0; | |
1749 | } | |
1750 | ||
1028e5a4 GL |
1751 | int wilc_wlan_cfg_set(int start, u32 wid, u8 *buffer, u32 buffer_size, |
1752 | int commit, u32 drvHandler) | |
c5c77ba1 | 1753 | { |
7ee8291a | 1754 | wilc_wlan_dev_t *p = &g_wlan; |
fbc2fe16 | 1755 | u32 offset; |
c5c77ba1 JK |
1756 | int ret_size; |
1757 | ||
1758 | ||
1759 | if (p->cfg_frame_in_use) | |
1760 | return 0; | |
1761 | ||
1762 | if (start) | |
1763 | p->cfg_frame_offset = 0; | |
1764 | ||
1765 | offset = p->cfg_frame_offset; | |
17e8f165 GL |
1766 | ret_size = wilc_wlan_cfg_set_wid(p->cfg_frame.frame, offset, (u16)wid, |
1767 | buffer, buffer_size); | |
c5c77ba1 JK |
1768 | offset += ret_size; |
1769 | p->cfg_frame_offset = offset; | |
1770 | ||
1771 | if (commit) { | |
1772 | PRINT_D(TX_DBG, "[WILC]PACKET Commit with sequence number %d\n", p->cfg_seq_no); | |
1773 | PRINT_D(RX_DBG, "Processing cfg_set()\n"); | |
1774 | p->cfg_frame_in_use = 1; | |
1775 | ||
c5c77ba1 | 1776 | if (wilc_wlan_cfg_commit(WILC_CFG_SET, drvHandler)) |
5af6b85b | 1777 | ret_size = 0; |
c5c77ba1 | 1778 | |
b002e20d GL |
1779 | if (linux_wlan_lock_timeout(&g_linux_wlan->cfg_event, |
1780 | CFG_PKTS_TIMEOUT)) { | |
c5c77ba1 JK |
1781 | PRINT_D(TX_DBG, "Set Timed Out\n"); |
1782 | ret_size = 0; | |
1783 | } | |
1784 | p->cfg_frame_in_use = 0; | |
1785 | p->cfg_frame_offset = 0; | |
1786 | p->cfg_seq_no += 1; | |
1787 | ||
1788 | } | |
1789 | ||
1790 | return ret_size; | |
1791 | } | |
07056a85 | 1792 | int wilc_wlan_cfg_get(int start, u32 wid, int commit, u32 drvHandler) |
c5c77ba1 | 1793 | { |
7ee8291a | 1794 | wilc_wlan_dev_t *p = &g_wlan; |
fbc2fe16 | 1795 | u32 offset; |
c5c77ba1 JK |
1796 | int ret_size; |
1797 | ||
1798 | ||
1799 | if (p->cfg_frame_in_use) | |
1800 | return 0; | |
1801 | ||
1802 | if (start) | |
1803 | p->cfg_frame_offset = 0; | |
1804 | ||
1805 | offset = p->cfg_frame_offset; | |
ec1b86bf | 1806 | ret_size = wilc_wlan_cfg_get_wid(p->cfg_frame.frame, offset, (u16)wid); |
c5c77ba1 JK |
1807 | offset += ret_size; |
1808 | p->cfg_frame_offset = offset; | |
1809 | ||
1810 | if (commit) { | |
1811 | p->cfg_frame_in_use = 1; | |
1812 | ||
c5c77ba1 | 1813 | if (wilc_wlan_cfg_commit(WILC_CFG_QUERY, drvHandler)) |
5af6b85b | 1814 | ret_size = 0; |
c5c77ba1 JK |
1815 | |
1816 | ||
b002e20d GL |
1817 | if (linux_wlan_lock_timeout(&g_linux_wlan->cfg_event, |
1818 | CFG_PKTS_TIMEOUT)) { | |
c5c77ba1 JK |
1819 | PRINT_D(TX_DBG, "Get Timed Out\n"); |
1820 | ret_size = 0; | |
1821 | } | |
1822 | PRINT_D(GENERIC_DBG, "[WILC]Get Response received\n"); | |
1823 | p->cfg_frame_in_use = 0; | |
1824 | p->cfg_frame_offset = 0; | |
1825 | p->cfg_seq_no += 1; | |
1826 | } | |
1827 | ||
1828 | return ret_size; | |
1829 | } | |
1830 | ||
894de36b | 1831 | int wilc_wlan_cfg_get_val(u32 wid, u8 *buffer, u32 buffer_size) |
c5c77ba1 | 1832 | { |
c5c77ba1 JK |
1833 | int ret; |
1834 | ||
355cca2a | 1835 | ret = wilc_wlan_cfg_get_wid_value((u16)wid, buffer, buffer_size); |
c5c77ba1 JK |
1836 | |
1837 | return ret; | |
1838 | } | |
1839 | ||
1840 | void wilc_bus_set_max_speed(void) | |
1841 | { | |
1842 | ||
1843 | /* Increase bus speed to max possible. */ | |
1844 | g_wlan.hif_func.hif_set_max_bus_speed(); | |
1845 | } | |
1846 | ||
1847 | void wilc_bus_set_default_speed(void) | |
1848 | { | |
1849 | ||
1850 | /* Restore bus speed to default. */ | |
1851 | g_wlan.hif_func.hif_set_default_bus_speed(); | |
1852 | } | |
fbc2fe16 | 1853 | u32 init_chip(void) |
c5c77ba1 | 1854 | { |
fbc2fe16 CL |
1855 | u32 chipid; |
1856 | u32 reg, ret = 0; | |
c5c77ba1 | 1857 | |
c5c77ba1 | 1858 | acquire_bus(ACQUIRE_ONLY); |
c5c77ba1 | 1859 | |
72ed4dc7 | 1860 | chipid = wilc_get_chipid(true); |
c5c77ba1 JK |
1861 | |
1862 | ||
1863 | ||
1864 | if ((chipid & 0xfff) != 0xa0) { | |
1865 | /** | |
1866 | * Avoid booting from boot ROM. Make sure that Drive IRQN [SDIO platform] | |
1867 | * or SD_DAT3 [SPI platform] to ?1? | |
1868 | **/ | |
1869 | /* Set cortus reset register to register control. */ | |
1870 | ret = g_wlan.hif_func.hif_read_reg(0x1118, ®); | |
1871 | if (!ret) { | |
1872 | wilc_debug(N_ERR, "[wilc start]: fail read reg 0x1118 ...\n"); | |
1873 | return ret; | |
1874 | } | |
ffda203c | 1875 | reg |= BIT(0); |
c5c77ba1 JK |
1876 | ret = g_wlan.hif_func.hif_write_reg(0x1118, reg); |
1877 | if (!ret) { | |
1878 | wilc_debug(N_ERR, "[wilc start]: fail write reg 0x1118 ...\n"); | |
1879 | return ret; | |
1880 | } | |
1881 | /** | |
1882 | * Write branch intruction to IRAM (0x71 trap) at location 0xFFFF0000 | |
1883 | * (Cortus map) or C0000 (AHB map). | |
1884 | **/ | |
1885 | ret = g_wlan.hif_func.hif_write_reg(0xc0000, 0x71); | |
1886 | if (!ret) { | |
1887 | wilc_debug(N_ERR, "[wilc start]: fail write reg 0xc0000 ...\n"); | |
1888 | return ret; | |
1889 | } | |
1890 | } | |
1891 | ||
c5c77ba1 JK |
1892 | release_bus(RELEASE_ONLY); |
1893 | ||
1894 | return ret; | |
1895 | ||
1896 | } | |
1897 | ||
fbc2fe16 | 1898 | u32 wilc_get_chipid(u8 update) |
c5c77ba1 | 1899 | { |
fbc2fe16 | 1900 | static u32 chipid; |
c5c77ba1 JK |
1901 | /* SDIO can't read into global variables */ |
1902 | /* Use this variable as a temp, then copy to the global */ | |
fbc2fe16 CL |
1903 | u32 tempchipid = 0; |
1904 | u32 rfrevid; | |
c5c77ba1 JK |
1905 | |
1906 | if (chipid == 0 || update != 0) { | |
1907 | g_wlan.hif_func.hif_read_reg(0x1000, &tempchipid); | |
1908 | g_wlan.hif_func.hif_read_reg(0x13f4, &rfrevid); | |
1909 | if (!ISWILC1000(tempchipid)) { | |
1910 | chipid = 0; | |
1911 | goto _fail_; | |
1912 | } | |
1913 | if (tempchipid == 0x1002a0) { | |
1914 | if (rfrevid == 0x1) { /* 1002A0 */ | |
1915 | } else { /* if (rfrevid == 0x2) */ /* 1002A1 */ | |
1916 | tempchipid = 0x1002a1; | |
1917 | } | |
1918 | } else if (tempchipid == 0x1002b0) { | |
1919 | if (rfrevid == 3) { /* 1002B0 */ | |
1920 | } else if (rfrevid == 4) { /* 1002B1 */ | |
1921 | tempchipid = 0x1002b1; | |
1922 | } else { /* if(rfrevid == 5) */ /* 1002B2 */ | |
1923 | tempchipid = 0x1002b2; | |
1924 | } | |
1925 | } else { | |
1926 | } | |
1927 | ||
1928 | chipid = tempchipid; | |
1929 | } | |
1930 | _fail_: | |
1931 | return chipid; | |
1932 | } | |
1933 | ||
c9d4834d | 1934 | int wilc_wlan_init(wilc_wlan_inp_t *inp) |
c5c77ba1 JK |
1935 | { |
1936 | ||
1937 | int ret = 0; | |
1938 | ||
1939 | PRINT_D(INIT_DBG, "Initializing WILC_Wlan ...\n"); | |
1940 | ||
1941 | memset((void *)&g_wlan, 0, sizeof(wilc_wlan_dev_t)); | |
1942 | ||
1943 | /** | |
1944 | * store the input | |
1945 | **/ | |
c5c77ba1 | 1946 | memcpy((void *)&g_wlan.io_func, (void *)&inp->io_func, sizeof(wilc_wlan_io_func_t)); |
c5c77ba1 JK |
1947 | /*** |
1948 | * host interface init | |
1949 | **/ | |
c5c77ba1 JK |
1950 | if ((inp->io_func.io_type & 0x1) == HIF_SDIO) { |
1951 | if (!hif_sdio.hif_init(inp, wilc_debug)) { | |
1952 | /* EIO 5 */ | |
1953 | ret = -5; | |
1954 | goto _fail_; | |
1955 | } | |
1956 | memcpy((void *)&g_wlan.hif_func, &hif_sdio, sizeof(wilc_hif_func_t)); | |
1957 | } else { | |
1958 | if ((inp->io_func.io_type & 0x1) == HIF_SPI) { | |
1959 | /** | |
1960 | * TODO: | |
1961 | **/ | |
1962 | if (!hif_spi.hif_init(inp, wilc_debug)) { | |
1963 | /* EIO 5 */ | |
1964 | ret = -5; | |
1965 | goto _fail_; | |
1966 | } | |
1967 | memcpy((void *)&g_wlan.hif_func, &hif_spi, sizeof(wilc_hif_func_t)); | |
1968 | } else { | |
1969 | /* EIO 5 */ | |
1970 | ret = -5; | |
1971 | goto _fail_; | |
1972 | } | |
1973 | } | |
1974 | ||
1975 | /*** | |
1976 | * mac interface init | |
1977 | **/ | |
814bc368 | 1978 | if (!wilc_wlan_cfg_init(wilc_debug)) { |
c5c77ba1 JK |
1979 | /* ENOBUFS 105 */ |
1980 | ret = -105; | |
1981 | goto _fail_; | |
1982 | } | |
c5c77ba1 JK |
1983 | |
1984 | /** | |
1985 | * alloc tx, rx buffer | |
1986 | **/ | |
b1413b60 | 1987 | if (g_wlan.tx_buffer == NULL) |
7015b5db | 1988 | g_wlan.tx_buffer = kmalloc(LINUX_TX_SIZE, GFP_KERNEL); |
7a8fd841 | 1989 | PRINT_D(TX_DBG, "g_wlan.tx_buffer = %p\n", g_wlan.tx_buffer); |
c5c77ba1 | 1990 | |
b1413b60 | 1991 | if (g_wlan.tx_buffer == NULL) { |
c5c77ba1 JK |
1992 | /* ENOBUFS 105 */ |
1993 | ret = -105; | |
1994 | PRINT_ER("Can't allocate Tx Buffer"); | |
1995 | goto _fail_; | |
1996 | } | |
1997 | ||
1998 | /* rx_buffer is not used unless we activate USE_MEM STATIC which is not applicable, allocating such memory is useless*/ | |
1999 | #if defined (MEMORY_STATIC) | |
b1413b60 | 2000 | if (g_wlan.rx_buffer == NULL) |
03eb7266 | 2001 | g_wlan.rx_buffer = kmalloc(LINUX_RX_SIZE, GFP_KERNEL); |
7a8fd841 | 2002 | PRINT_D(TX_DBG, "g_wlan.rx_buffer =%p\n", g_wlan.rx_buffer); |
b1413b60 | 2003 | if (g_wlan.rx_buffer == NULL) { |
c5c77ba1 JK |
2004 | /* ENOBUFS 105 */ |
2005 | ret = -105; | |
2006 | PRINT_ER("Can't allocate Rx Buffer"); | |
2007 | goto _fail_; | |
2008 | } | |
2009 | #endif | |
2010 | ||
c5c77ba1 JK |
2011 | if (!init_chip()) { |
2012 | /* EIO 5 */ | |
2013 | ret = -5; | |
2014 | goto _fail_; | |
2015 | } | |
2016 | #ifdef TCP_ACK_FILTER | |
2017 | Init_TCP_tracking(); | |
2018 | #endif | |
2019 | ||
c5c77ba1 JK |
2020 | return 1; |
2021 | ||
2022 | _fail_: | |
2023 | ||
c5c77ba1 | 2024 | #ifdef MEMORY_STATIC |
a18dd630 GKH |
2025 | kfree(g_wlan.rx_buffer); |
2026 | g_wlan.rx_buffer = NULL; | |
c5c77ba1 | 2027 | #endif |
a18dd630 GKH |
2028 | kfree(g_wlan.tx_buffer); |
2029 | g_wlan.tx_buffer = NULL; | |
c5c77ba1 | 2030 | |
c5c77ba1 JK |
2031 | return ret; |
2032 | ||
2033 | } | |
2034 | ||
178c383f | 2035 | u16 Set_machw_change_vir_if(struct net_device *dev, bool bValue) |
c5c77ba1 | 2036 | { |
d85f5326 | 2037 | u16 ret; |
4e4467fd | 2038 | u32 reg; |
178c383f GL |
2039 | perInterface_wlan_t *nic; |
2040 | struct wilc *wilc; | |
2041 | ||
2042 | nic = netdev_priv(dev); | |
2043 | wilc = nic->wilc; | |
c5c77ba1 JK |
2044 | |
2045 | /*Reset WILC_CHANGING_VIR_IF register to allow adding futrue keys to CE H/W*/ | |
178c383f | 2046 | mutex_lock(&wilc->hif_cs); |
c5c77ba1 | 2047 | ret = (&g_wlan)->hif_func.hif_read_reg(WILC_CHANGING_VIR_IF, ®); |
39823a50 | 2048 | if (!ret) |
c5c77ba1 | 2049 | PRINT_ER("Error while Reading reg WILC_CHANGING_VIR_IF\n"); |
c5c77ba1 | 2050 | |
78174ada | 2051 | if (bValue) |
50b51dac | 2052 | reg |= BIT(31); |
78174ada | 2053 | else |
50b51dac | 2054 | reg &= ~BIT(31); |
c5c77ba1 JK |
2055 | |
2056 | ret = (&g_wlan)->hif_func.hif_write_reg(WILC_CHANGING_VIR_IF, reg); | |
2057 | ||
39823a50 | 2058 | if (!ret) |
c5c77ba1 | 2059 | PRINT_ER("Error while writing reg WILC_CHANGING_VIR_IF\n"); |
39823a50 | 2060 | |
178c383f | 2061 | mutex_unlock(&wilc->hif_cs); |
c5c77ba1 JK |
2062 | |
2063 | return ret; | |
2064 | } |