[mirror_ubuntu-artful-kernel.git] / drivers / staging / xgifb / XGIfb.h

#ifndef _LINUX_XGIFB
#define _LINUX_XGIFB
#include "vgatypes.h"
#include "vb_struct.h"

enum xgifb_display_type {
	XGIFB_DISP_NONE = 0,
	XGIFB_DISP_CRT,
	XGIFB_DISP_LCD,
	XGIFB_DISP_TV,
};

#define HASVB_NONE	    0x00
#define HASVB_301	    0x01
#define HASVB_LVDS	    0x02
#define HASVB_TRUMPION	    0x04
#define HASVB_LVDS_CHRONTEL 0x10
#define HASVB_302	    0x20
#define HASVB_CHRONTEL	    0x80

enum XGI_CHIP_TYPE {
	XG40 = 32,
	XG42,
	XG20 = 48,
	XG21,
	XG27,
};

enum xgi_tvtype {
	TVMODE_NTSC = 0,
	TVMODE_PAL,
	TVMODE_HIVISION,
	TVTYPE_PALM,
	TVTYPE_PALN,
	TVTYPE_NTSCJ,
	TVMODE_TOTAL
};

enum xgi_tv_plug {
	TVPLUG_UNKNOWN = 0,
	TVPLUG_COMPOSITE = 1,
	TVPLUG_SVIDEO = 2,
	TVPLUG_COMPOSITE_AND_SVIDEO = 3,
	TVPLUG_SCART = 4,
	TVPLUG_YPBPR_525i = 5,
	TVPLUG_YPBPR_525P = 6,
	TVPLUG_YPBPR_750P = 7,
	TVPLUG_YPBPR_1080i = 8,
	TVPLUG_TOTAL
};

struct xgifb_video_info {
	struct fb_info *fb_info;
	struct xgi_hw_device_info hw_info;
	struct vb_device_info dev_info;

	int mode_idx;
	int rate_idx;

	u32 pseudo_palette[17];

	int           chip_id;
	unsigned int  video_size;
	phys_addr_t   video_base;
	void __iomem *video_vbase;
	phys_addr_t   mmio_base;
	unsigned long mmio_size;
	void __iomem *mmio_vbase;
	unsigned long vga_base;
	int mtrr;

	int    video_bpp;
	int    video_cmap_len;
	int    video_width;
	int    video_height;
	int    video_vwidth;
	int    video_vheight;
	int    org_x;
	int    org_y;
	int    video_linelength;
	unsigned int refresh_rate;

	enum xgifb_display_type display2; /* the second display output type */
	bool display2_force;
	unsigned char hasVB;
	unsigned char TV_type;
	unsigned char TV_plug;

	struct XGI21_LVDSCapStruct lvds_data;

	enum XGI_CHIP_TYPE chip;
	unsigned char revision_id;

	unsigned short DstColor;
	unsigned long  XGI310_AccelDepth;
	unsigned long  CommandReg;

	unsigned int   pcibus;
	unsigned int   pcislot;
	unsigned int   pcifunc;

	unsigned short subsysvendor;
	unsigned short subsysdevice;

	char reserved[236];
};

#endif
Commit	Line	Data
d7636e0b	1	#ifndef _LINUX_XGIFB
d7636e0b	2	#define _LINUX_XGIFB
c62f2e46	3	#include "vgatypes.h"
b33704df	4	#include "vb_struct.h"
c62f2e46	5
289ea524 AK	6	enum xgifb_display_type {
	7	XGIFB_DISP_NONE = 0,
	8	XGIFB_DISP_CRT,
	9	XGIFB_DISP_LCD,
	10	XGIFB_DISP_TV,
	11	};
d7636e0b	12
a17379e7 KT	13	#define HASVB_NONE 0x00
	14	#define HASVB_301 0x01
	15	#define HASVB_LVDS 0x02
	16	#define HASVB_TRUMPION 0x04
	17	#define HASVB_LVDS_CHRONTEL 0x10
	18	#define HASVB_302 0x20
a17379e7	19	#define HASVB_CHRONTEL 0x80
d7636e0b	20
716083c6	21	enum XGI_CHIP_TYPE {
a17379e7	22	XG40 = 32,
a17379e7	23	XG42,
a17379e7 KT	24	XG20 = 48,
	25	XG21,
	26	XG27,
716083c6	27	};
d7636e0b	28
716083c6	29	enum xgi_tvtype {
d7636e0b	30	TVMODE_NTSC = 0,
	31	TVMODE_PAL,
	32	TVMODE_HIVISION,
949eb0ae MG	33	TVTYPE_PALM,
	34	TVTYPE_PALN,
	35	TVTYPE_NTSCJ,
d7636e0b	36	TVMODE_TOTAL
716083c6	37	};
d7636e0b	38
949eb0ae	39	enum xgi_tv_plug {
a17379e7 KT	40	TVPLUG_UNKNOWN = 0,
	41	TVPLUG_COMPOSITE = 1,
	42	TVPLUG_SVIDEO = 2,
	43	TVPLUG_COMPOSITE_AND_SVIDEO = 3,
	44	TVPLUG_SCART = 4,
	45	TVPLUG_YPBPR_525i = 5,
	46	TVPLUG_YPBPR_525P = 6,
	47	TVPLUG_YPBPR_750P = 7,
	48	TVPLUG_YPBPR_1080i = 8,
d7636e0b	49	TVPLUG_TOTAL
a3e735a5	50	};
d7636e0b	51
ab886ff8	52	struct xgifb_video_info {
19c1e88e	53	struct fb_info *fb_info;
c62f2e46	54	struct xgi_hw_device_info hw_info;
f2df8c09	55	struct vb_device_info dev_info;
19c1e88e	56
ccf265ad	57	int mode_idx;
5aa55d9f	58	int rate_idx;
ccf265ad	59
76cabaa4 AK	60	u32 pseudo_palette[17];
76cabaa4 AK	61
a17379e7 KT	62	int chip_id;
a17379e7 KT	63	unsigned int video_size;
f650caaa	64	phys_addr_t video_base;
c44fa627	65	void __iomem *video_vbase;
f650caaa	66	phys_addr_t mmio_base;
1b3909e5	67	unsigned long mmio_size;
863c02af	68	void __iomem *mmio_vbase;
a17379e7	69	unsigned long vga_base;
8cedcc70	70	int mtrr;
a17379e7 KT	71
	72	int video_bpp;
	73	int video_cmap_len;
	74	int video_width;
	75	int video_height;
	76	int video_vwidth;
	77	int video_vheight;
	78	int org_x;
	79	int org_y;
	80	int video_linelength;
	81	unsigned int refresh_rate;
	82
289ea524	83	enum xgifb_display_type display2; /* the second display output type */
25aa75f1	84	bool display2_force;
a17379e7 KT	85	unsigned char hasVB;
	86	unsigned char TV_type;
	87	unsigned char TV_plug;
d7636e0b	88
fab04b97 AK	89	struct XGI21_LVDSCapStruct lvds_data;
fab04b97 AK	90
716083c6	91	enum XGI_CHIP_TYPE chip;
a17379e7	92	unsigned char revision_id;
d7636e0b	93
a17379e7 KT	94	unsigned short DstColor;
	95	unsigned long XGI310_AccelDepth;
	96	unsigned long CommandReg;
d7636e0b	97
a17379e7 KT	98	unsigned int pcibus;
	99	unsigned int pcislot;
	100	unsigned int pcifunc;
d7636e0b	101
a17379e7 KT	102	unsigned short subsysvendor;
a17379e7 KT	103	unsigned short subsysdevice;
d7636e0b	104
a17379e7	105	char reserved[236];
d7636e0b	106	};
d7636e0b	107
d7636e0b	108	#endif