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bc40b5e3 SP |
1 | /* |
2 | * intel_soc_dts_thermal.c | |
3 | * Copyright (c) 2014, Intel Corporation. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms and conditions of the GNU General Public License, | |
7 | * version 2, as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | */ | |
15 | ||
16 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
17 | ||
18 | #include <linux/module.h> | |
bc40b5e3 | 19 | #include <linux/interrupt.h> |
bc40b5e3 | 20 | #include <asm/cpu_device_id.h> |
ce53da02 | 21 | #include <asm/intel-family.h> |
3a2419f8 | 22 | #include "intel_soc_dts_iosf.h" |
bc40b5e3 SP |
23 | |
24 | #define CRITICAL_OFFSET_FROM_TJ_MAX 5000 | |
25 | ||
bc40b5e3 SP |
26 | static int crit_offset = CRITICAL_OFFSET_FROM_TJ_MAX; |
27 | module_param(crit_offset, int, 0644); | |
28 | MODULE_PARM_DESC(crit_offset, | |
29 | "Critical Temperature offset from tj max in millidegree Celsius."); | |
30 | ||
3a2419f8 SP |
31 | /* IRQ 86 is a fixed APIC interrupt for BYT DTS Aux threshold notifications */ |
32 | #define BYT_SOC_DTS_APIC_IRQ 86 | |
bc40b5e3 | 33 | |
3a2419f8 SP |
34 | static int soc_dts_thres_irq; |
35 | static struct intel_soc_dts_sensors *soc_dts; | |
bc40b5e3 SP |
36 | |
37 | static irqreturn_t soc_irq_thread_fn(int irq, void *dev_data) | |
38 | { | |
bc40b5e3 | 39 | pr_debug("proc_thermal_interrupt\n"); |
3a2419f8 | 40 | intel_soc_dts_iosf_interrupt_handler(soc_dts); |
bc40b5e3 SP |
41 | |
42 | return IRQ_HANDLED; | |
43 | } | |
44 | ||
45 | static const struct x86_cpu_id soc_thermal_ids[] = { | |
ce53da02 DH |
46 | { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_SILVERMONT1, 0, |
47 | BYT_SOC_DTS_APIC_IRQ}, | |
bc40b5e3 SP |
48 | {} |
49 | }; | |
50 | MODULE_DEVICE_TABLE(x86cpu, soc_thermal_ids); | |
51 | ||
52 | static int __init intel_soc_thermal_init(void) | |
53 | { | |
bc40b5e3 | 54 | int err = 0; |
bc40b5e3 SP |
55 | const struct x86_cpu_id *match_cpu; |
56 | ||
57 | match_cpu = x86_match_cpu(soc_thermal_ids); | |
58 | if (!match_cpu) | |
59 | return -ENODEV; | |
60 | ||
3a2419f8 SP |
61 | /* Create a zone with 2 trips with marked as read only */ |
62 | soc_dts = intel_soc_dts_iosf_init(INTEL_SOC_DTS_INTERRUPT_APIC, 2, 1); | |
63 | if (IS_ERR(soc_dts)) { | |
64 | err = PTR_ERR(soc_dts); | |
65 | return err; | |
bc40b5e3 SP |
66 | } |
67 | ||
3a2419f8 | 68 | soc_dts_thres_irq = (int)match_cpu->driver_data; |
bc40b5e3 | 69 | |
6c355faf SP |
70 | if (soc_dts_thres_irq) { |
71 | err = request_threaded_irq(soc_dts_thres_irq, NULL, | |
72 | soc_irq_thread_fn, | |
73 | IRQF_TRIGGER_RISING | IRQF_ONESHOT, | |
74 | "soc_dts", soc_dts); | |
75 | if (err) { | |
76 | pr_err("request_threaded_irq ret %d\n", err); | |
3a2419f8 | 77 | goto error_irq; |
6c355faf | 78 | } |
bc40b5e3 SP |
79 | } |
80 | ||
3a2419f8 SP |
81 | err = intel_soc_dts_iosf_add_read_only_critical_trip(soc_dts, |
82 | crit_offset); | |
83 | if (err) | |
84 | goto error_trips; | |
bc40b5e3 SP |
85 | |
86 | return 0; | |
87 | ||
3a2419f8 | 88 | error_trips: |
6c355faf SP |
89 | if (soc_dts_thres_irq) |
90 | free_irq(soc_dts_thres_irq, soc_dts); | |
3a2419f8 SP |
91 | error_irq: |
92 | intel_soc_dts_iosf_exit(soc_dts); | |
bc40b5e3 SP |
93 | |
94 | return err; | |
95 | } | |
96 | ||
97 | static void __exit intel_soc_thermal_exit(void) | |
98 | { | |
6c355faf SP |
99 | if (soc_dts_thres_irq) |
100 | free_irq(soc_dts_thres_irq, soc_dts); | |
3a2419f8 | 101 | intel_soc_dts_iosf_exit(soc_dts); |
bc40b5e3 SP |
102 | } |
103 | ||
104 | module_init(intel_soc_thermal_init) | |
105 | module_exit(intel_soc_thermal_exit) | |
106 | ||
107 | MODULE_DESCRIPTION("Intel SoC DTS Thermal Driver"); | |
108 | MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); | |
109 | MODULE_LICENSE("GPL v2"); |