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a92db1c8 SH |
1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * Author: Hanyi Wu <hanyi.wu@mediatek.com> | |
4 | * Sascha Hauer <s.hauer@pengutronix.de> | |
b7cf0053 | 5 | * Dawei Chien <dawei.chien@mediatek.com> |
6cf7f002 | 6 | * Louis Yu <louis.yu@mediatek.com> |
a92db1c8 SH |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/clk.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/nvmem-consumer.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_address.h> | |
b7cf0053 | 26 | #include <linux/of_device.h> |
a92db1c8 SH |
27 | #include <linux/platform_device.h> |
28 | #include <linux/slab.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/thermal.h> | |
31 | #include <linux/reset.h> | |
32 | #include <linux/types.h> | |
a92db1c8 SH |
33 | |
34 | /* AUXADC Registers */ | |
35 | #define AUXADC_CON0_V 0x000 | |
36 | #define AUXADC_CON1_V 0x004 | |
37 | #define AUXADC_CON1_SET_V 0x008 | |
38 | #define AUXADC_CON1_CLR_V 0x00c | |
39 | #define AUXADC_CON2_V 0x010 | |
40 | #define AUXADC_DATA(channel) (0x14 + (channel) * 4) | |
41 | #define AUXADC_MISC_V 0x094 | |
42 | ||
43 | #define AUXADC_CON1_CHANNEL(x) BIT(x) | |
44 | ||
45 | #define APMIXED_SYS_TS_CON1 0x604 | |
46 | ||
47 | /* Thermal Controller Registers */ | |
48 | #define TEMP_MONCTL0 0x000 | |
49 | #define TEMP_MONCTL1 0x004 | |
50 | #define TEMP_MONCTL2 0x008 | |
51 | #define TEMP_MONIDET0 0x014 | |
52 | #define TEMP_MONIDET1 0x018 | |
53 | #define TEMP_MSRCTL0 0x038 | |
54 | #define TEMP_AHBPOLL 0x040 | |
55 | #define TEMP_AHBTO 0x044 | |
56 | #define TEMP_ADCPNP0 0x048 | |
57 | #define TEMP_ADCPNP1 0x04c | |
58 | #define TEMP_ADCPNP2 0x050 | |
59 | #define TEMP_ADCPNP3 0x0b4 | |
60 | ||
61 | #define TEMP_ADCMUX 0x054 | |
62 | #define TEMP_ADCEN 0x060 | |
63 | #define TEMP_PNPMUXADDR 0x064 | |
64 | #define TEMP_ADCMUXADDR 0x068 | |
65 | #define TEMP_ADCENADDR 0x074 | |
66 | #define TEMP_ADCVALIDADDR 0x078 | |
67 | #define TEMP_ADCVOLTADDR 0x07c | |
68 | #define TEMP_RDCTRL 0x080 | |
69 | #define TEMP_ADCVALIDMASK 0x084 | |
70 | #define TEMP_ADCVOLTAGESHIFT 0x088 | |
71 | #define TEMP_ADCWRITECTRL 0x08c | |
72 | #define TEMP_MSR0 0x090 | |
73 | #define TEMP_MSR1 0x094 | |
74 | #define TEMP_MSR2 0x098 | |
75 | #define TEMP_MSR3 0x0B8 | |
76 | ||
77 | #define TEMP_SPARE0 0x0f0 | |
78 | ||
79 | #define PTPCORESEL 0x400 | |
80 | ||
81 | #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) | |
82 | ||
eb4fc33e | 83 | #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) |
a92db1c8 SH |
84 | #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) |
85 | ||
86 | #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) | |
87 | ||
88 | #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) | |
89 | #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) | |
90 | ||
91 | #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) | |
92 | #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) | |
93 | ||
b7cf0053 | 94 | /* MT8173 thermal sensors */ |
a92db1c8 SH |
95 | #define MT8173_TS1 0 |
96 | #define MT8173_TS2 1 | |
97 | #define MT8173_TS3 2 | |
98 | #define MT8173_TS4 3 | |
99 | #define MT8173_TSABB 4 | |
100 | ||
101 | /* AUXADC channel 11 is used for the temperature sensors */ | |
102 | #define MT8173_TEMP_AUXADC_CHANNEL 11 | |
103 | ||
104 | /* The total number of temperature sensors in the MT8173 */ | |
105 | #define MT8173_NUM_SENSORS 5 | |
106 | ||
107 | /* The number of banks in the MT8173 */ | |
108 | #define MT8173_NUM_ZONES 4 | |
109 | ||
110 | /* The number of sensing points per bank */ | |
111 | #define MT8173_NUM_SENSORS_PER_ZONE 4 | |
112 | ||
b7cf0053 | 113 | /* |
114 | * Layout of the fuses providing the calibration data | |
0a068993 LY |
115 | * These macros could be used for MT8173, MT2701, and MT2712. |
116 | * MT8173 has 5 sensors and needs 5 VTS calibration data. | |
117 | * MT2701 has 3 sensors and needs 3 VTS calibration data. | |
118 | * MT2712 has 4 sensors and needs 4 VTS calibration data. | |
b7cf0053 | 119 | */ |
eb4fc33e EV |
120 | #define MT8173_CALIB_BUF0_VALID BIT(0) |
121 | #define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff) | |
122 | #define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff) | |
123 | #define MT8173_CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff) | |
124 | #define MT8173_CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff) | |
125 | #define MT8173_CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff) | |
126 | #define MT8173_CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff) | |
127 | #define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f) | |
128 | #define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f) | |
0a068993 LY |
129 | #define MT8173_CALIB_BUF0_O_SLOPE_SIGN(x) (((x) >> 7) & 0x1) |
130 | #define MT8173_CALIB_BUF1_ID(x) (((x) >> 9) & 0x1) | |
a92db1c8 | 131 | |
b7cf0053 | 132 | /* MT2701 thermal sensors */ |
133 | #define MT2701_TS1 0 | |
134 | #define MT2701_TS2 1 | |
135 | #define MT2701_TSABB 2 | |
136 | ||
137 | /* AUXADC channel 11 is used for the temperature sensors */ | |
138 | #define MT2701_TEMP_AUXADC_CHANNEL 11 | |
139 | ||
140 | /* The total number of temperature sensors in the MT2701 */ | |
141 | #define MT2701_NUM_SENSORS 3 | |
142 | ||
b7cf0053 | 143 | /* The number of sensing points per bank */ |
144 | #define MT2701_NUM_SENSORS_PER_ZONE 3 | |
145 | ||
6cf7f002 LY |
146 | /* MT2712 thermal sensors */ |
147 | #define MT2712_TS1 0 | |
148 | #define MT2712_TS2 1 | |
149 | #define MT2712_TS3 2 | |
150 | #define MT2712_TS4 3 | |
151 | ||
152 | /* AUXADC channel 11 is used for the temperature sensors */ | |
153 | #define MT2712_TEMP_AUXADC_CHANNEL 11 | |
154 | ||
155 | /* The total number of temperature sensors in the MT2712 */ | |
156 | #define MT2712_NUM_SENSORS 4 | |
157 | ||
158 | /* The number of sensing points per bank */ | |
159 | #define MT2712_NUM_SENSORS_PER_ZONE 4 | |
160 | ||
161 | #define THERMAL_NAME "mtk-thermal" | |
162 | ||
a92db1c8 SH |
163 | struct mtk_thermal; |
164 | ||
b7cf0053 | 165 | struct thermal_bank_cfg { |
166 | unsigned int num_sensors; | |
167 | const int *sensors; | |
168 | }; | |
169 | ||
a92db1c8 SH |
170 | struct mtk_thermal_bank { |
171 | struct mtk_thermal *mt; | |
172 | int id; | |
173 | }; | |
174 | ||
b7cf0053 | 175 | struct mtk_thermal_data { |
176 | s32 num_banks; | |
177 | s32 num_sensors; | |
178 | s32 auxadc_channel; | |
179 | const int *sensor_mux_values; | |
180 | const int *msr; | |
181 | const int *adcpnp; | |
182 | struct thermal_bank_cfg bank_data[]; | |
183 | }; | |
184 | ||
a92db1c8 SH |
185 | struct mtk_thermal { |
186 | struct device *dev; | |
187 | void __iomem *thermal_base; | |
188 | ||
189 | struct clk *clk_peri_therm; | |
190 | struct clk *clk_auxadc; | |
eb4fc33e | 191 | /* lock: for getting and putting banks */ |
a92db1c8 SH |
192 | struct mutex lock; |
193 | ||
194 | /* Calibration values */ | |
195 | s32 adc_ge; | |
196 | s32 degc_cali; | |
197 | s32 o_slope; | |
198 | s32 vts[MT8173_NUM_SENSORS]; | |
199 | ||
b7cf0053 | 200 | const struct mtk_thermal_data *conf; |
201 | struct mtk_thermal_bank banks[]; | |
a92db1c8 SH |
202 | }; |
203 | ||
b7cf0053 | 204 | /* MT8173 thermal sensor data */ |
992edf39 | 205 | static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { |
b7cf0053 | 206 | { MT8173_TS2, MT8173_TS3 }, |
207 | { MT8173_TS2, MT8173_TS4 }, | |
208 | { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, | |
209 | { MT8173_TS2 }, | |
a92db1c8 SH |
210 | }; |
211 | ||
992edf39 | 212 | static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { |
05d7839a | 213 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 |
b7cf0053 | 214 | }; |
a92db1c8 | 215 | |
992edf39 | 216 | static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 217 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 |
218 | }; | |
219 | ||
992edf39 | 220 | static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; |
b7cf0053 | 221 | |
222 | /* MT2701 thermal sensor data */ | |
992edf39 | 223 | static const int mt2701_bank_data[MT2701_NUM_SENSORS] = { |
b7cf0053 | 224 | MT2701_TS1, MT2701_TS2, MT2701_TSABB |
225 | }; | |
226 | ||
992edf39 | 227 | static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 228 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 |
229 | }; | |
230 | ||
992edf39 | 231 | static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 232 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 |
233 | }; | |
234 | ||
992edf39 | 235 | static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; |
b7cf0053 | 236 | |
6cf7f002 LY |
237 | /* MT2712 thermal sensor data */ |
238 | static const int mt2712_bank_data[MT2712_NUM_SENSORS] = { | |
239 | MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4 | |
240 | }; | |
241 | ||
242 | static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = { | |
243 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 | |
244 | }; | |
245 | ||
246 | static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = { | |
247 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 | |
248 | }; | |
249 | ||
250 | static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; | |
251 | ||
b7cf0053 | 252 | /** |
a92db1c8 SH |
253 | * The MT8173 thermal controller has four banks. Each bank can read up to |
254 | * four temperature sensors simultaneously. The MT8173 has a total of 5 | |
255 | * temperature sensors. We use each bank to measure a certain area of the | |
256 | * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple | |
257 | * areas, hence is used in different banks. | |
258 | * | |
259 | * The thermal core only gets the maximum temperature of all banks, so | |
260 | * the bank concept wouldn't be necessary here. However, the SVS (Smart | |
261 | * Voltage Scaling) unit makes its decisions based on the same bank | |
262 | * data, and this indeed needs the temperatures of the individual banks | |
263 | * for making better decisions. | |
264 | */ | |
b7cf0053 | 265 | static const struct mtk_thermal_data mt8173_thermal_data = { |
266 | .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, | |
267 | .num_banks = MT8173_NUM_ZONES, | |
268 | .num_sensors = MT8173_NUM_SENSORS, | |
269 | .bank_data = { | |
270 | { | |
271 | .num_sensors = 2, | |
272 | .sensors = mt8173_bank_data[0], | |
273 | }, { | |
274 | .num_sensors = 2, | |
275 | .sensors = mt8173_bank_data[1], | |
276 | }, { | |
277 | .num_sensors = 3, | |
278 | .sensors = mt8173_bank_data[2], | |
279 | }, { | |
280 | .num_sensors = 1, | |
281 | .sensors = mt8173_bank_data[3], | |
282 | }, | |
a92db1c8 | 283 | }, |
b7cf0053 | 284 | .msr = mt8173_msr, |
285 | .adcpnp = mt8173_adcpnp, | |
286 | .sensor_mux_values = mt8173_mux_values, | |
a92db1c8 SH |
287 | }; |
288 | ||
b7cf0053 | 289 | /** |
290 | * The MT2701 thermal controller has one bank, which can read up to | |
291 | * three temperature sensors simultaneously. The MT2701 has a total of 3 | |
292 | * temperature sensors. | |
293 | * | |
294 | * The thermal core only gets the maximum temperature of this one bank, | |
295 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart | |
296 | * Voltage Scaling) unit makes its decisions based on the same bank | |
297 | * data. | |
298 | */ | |
299 | static const struct mtk_thermal_data mt2701_thermal_data = { | |
300 | .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, | |
301 | .num_banks = 1, | |
302 | .num_sensors = MT2701_NUM_SENSORS, | |
303 | .bank_data = { | |
304 | { | |
305 | .num_sensors = 3, | |
306 | .sensors = mt2701_bank_data, | |
307 | }, | |
a92db1c8 | 308 | }, |
b7cf0053 | 309 | .msr = mt2701_msr, |
310 | .adcpnp = mt2701_adcpnp, | |
311 | .sensor_mux_values = mt2701_mux_values, | |
a92db1c8 SH |
312 | }; |
313 | ||
6cf7f002 LY |
314 | /** |
315 | * The MT2712 thermal controller has one bank, which can read up to | |
316 | * four temperature sensors simultaneously. The MT2712 has a total of 4 | |
317 | * temperature sensors. | |
318 | * | |
319 | * The thermal core only gets the maximum temperature of this one bank, | |
320 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart | |
321 | * Voltage Scaling) unit makes its decisions based on the same bank | |
322 | * data. | |
323 | */ | |
324 | static const struct mtk_thermal_data mt2712_thermal_data = { | |
325 | .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL, | |
326 | .num_banks = 1, | |
327 | .num_sensors = MT2712_NUM_SENSORS, | |
328 | .bank_data = { | |
329 | { | |
330 | .num_sensors = 4, | |
331 | .sensors = mt2712_bank_data, | |
332 | }, | |
333 | }, | |
334 | .msr = mt2712_msr, | |
335 | .adcpnp = mt2712_adcpnp, | |
336 | .sensor_mux_values = mt2712_mux_values, | |
337 | }; | |
338 | ||
a92db1c8 SH |
339 | /** |
340 | * raw_to_mcelsius - convert a raw ADC value to mcelsius | |
341 | * @mt: The thermal controller | |
342 | * @raw: raw ADC value | |
343 | * | |
344 | * This converts the raw ADC value to mcelsius using the SoC specific | |
345 | * calibration constants | |
346 | */ | |
347 | static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) | |
348 | { | |
349 | s32 tmp; | |
350 | ||
351 | raw &= 0xfff; | |
352 | ||
353 | tmp = 203450520 << 3; | |
354 | tmp /= 165 + mt->o_slope; | |
355 | tmp /= 10000 + mt->adc_ge; | |
356 | tmp *= raw - mt->vts[sensno] - 3350; | |
357 | tmp >>= 3; | |
358 | ||
359 | return mt->degc_cali * 500 - tmp; | |
360 | } | |
361 | ||
362 | /** | |
363 | * mtk_thermal_get_bank - get bank | |
364 | * @bank: The bank | |
365 | * | |
366 | * The bank registers are banked, we have to select a bank in the | |
367 | * PTPCORESEL register to access it. | |
368 | */ | |
369 | static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) | |
370 | { | |
371 | struct mtk_thermal *mt = bank->mt; | |
372 | u32 val; | |
373 | ||
374 | mutex_lock(&mt->lock); | |
375 | ||
376 | val = readl(mt->thermal_base + PTPCORESEL); | |
377 | val &= ~0xf; | |
378 | val |= bank->id; | |
379 | writel(val, mt->thermal_base + PTPCORESEL); | |
380 | } | |
381 | ||
382 | /** | |
383 | * mtk_thermal_put_bank - release bank | |
384 | * @bank: The bank | |
385 | * | |
386 | * release a bank previously taken with mtk_thermal_get_bank, | |
387 | */ | |
388 | static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) | |
389 | { | |
390 | struct mtk_thermal *mt = bank->mt; | |
391 | ||
392 | mutex_unlock(&mt->lock); | |
393 | } | |
394 | ||
395 | /** | |
396 | * mtk_thermal_bank_temperature - get the temperature of a bank | |
397 | * @bank: The bank | |
398 | * | |
399 | * The temperature of a bank is considered the maximum temperature of | |
400 | * the sensors associated to the bank. | |
401 | */ | |
402 | static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) | |
403 | { | |
404 | struct mtk_thermal *mt = bank->mt; | |
b7cf0053 | 405 | const struct mtk_thermal_data *conf = mt->conf; |
eb4fc33e | 406 | int i, temp = INT_MIN, max = INT_MIN; |
a92db1c8 SH |
407 | u32 raw; |
408 | ||
b7cf0053 | 409 | for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { |
5e1b2fad MK |
410 | raw = readl(mt->thermal_base + |
411 | conf->msr[conf->bank_data[bank->id].sensors[i]]); | |
a92db1c8 | 412 | |
b7cf0053 | 413 | temp = raw_to_mcelsius(mt, |
414 | conf->bank_data[bank->id].sensors[i], | |
415 | raw); | |
a92db1c8 SH |
416 | |
417 | /* | |
418 | * The first read of a sensor often contains very high bogus | |
419 | * temperature value. Filter these out so that the system does | |
420 | * not immediately shut down. | |
421 | */ | |
422 | if (temp > 200000) | |
423 | temp = 0; | |
424 | ||
425 | if (temp > max) | |
426 | max = temp; | |
427 | } | |
428 | ||
429 | return max; | |
430 | } | |
431 | ||
432 | static int mtk_read_temp(void *data, int *temperature) | |
433 | { | |
434 | struct mtk_thermal *mt = data; | |
435 | int i; | |
436 | int tempmax = INT_MIN; | |
437 | ||
b7cf0053 | 438 | for (i = 0; i < mt->conf->num_banks; i++) { |
a92db1c8 SH |
439 | struct mtk_thermal_bank *bank = &mt->banks[i]; |
440 | ||
441 | mtk_thermal_get_bank(bank); | |
442 | ||
443 | tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); | |
444 | ||
445 | mtk_thermal_put_bank(bank); | |
446 | } | |
447 | ||
448 | *temperature = tempmax; | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | static const struct thermal_zone_of_device_ops mtk_thermal_ops = { | |
454 | .get_temp = mtk_read_temp, | |
455 | }; | |
456 | ||
457 | static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, | |
eb4fc33e | 458 | u32 apmixed_phys_base, u32 auxadc_phys_base) |
a92db1c8 SH |
459 | { |
460 | struct mtk_thermal_bank *bank = &mt->banks[num]; | |
b7cf0053 | 461 | const struct mtk_thermal_data *conf = mt->conf; |
a92db1c8 SH |
462 | int i; |
463 | ||
464 | bank->id = num; | |
465 | bank->mt = mt; | |
466 | ||
467 | mtk_thermal_get_bank(bank); | |
468 | ||
469 | /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ | |
470 | writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); | |
471 | ||
472 | /* | |
473 | * filt interval is 1 * 46.540us = 46.54us, | |
474 | * sen interval is 429 * 46.540us = 19.96ms | |
475 | */ | |
476 | writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | | |
477 | TEMP_MONCTL2_SENSOR_INTERVAL(429), | |
478 | mt->thermal_base + TEMP_MONCTL2); | |
479 | ||
480 | /* poll is set to 10u */ | |
481 | writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), | |
eb4fc33e | 482 | mt->thermal_base + TEMP_AHBPOLL); |
a92db1c8 SH |
483 | |
484 | /* temperature sampling control, 1 sample */ | |
485 | writel(0x0, mt->thermal_base + TEMP_MSRCTL0); | |
486 | ||
487 | /* exceed this polling time, IRQ would be inserted */ | |
488 | writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); | |
489 | ||
490 | /* number of interrupts per event, 1 is enough */ | |
491 | writel(0x0, mt->thermal_base + TEMP_MONIDET0); | |
492 | writel(0x0, mt->thermal_base + TEMP_MONIDET1); | |
493 | ||
494 | /* | |
495 | * The MT8173 thermal controller does not have its own ADC. Instead it | |
496 | * uses AHB bus accesses to control the AUXADC. To do this the thermal | |
497 | * controller has to be programmed with the physical addresses of the | |
498 | * AUXADC registers and with the various bit positions in the AUXADC. | |
499 | * Also the thermal controller controls a mux in the APMIXEDSYS register | |
500 | * space. | |
501 | */ | |
502 | ||
503 | /* | |
504 | * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) | |
505 | * automatically by hw | |
506 | */ | |
b7cf0053 | 507 | writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCMUX); |
a92db1c8 SH |
508 | |
509 | /* AHB address for auxadc mux selection */ | |
510 | writel(auxadc_phys_base + AUXADC_CON1_CLR_V, | |
eb4fc33e | 511 | mt->thermal_base + TEMP_ADCMUXADDR); |
a92db1c8 SH |
512 | |
513 | /* AHB address for pnp sensor mux selection */ | |
514 | writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, | |
eb4fc33e | 515 | mt->thermal_base + TEMP_PNPMUXADDR); |
a92db1c8 SH |
516 | |
517 | /* AHB value for auxadc enable */ | |
b7cf0053 | 518 | writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCEN); |
a92db1c8 SH |
519 | |
520 | /* AHB address for auxadc enable (channel 0 immediate mode selected) */ | |
521 | writel(auxadc_phys_base + AUXADC_CON1_SET_V, | |
eb4fc33e | 522 | mt->thermal_base + TEMP_ADCENADDR); |
a92db1c8 SH |
523 | |
524 | /* AHB address for auxadc valid bit */ | |
b7cf0053 | 525 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
eb4fc33e | 526 | mt->thermal_base + TEMP_ADCVALIDADDR); |
a92db1c8 SH |
527 | |
528 | /* AHB address for auxadc voltage output */ | |
b7cf0053 | 529 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
eb4fc33e | 530 | mt->thermal_base + TEMP_ADCVOLTADDR); |
a92db1c8 SH |
531 | |
532 | /* read valid & voltage are at the same register */ | |
533 | writel(0x0, mt->thermal_base + TEMP_RDCTRL); | |
534 | ||
535 | /* indicate where the valid bit is */ | |
536 | writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), | |
eb4fc33e | 537 | mt->thermal_base + TEMP_ADCVALIDMASK); |
a92db1c8 SH |
538 | |
539 | /* no shift */ | |
540 | writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); | |
541 | ||
542 | /* enable auxadc mux write transaction */ | |
543 | writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
eb4fc33e | 544 | mt->thermal_base + TEMP_ADCWRITECTRL); |
a92db1c8 | 545 | |
b7cf0053 | 546 | for (i = 0; i < conf->bank_data[num].num_sensors; i++) |
547 | writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], | |
5e1b2fad MK |
548 | mt->thermal_base + |
549 | conf->adcpnp[conf->bank_data[num].sensors[i]]); | |
a92db1c8 | 550 | |
b7cf0053 | 551 | writel((1 << conf->bank_data[num].num_sensors) - 1, |
552 | mt->thermal_base + TEMP_MONCTL0); | |
a92db1c8 | 553 | |
eb4fc33e EV |
554 | writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | |
555 | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
556 | mt->thermal_base + TEMP_ADCWRITECTRL); | |
a92db1c8 SH |
557 | |
558 | mtk_thermal_put_bank(bank); | |
559 | } | |
560 | ||
561 | static u64 of_get_phys_base(struct device_node *np) | |
562 | { | |
563 | u64 size64; | |
564 | const __be32 *regaddr_p; | |
565 | ||
566 | regaddr_p = of_get_address(np, 0, &size64, NULL); | |
567 | if (!regaddr_p) | |
568 | return OF_BAD_ADDR; | |
569 | ||
570 | return of_translate_address(np, regaddr_p); | |
571 | } | |
572 | ||
eb4fc33e EV |
573 | static int mtk_thermal_get_calibration_data(struct device *dev, |
574 | struct mtk_thermal *mt) | |
a92db1c8 SH |
575 | { |
576 | struct nvmem_cell *cell; | |
577 | u32 *buf; | |
578 | size_t len; | |
579 | int i, ret = 0; | |
580 | ||
581 | /* Start with default values */ | |
582 | mt->adc_ge = 512; | |
b7cf0053 | 583 | for (i = 0; i < mt->conf->num_sensors; i++) |
a92db1c8 SH |
584 | mt->vts[i] = 260; |
585 | mt->degc_cali = 40; | |
586 | mt->o_slope = 0; | |
587 | ||
588 | cell = nvmem_cell_get(dev, "calibration-data"); | |
589 | if (IS_ERR(cell)) { | |
590 | if (PTR_ERR(cell) == -EPROBE_DEFER) | |
591 | return PTR_ERR(cell); | |
592 | return 0; | |
593 | } | |
594 | ||
595 | buf = (u32 *)nvmem_cell_read(cell, &len); | |
596 | ||
597 | nvmem_cell_put(cell); | |
598 | ||
599 | if (IS_ERR(buf)) | |
600 | return PTR_ERR(buf); | |
601 | ||
602 | if (len < 3 * sizeof(u32)) { | |
603 | dev_warn(dev, "invalid calibration data\n"); | |
604 | ret = -EINVAL; | |
605 | goto out; | |
606 | } | |
607 | ||
608 | if (buf[0] & MT8173_CALIB_BUF0_VALID) { | |
609 | mt->adc_ge = MT8173_CALIB_BUF1_ADC_GE(buf[1]); | |
610 | mt->vts[MT8173_TS1] = MT8173_CALIB_BUF0_VTS_TS1(buf[0]); | |
611 | mt->vts[MT8173_TS2] = MT8173_CALIB_BUF0_VTS_TS2(buf[0]); | |
612 | mt->vts[MT8173_TS3] = MT8173_CALIB_BUF1_VTS_TS3(buf[1]); | |
613 | mt->vts[MT8173_TS4] = MT8173_CALIB_BUF2_VTS_TS4(buf[2]); | |
614 | mt->vts[MT8173_TSABB] = MT8173_CALIB_BUF2_VTS_TSABB(buf[2]); | |
615 | mt->degc_cali = MT8173_CALIB_BUF0_DEGC_CALI(buf[0]); | |
0a068993 LY |
616 | if (MT8173_CALIB_BUF1_ID(buf[1]) & |
617 | MT8173_CALIB_BUF0_O_SLOPE_SIGN(buf[0])) | |
618 | mt->o_slope = -MT8173_CALIB_BUF0_O_SLOPE(buf[0]); | |
619 | else | |
620 | mt->o_slope = MT8173_CALIB_BUF0_O_SLOPE(buf[0]); | |
a92db1c8 SH |
621 | } else { |
622 | dev_info(dev, "Device not calibrated, using default calibration values\n"); | |
623 | } | |
624 | ||
625 | out: | |
626 | kfree(buf); | |
627 | ||
628 | return ret; | |
629 | } | |
630 | ||
b7cf0053 | 631 | static const struct of_device_id mtk_thermal_of_match[] = { |
632 | { | |
633 | .compatible = "mediatek,mt8173-thermal", | |
634 | .data = (void *)&mt8173_thermal_data, | |
635 | }, | |
636 | { | |
637 | .compatible = "mediatek,mt2701-thermal", | |
638 | .data = (void *)&mt2701_thermal_data, | |
6cf7f002 LY |
639 | }, |
640 | { | |
641 | .compatible = "mediatek,mt2712-thermal", | |
642 | .data = (void *)&mt2712_thermal_data, | |
b7cf0053 | 643 | }, { |
644 | }, | |
645 | }; | |
646 | MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); | |
647 | ||
a92db1c8 SH |
648 | static int mtk_thermal_probe(struct platform_device *pdev) |
649 | { | |
650 | int ret, i; | |
651 | struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; | |
652 | struct mtk_thermal *mt; | |
653 | struct resource *res; | |
b7cf0053 | 654 | const struct of_device_id *of_id; |
a92db1c8 | 655 | u64 auxadc_phys_base, apmixed_phys_base; |
1f6b0889 | 656 | struct thermal_zone_device *tzdev; |
a92db1c8 SH |
657 | |
658 | mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); | |
659 | if (!mt) | |
660 | return -ENOMEM; | |
661 | ||
b7cf0053 | 662 | of_id = of_match_device(mtk_thermal_of_match, &pdev->dev); |
663 | if (of_id) | |
664 | mt->conf = (const struct mtk_thermal_data *)of_id->data; | |
665 | ||
a92db1c8 SH |
666 | mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); |
667 | if (IS_ERR(mt->clk_peri_therm)) | |
668 | return PTR_ERR(mt->clk_peri_therm); | |
669 | ||
670 | mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); | |
671 | if (IS_ERR(mt->clk_auxadc)) | |
672 | return PTR_ERR(mt->clk_auxadc); | |
673 | ||
674 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
675 | mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); | |
676 | if (IS_ERR(mt->thermal_base)) | |
677 | return PTR_ERR(mt->thermal_base); | |
678 | ||
679 | ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); | |
680 | if (ret) | |
681 | return ret; | |
682 | ||
683 | mutex_init(&mt->lock); | |
684 | ||
685 | mt->dev = &pdev->dev; | |
686 | ||
687 | auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); | |
688 | if (!auxadc) { | |
689 | dev_err(&pdev->dev, "missing auxadc node\n"); | |
690 | return -ENODEV; | |
691 | } | |
692 | ||
693 | auxadc_phys_base = of_get_phys_base(auxadc); | |
694 | ||
695 | of_node_put(auxadc); | |
696 | ||
697 | if (auxadc_phys_base == OF_BAD_ADDR) { | |
698 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
699 | return -EINVAL; | |
700 | } | |
701 | ||
702 | apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); | |
703 | if (!apmixedsys) { | |
704 | dev_err(&pdev->dev, "missing apmixedsys node\n"); | |
705 | return -ENODEV; | |
706 | } | |
707 | ||
708 | apmixed_phys_base = of_get_phys_base(apmixedsys); | |
709 | ||
710 | of_node_put(apmixedsys); | |
711 | ||
712 | if (apmixed_phys_base == OF_BAD_ADDR) { | |
713 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
714 | return -EINVAL; | |
715 | } | |
716 | ||
6760f3f7 LY |
717 | ret = device_reset(&pdev->dev); |
718 | if (ret) | |
719 | return ret; | |
720 | ||
a92db1c8 SH |
721 | ret = clk_prepare_enable(mt->clk_auxadc); |
722 | if (ret) { | |
723 | dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); | |
724 | return ret; | |
725 | } | |
726 | ||
a92db1c8 SH |
727 | ret = clk_prepare_enable(mt->clk_peri_therm); |
728 | if (ret) { | |
729 | dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); | |
730 | goto err_disable_clk_auxadc; | |
731 | } | |
732 | ||
b7cf0053 | 733 | for (i = 0; i < mt->conf->num_banks; i++) |
eb4fc33e EV |
734 | mtk_thermal_init_bank(mt, i, apmixed_phys_base, |
735 | auxadc_phys_base); | |
a92db1c8 SH |
736 | |
737 | platform_set_drvdata(pdev, mt); | |
738 | ||
1f6b0889 AL |
739 | tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt, |
740 | &mtk_thermal_ops); | |
741 | if (IS_ERR(tzdev)) { | |
742 | ret = PTR_ERR(tzdev); | |
743 | goto err_disable_clk_peri_therm; | |
744 | } | |
a92db1c8 SH |
745 | |
746 | return 0; | |
747 | ||
1f6b0889 AL |
748 | err_disable_clk_peri_therm: |
749 | clk_disable_unprepare(mt->clk_peri_therm); | |
a92db1c8 SH |
750 | err_disable_clk_auxadc: |
751 | clk_disable_unprepare(mt->clk_auxadc); | |
752 | ||
753 | return ret; | |
754 | } | |
755 | ||
756 | static int mtk_thermal_remove(struct platform_device *pdev) | |
757 | { | |
758 | struct mtk_thermal *mt = platform_get_drvdata(pdev); | |
759 | ||
a92db1c8 SH |
760 | clk_disable_unprepare(mt->clk_peri_therm); |
761 | clk_disable_unprepare(mt->clk_auxadc); | |
762 | ||
763 | return 0; | |
764 | } | |
765 | ||
a92db1c8 SH |
766 | static struct platform_driver mtk_thermal_driver = { |
767 | .probe = mtk_thermal_probe, | |
768 | .remove = mtk_thermal_remove, | |
769 | .driver = { | |
770 | .name = THERMAL_NAME, | |
771 | .of_match_table = mtk_thermal_of_match, | |
772 | }, | |
773 | }; | |
774 | ||
775 | module_platform_driver(mtk_thermal_driver); | |
776 | ||
6cf7f002 | 777 | MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>"); |
b7cf0053 | 778 | MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>"); |
9ebfb4e0 | 779 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
a92db1c8 SH |
780 | MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); |
781 | MODULE_DESCRIPTION("Mediatek thermal driver"); | |
782 | MODULE_LICENSE("GPL v2"); |