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a92db1c8 SH |
1 | /* |
2 | * Copyright (c) 2015 MediaTek Inc. | |
3 | * Author: Hanyi Wu <hanyi.wu@mediatek.com> | |
4 | * Sascha Hauer <s.hauer@pengutronix.de> | |
b7cf0053 | 5 | * Dawei Chien <dawei.chien@mediatek.com> |
6cf7f002 | 6 | * Louis Yu <louis.yu@mediatek.com> |
a92db1c8 SH |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
18 | #include <linux/clk.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/nvmem-consumer.h> | |
24 | #include <linux/of.h> | |
25 | #include <linux/of_address.h> | |
b7cf0053 | 26 | #include <linux/of_device.h> |
a92db1c8 SH |
27 | #include <linux/platform_device.h> |
28 | #include <linux/slab.h> | |
29 | #include <linux/io.h> | |
30 | #include <linux/thermal.h> | |
31 | #include <linux/reset.h> | |
32 | #include <linux/types.h> | |
a92db1c8 SH |
33 | |
34 | /* AUXADC Registers */ | |
a92db1c8 SH |
35 | #define AUXADC_CON1_SET_V 0x008 |
36 | #define AUXADC_CON1_CLR_V 0x00c | |
37 | #define AUXADC_CON2_V 0x010 | |
38 | #define AUXADC_DATA(channel) (0x14 + (channel) * 4) | |
a92db1c8 SH |
39 | |
40 | #define APMIXED_SYS_TS_CON1 0x604 | |
41 | ||
42 | /* Thermal Controller Registers */ | |
43 | #define TEMP_MONCTL0 0x000 | |
44 | #define TEMP_MONCTL1 0x004 | |
45 | #define TEMP_MONCTL2 0x008 | |
46 | #define TEMP_MONIDET0 0x014 | |
47 | #define TEMP_MONIDET1 0x018 | |
48 | #define TEMP_MSRCTL0 0x038 | |
49 | #define TEMP_AHBPOLL 0x040 | |
50 | #define TEMP_AHBTO 0x044 | |
51 | #define TEMP_ADCPNP0 0x048 | |
52 | #define TEMP_ADCPNP1 0x04c | |
53 | #define TEMP_ADCPNP2 0x050 | |
54 | #define TEMP_ADCPNP3 0x0b4 | |
55 | ||
56 | #define TEMP_ADCMUX 0x054 | |
57 | #define TEMP_ADCEN 0x060 | |
58 | #define TEMP_PNPMUXADDR 0x064 | |
59 | #define TEMP_ADCMUXADDR 0x068 | |
60 | #define TEMP_ADCENADDR 0x074 | |
61 | #define TEMP_ADCVALIDADDR 0x078 | |
62 | #define TEMP_ADCVOLTADDR 0x07c | |
63 | #define TEMP_RDCTRL 0x080 | |
64 | #define TEMP_ADCVALIDMASK 0x084 | |
65 | #define TEMP_ADCVOLTAGESHIFT 0x088 | |
66 | #define TEMP_ADCWRITECTRL 0x08c | |
67 | #define TEMP_MSR0 0x090 | |
68 | #define TEMP_MSR1 0x094 | |
69 | #define TEMP_MSR2 0x098 | |
70 | #define TEMP_MSR3 0x0B8 | |
71 | ||
72 | #define TEMP_SPARE0 0x0f0 | |
73 | ||
74 | #define PTPCORESEL 0x400 | |
75 | ||
76 | #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff) | |
77 | ||
eb4fc33e | 78 | #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16) |
a92db1c8 SH |
79 | #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff) |
80 | ||
81 | #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x) | |
82 | ||
83 | #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0) | |
84 | #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1) | |
85 | ||
86 | #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) | |
87 | #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) | |
88 | ||
b7cf0053 | 89 | /* MT8173 thermal sensors */ |
a92db1c8 SH |
90 | #define MT8173_TS1 0 |
91 | #define MT8173_TS2 1 | |
92 | #define MT8173_TS3 2 | |
93 | #define MT8173_TS4 3 | |
94 | #define MT8173_TSABB 4 | |
95 | ||
96 | /* AUXADC channel 11 is used for the temperature sensors */ | |
97 | #define MT8173_TEMP_AUXADC_CHANNEL 11 | |
98 | ||
99 | /* The total number of temperature sensors in the MT8173 */ | |
100 | #define MT8173_NUM_SENSORS 5 | |
101 | ||
102 | /* The number of banks in the MT8173 */ | |
103 | #define MT8173_NUM_ZONES 4 | |
104 | ||
105 | /* The number of sensing points per bank */ | |
106 | #define MT8173_NUM_SENSORS_PER_ZONE 4 | |
107 | ||
f8451476 MK |
108 | /* The calibration coefficient of sensor */ |
109 | #define MT8173_CALIBRATION 165 | |
110 | ||
b7cf0053 | 111 | /* |
112 | * Layout of the fuses providing the calibration data | |
0a068993 LY |
113 | * These macros could be used for MT8173, MT2701, and MT2712. |
114 | * MT8173 has 5 sensors and needs 5 VTS calibration data. | |
115 | * MT2701 has 3 sensors and needs 3 VTS calibration data. | |
116 | * MT2712 has 4 sensors and needs 4 VTS calibration data. | |
b7cf0053 | 117 | */ |
1d081945 MK |
118 | #define CALIB_BUF0_VALID BIT(0) |
119 | #define CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff) | |
120 | #define CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff) | |
121 | #define CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff) | |
122 | #define CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff) | |
123 | #define CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff) | |
124 | #define CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff) | |
125 | #define CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f) | |
126 | #define CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f) | |
127 | #define CALIB_BUF0_O_SLOPE_SIGN(x) (((x) >> 7) & 0x1) | |
128 | #define CALIB_BUF1_ID(x) (((x) >> 9) & 0x1) | |
129 | ||
130 | enum { | |
131 | VTS1, | |
132 | VTS2, | |
133 | VTS3, | |
134 | VTS4, | |
135 | VTSABB, | |
136 | MAX_NUM_VTS, | |
137 | }; | |
a92db1c8 | 138 | |
b7cf0053 | 139 | /* MT2701 thermal sensors */ |
140 | #define MT2701_TS1 0 | |
141 | #define MT2701_TS2 1 | |
142 | #define MT2701_TSABB 2 | |
143 | ||
144 | /* AUXADC channel 11 is used for the temperature sensors */ | |
145 | #define MT2701_TEMP_AUXADC_CHANNEL 11 | |
146 | ||
147 | /* The total number of temperature sensors in the MT2701 */ | |
148 | #define MT2701_NUM_SENSORS 3 | |
149 | ||
b7cf0053 | 150 | /* The number of sensing points per bank */ |
151 | #define MT2701_NUM_SENSORS_PER_ZONE 3 | |
152 | ||
f8451476 MK |
153 | /* The calibration coefficient of sensor */ |
154 | #define MT2701_CALIBRATION 165 | |
155 | ||
6cf7f002 LY |
156 | /* MT2712 thermal sensors */ |
157 | #define MT2712_TS1 0 | |
158 | #define MT2712_TS2 1 | |
159 | #define MT2712_TS3 2 | |
160 | #define MT2712_TS4 3 | |
161 | ||
162 | /* AUXADC channel 11 is used for the temperature sensors */ | |
163 | #define MT2712_TEMP_AUXADC_CHANNEL 11 | |
164 | ||
165 | /* The total number of temperature sensors in the MT2712 */ | |
166 | #define MT2712_NUM_SENSORS 4 | |
167 | ||
168 | /* The number of sensing points per bank */ | |
169 | #define MT2712_NUM_SENSORS_PER_ZONE 4 | |
170 | ||
f8451476 MK |
171 | /* The calibration coefficient of sensor */ |
172 | #define MT2712_CALIBRATION 165 | |
173 | ||
3966be3c SW |
174 | #define MT7622_TEMP_AUXADC_CHANNEL 11 |
175 | #define MT7622_NUM_SENSORS 1 | |
176 | #define MT7622_NUM_ZONES 1 | |
177 | #define MT7622_NUM_SENSORS_PER_ZONE 1 | |
178 | #define MT7622_TS1 0 | |
179 | ||
f8451476 MK |
180 | /* The calibration coefficient of sensor */ |
181 | #define MT7622_CALIBRATION 165 | |
182 | ||
a92db1c8 SH |
183 | struct mtk_thermal; |
184 | ||
b7cf0053 | 185 | struct thermal_bank_cfg { |
186 | unsigned int num_sensors; | |
187 | const int *sensors; | |
188 | }; | |
189 | ||
a92db1c8 SH |
190 | struct mtk_thermal_bank { |
191 | struct mtk_thermal *mt; | |
192 | int id; | |
193 | }; | |
194 | ||
b7cf0053 | 195 | struct mtk_thermal_data { |
196 | s32 num_banks; | |
197 | s32 num_sensors; | |
198 | s32 auxadc_channel; | |
1d081945 | 199 | const int *vts_index; |
b7cf0053 | 200 | const int *sensor_mux_values; |
201 | const int *msr; | |
202 | const int *adcpnp; | |
f8451476 | 203 | const int cali_val; |
b7cf0053 | 204 | struct thermal_bank_cfg bank_data[]; |
205 | }; | |
206 | ||
a92db1c8 SH |
207 | struct mtk_thermal { |
208 | struct device *dev; | |
209 | void __iomem *thermal_base; | |
210 | ||
211 | struct clk *clk_peri_therm; | |
212 | struct clk *clk_auxadc; | |
eb4fc33e | 213 | /* lock: for getting and putting banks */ |
a92db1c8 SH |
214 | struct mutex lock; |
215 | ||
216 | /* Calibration values */ | |
217 | s32 adc_ge; | |
218 | s32 degc_cali; | |
219 | s32 o_slope; | |
1d081945 | 220 | s32 vts[MAX_NUM_VTS]; |
a92db1c8 | 221 | |
b7cf0053 | 222 | const struct mtk_thermal_data *conf; |
223 | struct mtk_thermal_bank banks[]; | |
a92db1c8 SH |
224 | }; |
225 | ||
b7cf0053 | 226 | /* MT8173 thermal sensor data */ |
992edf39 | 227 | static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { |
b7cf0053 | 228 | { MT8173_TS2, MT8173_TS3 }, |
229 | { MT8173_TS2, MT8173_TS4 }, | |
230 | { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, | |
231 | { MT8173_TS2 }, | |
a92db1c8 SH |
232 | }; |
233 | ||
992edf39 | 234 | static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { |
05d7839a | 235 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 |
b7cf0053 | 236 | }; |
a92db1c8 | 237 | |
992edf39 | 238 | static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 239 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 |
240 | }; | |
241 | ||
992edf39 | 242 | static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; |
b7cf0053 | 243 | |
1d081945 MK |
244 | static const int mt8173_vts_index[MT8173_NUM_SENSORS] = { |
245 | VTS1, VTS2, VTS3, VTS4, VTSABB | |
246 | }; | |
247 | ||
b7cf0053 | 248 | /* MT2701 thermal sensor data */ |
992edf39 | 249 | static const int mt2701_bank_data[MT2701_NUM_SENSORS] = { |
b7cf0053 | 250 | MT2701_TS1, MT2701_TS2, MT2701_TSABB |
251 | }; | |
252 | ||
992edf39 | 253 | static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 254 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 |
255 | }; | |
256 | ||
992edf39 | 257 | static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { |
b7cf0053 | 258 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 |
259 | }; | |
260 | ||
992edf39 | 261 | static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; |
b7cf0053 | 262 | |
1d081945 MK |
263 | static const int mt2701_vts_index[MT2701_NUM_SENSORS] = { |
264 | VTS1, VTS2, VTS3 | |
265 | }; | |
266 | ||
6cf7f002 LY |
267 | /* MT2712 thermal sensor data */ |
268 | static const int mt2712_bank_data[MT2712_NUM_SENSORS] = { | |
269 | MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4 | |
270 | }; | |
271 | ||
272 | static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = { | |
273 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3 | |
274 | }; | |
275 | ||
276 | static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = { | |
277 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 | |
278 | }; | |
279 | ||
280 | static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 }; | |
281 | ||
1d081945 MK |
282 | static const int mt2712_vts_index[MT2712_NUM_SENSORS] = { |
283 | VTS1, VTS2, VTS3, VTS4 | |
284 | }; | |
285 | ||
3966be3c SW |
286 | /* MT7622 thermal sensor data */ |
287 | static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, }; | |
288 | static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, }; | |
289 | static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, }; | |
290 | static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, }; | |
1d081945 | 291 | static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 }; |
3966be3c | 292 | |
b7cf0053 | 293 | /** |
a92db1c8 SH |
294 | * The MT8173 thermal controller has four banks. Each bank can read up to |
295 | * four temperature sensors simultaneously. The MT8173 has a total of 5 | |
296 | * temperature sensors. We use each bank to measure a certain area of the | |
297 | * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple | |
298 | * areas, hence is used in different banks. | |
299 | * | |
300 | * The thermal core only gets the maximum temperature of all banks, so | |
301 | * the bank concept wouldn't be necessary here. However, the SVS (Smart | |
302 | * Voltage Scaling) unit makes its decisions based on the same bank | |
303 | * data, and this indeed needs the temperatures of the individual banks | |
304 | * for making better decisions. | |
305 | */ | |
b7cf0053 | 306 | static const struct mtk_thermal_data mt8173_thermal_data = { |
307 | .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, | |
308 | .num_banks = MT8173_NUM_ZONES, | |
309 | .num_sensors = MT8173_NUM_SENSORS, | |
1d081945 | 310 | .vts_index = mt8173_vts_index, |
f8451476 | 311 | .cali_val = MT8173_CALIBRATION, |
b7cf0053 | 312 | .bank_data = { |
313 | { | |
314 | .num_sensors = 2, | |
315 | .sensors = mt8173_bank_data[0], | |
316 | }, { | |
317 | .num_sensors = 2, | |
318 | .sensors = mt8173_bank_data[1], | |
319 | }, { | |
320 | .num_sensors = 3, | |
321 | .sensors = mt8173_bank_data[2], | |
322 | }, { | |
323 | .num_sensors = 1, | |
324 | .sensors = mt8173_bank_data[3], | |
325 | }, | |
a92db1c8 | 326 | }, |
b7cf0053 | 327 | .msr = mt8173_msr, |
328 | .adcpnp = mt8173_adcpnp, | |
329 | .sensor_mux_values = mt8173_mux_values, | |
a92db1c8 SH |
330 | }; |
331 | ||
b7cf0053 | 332 | /** |
333 | * The MT2701 thermal controller has one bank, which can read up to | |
334 | * three temperature sensors simultaneously. The MT2701 has a total of 3 | |
335 | * temperature sensors. | |
336 | * | |
337 | * The thermal core only gets the maximum temperature of this one bank, | |
338 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart | |
339 | * Voltage Scaling) unit makes its decisions based on the same bank | |
340 | * data. | |
341 | */ | |
342 | static const struct mtk_thermal_data mt2701_thermal_data = { | |
343 | .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, | |
344 | .num_banks = 1, | |
345 | .num_sensors = MT2701_NUM_SENSORS, | |
1d081945 | 346 | .vts_index = mt2701_vts_index, |
f8451476 | 347 | .cali_val = MT2701_CALIBRATION, |
b7cf0053 | 348 | .bank_data = { |
349 | { | |
350 | .num_sensors = 3, | |
351 | .sensors = mt2701_bank_data, | |
352 | }, | |
a92db1c8 | 353 | }, |
b7cf0053 | 354 | .msr = mt2701_msr, |
355 | .adcpnp = mt2701_adcpnp, | |
356 | .sensor_mux_values = mt2701_mux_values, | |
a92db1c8 SH |
357 | }; |
358 | ||
6cf7f002 LY |
359 | /** |
360 | * The MT2712 thermal controller has one bank, which can read up to | |
361 | * four temperature sensors simultaneously. The MT2712 has a total of 4 | |
362 | * temperature sensors. | |
363 | * | |
364 | * The thermal core only gets the maximum temperature of this one bank, | |
365 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart | |
366 | * Voltage Scaling) unit makes its decisions based on the same bank | |
367 | * data. | |
368 | */ | |
369 | static const struct mtk_thermal_data mt2712_thermal_data = { | |
370 | .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL, | |
371 | .num_banks = 1, | |
372 | .num_sensors = MT2712_NUM_SENSORS, | |
1d081945 | 373 | .vts_index = mt2712_vts_index, |
f8451476 | 374 | .cali_val = MT2712_CALIBRATION, |
6cf7f002 LY |
375 | .bank_data = { |
376 | { | |
377 | .num_sensors = 4, | |
378 | .sensors = mt2712_bank_data, | |
379 | }, | |
380 | }, | |
381 | .msr = mt2712_msr, | |
382 | .adcpnp = mt2712_adcpnp, | |
383 | .sensor_mux_values = mt2712_mux_values, | |
384 | }; | |
385 | ||
3966be3c SW |
386 | /* |
387 | * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data | |
388 | * access. | |
389 | */ | |
390 | static const struct mtk_thermal_data mt7622_thermal_data = { | |
391 | .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL, | |
392 | .num_banks = MT7622_NUM_ZONES, | |
393 | .num_sensors = MT7622_NUM_SENSORS, | |
1d081945 | 394 | .vts_index = mt7622_vts_index, |
f8451476 | 395 | .cali_val = MT7622_CALIBRATION, |
3966be3c SW |
396 | .bank_data = { |
397 | { | |
398 | .num_sensors = 1, | |
399 | .sensors = mt7622_bank_data, | |
400 | }, | |
401 | }, | |
402 | .msr = mt7622_msr, | |
403 | .adcpnp = mt7622_adcpnp, | |
404 | .sensor_mux_values = mt7622_mux_values, | |
405 | }; | |
406 | ||
a92db1c8 SH |
407 | /** |
408 | * raw_to_mcelsius - convert a raw ADC value to mcelsius | |
409 | * @mt: The thermal controller | |
410 | * @raw: raw ADC value | |
411 | * | |
412 | * This converts the raw ADC value to mcelsius using the SoC specific | |
413 | * calibration constants | |
414 | */ | |
415 | static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw) | |
416 | { | |
417 | s32 tmp; | |
418 | ||
419 | raw &= 0xfff; | |
420 | ||
421 | tmp = 203450520 << 3; | |
f8451476 | 422 | tmp /= mt->conf->cali_val + mt->o_slope; |
a92db1c8 SH |
423 | tmp /= 10000 + mt->adc_ge; |
424 | tmp *= raw - mt->vts[sensno] - 3350; | |
425 | tmp >>= 3; | |
426 | ||
427 | return mt->degc_cali * 500 - tmp; | |
428 | } | |
429 | ||
430 | /** | |
431 | * mtk_thermal_get_bank - get bank | |
432 | * @bank: The bank | |
433 | * | |
434 | * The bank registers are banked, we have to select a bank in the | |
435 | * PTPCORESEL register to access it. | |
436 | */ | |
437 | static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank) | |
438 | { | |
439 | struct mtk_thermal *mt = bank->mt; | |
440 | u32 val; | |
441 | ||
442 | mutex_lock(&mt->lock); | |
443 | ||
444 | val = readl(mt->thermal_base + PTPCORESEL); | |
445 | val &= ~0xf; | |
446 | val |= bank->id; | |
447 | writel(val, mt->thermal_base + PTPCORESEL); | |
448 | } | |
449 | ||
450 | /** | |
451 | * mtk_thermal_put_bank - release bank | |
452 | * @bank: The bank | |
453 | * | |
454 | * release a bank previously taken with mtk_thermal_get_bank, | |
455 | */ | |
456 | static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) | |
457 | { | |
458 | struct mtk_thermal *mt = bank->mt; | |
459 | ||
460 | mutex_unlock(&mt->lock); | |
461 | } | |
462 | ||
463 | /** | |
464 | * mtk_thermal_bank_temperature - get the temperature of a bank | |
465 | * @bank: The bank | |
466 | * | |
467 | * The temperature of a bank is considered the maximum temperature of | |
468 | * the sensors associated to the bank. | |
469 | */ | |
470 | static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) | |
471 | { | |
472 | struct mtk_thermal *mt = bank->mt; | |
b7cf0053 | 473 | const struct mtk_thermal_data *conf = mt->conf; |
eb4fc33e | 474 | int i, temp = INT_MIN, max = INT_MIN; |
a92db1c8 SH |
475 | u32 raw; |
476 | ||
b7cf0053 | 477 | for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { |
eb9aecd9 MK |
478 | raw = readl(mt->thermal_base + |
479 | conf->msr[conf->bank_data[bank->id].sensors[i]]); | |
a92db1c8 | 480 | |
b7cf0053 | 481 | temp = raw_to_mcelsius(mt, |
482 | conf->bank_data[bank->id].sensors[i], | |
483 | raw); | |
a92db1c8 SH |
484 | |
485 | /* | |
486 | * The first read of a sensor often contains very high bogus | |
487 | * temperature value. Filter these out so that the system does | |
488 | * not immediately shut down. | |
489 | */ | |
490 | if (temp > 200000) | |
491 | temp = 0; | |
492 | ||
493 | if (temp > max) | |
494 | max = temp; | |
495 | } | |
496 | ||
497 | return max; | |
498 | } | |
499 | ||
500 | static int mtk_read_temp(void *data, int *temperature) | |
501 | { | |
502 | struct mtk_thermal *mt = data; | |
503 | int i; | |
504 | int tempmax = INT_MIN; | |
505 | ||
b7cf0053 | 506 | for (i = 0; i < mt->conf->num_banks; i++) { |
a92db1c8 SH |
507 | struct mtk_thermal_bank *bank = &mt->banks[i]; |
508 | ||
509 | mtk_thermal_get_bank(bank); | |
510 | ||
511 | tempmax = max(tempmax, mtk_thermal_bank_temperature(bank)); | |
512 | ||
513 | mtk_thermal_put_bank(bank); | |
514 | } | |
515 | ||
516 | *temperature = tempmax; | |
517 | ||
518 | return 0; | |
519 | } | |
520 | ||
521 | static const struct thermal_zone_of_device_ops mtk_thermal_ops = { | |
522 | .get_temp = mtk_read_temp, | |
523 | }; | |
524 | ||
525 | static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, | |
eb4fc33e | 526 | u32 apmixed_phys_base, u32 auxadc_phys_base) |
a92db1c8 SH |
527 | { |
528 | struct mtk_thermal_bank *bank = &mt->banks[num]; | |
b7cf0053 | 529 | const struct mtk_thermal_data *conf = mt->conf; |
a92db1c8 SH |
530 | int i; |
531 | ||
532 | bank->id = num; | |
533 | bank->mt = mt; | |
534 | ||
535 | mtk_thermal_get_bank(bank); | |
536 | ||
537 | /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */ | |
538 | writel(TEMP_MONCTL1_PERIOD_UNIT(12), mt->thermal_base + TEMP_MONCTL1); | |
539 | ||
540 | /* | |
541 | * filt interval is 1 * 46.540us = 46.54us, | |
542 | * sen interval is 429 * 46.540us = 19.96ms | |
543 | */ | |
544 | writel(TEMP_MONCTL2_FILTER_INTERVAL(1) | | |
545 | TEMP_MONCTL2_SENSOR_INTERVAL(429), | |
546 | mt->thermal_base + TEMP_MONCTL2); | |
547 | ||
548 | /* poll is set to 10u */ | |
549 | writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768), | |
eb4fc33e | 550 | mt->thermal_base + TEMP_AHBPOLL); |
a92db1c8 SH |
551 | |
552 | /* temperature sampling control, 1 sample */ | |
553 | writel(0x0, mt->thermal_base + TEMP_MSRCTL0); | |
554 | ||
555 | /* exceed this polling time, IRQ would be inserted */ | |
556 | writel(0xffffffff, mt->thermal_base + TEMP_AHBTO); | |
557 | ||
558 | /* number of interrupts per event, 1 is enough */ | |
559 | writel(0x0, mt->thermal_base + TEMP_MONIDET0); | |
560 | writel(0x0, mt->thermal_base + TEMP_MONIDET1); | |
561 | ||
562 | /* | |
563 | * The MT8173 thermal controller does not have its own ADC. Instead it | |
564 | * uses AHB bus accesses to control the AUXADC. To do this the thermal | |
565 | * controller has to be programmed with the physical addresses of the | |
566 | * AUXADC registers and with the various bit positions in the AUXADC. | |
567 | * Also the thermal controller controls a mux in the APMIXEDSYS register | |
568 | * space. | |
569 | */ | |
570 | ||
571 | /* | |
572 | * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) | |
573 | * automatically by hw | |
574 | */ | |
b7cf0053 | 575 | writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCMUX); |
a92db1c8 SH |
576 | |
577 | /* AHB address for auxadc mux selection */ | |
578 | writel(auxadc_phys_base + AUXADC_CON1_CLR_V, | |
eb4fc33e | 579 | mt->thermal_base + TEMP_ADCMUXADDR); |
a92db1c8 SH |
580 | |
581 | /* AHB address for pnp sensor mux selection */ | |
582 | writel(apmixed_phys_base + APMIXED_SYS_TS_CON1, | |
eb4fc33e | 583 | mt->thermal_base + TEMP_PNPMUXADDR); |
a92db1c8 SH |
584 | |
585 | /* AHB value for auxadc enable */ | |
b7cf0053 | 586 | writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCEN); |
a92db1c8 SH |
587 | |
588 | /* AHB address for auxadc enable (channel 0 immediate mode selected) */ | |
589 | writel(auxadc_phys_base + AUXADC_CON1_SET_V, | |
eb4fc33e | 590 | mt->thermal_base + TEMP_ADCENADDR); |
a92db1c8 SH |
591 | |
592 | /* AHB address for auxadc valid bit */ | |
b7cf0053 | 593 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
eb4fc33e | 594 | mt->thermal_base + TEMP_ADCVALIDADDR); |
a92db1c8 SH |
595 | |
596 | /* AHB address for auxadc voltage output */ | |
b7cf0053 | 597 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
eb4fc33e | 598 | mt->thermal_base + TEMP_ADCVOLTADDR); |
a92db1c8 SH |
599 | |
600 | /* read valid & voltage are at the same register */ | |
601 | writel(0x0, mt->thermal_base + TEMP_RDCTRL); | |
602 | ||
603 | /* indicate where the valid bit is */ | |
604 | writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12), | |
eb4fc33e | 605 | mt->thermal_base + TEMP_ADCVALIDMASK); |
a92db1c8 SH |
606 | |
607 | /* no shift */ | |
608 | writel(0x0, mt->thermal_base + TEMP_ADCVOLTAGESHIFT); | |
609 | ||
610 | /* enable auxadc mux write transaction */ | |
611 | writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
eb4fc33e | 612 | mt->thermal_base + TEMP_ADCWRITECTRL); |
a92db1c8 | 613 | |
b7cf0053 | 614 | for (i = 0; i < conf->bank_data[num].num_sensors; i++) |
615 | writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], | |
eb9aecd9 MK |
616 | mt->thermal_base + |
617 | conf->adcpnp[conf->bank_data[num].sensors[i]]); | |
a92db1c8 | 618 | |
b7cf0053 | 619 | writel((1 << conf->bank_data[num].num_sensors) - 1, |
620 | mt->thermal_base + TEMP_MONCTL0); | |
a92db1c8 | 621 | |
eb4fc33e EV |
622 | writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | |
623 | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | |
624 | mt->thermal_base + TEMP_ADCWRITECTRL); | |
a92db1c8 SH |
625 | |
626 | mtk_thermal_put_bank(bank); | |
627 | } | |
628 | ||
629 | static u64 of_get_phys_base(struct device_node *np) | |
630 | { | |
631 | u64 size64; | |
632 | const __be32 *regaddr_p; | |
633 | ||
634 | regaddr_p = of_get_address(np, 0, &size64, NULL); | |
635 | if (!regaddr_p) | |
636 | return OF_BAD_ADDR; | |
637 | ||
638 | return of_translate_address(np, regaddr_p); | |
639 | } | |
640 | ||
eb4fc33e EV |
641 | static int mtk_thermal_get_calibration_data(struct device *dev, |
642 | struct mtk_thermal *mt) | |
a92db1c8 SH |
643 | { |
644 | struct nvmem_cell *cell; | |
645 | u32 *buf; | |
646 | size_t len; | |
647 | int i, ret = 0; | |
648 | ||
649 | /* Start with default values */ | |
650 | mt->adc_ge = 512; | |
b7cf0053 | 651 | for (i = 0; i < mt->conf->num_sensors; i++) |
a92db1c8 SH |
652 | mt->vts[i] = 260; |
653 | mt->degc_cali = 40; | |
654 | mt->o_slope = 0; | |
655 | ||
656 | cell = nvmem_cell_get(dev, "calibration-data"); | |
657 | if (IS_ERR(cell)) { | |
658 | if (PTR_ERR(cell) == -EPROBE_DEFER) | |
659 | return PTR_ERR(cell); | |
660 | return 0; | |
661 | } | |
662 | ||
663 | buf = (u32 *)nvmem_cell_read(cell, &len); | |
664 | ||
665 | nvmem_cell_put(cell); | |
666 | ||
667 | if (IS_ERR(buf)) | |
668 | return PTR_ERR(buf); | |
669 | ||
670 | if (len < 3 * sizeof(u32)) { | |
671 | dev_warn(dev, "invalid calibration data\n"); | |
672 | ret = -EINVAL; | |
673 | goto out; | |
674 | } | |
675 | ||
1d081945 MK |
676 | if (buf[0] & CALIB_BUF0_VALID) { |
677 | mt->adc_ge = CALIB_BUF1_ADC_GE(buf[1]); | |
678 | ||
679 | for (i = 0; i < mt->conf->num_sensors; i++) { | |
680 | switch (mt->conf->vts_index[i]) { | |
681 | case VTS1: | |
682 | mt->vts[VTS1] = CALIB_BUF0_VTS_TS1(buf[0]); | |
683 | break; | |
684 | case VTS2: | |
685 | mt->vts[VTS2] = CALIB_BUF0_VTS_TS2(buf[0]); | |
686 | break; | |
687 | case VTS3: | |
688 | mt->vts[VTS3] = CALIB_BUF1_VTS_TS3(buf[1]); | |
689 | break; | |
690 | case VTS4: | |
691 | mt->vts[VTS4] = CALIB_BUF2_VTS_TS4(buf[2]); | |
692 | break; | |
693 | case VTSABB: | |
694 | mt->vts[VTSABB] = CALIB_BUF2_VTS_TSABB(buf[2]); | |
695 | break; | |
696 | default: | |
697 | break; | |
698 | } | |
699 | } | |
700 | ||
701 | mt->degc_cali = CALIB_BUF0_DEGC_CALI(buf[0]); | |
702 | if (CALIB_BUF1_ID(buf[1]) & | |
703 | CALIB_BUF0_O_SLOPE_SIGN(buf[0])) | |
704 | mt->o_slope = -CALIB_BUF0_O_SLOPE(buf[0]); | |
0a068993 | 705 | else |
1d081945 | 706 | mt->o_slope = CALIB_BUF0_O_SLOPE(buf[0]); |
a92db1c8 SH |
707 | } else { |
708 | dev_info(dev, "Device not calibrated, using default calibration values\n"); | |
709 | } | |
710 | ||
711 | out: | |
712 | kfree(buf); | |
713 | ||
714 | return ret; | |
715 | } | |
716 | ||
b7cf0053 | 717 | static const struct of_device_id mtk_thermal_of_match[] = { |
718 | { | |
719 | .compatible = "mediatek,mt8173-thermal", | |
720 | .data = (void *)&mt8173_thermal_data, | |
721 | }, | |
722 | { | |
723 | .compatible = "mediatek,mt2701-thermal", | |
724 | .data = (void *)&mt2701_thermal_data, | |
6cf7f002 LY |
725 | }, |
726 | { | |
727 | .compatible = "mediatek,mt2712-thermal", | |
728 | .data = (void *)&mt2712_thermal_data, | |
3966be3c SW |
729 | }, |
730 | { | |
731 | .compatible = "mediatek,mt7622-thermal", | |
732 | .data = (void *)&mt7622_thermal_data, | |
b7cf0053 | 733 | }, { |
734 | }, | |
735 | }; | |
736 | MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); | |
737 | ||
a92db1c8 SH |
738 | static int mtk_thermal_probe(struct platform_device *pdev) |
739 | { | |
740 | int ret, i; | |
741 | struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; | |
742 | struct mtk_thermal *mt; | |
743 | struct resource *res; | |
744 | u64 auxadc_phys_base, apmixed_phys_base; | |
1f6b0889 | 745 | struct thermal_zone_device *tzdev; |
a92db1c8 SH |
746 | |
747 | mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); | |
748 | if (!mt) | |
749 | return -ENOMEM; | |
750 | ||
9efc58df | 751 | mt->conf = of_device_get_match_data(&pdev->dev); |
b7cf0053 | 752 | |
a92db1c8 SH |
753 | mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); |
754 | if (IS_ERR(mt->clk_peri_therm)) | |
755 | return PTR_ERR(mt->clk_peri_therm); | |
756 | ||
757 | mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc"); | |
758 | if (IS_ERR(mt->clk_auxadc)) | |
759 | return PTR_ERR(mt->clk_auxadc); | |
760 | ||
761 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
762 | mt->thermal_base = devm_ioremap_resource(&pdev->dev, res); | |
763 | if (IS_ERR(mt->thermal_base)) | |
764 | return PTR_ERR(mt->thermal_base); | |
765 | ||
766 | ret = mtk_thermal_get_calibration_data(&pdev->dev, mt); | |
767 | if (ret) | |
768 | return ret; | |
769 | ||
770 | mutex_init(&mt->lock); | |
771 | ||
772 | mt->dev = &pdev->dev; | |
773 | ||
774 | auxadc = of_parse_phandle(np, "mediatek,auxadc", 0); | |
775 | if (!auxadc) { | |
776 | dev_err(&pdev->dev, "missing auxadc node\n"); | |
777 | return -ENODEV; | |
778 | } | |
779 | ||
780 | auxadc_phys_base = of_get_phys_base(auxadc); | |
781 | ||
782 | of_node_put(auxadc); | |
783 | ||
784 | if (auxadc_phys_base == OF_BAD_ADDR) { | |
785 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
786 | return -EINVAL; | |
787 | } | |
788 | ||
789 | apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0); | |
790 | if (!apmixedsys) { | |
791 | dev_err(&pdev->dev, "missing apmixedsys node\n"); | |
792 | return -ENODEV; | |
793 | } | |
794 | ||
795 | apmixed_phys_base = of_get_phys_base(apmixedsys); | |
796 | ||
797 | of_node_put(apmixedsys); | |
798 | ||
799 | if (apmixed_phys_base == OF_BAD_ADDR) { | |
800 | dev_err(&pdev->dev, "Can't get auxadc phys address\n"); | |
801 | return -EINVAL; | |
802 | } | |
803 | ||
6760f3f7 LY |
804 | ret = device_reset(&pdev->dev); |
805 | if (ret) | |
806 | return ret; | |
807 | ||
a92db1c8 SH |
808 | ret = clk_prepare_enable(mt->clk_auxadc); |
809 | if (ret) { | |
810 | dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret); | |
811 | return ret; | |
812 | } | |
813 | ||
a92db1c8 SH |
814 | ret = clk_prepare_enable(mt->clk_peri_therm); |
815 | if (ret) { | |
816 | dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret); | |
817 | goto err_disable_clk_auxadc; | |
818 | } | |
819 | ||
b7cf0053 | 820 | for (i = 0; i < mt->conf->num_banks; i++) |
eb4fc33e EV |
821 | mtk_thermal_init_bank(mt, i, apmixed_phys_base, |
822 | auxadc_phys_base); | |
a92db1c8 SH |
823 | |
824 | platform_set_drvdata(pdev, mt); | |
825 | ||
1f6b0889 AL |
826 | tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt, |
827 | &mtk_thermal_ops); | |
828 | if (IS_ERR(tzdev)) { | |
829 | ret = PTR_ERR(tzdev); | |
830 | goto err_disable_clk_peri_therm; | |
831 | } | |
a92db1c8 SH |
832 | |
833 | return 0; | |
834 | ||
1f6b0889 AL |
835 | err_disable_clk_peri_therm: |
836 | clk_disable_unprepare(mt->clk_peri_therm); | |
a92db1c8 SH |
837 | err_disable_clk_auxadc: |
838 | clk_disable_unprepare(mt->clk_auxadc); | |
839 | ||
840 | return ret; | |
841 | } | |
842 | ||
843 | static int mtk_thermal_remove(struct platform_device *pdev) | |
844 | { | |
845 | struct mtk_thermal *mt = platform_get_drvdata(pdev); | |
846 | ||
a92db1c8 SH |
847 | clk_disable_unprepare(mt->clk_peri_therm); |
848 | clk_disable_unprepare(mt->clk_auxadc); | |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
a92db1c8 SH |
853 | static struct platform_driver mtk_thermal_driver = { |
854 | .probe = mtk_thermal_probe, | |
855 | .remove = mtk_thermal_remove, | |
856 | .driver = { | |
f45ce7ee | 857 | .name = "mtk-thermal", |
a92db1c8 SH |
858 | .of_match_table = mtk_thermal_of_match, |
859 | }, | |
860 | }; | |
861 | ||
862 | module_platform_driver(mtk_thermal_driver); | |
863 | ||
6cf7f002 | 864 | MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>"); |
b7cf0053 | 865 | MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>"); |
9ebfb4e0 | 866 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
a92db1c8 SH |
867 | MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); |
868 | MODULE_DESCRIPTION("Mediatek thermal driver"); | |
869 | MODULE_LICENSE("GPL v2"); |