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cbac8f63 CW |
1 | /* |
2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_irq.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/reset.h> | |
24 | #include <linux/thermal.h> | |
c970872e | 25 | #include <linux/pinctrl/consumer.h> |
cbac8f63 CW |
26 | |
27 | /** | |
28 | * If the temperature over a period of time High, | |
29 | * the resulting TSHUT gave CRU module,let it reset the entire chip, | |
30 | * or via GPIO give PMIC. | |
31 | */ | |
32 | enum tshut_mode { | |
33 | TSHUT_MODE_CRU = 0, | |
34 | TSHUT_MODE_GPIO, | |
35 | }; | |
36 | ||
37 | /** | |
38 | * the system Temperature Sensors tshut(tshut) polarity | |
39 | * the bit 8 is tshut polarity. | |
40 | * 0: low active, 1: high active | |
41 | */ | |
42 | enum tshut_polarity { | |
43 | TSHUT_LOW_ACTIVE = 0, | |
44 | TSHUT_HIGH_ACTIVE, | |
45 | }; | |
46 | ||
47 | /** | |
1d98b618 CW |
48 | * The system has two Temperature Sensors. |
49 | * sensor0 is for CPU, and sensor1 is for GPU. | |
cbac8f63 CW |
50 | */ |
51 | enum sensor_id { | |
1d98b618 | 52 | SENSOR_CPU = 0, |
cbac8f63 CW |
53 | SENSOR_GPU, |
54 | }; | |
55 | ||
1d98b618 CW |
56 | /** |
57 | * The max sensors is two in rockchip SoCs. | |
58 | * Two sensors: CPU and GPU sensor. | |
59 | */ | |
60 | #define SOC_MAX_SENSORS 2 | |
61 | ||
cbac8f63 | 62 | struct rockchip_tsadc_chip { |
1d98b618 CW |
63 | /* The sensor id of chip correspond to the ADC channel */ |
64 | int chn_id[SOC_MAX_SENSORS]; | |
65 | int chn_num; | |
66 | ||
cbac8f63 CW |
67 | /* The hardware-controlled tshut property */ |
68 | long tshut_temp; | |
69 | enum tshut_mode tshut_mode; | |
70 | enum tshut_polarity tshut_polarity; | |
71 | ||
72 | /* Chip-wide methods */ | |
73 | void (*initialize)(void __iomem *reg, enum tshut_polarity p); | |
74 | void (*irq_ack)(void __iomem *reg); | |
75 | void (*control)(void __iomem *reg, bool on); | |
76 | ||
77 | /* Per-sensor methods */ | |
17e8351a | 78 | int (*get_temp)(int chn, void __iomem *reg, int *temp); |
cbac8f63 CW |
79 | void (*set_tshut_temp)(int chn, void __iomem *reg, long temp); |
80 | void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); | |
81 | }; | |
82 | ||
83 | struct rockchip_thermal_sensor { | |
84 | struct rockchip_thermal_data *thermal; | |
85 | struct thermal_zone_device *tzd; | |
1d98b618 | 86 | int id; |
cbac8f63 CW |
87 | }; |
88 | ||
cbac8f63 CW |
89 | struct rockchip_thermal_data { |
90 | const struct rockchip_tsadc_chip *chip; | |
91 | struct platform_device *pdev; | |
92 | struct reset_control *reset; | |
93 | ||
1d98b618 | 94 | struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; |
cbac8f63 CW |
95 | |
96 | struct clk *clk; | |
97 | struct clk *pclk; | |
98 | ||
99 | void __iomem *regs; | |
100 | ||
101 | long tshut_temp; | |
102 | enum tshut_mode tshut_mode; | |
103 | enum tshut_polarity tshut_polarity; | |
104 | }; | |
105 | ||
1d98b618 | 106 | /* TSADC Sensor info define: */ |
cbac8f63 CW |
107 | #define TSADCV2_AUTO_CON 0x04 |
108 | #define TSADCV2_INT_EN 0x08 | |
109 | #define TSADCV2_INT_PD 0x0c | |
110 | #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) | |
111 | #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) | |
112 | #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 | |
113 | #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 | |
114 | #define TSADCV2_AUTO_PERIOD 0x68 | |
115 | #define TSADCV2_AUTO_PERIOD_HT 0x6c | |
116 | ||
117 | #define TSADCV2_AUTO_EN BIT(0) | |
cbac8f63 CW |
118 | #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) |
119 | #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) | |
cbac8f63 CW |
120 | |
121 | #define TSADCV2_INT_SRC_EN(chn) BIT(chn) | |
122 | #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) | |
123 | #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) | |
124 | ||
452e01b3 | 125 | #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) |
cbac8f63 CW |
126 | |
127 | #define TSADCV2_DATA_MASK 0xfff | |
128 | #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 | |
129 | #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 | |
130 | #define TSADCV2_AUTO_PERIOD_TIME 250 /* msec */ | |
131 | #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* msec */ | |
132 | ||
133 | struct tsadc_table { | |
d9a241cb | 134 | u32 code; |
cbac8f63 CW |
135 | long temp; |
136 | }; | |
137 | ||
138 | static const struct tsadc_table v2_code_table[] = { | |
139 | {TSADCV2_DATA_MASK, -40000}, | |
140 | {3800, -40000}, | |
141 | {3792, -35000}, | |
142 | {3783, -30000}, | |
143 | {3774, -25000}, | |
144 | {3765, -20000}, | |
145 | {3756, -15000}, | |
146 | {3747, -10000}, | |
147 | {3737, -5000}, | |
148 | {3728, 0}, | |
149 | {3718, 5000}, | |
150 | {3708, 10000}, | |
151 | {3698, 15000}, | |
152 | {3688, 20000}, | |
153 | {3678, 25000}, | |
154 | {3667, 30000}, | |
155 | {3656, 35000}, | |
156 | {3645, 40000}, | |
157 | {3634, 45000}, | |
158 | {3623, 50000}, | |
159 | {3611, 55000}, | |
160 | {3600, 60000}, | |
161 | {3588, 65000}, | |
162 | {3575, 70000}, | |
163 | {3563, 75000}, | |
164 | {3550, 80000}, | |
165 | {3537, 85000}, | |
166 | {3524, 90000}, | |
167 | {3510, 95000}, | |
168 | {3496, 100000}, | |
169 | {3482, 105000}, | |
170 | {3467, 110000}, | |
171 | {3452, 115000}, | |
172 | {3437, 120000}, | |
173 | {3421, 125000}, | |
cbac8f63 CW |
174 | }; |
175 | ||
176 | static u32 rk_tsadcv2_temp_to_code(long temp) | |
177 | { | |
178 | int high, low, mid; | |
179 | ||
180 | low = 0; | |
181 | high = ARRAY_SIZE(v2_code_table) - 1; | |
182 | mid = (high + low) / 2; | |
183 | ||
184 | if (temp < v2_code_table[low].temp || temp > v2_code_table[high].temp) | |
185 | return 0; | |
186 | ||
187 | while (low <= high) { | |
188 | if (temp == v2_code_table[mid].temp) | |
189 | return v2_code_table[mid].code; | |
190 | else if (temp < v2_code_table[mid].temp) | |
191 | high = mid - 1; | |
192 | else | |
193 | low = mid + 1; | |
194 | mid = (low + high) / 2; | |
195 | } | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
d9a241cb | 200 | static int rk_tsadcv2_code_to_temp(u32 code, int *temp) |
cbac8f63 | 201 | { |
d9a241cb | 202 | unsigned int low = 1; |
1e9a1aea CW |
203 | unsigned int high = ARRAY_SIZE(v2_code_table) - 1; |
204 | unsigned int mid = (low + high) / 2; | |
205 | unsigned int num; | |
206 | unsigned long denom; | |
207 | ||
d9a241cb | 208 | BUILD_BUG_ON(ARRAY_SIZE(v2_code_table) < 2); |
1e9a1aea | 209 | |
d9a241cb DT |
210 | code &= TSADCV2_DATA_MASK; |
211 | if (code < v2_code_table[high].code) | |
212 | return -EAGAIN; /* Incorrect reading */ | |
213 | ||
214 | while (low <= high) { | |
1e9a1aea CW |
215 | if (code >= v2_code_table[mid].code && |
216 | code < v2_code_table[mid - 1].code) | |
217 | break; | |
cbac8f63 CW |
218 | else if (code < v2_code_table[mid].code) |
219 | low = mid + 1; | |
220 | else | |
221 | high = mid - 1; | |
222 | mid = (low + high) / 2; | |
223 | } | |
224 | ||
1e9a1aea CW |
225 | /* |
226 | * The 5C granularity provided by the table is too much. Let's | |
227 | * assume that the relationship between sensor readings and | |
228 | * temperature between 2 table entries is linear and interpolate | |
229 | * to produce less granular result. | |
230 | */ | |
231 | num = v2_code_table[mid].temp - v2_code_table[mid - 1].temp; | |
232 | num *= v2_code_table[mid - 1].code - code; | |
233 | denom = v2_code_table[mid - 1].code - v2_code_table[mid].code; | |
d9a241cb DT |
234 | *temp = v2_code_table[mid - 1].temp + (num / denom); |
235 | ||
236 | return 0; | |
cbac8f63 CW |
237 | } |
238 | ||
239 | /** | |
240 | * rk_tsadcv2_initialize - initialize TASDC Controller | |
241 | * (1) Set TSADCV2_AUTO_PERIOD, configure the interleave between | |
242 | * every two accessing of TSADC in normal operation. | |
243 | * (2) Set TSADCV2_AUTO_PERIOD_HT, configure the interleave between | |
244 | * every two accessing of TSADC after the temperature is higher | |
245 | * than COM_SHUT or COM_INT. | |
246 | * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE, | |
247 | * if the temperature is higher than COMP_INT or COMP_SHUT for | |
248 | * "debounce" times, TSADC controller will generate interrupt or TSHUT. | |
249 | */ | |
250 | static void rk_tsadcv2_initialize(void __iomem *regs, | |
251 | enum tshut_polarity tshut_polarity) | |
252 | { | |
253 | if (tshut_polarity == TSHUT_HIGH_ACTIVE) | |
452e01b3 | 254 | writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
cbac8f63 CW |
255 | regs + TSADCV2_AUTO_CON); |
256 | else | |
452e01b3 | 257 | writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
cbac8f63 CW |
258 | regs + TSADCV2_AUTO_CON); |
259 | ||
260 | writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); | |
261 | writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, | |
262 | regs + TSADCV2_HIGHT_INT_DEBOUNCE); | |
263 | writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, | |
264 | regs + TSADCV2_AUTO_PERIOD_HT); | |
265 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, | |
266 | regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); | |
267 | } | |
268 | ||
269 | static void rk_tsadcv2_irq_ack(void __iomem *regs) | |
270 | { | |
271 | u32 val; | |
272 | ||
273 | val = readl_relaxed(regs + TSADCV2_INT_PD); | |
452e01b3 | 274 | writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); |
cbac8f63 CW |
275 | } |
276 | ||
277 | static void rk_tsadcv2_control(void __iomem *regs, bool enable) | |
278 | { | |
279 | u32 val; | |
280 | ||
281 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
282 | if (enable) | |
283 | val |= TSADCV2_AUTO_EN; | |
284 | else | |
285 | val &= ~TSADCV2_AUTO_EN; | |
286 | ||
287 | writel_relaxed(val, regs + TSADCV2_AUTO_CON); | |
288 | } | |
289 | ||
17e8351a | 290 | static int rk_tsadcv2_get_temp(int chn, void __iomem *regs, int *temp) |
cbac8f63 CW |
291 | { |
292 | u32 val; | |
293 | ||
cbac8f63 | 294 | val = readl_relaxed(regs + TSADCV2_DATA(chn)); |
cbac8f63 | 295 | |
d9a241cb | 296 | return rk_tsadcv2_code_to_temp(val, temp); |
cbac8f63 CW |
297 | } |
298 | ||
299 | static void rk_tsadcv2_tshut_temp(int chn, void __iomem *regs, long temp) | |
300 | { | |
301 | u32 tshut_value, val; | |
302 | ||
303 | tshut_value = rk_tsadcv2_temp_to_code(temp); | |
304 | writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); | |
305 | ||
306 | /* TSHUT will be valid */ | |
307 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
308 | writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); | |
309 | } | |
310 | ||
311 | static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, | |
312 | enum tshut_mode mode) | |
313 | { | |
314 | u32 val; | |
315 | ||
316 | val = readl_relaxed(regs + TSADCV2_INT_EN); | |
317 | if (mode == TSHUT_MODE_GPIO) { | |
318 | val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); | |
319 | val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); | |
320 | } else { | |
321 | val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); | |
322 | val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); | |
323 | } | |
324 | ||
325 | writel_relaxed(val, regs + TSADCV2_INT_EN); | |
326 | } | |
327 | ||
328 | static const struct rockchip_tsadc_chip rk3288_tsadc_data = { | |
1d98b618 CW |
329 | .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ |
330 | .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ | |
331 | .chn_num = 2, /* two channels for tsadc */ | |
332 | ||
cbac8f63 CW |
333 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
334 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
335 | .tshut_temp = 95000, | |
336 | ||
337 | .initialize = rk_tsadcv2_initialize, | |
338 | .irq_ack = rk_tsadcv2_irq_ack, | |
339 | .control = rk_tsadcv2_control, | |
340 | .get_temp = rk_tsadcv2_get_temp, | |
341 | .set_tshut_temp = rk_tsadcv2_tshut_temp, | |
342 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
343 | }; | |
344 | ||
345 | static const struct of_device_id of_rockchip_thermal_match[] = { | |
346 | { | |
347 | .compatible = "rockchip,rk3288-tsadc", | |
348 | .data = (void *)&rk3288_tsadc_data, | |
349 | }, | |
350 | { /* end */ }, | |
351 | }; | |
352 | MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); | |
353 | ||
354 | static void | |
355 | rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on) | |
356 | { | |
357 | struct thermal_zone_device *tzd = sensor->tzd; | |
358 | ||
359 | tzd->ops->set_mode(tzd, | |
360 | on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED); | |
361 | } | |
362 | ||
363 | static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) | |
364 | { | |
365 | struct rockchip_thermal_data *thermal = dev; | |
366 | int i; | |
367 | ||
368 | dev_dbg(&thermal->pdev->dev, "thermal alarm\n"); | |
369 | ||
370 | thermal->chip->irq_ack(thermal->regs); | |
371 | ||
1d98b618 | 372 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
373 | thermal_zone_device_update(thermal->sensors[i].tzd); |
374 | ||
375 | return IRQ_HANDLED; | |
376 | } | |
377 | ||
17e8351a | 378 | static int rockchip_thermal_get_temp(void *_sensor, int *out_temp) |
cbac8f63 CW |
379 | { |
380 | struct rockchip_thermal_sensor *sensor = _sensor; | |
381 | struct rockchip_thermal_data *thermal = sensor->thermal; | |
382 | const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip; | |
383 | int retval; | |
384 | ||
385 | retval = tsadc->get_temp(sensor->id, thermal->regs, out_temp); | |
17e8351a | 386 | dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", |
cbac8f63 CW |
387 | sensor->id, *out_temp, retval); |
388 | ||
389 | return retval; | |
390 | } | |
391 | ||
392 | static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = { | |
393 | .get_temp = rockchip_thermal_get_temp, | |
394 | }; | |
395 | ||
396 | static int rockchip_configure_from_dt(struct device *dev, | |
397 | struct device_node *np, | |
398 | struct rockchip_thermal_data *thermal) | |
399 | { | |
400 | u32 shut_temp, tshut_mode, tshut_polarity; | |
401 | ||
402 | if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) { | |
403 | dev_warn(dev, | |
404 | "Missing tshut temp property, using default %ld\n", | |
405 | thermal->chip->tshut_temp); | |
406 | thermal->tshut_temp = thermal->chip->tshut_temp; | |
407 | } else { | |
408 | thermal->tshut_temp = shut_temp; | |
409 | } | |
410 | ||
411 | if (thermal->tshut_temp > INT_MAX) { | |
412 | dev_err(dev, "Invalid tshut temperature specified: %ld\n", | |
413 | thermal->tshut_temp); | |
414 | return -ERANGE; | |
415 | } | |
416 | ||
417 | if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) { | |
418 | dev_warn(dev, | |
419 | "Missing tshut mode property, using default (%s)\n", | |
420 | thermal->chip->tshut_mode == TSHUT_MODE_GPIO ? | |
421 | "gpio" : "cru"); | |
422 | thermal->tshut_mode = thermal->chip->tshut_mode; | |
423 | } else { | |
424 | thermal->tshut_mode = tshut_mode; | |
425 | } | |
426 | ||
427 | if (thermal->tshut_mode > 1) { | |
428 | dev_err(dev, "Invalid tshut mode specified: %d\n", | |
429 | thermal->tshut_mode); | |
430 | return -EINVAL; | |
431 | } | |
432 | ||
433 | if (of_property_read_u32(np, "rockchip,hw-tshut-polarity", | |
434 | &tshut_polarity)) { | |
435 | dev_warn(dev, | |
436 | "Missing tshut-polarity property, using default (%s)\n", | |
437 | thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ? | |
438 | "low" : "high"); | |
439 | thermal->tshut_polarity = thermal->chip->tshut_polarity; | |
440 | } else { | |
441 | thermal->tshut_polarity = tshut_polarity; | |
442 | } | |
443 | ||
444 | if (thermal->tshut_polarity > 1) { | |
445 | dev_err(dev, "Invalid tshut-polarity specified: %d\n", | |
446 | thermal->tshut_polarity); | |
447 | return -EINVAL; | |
448 | } | |
449 | ||
450 | return 0; | |
451 | } | |
452 | ||
453 | static int | |
454 | rockchip_thermal_register_sensor(struct platform_device *pdev, | |
455 | struct rockchip_thermal_data *thermal, | |
456 | struct rockchip_thermal_sensor *sensor, | |
1d98b618 | 457 | int id) |
cbac8f63 CW |
458 | { |
459 | const struct rockchip_tsadc_chip *tsadc = thermal->chip; | |
460 | int error; | |
461 | ||
462 | tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); | |
463 | tsadc->set_tshut_temp(id, thermal->regs, thermal->tshut_temp); | |
464 | ||
465 | sensor->thermal = thermal; | |
466 | sensor->id = id; | |
467 | sensor->tzd = thermal_zone_of_sensor_register(&pdev->dev, id, sensor, | |
468 | &rockchip_of_thermal_ops); | |
469 | if (IS_ERR(sensor->tzd)) { | |
470 | error = PTR_ERR(sensor->tzd); | |
471 | dev_err(&pdev->dev, "failed to register sensor %d: %d\n", | |
472 | id, error); | |
473 | return error; | |
474 | } | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | /* | |
480 | * Reset TSADC Controller, reset all tsadc registers. | |
481 | */ | |
482 | static void rockchip_thermal_reset_controller(struct reset_control *reset) | |
483 | { | |
484 | reset_control_assert(reset); | |
485 | usleep_range(10, 20); | |
486 | reset_control_deassert(reset); | |
487 | } | |
488 | ||
489 | static int rockchip_thermal_probe(struct platform_device *pdev) | |
490 | { | |
491 | struct device_node *np = pdev->dev.of_node; | |
492 | struct rockchip_thermal_data *thermal; | |
493 | const struct of_device_id *match; | |
494 | struct resource *res; | |
495 | int irq; | |
1d98b618 | 496 | int i, j; |
cbac8f63 CW |
497 | int error; |
498 | ||
499 | match = of_match_node(of_rockchip_thermal_match, np); | |
500 | if (!match) | |
501 | return -ENXIO; | |
502 | ||
503 | irq = platform_get_irq(pdev, 0); | |
504 | if (irq < 0) { | |
505 | dev_err(&pdev->dev, "no irq resource?\n"); | |
506 | return -EINVAL; | |
507 | } | |
508 | ||
509 | thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), | |
510 | GFP_KERNEL); | |
511 | if (!thermal) | |
512 | return -ENOMEM; | |
513 | ||
514 | thermal->pdev = pdev; | |
515 | ||
516 | thermal->chip = (const struct rockchip_tsadc_chip *)match->data; | |
517 | if (!thermal->chip) | |
518 | return -EINVAL; | |
519 | ||
520 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
521 | thermal->regs = devm_ioremap_resource(&pdev->dev, res); | |
522 | if (IS_ERR(thermal->regs)) | |
523 | return PTR_ERR(thermal->regs); | |
524 | ||
525 | thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); | |
526 | if (IS_ERR(thermal->reset)) { | |
527 | error = PTR_ERR(thermal->reset); | |
528 | dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); | |
529 | return error; | |
530 | } | |
531 | ||
532 | thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); | |
533 | if (IS_ERR(thermal->clk)) { | |
534 | error = PTR_ERR(thermal->clk); | |
535 | dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); | |
536 | return error; | |
537 | } | |
538 | ||
539 | thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | |
540 | if (IS_ERR(thermal->pclk)) { | |
0d0a2bf6 | 541 | error = PTR_ERR(thermal->pclk); |
cbac8f63 CW |
542 | dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", |
543 | error); | |
544 | return error; | |
545 | } | |
546 | ||
547 | error = clk_prepare_enable(thermal->clk); | |
548 | if (error) { | |
549 | dev_err(&pdev->dev, "failed to enable converter clock: %d\n", | |
550 | error); | |
551 | return error; | |
552 | } | |
553 | ||
554 | error = clk_prepare_enable(thermal->pclk); | |
555 | if (error) { | |
556 | dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); | |
557 | goto err_disable_clk; | |
558 | } | |
559 | ||
560 | rockchip_thermal_reset_controller(thermal->reset); | |
561 | ||
562 | error = rockchip_configure_from_dt(&pdev->dev, np, thermal); | |
563 | if (error) { | |
564 | dev_err(&pdev->dev, "failed to parse device tree data: %d\n", | |
565 | error); | |
566 | goto err_disable_pclk; | |
567 | } | |
568 | ||
569 | thermal->chip->initialize(thermal->regs, thermal->tshut_polarity); | |
570 | ||
1d98b618 CW |
571 | for (i = 0; i < thermal->chip->chn_num; i++) { |
572 | error = rockchip_thermal_register_sensor(pdev, thermal, | |
573 | &thermal->sensors[i], | |
574 | thermal->chip->chn_id[i]); | |
575 | if (error) { | |
576 | dev_err(&pdev->dev, | |
577 | "failed to register sensor[%d] : error = %d\n", | |
578 | i, error); | |
579 | for (j = 0; j < i; j++) | |
580 | thermal_zone_of_sensor_unregister(&pdev->dev, | |
581 | thermal->sensors[j].tzd); | |
582 | goto err_disable_pclk; | |
583 | } | |
cbac8f63 CW |
584 | } |
585 | ||
586 | error = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
587 | &rockchip_thermal_alarm_irq_thread, | |
588 | IRQF_ONESHOT, | |
589 | "rockchip_thermal", thermal); | |
590 | if (error) { | |
591 | dev_err(&pdev->dev, | |
592 | "failed to request tsadc irq: %d\n", error); | |
1d98b618 | 593 | goto err_unregister_sensor; |
cbac8f63 CW |
594 | } |
595 | ||
596 | thermal->chip->control(thermal->regs, true); | |
597 | ||
1d98b618 | 598 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
599 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
600 | ||
601 | platform_set_drvdata(pdev, thermal); | |
602 | ||
603 | return 0; | |
604 | ||
1d98b618 CW |
605 | err_unregister_sensor: |
606 | while (i--) | |
607 | thermal_zone_of_sensor_unregister(&pdev->dev, | |
608 | thermal->sensors[i].tzd); | |
609 | ||
cbac8f63 CW |
610 | err_disable_pclk: |
611 | clk_disable_unprepare(thermal->pclk); | |
612 | err_disable_clk: | |
613 | clk_disable_unprepare(thermal->clk); | |
614 | ||
615 | return error; | |
616 | } | |
617 | ||
618 | static int rockchip_thermal_remove(struct platform_device *pdev) | |
619 | { | |
620 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
621 | int i; | |
622 | ||
1d98b618 | 623 | for (i = 0; i < thermal->chip->chn_num; i++) { |
cbac8f63 CW |
624 | struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; |
625 | ||
626 | rockchip_thermal_toggle_sensor(sensor, false); | |
627 | thermal_zone_of_sensor_unregister(&pdev->dev, sensor->tzd); | |
628 | } | |
629 | ||
630 | thermal->chip->control(thermal->regs, false); | |
631 | ||
632 | clk_disable_unprepare(thermal->pclk); | |
633 | clk_disable_unprepare(thermal->clk); | |
634 | ||
635 | return 0; | |
636 | } | |
637 | ||
638 | static int __maybe_unused rockchip_thermal_suspend(struct device *dev) | |
639 | { | |
640 | struct platform_device *pdev = to_platform_device(dev); | |
641 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
642 | int i; | |
643 | ||
1d98b618 | 644 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
645 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], false); |
646 | ||
647 | thermal->chip->control(thermal->regs, false); | |
648 | ||
649 | clk_disable(thermal->pclk); | |
650 | clk_disable(thermal->clk); | |
651 | ||
7e38a5b1 CW |
652 | pinctrl_pm_select_sleep_state(dev); |
653 | ||
cbac8f63 CW |
654 | return 0; |
655 | } | |
656 | ||
657 | static int __maybe_unused rockchip_thermal_resume(struct device *dev) | |
658 | { | |
659 | struct platform_device *pdev = to_platform_device(dev); | |
660 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
661 | int i; | |
662 | int error; | |
663 | ||
664 | error = clk_enable(thermal->clk); | |
665 | if (error) | |
666 | return error; | |
667 | ||
668 | error = clk_enable(thermal->pclk); | |
669 | if (error) | |
670 | return error; | |
671 | ||
672 | rockchip_thermal_reset_controller(thermal->reset); | |
673 | ||
674 | thermal->chip->initialize(thermal->regs, thermal->tshut_polarity); | |
675 | ||
1d98b618 CW |
676 | for (i = 0; i < thermal->chip->chn_num; i++) { |
677 | int id = thermal->sensors[i].id; | |
cbac8f63 CW |
678 | |
679 | thermal->chip->set_tshut_mode(id, thermal->regs, | |
680 | thermal->tshut_mode); | |
681 | thermal->chip->set_tshut_temp(id, thermal->regs, | |
682 | thermal->tshut_temp); | |
683 | } | |
684 | ||
685 | thermal->chip->control(thermal->regs, true); | |
686 | ||
1d98b618 | 687 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
688 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
689 | ||
7e38a5b1 CW |
690 | pinctrl_pm_select_default_state(dev); |
691 | ||
cbac8f63 CW |
692 | return 0; |
693 | } | |
694 | ||
695 | static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops, | |
696 | rockchip_thermal_suspend, rockchip_thermal_resume); | |
697 | ||
698 | static struct platform_driver rockchip_thermal_driver = { | |
699 | .driver = { | |
700 | .name = "rockchip-thermal", | |
cbac8f63 CW |
701 | .pm = &rockchip_thermal_pm_ops, |
702 | .of_match_table = of_rockchip_thermal_match, | |
703 | }, | |
704 | .probe = rockchip_thermal_probe, | |
705 | .remove = rockchip_thermal_remove, | |
706 | }; | |
707 | ||
708 | module_platform_driver(rockchip_thermal_driver); | |
709 | ||
710 | MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver"); | |
711 | MODULE_AUTHOR("Rockchip, Inc."); | |
712 | MODULE_LICENSE("GPL v2"); | |
713 | MODULE_ALIAS("platform:rockchip-thermal"); |