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Commit | Line | Data |
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2025cf9e | 1 | // SPDX-License-Identifier: GPL-2.0-only |
cbac8f63 | 2 | /* |
678065d5 | 3 | * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd |
20f0af75 | 4 | * Caesar Wang <wxt@rock-chips.com> |
cbac8f63 CW |
5 | */ |
6 | ||
7 | #include <linux/clk.h> | |
8 | #include <linux/delay.h> | |
9 | #include <linux/interrupt.h> | |
10 | #include <linux/io.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/of.h> | |
13 | #include <linux/of_address.h> | |
14 | #include <linux/of_irq.h> | |
15 | #include <linux/platform_device.h> | |
b9484763 | 16 | #include <linux/regmap.h> |
cbac8f63 CW |
17 | #include <linux/reset.h> |
18 | #include <linux/thermal.h> | |
b9484763 | 19 | #include <linux/mfd/syscon.h> |
c970872e | 20 | #include <linux/pinctrl/consumer.h> |
cbac8f63 | 21 | |
66ec4bfc | 22 | /* |
cbac8f63 CW |
23 | * If the temperature over a period of time High, |
24 | * the resulting TSHUT gave CRU module,let it reset the entire chip, | |
25 | * or via GPIO give PMIC. | |
26 | */ | |
27 | enum tshut_mode { | |
28 | TSHUT_MODE_CRU = 0, | |
29 | TSHUT_MODE_GPIO, | |
30 | }; | |
31 | ||
66ec4bfc | 32 | /* |
13c1cfda | 33 | * The system Temperature Sensors tshut(tshut) polarity |
cbac8f63 CW |
34 | * the bit 8 is tshut polarity. |
35 | * 0: low active, 1: high active | |
36 | */ | |
37 | enum tshut_polarity { | |
38 | TSHUT_LOW_ACTIVE = 0, | |
39 | TSHUT_HIGH_ACTIVE, | |
40 | }; | |
41 | ||
66ec4bfc | 42 | /* |
13c1cfda | 43 | * The conversion table has the adc value and temperature. |
952418a3 CW |
44 | * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) |
45 | * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) | |
13c1cfda | 46 | */ |
020ba95d CW |
47 | enum adc_sort_mode { |
48 | ADC_DECREMENT = 0, | |
49 | ADC_INCREMENT, | |
50 | }; | |
51 | ||
d27970b8 SS |
52 | #include "thermal_hwmon.h" |
53 | ||
13c1cfda | 54 | /** |
678065d5 | 55 | * struct chip_tsadc_table - hold information about chip-specific differences |
13c1cfda CW |
56 | * @id: conversion table |
57 | * @length: size of conversion table | |
58 | * @data_mask: mask to apply on data inputs | |
59 | * @mode: sort mode of this adc variant (incrementing or decrementing) | |
60 | */ | |
ce74110d CW |
61 | struct chip_tsadc_table { |
62 | const struct tsadc_table *id; | |
ce74110d | 63 | unsigned int length; |
ce74110d | 64 | u32 data_mask; |
020ba95d | 65 | enum adc_sort_mode mode; |
ce74110d CW |
66 | }; |
67 | ||
678065d5 CW |
68 | /** |
69 | * struct rockchip_tsadc_chip - hold the private data of tsadc chip | |
f7cef1b7 | 70 | * @chn_offset: the channel offset of the first channel |
678065d5 CW |
71 | * @chn_num: the channel number of tsadc chip |
72 | * @tshut_temp: the hardware-controlled shutdown temperature value | |
73 | * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) | |
74 | * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) | |
75 | * @initialize: SoC special initialize tsadc controller method | |
76 | * @irq_ack: clear the interrupt | |
66ec4bfc | 77 | * @control: enable/disable method for the tsadc controller |
678065d5 | 78 | * @get_temp: get the temperature |
14848502 | 79 | * @set_alarm_temp: set the high temperature interrupt |
678065d5 CW |
80 | * @set_tshut_temp: set the hardware-controlled shutdown temperature |
81 | * @set_tshut_mode: set the hardware-controlled shutdown mode | |
82 | * @table: the chip-specific conversion table | |
83 | */ | |
cbac8f63 | 84 | struct rockchip_tsadc_chip { |
1d98b618 | 85 | /* The sensor id of chip correspond to the ADC channel */ |
f7cef1b7 | 86 | int chn_offset; |
1d98b618 CW |
87 | int chn_num; |
88 | ||
cbac8f63 | 89 | /* The hardware-controlled tshut property */ |
437df217 | 90 | int tshut_temp; |
cbac8f63 CW |
91 | enum tshut_mode tshut_mode; |
92 | enum tshut_polarity tshut_polarity; | |
93 | ||
94 | /* Chip-wide methods */ | |
b9484763 CW |
95 | void (*initialize)(struct regmap *grf, |
96 | void __iomem *reg, enum tshut_polarity p); | |
cbac8f63 CW |
97 | void (*irq_ack)(void __iomem *reg); |
98 | void (*control)(void __iomem *reg, bool on); | |
99 | ||
100 | /* Per-sensor methods */ | |
cdd8b3f7 | 101 | int (*get_temp)(const struct chip_tsadc_table *table, |
ce74110d | 102 | int chn, void __iomem *reg, int *temp); |
d3530497 CW |
103 | int (*set_alarm_temp)(const struct chip_tsadc_table *table, |
104 | int chn, void __iomem *reg, int temp); | |
105 | int (*set_tshut_temp)(const struct chip_tsadc_table *table, | |
106 | int chn, void __iomem *reg, int temp); | |
cbac8f63 | 107 | void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); |
ce74110d CW |
108 | |
109 | /* Per-table methods */ | |
110 | struct chip_tsadc_table table; | |
cbac8f63 CW |
111 | }; |
112 | ||
678065d5 CW |
113 | /** |
114 | * struct rockchip_thermal_sensor - hold the information of thermal sensor | |
115 | * @thermal: pointer to the platform/configuration data | |
116 | * @tzd: pointer to a thermal zone | |
117 | * @id: identifier of the thermal sensor | |
118 | */ | |
cbac8f63 CW |
119 | struct rockchip_thermal_sensor { |
120 | struct rockchip_thermal_data *thermal; | |
121 | struct thermal_zone_device *tzd; | |
1d98b618 | 122 | int id; |
cbac8f63 CW |
123 | }; |
124 | ||
678065d5 CW |
125 | /** |
126 | * struct rockchip_thermal_data - hold the private data of thermal driver | |
127 | * @chip: pointer to the platform/configuration data | |
128 | * @pdev: platform device of thermal | |
129 | * @reset: the reset controller of tsadc | |
66ec4bfc | 130 | * @sensors: array of thermal sensors |
678065d5 CW |
131 | * @clk: the controller clock is divided by the exteral 24MHz |
132 | * @pclk: the advanced peripherals bus clock | |
133 | * @grf: the general register file will be used to do static set by software | |
134 | * @regs: the base address of tsadc controller | |
135 | * @tshut_temp: the hardware-controlled shutdown temperature value | |
136 | * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) | |
137 | * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) | |
138 | */ | |
cbac8f63 CW |
139 | struct rockchip_thermal_data { |
140 | const struct rockchip_tsadc_chip *chip; | |
141 | struct platform_device *pdev; | |
142 | struct reset_control *reset; | |
143 | ||
267f5965 | 144 | struct rockchip_thermal_sensor *sensors; |
cbac8f63 CW |
145 | |
146 | struct clk *clk; | |
147 | struct clk *pclk; | |
148 | ||
b9484763 | 149 | struct regmap *grf; |
cbac8f63 CW |
150 | void __iomem *regs; |
151 | ||
437df217 | 152 | int tshut_temp; |
cbac8f63 CW |
153 | enum tshut_mode tshut_mode; |
154 | enum tshut_polarity tshut_polarity; | |
155 | }; | |
156 | ||
6d5dad7b | 157 | /* |
952418a3 CW |
158 | * TSADC Sensor Register description: |
159 | * | |
160 | * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it. | |
161 | * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399) | |
162 | * | |
163 | */ | |
b9484763 | 164 | #define TSADCV2_USER_CON 0x00 |
cbac8f63 CW |
165 | #define TSADCV2_AUTO_CON 0x04 |
166 | #define TSADCV2_INT_EN 0x08 | |
167 | #define TSADCV2_INT_PD 0x0c | |
168 | #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) | |
14848502 | 169 | #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) |
cbac8f63 CW |
170 | #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) |
171 | #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 | |
172 | #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 | |
173 | #define TSADCV2_AUTO_PERIOD 0x68 | |
174 | #define TSADCV2_AUTO_PERIOD_HT 0x6c | |
175 | ||
176 | #define TSADCV2_AUTO_EN BIT(0) | |
cbac8f63 CW |
177 | #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) |
178 | #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) | |
678065d5 | 179 | |
7ea38c6c | 180 | #define TSADCV3_AUTO_Q_SEL_EN BIT(1) |
cbac8f63 CW |
181 | |
182 | #define TSADCV2_INT_SRC_EN(chn) BIT(chn) | |
183 | #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) | |
184 | #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) | |
185 | ||
452e01b3 | 186 | #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) |
952418a3 | 187 | #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) |
cbac8f63 CW |
188 | |
189 | #define TSADCV2_DATA_MASK 0xfff | |
20f0af75 CW |
190 | #define TSADCV3_DATA_MASK 0x3ff |
191 | ||
cbac8f63 CW |
192 | #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 |
193 | #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 | |
46667879 CW |
194 | #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */ |
195 | #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */ | |
5ef62de7 RH |
196 | #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */ |
197 | #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */ | |
46667879 | 198 | |
16bee043 FX |
199 | #define TSADCV5_AUTO_PERIOD_TIME 1622 /* 2.5ms */ |
200 | #define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */ | |
201 | ||
b9484763 | 202 | #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ |
16bee043 | 203 | #define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */ |
b9484763 CW |
204 | |
205 | #define GRF_SARADC_TESTBIT 0x0e644 | |
206 | #define GRF_TSADC_TESTBIT_L 0x0e648 | |
207 | #define GRF_TSADC_TESTBIT_H 0x0e64c | |
208 | ||
ffd1b122 EZ |
209 | #define PX30_GRF_SOC_CON2 0x0408 |
210 | ||
16bee043 FX |
211 | #define RK3568_GRF_TSADC_CON 0x0600 |
212 | #define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0) | |
213 | #define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1) | |
214 | #define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2) | |
215 | #define RK3568_GRF_TSADC_TSEN (0x10001 << 8) | |
216 | ||
b9484763 CW |
217 | #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) |
218 | #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) | |
23f75e48 RH |
219 | #define GRF_TSADC_VCM_EN_L (0x10001 << 7) |
220 | #define GRF_TSADC_VCM_EN_H (0x10001 << 7) | |
cbac8f63 | 221 | |
ffd1b122 EZ |
222 | #define GRF_CON_TSADC_CH_INV (0x10001 << 1) |
223 | ||
7b02a5e7 | 224 | /** |
678065d5 CW |
225 | * struct tsadc_table - code to temperature conversion table |
226 | * @code: the value of adc channel | |
227 | * @temp: the temperature | |
7b02a5e7 | 228 | * Note: |
678065d5 | 229 | * code to temperature mapping of the temperature sensor is a piece wise linear |
7b02a5e7 CW |
230 | * curve.Any temperature, code faling between to 2 give temperatures can be |
231 | * linearly interpolated. | |
678065d5 | 232 | * Code to Temperature mapping should be updated based on manufacturer results. |
7b02a5e7 | 233 | */ |
678065d5 CW |
234 | struct tsadc_table { |
235 | u32 code; | |
236 | int temp; | |
237 | }; | |
238 | ||
4eca8cac RH |
239 | static const struct tsadc_table rv1108_table[] = { |
240 | {0, -40000}, | |
241 | {374, -40000}, | |
242 | {382, -35000}, | |
243 | {389, -30000}, | |
244 | {397, -25000}, | |
245 | {405, -20000}, | |
246 | {413, -15000}, | |
247 | {421, -10000}, | |
248 | {429, -5000}, | |
249 | {436, 0}, | |
250 | {444, 5000}, | |
251 | {452, 10000}, | |
252 | {460, 15000}, | |
253 | {468, 20000}, | |
254 | {476, 25000}, | |
255 | {483, 30000}, | |
256 | {491, 35000}, | |
257 | {499, 40000}, | |
258 | {507, 45000}, | |
259 | {515, 50000}, | |
260 | {523, 55000}, | |
261 | {531, 60000}, | |
262 | {539, 65000}, | |
263 | {547, 70000}, | |
264 | {555, 75000}, | |
265 | {562, 80000}, | |
266 | {570, 85000}, | |
267 | {578, 90000}, | |
268 | {586, 95000}, | |
269 | {594, 100000}, | |
270 | {602, 105000}, | |
271 | {610, 110000}, | |
272 | {618, 115000}, | |
273 | {626, 120000}, | |
274 | {634, 125000}, | |
275 | {TSADCV2_DATA_MASK, 125000}, | |
276 | }; | |
277 | ||
952418a3 | 278 | static const struct tsadc_table rk3228_code_table[] = { |
7ea38c6c CW |
279 | {0, -40000}, |
280 | {588, -40000}, | |
281 | {593, -35000}, | |
282 | {598, -30000}, | |
283 | {603, -25000}, | |
284 | {608, -20000}, | |
285 | {613, -15000}, | |
286 | {618, -10000}, | |
287 | {623, -5000}, | |
288 | {629, 0}, | |
289 | {634, 5000}, | |
290 | {639, 10000}, | |
291 | {644, 15000}, | |
292 | {649, 20000}, | |
293 | {654, 25000}, | |
294 | {660, 30000}, | |
295 | {665, 35000}, | |
296 | {670, 40000}, | |
297 | {675, 45000}, | |
298 | {681, 50000}, | |
299 | {686, 55000}, | |
300 | {691, 60000}, | |
301 | {696, 65000}, | |
302 | {702, 70000}, | |
303 | {707, 75000}, | |
304 | {712, 80000}, | |
305 | {717, 85000}, | |
306 | {723, 90000}, | |
307 | {728, 95000}, | |
308 | {733, 100000}, | |
309 | {738, 105000}, | |
310 | {744, 110000}, | |
311 | {749, 115000}, | |
312 | {754, 120000}, | |
313 | {760, 125000}, | |
314 | {TSADCV2_DATA_MASK, 125000}, | |
7b02a5e7 CW |
315 | }; |
316 | ||
952418a3 | 317 | static const struct tsadc_table rk3288_code_table[] = { |
cbac8f63 CW |
318 | {TSADCV2_DATA_MASK, -40000}, |
319 | {3800, -40000}, | |
320 | {3792, -35000}, | |
321 | {3783, -30000}, | |
322 | {3774, -25000}, | |
323 | {3765, -20000}, | |
324 | {3756, -15000}, | |
325 | {3747, -10000}, | |
326 | {3737, -5000}, | |
327 | {3728, 0}, | |
328 | {3718, 5000}, | |
329 | {3708, 10000}, | |
330 | {3698, 15000}, | |
331 | {3688, 20000}, | |
332 | {3678, 25000}, | |
333 | {3667, 30000}, | |
334 | {3656, 35000}, | |
335 | {3645, 40000}, | |
336 | {3634, 45000}, | |
337 | {3623, 50000}, | |
338 | {3611, 55000}, | |
339 | {3600, 60000}, | |
340 | {3588, 65000}, | |
341 | {3575, 70000}, | |
342 | {3563, 75000}, | |
343 | {3550, 80000}, | |
344 | {3537, 85000}, | |
345 | {3524, 90000}, | |
346 | {3510, 95000}, | |
347 | {3496, 100000}, | |
348 | {3482, 105000}, | |
349 | {3467, 110000}, | |
350 | {3452, 115000}, | |
351 | {3437, 120000}, | |
352 | {3421, 125000}, | |
cadf29dc | 353 | {0, 125000}, |
cbac8f63 CW |
354 | }; |
355 | ||
eda519d5 RH |
356 | static const struct tsadc_table rk3328_code_table[] = { |
357 | {0, -40000}, | |
358 | {296, -40000}, | |
359 | {304, -35000}, | |
360 | {313, -30000}, | |
361 | {331, -20000}, | |
362 | {340, -15000}, | |
363 | {349, -10000}, | |
364 | {359, -5000}, | |
365 | {368, 0}, | |
366 | {378, 5000}, | |
367 | {388, 10000}, | |
368 | {398, 15000}, | |
369 | {408, 20000}, | |
370 | {418, 25000}, | |
371 | {429, 30000}, | |
372 | {440, 35000}, | |
373 | {451, 40000}, | |
374 | {462, 45000}, | |
375 | {473, 50000}, | |
376 | {485, 55000}, | |
377 | {496, 60000}, | |
378 | {508, 65000}, | |
379 | {521, 70000}, | |
380 | {533, 75000}, | |
381 | {546, 80000}, | |
382 | {559, 85000}, | |
383 | {572, 90000}, | |
384 | {586, 95000}, | |
385 | {600, 100000}, | |
386 | {614, 105000}, | |
387 | {629, 110000}, | |
388 | {644, 115000}, | |
389 | {659, 120000}, | |
390 | {675, 125000}, | |
391 | {TSADCV2_DATA_MASK, 125000}, | |
392 | }; | |
393 | ||
952418a3 | 394 | static const struct tsadc_table rk3368_code_table[] = { |
20f0af75 CW |
395 | {0, -40000}, |
396 | {106, -40000}, | |
397 | {108, -35000}, | |
398 | {110, -30000}, | |
399 | {112, -25000}, | |
400 | {114, -20000}, | |
401 | {116, -15000}, | |
402 | {118, -10000}, | |
403 | {120, -5000}, | |
404 | {122, 0}, | |
405 | {124, 5000}, | |
406 | {126, 10000}, | |
407 | {128, 15000}, | |
408 | {130, 20000}, | |
409 | {132, 25000}, | |
410 | {134, 30000}, | |
411 | {136, 35000}, | |
412 | {138, 40000}, | |
413 | {140, 45000}, | |
414 | {142, 50000}, | |
415 | {144, 55000}, | |
416 | {146, 60000}, | |
417 | {148, 65000}, | |
418 | {150, 70000}, | |
419 | {152, 75000}, | |
420 | {154, 80000}, | |
421 | {156, 85000}, | |
422 | {158, 90000}, | |
423 | {160, 95000}, | |
424 | {162, 100000}, | |
425 | {163, 105000}, | |
426 | {165, 110000}, | |
427 | {167, 115000}, | |
428 | {169, 120000}, | |
429 | {171, 125000}, | |
430 | {TSADCV3_DATA_MASK, 125000}, | |
431 | }; | |
432 | ||
952418a3 | 433 | static const struct tsadc_table rk3399_code_table[] = { |
7ea38c6c | 434 | {0, -40000}, |
f762a35d CW |
435 | {402, -40000}, |
436 | {410, -35000}, | |
437 | {419, -30000}, | |
438 | {427, -25000}, | |
439 | {436, -20000}, | |
440 | {444, -15000}, | |
441 | {453, -10000}, | |
442 | {461, -5000}, | |
443 | {470, 0}, | |
444 | {478, 5000}, | |
445 | {487, 10000}, | |
446 | {496, 15000}, | |
447 | {504, 20000}, | |
448 | {513, 25000}, | |
449 | {521, 30000}, | |
450 | {530, 35000}, | |
451 | {538, 40000}, | |
452 | {547, 45000}, | |
453 | {555, 50000}, | |
454 | {564, 55000}, | |
455 | {573, 60000}, | |
456 | {581, 65000}, | |
457 | {590, 70000}, | |
458 | {599, 75000}, | |
459 | {607, 80000}, | |
460 | {616, 85000}, | |
461 | {624, 90000}, | |
462 | {633, 95000}, | |
463 | {642, 100000}, | |
464 | {650, 105000}, | |
465 | {659, 110000}, | |
466 | {668, 115000}, | |
467 | {677, 120000}, | |
468 | {685, 125000}, | |
7ea38c6c | 469 | {TSADCV3_DATA_MASK, 125000}, |
b0d70338 CW |
470 | }; |
471 | ||
16bee043 FX |
472 | static const struct tsadc_table rk3568_code_table[] = { |
473 | {0, -40000}, | |
474 | {1584, -40000}, | |
475 | {1620, -35000}, | |
476 | {1652, -30000}, | |
477 | {1688, -25000}, | |
478 | {1720, -20000}, | |
479 | {1756, -15000}, | |
480 | {1788, -10000}, | |
481 | {1824, -5000}, | |
482 | {1856, 0}, | |
483 | {1892, 5000}, | |
484 | {1924, 10000}, | |
485 | {1956, 15000}, | |
486 | {1992, 20000}, | |
487 | {2024, 25000}, | |
488 | {2060, 30000}, | |
489 | {2092, 35000}, | |
490 | {2128, 40000}, | |
491 | {2160, 45000}, | |
492 | {2196, 50000}, | |
493 | {2228, 55000}, | |
494 | {2264, 60000}, | |
495 | {2300, 65000}, | |
496 | {2332, 70000}, | |
497 | {2368, 75000}, | |
498 | {2400, 80000}, | |
499 | {2436, 85000}, | |
500 | {2468, 90000}, | |
501 | {2500, 95000}, | |
502 | {2536, 100000}, | |
503 | {2572, 105000}, | |
504 | {2604, 110000}, | |
505 | {2636, 115000}, | |
506 | {2672, 120000}, | |
507 | {2704, 125000}, | |
508 | {TSADCV2_DATA_MASK, 125000}, | |
509 | }; | |
510 | ||
cdd8b3f7 | 511 | static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table, |
437df217 | 512 | int temp) |
cbac8f63 CW |
513 | { |
514 | int high, low, mid; | |
cadf29dc CW |
515 | unsigned long num; |
516 | unsigned int denom; | |
d3530497 | 517 | u32 error = table->data_mask; |
cbac8f63 CW |
518 | |
519 | low = 0; | |
cadf29dc | 520 | high = (table->length - 1) - 1; /* ignore the last check for table */ |
cbac8f63 CW |
521 | mid = (high + low) / 2; |
522 | ||
1f09ba82 | 523 | /* Return mask code data when the temp is over table range */ |
d3530497 | 524 | if (temp < table->id[low].temp || temp > table->id[high].temp) |
1f09ba82 | 525 | goto exit; |
cbac8f63 CW |
526 | |
527 | while (low <= high) { | |
cdd8b3f7 BN |
528 | if (temp == table->id[mid].temp) |
529 | return table->id[mid].code; | |
530 | else if (temp < table->id[mid].temp) | |
cbac8f63 CW |
531 | high = mid - 1; |
532 | else | |
533 | low = mid + 1; | |
534 | mid = (low + high) / 2; | |
535 | } | |
536 | ||
cadf29dc CW |
537 | /* |
538 | * The conversion code granularity provided by the table. Let's | |
539 | * assume that the relationship between temperature and | |
540 | * analog value between 2 table entries is linear and interpolate | |
541 | * to produce less granular result. | |
542 | */ | |
543 | num = abs(table->id[mid + 1].code - table->id[mid].code); | |
544 | num *= temp - table->id[mid].temp; | |
545 | denom = table->id[mid + 1].temp - table->id[mid].temp; | |
546 | ||
547 | switch (table->mode) { | |
548 | case ADC_DECREMENT: | |
549 | return table->id[mid].code - (num / denom); | |
550 | case ADC_INCREMENT: | |
551 | return table->id[mid].code + (num / denom); | |
552 | default: | |
553 | pr_err("%s: unknown table mode: %d\n", __func__, table->mode); | |
554 | return error; | |
555 | } | |
556 | ||
1f09ba82 | 557 | exit: |
e6ed1b4a BN |
558 | pr_err("%s: invalid temperature, temp=%d error=%d\n", |
559 | __func__, temp, error); | |
1f09ba82 | 560 | return error; |
cbac8f63 CW |
561 | } |
562 | ||
cdd8b3f7 BN |
563 | static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table, |
564 | u32 code, int *temp) | |
cbac8f63 | 565 | { |
d9a241cb | 566 | unsigned int low = 1; |
cdd8b3f7 | 567 | unsigned int high = table->length - 1; |
1e9a1aea CW |
568 | unsigned int mid = (low + high) / 2; |
569 | unsigned int num; | |
570 | unsigned long denom; | |
571 | ||
cdd8b3f7 | 572 | WARN_ON(table->length < 2); |
1e9a1aea | 573 | |
cdd8b3f7 | 574 | switch (table->mode) { |
020ba95d | 575 | case ADC_DECREMENT: |
cdd8b3f7 | 576 | code &= table->data_mask; |
db831886 | 577 | if (code <= table->id[high].code) |
020ba95d CW |
578 | return -EAGAIN; /* Incorrect reading */ |
579 | ||
580 | while (low <= high) { | |
cdd8b3f7 BN |
581 | if (code >= table->id[mid].code && |
582 | code < table->id[mid - 1].code) | |
020ba95d | 583 | break; |
cdd8b3f7 | 584 | else if (code < table->id[mid].code) |
020ba95d CW |
585 | low = mid + 1; |
586 | else | |
587 | high = mid - 1; | |
588 | ||
589 | mid = (low + high) / 2; | |
590 | } | |
591 | break; | |
592 | case ADC_INCREMENT: | |
cdd8b3f7 BN |
593 | code &= table->data_mask; |
594 | if (code < table->id[low].code) | |
020ba95d CW |
595 | return -EAGAIN; /* Incorrect reading */ |
596 | ||
597 | while (low <= high) { | |
cdd8b3f7 BN |
598 | if (code <= table->id[mid].code && |
599 | code > table->id[mid - 1].code) | |
020ba95d | 600 | break; |
cdd8b3f7 | 601 | else if (code > table->id[mid].code) |
020ba95d CW |
602 | low = mid + 1; |
603 | else | |
604 | high = mid - 1; | |
605 | ||
606 | mid = (low + high) / 2; | |
607 | } | |
608 | break; | |
609 | default: | |
cdd8b3f7 | 610 | pr_err("%s: unknown table mode: %d\n", __func__, table->mode); |
e6ed1b4a | 611 | return -EINVAL; |
cbac8f63 CW |
612 | } |
613 | ||
1e9a1aea CW |
614 | /* |
615 | * The 5C granularity provided by the table is too much. Let's | |
616 | * assume that the relationship between sensor readings and | |
617 | * temperature between 2 table entries is linear and interpolate | |
618 | * to produce less granular result. | |
619 | */ | |
cdd8b3f7 BN |
620 | num = table->id[mid].temp - table->id[mid - 1].temp; |
621 | num *= abs(table->id[mid - 1].code - code); | |
622 | denom = abs(table->id[mid - 1].code - table->id[mid].code); | |
623 | *temp = table->id[mid - 1].temp + (num / denom); | |
d9a241cb DT |
624 | |
625 | return 0; | |
cbac8f63 CW |
626 | } |
627 | ||
628 | /** | |
144c5565 | 629 | * rk_tsadcv2_initialize - initialize TASDC Controller. |
66ec4bfc AK |
630 | * @grf: the general register file will be used to do static set by software |
631 | * @regs: the base address of tsadc controller | |
632 | * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) | |
144c5565 CW |
633 | * |
634 | * (1) Set TSADC_V2_AUTO_PERIOD: | |
635 | * Configure the interleave between every two accessing of | |
636 | * TSADC in normal operation. | |
637 | * | |
638 | * (2) Set TSADCV2_AUTO_PERIOD_HT: | |
639 | * Configure the interleave between every two accessing of | |
640 | * TSADC after the temperature is higher than COM_SHUT or COM_INT. | |
641 | * | |
642 | * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: | |
643 | * If the temperature is higher than COMP_INT or COMP_SHUT for | |
644 | * "debounce" times, TSADC controller will generate interrupt or TSHUT. | |
cbac8f63 | 645 | */ |
b9484763 | 646 | static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs, |
cbac8f63 CW |
647 | enum tshut_polarity tshut_polarity) |
648 | { | |
649 | if (tshut_polarity == TSHUT_HIGH_ACTIVE) | |
452e01b3 | 650 | writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
cbac8f63 CW |
651 | regs + TSADCV2_AUTO_CON); |
652 | else | |
452e01b3 | 653 | writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
cbac8f63 CW |
654 | regs + TSADCV2_AUTO_CON); |
655 | ||
656 | writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); | |
657 | writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, | |
658 | regs + TSADCV2_HIGHT_INT_DEBOUNCE); | |
659 | writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, | |
660 | regs + TSADCV2_AUTO_PERIOD_HT); | |
661 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, | |
662 | regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); | |
b9484763 CW |
663 | } |
664 | ||
665 | /** | |
666 | * rk_tsadcv3_initialize - initialize TASDC Controller. | |
66ec4bfc AK |
667 | * @grf: the general register file will be used to do static set by software |
668 | * @regs: the base address of tsadc controller | |
669 | * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) | |
678065d5 | 670 | * |
b9484763 CW |
671 | * (1) The tsadc control power sequence. |
672 | * | |
673 | * (2) Set TSADC_V2_AUTO_PERIOD: | |
674 | * Configure the interleave between every two accessing of | |
675 | * TSADC in normal operation. | |
676 | * | |
677 | * (2) Set TSADCV2_AUTO_PERIOD_HT: | |
678 | * Configure the interleave between every two accessing of | |
679 | * TSADC after the temperature is higher than COM_SHUT or COM_INT. | |
680 | * | |
681 | * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: | |
682 | * If the temperature is higher than COMP_INT or COMP_SHUT for | |
683 | * "debounce" times, TSADC controller will generate interrupt or TSHUT. | |
684 | */ | |
685 | static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs, | |
686 | enum tshut_polarity tshut_polarity) | |
687 | { | |
688 | /* The tsadc control power sequence */ | |
689 | if (IS_ERR(grf)) { | |
690 | /* Set interleave value to workround ic time sync issue */ | |
691 | writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs + | |
692 | TSADCV2_USER_CON); | |
46667879 CW |
693 | |
694 | writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, | |
695 | regs + TSADCV2_AUTO_PERIOD); | |
696 | writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, | |
697 | regs + TSADCV2_HIGHT_INT_DEBOUNCE); | |
698 | writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, | |
699 | regs + TSADCV2_AUTO_PERIOD_HT); | |
700 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, | |
701 | regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); | |
702 | ||
b9484763 | 703 | } else { |
23f75e48 RH |
704 | /* Enable the voltage common mode feature */ |
705 | regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L); | |
706 | regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H); | |
707 | ||
2fe5c1b0 | 708 | usleep_range(15, 100); /* The spec note says at least 15 us */ |
b9484763 CW |
709 | regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON); |
710 | regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON); | |
2fe5c1b0 | 711 | usleep_range(90, 200); /* The spec note says at least 90 us */ |
46667879 CW |
712 | |
713 | writel_relaxed(TSADCV3_AUTO_PERIOD_TIME, | |
714 | regs + TSADCV2_AUTO_PERIOD); | |
715 | writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, | |
716 | regs + TSADCV2_HIGHT_INT_DEBOUNCE); | |
717 | writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME, | |
718 | regs + TSADCV2_AUTO_PERIOD_HT); | |
719 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, | |
720 | regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); | |
b9484763 CW |
721 | } |
722 | ||
723 | if (tshut_polarity == TSHUT_HIGH_ACTIVE) | |
724 | writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, | |
725 | regs + TSADCV2_AUTO_CON); | |
726 | else | |
727 | writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, | |
728 | regs + TSADCV2_AUTO_CON); | |
cbac8f63 CW |
729 | } |
730 | ||
ffd1b122 EZ |
731 | static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs, |
732 | enum tshut_polarity tshut_polarity) | |
733 | { | |
734 | rk_tsadcv2_initialize(grf, regs, tshut_polarity); | |
735 | regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV); | |
736 | } | |
737 | ||
16bee043 FX |
738 | static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs, |
739 | enum tshut_polarity tshut_polarity) | |
740 | { | |
741 | writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON); | |
742 | writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); | |
743 | writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, | |
744 | regs + TSADCV2_HIGHT_INT_DEBOUNCE); | |
745 | writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME, | |
746 | regs + TSADCV2_AUTO_PERIOD_HT); | |
747 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, | |
748 | regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); | |
749 | ||
750 | if (tshut_polarity == TSHUT_HIGH_ACTIVE) | |
751 | writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, | |
752 | regs + TSADCV2_AUTO_CON); | |
753 | else | |
754 | writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, | |
755 | regs + TSADCV2_AUTO_CON); | |
756 | ||
757 | /* | |
758 | * The general register file will is optional | |
759 | * and might not be available. | |
760 | */ | |
761 | if (!IS_ERR(grf)) { | |
762 | regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN); | |
763 | /* | |
764 | * RK3568 TRM, section 18.5. requires a delay no less | |
765 | * than 10us between the rising edge of tsadc_tsen_en | |
766 | * and the rising edge of tsadc_ana_reg_0/1/2. | |
767 | */ | |
768 | udelay(15); | |
769 | regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0); | |
770 | regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1); | |
771 | regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2); | |
772 | ||
773 | /* | |
774 | * RK3568 TRM, section 18.5. requires a delay no less | |
775 | * than 90us after the rising edge of tsadc_ana_reg_0/1/2. | |
776 | */ | |
777 | usleep_range(100, 200); | |
778 | } | |
779 | } | |
780 | ||
952418a3 | 781 | static void rk_tsadcv2_irq_ack(void __iomem *regs) |
7b02a5e7 CW |
782 | { |
783 | u32 val; | |
784 | ||
785 | val = readl_relaxed(regs + TSADCV2_INT_PD); | |
952418a3 | 786 | writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); |
7b02a5e7 CW |
787 | } |
788 | ||
952418a3 | 789 | static void rk_tsadcv3_irq_ack(void __iomem *regs) |
cbac8f63 CW |
790 | { |
791 | u32 val; | |
792 | ||
793 | val = readl_relaxed(regs + TSADCV2_INT_PD); | |
952418a3 | 794 | writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); |
cbac8f63 CW |
795 | } |
796 | ||
797 | static void rk_tsadcv2_control(void __iomem *regs, bool enable) | |
798 | { | |
799 | u32 val; | |
800 | ||
801 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
802 | if (enable) | |
803 | val |= TSADCV2_AUTO_EN; | |
804 | else | |
805 | val &= ~TSADCV2_AUTO_EN; | |
806 | ||
807 | writel_relaxed(val, regs + TSADCV2_AUTO_CON); | |
808 | } | |
809 | ||
7ea38c6c | 810 | /** |
678065d5 | 811 | * rk_tsadcv3_control - the tsadc controller is enabled or disabled. |
66ec4bfc AK |
812 | * @regs: the base address of tsadc controller |
813 | * @enable: boolean flag to enable the controller | |
678065d5 CW |
814 | * |
815 | * NOTE: TSADC controller works at auto mode, and some SoCs need set the | |
816 | * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output | |
817 | * adc value if setting this bit to enable. | |
7ea38c6c CW |
818 | */ |
819 | static void rk_tsadcv3_control(void __iomem *regs, bool enable) | |
820 | { | |
821 | u32 val; | |
822 | ||
823 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
824 | if (enable) | |
825 | val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; | |
826 | else | |
827 | val &= ~TSADCV2_AUTO_EN; | |
828 | ||
829 | writel_relaxed(val, regs + TSADCV2_AUTO_CON); | |
830 | } | |
831 | ||
cdd8b3f7 | 832 | static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, |
ce74110d | 833 | int chn, void __iomem *regs, int *temp) |
cbac8f63 CW |
834 | { |
835 | u32 val; | |
836 | ||
cbac8f63 | 837 | val = readl_relaxed(regs + TSADCV2_DATA(chn)); |
cbac8f63 | 838 | |
ce74110d | 839 | return rk_tsadcv2_code_to_temp(table, val, temp); |
cbac8f63 CW |
840 | } |
841 | ||
d3530497 CW |
842 | static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, |
843 | int chn, void __iomem *regs, int temp) | |
14848502 | 844 | { |
18591add CW |
845 | u32 alarm_value; |
846 | u32 int_en, int_clr; | |
847 | ||
848 | /* | |
849 | * In some cases, some sensors didn't need the trip points, the | |
850 | * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm | |
851 | * in the end, ignore this case and disable the high temperature | |
852 | * interrupt. | |
853 | */ | |
854 | if (temp == INT_MAX) { | |
855 | int_clr = readl_relaxed(regs + TSADCV2_INT_EN); | |
856 | int_clr &= ~TSADCV2_INT_SRC_EN(chn); | |
857 | writel_relaxed(int_clr, regs + TSADCV2_INT_EN); | |
858 | return 0; | |
859 | } | |
14848502 | 860 | |
1f09ba82 | 861 | /* Make sure the value is valid */ |
14848502 | 862 | alarm_value = rk_tsadcv2_temp_to_code(table, temp); |
cdd8b3f7 | 863 | if (alarm_value == table->data_mask) |
d3530497 | 864 | return -ERANGE; |
1f09ba82 | 865 | |
cdd8b3f7 | 866 | writel_relaxed(alarm_value & table->data_mask, |
14848502 CW |
867 | regs + TSADCV2_COMP_INT(chn)); |
868 | ||
869 | int_en = readl_relaxed(regs + TSADCV2_INT_EN); | |
870 | int_en |= TSADCV2_INT_SRC_EN(chn); | |
871 | writel_relaxed(int_en, regs + TSADCV2_INT_EN); | |
d3530497 CW |
872 | |
873 | return 0; | |
14848502 CW |
874 | } |
875 | ||
d3530497 CW |
876 | static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, |
877 | int chn, void __iomem *regs, int temp) | |
cbac8f63 CW |
878 | { |
879 | u32 tshut_value, val; | |
880 | ||
1f09ba82 | 881 | /* Make sure the value is valid */ |
ce74110d | 882 | tshut_value = rk_tsadcv2_temp_to_code(table, temp); |
cdd8b3f7 | 883 | if (tshut_value == table->data_mask) |
d3530497 | 884 | return -ERANGE; |
1f09ba82 | 885 | |
cbac8f63 CW |
886 | writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); |
887 | ||
888 | /* TSHUT will be valid */ | |
889 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
890 | writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); | |
d3530497 CW |
891 | |
892 | return 0; | |
cbac8f63 CW |
893 | } |
894 | ||
895 | static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, | |
896 | enum tshut_mode mode) | |
897 | { | |
898 | u32 val; | |
899 | ||
900 | val = readl_relaxed(regs + TSADCV2_INT_EN); | |
901 | if (mode == TSHUT_MODE_GPIO) { | |
902 | val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); | |
903 | val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); | |
904 | } else { | |
905 | val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); | |
906 | val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); | |
907 | } | |
908 | ||
909 | writel_relaxed(val, regs + TSADCV2_INT_EN); | |
910 | } | |
911 | ||
ffd1b122 | 912 | static const struct rockchip_tsadc_chip px30_tsadc_data = { |
f7cef1b7 SR |
913 | /* cpu, gpu */ |
914 | .chn_offset = 0, | |
ffd1b122 EZ |
915 | .chn_num = 2, /* 2 channels for tsadc */ |
916 | ||
917 | .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ | |
918 | .tshut_temp = 95000, | |
919 | ||
920 | .initialize = rk_tsadcv4_initialize, | |
921 | .irq_ack = rk_tsadcv3_irq_ack, | |
922 | .control = rk_tsadcv3_control, | |
923 | .get_temp = rk_tsadcv2_get_temp, | |
924 | .set_alarm_temp = rk_tsadcv2_alarm_temp, | |
925 | .set_tshut_temp = rk_tsadcv2_tshut_temp, | |
926 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
927 | ||
928 | .table = { | |
929 | .id = rk3328_code_table, | |
930 | .length = ARRAY_SIZE(rk3328_code_table), | |
931 | .data_mask = TSADCV2_DATA_MASK, | |
932 | .mode = ADC_INCREMENT, | |
933 | }, | |
934 | }; | |
935 | ||
4eca8cac | 936 | static const struct rockchip_tsadc_chip rv1108_tsadc_data = { |
f7cef1b7 SR |
937 | /* cpu */ |
938 | .chn_offset = 0, | |
4eca8cac RH |
939 | .chn_num = 1, /* one channel for tsadc */ |
940 | ||
941 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
942 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
943 | .tshut_temp = 95000, | |
944 | ||
945 | .initialize = rk_tsadcv2_initialize, | |
946 | .irq_ack = rk_tsadcv3_irq_ack, | |
947 | .control = rk_tsadcv3_control, | |
948 | .get_temp = rk_tsadcv2_get_temp, | |
949 | .set_alarm_temp = rk_tsadcv2_alarm_temp, | |
950 | .set_tshut_temp = rk_tsadcv2_tshut_temp, | |
951 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
952 | ||
953 | .table = { | |
954 | .id = rv1108_table, | |
955 | .length = ARRAY_SIZE(rv1108_table), | |
956 | .data_mask = TSADCV2_DATA_MASK, | |
957 | .mode = ADC_INCREMENT, | |
958 | }, | |
959 | }; | |
960 | ||
7b02a5e7 | 961 | static const struct rockchip_tsadc_chip rk3228_tsadc_data = { |
f7cef1b7 SR |
962 | /* cpu */ |
963 | .chn_offset = 0, | |
7b02a5e7 CW |
964 | .chn_num = 1, /* one channel for tsadc */ |
965 | ||
966 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
967 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
968 | .tshut_temp = 95000, | |
969 | ||
970 | .initialize = rk_tsadcv2_initialize, | |
952418a3 | 971 | .irq_ack = rk_tsadcv3_irq_ack, |
7ea38c6c | 972 | .control = rk_tsadcv3_control, |
7b02a5e7 | 973 | .get_temp = rk_tsadcv2_get_temp, |
14848502 | 974 | .set_alarm_temp = rk_tsadcv2_alarm_temp, |
7b02a5e7 CW |
975 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
976 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
977 | ||
978 | .table = { | |
952418a3 CW |
979 | .id = rk3228_code_table, |
980 | .length = ARRAY_SIZE(rk3228_code_table), | |
7b02a5e7 | 981 | .data_mask = TSADCV3_DATA_MASK, |
7ea38c6c | 982 | .mode = ADC_INCREMENT, |
7b02a5e7 CW |
983 | }, |
984 | }; | |
985 | ||
cbac8f63 | 986 | static const struct rockchip_tsadc_chip rk3288_tsadc_data = { |
f7cef1b7 SR |
987 | /* cpu, gpu */ |
988 | .chn_offset = 1, | |
1d98b618 CW |
989 | .chn_num = 2, /* two channels for tsadc */ |
990 | ||
cbac8f63 CW |
991 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
992 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
993 | .tshut_temp = 95000, | |
994 | ||
995 | .initialize = rk_tsadcv2_initialize, | |
996 | .irq_ack = rk_tsadcv2_irq_ack, | |
997 | .control = rk_tsadcv2_control, | |
998 | .get_temp = rk_tsadcv2_get_temp, | |
14848502 | 999 | .set_alarm_temp = rk_tsadcv2_alarm_temp, |
cbac8f63 CW |
1000 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
1001 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
ce74110d CW |
1002 | |
1003 | .table = { | |
952418a3 CW |
1004 | .id = rk3288_code_table, |
1005 | .length = ARRAY_SIZE(rk3288_code_table), | |
ce74110d | 1006 | .data_mask = TSADCV2_DATA_MASK, |
020ba95d | 1007 | .mode = ADC_DECREMENT, |
ce74110d | 1008 | }, |
cbac8f63 CW |
1009 | }; |
1010 | ||
eda519d5 | 1011 | static const struct rockchip_tsadc_chip rk3328_tsadc_data = { |
f7cef1b7 SR |
1012 | /* cpu */ |
1013 | .chn_offset = 0, | |
eda519d5 RH |
1014 | .chn_num = 1, /* one channels for tsadc */ |
1015 | ||
1016 | .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ | |
1017 | .tshut_temp = 95000, | |
1018 | ||
1019 | .initialize = rk_tsadcv2_initialize, | |
1020 | .irq_ack = rk_tsadcv3_irq_ack, | |
1021 | .control = rk_tsadcv3_control, | |
1022 | .get_temp = rk_tsadcv2_get_temp, | |
1023 | .set_alarm_temp = rk_tsadcv2_alarm_temp, | |
1024 | .set_tshut_temp = rk_tsadcv2_tshut_temp, | |
1025 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
1026 | ||
1027 | .table = { | |
1028 | .id = rk3328_code_table, | |
1029 | .length = ARRAY_SIZE(rk3328_code_table), | |
1030 | .data_mask = TSADCV2_DATA_MASK, | |
1031 | .mode = ADC_INCREMENT, | |
1032 | }, | |
1033 | }; | |
1034 | ||
1cd60269 | 1035 | static const struct rockchip_tsadc_chip rk3366_tsadc_data = { |
f7cef1b7 SR |
1036 | /* cpu, gpu */ |
1037 | .chn_offset = 0, | |
1cd60269 EZ |
1038 | .chn_num = 2, /* two channels for tsadc */ |
1039 | ||
1040 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
1041 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
1042 | .tshut_temp = 95000, | |
1043 | ||
1044 | .initialize = rk_tsadcv3_initialize, | |
1045 | .irq_ack = rk_tsadcv3_irq_ack, | |
1046 | .control = rk_tsadcv3_control, | |
1047 | .get_temp = rk_tsadcv2_get_temp, | |
14848502 | 1048 | .set_alarm_temp = rk_tsadcv2_alarm_temp, |
1cd60269 EZ |
1049 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
1050 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
1051 | ||
1052 | .table = { | |
1053 | .id = rk3228_code_table, | |
1054 | .length = ARRAY_SIZE(rk3228_code_table), | |
1055 | .data_mask = TSADCV3_DATA_MASK, | |
1056 | .mode = ADC_INCREMENT, | |
1057 | }, | |
1058 | }; | |
1059 | ||
20f0af75 | 1060 | static const struct rockchip_tsadc_chip rk3368_tsadc_data = { |
f7cef1b7 SR |
1061 | /* cpu, gpu */ |
1062 | .chn_offset = 0, | |
20f0af75 CW |
1063 | .chn_num = 2, /* two channels for tsadc */ |
1064 | ||
1065 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
1066 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
1067 | .tshut_temp = 95000, | |
1068 | ||
1069 | .initialize = rk_tsadcv2_initialize, | |
1070 | .irq_ack = rk_tsadcv2_irq_ack, | |
1071 | .control = rk_tsadcv2_control, | |
1072 | .get_temp = rk_tsadcv2_get_temp, | |
14848502 | 1073 | .set_alarm_temp = rk_tsadcv2_alarm_temp, |
20f0af75 CW |
1074 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
1075 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
1076 | ||
1077 | .table = { | |
952418a3 CW |
1078 | .id = rk3368_code_table, |
1079 | .length = ARRAY_SIZE(rk3368_code_table), | |
20f0af75 CW |
1080 | .data_mask = TSADCV3_DATA_MASK, |
1081 | .mode = ADC_INCREMENT, | |
1082 | }, | |
1083 | }; | |
1084 | ||
b0d70338 | 1085 | static const struct rockchip_tsadc_chip rk3399_tsadc_data = { |
f7cef1b7 SR |
1086 | /* cpu, gpu */ |
1087 | .chn_offset = 0, | |
b0d70338 CW |
1088 | .chn_num = 2, /* two channels for tsadc */ |
1089 | ||
1090 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
1091 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
1092 | .tshut_temp = 95000, | |
1093 | ||
b9484763 | 1094 | .initialize = rk_tsadcv3_initialize, |
952418a3 | 1095 | .irq_ack = rk_tsadcv3_irq_ack, |
7ea38c6c | 1096 | .control = rk_tsadcv3_control, |
b0d70338 | 1097 | .get_temp = rk_tsadcv2_get_temp, |
14848502 | 1098 | .set_alarm_temp = rk_tsadcv2_alarm_temp, |
b0d70338 CW |
1099 | .set_tshut_temp = rk_tsadcv2_tshut_temp, |
1100 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
1101 | ||
1102 | .table = { | |
952418a3 CW |
1103 | .id = rk3399_code_table, |
1104 | .length = ARRAY_SIZE(rk3399_code_table), | |
b0d70338 | 1105 | .data_mask = TSADCV3_DATA_MASK, |
7ea38c6c | 1106 | .mode = ADC_INCREMENT, |
b0d70338 CW |
1107 | }, |
1108 | }; | |
1109 | ||
16bee043 | 1110 | static const struct rockchip_tsadc_chip rk3568_tsadc_data = { |
f7cef1b7 SR |
1111 | /* cpu, gpu */ |
1112 | .chn_offset = 0, | |
16bee043 FX |
1113 | .chn_num = 2, /* two channels for tsadc */ |
1114 | ||
1115 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ | |
1116 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
1117 | .tshut_temp = 95000, | |
1118 | ||
1119 | .initialize = rk_tsadcv7_initialize, | |
1120 | .irq_ack = rk_tsadcv3_irq_ack, | |
1121 | .control = rk_tsadcv3_control, | |
1122 | .get_temp = rk_tsadcv2_get_temp, | |
1123 | .set_alarm_temp = rk_tsadcv2_alarm_temp, | |
1124 | .set_tshut_temp = rk_tsadcv2_tshut_temp, | |
1125 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
1126 | ||
1127 | .table = { | |
1128 | .id = rk3568_code_table, | |
1129 | .length = ARRAY_SIZE(rk3568_code_table), | |
1130 | .data_mask = TSADCV2_DATA_MASK, | |
1131 | .mode = ADC_INCREMENT, | |
1132 | }, | |
1133 | }; | |
1134 | ||
cbac8f63 | 1135 | static const struct of_device_id of_rockchip_thermal_match[] = { |
ffd1b122 EZ |
1136 | { .compatible = "rockchip,px30-tsadc", |
1137 | .data = (void *)&px30_tsadc_data, | |
1138 | }, | |
4eca8cac RH |
1139 | { |
1140 | .compatible = "rockchip,rv1108-tsadc", | |
1141 | .data = (void *)&rv1108_tsadc_data, | |
1142 | }, | |
7b02a5e7 CW |
1143 | { |
1144 | .compatible = "rockchip,rk3228-tsadc", | |
1145 | .data = (void *)&rk3228_tsadc_data, | |
1146 | }, | |
cbac8f63 CW |
1147 | { |
1148 | .compatible = "rockchip,rk3288-tsadc", | |
1149 | .data = (void *)&rk3288_tsadc_data, | |
1150 | }, | |
eda519d5 RH |
1151 | { |
1152 | .compatible = "rockchip,rk3328-tsadc", | |
1153 | .data = (void *)&rk3328_tsadc_data, | |
1154 | }, | |
1cd60269 EZ |
1155 | { |
1156 | .compatible = "rockchip,rk3366-tsadc", | |
1157 | .data = (void *)&rk3366_tsadc_data, | |
1158 | }, | |
20f0af75 CW |
1159 | { |
1160 | .compatible = "rockchip,rk3368-tsadc", | |
1161 | .data = (void *)&rk3368_tsadc_data, | |
1162 | }, | |
b0d70338 CW |
1163 | { |
1164 | .compatible = "rockchip,rk3399-tsadc", | |
1165 | .data = (void *)&rk3399_tsadc_data, | |
1166 | }, | |
16bee043 FX |
1167 | { |
1168 | .compatible = "rockchip,rk3568-tsadc", | |
1169 | .data = (void *)&rk3568_tsadc_data, | |
1170 | }, | |
cbac8f63 CW |
1171 | { /* end */ }, |
1172 | }; | |
1173 | MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); | |
1174 | ||
1175 | static void | |
1176 | rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on) | |
1177 | { | |
1178 | struct thermal_zone_device *tzd = sensor->tzd; | |
1179 | ||
7f4957be AP |
1180 | if (on) |
1181 | thermal_zone_device_enable(tzd); | |
1182 | else | |
1183 | thermal_zone_device_disable(tzd); | |
cbac8f63 CW |
1184 | } |
1185 | ||
1186 | static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) | |
1187 | { | |
1188 | struct rockchip_thermal_data *thermal = dev; | |
1189 | int i; | |
1190 | ||
1191 | dev_dbg(&thermal->pdev->dev, "thermal alarm\n"); | |
1192 | ||
1193 | thermal->chip->irq_ack(thermal->regs); | |
1194 | ||
1d98b618 | 1195 | for (i = 0; i < thermal->chip->chn_num; i++) |
0e70f466 SP |
1196 | thermal_zone_device_update(thermal->sensors[i].tzd, |
1197 | THERMAL_EVENT_UNSPECIFIED); | |
cbac8f63 CW |
1198 | |
1199 | return IRQ_HANDLED; | |
1200 | } | |
1201 | ||
90b2ca02 | 1202 | static int rockchip_thermal_set_trips(struct thermal_zone_device *tz, int low, int high) |
14848502 | 1203 | { |
5f68d078 | 1204 | struct rockchip_thermal_sensor *sensor = thermal_zone_device_priv(tz); |
14848502 CW |
1205 | struct rockchip_thermal_data *thermal = sensor->thermal; |
1206 | const struct rockchip_tsadc_chip *tsadc = thermal->chip; | |
1207 | ||
1208 | dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n", | |
1209 | __func__, sensor->id, low, high); | |
1210 | ||
d3530497 CW |
1211 | return tsadc->set_alarm_temp(&tsadc->table, |
1212 | sensor->id, thermal->regs, high); | |
14848502 CW |
1213 | } |
1214 | ||
90b2ca02 | 1215 | static int rockchip_thermal_get_temp(struct thermal_zone_device *tz, int *out_temp) |
cbac8f63 | 1216 | { |
5f68d078 | 1217 | struct rockchip_thermal_sensor *sensor = thermal_zone_device_priv(tz); |
cbac8f63 CW |
1218 | struct rockchip_thermal_data *thermal = sensor->thermal; |
1219 | const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip; | |
1220 | int retval; | |
1221 | ||
cdd8b3f7 | 1222 | retval = tsadc->get_temp(&tsadc->table, |
ce74110d | 1223 | sensor->id, thermal->regs, out_temp); |
cbac8f63 CW |
1224 | return retval; |
1225 | } | |
1226 | ||
90b2ca02 | 1227 | static const struct thermal_zone_device_ops rockchip_of_thermal_ops = { |
cbac8f63 | 1228 | .get_temp = rockchip_thermal_get_temp, |
14848502 | 1229 | .set_trips = rockchip_thermal_set_trips, |
cbac8f63 CW |
1230 | }; |
1231 | ||
1232 | static int rockchip_configure_from_dt(struct device *dev, | |
1233 | struct device_node *np, | |
1234 | struct rockchip_thermal_data *thermal) | |
1235 | { | |
1236 | u32 shut_temp, tshut_mode, tshut_polarity; | |
1237 | ||
1238 | if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) { | |
1239 | dev_warn(dev, | |
437df217 | 1240 | "Missing tshut temp property, using default %d\n", |
cbac8f63 CW |
1241 | thermal->chip->tshut_temp); |
1242 | thermal->tshut_temp = thermal->chip->tshut_temp; | |
1243 | } else { | |
43b4eb9f CW |
1244 | if (shut_temp > INT_MAX) { |
1245 | dev_err(dev, "Invalid tshut temperature specified: %d\n", | |
1246 | shut_temp); | |
1247 | return -ERANGE; | |
1248 | } | |
cbac8f63 CW |
1249 | thermal->tshut_temp = shut_temp; |
1250 | } | |
1251 | ||
cbac8f63 CW |
1252 | if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) { |
1253 | dev_warn(dev, | |
1254 | "Missing tshut mode property, using default (%s)\n", | |
1255 | thermal->chip->tshut_mode == TSHUT_MODE_GPIO ? | |
1256 | "gpio" : "cru"); | |
1257 | thermal->tshut_mode = thermal->chip->tshut_mode; | |
1258 | } else { | |
1259 | thermal->tshut_mode = tshut_mode; | |
1260 | } | |
1261 | ||
1262 | if (thermal->tshut_mode > 1) { | |
1263 | dev_err(dev, "Invalid tshut mode specified: %d\n", | |
1264 | thermal->tshut_mode); | |
1265 | return -EINVAL; | |
1266 | } | |
1267 | ||
1268 | if (of_property_read_u32(np, "rockchip,hw-tshut-polarity", | |
1269 | &tshut_polarity)) { | |
1270 | dev_warn(dev, | |
1271 | "Missing tshut-polarity property, using default (%s)\n", | |
1272 | thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ? | |
1273 | "low" : "high"); | |
1274 | thermal->tshut_polarity = thermal->chip->tshut_polarity; | |
1275 | } else { | |
1276 | thermal->tshut_polarity = tshut_polarity; | |
1277 | } | |
1278 | ||
1279 | if (thermal->tshut_polarity > 1) { | |
1280 | dev_err(dev, "Invalid tshut-polarity specified: %d\n", | |
1281 | thermal->tshut_polarity); | |
1282 | return -EINVAL; | |
1283 | } | |
1284 | ||
b9484763 CW |
1285 | /* The tsadc wont to handle the error in here since some SoCs didn't |
1286 | * need this property. | |
1287 | */ | |
1288 | thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); | |
ce62abae SL |
1289 | if (IS_ERR(thermal->grf)) |
1290 | dev_warn(dev, "Missing rockchip,grf property\n"); | |
b9484763 | 1291 | |
cbac8f63 CW |
1292 | return 0; |
1293 | } | |
1294 | ||
1295 | static int | |
1296 | rockchip_thermal_register_sensor(struct platform_device *pdev, | |
1297 | struct rockchip_thermal_data *thermal, | |
1298 | struct rockchip_thermal_sensor *sensor, | |
1d98b618 | 1299 | int id) |
cbac8f63 CW |
1300 | { |
1301 | const struct rockchip_tsadc_chip *tsadc = thermal->chip; | |
1302 | int error; | |
1303 | ||
1304 | tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); | |
d3530497 CW |
1305 | |
1306 | error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, | |
ce74110d | 1307 | thermal->tshut_temp); |
d3530497 CW |
1308 | if (error) |
1309 | dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n", | |
1310 | __func__, thermal->tshut_temp, error); | |
cbac8f63 CW |
1311 | |
1312 | sensor->thermal = thermal; | |
1313 | sensor->id = id; | |
90b2ca02 DL |
1314 | sensor->tzd = devm_thermal_of_zone_register(&pdev->dev, id, sensor, |
1315 | &rockchip_of_thermal_ops); | |
cbac8f63 CW |
1316 | if (IS_ERR(sensor->tzd)) { |
1317 | error = PTR_ERR(sensor->tzd); | |
1318 | dev_err(&pdev->dev, "failed to register sensor %d: %d\n", | |
1319 | id, error); | |
1320 | return error; | |
1321 | } | |
1322 | ||
1323 | return 0; | |
1324 | } | |
1325 | ||
13c1cfda | 1326 | /** |
6d5dad7b | 1327 | * rockchip_thermal_reset_controller - Reset TSADC Controller, reset all tsadc registers. |
66ec4bfc | 1328 | * @reset: the reset controller of tsadc |
cbac8f63 CW |
1329 | */ |
1330 | static void rockchip_thermal_reset_controller(struct reset_control *reset) | |
1331 | { | |
1332 | reset_control_assert(reset); | |
1333 | usleep_range(10, 20); | |
1334 | reset_control_deassert(reset); | |
1335 | } | |
1336 | ||
1337 | static int rockchip_thermal_probe(struct platform_device *pdev) | |
1338 | { | |
1339 | struct device_node *np = pdev->dev.of_node; | |
1340 | struct rockchip_thermal_data *thermal; | |
cbac8f63 | 1341 | int irq; |
2633ad19 | 1342 | int i; |
cbac8f63 CW |
1343 | int error; |
1344 | ||
cbac8f63 | 1345 | irq = platform_get_irq(pdev, 0); |
8cb775bb | 1346 | if (irq < 0) |
cbac8f63 | 1347 | return -EINVAL; |
cbac8f63 CW |
1348 | |
1349 | thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), | |
1350 | GFP_KERNEL); | |
1351 | if (!thermal) | |
1352 | return -ENOMEM; | |
1353 | ||
1354 | thermal->pdev = pdev; | |
1355 | ||
f1d2427c | 1356 | thermal->chip = device_get_match_data(&pdev->dev); |
cbac8f63 CW |
1357 | if (!thermal->chip) |
1358 | return -EINVAL; | |
1359 | ||
267f5965 SR |
1360 | thermal->sensors = devm_kcalloc(&pdev->dev, thermal->chip->chn_num, |
1361 | sizeof(*thermal->sensors), GFP_KERNEL); | |
1362 | if (!thermal->sensors) | |
1363 | return -ENOMEM; | |
1364 | ||
2484b632 | 1365 | thermal->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); |
cbac8f63 CW |
1366 | if (IS_ERR(thermal->regs)) |
1367 | return PTR_ERR(thermal->regs); | |
1368 | ||
02832ed8 | 1369 | thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false); |
cb71c5f9 SR |
1370 | if (IS_ERR(thermal->reset)) |
1371 | return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset), | |
1372 | "failed to get tsadc reset.\n"); | |
cbac8f63 | 1373 | |
2f6916f1 | 1374 | thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc"); |
cb71c5f9 SR |
1375 | if (IS_ERR(thermal->clk)) |
1376 | return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk), | |
1377 | "failed to get tsadc clock.\n"); | |
cbac8f63 | 1378 | |
2f6916f1 | 1379 | thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); |
cb71c5f9 SR |
1380 | if (IS_ERR(thermal->pclk)) |
1381 | return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk), | |
1382 | "failed to get apb_pclk clock.\n"); | |
cbac8f63 | 1383 | |
cbac8f63 CW |
1384 | rockchip_thermal_reset_controller(thermal->reset); |
1385 | ||
1386 | error = rockchip_configure_from_dt(&pdev->dev, np, thermal); | |
cb71c5f9 SR |
1387 | if (error) |
1388 | return dev_err_probe(&pdev->dev, error, | |
1389 | "failed to parse device tree data\n"); | |
cbac8f63 | 1390 | |
b9484763 CW |
1391 | thermal->chip->initialize(thermal->grf, thermal->regs, |
1392 | thermal->tshut_polarity); | |
cbac8f63 | 1393 | |
1d98b618 CW |
1394 | for (i = 0; i < thermal->chip->chn_num; i++) { |
1395 | error = rockchip_thermal_register_sensor(pdev, thermal, | |
1396 | &thermal->sensors[i], | |
f7cef1b7 | 1397 | thermal->chip->chn_offset + i); |
cb71c5f9 SR |
1398 | if (error) |
1399 | return dev_err_probe(&pdev->dev, error, | |
1400 | "failed to register sensor[%d].\n", i); | |
cbac8f63 CW |
1401 | } |
1402 | ||
1403 | error = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
1404 | &rockchip_thermal_alarm_irq_thread, | |
1405 | IRQF_ONESHOT, | |
1406 | "rockchip_thermal", thermal); | |
cb71c5f9 SR |
1407 | if (error) |
1408 | return dev_err_probe(&pdev->dev, error, | |
1409 | "failed to request tsadc irq.\n"); | |
cbac8f63 CW |
1410 | |
1411 | thermal->chip->control(thermal->regs, true); | |
1412 | ||
d27970b8 | 1413 | for (i = 0; i < thermal->chip->chn_num; i++) { |
cbac8f63 | 1414 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
d27970b8 SS |
1415 | error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd); |
1416 | if (error) | |
1417 | dev_warn(&pdev->dev, | |
1418 | "failed to register sensor %d with hwmon: %d\n", | |
1419 | i, error); | |
1420 | } | |
cbac8f63 CW |
1421 | |
1422 | platform_set_drvdata(pdev, thermal); | |
1423 | ||
1424 | return 0; | |
cbac8f63 CW |
1425 | } |
1426 | ||
1427 | static int rockchip_thermal_remove(struct platform_device *pdev) | |
1428 | { | |
1429 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
1430 | int i; | |
1431 | ||
1d98b618 | 1432 | for (i = 0; i < thermal->chip->chn_num; i++) { |
cbac8f63 CW |
1433 | struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; |
1434 | ||
d27970b8 | 1435 | thermal_remove_hwmon_sysfs(sensor->tzd); |
cbac8f63 | 1436 | rockchip_thermal_toggle_sensor(sensor, false); |
cbac8f63 CW |
1437 | } |
1438 | ||
1439 | thermal->chip->control(thermal->regs, false); | |
1440 | ||
cbac8f63 CW |
1441 | return 0; |
1442 | } | |
1443 | ||
1444 | static int __maybe_unused rockchip_thermal_suspend(struct device *dev) | |
1445 | { | |
26d84c27 | 1446 | struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); |
cbac8f63 CW |
1447 | int i; |
1448 | ||
1d98b618 | 1449 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
1450 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], false); |
1451 | ||
1452 | thermal->chip->control(thermal->regs, false); | |
1453 | ||
1454 | clk_disable(thermal->pclk); | |
1455 | clk_disable(thermal->clk); | |
0f5ee062 HS |
1456 | |
1457 | pinctrl_pm_select_sleep_state(dev); | |
7e38a5b1 | 1458 | |
cbac8f63 CW |
1459 | return 0; |
1460 | } | |
1461 | ||
1462 | static int __maybe_unused rockchip_thermal_resume(struct device *dev) | |
1463 | { | |
26d84c27 | 1464 | struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); |
cbac8f63 CW |
1465 | int i; |
1466 | int error; | |
1467 | ||
1468 | error = clk_enable(thermal->clk); | |
1469 | if (error) | |
1470 | return error; | |
1471 | ||
1472 | error = clk_enable(thermal->pclk); | |
ab5b52f1 SL |
1473 | if (error) { |
1474 | clk_disable(thermal->clk); | |
cbac8f63 | 1475 | return error; |
ab5b52f1 | 1476 | } |
cbac8f63 CW |
1477 | |
1478 | rockchip_thermal_reset_controller(thermal->reset); | |
1479 | ||
b9484763 CW |
1480 | thermal->chip->initialize(thermal->grf, thermal->regs, |
1481 | thermal->tshut_polarity); | |
cbac8f63 | 1482 | |
1d98b618 CW |
1483 | for (i = 0; i < thermal->chip->chn_num; i++) { |
1484 | int id = thermal->sensors[i].id; | |
cbac8f63 CW |
1485 | |
1486 | thermal->chip->set_tshut_mode(id, thermal->regs, | |
1487 | thermal->tshut_mode); | |
d3530497 CW |
1488 | |
1489 | error = thermal->chip->set_tshut_temp(&thermal->chip->table, | |
ce74110d | 1490 | id, thermal->regs, |
cbac8f63 | 1491 | thermal->tshut_temp); |
d3530497 | 1492 | if (error) |
26d84c27 | 1493 | dev_err(dev, "%s: invalid tshut=%d, error=%d\n", |
d3530497 | 1494 | __func__, thermal->tshut_temp, error); |
cbac8f63 CW |
1495 | } |
1496 | ||
1497 | thermal->chip->control(thermal->regs, true); | |
1498 | ||
1d98b618 | 1499 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
1500 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
1501 | ||
0f5ee062 | 1502 | pinctrl_pm_select_default_state(dev); |
7e38a5b1 | 1503 | |
cbac8f63 CW |
1504 | return 0; |
1505 | } | |
1506 | ||
1507 | static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops, | |
1508 | rockchip_thermal_suspend, rockchip_thermal_resume); | |
1509 | ||
1510 | static struct platform_driver rockchip_thermal_driver = { | |
1511 | .driver = { | |
1512 | .name = "rockchip-thermal", | |
cbac8f63 CW |
1513 | .pm = &rockchip_thermal_pm_ops, |
1514 | .of_match_table = of_rockchip_thermal_match, | |
1515 | }, | |
1516 | .probe = rockchip_thermal_probe, | |
1517 | .remove = rockchip_thermal_remove, | |
1518 | }; | |
1519 | ||
1520 | module_platform_driver(rockchip_thermal_driver); | |
1521 | ||
1522 | MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver"); | |
1523 | MODULE_AUTHOR("Rockchip, Inc."); | |
1524 | MODULE_LICENSE("GPL v2"); | |
1525 | MODULE_ALIAS("platform:rockchip-thermal"); |