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cbac8f63 CW |
1 | /* |
2 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | */ | |
13 | ||
14 | #include <linux/clk.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/of_address.h> | |
21 | #include <linux/of_irq.h> | |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/reset.h> | |
24 | #include <linux/thermal.h> | |
c970872e | 25 | #include <linux/pinctrl/consumer.h> |
cbac8f63 CW |
26 | |
27 | /** | |
28 | * If the temperature over a period of time High, | |
29 | * the resulting TSHUT gave CRU module,let it reset the entire chip, | |
30 | * or via GPIO give PMIC. | |
31 | */ | |
32 | enum tshut_mode { | |
33 | TSHUT_MODE_CRU = 0, | |
34 | TSHUT_MODE_GPIO, | |
35 | }; | |
36 | ||
37 | /** | |
38 | * the system Temperature Sensors tshut(tshut) polarity | |
39 | * the bit 8 is tshut polarity. | |
40 | * 0: low active, 1: high active | |
41 | */ | |
42 | enum tshut_polarity { | |
43 | TSHUT_LOW_ACTIVE = 0, | |
44 | TSHUT_HIGH_ACTIVE, | |
45 | }; | |
46 | ||
47 | /** | |
1d98b618 CW |
48 | * The system has two Temperature Sensors. |
49 | * sensor0 is for CPU, and sensor1 is for GPU. | |
cbac8f63 CW |
50 | */ |
51 | enum sensor_id { | |
1d98b618 | 52 | SENSOR_CPU = 0, |
cbac8f63 CW |
53 | SENSOR_GPU, |
54 | }; | |
55 | ||
020ba95d CW |
56 | /** |
57 | * The conversion table has the adc value and temperature. | |
58 | * ADC_DECREMENT is the adc value decremnet.(e.g. v2_code_table) | |
59 | * ADC_INCREMNET is the adc value incremnet.(e.g. v3_code_table) | |
60 | */ | |
61 | enum adc_sort_mode { | |
62 | ADC_DECREMENT = 0, | |
63 | ADC_INCREMENT, | |
64 | }; | |
65 | ||
1d98b618 CW |
66 | /** |
67 | * The max sensors is two in rockchip SoCs. | |
68 | * Two sensors: CPU and GPU sensor. | |
69 | */ | |
70 | #define SOC_MAX_SENSORS 2 | |
71 | ||
ce74110d CW |
72 | struct chip_tsadc_table { |
73 | const struct tsadc_table *id; | |
74 | ||
75 | /* the array table size*/ | |
76 | unsigned int length; | |
77 | ||
78 | /* that analogic mask data */ | |
79 | u32 data_mask; | |
020ba95d CW |
80 | |
81 | /* the sort mode is adc value that increment or decrement in table */ | |
82 | enum adc_sort_mode mode; | |
ce74110d CW |
83 | }; |
84 | ||
cbac8f63 | 85 | struct rockchip_tsadc_chip { |
1d98b618 CW |
86 | /* The sensor id of chip correspond to the ADC channel */ |
87 | int chn_id[SOC_MAX_SENSORS]; | |
88 | int chn_num; | |
89 | ||
cbac8f63 | 90 | /* The hardware-controlled tshut property */ |
437df217 | 91 | int tshut_temp; |
cbac8f63 CW |
92 | enum tshut_mode tshut_mode; |
93 | enum tshut_polarity tshut_polarity; | |
94 | ||
95 | /* Chip-wide methods */ | |
96 | void (*initialize)(void __iomem *reg, enum tshut_polarity p); | |
97 | void (*irq_ack)(void __iomem *reg); | |
98 | void (*control)(void __iomem *reg, bool on); | |
99 | ||
100 | /* Per-sensor methods */ | |
ce74110d CW |
101 | int (*get_temp)(struct chip_tsadc_table table, |
102 | int chn, void __iomem *reg, int *temp); | |
103 | void (*set_tshut_temp)(struct chip_tsadc_table table, | |
437df217 | 104 | int chn, void __iomem *reg, int temp); |
cbac8f63 | 105 | void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); |
ce74110d CW |
106 | |
107 | /* Per-table methods */ | |
108 | struct chip_tsadc_table table; | |
cbac8f63 CW |
109 | }; |
110 | ||
111 | struct rockchip_thermal_sensor { | |
112 | struct rockchip_thermal_data *thermal; | |
113 | struct thermal_zone_device *tzd; | |
1d98b618 | 114 | int id; |
cbac8f63 CW |
115 | }; |
116 | ||
cbac8f63 CW |
117 | struct rockchip_thermal_data { |
118 | const struct rockchip_tsadc_chip *chip; | |
119 | struct platform_device *pdev; | |
120 | struct reset_control *reset; | |
121 | ||
1d98b618 | 122 | struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; |
cbac8f63 CW |
123 | |
124 | struct clk *clk; | |
125 | struct clk *pclk; | |
126 | ||
127 | void __iomem *regs; | |
128 | ||
437df217 | 129 | int tshut_temp; |
cbac8f63 CW |
130 | enum tshut_mode tshut_mode; |
131 | enum tshut_polarity tshut_polarity; | |
132 | }; | |
133 | ||
1d98b618 | 134 | /* TSADC Sensor info define: */ |
cbac8f63 CW |
135 | #define TSADCV2_AUTO_CON 0x04 |
136 | #define TSADCV2_INT_EN 0x08 | |
137 | #define TSADCV2_INT_PD 0x0c | |
138 | #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) | |
139 | #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) | |
140 | #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 | |
141 | #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 | |
142 | #define TSADCV2_AUTO_PERIOD 0x68 | |
143 | #define TSADCV2_AUTO_PERIOD_HT 0x6c | |
144 | ||
145 | #define TSADCV2_AUTO_EN BIT(0) | |
cbac8f63 CW |
146 | #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) |
147 | #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) | |
cbac8f63 CW |
148 | |
149 | #define TSADCV2_INT_SRC_EN(chn) BIT(chn) | |
150 | #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) | |
151 | #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) | |
152 | ||
452e01b3 | 153 | #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) |
cbac8f63 CW |
154 | |
155 | #define TSADCV2_DATA_MASK 0xfff | |
156 | #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 | |
157 | #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 | |
158 | #define TSADCV2_AUTO_PERIOD_TIME 250 /* msec */ | |
159 | #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* msec */ | |
160 | ||
161 | struct tsadc_table { | |
d9a241cb | 162 | u32 code; |
437df217 | 163 | int temp; |
cbac8f63 CW |
164 | }; |
165 | ||
166 | static const struct tsadc_table v2_code_table[] = { | |
167 | {TSADCV2_DATA_MASK, -40000}, | |
168 | {3800, -40000}, | |
169 | {3792, -35000}, | |
170 | {3783, -30000}, | |
171 | {3774, -25000}, | |
172 | {3765, -20000}, | |
173 | {3756, -15000}, | |
174 | {3747, -10000}, | |
175 | {3737, -5000}, | |
176 | {3728, 0}, | |
177 | {3718, 5000}, | |
178 | {3708, 10000}, | |
179 | {3698, 15000}, | |
180 | {3688, 20000}, | |
181 | {3678, 25000}, | |
182 | {3667, 30000}, | |
183 | {3656, 35000}, | |
184 | {3645, 40000}, | |
185 | {3634, 45000}, | |
186 | {3623, 50000}, | |
187 | {3611, 55000}, | |
188 | {3600, 60000}, | |
189 | {3588, 65000}, | |
190 | {3575, 70000}, | |
191 | {3563, 75000}, | |
192 | {3550, 80000}, | |
193 | {3537, 85000}, | |
194 | {3524, 90000}, | |
195 | {3510, 95000}, | |
196 | {3496, 100000}, | |
197 | {3482, 105000}, | |
198 | {3467, 110000}, | |
199 | {3452, 115000}, | |
200 | {3437, 120000}, | |
201 | {3421, 125000}, | |
cbac8f63 CW |
202 | }; |
203 | ||
ce74110d | 204 | static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table, |
437df217 | 205 | int temp) |
cbac8f63 CW |
206 | { |
207 | int high, low, mid; | |
208 | ||
209 | low = 0; | |
ce74110d | 210 | high = table.length - 1; |
cbac8f63 CW |
211 | mid = (high + low) / 2; |
212 | ||
ce74110d | 213 | if (temp < table.id[low].temp || temp > table.id[high].temp) |
cbac8f63 CW |
214 | return 0; |
215 | ||
216 | while (low <= high) { | |
ce74110d CW |
217 | if (temp == table.id[mid].temp) |
218 | return table.id[mid].code; | |
219 | else if (temp < table.id[mid].temp) | |
cbac8f63 CW |
220 | high = mid - 1; |
221 | else | |
222 | low = mid + 1; | |
223 | mid = (low + high) / 2; | |
224 | } | |
225 | ||
226 | return 0; | |
227 | } | |
228 | ||
ce74110d CW |
229 | static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code, |
230 | int *temp) | |
cbac8f63 | 231 | { |
d9a241cb | 232 | unsigned int low = 1; |
ce74110d | 233 | unsigned int high = table.length - 1; |
1e9a1aea CW |
234 | unsigned int mid = (low + high) / 2; |
235 | unsigned int num; | |
236 | unsigned long denom; | |
237 | ||
ce74110d | 238 | WARN_ON(table.length < 2); |
1e9a1aea | 239 | |
020ba95d CW |
240 | switch (table.mode) { |
241 | case ADC_DECREMENT: | |
242 | code &= table.data_mask; | |
243 | if (code < table.id[high].code) | |
244 | return -EAGAIN; /* Incorrect reading */ | |
245 | ||
246 | while (low <= high) { | |
247 | if (code >= table.id[mid].code && | |
248 | code < table.id[mid - 1].code) | |
249 | break; | |
250 | else if (code < table.id[mid].code) | |
251 | low = mid + 1; | |
252 | else | |
253 | high = mid - 1; | |
254 | ||
255 | mid = (low + high) / 2; | |
256 | } | |
257 | break; | |
258 | case ADC_INCREMENT: | |
259 | code &= table.data_mask; | |
260 | if (code < table.id[low].code) | |
261 | return -EAGAIN; /* Incorrect reading */ | |
262 | ||
263 | while (low <= high) { | |
264 | if (code >= table.id[mid - 1].code && | |
265 | code < table.id[mid].code) | |
266 | break; | |
267 | else if (code > table.id[mid].code) | |
268 | low = mid + 1; | |
269 | else | |
270 | high = mid - 1; | |
271 | ||
272 | mid = (low + high) / 2; | |
273 | } | |
274 | break; | |
275 | default: | |
276 | pr_err("Invalid the conversion table\n"); | |
cbac8f63 CW |
277 | } |
278 | ||
1e9a1aea CW |
279 | /* |
280 | * The 5C granularity provided by the table is too much. Let's | |
281 | * assume that the relationship between sensor readings and | |
282 | * temperature between 2 table entries is linear and interpolate | |
283 | * to produce less granular result. | |
284 | */ | |
ce74110d | 285 | num = table.id[mid].temp - v2_code_table[mid - 1].temp; |
020ba95d CW |
286 | num *= abs(table.id[mid - 1].code - code); |
287 | denom = abs(table.id[mid - 1].code - table.id[mid].code); | |
ce74110d | 288 | *temp = table.id[mid - 1].temp + (num / denom); |
d9a241cb DT |
289 | |
290 | return 0; | |
cbac8f63 CW |
291 | } |
292 | ||
293 | /** | |
144c5565 CW |
294 | * rk_tsadcv2_initialize - initialize TASDC Controller. |
295 | * | |
296 | * (1) Set TSADC_V2_AUTO_PERIOD: | |
297 | * Configure the interleave between every two accessing of | |
298 | * TSADC in normal operation. | |
299 | * | |
300 | * (2) Set TSADCV2_AUTO_PERIOD_HT: | |
301 | * Configure the interleave between every two accessing of | |
302 | * TSADC after the temperature is higher than COM_SHUT or COM_INT. | |
303 | * | |
304 | * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: | |
305 | * If the temperature is higher than COMP_INT or COMP_SHUT for | |
306 | * "debounce" times, TSADC controller will generate interrupt or TSHUT. | |
cbac8f63 CW |
307 | */ |
308 | static void rk_tsadcv2_initialize(void __iomem *regs, | |
309 | enum tshut_polarity tshut_polarity) | |
310 | { | |
311 | if (tshut_polarity == TSHUT_HIGH_ACTIVE) | |
452e01b3 | 312 | writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
cbac8f63 CW |
313 | regs + TSADCV2_AUTO_CON); |
314 | else | |
452e01b3 | 315 | writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, |
cbac8f63 CW |
316 | regs + TSADCV2_AUTO_CON); |
317 | ||
318 | writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); | |
319 | writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, | |
320 | regs + TSADCV2_HIGHT_INT_DEBOUNCE); | |
321 | writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, | |
322 | regs + TSADCV2_AUTO_PERIOD_HT); | |
323 | writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, | |
324 | regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); | |
325 | } | |
326 | ||
327 | static void rk_tsadcv2_irq_ack(void __iomem *regs) | |
328 | { | |
329 | u32 val; | |
330 | ||
331 | val = readl_relaxed(regs + TSADCV2_INT_PD); | |
452e01b3 | 332 | writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); |
cbac8f63 CW |
333 | } |
334 | ||
335 | static void rk_tsadcv2_control(void __iomem *regs, bool enable) | |
336 | { | |
337 | u32 val; | |
338 | ||
339 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
340 | if (enable) | |
341 | val |= TSADCV2_AUTO_EN; | |
342 | else | |
343 | val &= ~TSADCV2_AUTO_EN; | |
344 | ||
345 | writel_relaxed(val, regs + TSADCV2_AUTO_CON); | |
346 | } | |
347 | ||
ce74110d CW |
348 | static int rk_tsadcv2_get_temp(struct chip_tsadc_table table, |
349 | int chn, void __iomem *regs, int *temp) | |
cbac8f63 CW |
350 | { |
351 | u32 val; | |
352 | ||
cbac8f63 | 353 | val = readl_relaxed(regs + TSADCV2_DATA(chn)); |
cbac8f63 | 354 | |
ce74110d | 355 | return rk_tsadcv2_code_to_temp(table, val, temp); |
cbac8f63 CW |
356 | } |
357 | ||
ce74110d | 358 | static void rk_tsadcv2_tshut_temp(struct chip_tsadc_table table, |
437df217 | 359 | int chn, void __iomem *regs, int temp) |
cbac8f63 CW |
360 | { |
361 | u32 tshut_value, val; | |
362 | ||
ce74110d | 363 | tshut_value = rk_tsadcv2_temp_to_code(table, temp); |
cbac8f63 CW |
364 | writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); |
365 | ||
366 | /* TSHUT will be valid */ | |
367 | val = readl_relaxed(regs + TSADCV2_AUTO_CON); | |
368 | writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); | |
369 | } | |
370 | ||
371 | static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, | |
372 | enum tshut_mode mode) | |
373 | { | |
374 | u32 val; | |
375 | ||
376 | val = readl_relaxed(regs + TSADCV2_INT_EN); | |
377 | if (mode == TSHUT_MODE_GPIO) { | |
378 | val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); | |
379 | val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); | |
380 | } else { | |
381 | val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); | |
382 | val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); | |
383 | } | |
384 | ||
385 | writel_relaxed(val, regs + TSADCV2_INT_EN); | |
386 | } | |
387 | ||
388 | static const struct rockchip_tsadc_chip rk3288_tsadc_data = { | |
1d98b618 CW |
389 | .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ |
390 | .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ | |
391 | .chn_num = 2, /* two channels for tsadc */ | |
392 | ||
cbac8f63 CW |
393 | .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ |
394 | .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ | |
395 | .tshut_temp = 95000, | |
396 | ||
397 | .initialize = rk_tsadcv2_initialize, | |
398 | .irq_ack = rk_tsadcv2_irq_ack, | |
399 | .control = rk_tsadcv2_control, | |
400 | .get_temp = rk_tsadcv2_get_temp, | |
401 | .set_tshut_temp = rk_tsadcv2_tshut_temp, | |
402 | .set_tshut_mode = rk_tsadcv2_tshut_mode, | |
ce74110d CW |
403 | |
404 | .table = { | |
405 | .id = v2_code_table, | |
406 | .length = ARRAY_SIZE(v2_code_table), | |
407 | .data_mask = TSADCV2_DATA_MASK, | |
020ba95d | 408 | .mode = ADC_DECREMENT, |
ce74110d | 409 | }, |
cbac8f63 CW |
410 | }; |
411 | ||
412 | static const struct of_device_id of_rockchip_thermal_match[] = { | |
413 | { | |
414 | .compatible = "rockchip,rk3288-tsadc", | |
415 | .data = (void *)&rk3288_tsadc_data, | |
416 | }, | |
417 | { /* end */ }, | |
418 | }; | |
419 | MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); | |
420 | ||
421 | static void | |
422 | rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on) | |
423 | { | |
424 | struct thermal_zone_device *tzd = sensor->tzd; | |
425 | ||
426 | tzd->ops->set_mode(tzd, | |
427 | on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED); | |
428 | } | |
429 | ||
430 | static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) | |
431 | { | |
432 | struct rockchip_thermal_data *thermal = dev; | |
433 | int i; | |
434 | ||
435 | dev_dbg(&thermal->pdev->dev, "thermal alarm\n"); | |
436 | ||
437 | thermal->chip->irq_ack(thermal->regs); | |
438 | ||
1d98b618 | 439 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
440 | thermal_zone_device_update(thermal->sensors[i].tzd); |
441 | ||
442 | return IRQ_HANDLED; | |
443 | } | |
444 | ||
17e8351a | 445 | static int rockchip_thermal_get_temp(void *_sensor, int *out_temp) |
cbac8f63 CW |
446 | { |
447 | struct rockchip_thermal_sensor *sensor = _sensor; | |
448 | struct rockchip_thermal_data *thermal = sensor->thermal; | |
449 | const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip; | |
450 | int retval; | |
451 | ||
ce74110d CW |
452 | retval = tsadc->get_temp(tsadc->table, |
453 | sensor->id, thermal->regs, out_temp); | |
17e8351a | 454 | dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", |
cbac8f63 CW |
455 | sensor->id, *out_temp, retval); |
456 | ||
457 | return retval; | |
458 | } | |
459 | ||
460 | static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = { | |
461 | .get_temp = rockchip_thermal_get_temp, | |
462 | }; | |
463 | ||
464 | static int rockchip_configure_from_dt(struct device *dev, | |
465 | struct device_node *np, | |
466 | struct rockchip_thermal_data *thermal) | |
467 | { | |
468 | u32 shut_temp, tshut_mode, tshut_polarity; | |
469 | ||
470 | if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) { | |
471 | dev_warn(dev, | |
437df217 | 472 | "Missing tshut temp property, using default %d\n", |
cbac8f63 CW |
473 | thermal->chip->tshut_temp); |
474 | thermal->tshut_temp = thermal->chip->tshut_temp; | |
475 | } else { | |
476 | thermal->tshut_temp = shut_temp; | |
477 | } | |
478 | ||
479 | if (thermal->tshut_temp > INT_MAX) { | |
437df217 | 480 | dev_err(dev, "Invalid tshut temperature specified: %d\n", |
cbac8f63 CW |
481 | thermal->tshut_temp); |
482 | return -ERANGE; | |
483 | } | |
484 | ||
485 | if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) { | |
486 | dev_warn(dev, | |
487 | "Missing tshut mode property, using default (%s)\n", | |
488 | thermal->chip->tshut_mode == TSHUT_MODE_GPIO ? | |
489 | "gpio" : "cru"); | |
490 | thermal->tshut_mode = thermal->chip->tshut_mode; | |
491 | } else { | |
492 | thermal->tshut_mode = tshut_mode; | |
493 | } | |
494 | ||
495 | if (thermal->tshut_mode > 1) { | |
496 | dev_err(dev, "Invalid tshut mode specified: %d\n", | |
497 | thermal->tshut_mode); | |
498 | return -EINVAL; | |
499 | } | |
500 | ||
501 | if (of_property_read_u32(np, "rockchip,hw-tshut-polarity", | |
502 | &tshut_polarity)) { | |
503 | dev_warn(dev, | |
504 | "Missing tshut-polarity property, using default (%s)\n", | |
505 | thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ? | |
506 | "low" : "high"); | |
507 | thermal->tshut_polarity = thermal->chip->tshut_polarity; | |
508 | } else { | |
509 | thermal->tshut_polarity = tshut_polarity; | |
510 | } | |
511 | ||
512 | if (thermal->tshut_polarity > 1) { | |
513 | dev_err(dev, "Invalid tshut-polarity specified: %d\n", | |
514 | thermal->tshut_polarity); | |
515 | return -EINVAL; | |
516 | } | |
517 | ||
518 | return 0; | |
519 | } | |
520 | ||
521 | static int | |
522 | rockchip_thermal_register_sensor(struct platform_device *pdev, | |
523 | struct rockchip_thermal_data *thermal, | |
524 | struct rockchip_thermal_sensor *sensor, | |
1d98b618 | 525 | int id) |
cbac8f63 CW |
526 | { |
527 | const struct rockchip_tsadc_chip *tsadc = thermal->chip; | |
528 | int error; | |
529 | ||
530 | tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); | |
ce74110d CW |
531 | tsadc->set_tshut_temp(tsadc->table, id, thermal->regs, |
532 | thermal->tshut_temp); | |
cbac8f63 CW |
533 | |
534 | sensor->thermal = thermal; | |
535 | sensor->id = id; | |
536 | sensor->tzd = thermal_zone_of_sensor_register(&pdev->dev, id, sensor, | |
537 | &rockchip_of_thermal_ops); | |
538 | if (IS_ERR(sensor->tzd)) { | |
539 | error = PTR_ERR(sensor->tzd); | |
540 | dev_err(&pdev->dev, "failed to register sensor %d: %d\n", | |
541 | id, error); | |
542 | return error; | |
543 | } | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
548 | /* | |
549 | * Reset TSADC Controller, reset all tsadc registers. | |
550 | */ | |
551 | static void rockchip_thermal_reset_controller(struct reset_control *reset) | |
552 | { | |
553 | reset_control_assert(reset); | |
554 | usleep_range(10, 20); | |
555 | reset_control_deassert(reset); | |
556 | } | |
557 | ||
558 | static int rockchip_thermal_probe(struct platform_device *pdev) | |
559 | { | |
560 | struct device_node *np = pdev->dev.of_node; | |
561 | struct rockchip_thermal_data *thermal; | |
562 | const struct of_device_id *match; | |
563 | struct resource *res; | |
564 | int irq; | |
1d98b618 | 565 | int i, j; |
cbac8f63 CW |
566 | int error; |
567 | ||
568 | match = of_match_node(of_rockchip_thermal_match, np); | |
569 | if (!match) | |
570 | return -ENXIO; | |
571 | ||
572 | irq = platform_get_irq(pdev, 0); | |
573 | if (irq < 0) { | |
574 | dev_err(&pdev->dev, "no irq resource?\n"); | |
575 | return -EINVAL; | |
576 | } | |
577 | ||
578 | thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), | |
579 | GFP_KERNEL); | |
580 | if (!thermal) | |
581 | return -ENOMEM; | |
582 | ||
583 | thermal->pdev = pdev; | |
584 | ||
585 | thermal->chip = (const struct rockchip_tsadc_chip *)match->data; | |
586 | if (!thermal->chip) | |
587 | return -EINVAL; | |
588 | ||
589 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
590 | thermal->regs = devm_ioremap_resource(&pdev->dev, res); | |
591 | if (IS_ERR(thermal->regs)) | |
592 | return PTR_ERR(thermal->regs); | |
593 | ||
594 | thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); | |
595 | if (IS_ERR(thermal->reset)) { | |
596 | error = PTR_ERR(thermal->reset); | |
597 | dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); | |
598 | return error; | |
599 | } | |
600 | ||
601 | thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); | |
602 | if (IS_ERR(thermal->clk)) { | |
603 | error = PTR_ERR(thermal->clk); | |
604 | dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); | |
605 | return error; | |
606 | } | |
607 | ||
608 | thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); | |
609 | if (IS_ERR(thermal->pclk)) { | |
0d0a2bf6 | 610 | error = PTR_ERR(thermal->pclk); |
cbac8f63 CW |
611 | dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", |
612 | error); | |
613 | return error; | |
614 | } | |
615 | ||
616 | error = clk_prepare_enable(thermal->clk); | |
617 | if (error) { | |
618 | dev_err(&pdev->dev, "failed to enable converter clock: %d\n", | |
619 | error); | |
620 | return error; | |
621 | } | |
622 | ||
623 | error = clk_prepare_enable(thermal->pclk); | |
624 | if (error) { | |
625 | dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); | |
626 | goto err_disable_clk; | |
627 | } | |
628 | ||
629 | rockchip_thermal_reset_controller(thermal->reset); | |
630 | ||
631 | error = rockchip_configure_from_dt(&pdev->dev, np, thermal); | |
632 | if (error) { | |
633 | dev_err(&pdev->dev, "failed to parse device tree data: %d\n", | |
634 | error); | |
635 | goto err_disable_pclk; | |
636 | } | |
637 | ||
638 | thermal->chip->initialize(thermal->regs, thermal->tshut_polarity); | |
639 | ||
1d98b618 CW |
640 | for (i = 0; i < thermal->chip->chn_num; i++) { |
641 | error = rockchip_thermal_register_sensor(pdev, thermal, | |
642 | &thermal->sensors[i], | |
643 | thermal->chip->chn_id[i]); | |
644 | if (error) { | |
645 | dev_err(&pdev->dev, | |
646 | "failed to register sensor[%d] : error = %d\n", | |
647 | i, error); | |
648 | for (j = 0; j < i; j++) | |
649 | thermal_zone_of_sensor_unregister(&pdev->dev, | |
650 | thermal->sensors[j].tzd); | |
651 | goto err_disable_pclk; | |
652 | } | |
cbac8f63 CW |
653 | } |
654 | ||
655 | error = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
656 | &rockchip_thermal_alarm_irq_thread, | |
657 | IRQF_ONESHOT, | |
658 | "rockchip_thermal", thermal); | |
659 | if (error) { | |
660 | dev_err(&pdev->dev, | |
661 | "failed to request tsadc irq: %d\n", error); | |
1d98b618 | 662 | goto err_unregister_sensor; |
cbac8f63 CW |
663 | } |
664 | ||
665 | thermal->chip->control(thermal->regs, true); | |
666 | ||
1d98b618 | 667 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
668 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
669 | ||
670 | platform_set_drvdata(pdev, thermal); | |
671 | ||
672 | return 0; | |
673 | ||
1d98b618 CW |
674 | err_unregister_sensor: |
675 | while (i--) | |
676 | thermal_zone_of_sensor_unregister(&pdev->dev, | |
677 | thermal->sensors[i].tzd); | |
678 | ||
cbac8f63 CW |
679 | err_disable_pclk: |
680 | clk_disable_unprepare(thermal->pclk); | |
681 | err_disable_clk: | |
682 | clk_disable_unprepare(thermal->clk); | |
683 | ||
684 | return error; | |
685 | } | |
686 | ||
687 | static int rockchip_thermal_remove(struct platform_device *pdev) | |
688 | { | |
689 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
690 | int i; | |
691 | ||
1d98b618 | 692 | for (i = 0; i < thermal->chip->chn_num; i++) { |
cbac8f63 CW |
693 | struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; |
694 | ||
695 | rockchip_thermal_toggle_sensor(sensor, false); | |
696 | thermal_zone_of_sensor_unregister(&pdev->dev, sensor->tzd); | |
697 | } | |
698 | ||
699 | thermal->chip->control(thermal->regs, false); | |
700 | ||
701 | clk_disable_unprepare(thermal->pclk); | |
702 | clk_disable_unprepare(thermal->clk); | |
703 | ||
704 | return 0; | |
705 | } | |
706 | ||
707 | static int __maybe_unused rockchip_thermal_suspend(struct device *dev) | |
708 | { | |
709 | struct platform_device *pdev = to_platform_device(dev); | |
710 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
711 | int i; | |
712 | ||
1d98b618 | 713 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
714 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], false); |
715 | ||
716 | thermal->chip->control(thermal->regs, false); | |
717 | ||
718 | clk_disable(thermal->pclk); | |
719 | clk_disable(thermal->clk); | |
720 | ||
7e38a5b1 CW |
721 | pinctrl_pm_select_sleep_state(dev); |
722 | ||
cbac8f63 CW |
723 | return 0; |
724 | } | |
725 | ||
726 | static int __maybe_unused rockchip_thermal_resume(struct device *dev) | |
727 | { | |
728 | struct platform_device *pdev = to_platform_device(dev); | |
729 | struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); | |
730 | int i; | |
731 | int error; | |
732 | ||
733 | error = clk_enable(thermal->clk); | |
734 | if (error) | |
735 | return error; | |
736 | ||
737 | error = clk_enable(thermal->pclk); | |
738 | if (error) | |
739 | return error; | |
740 | ||
741 | rockchip_thermal_reset_controller(thermal->reset); | |
742 | ||
743 | thermal->chip->initialize(thermal->regs, thermal->tshut_polarity); | |
744 | ||
1d98b618 CW |
745 | for (i = 0; i < thermal->chip->chn_num; i++) { |
746 | int id = thermal->sensors[i].id; | |
cbac8f63 CW |
747 | |
748 | thermal->chip->set_tshut_mode(id, thermal->regs, | |
749 | thermal->tshut_mode); | |
ce74110d CW |
750 | thermal->chip->set_tshut_temp(thermal->chip->table, |
751 | id, thermal->regs, | |
cbac8f63 CW |
752 | thermal->tshut_temp); |
753 | } | |
754 | ||
755 | thermal->chip->control(thermal->regs, true); | |
756 | ||
1d98b618 | 757 | for (i = 0; i < thermal->chip->chn_num; i++) |
cbac8f63 CW |
758 | rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); |
759 | ||
7e38a5b1 CW |
760 | pinctrl_pm_select_default_state(dev); |
761 | ||
cbac8f63 CW |
762 | return 0; |
763 | } | |
764 | ||
765 | static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops, | |
766 | rockchip_thermal_suspend, rockchip_thermal_resume); | |
767 | ||
768 | static struct platform_driver rockchip_thermal_driver = { | |
769 | .driver = { | |
770 | .name = "rockchip-thermal", | |
cbac8f63 CW |
771 | .pm = &rockchip_thermal_pm_ops, |
772 | .of_match_table = of_rockchip_thermal_match, | |
773 | }, | |
774 | .probe = rockchip_thermal_probe, | |
775 | .remove = rockchip_thermal_remove, | |
776 | }; | |
777 | ||
778 | module_platform_driver(rockchip_thermal_driver); | |
779 | ||
780 | MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver"); | |
781 | MODULE_AUTHOR("Rockchip, Inc."); | |
782 | MODULE_LICENSE("GPL v2"); | |
783 | MODULE_ALIAS("platform:rockchip-thermal"); |