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Commit | Line | Data |
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9d97e5c8 | 1 | /* |
59dfa54c | 2 | * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) |
9d97e5c8 | 3 | * |
3b6a1a80 LM |
4 | * Copyright (C) 2014 Samsung Electronics |
5 | * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> | |
6 | * Lukasz Majewski <l.majewski@samsung.com> | |
7 | * | |
9d97e5c8 DK |
8 | * Copyright (C) 2011 Samsung Electronics |
9 | * Donggeun Kim <dg77.kim@samsung.com> | |
c48cbba6 | 10 | * Amit Daniel Kachhap <amit.kachhap@linaro.org> |
9d97e5c8 DK |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | */ | |
27 | ||
9d97e5c8 | 28 | #include <linux/clk.h> |
9d97e5c8 | 29 | #include <linux/io.h> |
1b678641 ADK |
30 | #include <linux/interrupt.h> |
31 | #include <linux/module.h> | |
f22d9c03 | 32 | #include <linux/of.h> |
cebe7373 ADK |
33 | #include <linux/of_address.h> |
34 | #include <linux/of_irq.h> | |
1b678641 | 35 | #include <linux/platform_device.h> |
498d22f6 | 36 | #include <linux/regulator/consumer.h> |
1b678641 | 37 | |
0c1836a6 | 38 | #include "exynos_tmu.h" |
3b6a1a80 | 39 | #include "../thermal_core.h" |
2845f6ec BZ |
40 | |
41 | /* Exynos generic registers */ | |
42 | #define EXYNOS_TMU_REG_TRIMINFO 0x0 | |
43 | #define EXYNOS_TMU_REG_CONTROL 0x20 | |
44 | #define EXYNOS_TMU_REG_STATUS 0x28 | |
45 | #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 | |
46 | #define EXYNOS_TMU_REG_INTEN 0x70 | |
47 | #define EXYNOS_TMU_REG_INTSTAT 0x74 | |
48 | #define EXYNOS_TMU_REG_INTCLEAR 0x78 | |
49 | ||
50 | #define EXYNOS_TMU_TEMP_MASK 0xff | |
51 | #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 | |
52 | #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f | |
53 | #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf | |
54 | #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 | |
55 | #define EXYNOS_TMU_CORE_EN_SHIFT 0 | |
56 | ||
57 | /* Exynos3250 specific registers */ | |
58 | #define EXYNOS_TMU_TRIMINFO_CON1 0x10 | |
59 | ||
60 | /* Exynos4210 specific registers */ | |
61 | #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 | |
62 | #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 | |
63 | ||
64 | /* Exynos5250, Exynos4412, Exynos3250 specific registers */ | |
65 | #define EXYNOS_TMU_TRIMINFO_CON2 0x14 | |
66 | #define EXYNOS_THD_TEMP_RISE 0x50 | |
67 | #define EXYNOS_THD_TEMP_FALL 0x54 | |
68 | #define EXYNOS_EMUL_CON 0x80 | |
69 | ||
70 | #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 | |
71 | #define EXYNOS_TRIMINFO_25_SHIFT 0 | |
72 | #define EXYNOS_TRIMINFO_85_SHIFT 8 | |
73 | #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 | |
74 | #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 | |
75 | #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 | |
76 | ||
77 | #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 | |
78 | #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 | |
79 | #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8 | |
80 | #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12 | |
81 | #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 | |
82 | ||
83 | #define EXYNOS_EMUL_TIME 0x57F0 | |
84 | #define EXYNOS_EMUL_TIME_MASK 0xffff | |
85 | #define EXYNOS_EMUL_TIME_SHIFT 16 | |
86 | #define EXYNOS_EMUL_DATA_SHIFT 8 | |
87 | #define EXYNOS_EMUL_DATA_MASK 0xFF | |
88 | #define EXYNOS_EMUL_ENABLE 0x1 | |
89 | ||
90 | /* Exynos5260 specific */ | |
91 | #define EXYNOS5260_TMU_REG_INTEN 0xC0 | |
92 | #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 | |
93 | #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 | |
94 | #define EXYNOS5260_EMUL_CON 0x100 | |
95 | ||
96 | /* Exynos4412 specific */ | |
97 | #define EXYNOS4412_MUX_ADDR_VALUE 6 | |
98 | #define EXYNOS4412_MUX_ADDR_SHIFT 20 | |
99 | ||
100 | /*exynos5440 specific registers*/ | |
101 | #define EXYNOS5440_TMU_S0_7_TRIM 0x000 | |
102 | #define EXYNOS5440_TMU_S0_7_CTRL 0x020 | |
103 | #define EXYNOS5440_TMU_S0_7_DEBUG 0x040 | |
104 | #define EXYNOS5440_TMU_S0_7_TEMP 0x0f0 | |
105 | #define EXYNOS5440_TMU_S0_7_TH0 0x110 | |
106 | #define EXYNOS5440_TMU_S0_7_TH1 0x130 | |
107 | #define EXYNOS5440_TMU_S0_7_TH2 0x150 | |
108 | #define EXYNOS5440_TMU_S0_7_IRQEN 0x210 | |
109 | #define EXYNOS5440_TMU_S0_7_IRQ 0x230 | |
110 | /* exynos5440 common registers */ | |
111 | #define EXYNOS5440_TMU_IRQ_STATUS 0x000 | |
112 | #define EXYNOS5440_TMU_PMIN 0x004 | |
113 | ||
114 | #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0 | |
115 | #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1 | |
116 | #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2 | |
117 | #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3 | |
118 | #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4 | |
119 | #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24 | |
120 | #define EXYNOS5440_EFUSE_SWAP_OFFSET 8 | |
f22d9c03 | 121 | |
6c247393 AK |
122 | /* Exynos7 specific registers */ |
123 | #define EXYNOS7_THD_TEMP_RISE7_6 0x50 | |
124 | #define EXYNOS7_THD_TEMP_FALL7_6 0x60 | |
125 | #define EXYNOS7_TMU_REG_INTEN 0x110 | |
126 | #define EXYNOS7_TMU_REG_INTPEND 0x118 | |
127 | #define EXYNOS7_TMU_REG_EMUL_CON 0x160 | |
128 | ||
129 | #define EXYNOS7_TMU_TEMP_MASK 0x1ff | |
130 | #define EXYNOS7_PD_DET_EN_SHIFT 23 | |
131 | #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 | |
132 | #define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1 | |
133 | #define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2 | |
134 | #define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3 | |
135 | #define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4 | |
136 | #define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5 | |
137 | #define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6 | |
138 | #define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7 | |
139 | #define EXYNOS7_EMUL_DATA_SHIFT 7 | |
140 | #define EXYNOS7_EMUL_DATA_MASK 0x1ff | |
141 | ||
3b6a1a80 | 142 | #define MCELSIUS 1000 |
cebe7373 ADK |
143 | /** |
144 | * struct exynos_tmu_data : A structure to hold the private data of the TMU | |
145 | driver | |
146 | * @id: identifier of the one instance of the TMU controller. | |
147 | * @pdata: pointer to the tmu platform/configuration data | |
148 | * @base: base address of the single instance of the TMU controller. | |
9025d563 | 149 | * @base_second: base address of the common registers of the TMU controller. |
cebe7373 ADK |
150 | * @irq: irq number of the TMU controller. |
151 | * @soc: id of the SOC type. | |
152 | * @irq_work: pointer to the irq work structure. | |
153 | * @lock: lock to implement synchronization. | |
154 | * @clk: pointer to the clock structure. | |
14a11dc7 | 155 | * @clk_sec: pointer to the clock structure for accessing the base_second. |
6c247393 | 156 | * @sclk: pointer to the clock structure for accessing the tmu special clk. |
cebe7373 ADK |
157 | * @temp_error1: fused value of the first point trim. |
158 | * @temp_error2: fused value of the second point trim. | |
498d22f6 | 159 | * @regulator: pointer to the TMU regulator structure. |
cebe7373 | 160 | * @reg_conf: pointer to structure to register with core thermal. |
72d1100b | 161 | * @tmu_initialize: SoC specific TMU initialization method |
37f9034f | 162 | * @tmu_control: SoC specific TMU control method |
b79985ca | 163 | * @tmu_read: SoC specific TMU temperature read method |
285d994a | 164 | * @tmu_set_emulation: SoC specific TMU emulation setting method |
a7331f72 | 165 | * @tmu_clear_irqs: SoC specific TMU interrupts clearing method |
cebe7373 | 166 | */ |
f22d9c03 | 167 | struct exynos_tmu_data { |
cebe7373 | 168 | int id; |
f22d9c03 | 169 | struct exynos_tmu_platform_data *pdata; |
9d97e5c8 | 170 | void __iomem *base; |
9025d563 | 171 | void __iomem *base_second; |
9d97e5c8 | 172 | int irq; |
f22d9c03 | 173 | enum soc_type soc; |
9d97e5c8 DK |
174 | struct work_struct irq_work; |
175 | struct mutex lock; | |
6c247393 AK |
176 | struct clk *clk, *clk_sec, *sclk; |
177 | u16 temp_error1, temp_error2; | |
498d22f6 | 178 | struct regulator *regulator; |
3b6a1a80 LM |
179 | struct thermal_zone_device *tzd; |
180 | ||
72d1100b | 181 | int (*tmu_initialize)(struct platform_device *pdev); |
37f9034f | 182 | void (*tmu_control)(struct platform_device *pdev, bool on); |
b79985ca | 183 | int (*tmu_read)(struct exynos_tmu_data *data); |
285d994a BZ |
184 | void (*tmu_set_emulation)(struct exynos_tmu_data *data, |
185 | unsigned long temp); | |
a7331f72 | 186 | void (*tmu_clear_irqs)(struct exynos_tmu_data *data); |
9d97e5c8 DK |
187 | }; |
188 | ||
3b6a1a80 LM |
189 | static void exynos_report_trigger(struct exynos_tmu_data *p) |
190 | { | |
191 | char data[10], *envp[] = { data, NULL }; | |
192 | struct thermal_zone_device *tz = p->tzd; | |
193 | unsigned long temp; | |
194 | unsigned int i; | |
195 | ||
eccb6014 LM |
196 | if (!tz) { |
197 | pr_err("No thermal zone device defined\n"); | |
3b6a1a80 LM |
198 | return; |
199 | } | |
200 | ||
201 | thermal_zone_device_update(tz); | |
202 | ||
203 | mutex_lock(&tz->lock); | |
204 | /* Find the level for which trip happened */ | |
205 | for (i = 0; i < of_thermal_get_ntrips(tz); i++) { | |
206 | tz->ops->get_trip_temp(tz, i, &temp); | |
207 | if (tz->last_temperature < temp) | |
208 | break; | |
209 | } | |
210 | ||
211 | snprintf(data, sizeof(data), "%u", i); | |
212 | kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp); | |
213 | mutex_unlock(&tz->lock); | |
214 | } | |
215 | ||
9d97e5c8 DK |
216 | /* |
217 | * TMU treats temperature as a mapped temperature code. | |
218 | * The temperature is converted differently depending on the calibration type. | |
219 | */ | |
f22d9c03 | 220 | static int temp_to_code(struct exynos_tmu_data *data, u8 temp) |
9d97e5c8 | 221 | { |
f22d9c03 | 222 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 DK |
223 | int temp_code; |
224 | ||
9d97e5c8 DK |
225 | switch (pdata->cal_type) { |
226 | case TYPE_TWO_POINT_TRIMMING: | |
bb34b4c8 ADK |
227 | temp_code = (temp - pdata->first_point_trim) * |
228 | (data->temp_error2 - data->temp_error1) / | |
229 | (pdata->second_point_trim - pdata->first_point_trim) + | |
230 | data->temp_error1; | |
9d97e5c8 DK |
231 | break; |
232 | case TYPE_ONE_POINT_TRIMMING: | |
bb34b4c8 | 233 | temp_code = temp + data->temp_error1 - pdata->first_point_trim; |
9d97e5c8 DK |
234 | break; |
235 | default: | |
bb34b4c8 | 236 | temp_code = temp + pdata->default_temp_offset; |
9d97e5c8 DK |
237 | break; |
238 | } | |
ddb31d43 | 239 | |
9d97e5c8 DK |
240 | return temp_code; |
241 | } | |
242 | ||
243 | /* | |
244 | * Calculate a temperature value from a temperature code. | |
245 | * The unit of the temperature is degree Celsius. | |
246 | */ | |
6c247393 | 247 | static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) |
9d97e5c8 | 248 | { |
f22d9c03 | 249 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 DK |
250 | int temp; |
251 | ||
9d97e5c8 DK |
252 | switch (pdata->cal_type) { |
253 | case TYPE_TWO_POINT_TRIMMING: | |
bb34b4c8 ADK |
254 | temp = (temp_code - data->temp_error1) * |
255 | (pdata->second_point_trim - pdata->first_point_trim) / | |
256 | (data->temp_error2 - data->temp_error1) + | |
257 | pdata->first_point_trim; | |
9d97e5c8 DK |
258 | break; |
259 | case TYPE_ONE_POINT_TRIMMING: | |
bb34b4c8 | 260 | temp = temp_code - data->temp_error1 + pdata->first_point_trim; |
9d97e5c8 DK |
261 | break; |
262 | default: | |
bb34b4c8 | 263 | temp = temp_code - pdata->default_temp_offset; |
9d97e5c8 DK |
264 | break; |
265 | } | |
ddb31d43 | 266 | |
9d97e5c8 DK |
267 | return temp; |
268 | } | |
269 | ||
8328a4b1 | 270 | static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) |
9d97e5c8 | 271 | { |
f22d9c03 | 272 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 | 273 | |
b8d582b9 | 274 | data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK; |
99d67fb9 | 275 | data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & |
b8d582b9 | 276 | EXYNOS_TMU_TEMP_MASK); |
f22d9c03 | 277 | |
5000806c ADK |
278 | if (!data->temp_error1 || |
279 | (pdata->min_efuse_value > data->temp_error1) || | |
280 | (data->temp_error1 > pdata->max_efuse_value)) | |
281 | data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK; | |
282 | ||
283 | if (!data->temp_error2) | |
284 | data->temp_error2 = | |
99d67fb9 | 285 | (pdata->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & |
5000806c | 286 | EXYNOS_TMU_TEMP_MASK; |
8328a4b1 | 287 | } |
f22d9c03 | 288 | |
fe87789c BZ |
289 | static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling) |
290 | { | |
3b6a1a80 LM |
291 | struct thermal_zone_device *tz = data->tzd; |
292 | const struct thermal_trip * const trips = | |
293 | of_thermal_get_trip_points(tz); | |
294 | unsigned long temp; | |
fe87789c | 295 | int i; |
c65d3473 | 296 | |
3b6a1a80 LM |
297 | if (!trips) { |
298 | pr_err("%s: Cannot get trip points from of-thermal.c!\n", | |
299 | __func__); | |
300 | return 0; | |
301 | } | |
f22d9c03 | 302 | |
3b6a1a80 LM |
303 | for (i = 0; i < of_thermal_get_ntrips(tz); i++) { |
304 | if (trips[i].type == THERMAL_TRIP_CRITICAL) | |
305 | continue; | |
306 | ||
307 | temp = trips[i].temperature / MCELSIUS; | |
fe87789c | 308 | if (falling) |
3b6a1a80 | 309 | temp -= (trips[i].hysteresis / MCELSIUS); |
fe87789c BZ |
310 | else |
311 | threshold &= ~(0xff << 8 * i); | |
f22d9c03 | 312 | |
fe87789c | 313 | threshold |= temp_to_code(data, temp) << 8 * i; |
9d97e5c8 | 314 | } |
fe87789c BZ |
315 | |
316 | return threshold; | |
317 | } | |
318 | ||
f22d9c03 | 319 | static int exynos_tmu_initialize(struct platform_device *pdev) |
9d97e5c8 | 320 | { |
f22d9c03 | 321 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
72d1100b | 322 | int ret; |
9d97e5c8 DK |
323 | |
324 | mutex_lock(&data->lock); | |
325 | clk_enable(data->clk); | |
14a11dc7 NKC |
326 | if (!IS_ERR(data->clk_sec)) |
327 | clk_enable(data->clk_sec); | |
72d1100b | 328 | ret = data->tmu_initialize(pdev); |
9d97e5c8 DK |
329 | clk_disable(data->clk); |
330 | mutex_unlock(&data->lock); | |
14a11dc7 NKC |
331 | if (!IS_ERR(data->clk_sec)) |
332 | clk_disable(data->clk_sec); | |
9d97e5c8 DK |
333 | |
334 | return ret; | |
335 | } | |
336 | ||
d00671c3 | 337 | static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) |
9d97e5c8 | 338 | { |
f22d9c03 | 339 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 | 340 | |
7575983c BZ |
341 | if (data->soc == SOC_ARCH_EXYNOS4412 || |
342 | data->soc == SOC_ARCH_EXYNOS3250) | |
343 | con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT); | |
86f5362e | 344 | |
99d67fb9 BZ |
345 | con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); |
346 | con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; | |
d0a0ce3e | 347 | |
99d67fb9 BZ |
348 | con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); |
349 | con |= (pdata->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); | |
d0a0ce3e ADK |
350 | |
351 | if (pdata->noise_cancel_mode) { | |
b9504a6a BZ |
352 | con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT); |
353 | con |= (pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT); | |
f22d9c03 ADK |
354 | } |
355 | ||
d00671c3 BZ |
356 | return con; |
357 | } | |
358 | ||
359 | static void exynos_tmu_control(struct platform_device *pdev, bool on) | |
360 | { | |
361 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
9d97e5c8 | 362 | |
d00671c3 BZ |
363 | mutex_lock(&data->lock); |
364 | clk_enable(data->clk); | |
37f9034f | 365 | data->tmu_control(pdev, on); |
9d97e5c8 DK |
366 | clk_disable(data->clk); |
367 | mutex_unlock(&data->lock); | |
368 | } | |
369 | ||
72d1100b | 370 | static int exynos4210_tmu_initialize(struct platform_device *pdev) |
9d97e5c8 | 371 | { |
72d1100b | 372 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
3b6a1a80 LM |
373 | struct thermal_zone_device *tz = data->tzd; |
374 | const struct thermal_trip * const trips = | |
375 | of_thermal_get_trip_points(tz); | |
72d1100b | 376 | int ret = 0, threshold_code, i; |
3b6a1a80 LM |
377 | unsigned long reference, temp; |
378 | unsigned int status; | |
379 | ||
380 | if (!trips) { | |
381 | pr_err("%s: Cannot get trip points from of-thermal.c!\n", | |
382 | __func__); | |
383 | ret = -ENODEV; | |
384 | goto out; | |
385 | } | |
9d97e5c8 | 386 | |
72d1100b BZ |
387 | status = readb(data->base + EXYNOS_TMU_REG_STATUS); |
388 | if (!status) { | |
389 | ret = -EBUSY; | |
390 | goto out; | |
391 | } | |
9d97e5c8 | 392 | |
72d1100b | 393 | sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); |
9d97e5c8 | 394 | |
72d1100b | 395 | /* Write temperature code for threshold */ |
3b6a1a80 LM |
396 | reference = trips[0].temperature / MCELSIUS; |
397 | threshold_code = temp_to_code(data, reference); | |
398 | if (threshold_code < 0) { | |
399 | ret = threshold_code; | |
400 | goto out; | |
401 | } | |
72d1100b BZ |
402 | writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); |
403 | ||
3b6a1a80 LM |
404 | for (i = 0; i < of_thermal_get_ntrips(tz); i++) { |
405 | temp = trips[i].temperature / MCELSIUS; | |
406 | writeb(temp - reference, data->base + | |
72d1100b | 407 | EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4); |
3b6a1a80 | 408 | } |
72d1100b | 409 | |
a7331f72 | 410 | data->tmu_clear_irqs(data); |
72d1100b BZ |
411 | out: |
412 | return ret; | |
413 | } | |
414 | ||
415 | static int exynos4412_tmu_initialize(struct platform_device *pdev) | |
416 | { | |
417 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
3b6a1a80 LM |
418 | const struct thermal_trip * const trips = |
419 | of_thermal_get_trip_points(data->tzd); | |
72d1100b BZ |
420 | unsigned int status, trim_info, con, ctrl, rising_threshold; |
421 | int ret = 0, threshold_code, i; | |
3b6a1a80 | 422 | unsigned long crit_temp = 0; |
72d1100b BZ |
423 | |
424 | status = readb(data->base + EXYNOS_TMU_REG_STATUS); | |
425 | if (!status) { | |
426 | ret = -EBUSY; | |
427 | goto out; | |
428 | } | |
429 | ||
430 | if (data->soc == SOC_ARCH_EXYNOS3250 || | |
431 | data->soc == SOC_ARCH_EXYNOS4412 || | |
432 | data->soc == SOC_ARCH_EXYNOS5250) { | |
433 | if (data->soc == SOC_ARCH_EXYNOS3250) { | |
434 | ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); | |
435 | ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; | |
436 | writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); | |
ddb31d43 | 437 | } |
72d1100b BZ |
438 | ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); |
439 | ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; | |
440 | writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); | |
441 | } | |
ddb31d43 | 442 | |
72d1100b BZ |
443 | /* On exynos5420 the triminfo register is in the shared space */ |
444 | if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) | |
445 | trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); | |
446 | else | |
447 | trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); | |
448 | ||
449 | sanitize_temp_error(data, trim_info); | |
450 | ||
451 | /* Write temperature code for rising and falling threshold */ | |
452 | rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE); | |
453 | rising_threshold = get_th_reg(data, rising_threshold, false); | |
454 | writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE); | |
455 | writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL); | |
456 | ||
a7331f72 | 457 | data->tmu_clear_irqs(data); |
72d1100b BZ |
458 | |
459 | /* if last threshold limit is also present */ | |
3b6a1a80 LM |
460 | for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) { |
461 | if (trips[i].type == THERMAL_TRIP_CRITICAL) { | |
462 | crit_temp = trips[i].temperature; | |
463 | break; | |
464 | } | |
72d1100b | 465 | } |
3b6a1a80 LM |
466 | |
467 | if (i == of_thermal_get_ntrips(data->tzd)) { | |
468 | pr_err("%s: No CRITICAL trip point defined at of-thermal.c!\n", | |
469 | __func__); | |
470 | ret = -EINVAL; | |
471 | goto out; | |
472 | } | |
473 | ||
474 | threshold_code = temp_to_code(data, crit_temp / MCELSIUS); | |
475 | /* 1-4 level to be assigned in th0 reg */ | |
476 | rising_threshold &= ~(0xff << 8 * i); | |
477 | rising_threshold |= threshold_code << 8 * i; | |
478 | writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE); | |
479 | con = readl(data->base + EXYNOS_TMU_REG_CONTROL); | |
480 | con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); | |
481 | writel(con, data->base + EXYNOS_TMU_REG_CONTROL); | |
482 | ||
ddb31d43 | 483 | out: |
72d1100b BZ |
484 | return ret; |
485 | } | |
9d97e5c8 | 486 | |
72d1100b BZ |
487 | static int exynos5440_tmu_initialize(struct platform_device *pdev) |
488 | { | |
489 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
72d1100b | 490 | unsigned int trim_info = 0, con, rising_threshold; |
3b6a1a80 LM |
491 | int ret = 0, threshold_code; |
492 | unsigned long crit_temp = 0; | |
72d1100b BZ |
493 | |
494 | /* | |
495 | * For exynos5440 soc triminfo value is swapped between TMU0 and | |
496 | * TMU2, so the below logic is needed. | |
497 | */ | |
498 | switch (data->id) { | |
499 | case 0: | |
500 | trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET + | |
501 | EXYNOS5440_TMU_S0_7_TRIM); | |
502 | break; | |
503 | case 1: | |
504 | trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM); | |
505 | break; | |
506 | case 2: | |
507 | trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET + | |
508 | EXYNOS5440_TMU_S0_7_TRIM); | |
509 | } | |
510 | sanitize_temp_error(data, trim_info); | |
511 | ||
512 | /* Write temperature code for rising and falling threshold */ | |
513 | rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0); | |
514 | rising_threshold = get_th_reg(data, rising_threshold, false); | |
515 | writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0); | |
516 | writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1); | |
517 | ||
a7331f72 | 518 | data->tmu_clear_irqs(data); |
72d1100b BZ |
519 | |
520 | /* if last threshold limit is also present */ | |
3b6a1a80 LM |
521 | if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) { |
522 | threshold_code = temp_to_code(data, crit_temp / MCELSIUS); | |
72d1100b BZ |
523 | /* 5th level to be assigned in th2 reg */ |
524 | rising_threshold = | |
525 | threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT; | |
526 | writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2); | |
527 | con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL); | |
528 | con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); | |
529 | writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL); | |
530 | } | |
531 | /* Clear the PMIN in the common TMU register */ | |
532 | if (!data->id) | |
533 | writel(0, data->base_second + EXYNOS5440_TMU_PMIN); | |
534 | return ret; | |
9d97e5c8 DK |
535 | } |
536 | ||
6c247393 AK |
537 | static int exynos7_tmu_initialize(struct platform_device *pdev) |
538 | { | |
539 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
540 | struct thermal_zone_device *tz = data->tzd; | |
541 | struct exynos_tmu_platform_data *pdata = data->pdata; | |
542 | unsigned int status, trim_info; | |
543 | unsigned int rising_threshold = 0, falling_threshold = 0; | |
544 | int ret = 0, threshold_code, i; | |
545 | unsigned long temp, temp_hist; | |
546 | unsigned int reg_off, bit_off; | |
547 | ||
548 | status = readb(data->base + EXYNOS_TMU_REG_STATUS); | |
549 | if (!status) { | |
550 | ret = -EBUSY; | |
551 | goto out; | |
552 | } | |
553 | ||
554 | trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); | |
555 | ||
556 | data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK; | |
557 | if (!data->temp_error1 || | |
558 | (pdata->min_efuse_value > data->temp_error1) || | |
559 | (data->temp_error1 > pdata->max_efuse_value)) | |
560 | data->temp_error1 = pdata->efuse_value & EXYNOS_TMU_TEMP_MASK; | |
561 | ||
562 | /* Write temperature code for rising and falling threshold */ | |
563 | for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) { | |
564 | /* | |
565 | * On exynos7 there are 4 rising and 4 falling threshold | |
566 | * registers (0x50-0x5c and 0x60-0x6c respectively). Each | |
567 | * register holds the value of two threshold levels (at bit | |
568 | * offsets 0 and 16). Based on the fact that there are atmost | |
569 | * eight possible trigger levels, calculate the register and | |
570 | * bit offsets where the threshold levels are to be written. | |
571 | * | |
572 | * e.g. EXYNOS7_THD_TEMP_RISE7_6 (0x50) | |
573 | * [24:16] - Threshold level 7 | |
574 | * [8:0] - Threshold level 6 | |
575 | * e.g. EXYNOS7_THD_TEMP_RISE5_4 (0x54) | |
576 | * [24:16] - Threshold level 5 | |
577 | * [8:0] - Threshold level 4 | |
578 | * | |
579 | * and similarly for falling thresholds. | |
580 | * | |
581 | * Based on the above, calculate the register and bit offsets | |
582 | * for rising/falling threshold levels and populate them. | |
583 | */ | |
584 | reg_off = ((7 - i) / 2) * 4; | |
585 | bit_off = ((8 - i) % 2); | |
586 | ||
587 | tz->ops->get_trip_temp(tz, i, &temp); | |
588 | temp /= MCELSIUS; | |
589 | ||
590 | tz->ops->get_trip_hyst(tz, i, &temp_hist); | |
591 | temp_hist = temp - (temp_hist / MCELSIUS); | |
592 | ||
593 | /* Set 9-bit temperature code for rising threshold levels */ | |
594 | threshold_code = temp_to_code(data, temp); | |
595 | rising_threshold = readl(data->base + | |
596 | EXYNOS7_THD_TEMP_RISE7_6 + reg_off); | |
597 | rising_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); | |
598 | rising_threshold |= threshold_code << (16 * bit_off); | |
599 | writel(rising_threshold, | |
600 | data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); | |
601 | ||
602 | /* Set 9-bit temperature code for falling threshold levels */ | |
603 | threshold_code = temp_to_code(data, temp_hist); | |
604 | falling_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); | |
605 | falling_threshold |= threshold_code << (16 * bit_off); | |
606 | writel(falling_threshold, | |
607 | data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); | |
608 | } | |
609 | ||
610 | data->tmu_clear_irqs(data); | |
611 | out: | |
612 | return ret; | |
613 | } | |
614 | ||
37f9034f | 615 | static void exynos4210_tmu_control(struct platform_device *pdev, bool on) |
bffd1f8a | 616 | { |
37f9034f | 617 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
3b6a1a80 | 618 | struct thermal_zone_device *tz = data->tzd; |
37f9034f | 619 | unsigned int con, interrupt_en; |
bffd1f8a | 620 | |
37f9034f | 621 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); |
bffd1f8a | 622 | |
37f9034f BZ |
623 | if (on) { |
624 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | |
625 | interrupt_en = | |
3b6a1a80 LM |
626 | (of_thermal_is_trip_valid(tz, 3) |
627 | << EXYNOS_TMU_INTEN_RISE3_SHIFT) | | |
628 | (of_thermal_is_trip_valid(tz, 2) | |
629 | << EXYNOS_TMU_INTEN_RISE2_SHIFT) | | |
630 | (of_thermal_is_trip_valid(tz, 1) | |
631 | << EXYNOS_TMU_INTEN_RISE1_SHIFT) | | |
632 | (of_thermal_is_trip_valid(tz, 0) | |
633 | << EXYNOS_TMU_INTEN_RISE0_SHIFT); | |
634 | ||
e0761533 | 635 | if (data->soc != SOC_ARCH_EXYNOS4210) |
37f9034f BZ |
636 | interrupt_en |= |
637 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; | |
638 | } else { | |
639 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); | |
640 | interrupt_en = 0; /* Disable all interrupts */ | |
641 | } | |
642 | writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); | |
643 | writel(con, data->base + EXYNOS_TMU_REG_CONTROL); | |
644 | } | |
645 | ||
646 | static void exynos5440_tmu_control(struct platform_device *pdev, bool on) | |
647 | { | |
648 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
3b6a1a80 | 649 | struct thermal_zone_device *tz = data->tzd; |
37f9034f BZ |
650 | unsigned int con, interrupt_en; |
651 | ||
652 | con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL)); | |
653 | ||
654 | if (on) { | |
655 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | |
656 | interrupt_en = | |
3b6a1a80 LM |
657 | (of_thermal_is_trip_valid(tz, 3) |
658 | << EXYNOS5440_TMU_INTEN_RISE3_SHIFT) | | |
659 | (of_thermal_is_trip_valid(tz, 2) | |
660 | << EXYNOS5440_TMU_INTEN_RISE2_SHIFT) | | |
661 | (of_thermal_is_trip_valid(tz, 1) | |
662 | << EXYNOS5440_TMU_INTEN_RISE1_SHIFT) | | |
663 | (of_thermal_is_trip_valid(tz, 0) | |
664 | << EXYNOS5440_TMU_INTEN_RISE0_SHIFT); | |
665 | interrupt_en |= | |
666 | interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT; | |
37f9034f BZ |
667 | } else { |
668 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); | |
669 | interrupt_en = 0; /* Disable all interrupts */ | |
670 | } | |
671 | writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN); | |
672 | writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL); | |
673 | } | |
674 | ||
6c247393 AK |
675 | static void exynos7_tmu_control(struct platform_device *pdev, bool on) |
676 | { | |
677 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); | |
678 | struct thermal_zone_device *tz = data->tzd; | |
679 | unsigned int con, interrupt_en; | |
680 | ||
681 | con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); | |
682 | ||
683 | if (on) { | |
684 | con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); | |
685 | interrupt_en = | |
686 | (of_thermal_is_trip_valid(tz, 7) | |
687 | << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | | |
688 | (of_thermal_is_trip_valid(tz, 6) | |
689 | << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | | |
690 | (of_thermal_is_trip_valid(tz, 5) | |
691 | << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | | |
692 | (of_thermal_is_trip_valid(tz, 4) | |
693 | << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | | |
694 | (of_thermal_is_trip_valid(tz, 3) | |
695 | << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | | |
696 | (of_thermal_is_trip_valid(tz, 2) | |
697 | << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | | |
698 | (of_thermal_is_trip_valid(tz, 1) | |
699 | << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | | |
700 | (of_thermal_is_trip_valid(tz, 0) | |
701 | << EXYNOS7_TMU_INTEN_RISE0_SHIFT); | |
702 | ||
703 | interrupt_en |= | |
704 | interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; | |
705 | } else { | |
706 | con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); | |
707 | interrupt_en = 0; /* Disable all interrupts */ | |
708 | } | |
709 | con |= 1 << EXYNOS7_PD_DET_EN_SHIFT; | |
710 | ||
711 | writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); | |
712 | writel(con, data->base + EXYNOS_TMU_REG_CONTROL); | |
713 | } | |
714 | ||
3b6a1a80 | 715 | static int exynos_get_temp(void *p, long *temp) |
9d97e5c8 | 716 | { |
3b6a1a80 LM |
717 | struct exynos_tmu_data *data = p; |
718 | ||
4531fa16 | 719 | if (!data || !data->tmu_read) |
3b6a1a80 | 720 | return -EINVAL; |
bffd1f8a ADK |
721 | |
722 | mutex_lock(&data->lock); | |
723 | clk_enable(data->clk); | |
3b6a1a80 LM |
724 | |
725 | *temp = code_to_temp(data, data->tmu_read(data)) * MCELSIUS; | |
726 | ||
9d97e5c8 DK |
727 | clk_disable(data->clk); |
728 | mutex_unlock(&data->lock); | |
bffd1f8a | 729 | |
3b6a1a80 | 730 | return 0; |
9d97e5c8 | 731 | } |
bffd1f8a | 732 | |
bffd1f8a | 733 | #ifdef CONFIG_THERMAL_EMULATION |
154013ea BZ |
734 | static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, |
735 | unsigned long temp) | |
736 | { | |
bffd1f8a ADK |
737 | if (temp) { |
738 | temp /= MCELSIUS; | |
739 | ||
d564b55a | 740 | if (data->soc != SOC_ARCH_EXYNOS5440) { |
154013ea BZ |
741 | val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); |
742 | val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); | |
f4dae753 | 743 | } |
6c247393 AK |
744 | if (data->soc == SOC_ARCH_EXYNOS7) { |
745 | val &= ~(EXYNOS7_EMUL_DATA_MASK << | |
746 | EXYNOS7_EMUL_DATA_SHIFT); | |
747 | val |= (temp_to_code(data, temp) << | |
748 | EXYNOS7_EMUL_DATA_SHIFT) | | |
749 | EXYNOS_EMUL_ENABLE; | |
750 | } else { | |
751 | val &= ~(EXYNOS_EMUL_DATA_MASK << | |
752 | EXYNOS_EMUL_DATA_SHIFT); | |
753 | val |= (temp_to_code(data, temp) << | |
754 | EXYNOS_EMUL_DATA_SHIFT) | | |
755 | EXYNOS_EMUL_ENABLE; | |
756 | } | |
bffd1f8a | 757 | } else { |
b8d582b9 | 758 | val &= ~EXYNOS_EMUL_ENABLE; |
bffd1f8a ADK |
759 | } |
760 | ||
154013ea BZ |
761 | return val; |
762 | } | |
763 | ||
285d994a BZ |
764 | static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, |
765 | unsigned long temp) | |
766 | { | |
767 | unsigned int val; | |
768 | u32 emul_con; | |
769 | ||
770 | if (data->soc == SOC_ARCH_EXYNOS5260) | |
771 | emul_con = EXYNOS5260_EMUL_CON; | |
6c247393 AK |
772 | else if (data->soc == SOC_ARCH_EXYNOS7) |
773 | emul_con = EXYNOS7_TMU_REG_EMUL_CON; | |
285d994a BZ |
774 | else |
775 | emul_con = EXYNOS_EMUL_CON; | |
776 | ||
777 | val = readl(data->base + emul_con); | |
778 | val = get_emul_con_reg(data, val, temp); | |
779 | writel(val, data->base + emul_con); | |
780 | } | |
781 | ||
782 | static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data, | |
783 | unsigned long temp) | |
784 | { | |
785 | unsigned int val; | |
786 | ||
787 | val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG); | |
788 | val = get_emul_con_reg(data, val, temp); | |
789 | writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG); | |
790 | } | |
791 | ||
bffd1f8a ADK |
792 | static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) |
793 | { | |
794 | struct exynos_tmu_data *data = drv_data; | |
bffd1f8a ADK |
795 | int ret = -EINVAL; |
796 | ||
ef3f80fc | 797 | if (data->soc == SOC_ARCH_EXYNOS4210) |
bffd1f8a | 798 | goto out; |
bffd1f8a | 799 | |
bffd1f8a ADK |
800 | if (temp && temp < MCELSIUS) |
801 | goto out; | |
802 | ||
803 | mutex_lock(&data->lock); | |
804 | clk_enable(data->clk); | |
285d994a | 805 | data->tmu_set_emulation(data, temp); |
bffd1f8a ADK |
806 | clk_disable(data->clk); |
807 | mutex_unlock(&data->lock); | |
808 | return 0; | |
809 | out: | |
810 | return ret; | |
811 | } | |
812 | #else | |
285d994a BZ |
813 | #define exynos4412_tmu_set_emulation NULL |
814 | #define exynos5440_tmu_set_emulation NULL | |
bffd1f8a ADK |
815 | static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) |
816 | { return -EINVAL; } | |
afae1442 | 817 | #endif /* CONFIG_THERMAL_EMULATION */ |
bffd1f8a | 818 | |
b79985ca BZ |
819 | static int exynos4210_tmu_read(struct exynos_tmu_data *data) |
820 | { | |
821 | int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); | |
822 | ||
823 | /* "temp_code" should range between 75 and 175 */ | |
824 | return (ret < 75 || ret > 175) ? -ENODATA : ret; | |
825 | } | |
826 | ||
827 | static int exynos4412_tmu_read(struct exynos_tmu_data *data) | |
828 | { | |
829 | return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); | |
830 | } | |
831 | ||
832 | static int exynos5440_tmu_read(struct exynos_tmu_data *data) | |
833 | { | |
834 | return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP); | |
835 | } | |
836 | ||
6c247393 AK |
837 | static int exynos7_tmu_read(struct exynos_tmu_data *data) |
838 | { | |
839 | return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & | |
840 | EXYNOS7_TMU_TEMP_MASK; | |
841 | } | |
842 | ||
f22d9c03 | 843 | static void exynos_tmu_work(struct work_struct *work) |
9d97e5c8 | 844 | { |
f22d9c03 ADK |
845 | struct exynos_tmu_data *data = container_of(work, |
846 | struct exynos_tmu_data, irq_work); | |
b835ced1 | 847 | unsigned int val_type; |
a0395eee | 848 | |
14a11dc7 NKC |
849 | if (!IS_ERR(data->clk_sec)) |
850 | clk_enable(data->clk_sec); | |
a0395eee | 851 | /* Find which sensor generated this interrupt */ |
421d5d12 BZ |
852 | if (data->soc == SOC_ARCH_EXYNOS5440) { |
853 | val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS); | |
a0395eee ADK |
854 | if (!((val_type >> data->id) & 0x1)) |
855 | goto out; | |
856 | } | |
14a11dc7 NKC |
857 | if (!IS_ERR(data->clk_sec)) |
858 | clk_disable(data->clk_sec); | |
9d97e5c8 | 859 | |
3b6a1a80 | 860 | exynos_report_trigger(data); |
9d97e5c8 DK |
861 | mutex_lock(&data->lock); |
862 | clk_enable(data->clk); | |
b8d582b9 | 863 | |
a4463c4f | 864 | /* TODO: take action based on particular interrupt */ |
a7331f72 | 865 | data->tmu_clear_irqs(data); |
b8d582b9 | 866 | |
9d97e5c8 DK |
867 | clk_disable(data->clk); |
868 | mutex_unlock(&data->lock); | |
a0395eee | 869 | out: |
f22d9c03 | 870 | enable_irq(data->irq); |
9d97e5c8 DK |
871 | } |
872 | ||
a7331f72 BZ |
873 | static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) |
874 | { | |
875 | unsigned int val_irq; | |
876 | u32 tmu_intstat, tmu_intclear; | |
877 | ||
878 | if (data->soc == SOC_ARCH_EXYNOS5260) { | |
879 | tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; | |
880 | tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; | |
6c247393 AK |
881 | } else if (data->soc == SOC_ARCH_EXYNOS7) { |
882 | tmu_intstat = EXYNOS7_TMU_REG_INTPEND; | |
883 | tmu_intclear = EXYNOS7_TMU_REG_INTPEND; | |
a7331f72 BZ |
884 | } else { |
885 | tmu_intstat = EXYNOS_TMU_REG_INTSTAT; | |
886 | tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; | |
887 | } | |
888 | ||
889 | val_irq = readl(data->base + tmu_intstat); | |
890 | /* | |
891 | * Clear the interrupts. Please note that the documentation for | |
892 | * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly | |
893 | * states that INTCLEAR register has a different placing of bits | |
894 | * responsible for FALL IRQs than INTSTAT register. Exynos5420 | |
895 | * and Exynos5440 documentation is correct (Exynos4210 doesn't | |
896 | * support FALL IRQs at all). | |
897 | */ | |
898 | writel(val_irq, data->base + tmu_intclear); | |
899 | } | |
900 | ||
901 | static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data) | |
902 | { | |
903 | unsigned int val_irq; | |
904 | ||
905 | val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ); | |
906 | /* clear the interrupts */ | |
907 | writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ); | |
908 | } | |
909 | ||
f22d9c03 | 910 | static irqreturn_t exynos_tmu_irq(int irq, void *id) |
9d97e5c8 | 911 | { |
f22d9c03 | 912 | struct exynos_tmu_data *data = id; |
9d97e5c8 DK |
913 | |
914 | disable_irq_nosync(irq); | |
915 | schedule_work(&data->irq_work); | |
916 | ||
917 | return IRQ_HANDLED; | |
918 | } | |
17be868e | 919 | |
17be868e | 920 | static const struct of_device_id exynos_tmu_match[] = { |
b71d399c CC |
921 | { .compatible = "samsung,exynos3250-tmu", }, |
922 | { .compatible = "samsung,exynos4210-tmu", }, | |
923 | { .compatible = "samsung,exynos4412-tmu", }, | |
924 | { .compatible = "samsung,exynos5250-tmu", }, | |
925 | { .compatible = "samsung,exynos5260-tmu", }, | |
926 | { .compatible = "samsung,exynos5420-tmu", }, | |
927 | { .compatible = "samsung,exynos5420-tmu-ext-triminfo", }, | |
928 | { .compatible = "samsung,exynos5440-tmu", }, | |
929 | { .compatible = "samsung,exynos7-tmu", }, | |
930 | { /* sentinel */ }, | |
17be868e ADK |
931 | }; |
932 | MODULE_DEVICE_TABLE(of, exynos_tmu_match); | |
17be868e | 933 | |
3b6a1a80 | 934 | static int exynos_of_get_soc_type(struct device_node *np) |
17be868e | 935 | { |
3b6a1a80 LM |
936 | if (of_device_is_compatible(np, "samsung,exynos3250-tmu")) |
937 | return SOC_ARCH_EXYNOS3250; | |
938 | else if (of_device_is_compatible(np, "samsung,exynos4210-tmu")) | |
939 | return SOC_ARCH_EXYNOS4210; | |
940 | else if (of_device_is_compatible(np, "samsung,exynos4412-tmu")) | |
941 | return SOC_ARCH_EXYNOS4412; | |
942 | else if (of_device_is_compatible(np, "samsung,exynos5250-tmu")) | |
943 | return SOC_ARCH_EXYNOS5250; | |
944 | else if (of_device_is_compatible(np, "samsung,exynos5260-tmu")) | |
945 | return SOC_ARCH_EXYNOS5260; | |
946 | else if (of_device_is_compatible(np, "samsung,exynos5420-tmu")) | |
947 | return SOC_ARCH_EXYNOS5420; | |
948 | else if (of_device_is_compatible(np, | |
949 | "samsung,exynos5420-tmu-ext-triminfo")) | |
950 | return SOC_ARCH_EXYNOS5420_TRIMINFO; | |
951 | else if (of_device_is_compatible(np, "samsung,exynos5440-tmu")) | |
952 | return SOC_ARCH_EXYNOS5440; | |
6c247393 AK |
953 | else if (of_device_is_compatible(np, "samsung,exynos7-tmu")) |
954 | return SOC_ARCH_EXYNOS7; | |
3b6a1a80 LM |
955 | |
956 | return -EINVAL; | |
957 | } | |
958 | ||
959 | static int exynos_of_sensor_conf(struct device_node *np, | |
960 | struct exynos_tmu_platform_data *pdata) | |
961 | { | |
962 | u32 value; | |
963 | int ret; | |
964 | ||
965 | of_node_get(np); | |
966 | ||
967 | ret = of_property_read_u32(np, "samsung,tmu_gain", &value); | |
968 | pdata->gain = (u8)value; | |
969 | of_property_read_u32(np, "samsung,tmu_reference_voltage", &value); | |
970 | pdata->reference_voltage = (u8)value; | |
971 | of_property_read_u32(np, "samsung,tmu_noise_cancel_mode", &value); | |
972 | pdata->noise_cancel_mode = (u8)value; | |
973 | ||
974 | of_property_read_u32(np, "samsung,tmu_efuse_value", | |
975 | &pdata->efuse_value); | |
976 | of_property_read_u32(np, "samsung,tmu_min_efuse_value", | |
977 | &pdata->min_efuse_value); | |
978 | of_property_read_u32(np, "samsung,tmu_max_efuse_value", | |
979 | &pdata->max_efuse_value); | |
980 | ||
981 | of_property_read_u32(np, "samsung,tmu_first_point_trim", &value); | |
982 | pdata->first_point_trim = (u8)value; | |
983 | of_property_read_u32(np, "samsung,tmu_second_point_trim", &value); | |
984 | pdata->second_point_trim = (u8)value; | |
985 | of_property_read_u32(np, "samsung,tmu_default_temp_offset", &value); | |
986 | pdata->default_temp_offset = (u8)value; | |
987 | ||
988 | of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type); | |
989 | of_property_read_u32(np, "samsung,tmu_cal_mode", &pdata->cal_mode); | |
990 | ||
991 | of_node_put(np); | |
992 | return 0; | |
7e0b55e6 | 993 | } |
bbf63be4 | 994 | |
cebe7373 | 995 | static int exynos_map_dt_data(struct platform_device *pdev) |
9d97e5c8 | 996 | { |
cebe7373 ADK |
997 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
998 | struct exynos_tmu_platform_data *pdata; | |
999 | struct resource res; | |
498d22f6 | 1000 | int ret; |
cebe7373 | 1001 | |
73b5b1d7 | 1002 | if (!data || !pdev->dev.of_node) |
cebe7373 | 1003 | return -ENODEV; |
9d97e5c8 | 1004 | |
498d22f6 ADK |
1005 | /* |
1006 | * Try enabling the regulator if found | |
1007 | * TODO: Add regulator as an SOC feature, so that regulator enable | |
1008 | * is a compulsory call. | |
1009 | */ | |
1010 | data->regulator = devm_regulator_get(&pdev->dev, "vtmu"); | |
1011 | if (!IS_ERR(data->regulator)) { | |
1012 | ret = regulator_enable(data->regulator); | |
1013 | if (ret) { | |
1014 | dev_err(&pdev->dev, "failed to enable vtmu\n"); | |
1015 | return ret; | |
1016 | } | |
1017 | } else { | |
1018 | dev_info(&pdev->dev, "Regulator node (vtmu) not found\n"); | |
1019 | } | |
1020 | ||
cebe7373 ADK |
1021 | data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); |
1022 | if (data->id < 0) | |
1023 | data->id = 0; | |
17be868e | 1024 | |
cebe7373 ADK |
1025 | data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); |
1026 | if (data->irq <= 0) { | |
1027 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
1028 | return -ENODEV; | |
1029 | } | |
1030 | ||
1031 | if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { | |
1032 | dev_err(&pdev->dev, "failed to get Resource 0\n"); | |
1033 | return -ENODEV; | |
1034 | } | |
1035 | ||
1036 | data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); | |
1037 | if (!data->base) { | |
1038 | dev_err(&pdev->dev, "Failed to ioremap memory\n"); | |
1039 | return -EADDRNOTAVAIL; | |
1040 | } | |
1041 | ||
3b6a1a80 LM |
1042 | pdata = devm_kzalloc(&pdev->dev, |
1043 | sizeof(struct exynos_tmu_platform_data), | |
1044 | GFP_KERNEL); | |
1045 | if (!pdata) | |
1046 | return -ENOMEM; | |
56adb9ef | 1047 | |
3b6a1a80 | 1048 | exynos_of_sensor_conf(pdev->dev.of_node, pdata); |
cebe7373 | 1049 | data->pdata = pdata; |
3b6a1a80 | 1050 | data->soc = exynos_of_get_soc_type(pdev->dev.of_node); |
56adb9ef BZ |
1051 | |
1052 | switch (data->soc) { | |
1053 | case SOC_ARCH_EXYNOS4210: | |
1054 | data->tmu_initialize = exynos4210_tmu_initialize; | |
1055 | data->tmu_control = exynos4210_tmu_control; | |
1056 | data->tmu_read = exynos4210_tmu_read; | |
1057 | data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; | |
1058 | break; | |
1059 | case SOC_ARCH_EXYNOS3250: | |
1060 | case SOC_ARCH_EXYNOS4412: | |
1061 | case SOC_ARCH_EXYNOS5250: | |
1062 | case SOC_ARCH_EXYNOS5260: | |
1063 | case SOC_ARCH_EXYNOS5420: | |
1064 | case SOC_ARCH_EXYNOS5420_TRIMINFO: | |
1065 | data->tmu_initialize = exynos4412_tmu_initialize; | |
1066 | data->tmu_control = exynos4210_tmu_control; | |
1067 | data->tmu_read = exynos4412_tmu_read; | |
1068 | data->tmu_set_emulation = exynos4412_tmu_set_emulation; | |
1069 | data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; | |
1070 | break; | |
1071 | case SOC_ARCH_EXYNOS5440: | |
1072 | data->tmu_initialize = exynos5440_tmu_initialize; | |
1073 | data->tmu_control = exynos5440_tmu_control; | |
1074 | data->tmu_read = exynos5440_tmu_read; | |
1075 | data->tmu_set_emulation = exynos5440_tmu_set_emulation; | |
1076 | data->tmu_clear_irqs = exynos5440_tmu_clear_irqs; | |
1077 | break; | |
6c247393 AK |
1078 | case SOC_ARCH_EXYNOS7: |
1079 | data->tmu_initialize = exynos7_tmu_initialize; | |
1080 | data->tmu_control = exynos7_tmu_control; | |
1081 | data->tmu_read = exynos7_tmu_read; | |
1082 | data->tmu_set_emulation = exynos4412_tmu_set_emulation; | |
1083 | data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; | |
1084 | break; | |
56adb9ef BZ |
1085 | default: |
1086 | dev_err(&pdev->dev, "Platform not supported\n"); | |
1087 | return -EINVAL; | |
1088 | } | |
1089 | ||
d9b6ee14 ADK |
1090 | /* |
1091 | * Check if the TMU shares some registers and then try to map the | |
1092 | * memory of common registers. | |
1093 | */ | |
56adb9ef BZ |
1094 | if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO && |
1095 | data->soc != SOC_ARCH_EXYNOS5440) | |
d9b6ee14 ADK |
1096 | return 0; |
1097 | ||
1098 | if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { | |
1099 | dev_err(&pdev->dev, "failed to get Resource 1\n"); | |
1100 | return -ENODEV; | |
1101 | } | |
1102 | ||
9025d563 | 1103 | data->base_second = devm_ioremap(&pdev->dev, res.start, |
d9b6ee14 | 1104 | resource_size(&res)); |
9025d563 | 1105 | if (!data->base_second) { |
d9b6ee14 ADK |
1106 | dev_err(&pdev->dev, "Failed to ioremap memory\n"); |
1107 | return -ENOMEM; | |
1108 | } | |
cebe7373 ADK |
1109 | |
1110 | return 0; | |
1111 | } | |
1112 | ||
3b6a1a80 LM |
1113 | static struct thermal_zone_of_device_ops exynos_sensor_ops = { |
1114 | .get_temp = exynos_get_temp, | |
1115 | .set_emul_temp = exynos_tmu_set_emulation, | |
1116 | }; | |
1117 | ||
cebe7373 ADK |
1118 | static int exynos_tmu_probe(struct platform_device *pdev) |
1119 | { | |
cebe7373 | 1120 | struct exynos_tmu_platform_data *pdata; |
3b6a1a80 LM |
1121 | struct exynos_tmu_data *data; |
1122 | int ret; | |
cebe7373 | 1123 | |
79e093c3 ADK |
1124 | data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), |
1125 | GFP_KERNEL); | |
2a9675b3 | 1126 | if (!data) |
9d97e5c8 | 1127 | return -ENOMEM; |
9d97e5c8 | 1128 | |
cebe7373 ADK |
1129 | platform_set_drvdata(pdev, data); |
1130 | mutex_init(&data->lock); | |
9d97e5c8 | 1131 | |
3b6a1a80 LM |
1132 | data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, |
1133 | &exynos_sensor_ops); | |
1134 | if (IS_ERR(data->tzd)) { | |
1135 | pr_err("thermal: tz: %p ERROR\n", data->tzd); | |
1136 | return PTR_ERR(data->tzd); | |
1137 | } | |
cebe7373 ADK |
1138 | ret = exynos_map_dt_data(pdev); |
1139 | if (ret) | |
3b6a1a80 | 1140 | goto err_sensor; |
9d97e5c8 | 1141 | |
cebe7373 | 1142 | pdata = data->pdata; |
9d97e5c8 | 1143 | |
cebe7373 | 1144 | INIT_WORK(&data->irq_work, exynos_tmu_work); |
9d97e5c8 | 1145 | |
2a16279c | 1146 | data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); |
9d97e5c8 | 1147 | if (IS_ERR(data->clk)) { |
9d97e5c8 | 1148 | dev_err(&pdev->dev, "Failed to get clock\n"); |
3b6a1a80 LM |
1149 | ret = PTR_ERR(data->clk); |
1150 | goto err_sensor; | |
9d97e5c8 DK |
1151 | } |
1152 | ||
14a11dc7 NKC |
1153 | data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); |
1154 | if (IS_ERR(data->clk_sec)) { | |
1155 | if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { | |
1156 | dev_err(&pdev->dev, "Failed to get triminfo clock\n"); | |
3b6a1a80 LM |
1157 | ret = PTR_ERR(data->clk_sec); |
1158 | goto err_sensor; | |
14a11dc7 NKC |
1159 | } |
1160 | } else { | |
1161 | ret = clk_prepare(data->clk_sec); | |
1162 | if (ret) { | |
1163 | dev_err(&pdev->dev, "Failed to get clock\n"); | |
3b6a1a80 | 1164 | goto err_sensor; |
14a11dc7 NKC |
1165 | } |
1166 | } | |
1167 | ||
2a16279c | 1168 | ret = clk_prepare(data->clk); |
14a11dc7 NKC |
1169 | if (ret) { |
1170 | dev_err(&pdev->dev, "Failed to get clock\n"); | |
1171 | goto err_clk_sec; | |
1172 | } | |
2a16279c | 1173 | |
6c247393 AK |
1174 | if (data->soc == SOC_ARCH_EXYNOS7) { |
1175 | data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); | |
1176 | if (IS_ERR(data->sclk)) { | |
1177 | dev_err(&pdev->dev, "Failed to get sclk\n"); | |
1178 | goto err_clk; | |
1179 | } else { | |
1180 | ret = clk_prepare_enable(data->sclk); | |
1181 | if (ret) { | |
1182 | dev_err(&pdev->dev, "Failed to enable sclk\n"); | |
1183 | goto err_clk; | |
1184 | } | |
1185 | } | |
1186 | } | |
1187 | ||
f22d9c03 | 1188 | ret = exynos_tmu_initialize(pdev); |
9d97e5c8 DK |
1189 | if (ret) { |
1190 | dev_err(&pdev->dev, "Failed to initialize TMU\n"); | |
6c247393 | 1191 | goto err_sclk; |
9d97e5c8 DK |
1192 | } |
1193 | ||
cebe7373 ADK |
1194 | ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, |
1195 | IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); | |
1196 | if (ret) { | |
1197 | dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); | |
6c247393 | 1198 | goto err_sclk; |
cebe7373 | 1199 | } |
bbf63be4 | 1200 | |
3b6a1a80 | 1201 | exynos_tmu_control(pdev, true); |
9d97e5c8 | 1202 | return 0; |
6c247393 AK |
1203 | err_sclk: |
1204 | clk_disable_unprepare(data->sclk); | |
9d97e5c8 | 1205 | err_clk: |
2a16279c | 1206 | clk_unprepare(data->clk); |
14a11dc7 NKC |
1207 | err_clk_sec: |
1208 | if (!IS_ERR(data->clk_sec)) | |
1209 | clk_unprepare(data->clk_sec); | |
3b6a1a80 LM |
1210 | err_sensor: |
1211 | thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); | |
1212 | ||
9d97e5c8 DK |
1213 | return ret; |
1214 | } | |
1215 | ||
4eab7a9e | 1216 | static int exynos_tmu_remove(struct platform_device *pdev) |
9d97e5c8 | 1217 | { |
f22d9c03 | 1218 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
3b6a1a80 | 1219 | struct thermal_zone_device *tzd = data->tzd; |
9d97e5c8 | 1220 | |
3b6a1a80 | 1221 | thermal_zone_of_sensor_unregister(&pdev->dev, tzd); |
4215688e BZ |
1222 | exynos_tmu_control(pdev, false); |
1223 | ||
6c247393 | 1224 | clk_disable_unprepare(data->sclk); |
2a16279c | 1225 | clk_unprepare(data->clk); |
14a11dc7 NKC |
1226 | if (!IS_ERR(data->clk_sec)) |
1227 | clk_unprepare(data->clk_sec); | |
9d97e5c8 | 1228 | |
498d22f6 ADK |
1229 | if (!IS_ERR(data->regulator)) |
1230 | regulator_disable(data->regulator); | |
1231 | ||
9d97e5c8 DK |
1232 | return 0; |
1233 | } | |
1234 | ||
08cd6753 | 1235 | #ifdef CONFIG_PM_SLEEP |
f22d9c03 | 1236 | static int exynos_tmu_suspend(struct device *dev) |
9d97e5c8 | 1237 | { |
f22d9c03 | 1238 | exynos_tmu_control(to_platform_device(dev), false); |
9d97e5c8 DK |
1239 | |
1240 | return 0; | |
1241 | } | |
1242 | ||
f22d9c03 | 1243 | static int exynos_tmu_resume(struct device *dev) |
9d97e5c8 | 1244 | { |
08cd6753 RW |
1245 | struct platform_device *pdev = to_platform_device(dev); |
1246 | ||
f22d9c03 ADK |
1247 | exynos_tmu_initialize(pdev); |
1248 | exynos_tmu_control(pdev, true); | |
9d97e5c8 DK |
1249 | |
1250 | return 0; | |
1251 | } | |
08cd6753 | 1252 | |
f22d9c03 ADK |
1253 | static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, |
1254 | exynos_tmu_suspend, exynos_tmu_resume); | |
1255 | #define EXYNOS_TMU_PM (&exynos_tmu_pm) | |
9d97e5c8 | 1256 | #else |
f22d9c03 | 1257 | #define EXYNOS_TMU_PM NULL |
9d97e5c8 DK |
1258 | #endif |
1259 | ||
f22d9c03 | 1260 | static struct platform_driver exynos_tmu_driver = { |
9d97e5c8 | 1261 | .driver = { |
f22d9c03 | 1262 | .name = "exynos-tmu", |
f22d9c03 | 1263 | .pm = EXYNOS_TMU_PM, |
73b5b1d7 | 1264 | .of_match_table = exynos_tmu_match, |
9d97e5c8 | 1265 | }, |
f22d9c03 | 1266 | .probe = exynos_tmu_probe, |
4eab7a9e | 1267 | .remove = exynos_tmu_remove, |
9d97e5c8 DK |
1268 | }; |
1269 | ||
f22d9c03 | 1270 | module_platform_driver(exynos_tmu_driver); |
9d97e5c8 | 1271 | |
f22d9c03 | 1272 | MODULE_DESCRIPTION("EXYNOS TMU Driver"); |
9d97e5c8 DK |
1273 | MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); |
1274 | MODULE_LICENSE("GPL"); | |
f22d9c03 | 1275 | MODULE_ALIAS("platform:exynos-tmu"); |