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Commit | Line | Data |
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9d97e5c8 | 1 | /* |
59dfa54c | 2 | * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) |
9d97e5c8 DK |
3 | * |
4 | * Copyright (C) 2011 Samsung Electronics | |
5 | * Donggeun Kim <dg77.kim@samsung.com> | |
c48cbba6 | 6 | * Amit Daniel Kachhap <amit.kachhap@linaro.org> |
9d97e5c8 DK |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
9d97e5c8 | 24 | #include <linux/clk.h> |
9d97e5c8 | 25 | #include <linux/io.h> |
1b678641 ADK |
26 | #include <linux/interrupt.h> |
27 | #include <linux/module.h> | |
f22d9c03 | 28 | #include <linux/of.h> |
cebe7373 ADK |
29 | #include <linux/of_address.h> |
30 | #include <linux/of_irq.h> | |
1b678641 | 31 | #include <linux/platform_device.h> |
1b678641 ADK |
32 | |
33 | #include "exynos_thermal_common.h" | |
0c1836a6 | 34 | #include "exynos_tmu.h" |
e6b7991e | 35 | #include "exynos_tmu_data.h" |
f22d9c03 | 36 | |
cebe7373 ADK |
37 | /** |
38 | * struct exynos_tmu_data : A structure to hold the private data of the TMU | |
39 | driver | |
40 | * @id: identifier of the one instance of the TMU controller. | |
41 | * @pdata: pointer to the tmu platform/configuration data | |
42 | * @base: base address of the single instance of the TMU controller. | |
d9b6ee14 | 43 | * @base_common: base address of the common registers of the TMU controller. |
cebe7373 ADK |
44 | * @irq: irq number of the TMU controller. |
45 | * @soc: id of the SOC type. | |
46 | * @irq_work: pointer to the irq work structure. | |
47 | * @lock: lock to implement synchronization. | |
48 | * @clk: pointer to the clock structure. | |
49 | * @temp_error1: fused value of the first point trim. | |
50 | * @temp_error2: fused value of the second point trim. | |
51 | * @reg_conf: pointer to structure to register with core thermal. | |
52 | */ | |
f22d9c03 | 53 | struct exynos_tmu_data { |
cebe7373 | 54 | int id; |
f22d9c03 | 55 | struct exynos_tmu_platform_data *pdata; |
9d97e5c8 | 56 | void __iomem *base; |
d9b6ee14 | 57 | void __iomem *base_common; |
9d97e5c8 | 58 | int irq; |
f22d9c03 | 59 | enum soc_type soc; |
9d97e5c8 DK |
60 | struct work_struct irq_work; |
61 | struct mutex lock; | |
62 | struct clk *clk; | |
63 | u8 temp_error1, temp_error2; | |
cebe7373 | 64 | struct thermal_sensor_conf *reg_conf; |
9d97e5c8 DK |
65 | }; |
66 | ||
67 | /* | |
68 | * TMU treats temperature as a mapped temperature code. | |
69 | * The temperature is converted differently depending on the calibration type. | |
70 | */ | |
f22d9c03 | 71 | static int temp_to_code(struct exynos_tmu_data *data, u8 temp) |
9d97e5c8 | 72 | { |
f22d9c03 | 73 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 DK |
74 | int temp_code; |
75 | ||
f22d9c03 ADK |
76 | if (data->soc == SOC_ARCH_EXYNOS4210) |
77 | /* temp should range between 25 and 125 */ | |
78 | if (temp < 25 || temp > 125) { | |
79 | temp_code = -EINVAL; | |
80 | goto out; | |
81 | } | |
9d97e5c8 DK |
82 | |
83 | switch (pdata->cal_type) { | |
84 | case TYPE_TWO_POINT_TRIMMING: | |
bb34b4c8 ADK |
85 | temp_code = (temp - pdata->first_point_trim) * |
86 | (data->temp_error2 - data->temp_error1) / | |
87 | (pdata->second_point_trim - pdata->first_point_trim) + | |
88 | data->temp_error1; | |
9d97e5c8 DK |
89 | break; |
90 | case TYPE_ONE_POINT_TRIMMING: | |
bb34b4c8 | 91 | temp_code = temp + data->temp_error1 - pdata->first_point_trim; |
9d97e5c8 DK |
92 | break; |
93 | default: | |
bb34b4c8 | 94 | temp_code = temp + pdata->default_temp_offset; |
9d97e5c8 DK |
95 | break; |
96 | } | |
97 | out: | |
98 | return temp_code; | |
99 | } | |
100 | ||
101 | /* | |
102 | * Calculate a temperature value from a temperature code. | |
103 | * The unit of the temperature is degree Celsius. | |
104 | */ | |
f22d9c03 | 105 | static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code) |
9d97e5c8 | 106 | { |
f22d9c03 | 107 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 DK |
108 | int temp; |
109 | ||
f22d9c03 ADK |
110 | if (data->soc == SOC_ARCH_EXYNOS4210) |
111 | /* temp_code should range between 75 and 175 */ | |
112 | if (temp_code < 75 || temp_code > 175) { | |
113 | temp = -ENODATA; | |
114 | goto out; | |
115 | } | |
9d97e5c8 DK |
116 | |
117 | switch (pdata->cal_type) { | |
118 | case TYPE_TWO_POINT_TRIMMING: | |
bb34b4c8 ADK |
119 | temp = (temp_code - data->temp_error1) * |
120 | (pdata->second_point_trim - pdata->first_point_trim) / | |
121 | (data->temp_error2 - data->temp_error1) + | |
122 | pdata->first_point_trim; | |
9d97e5c8 DK |
123 | break; |
124 | case TYPE_ONE_POINT_TRIMMING: | |
bb34b4c8 | 125 | temp = temp_code - data->temp_error1 + pdata->first_point_trim; |
9d97e5c8 DK |
126 | break; |
127 | default: | |
bb34b4c8 | 128 | temp = temp_code - pdata->default_temp_offset; |
9d97e5c8 DK |
129 | break; |
130 | } | |
131 | out: | |
132 | return temp; | |
133 | } | |
134 | ||
f22d9c03 | 135 | static int exynos_tmu_initialize(struct platform_device *pdev) |
9d97e5c8 | 136 | { |
f22d9c03 ADK |
137 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
138 | struct exynos_tmu_platform_data *pdata = data->pdata; | |
b8d582b9 | 139 | const struct exynos_tmu_registers *reg = pdata->registers; |
7ca04e58 | 140 | unsigned int status, trim_info = 0, con; |
4f0a6847 JL |
141 | unsigned int rising_threshold = 0, falling_threshold = 0; |
142 | int ret = 0, threshold_code, i, trigger_levs = 0; | |
9d97e5c8 DK |
143 | |
144 | mutex_lock(&data->lock); | |
145 | clk_enable(data->clk); | |
146 | ||
f4dae753 ADK |
147 | if (TMU_SUPPORTS(pdata, READY_STATUS)) { |
148 | status = readb(data->base + reg->tmu_status); | |
149 | if (!status) { | |
150 | ret = -EBUSY; | |
151 | goto out; | |
152 | } | |
9d97e5c8 DK |
153 | } |
154 | ||
f4dae753 | 155 | if (TMU_SUPPORTS(pdata, TRIM_RELOAD)) |
b8d582b9 ADK |
156 | __raw_writel(1, data->base + reg->triminfo_ctrl); |
157 | ||
9d97e5c8 | 158 | /* Save trimming info in order to perform calibration */ |
a0395eee ADK |
159 | if (data->soc == SOC_ARCH_EXYNOS5440) { |
160 | /* | |
161 | * For exynos5440 soc triminfo value is swapped between TMU0 and | |
162 | * TMU2, so the below logic is needed. | |
163 | */ | |
164 | switch (data->id) { | |
165 | case 0: | |
166 | trim_info = readl(data->base + | |
167 | EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data); | |
168 | break; | |
169 | case 1: | |
170 | trim_info = readl(data->base + reg->triminfo_data); | |
171 | break; | |
172 | case 2: | |
173 | trim_info = readl(data->base - | |
174 | EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data); | |
175 | } | |
176 | } else { | |
177 | trim_info = readl(data->base + reg->triminfo_data); | |
178 | } | |
b8d582b9 ADK |
179 | data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK; |
180 | data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) & | |
181 | EXYNOS_TMU_TEMP_MASK); | |
f22d9c03 | 182 | |
bb34b4c8 ADK |
183 | if ((pdata->min_efuse_value > data->temp_error1) || |
184 | (data->temp_error1 > pdata->max_efuse_value) || | |
f22d9c03 ADK |
185 | (data->temp_error2 != 0)) |
186 | data->temp_error1 = pdata->efuse_value; | |
187 | ||
7ca04e58 ADK |
188 | if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) { |
189 | dev_err(&pdev->dev, "Invalid max trigger level\n"); | |
190 | goto out; | |
191 | } | |
192 | ||
193 | for (i = 0; i < pdata->max_trigger_level; i++) { | |
194 | if (!pdata->trigger_levels[i]) | |
195 | continue; | |
196 | ||
197 | if ((pdata->trigger_type[i] == HW_TRIP) && | |
198 | (!pdata->trigger_levels[pdata->max_trigger_level - 1])) { | |
199 | dev_err(&pdev->dev, "Invalid hw trigger level\n"); | |
200 | ret = -EINVAL; | |
201 | goto out; | |
202 | } | |
203 | ||
204 | /* Count trigger levels except the HW trip*/ | |
205 | if (!(pdata->trigger_type[i] == HW_TRIP)) | |
4f0a6847 | 206 | trigger_levs++; |
7ca04e58 | 207 | } |
4f0a6847 | 208 | |
f22d9c03 ADK |
209 | if (data->soc == SOC_ARCH_EXYNOS4210) { |
210 | /* Write temperature code for threshold */ | |
211 | threshold_code = temp_to_code(data, pdata->threshold); | |
212 | if (threshold_code < 0) { | |
213 | ret = threshold_code; | |
214 | goto out; | |
215 | } | |
216 | writeb(threshold_code, | |
b8d582b9 | 217 | data->base + reg->threshold_temp); |
4f0a6847 | 218 | for (i = 0; i < trigger_levs; i++) |
b8d582b9 ADK |
219 | writeb(pdata->trigger_levels[i], data->base + |
220 | reg->threshold_th0 + i * sizeof(reg->threshold_th0)); | |
f22d9c03 | 221 | |
b8d582b9 | 222 | writel(reg->inten_rise_mask, data->base + reg->tmu_intclear); |
a0395eee | 223 | } else { |
4f0a6847 | 224 | /* Write temperature code for rising and falling threshold */ |
7ca04e58 ADK |
225 | for (i = 0; |
226 | i < trigger_levs && i < EXYNOS_MAX_TRIGGER_PER_REG; i++) { | |
4f0a6847 JL |
227 | threshold_code = temp_to_code(data, |
228 | pdata->trigger_levels[i]); | |
229 | if (threshold_code < 0) { | |
230 | ret = threshold_code; | |
231 | goto out; | |
232 | } | |
233 | rising_threshold |= threshold_code << 8 * i; | |
234 | if (pdata->threshold_falling) { | |
235 | threshold_code = temp_to_code(data, | |
236 | pdata->trigger_levels[i] - | |
237 | pdata->threshold_falling); | |
238 | if (threshold_code > 0) | |
239 | falling_threshold |= | |
240 | threshold_code << 8 * i; | |
241 | } | |
f22d9c03 | 242 | } |
f22d9c03 ADK |
243 | |
244 | writel(rising_threshold, | |
b8d582b9 | 245 | data->base + reg->threshold_th0); |
4f0a6847 | 246 | writel(falling_threshold, |
b8d582b9 | 247 | data->base + reg->threshold_th1); |
f22d9c03 | 248 | |
b8d582b9 ADK |
249 | writel((reg->inten_rise_mask << reg->inten_rise_shift) | |
250 | (reg->inten_fall_mask << reg->inten_fall_shift), | |
251 | data->base + reg->tmu_intclear); | |
7ca04e58 ADK |
252 | |
253 | /* if last threshold limit is also present */ | |
254 | i = pdata->max_trigger_level - 1; | |
255 | if (pdata->trigger_levels[i] && | |
256 | (pdata->trigger_type[i] == HW_TRIP)) { | |
257 | threshold_code = temp_to_code(data, | |
258 | pdata->trigger_levels[i]); | |
259 | if (threshold_code < 0) { | |
260 | ret = threshold_code; | |
261 | goto out; | |
262 | } | |
a0395eee ADK |
263 | if (i == EXYNOS_MAX_TRIGGER_PER_REG - 1) { |
264 | /* 1-4 level to be assigned in th0 reg */ | |
265 | rising_threshold |= threshold_code << 8 * i; | |
266 | writel(rising_threshold, | |
267 | data->base + reg->threshold_th0); | |
268 | } else if (i == EXYNOS_MAX_TRIGGER_PER_REG) { | |
269 | /* 5th level to be assigned in th2 reg */ | |
270 | rising_threshold = | |
271 | threshold_code << reg->threshold_th3_l0_shift; | |
272 | writel(rising_threshold, | |
273 | data->base + reg->threshold_th2); | |
274 | } | |
7ca04e58 ADK |
275 | con = readl(data->base + reg->tmu_ctrl); |
276 | con |= (1 << reg->therm_trip_en_shift); | |
277 | writel(con, data->base + reg->tmu_ctrl); | |
278 | } | |
9d97e5c8 | 279 | } |
a0395eee ADK |
280 | /*Clear the PMIN in the common TMU register*/ |
281 | if (reg->tmu_pmin && !data->id) | |
282 | writel(0, data->base_common + reg->tmu_pmin); | |
9d97e5c8 DK |
283 | out: |
284 | clk_disable(data->clk); | |
285 | mutex_unlock(&data->lock); | |
286 | ||
287 | return ret; | |
288 | } | |
289 | ||
f22d9c03 | 290 | static void exynos_tmu_control(struct platform_device *pdev, bool on) |
9d97e5c8 | 291 | { |
f22d9c03 ADK |
292 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
293 | struct exynos_tmu_platform_data *pdata = data->pdata; | |
b8d582b9 | 294 | const struct exynos_tmu_registers *reg = pdata->registers; |
9d97e5c8 DK |
295 | unsigned int con, interrupt_en; |
296 | ||
297 | mutex_lock(&data->lock); | |
298 | clk_enable(data->clk); | |
299 | ||
b8d582b9 | 300 | con = readl(data->base + reg->tmu_ctrl); |
f22d9c03 | 301 | |
d0a0ce3e | 302 | if (pdata->reference_voltage) { |
b8d582b9 ADK |
303 | con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift); |
304 | con |= pdata->reference_voltage << reg->buf_vref_sel_shift; | |
d0a0ce3e ADK |
305 | } |
306 | ||
307 | if (pdata->gain) { | |
b8d582b9 ADK |
308 | con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift); |
309 | con |= (pdata->gain << reg->buf_slope_sel_shift); | |
d0a0ce3e ADK |
310 | } |
311 | ||
312 | if (pdata->noise_cancel_mode) { | |
b8d582b9 ADK |
313 | con &= ~(reg->therm_trip_mode_mask << |
314 | reg->therm_trip_mode_shift); | |
315 | con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift); | |
f22d9c03 ADK |
316 | } |
317 | ||
9d97e5c8 | 318 | if (on) { |
b8d582b9 | 319 | con |= (1 << reg->core_en_shift); |
d0a0ce3e | 320 | interrupt_en = |
b8d582b9 ADK |
321 | pdata->trigger_enable[3] << reg->inten_rise3_shift | |
322 | pdata->trigger_enable[2] << reg->inten_rise2_shift | | |
323 | pdata->trigger_enable[1] << reg->inten_rise1_shift | | |
324 | pdata->trigger_enable[0] << reg->inten_rise0_shift; | |
f4dae753 | 325 | if (TMU_SUPPORTS(pdata, FALLING_TRIP)) |
d0a0ce3e | 326 | interrupt_en |= |
b8d582b9 | 327 | interrupt_en << reg->inten_fall0_shift; |
9d97e5c8 | 328 | } else { |
b8d582b9 | 329 | con &= ~(1 << reg->core_en_shift); |
9d97e5c8 DK |
330 | interrupt_en = 0; /* Disable all interrupts */ |
331 | } | |
b8d582b9 ADK |
332 | writel(interrupt_en, data->base + reg->tmu_inten); |
333 | writel(con, data->base + reg->tmu_ctrl); | |
9d97e5c8 DK |
334 | |
335 | clk_disable(data->clk); | |
336 | mutex_unlock(&data->lock); | |
337 | } | |
338 | ||
f22d9c03 | 339 | static int exynos_tmu_read(struct exynos_tmu_data *data) |
9d97e5c8 | 340 | { |
b8d582b9 ADK |
341 | struct exynos_tmu_platform_data *pdata = data->pdata; |
342 | const struct exynos_tmu_registers *reg = pdata->registers; | |
9d97e5c8 DK |
343 | u8 temp_code; |
344 | int temp; | |
345 | ||
346 | mutex_lock(&data->lock); | |
347 | clk_enable(data->clk); | |
348 | ||
b8d582b9 | 349 | temp_code = readb(data->base + reg->tmu_cur_temp); |
9d97e5c8 DK |
350 | temp = code_to_temp(data, temp_code); |
351 | ||
352 | clk_disable(data->clk); | |
353 | mutex_unlock(&data->lock); | |
354 | ||
355 | return temp; | |
356 | } | |
357 | ||
bffd1f8a ADK |
358 | #ifdef CONFIG_THERMAL_EMULATION |
359 | static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) | |
360 | { | |
361 | struct exynos_tmu_data *data = drv_data; | |
b8d582b9 ADK |
362 | struct exynos_tmu_platform_data *pdata = data->pdata; |
363 | const struct exynos_tmu_registers *reg = pdata->registers; | |
364 | unsigned int val; | |
bffd1f8a ADK |
365 | int ret = -EINVAL; |
366 | ||
f4dae753 | 367 | if (!TMU_SUPPORTS(pdata, EMULATION)) |
bffd1f8a ADK |
368 | goto out; |
369 | ||
370 | if (temp && temp < MCELSIUS) | |
371 | goto out; | |
372 | ||
373 | mutex_lock(&data->lock); | |
374 | clk_enable(data->clk); | |
375 | ||
b8d582b9 | 376 | val = readl(data->base + reg->emul_con); |
bffd1f8a ADK |
377 | |
378 | if (temp) { | |
379 | temp /= MCELSIUS; | |
380 | ||
f4dae753 ADK |
381 | if (TMU_SUPPORTS(pdata, EMUL_TIME)) { |
382 | val &= ~(EXYNOS_EMUL_TIME_MASK << reg->emul_time_shift); | |
383 | val |= (EXYNOS_EMUL_TIME << reg->emul_time_shift); | |
384 | } | |
385 | val &= ~(EXYNOS_EMUL_DATA_MASK << reg->emul_temp_shift); | |
386 | val |= (temp_to_code(data, temp) << reg->emul_temp_shift) | | |
387 | EXYNOS_EMUL_ENABLE; | |
bffd1f8a | 388 | } else { |
b8d582b9 | 389 | val &= ~EXYNOS_EMUL_ENABLE; |
bffd1f8a ADK |
390 | } |
391 | ||
b8d582b9 | 392 | writel(val, data->base + reg->emul_con); |
bffd1f8a ADK |
393 | |
394 | clk_disable(data->clk); | |
395 | mutex_unlock(&data->lock); | |
396 | return 0; | |
397 | out: | |
398 | return ret; | |
399 | } | |
400 | #else | |
401 | static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) | |
402 | { return -EINVAL; } | |
403 | #endif/*CONFIG_THERMAL_EMULATION*/ | |
404 | ||
f22d9c03 | 405 | static void exynos_tmu_work(struct work_struct *work) |
9d97e5c8 | 406 | { |
f22d9c03 ADK |
407 | struct exynos_tmu_data *data = container_of(work, |
408 | struct exynos_tmu_data, irq_work); | |
b8d582b9 ADK |
409 | struct exynos_tmu_platform_data *pdata = data->pdata; |
410 | const struct exynos_tmu_registers *reg = pdata->registers; | |
a0395eee ADK |
411 | unsigned int val_irq, val_type; |
412 | ||
413 | /* Find which sensor generated this interrupt */ | |
414 | if (reg->tmu_irqstatus) { | |
415 | val_type = readl(data->base_common + reg->tmu_irqstatus); | |
416 | if (!((val_type >> data->id) & 0x1)) | |
417 | goto out; | |
418 | } | |
9d97e5c8 | 419 | |
cebe7373 | 420 | exynos_report_trigger(data->reg_conf); |
9d97e5c8 DK |
421 | mutex_lock(&data->lock); |
422 | clk_enable(data->clk); | |
b8d582b9 | 423 | |
a4463c4f ADK |
424 | /* TODO: take action based on particular interrupt */ |
425 | val_irq = readl(data->base + reg->tmu_intstat); | |
426 | /* clear the interrupts */ | |
427 | writel(val_irq, data->base + reg->tmu_intclear); | |
b8d582b9 | 428 | |
9d97e5c8 DK |
429 | clk_disable(data->clk); |
430 | mutex_unlock(&data->lock); | |
a0395eee | 431 | out: |
f22d9c03 | 432 | enable_irq(data->irq); |
9d97e5c8 DK |
433 | } |
434 | ||
f22d9c03 | 435 | static irqreturn_t exynos_tmu_irq(int irq, void *id) |
9d97e5c8 | 436 | { |
f22d9c03 | 437 | struct exynos_tmu_data *data = id; |
9d97e5c8 DK |
438 | |
439 | disable_irq_nosync(irq); | |
440 | schedule_work(&data->irq_work); | |
441 | ||
442 | return IRQ_HANDLED; | |
443 | } | |
17be868e | 444 | |
17be868e ADK |
445 | #ifdef CONFIG_OF |
446 | static const struct of_device_id exynos_tmu_match[] = { | |
447 | { | |
448 | .compatible = "samsung,exynos4210-tmu", | |
449 | .data = (void *)EXYNOS4210_TMU_DRV_DATA, | |
450 | }, | |
b6cee53c SK |
451 | { |
452 | .compatible = "samsung,exynos4412-tmu", | |
e6b7991e | 453 | .data = (void *)EXYNOS5250_TMU_DRV_DATA, |
b6cee53c | 454 | }, |
17be868e ADK |
455 | { |
456 | .compatible = "samsung,exynos5250-tmu", | |
e6b7991e | 457 | .data = (void *)EXYNOS5250_TMU_DRV_DATA, |
17be868e ADK |
458 | }, |
459 | {}, | |
460 | }; | |
461 | MODULE_DEVICE_TABLE(of, exynos_tmu_match); | |
17be868e ADK |
462 | #endif |
463 | ||
17be868e | 464 | static inline struct exynos_tmu_platform_data *exynos_get_driver_data( |
cebe7373 | 465 | struct platform_device *pdev, int id) |
17be868e ADK |
466 | { |
467 | #ifdef CONFIG_OF | |
cebe7373 ADK |
468 | struct exynos_tmu_init_data *data_table; |
469 | struct exynos_tmu_platform_data *tmu_data; | |
17be868e ADK |
470 | if (pdev->dev.of_node) { |
471 | const struct of_device_id *match; | |
472 | match = of_match_node(exynos_tmu_match, pdev->dev.of_node); | |
473 | if (!match) | |
474 | return NULL; | |
cebe7373 ADK |
475 | data_table = (struct exynos_tmu_init_data *) match->data; |
476 | if (!data_table || id >= data_table->tmu_count) | |
477 | return NULL; | |
478 | tmu_data = data_table->tmu_data; | |
479 | return (struct exynos_tmu_platform_data *) (tmu_data + id); | |
17be868e ADK |
480 | } |
481 | #endif | |
1cd1ecb6 | 482 | return NULL; |
7e0b55e6 | 483 | } |
bbf63be4 | 484 | |
cebe7373 | 485 | static int exynos_map_dt_data(struct platform_device *pdev) |
9d97e5c8 | 486 | { |
cebe7373 ADK |
487 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
488 | struct exynos_tmu_platform_data *pdata; | |
489 | struct resource res; | |
490 | ||
491 | if (!data) | |
492 | return -ENODEV; | |
9d97e5c8 | 493 | |
cebe7373 ADK |
494 | data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); |
495 | if (data->id < 0) | |
496 | data->id = 0; | |
17be868e | 497 | |
cebe7373 ADK |
498 | data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); |
499 | if (data->irq <= 0) { | |
500 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
501 | return -ENODEV; | |
502 | } | |
503 | ||
504 | if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { | |
505 | dev_err(&pdev->dev, "failed to get Resource 0\n"); | |
506 | return -ENODEV; | |
507 | } | |
508 | ||
509 | data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); | |
510 | if (!data->base) { | |
511 | dev_err(&pdev->dev, "Failed to ioremap memory\n"); | |
512 | return -EADDRNOTAVAIL; | |
513 | } | |
514 | ||
515 | pdata = exynos_get_driver_data(pdev, data->id); | |
9d97e5c8 DK |
516 | if (!pdata) { |
517 | dev_err(&pdev->dev, "No platform init data supplied.\n"); | |
518 | return -ENODEV; | |
519 | } | |
cebe7373 | 520 | data->pdata = pdata; |
d9b6ee14 ADK |
521 | /* |
522 | * Check if the TMU shares some registers and then try to map the | |
523 | * memory of common registers. | |
524 | */ | |
525 | if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) | |
526 | return 0; | |
527 | ||
528 | if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { | |
529 | dev_err(&pdev->dev, "failed to get Resource 1\n"); | |
530 | return -ENODEV; | |
531 | } | |
532 | ||
533 | data->base_common = devm_ioremap(&pdev->dev, res.start, | |
534 | resource_size(&res)); | |
535 | if (!data->base) { | |
536 | dev_err(&pdev->dev, "Failed to ioremap memory\n"); | |
537 | return -ENOMEM; | |
538 | } | |
cebe7373 ADK |
539 | |
540 | return 0; | |
541 | } | |
542 | ||
543 | static int exynos_tmu_probe(struct platform_device *pdev) | |
544 | { | |
545 | struct exynos_tmu_data *data; | |
546 | struct exynos_tmu_platform_data *pdata; | |
547 | struct thermal_sensor_conf *sensor_conf; | |
548 | int ret, i; | |
549 | ||
79e093c3 ADK |
550 | data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), |
551 | GFP_KERNEL); | |
9d97e5c8 DK |
552 | if (!data) { |
553 | dev_err(&pdev->dev, "Failed to allocate driver structure\n"); | |
554 | return -ENOMEM; | |
555 | } | |
556 | ||
cebe7373 ADK |
557 | platform_set_drvdata(pdev, data); |
558 | mutex_init(&data->lock); | |
9d97e5c8 | 559 | |
cebe7373 ADK |
560 | ret = exynos_map_dt_data(pdev); |
561 | if (ret) | |
562 | return ret; | |
9d97e5c8 | 563 | |
cebe7373 | 564 | pdata = data->pdata; |
9d97e5c8 | 565 | |
cebe7373 | 566 | INIT_WORK(&data->irq_work, exynos_tmu_work); |
9d97e5c8 | 567 | |
2a16279c | 568 | data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); |
9d97e5c8 | 569 | if (IS_ERR(data->clk)) { |
9d97e5c8 | 570 | dev_err(&pdev->dev, "Failed to get clock\n"); |
79e093c3 | 571 | return PTR_ERR(data->clk); |
9d97e5c8 DK |
572 | } |
573 | ||
2a16279c SK |
574 | ret = clk_prepare(data->clk); |
575 | if (ret) | |
576 | return ret; | |
577 | ||
f22d9c03 | 578 | if (pdata->type == SOC_ARCH_EXYNOS || |
a0395eee ADK |
579 | pdata->type == SOC_ARCH_EXYNOS4210 || |
580 | pdata->type == SOC_ARCH_EXYNOS5440) | |
f22d9c03 ADK |
581 | data->soc = pdata->type; |
582 | else { | |
583 | ret = -EINVAL; | |
584 | dev_err(&pdev->dev, "Platform not supported\n"); | |
585 | goto err_clk; | |
586 | } | |
587 | ||
f22d9c03 | 588 | ret = exynos_tmu_initialize(pdev); |
9d97e5c8 DK |
589 | if (ret) { |
590 | dev_err(&pdev->dev, "Failed to initialize TMU\n"); | |
591 | goto err_clk; | |
592 | } | |
593 | ||
f22d9c03 | 594 | exynos_tmu_control(pdev, true); |
9d97e5c8 | 595 | |
cebe7373 ADK |
596 | /* Allocate a structure to register with the exynos core thermal */ |
597 | sensor_conf = devm_kzalloc(&pdev->dev, | |
598 | sizeof(struct thermal_sensor_conf), GFP_KERNEL); | |
599 | if (!sensor_conf) { | |
600 | dev_err(&pdev->dev, "Failed to allocate registration struct\n"); | |
601 | ret = -ENOMEM; | |
602 | goto err_clk; | |
603 | } | |
604 | sprintf(sensor_conf->name, "therm_zone%d", data->id); | |
605 | sensor_conf->read_temperature = (int (*)(void *))exynos_tmu_read; | |
606 | sensor_conf->write_emul_temp = | |
607 | (int (*)(void *, unsigned long))exynos_tmu_set_emulation; | |
608 | sensor_conf->driver_data = data; | |
609 | sensor_conf->trip_data.trip_count = pdata->trigger_enable[0] + | |
bb34b4c8 ADK |
610 | pdata->trigger_enable[1] + pdata->trigger_enable[2]+ |
611 | pdata->trigger_enable[3]; | |
7e0b55e6 | 612 | |
cebe7373 ADK |
613 | for (i = 0; i < sensor_conf->trip_data.trip_count; i++) { |
614 | sensor_conf->trip_data.trip_val[i] = | |
7e0b55e6 | 615 | pdata->threshold + pdata->trigger_levels[i]; |
cebe7373 | 616 | sensor_conf->trip_data.trip_type[i] = |
5c3cf552 ADK |
617 | pdata->trigger_type[i]; |
618 | } | |
7e0b55e6 | 619 | |
cebe7373 | 620 | sensor_conf->trip_data.trigger_falling = pdata->threshold_falling; |
4f0a6847 | 621 | |
cebe7373 | 622 | sensor_conf->cooling_data.freq_clip_count = pdata->freq_tab_count; |
7e0b55e6 | 623 | for (i = 0; i < pdata->freq_tab_count; i++) { |
cebe7373 | 624 | sensor_conf->cooling_data.freq_data[i].freq_clip_max = |
7e0b55e6 | 625 | pdata->freq_tab[i].freq_clip_max; |
cebe7373 | 626 | sensor_conf->cooling_data.freq_data[i].temp_level = |
7e0b55e6 ADK |
627 | pdata->freq_tab[i].temp_level; |
628 | } | |
cebe7373 ADK |
629 | sensor_conf->dev = &pdev->dev; |
630 | /* Register the sensor with thermal management interface */ | |
631 | ret = exynos_register_thermal(sensor_conf); | |
7e0b55e6 ADK |
632 | if (ret) { |
633 | dev_err(&pdev->dev, "Failed to register thermal interface\n"); | |
634 | goto err_clk; | |
635 | } | |
cebe7373 ADK |
636 | data->reg_conf = sensor_conf; |
637 | ||
638 | ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, | |
639 | IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); | |
640 | if (ret) { | |
641 | dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); | |
642 | goto err_clk; | |
643 | } | |
bbf63be4 | 644 | |
9d97e5c8 | 645 | return 0; |
9d97e5c8 | 646 | err_clk: |
2a16279c | 647 | clk_unprepare(data->clk); |
9d97e5c8 DK |
648 | return ret; |
649 | } | |
650 | ||
4eab7a9e | 651 | static int exynos_tmu_remove(struct platform_device *pdev) |
9d97e5c8 | 652 | { |
f22d9c03 | 653 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
9d97e5c8 | 654 | |
f22d9c03 | 655 | exynos_tmu_control(pdev, false); |
9d97e5c8 | 656 | |
cebe7373 | 657 | exynos_unregister_thermal(data->reg_conf); |
7e0b55e6 | 658 | |
2a16279c | 659 | clk_unprepare(data->clk); |
9d97e5c8 | 660 | |
9d97e5c8 DK |
661 | return 0; |
662 | } | |
663 | ||
08cd6753 | 664 | #ifdef CONFIG_PM_SLEEP |
f22d9c03 | 665 | static int exynos_tmu_suspend(struct device *dev) |
9d97e5c8 | 666 | { |
f22d9c03 | 667 | exynos_tmu_control(to_platform_device(dev), false); |
9d97e5c8 DK |
668 | |
669 | return 0; | |
670 | } | |
671 | ||
f22d9c03 | 672 | static int exynos_tmu_resume(struct device *dev) |
9d97e5c8 | 673 | { |
08cd6753 RW |
674 | struct platform_device *pdev = to_platform_device(dev); |
675 | ||
f22d9c03 ADK |
676 | exynos_tmu_initialize(pdev); |
677 | exynos_tmu_control(pdev, true); | |
9d97e5c8 DK |
678 | |
679 | return 0; | |
680 | } | |
08cd6753 | 681 | |
f22d9c03 ADK |
682 | static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, |
683 | exynos_tmu_suspend, exynos_tmu_resume); | |
684 | #define EXYNOS_TMU_PM (&exynos_tmu_pm) | |
9d97e5c8 | 685 | #else |
f22d9c03 | 686 | #define EXYNOS_TMU_PM NULL |
9d97e5c8 DK |
687 | #endif |
688 | ||
f22d9c03 | 689 | static struct platform_driver exynos_tmu_driver = { |
9d97e5c8 | 690 | .driver = { |
f22d9c03 | 691 | .name = "exynos-tmu", |
9d97e5c8 | 692 | .owner = THIS_MODULE, |
f22d9c03 | 693 | .pm = EXYNOS_TMU_PM, |
caa5cbd5 | 694 | .of_match_table = of_match_ptr(exynos_tmu_match), |
9d97e5c8 | 695 | }, |
f22d9c03 | 696 | .probe = exynos_tmu_probe, |
4eab7a9e | 697 | .remove = exynos_tmu_remove, |
9d97e5c8 DK |
698 | }; |
699 | ||
f22d9c03 | 700 | module_platform_driver(exynos_tmu_driver); |
9d97e5c8 | 701 | |
f22d9c03 | 702 | MODULE_DESCRIPTION("EXYNOS TMU Driver"); |
9d97e5c8 DK |
703 | MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); |
704 | MODULE_LICENSE("GPL"); | |
f22d9c03 | 705 | MODULE_ALIAS("platform:exynos-tmu"); |