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Commit | Line | Data |
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9d97e5c8 | 1 | /* |
59dfa54c | 2 | * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) |
9d97e5c8 DK |
3 | * |
4 | * Copyright (C) 2011 Samsung Electronics | |
5 | * Donggeun Kim <dg77.kim@samsung.com> | |
c48cbba6 | 6 | * Amit Daniel Kachhap <amit.kachhap@linaro.org> |
9d97e5c8 DK |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
9d97e5c8 | 24 | #include <linux/clk.h> |
9d97e5c8 | 25 | #include <linux/io.h> |
1b678641 ADK |
26 | #include <linux/interrupt.h> |
27 | #include <linux/module.h> | |
f22d9c03 | 28 | #include <linux/of.h> |
cebe7373 ADK |
29 | #include <linux/of_address.h> |
30 | #include <linux/of_irq.h> | |
1b678641 | 31 | #include <linux/platform_device.h> |
1b678641 ADK |
32 | |
33 | #include "exynos_thermal_common.h" | |
0c1836a6 | 34 | #include "exynos_tmu.h" |
e6b7991e | 35 | #include "exynos_tmu_data.h" |
f22d9c03 | 36 | |
cebe7373 ADK |
37 | /** |
38 | * struct exynos_tmu_data : A structure to hold the private data of the TMU | |
39 | driver | |
40 | * @id: identifier of the one instance of the TMU controller. | |
41 | * @pdata: pointer to the tmu platform/configuration data | |
42 | * @base: base address of the single instance of the TMU controller. | |
43 | * @irq: irq number of the TMU controller. | |
44 | * @soc: id of the SOC type. | |
45 | * @irq_work: pointer to the irq work structure. | |
46 | * @lock: lock to implement synchronization. | |
47 | * @clk: pointer to the clock structure. | |
48 | * @temp_error1: fused value of the first point trim. | |
49 | * @temp_error2: fused value of the second point trim. | |
50 | * @reg_conf: pointer to structure to register with core thermal. | |
51 | */ | |
f22d9c03 | 52 | struct exynos_tmu_data { |
cebe7373 | 53 | int id; |
f22d9c03 | 54 | struct exynos_tmu_platform_data *pdata; |
9d97e5c8 DK |
55 | void __iomem *base; |
56 | int irq; | |
f22d9c03 | 57 | enum soc_type soc; |
9d97e5c8 DK |
58 | struct work_struct irq_work; |
59 | struct mutex lock; | |
60 | struct clk *clk; | |
61 | u8 temp_error1, temp_error2; | |
cebe7373 | 62 | struct thermal_sensor_conf *reg_conf; |
9d97e5c8 DK |
63 | }; |
64 | ||
65 | /* | |
66 | * TMU treats temperature as a mapped temperature code. | |
67 | * The temperature is converted differently depending on the calibration type. | |
68 | */ | |
f22d9c03 | 69 | static int temp_to_code(struct exynos_tmu_data *data, u8 temp) |
9d97e5c8 | 70 | { |
f22d9c03 | 71 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 DK |
72 | int temp_code; |
73 | ||
f22d9c03 ADK |
74 | if (data->soc == SOC_ARCH_EXYNOS4210) |
75 | /* temp should range between 25 and 125 */ | |
76 | if (temp < 25 || temp > 125) { | |
77 | temp_code = -EINVAL; | |
78 | goto out; | |
79 | } | |
9d97e5c8 DK |
80 | |
81 | switch (pdata->cal_type) { | |
82 | case TYPE_TWO_POINT_TRIMMING: | |
bb34b4c8 ADK |
83 | temp_code = (temp - pdata->first_point_trim) * |
84 | (data->temp_error2 - data->temp_error1) / | |
85 | (pdata->second_point_trim - pdata->first_point_trim) + | |
86 | data->temp_error1; | |
9d97e5c8 DK |
87 | break; |
88 | case TYPE_ONE_POINT_TRIMMING: | |
bb34b4c8 | 89 | temp_code = temp + data->temp_error1 - pdata->first_point_trim; |
9d97e5c8 DK |
90 | break; |
91 | default: | |
bb34b4c8 | 92 | temp_code = temp + pdata->default_temp_offset; |
9d97e5c8 DK |
93 | break; |
94 | } | |
95 | out: | |
96 | return temp_code; | |
97 | } | |
98 | ||
99 | /* | |
100 | * Calculate a temperature value from a temperature code. | |
101 | * The unit of the temperature is degree Celsius. | |
102 | */ | |
f22d9c03 | 103 | static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code) |
9d97e5c8 | 104 | { |
f22d9c03 | 105 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 DK |
106 | int temp; |
107 | ||
f22d9c03 ADK |
108 | if (data->soc == SOC_ARCH_EXYNOS4210) |
109 | /* temp_code should range between 75 and 175 */ | |
110 | if (temp_code < 75 || temp_code > 175) { | |
111 | temp = -ENODATA; | |
112 | goto out; | |
113 | } | |
9d97e5c8 DK |
114 | |
115 | switch (pdata->cal_type) { | |
116 | case TYPE_TWO_POINT_TRIMMING: | |
bb34b4c8 ADK |
117 | temp = (temp_code - data->temp_error1) * |
118 | (pdata->second_point_trim - pdata->first_point_trim) / | |
119 | (data->temp_error2 - data->temp_error1) + | |
120 | pdata->first_point_trim; | |
9d97e5c8 DK |
121 | break; |
122 | case TYPE_ONE_POINT_TRIMMING: | |
bb34b4c8 | 123 | temp = temp_code - data->temp_error1 + pdata->first_point_trim; |
9d97e5c8 DK |
124 | break; |
125 | default: | |
bb34b4c8 | 126 | temp = temp_code - pdata->default_temp_offset; |
9d97e5c8 DK |
127 | break; |
128 | } | |
129 | out: | |
130 | return temp; | |
131 | } | |
132 | ||
f22d9c03 | 133 | static int exynos_tmu_initialize(struct platform_device *pdev) |
9d97e5c8 | 134 | { |
f22d9c03 ADK |
135 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
136 | struct exynos_tmu_platform_data *pdata = data->pdata; | |
b8d582b9 | 137 | const struct exynos_tmu_registers *reg = pdata->registers; |
7ca04e58 | 138 | unsigned int status, trim_info = 0, con; |
4f0a6847 JL |
139 | unsigned int rising_threshold = 0, falling_threshold = 0; |
140 | int ret = 0, threshold_code, i, trigger_levs = 0; | |
9d97e5c8 DK |
141 | |
142 | mutex_lock(&data->lock); | |
143 | clk_enable(data->clk); | |
144 | ||
f4dae753 ADK |
145 | if (TMU_SUPPORTS(pdata, READY_STATUS)) { |
146 | status = readb(data->base + reg->tmu_status); | |
147 | if (!status) { | |
148 | ret = -EBUSY; | |
149 | goto out; | |
150 | } | |
9d97e5c8 DK |
151 | } |
152 | ||
f4dae753 | 153 | if (TMU_SUPPORTS(pdata, TRIM_RELOAD)) |
b8d582b9 ADK |
154 | __raw_writel(1, data->base + reg->triminfo_ctrl); |
155 | ||
9d97e5c8 | 156 | /* Save trimming info in order to perform calibration */ |
b8d582b9 ADK |
157 | trim_info = readl(data->base + reg->triminfo_data); |
158 | data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK; | |
159 | data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) & | |
160 | EXYNOS_TMU_TEMP_MASK); | |
f22d9c03 | 161 | |
bb34b4c8 ADK |
162 | if ((pdata->min_efuse_value > data->temp_error1) || |
163 | (data->temp_error1 > pdata->max_efuse_value) || | |
f22d9c03 ADK |
164 | (data->temp_error2 != 0)) |
165 | data->temp_error1 = pdata->efuse_value; | |
166 | ||
7ca04e58 ADK |
167 | if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) { |
168 | dev_err(&pdev->dev, "Invalid max trigger level\n"); | |
169 | goto out; | |
170 | } | |
171 | ||
172 | for (i = 0; i < pdata->max_trigger_level; i++) { | |
173 | if (!pdata->trigger_levels[i]) | |
174 | continue; | |
175 | ||
176 | if ((pdata->trigger_type[i] == HW_TRIP) && | |
177 | (!pdata->trigger_levels[pdata->max_trigger_level - 1])) { | |
178 | dev_err(&pdev->dev, "Invalid hw trigger level\n"); | |
179 | ret = -EINVAL; | |
180 | goto out; | |
181 | } | |
182 | ||
183 | /* Count trigger levels except the HW trip*/ | |
184 | if (!(pdata->trigger_type[i] == HW_TRIP)) | |
4f0a6847 | 185 | trigger_levs++; |
7ca04e58 | 186 | } |
4f0a6847 | 187 | |
f22d9c03 ADK |
188 | if (data->soc == SOC_ARCH_EXYNOS4210) { |
189 | /* Write temperature code for threshold */ | |
190 | threshold_code = temp_to_code(data, pdata->threshold); | |
191 | if (threshold_code < 0) { | |
192 | ret = threshold_code; | |
193 | goto out; | |
194 | } | |
195 | writeb(threshold_code, | |
b8d582b9 | 196 | data->base + reg->threshold_temp); |
4f0a6847 | 197 | for (i = 0; i < trigger_levs; i++) |
b8d582b9 ADK |
198 | writeb(pdata->trigger_levels[i], data->base + |
199 | reg->threshold_th0 + i * sizeof(reg->threshold_th0)); | |
f22d9c03 | 200 | |
b8d582b9 | 201 | writel(reg->inten_rise_mask, data->base + reg->tmu_intclear); |
f22d9c03 | 202 | } else if (data->soc == SOC_ARCH_EXYNOS) { |
4f0a6847 | 203 | /* Write temperature code for rising and falling threshold */ |
7ca04e58 ADK |
204 | for (i = 0; |
205 | i < trigger_levs && i < EXYNOS_MAX_TRIGGER_PER_REG; i++) { | |
4f0a6847 JL |
206 | threshold_code = temp_to_code(data, |
207 | pdata->trigger_levels[i]); | |
208 | if (threshold_code < 0) { | |
209 | ret = threshold_code; | |
210 | goto out; | |
211 | } | |
212 | rising_threshold |= threshold_code << 8 * i; | |
213 | if (pdata->threshold_falling) { | |
214 | threshold_code = temp_to_code(data, | |
215 | pdata->trigger_levels[i] - | |
216 | pdata->threshold_falling); | |
217 | if (threshold_code > 0) | |
218 | falling_threshold |= | |
219 | threshold_code << 8 * i; | |
220 | } | |
f22d9c03 | 221 | } |
f22d9c03 ADK |
222 | |
223 | writel(rising_threshold, | |
b8d582b9 | 224 | data->base + reg->threshold_th0); |
4f0a6847 | 225 | writel(falling_threshold, |
b8d582b9 | 226 | data->base + reg->threshold_th1); |
f22d9c03 | 227 | |
b8d582b9 ADK |
228 | writel((reg->inten_rise_mask << reg->inten_rise_shift) | |
229 | (reg->inten_fall_mask << reg->inten_fall_shift), | |
230 | data->base + reg->tmu_intclear); | |
7ca04e58 ADK |
231 | |
232 | /* if last threshold limit is also present */ | |
233 | i = pdata->max_trigger_level - 1; | |
234 | if (pdata->trigger_levels[i] && | |
235 | (pdata->trigger_type[i] == HW_TRIP)) { | |
236 | threshold_code = temp_to_code(data, | |
237 | pdata->trigger_levels[i]); | |
238 | if (threshold_code < 0) { | |
239 | ret = threshold_code; | |
240 | goto out; | |
241 | } | |
242 | rising_threshold |= threshold_code << 8 * i; | |
243 | writel(rising_threshold, | |
244 | data->base + reg->threshold_th0); | |
245 | con = readl(data->base + reg->tmu_ctrl); | |
246 | con |= (1 << reg->therm_trip_en_shift); | |
247 | writel(con, data->base + reg->tmu_ctrl); | |
248 | } | |
9d97e5c8 | 249 | } |
9d97e5c8 DK |
250 | out: |
251 | clk_disable(data->clk); | |
252 | mutex_unlock(&data->lock); | |
253 | ||
254 | return ret; | |
255 | } | |
256 | ||
f22d9c03 | 257 | static void exynos_tmu_control(struct platform_device *pdev, bool on) |
9d97e5c8 | 258 | { |
f22d9c03 ADK |
259 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
260 | struct exynos_tmu_platform_data *pdata = data->pdata; | |
b8d582b9 | 261 | const struct exynos_tmu_registers *reg = pdata->registers; |
9d97e5c8 DK |
262 | unsigned int con, interrupt_en; |
263 | ||
264 | mutex_lock(&data->lock); | |
265 | clk_enable(data->clk); | |
266 | ||
b8d582b9 | 267 | con = readl(data->base + reg->tmu_ctrl); |
f22d9c03 | 268 | |
d0a0ce3e | 269 | if (pdata->reference_voltage) { |
b8d582b9 ADK |
270 | con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift); |
271 | con |= pdata->reference_voltage << reg->buf_vref_sel_shift; | |
d0a0ce3e ADK |
272 | } |
273 | ||
274 | if (pdata->gain) { | |
b8d582b9 ADK |
275 | con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift); |
276 | con |= (pdata->gain << reg->buf_slope_sel_shift); | |
d0a0ce3e ADK |
277 | } |
278 | ||
279 | if (pdata->noise_cancel_mode) { | |
b8d582b9 ADK |
280 | con &= ~(reg->therm_trip_mode_mask << |
281 | reg->therm_trip_mode_shift); | |
282 | con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift); | |
f22d9c03 ADK |
283 | } |
284 | ||
9d97e5c8 | 285 | if (on) { |
b8d582b9 | 286 | con |= (1 << reg->core_en_shift); |
d0a0ce3e | 287 | interrupt_en = |
b8d582b9 ADK |
288 | pdata->trigger_enable[3] << reg->inten_rise3_shift | |
289 | pdata->trigger_enable[2] << reg->inten_rise2_shift | | |
290 | pdata->trigger_enable[1] << reg->inten_rise1_shift | | |
291 | pdata->trigger_enable[0] << reg->inten_rise0_shift; | |
f4dae753 | 292 | if (TMU_SUPPORTS(pdata, FALLING_TRIP)) |
d0a0ce3e | 293 | interrupt_en |= |
b8d582b9 | 294 | interrupt_en << reg->inten_fall0_shift; |
9d97e5c8 | 295 | } else { |
b8d582b9 | 296 | con &= ~(1 << reg->core_en_shift); |
9d97e5c8 DK |
297 | interrupt_en = 0; /* Disable all interrupts */ |
298 | } | |
b8d582b9 ADK |
299 | writel(interrupt_en, data->base + reg->tmu_inten); |
300 | writel(con, data->base + reg->tmu_ctrl); | |
9d97e5c8 DK |
301 | |
302 | clk_disable(data->clk); | |
303 | mutex_unlock(&data->lock); | |
304 | } | |
305 | ||
f22d9c03 | 306 | static int exynos_tmu_read(struct exynos_tmu_data *data) |
9d97e5c8 | 307 | { |
b8d582b9 ADK |
308 | struct exynos_tmu_platform_data *pdata = data->pdata; |
309 | const struct exynos_tmu_registers *reg = pdata->registers; | |
9d97e5c8 DK |
310 | u8 temp_code; |
311 | int temp; | |
312 | ||
313 | mutex_lock(&data->lock); | |
314 | clk_enable(data->clk); | |
315 | ||
b8d582b9 | 316 | temp_code = readb(data->base + reg->tmu_cur_temp); |
9d97e5c8 DK |
317 | temp = code_to_temp(data, temp_code); |
318 | ||
319 | clk_disable(data->clk); | |
320 | mutex_unlock(&data->lock); | |
321 | ||
322 | return temp; | |
323 | } | |
324 | ||
bffd1f8a ADK |
325 | #ifdef CONFIG_THERMAL_EMULATION |
326 | static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) | |
327 | { | |
328 | struct exynos_tmu_data *data = drv_data; | |
b8d582b9 ADK |
329 | struct exynos_tmu_platform_data *pdata = data->pdata; |
330 | const struct exynos_tmu_registers *reg = pdata->registers; | |
331 | unsigned int val; | |
bffd1f8a ADK |
332 | int ret = -EINVAL; |
333 | ||
f4dae753 | 334 | if (!TMU_SUPPORTS(pdata, EMULATION)) |
bffd1f8a ADK |
335 | goto out; |
336 | ||
337 | if (temp && temp < MCELSIUS) | |
338 | goto out; | |
339 | ||
340 | mutex_lock(&data->lock); | |
341 | clk_enable(data->clk); | |
342 | ||
b8d582b9 | 343 | val = readl(data->base + reg->emul_con); |
bffd1f8a ADK |
344 | |
345 | if (temp) { | |
346 | temp /= MCELSIUS; | |
347 | ||
f4dae753 ADK |
348 | if (TMU_SUPPORTS(pdata, EMUL_TIME)) { |
349 | val &= ~(EXYNOS_EMUL_TIME_MASK << reg->emul_time_shift); | |
350 | val |= (EXYNOS_EMUL_TIME << reg->emul_time_shift); | |
351 | } | |
352 | val &= ~(EXYNOS_EMUL_DATA_MASK << reg->emul_temp_shift); | |
353 | val |= (temp_to_code(data, temp) << reg->emul_temp_shift) | | |
354 | EXYNOS_EMUL_ENABLE; | |
bffd1f8a | 355 | } else { |
b8d582b9 | 356 | val &= ~EXYNOS_EMUL_ENABLE; |
bffd1f8a ADK |
357 | } |
358 | ||
b8d582b9 | 359 | writel(val, data->base + reg->emul_con); |
bffd1f8a ADK |
360 | |
361 | clk_disable(data->clk); | |
362 | mutex_unlock(&data->lock); | |
363 | return 0; | |
364 | out: | |
365 | return ret; | |
366 | } | |
367 | #else | |
368 | static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) | |
369 | { return -EINVAL; } | |
370 | #endif/*CONFIG_THERMAL_EMULATION*/ | |
371 | ||
f22d9c03 | 372 | static void exynos_tmu_work(struct work_struct *work) |
9d97e5c8 | 373 | { |
f22d9c03 ADK |
374 | struct exynos_tmu_data *data = container_of(work, |
375 | struct exynos_tmu_data, irq_work); | |
b8d582b9 ADK |
376 | struct exynos_tmu_platform_data *pdata = data->pdata; |
377 | const struct exynos_tmu_registers *reg = pdata->registers; | |
a4463c4f | 378 | unsigned int val_irq; |
9d97e5c8 | 379 | |
cebe7373 | 380 | exynos_report_trigger(data->reg_conf); |
9d97e5c8 DK |
381 | mutex_lock(&data->lock); |
382 | clk_enable(data->clk); | |
b8d582b9 | 383 | |
a4463c4f ADK |
384 | /* TODO: take action based on particular interrupt */ |
385 | val_irq = readl(data->base + reg->tmu_intstat); | |
386 | /* clear the interrupts */ | |
387 | writel(val_irq, data->base + reg->tmu_intclear); | |
b8d582b9 | 388 | |
9d97e5c8 DK |
389 | clk_disable(data->clk); |
390 | mutex_unlock(&data->lock); | |
3ad9524a | 391 | |
f22d9c03 | 392 | enable_irq(data->irq); |
9d97e5c8 DK |
393 | } |
394 | ||
f22d9c03 | 395 | static irqreturn_t exynos_tmu_irq(int irq, void *id) |
9d97e5c8 | 396 | { |
f22d9c03 | 397 | struct exynos_tmu_data *data = id; |
9d97e5c8 DK |
398 | |
399 | disable_irq_nosync(irq); | |
400 | schedule_work(&data->irq_work); | |
401 | ||
402 | return IRQ_HANDLED; | |
403 | } | |
17be868e | 404 | |
17be868e ADK |
405 | #ifdef CONFIG_OF |
406 | static const struct of_device_id exynos_tmu_match[] = { | |
407 | { | |
408 | .compatible = "samsung,exynos4210-tmu", | |
409 | .data = (void *)EXYNOS4210_TMU_DRV_DATA, | |
410 | }, | |
b6cee53c SK |
411 | { |
412 | .compatible = "samsung,exynos4412-tmu", | |
e6b7991e | 413 | .data = (void *)EXYNOS5250_TMU_DRV_DATA, |
b6cee53c | 414 | }, |
17be868e ADK |
415 | { |
416 | .compatible = "samsung,exynos5250-tmu", | |
e6b7991e | 417 | .data = (void *)EXYNOS5250_TMU_DRV_DATA, |
17be868e ADK |
418 | }, |
419 | {}, | |
420 | }; | |
421 | MODULE_DEVICE_TABLE(of, exynos_tmu_match); | |
17be868e ADK |
422 | #endif |
423 | ||
17be868e | 424 | static inline struct exynos_tmu_platform_data *exynos_get_driver_data( |
cebe7373 | 425 | struct platform_device *pdev, int id) |
17be868e ADK |
426 | { |
427 | #ifdef CONFIG_OF | |
cebe7373 ADK |
428 | struct exynos_tmu_init_data *data_table; |
429 | struct exynos_tmu_platform_data *tmu_data; | |
17be868e ADK |
430 | if (pdev->dev.of_node) { |
431 | const struct of_device_id *match; | |
432 | match = of_match_node(exynos_tmu_match, pdev->dev.of_node); | |
433 | if (!match) | |
434 | return NULL; | |
cebe7373 ADK |
435 | data_table = (struct exynos_tmu_init_data *) match->data; |
436 | if (!data_table || id >= data_table->tmu_count) | |
437 | return NULL; | |
438 | tmu_data = data_table->tmu_data; | |
439 | return (struct exynos_tmu_platform_data *) (tmu_data + id); | |
17be868e ADK |
440 | } |
441 | #endif | |
1cd1ecb6 | 442 | return NULL; |
7e0b55e6 | 443 | } |
bbf63be4 | 444 | |
cebe7373 | 445 | static int exynos_map_dt_data(struct platform_device *pdev) |
9d97e5c8 | 446 | { |
cebe7373 ADK |
447 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
448 | struct exynos_tmu_platform_data *pdata; | |
449 | struct resource res; | |
450 | ||
451 | if (!data) | |
452 | return -ENODEV; | |
9d97e5c8 | 453 | |
cebe7373 ADK |
454 | data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); |
455 | if (data->id < 0) | |
456 | data->id = 0; | |
17be868e | 457 | |
cebe7373 ADK |
458 | data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); |
459 | if (data->irq <= 0) { | |
460 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
461 | return -ENODEV; | |
462 | } | |
463 | ||
464 | if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { | |
465 | dev_err(&pdev->dev, "failed to get Resource 0\n"); | |
466 | return -ENODEV; | |
467 | } | |
468 | ||
469 | data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); | |
470 | if (!data->base) { | |
471 | dev_err(&pdev->dev, "Failed to ioremap memory\n"); | |
472 | return -EADDRNOTAVAIL; | |
473 | } | |
474 | ||
475 | pdata = exynos_get_driver_data(pdev, data->id); | |
9d97e5c8 DK |
476 | if (!pdata) { |
477 | dev_err(&pdev->dev, "No platform init data supplied.\n"); | |
478 | return -ENODEV; | |
479 | } | |
cebe7373 ADK |
480 | data->pdata = pdata; |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static int exynos_tmu_probe(struct platform_device *pdev) | |
486 | { | |
487 | struct exynos_tmu_data *data; | |
488 | struct exynos_tmu_platform_data *pdata; | |
489 | struct thermal_sensor_conf *sensor_conf; | |
490 | int ret, i; | |
491 | ||
79e093c3 ADK |
492 | data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), |
493 | GFP_KERNEL); | |
9d97e5c8 DK |
494 | if (!data) { |
495 | dev_err(&pdev->dev, "Failed to allocate driver structure\n"); | |
496 | return -ENOMEM; | |
497 | } | |
498 | ||
cebe7373 ADK |
499 | platform_set_drvdata(pdev, data); |
500 | mutex_init(&data->lock); | |
9d97e5c8 | 501 | |
cebe7373 ADK |
502 | ret = exynos_map_dt_data(pdev); |
503 | if (ret) | |
504 | return ret; | |
9d97e5c8 | 505 | |
cebe7373 | 506 | pdata = data->pdata; |
9d97e5c8 | 507 | |
cebe7373 | 508 | INIT_WORK(&data->irq_work, exynos_tmu_work); |
9d97e5c8 | 509 | |
2a16279c | 510 | data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); |
9d97e5c8 | 511 | if (IS_ERR(data->clk)) { |
9d97e5c8 | 512 | dev_err(&pdev->dev, "Failed to get clock\n"); |
79e093c3 | 513 | return PTR_ERR(data->clk); |
9d97e5c8 DK |
514 | } |
515 | ||
2a16279c SK |
516 | ret = clk_prepare(data->clk); |
517 | if (ret) | |
518 | return ret; | |
519 | ||
f22d9c03 ADK |
520 | if (pdata->type == SOC_ARCH_EXYNOS || |
521 | pdata->type == SOC_ARCH_EXYNOS4210) | |
522 | data->soc = pdata->type; | |
523 | else { | |
524 | ret = -EINVAL; | |
525 | dev_err(&pdev->dev, "Platform not supported\n"); | |
526 | goto err_clk; | |
527 | } | |
528 | ||
f22d9c03 | 529 | ret = exynos_tmu_initialize(pdev); |
9d97e5c8 DK |
530 | if (ret) { |
531 | dev_err(&pdev->dev, "Failed to initialize TMU\n"); | |
532 | goto err_clk; | |
533 | } | |
534 | ||
f22d9c03 | 535 | exynos_tmu_control(pdev, true); |
9d97e5c8 | 536 | |
cebe7373 ADK |
537 | /* Allocate a structure to register with the exynos core thermal */ |
538 | sensor_conf = devm_kzalloc(&pdev->dev, | |
539 | sizeof(struct thermal_sensor_conf), GFP_KERNEL); | |
540 | if (!sensor_conf) { | |
541 | dev_err(&pdev->dev, "Failed to allocate registration struct\n"); | |
542 | ret = -ENOMEM; | |
543 | goto err_clk; | |
544 | } | |
545 | sprintf(sensor_conf->name, "therm_zone%d", data->id); | |
546 | sensor_conf->read_temperature = (int (*)(void *))exynos_tmu_read; | |
547 | sensor_conf->write_emul_temp = | |
548 | (int (*)(void *, unsigned long))exynos_tmu_set_emulation; | |
549 | sensor_conf->driver_data = data; | |
550 | sensor_conf->trip_data.trip_count = pdata->trigger_enable[0] + | |
bb34b4c8 ADK |
551 | pdata->trigger_enable[1] + pdata->trigger_enable[2]+ |
552 | pdata->trigger_enable[3]; | |
7e0b55e6 | 553 | |
cebe7373 ADK |
554 | for (i = 0; i < sensor_conf->trip_data.trip_count; i++) { |
555 | sensor_conf->trip_data.trip_val[i] = | |
7e0b55e6 | 556 | pdata->threshold + pdata->trigger_levels[i]; |
cebe7373 | 557 | sensor_conf->trip_data.trip_type[i] = |
5c3cf552 ADK |
558 | pdata->trigger_type[i]; |
559 | } | |
7e0b55e6 | 560 | |
cebe7373 | 561 | sensor_conf->trip_data.trigger_falling = pdata->threshold_falling; |
4f0a6847 | 562 | |
cebe7373 | 563 | sensor_conf->cooling_data.freq_clip_count = pdata->freq_tab_count; |
7e0b55e6 | 564 | for (i = 0; i < pdata->freq_tab_count; i++) { |
cebe7373 | 565 | sensor_conf->cooling_data.freq_data[i].freq_clip_max = |
7e0b55e6 | 566 | pdata->freq_tab[i].freq_clip_max; |
cebe7373 | 567 | sensor_conf->cooling_data.freq_data[i].temp_level = |
7e0b55e6 ADK |
568 | pdata->freq_tab[i].temp_level; |
569 | } | |
cebe7373 ADK |
570 | sensor_conf->dev = &pdev->dev; |
571 | /* Register the sensor with thermal management interface */ | |
572 | ret = exynos_register_thermal(sensor_conf); | |
7e0b55e6 ADK |
573 | if (ret) { |
574 | dev_err(&pdev->dev, "Failed to register thermal interface\n"); | |
575 | goto err_clk; | |
576 | } | |
cebe7373 ADK |
577 | data->reg_conf = sensor_conf; |
578 | ||
579 | ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, | |
580 | IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); | |
581 | if (ret) { | |
582 | dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); | |
583 | goto err_clk; | |
584 | } | |
bbf63be4 | 585 | |
9d97e5c8 | 586 | return 0; |
9d97e5c8 | 587 | err_clk: |
2a16279c | 588 | clk_unprepare(data->clk); |
9d97e5c8 DK |
589 | return ret; |
590 | } | |
591 | ||
4eab7a9e | 592 | static int exynos_tmu_remove(struct platform_device *pdev) |
9d97e5c8 | 593 | { |
f22d9c03 | 594 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
9d97e5c8 | 595 | |
f22d9c03 | 596 | exynos_tmu_control(pdev, false); |
9d97e5c8 | 597 | |
cebe7373 | 598 | exynos_unregister_thermal(data->reg_conf); |
7e0b55e6 | 599 | |
2a16279c | 600 | clk_unprepare(data->clk); |
9d97e5c8 | 601 | |
9d97e5c8 DK |
602 | return 0; |
603 | } | |
604 | ||
08cd6753 | 605 | #ifdef CONFIG_PM_SLEEP |
f22d9c03 | 606 | static int exynos_tmu_suspend(struct device *dev) |
9d97e5c8 | 607 | { |
f22d9c03 | 608 | exynos_tmu_control(to_platform_device(dev), false); |
9d97e5c8 DK |
609 | |
610 | return 0; | |
611 | } | |
612 | ||
f22d9c03 | 613 | static int exynos_tmu_resume(struct device *dev) |
9d97e5c8 | 614 | { |
08cd6753 RW |
615 | struct platform_device *pdev = to_platform_device(dev); |
616 | ||
f22d9c03 ADK |
617 | exynos_tmu_initialize(pdev); |
618 | exynos_tmu_control(pdev, true); | |
9d97e5c8 DK |
619 | |
620 | return 0; | |
621 | } | |
08cd6753 | 622 | |
f22d9c03 ADK |
623 | static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, |
624 | exynos_tmu_suspend, exynos_tmu_resume); | |
625 | #define EXYNOS_TMU_PM (&exynos_tmu_pm) | |
9d97e5c8 | 626 | #else |
f22d9c03 | 627 | #define EXYNOS_TMU_PM NULL |
9d97e5c8 DK |
628 | #endif |
629 | ||
f22d9c03 | 630 | static struct platform_driver exynos_tmu_driver = { |
9d97e5c8 | 631 | .driver = { |
f22d9c03 | 632 | .name = "exynos-tmu", |
9d97e5c8 | 633 | .owner = THIS_MODULE, |
f22d9c03 | 634 | .pm = EXYNOS_TMU_PM, |
caa5cbd5 | 635 | .of_match_table = of_match_ptr(exynos_tmu_match), |
9d97e5c8 | 636 | }, |
f22d9c03 | 637 | .probe = exynos_tmu_probe, |
4eab7a9e | 638 | .remove = exynos_tmu_remove, |
9d97e5c8 DK |
639 | }; |
640 | ||
f22d9c03 | 641 | module_platform_driver(exynos_tmu_driver); |
9d97e5c8 | 642 | |
f22d9c03 | 643 | MODULE_DESCRIPTION("EXYNOS TMU Driver"); |
9d97e5c8 DK |
644 | MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); |
645 | MODULE_LICENSE("GPL"); | |
f22d9c03 | 646 | MODULE_ALIAS("platform:exynos-tmu"); |