]>
Commit | Line | Data |
---|---|---|
9d97e5c8 | 1 | /* |
59dfa54c | 2 | * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) |
9d97e5c8 DK |
3 | * |
4 | * Copyright (C) 2011 Samsung Electronics | |
5 | * Donggeun Kim <dg77.kim@samsung.com> | |
c48cbba6 | 6 | * Amit Daniel Kachhap <amit.kachhap@linaro.org> |
9d97e5c8 DK |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | */ | |
23 | ||
9d97e5c8 | 24 | #include <linux/clk.h> |
9d97e5c8 | 25 | #include <linux/io.h> |
1b678641 ADK |
26 | #include <linux/interrupt.h> |
27 | #include <linux/module.h> | |
f22d9c03 | 28 | #include <linux/of.h> |
cebe7373 ADK |
29 | #include <linux/of_address.h> |
30 | #include <linux/of_irq.h> | |
1b678641 | 31 | #include <linux/platform_device.h> |
1b678641 ADK |
32 | |
33 | #include "exynos_thermal_common.h" | |
0c1836a6 | 34 | #include "exynos_tmu.h" |
e6b7991e | 35 | #include "exynos_tmu_data.h" |
f22d9c03 | 36 | |
cebe7373 ADK |
37 | /** |
38 | * struct exynos_tmu_data : A structure to hold the private data of the TMU | |
39 | driver | |
40 | * @id: identifier of the one instance of the TMU controller. | |
41 | * @pdata: pointer to the tmu platform/configuration data | |
42 | * @base: base address of the single instance of the TMU controller. | |
43 | * @irq: irq number of the TMU controller. | |
44 | * @soc: id of the SOC type. | |
45 | * @irq_work: pointer to the irq work structure. | |
46 | * @lock: lock to implement synchronization. | |
47 | * @clk: pointer to the clock structure. | |
48 | * @temp_error1: fused value of the first point trim. | |
49 | * @temp_error2: fused value of the second point trim. | |
50 | * @reg_conf: pointer to structure to register with core thermal. | |
51 | */ | |
f22d9c03 | 52 | struct exynos_tmu_data { |
cebe7373 | 53 | int id; |
f22d9c03 | 54 | struct exynos_tmu_platform_data *pdata; |
9d97e5c8 DK |
55 | void __iomem *base; |
56 | int irq; | |
f22d9c03 | 57 | enum soc_type soc; |
9d97e5c8 DK |
58 | struct work_struct irq_work; |
59 | struct mutex lock; | |
60 | struct clk *clk; | |
61 | u8 temp_error1, temp_error2; | |
cebe7373 | 62 | struct thermal_sensor_conf *reg_conf; |
9d97e5c8 DK |
63 | }; |
64 | ||
65 | /* | |
66 | * TMU treats temperature as a mapped temperature code. | |
67 | * The temperature is converted differently depending on the calibration type. | |
68 | */ | |
f22d9c03 | 69 | static int temp_to_code(struct exynos_tmu_data *data, u8 temp) |
9d97e5c8 | 70 | { |
f22d9c03 | 71 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 DK |
72 | int temp_code; |
73 | ||
f22d9c03 ADK |
74 | if (data->soc == SOC_ARCH_EXYNOS4210) |
75 | /* temp should range between 25 and 125 */ | |
76 | if (temp < 25 || temp > 125) { | |
77 | temp_code = -EINVAL; | |
78 | goto out; | |
79 | } | |
9d97e5c8 DK |
80 | |
81 | switch (pdata->cal_type) { | |
82 | case TYPE_TWO_POINT_TRIMMING: | |
bb34b4c8 ADK |
83 | temp_code = (temp - pdata->first_point_trim) * |
84 | (data->temp_error2 - data->temp_error1) / | |
85 | (pdata->second_point_trim - pdata->first_point_trim) + | |
86 | data->temp_error1; | |
9d97e5c8 DK |
87 | break; |
88 | case TYPE_ONE_POINT_TRIMMING: | |
bb34b4c8 | 89 | temp_code = temp + data->temp_error1 - pdata->first_point_trim; |
9d97e5c8 DK |
90 | break; |
91 | default: | |
bb34b4c8 | 92 | temp_code = temp + pdata->default_temp_offset; |
9d97e5c8 DK |
93 | break; |
94 | } | |
95 | out: | |
96 | return temp_code; | |
97 | } | |
98 | ||
99 | /* | |
100 | * Calculate a temperature value from a temperature code. | |
101 | * The unit of the temperature is degree Celsius. | |
102 | */ | |
f22d9c03 | 103 | static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code) |
9d97e5c8 | 104 | { |
f22d9c03 | 105 | struct exynos_tmu_platform_data *pdata = data->pdata; |
9d97e5c8 DK |
106 | int temp; |
107 | ||
f22d9c03 ADK |
108 | if (data->soc == SOC_ARCH_EXYNOS4210) |
109 | /* temp_code should range between 75 and 175 */ | |
110 | if (temp_code < 75 || temp_code > 175) { | |
111 | temp = -ENODATA; | |
112 | goto out; | |
113 | } | |
9d97e5c8 DK |
114 | |
115 | switch (pdata->cal_type) { | |
116 | case TYPE_TWO_POINT_TRIMMING: | |
bb34b4c8 ADK |
117 | temp = (temp_code - data->temp_error1) * |
118 | (pdata->second_point_trim - pdata->first_point_trim) / | |
119 | (data->temp_error2 - data->temp_error1) + | |
120 | pdata->first_point_trim; | |
9d97e5c8 DK |
121 | break; |
122 | case TYPE_ONE_POINT_TRIMMING: | |
bb34b4c8 | 123 | temp = temp_code - data->temp_error1 + pdata->first_point_trim; |
9d97e5c8 DK |
124 | break; |
125 | default: | |
bb34b4c8 | 126 | temp = temp_code - pdata->default_temp_offset; |
9d97e5c8 DK |
127 | break; |
128 | } | |
129 | out: | |
130 | return temp; | |
131 | } | |
132 | ||
f22d9c03 | 133 | static int exynos_tmu_initialize(struct platform_device *pdev) |
9d97e5c8 | 134 | { |
f22d9c03 ADK |
135 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
136 | struct exynos_tmu_platform_data *pdata = data->pdata; | |
b8d582b9 | 137 | const struct exynos_tmu_registers *reg = pdata->registers; |
7ca04e58 | 138 | unsigned int status, trim_info = 0, con; |
4f0a6847 JL |
139 | unsigned int rising_threshold = 0, falling_threshold = 0; |
140 | int ret = 0, threshold_code, i, trigger_levs = 0; | |
9d97e5c8 DK |
141 | |
142 | mutex_lock(&data->lock); | |
143 | clk_enable(data->clk); | |
144 | ||
b8d582b9 | 145 | status = readb(data->base + reg->tmu_status); |
9d97e5c8 DK |
146 | if (!status) { |
147 | ret = -EBUSY; | |
148 | goto out; | |
149 | } | |
150 | ||
b8d582b9 ADK |
151 | if (data->soc == SOC_ARCH_EXYNOS) |
152 | __raw_writel(1, data->base + reg->triminfo_ctrl); | |
153 | ||
9d97e5c8 | 154 | /* Save trimming info in order to perform calibration */ |
b8d582b9 ADK |
155 | trim_info = readl(data->base + reg->triminfo_data); |
156 | data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK; | |
157 | data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) & | |
158 | EXYNOS_TMU_TEMP_MASK); | |
f22d9c03 | 159 | |
bb34b4c8 ADK |
160 | if ((pdata->min_efuse_value > data->temp_error1) || |
161 | (data->temp_error1 > pdata->max_efuse_value) || | |
f22d9c03 ADK |
162 | (data->temp_error2 != 0)) |
163 | data->temp_error1 = pdata->efuse_value; | |
164 | ||
7ca04e58 ADK |
165 | if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) { |
166 | dev_err(&pdev->dev, "Invalid max trigger level\n"); | |
167 | goto out; | |
168 | } | |
169 | ||
170 | for (i = 0; i < pdata->max_trigger_level; i++) { | |
171 | if (!pdata->trigger_levels[i]) | |
172 | continue; | |
173 | ||
174 | if ((pdata->trigger_type[i] == HW_TRIP) && | |
175 | (!pdata->trigger_levels[pdata->max_trigger_level - 1])) { | |
176 | dev_err(&pdev->dev, "Invalid hw trigger level\n"); | |
177 | ret = -EINVAL; | |
178 | goto out; | |
179 | } | |
180 | ||
181 | /* Count trigger levels except the HW trip*/ | |
182 | if (!(pdata->trigger_type[i] == HW_TRIP)) | |
4f0a6847 | 183 | trigger_levs++; |
7ca04e58 | 184 | } |
4f0a6847 | 185 | |
f22d9c03 ADK |
186 | if (data->soc == SOC_ARCH_EXYNOS4210) { |
187 | /* Write temperature code for threshold */ | |
188 | threshold_code = temp_to_code(data, pdata->threshold); | |
189 | if (threshold_code < 0) { | |
190 | ret = threshold_code; | |
191 | goto out; | |
192 | } | |
193 | writeb(threshold_code, | |
b8d582b9 | 194 | data->base + reg->threshold_temp); |
4f0a6847 | 195 | for (i = 0; i < trigger_levs; i++) |
b8d582b9 ADK |
196 | writeb(pdata->trigger_levels[i], data->base + |
197 | reg->threshold_th0 + i * sizeof(reg->threshold_th0)); | |
f22d9c03 | 198 | |
b8d582b9 | 199 | writel(reg->inten_rise_mask, data->base + reg->tmu_intclear); |
f22d9c03 | 200 | } else if (data->soc == SOC_ARCH_EXYNOS) { |
4f0a6847 | 201 | /* Write temperature code for rising and falling threshold */ |
7ca04e58 ADK |
202 | for (i = 0; |
203 | i < trigger_levs && i < EXYNOS_MAX_TRIGGER_PER_REG; i++) { | |
4f0a6847 JL |
204 | threshold_code = temp_to_code(data, |
205 | pdata->trigger_levels[i]); | |
206 | if (threshold_code < 0) { | |
207 | ret = threshold_code; | |
208 | goto out; | |
209 | } | |
210 | rising_threshold |= threshold_code << 8 * i; | |
211 | if (pdata->threshold_falling) { | |
212 | threshold_code = temp_to_code(data, | |
213 | pdata->trigger_levels[i] - | |
214 | pdata->threshold_falling); | |
215 | if (threshold_code > 0) | |
216 | falling_threshold |= | |
217 | threshold_code << 8 * i; | |
218 | } | |
f22d9c03 | 219 | } |
f22d9c03 ADK |
220 | |
221 | writel(rising_threshold, | |
b8d582b9 | 222 | data->base + reg->threshold_th0); |
4f0a6847 | 223 | writel(falling_threshold, |
b8d582b9 | 224 | data->base + reg->threshold_th1); |
f22d9c03 | 225 | |
b8d582b9 ADK |
226 | writel((reg->inten_rise_mask << reg->inten_rise_shift) | |
227 | (reg->inten_fall_mask << reg->inten_fall_shift), | |
228 | data->base + reg->tmu_intclear); | |
7ca04e58 ADK |
229 | |
230 | /* if last threshold limit is also present */ | |
231 | i = pdata->max_trigger_level - 1; | |
232 | if (pdata->trigger_levels[i] && | |
233 | (pdata->trigger_type[i] == HW_TRIP)) { | |
234 | threshold_code = temp_to_code(data, | |
235 | pdata->trigger_levels[i]); | |
236 | if (threshold_code < 0) { | |
237 | ret = threshold_code; | |
238 | goto out; | |
239 | } | |
240 | rising_threshold |= threshold_code << 8 * i; | |
241 | writel(rising_threshold, | |
242 | data->base + reg->threshold_th0); | |
243 | con = readl(data->base + reg->tmu_ctrl); | |
244 | con |= (1 << reg->therm_trip_en_shift); | |
245 | writel(con, data->base + reg->tmu_ctrl); | |
246 | } | |
9d97e5c8 | 247 | } |
9d97e5c8 DK |
248 | out: |
249 | clk_disable(data->clk); | |
250 | mutex_unlock(&data->lock); | |
251 | ||
252 | return ret; | |
253 | } | |
254 | ||
f22d9c03 | 255 | static void exynos_tmu_control(struct platform_device *pdev, bool on) |
9d97e5c8 | 256 | { |
f22d9c03 ADK |
257 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
258 | struct exynos_tmu_platform_data *pdata = data->pdata; | |
b8d582b9 | 259 | const struct exynos_tmu_registers *reg = pdata->registers; |
9d97e5c8 DK |
260 | unsigned int con, interrupt_en; |
261 | ||
262 | mutex_lock(&data->lock); | |
263 | clk_enable(data->clk); | |
264 | ||
b8d582b9 | 265 | con = readl(data->base + reg->tmu_ctrl); |
f22d9c03 | 266 | |
d0a0ce3e | 267 | if (pdata->reference_voltage) { |
b8d582b9 ADK |
268 | con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift); |
269 | con |= pdata->reference_voltage << reg->buf_vref_sel_shift; | |
d0a0ce3e ADK |
270 | } |
271 | ||
272 | if (pdata->gain) { | |
b8d582b9 ADK |
273 | con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift); |
274 | con |= (pdata->gain << reg->buf_slope_sel_shift); | |
d0a0ce3e ADK |
275 | } |
276 | ||
277 | if (pdata->noise_cancel_mode) { | |
b8d582b9 ADK |
278 | con &= ~(reg->therm_trip_mode_mask << |
279 | reg->therm_trip_mode_shift); | |
280 | con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift); | |
f22d9c03 ADK |
281 | } |
282 | ||
9d97e5c8 | 283 | if (on) { |
b8d582b9 | 284 | con |= (1 << reg->core_en_shift); |
d0a0ce3e | 285 | interrupt_en = |
b8d582b9 ADK |
286 | pdata->trigger_enable[3] << reg->inten_rise3_shift | |
287 | pdata->trigger_enable[2] << reg->inten_rise2_shift | | |
288 | pdata->trigger_enable[1] << reg->inten_rise1_shift | | |
289 | pdata->trigger_enable[0] << reg->inten_rise0_shift; | |
4f0a6847 | 290 | if (pdata->threshold_falling) |
d0a0ce3e | 291 | interrupt_en |= |
b8d582b9 | 292 | interrupt_en << reg->inten_fall0_shift; |
9d97e5c8 | 293 | } else { |
b8d582b9 | 294 | con &= ~(1 << reg->core_en_shift); |
9d97e5c8 DK |
295 | interrupt_en = 0; /* Disable all interrupts */ |
296 | } | |
b8d582b9 ADK |
297 | writel(interrupt_en, data->base + reg->tmu_inten); |
298 | writel(con, data->base + reg->tmu_ctrl); | |
9d97e5c8 DK |
299 | |
300 | clk_disable(data->clk); | |
301 | mutex_unlock(&data->lock); | |
302 | } | |
303 | ||
f22d9c03 | 304 | static int exynos_tmu_read(struct exynos_tmu_data *data) |
9d97e5c8 | 305 | { |
b8d582b9 ADK |
306 | struct exynos_tmu_platform_data *pdata = data->pdata; |
307 | const struct exynos_tmu_registers *reg = pdata->registers; | |
9d97e5c8 DK |
308 | u8 temp_code; |
309 | int temp; | |
310 | ||
311 | mutex_lock(&data->lock); | |
312 | clk_enable(data->clk); | |
313 | ||
b8d582b9 | 314 | temp_code = readb(data->base + reg->tmu_cur_temp); |
9d97e5c8 DK |
315 | temp = code_to_temp(data, temp_code); |
316 | ||
317 | clk_disable(data->clk); | |
318 | mutex_unlock(&data->lock); | |
319 | ||
320 | return temp; | |
321 | } | |
322 | ||
bffd1f8a ADK |
323 | #ifdef CONFIG_THERMAL_EMULATION |
324 | static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) | |
325 | { | |
326 | struct exynos_tmu_data *data = drv_data; | |
b8d582b9 ADK |
327 | struct exynos_tmu_platform_data *pdata = data->pdata; |
328 | const struct exynos_tmu_registers *reg = pdata->registers; | |
329 | unsigned int val; | |
bffd1f8a ADK |
330 | int ret = -EINVAL; |
331 | ||
332 | if (data->soc == SOC_ARCH_EXYNOS4210) | |
333 | goto out; | |
334 | ||
335 | if (temp && temp < MCELSIUS) | |
336 | goto out; | |
337 | ||
338 | mutex_lock(&data->lock); | |
339 | clk_enable(data->clk); | |
340 | ||
b8d582b9 | 341 | val = readl(data->base + reg->emul_con); |
bffd1f8a ADK |
342 | |
343 | if (temp) { | |
344 | temp /= MCELSIUS; | |
345 | ||
b8d582b9 | 346 | val = (EXYNOS_EMUL_TIME << reg->emul_time_shift) | |
bffd1f8a | 347 | (temp_to_code(data, temp) |
b8d582b9 | 348 | << reg->emul_temp_shift) | EXYNOS_EMUL_ENABLE; |
bffd1f8a | 349 | } else { |
b8d582b9 | 350 | val &= ~EXYNOS_EMUL_ENABLE; |
bffd1f8a ADK |
351 | } |
352 | ||
b8d582b9 | 353 | writel(val, data->base + reg->emul_con); |
bffd1f8a ADK |
354 | |
355 | clk_disable(data->clk); | |
356 | mutex_unlock(&data->lock); | |
357 | return 0; | |
358 | out: | |
359 | return ret; | |
360 | } | |
361 | #else | |
362 | static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp) | |
363 | { return -EINVAL; } | |
364 | #endif/*CONFIG_THERMAL_EMULATION*/ | |
365 | ||
f22d9c03 | 366 | static void exynos_tmu_work(struct work_struct *work) |
9d97e5c8 | 367 | { |
f22d9c03 ADK |
368 | struct exynos_tmu_data *data = container_of(work, |
369 | struct exynos_tmu_data, irq_work); | |
b8d582b9 ADK |
370 | struct exynos_tmu_platform_data *pdata = data->pdata; |
371 | const struct exynos_tmu_registers *reg = pdata->registers; | |
a4463c4f | 372 | unsigned int val_irq; |
9d97e5c8 | 373 | |
cebe7373 | 374 | exynos_report_trigger(data->reg_conf); |
9d97e5c8 DK |
375 | mutex_lock(&data->lock); |
376 | clk_enable(data->clk); | |
b8d582b9 | 377 | |
a4463c4f ADK |
378 | /* TODO: take action based on particular interrupt */ |
379 | val_irq = readl(data->base + reg->tmu_intstat); | |
380 | /* clear the interrupts */ | |
381 | writel(val_irq, data->base + reg->tmu_intclear); | |
b8d582b9 | 382 | |
9d97e5c8 DK |
383 | clk_disable(data->clk); |
384 | mutex_unlock(&data->lock); | |
3ad9524a | 385 | |
f22d9c03 | 386 | enable_irq(data->irq); |
9d97e5c8 DK |
387 | } |
388 | ||
f22d9c03 | 389 | static irqreturn_t exynos_tmu_irq(int irq, void *id) |
9d97e5c8 | 390 | { |
f22d9c03 | 391 | struct exynos_tmu_data *data = id; |
9d97e5c8 DK |
392 | |
393 | disable_irq_nosync(irq); | |
394 | schedule_work(&data->irq_work); | |
395 | ||
396 | return IRQ_HANDLED; | |
397 | } | |
17be868e | 398 | |
17be868e ADK |
399 | #ifdef CONFIG_OF |
400 | static const struct of_device_id exynos_tmu_match[] = { | |
401 | { | |
402 | .compatible = "samsung,exynos4210-tmu", | |
403 | .data = (void *)EXYNOS4210_TMU_DRV_DATA, | |
404 | }, | |
b6cee53c SK |
405 | { |
406 | .compatible = "samsung,exynos4412-tmu", | |
e6b7991e | 407 | .data = (void *)EXYNOS5250_TMU_DRV_DATA, |
b6cee53c | 408 | }, |
17be868e ADK |
409 | { |
410 | .compatible = "samsung,exynos5250-tmu", | |
e6b7991e | 411 | .data = (void *)EXYNOS5250_TMU_DRV_DATA, |
17be868e ADK |
412 | }, |
413 | {}, | |
414 | }; | |
415 | MODULE_DEVICE_TABLE(of, exynos_tmu_match); | |
17be868e ADK |
416 | #endif |
417 | ||
17be868e | 418 | static inline struct exynos_tmu_platform_data *exynos_get_driver_data( |
cebe7373 | 419 | struct platform_device *pdev, int id) |
17be868e ADK |
420 | { |
421 | #ifdef CONFIG_OF | |
cebe7373 ADK |
422 | struct exynos_tmu_init_data *data_table; |
423 | struct exynos_tmu_platform_data *tmu_data; | |
17be868e ADK |
424 | if (pdev->dev.of_node) { |
425 | const struct of_device_id *match; | |
426 | match = of_match_node(exynos_tmu_match, pdev->dev.of_node); | |
427 | if (!match) | |
428 | return NULL; | |
cebe7373 ADK |
429 | data_table = (struct exynos_tmu_init_data *) match->data; |
430 | if (!data_table || id >= data_table->tmu_count) | |
431 | return NULL; | |
432 | tmu_data = data_table->tmu_data; | |
433 | return (struct exynos_tmu_platform_data *) (tmu_data + id); | |
17be868e ADK |
434 | } |
435 | #endif | |
1cd1ecb6 | 436 | return NULL; |
7e0b55e6 | 437 | } |
bbf63be4 | 438 | |
cebe7373 | 439 | static int exynos_map_dt_data(struct platform_device *pdev) |
9d97e5c8 | 440 | { |
cebe7373 ADK |
441 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
442 | struct exynos_tmu_platform_data *pdata; | |
443 | struct resource res; | |
444 | ||
445 | if (!data) | |
446 | return -ENODEV; | |
9d97e5c8 | 447 | |
cebe7373 ADK |
448 | data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); |
449 | if (data->id < 0) | |
450 | data->id = 0; | |
17be868e | 451 | |
cebe7373 ADK |
452 | data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); |
453 | if (data->irq <= 0) { | |
454 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
455 | return -ENODEV; | |
456 | } | |
457 | ||
458 | if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { | |
459 | dev_err(&pdev->dev, "failed to get Resource 0\n"); | |
460 | return -ENODEV; | |
461 | } | |
462 | ||
463 | data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); | |
464 | if (!data->base) { | |
465 | dev_err(&pdev->dev, "Failed to ioremap memory\n"); | |
466 | return -EADDRNOTAVAIL; | |
467 | } | |
468 | ||
469 | pdata = exynos_get_driver_data(pdev, data->id); | |
9d97e5c8 DK |
470 | if (!pdata) { |
471 | dev_err(&pdev->dev, "No platform init data supplied.\n"); | |
472 | return -ENODEV; | |
473 | } | |
cebe7373 ADK |
474 | data->pdata = pdata; |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | static int exynos_tmu_probe(struct platform_device *pdev) | |
480 | { | |
481 | struct exynos_tmu_data *data; | |
482 | struct exynos_tmu_platform_data *pdata; | |
483 | struct thermal_sensor_conf *sensor_conf; | |
484 | int ret, i; | |
485 | ||
79e093c3 ADK |
486 | data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), |
487 | GFP_KERNEL); | |
9d97e5c8 DK |
488 | if (!data) { |
489 | dev_err(&pdev->dev, "Failed to allocate driver structure\n"); | |
490 | return -ENOMEM; | |
491 | } | |
492 | ||
cebe7373 ADK |
493 | platform_set_drvdata(pdev, data); |
494 | mutex_init(&data->lock); | |
9d97e5c8 | 495 | |
cebe7373 ADK |
496 | ret = exynos_map_dt_data(pdev); |
497 | if (ret) | |
498 | return ret; | |
9d97e5c8 | 499 | |
cebe7373 | 500 | pdata = data->pdata; |
9d97e5c8 | 501 | |
cebe7373 | 502 | INIT_WORK(&data->irq_work, exynos_tmu_work); |
9d97e5c8 | 503 | |
2a16279c | 504 | data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); |
9d97e5c8 | 505 | if (IS_ERR(data->clk)) { |
9d97e5c8 | 506 | dev_err(&pdev->dev, "Failed to get clock\n"); |
79e093c3 | 507 | return PTR_ERR(data->clk); |
9d97e5c8 DK |
508 | } |
509 | ||
2a16279c SK |
510 | ret = clk_prepare(data->clk); |
511 | if (ret) | |
512 | return ret; | |
513 | ||
f22d9c03 ADK |
514 | if (pdata->type == SOC_ARCH_EXYNOS || |
515 | pdata->type == SOC_ARCH_EXYNOS4210) | |
516 | data->soc = pdata->type; | |
517 | else { | |
518 | ret = -EINVAL; | |
519 | dev_err(&pdev->dev, "Platform not supported\n"); | |
520 | goto err_clk; | |
521 | } | |
522 | ||
f22d9c03 | 523 | ret = exynos_tmu_initialize(pdev); |
9d97e5c8 DK |
524 | if (ret) { |
525 | dev_err(&pdev->dev, "Failed to initialize TMU\n"); | |
526 | goto err_clk; | |
527 | } | |
528 | ||
f22d9c03 | 529 | exynos_tmu_control(pdev, true); |
9d97e5c8 | 530 | |
cebe7373 ADK |
531 | /* Allocate a structure to register with the exynos core thermal */ |
532 | sensor_conf = devm_kzalloc(&pdev->dev, | |
533 | sizeof(struct thermal_sensor_conf), GFP_KERNEL); | |
534 | if (!sensor_conf) { | |
535 | dev_err(&pdev->dev, "Failed to allocate registration struct\n"); | |
536 | ret = -ENOMEM; | |
537 | goto err_clk; | |
538 | } | |
539 | sprintf(sensor_conf->name, "therm_zone%d", data->id); | |
540 | sensor_conf->read_temperature = (int (*)(void *))exynos_tmu_read; | |
541 | sensor_conf->write_emul_temp = | |
542 | (int (*)(void *, unsigned long))exynos_tmu_set_emulation; | |
543 | sensor_conf->driver_data = data; | |
544 | sensor_conf->trip_data.trip_count = pdata->trigger_enable[0] + | |
bb34b4c8 ADK |
545 | pdata->trigger_enable[1] + pdata->trigger_enable[2]+ |
546 | pdata->trigger_enable[3]; | |
7e0b55e6 | 547 | |
cebe7373 ADK |
548 | for (i = 0; i < sensor_conf->trip_data.trip_count; i++) { |
549 | sensor_conf->trip_data.trip_val[i] = | |
7e0b55e6 | 550 | pdata->threshold + pdata->trigger_levels[i]; |
cebe7373 | 551 | sensor_conf->trip_data.trip_type[i] = |
5c3cf552 ADK |
552 | pdata->trigger_type[i]; |
553 | } | |
7e0b55e6 | 554 | |
cebe7373 | 555 | sensor_conf->trip_data.trigger_falling = pdata->threshold_falling; |
4f0a6847 | 556 | |
cebe7373 | 557 | sensor_conf->cooling_data.freq_clip_count = pdata->freq_tab_count; |
7e0b55e6 | 558 | for (i = 0; i < pdata->freq_tab_count; i++) { |
cebe7373 | 559 | sensor_conf->cooling_data.freq_data[i].freq_clip_max = |
7e0b55e6 | 560 | pdata->freq_tab[i].freq_clip_max; |
cebe7373 | 561 | sensor_conf->cooling_data.freq_data[i].temp_level = |
7e0b55e6 ADK |
562 | pdata->freq_tab[i].temp_level; |
563 | } | |
cebe7373 ADK |
564 | sensor_conf->dev = &pdev->dev; |
565 | /* Register the sensor with thermal management interface */ | |
566 | ret = exynos_register_thermal(sensor_conf); | |
7e0b55e6 ADK |
567 | if (ret) { |
568 | dev_err(&pdev->dev, "Failed to register thermal interface\n"); | |
569 | goto err_clk; | |
570 | } | |
cebe7373 ADK |
571 | data->reg_conf = sensor_conf; |
572 | ||
573 | ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, | |
574 | IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); | |
575 | if (ret) { | |
576 | dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); | |
577 | goto err_clk; | |
578 | } | |
bbf63be4 | 579 | |
9d97e5c8 | 580 | return 0; |
9d97e5c8 | 581 | err_clk: |
2a16279c | 582 | clk_unprepare(data->clk); |
9d97e5c8 DK |
583 | return ret; |
584 | } | |
585 | ||
4eab7a9e | 586 | static int exynos_tmu_remove(struct platform_device *pdev) |
9d97e5c8 | 587 | { |
f22d9c03 | 588 | struct exynos_tmu_data *data = platform_get_drvdata(pdev); |
9d97e5c8 | 589 | |
f22d9c03 | 590 | exynos_tmu_control(pdev, false); |
9d97e5c8 | 591 | |
cebe7373 | 592 | exynos_unregister_thermal(data->reg_conf); |
7e0b55e6 | 593 | |
2a16279c | 594 | clk_unprepare(data->clk); |
9d97e5c8 | 595 | |
9d97e5c8 DK |
596 | return 0; |
597 | } | |
598 | ||
08cd6753 | 599 | #ifdef CONFIG_PM_SLEEP |
f22d9c03 | 600 | static int exynos_tmu_suspend(struct device *dev) |
9d97e5c8 | 601 | { |
f22d9c03 | 602 | exynos_tmu_control(to_platform_device(dev), false); |
9d97e5c8 DK |
603 | |
604 | return 0; | |
605 | } | |
606 | ||
f22d9c03 | 607 | static int exynos_tmu_resume(struct device *dev) |
9d97e5c8 | 608 | { |
08cd6753 RW |
609 | struct platform_device *pdev = to_platform_device(dev); |
610 | ||
f22d9c03 ADK |
611 | exynos_tmu_initialize(pdev); |
612 | exynos_tmu_control(pdev, true); | |
9d97e5c8 DK |
613 | |
614 | return 0; | |
615 | } | |
08cd6753 | 616 | |
f22d9c03 ADK |
617 | static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, |
618 | exynos_tmu_suspend, exynos_tmu_resume); | |
619 | #define EXYNOS_TMU_PM (&exynos_tmu_pm) | |
9d97e5c8 | 620 | #else |
f22d9c03 | 621 | #define EXYNOS_TMU_PM NULL |
9d97e5c8 DK |
622 | #endif |
623 | ||
f22d9c03 | 624 | static struct platform_driver exynos_tmu_driver = { |
9d97e5c8 | 625 | .driver = { |
f22d9c03 | 626 | .name = "exynos-tmu", |
9d97e5c8 | 627 | .owner = THIS_MODULE, |
f22d9c03 | 628 | .pm = EXYNOS_TMU_PM, |
caa5cbd5 | 629 | .of_match_table = of_match_ptr(exynos_tmu_match), |
9d97e5c8 | 630 | }, |
f22d9c03 | 631 | .probe = exynos_tmu_probe, |
4eab7a9e | 632 | .remove = exynos_tmu_remove, |
9d97e5c8 DK |
633 | }; |
634 | ||
f22d9c03 | 635 | module_platform_driver(exynos_tmu_driver); |
9d97e5c8 | 636 | |
f22d9c03 | 637 | MODULE_DESCRIPTION("EXYNOS TMU Driver"); |
9d97e5c8 DK |
638 | MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); |
639 | MODULE_LICENSE("GPL"); | |
f22d9c03 | 640 | MODULE_ALIAS("platform:exynos-tmu"); |