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9d97e5c8 | 1 | /* |
0c1836a6 | 2 | * exynos_tmu.h - Samsung EXYNOS TMU (Thermal Management Unit) |
9d97e5c8 DK |
3 | * |
4 | * Copyright (C) 2011 Samsung Electronics | |
5 | * Donggeun Kim <dg77.kim@samsung.com> | |
0c1836a6 | 6 | * Amit Daniel Kachhap <amit.daniel@samsung.com> |
9d97e5c8 DK |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
0c1836a6 ADK |
23 | #ifndef _EXYNOS_TMU_H |
24 | #define _EXYNOS_TMU_H | |
7e0b55e6 | 25 | #include <linux/cpu_cooling.h> |
9d97e5c8 | 26 | |
0c1836a6 ADK |
27 | #include "exynos_thermal_common.h" |
28 | ||
9d97e5c8 DK |
29 | enum calibration_type { |
30 | TYPE_ONE_POINT_TRIMMING, | |
31 | TYPE_TWO_POINT_TRIMMING, | |
32 | TYPE_NONE, | |
33 | }; | |
34 | ||
bb34b4c8 ADK |
35 | enum calibration_mode { |
36 | SW_MODE, | |
37 | HW_MODE, | |
38 | }; | |
39 | ||
f22d9c03 ADK |
40 | enum soc_type { |
41 | SOC_ARCH_EXYNOS4210 = 1, | |
42 | SOC_ARCH_EXYNOS, | |
43 | }; | |
7e0b55e6 | 44 | |
b8d582b9 ADK |
45 | /** |
46 | * struct exynos_tmu_register - register descriptors to access registers and | |
47 | * bitfields. The register validity, offsets and bitfield values may vary | |
48 | * slightly across different exynos SOC's. | |
49 | * @triminfo_data: register containing 2 pont trimming data | |
50 | * @triminfo_25_shift: shift bit of the 25 C trim value in triminfo_data reg. | |
51 | * @triminfo_85_shift: shift bit of the 85 C trim value in triminfo_data reg. | |
52 | * @triminfo_ctrl: trim info controller register. | |
53 | * @triminfo_reload_shift: shift of triminfo reload enable bit in triminfo_ctrl | |
54 | reg. | |
55 | * @tmu_ctrl: TMU main controller register. | |
56 | * @buf_vref_sel_shift: shift bits of reference voltage in tmu_ctrl register. | |
57 | * @buf_vref_sel_mask: mask bits of reference voltage in tmu_ctrl register. | |
58 | * @therm_trip_mode_shift: shift bits of tripping mode in tmu_ctrl register. | |
59 | * @therm_trip_mode_mask: mask bits of tripping mode in tmu_ctrl register. | |
60 | * @therm_trip_en_shift: shift bits of tripping enable in tmu_ctrl register. | |
61 | * @buf_slope_sel_shift: shift bits of amplifier gain value in tmu_ctrl | |
62 | register. | |
63 | * @buf_slope_sel_mask: mask bits of amplifier gain value in tmu_ctrl register. | |
64 | * @therm_trip_tq_en_shift: shift bits of thermal trip enable by TQ pin in | |
65 | tmu_ctrl register. | |
66 | * @core_en_shift: shift bits of TMU core enable bit in tmu_ctrl register. | |
67 | * @tmu_status: register drescribing the TMU status. | |
68 | * @tmu_cur_temp: register containing the current temperature of the TMU. | |
69 | * @tmu_cur_temp_shift: shift bits of current temp value in tmu_cur_temp | |
70 | register. | |
71 | * @threshold_temp: register containing the base threshold level. | |
72 | * @threshold_th0: Register containing first set of rising levels. | |
73 | * @threshold_th0_l0_shift: shift bits of level0 threshold temperature. | |
74 | * @threshold_th0_l1_shift: shift bits of level1 threshold temperature. | |
75 | * @threshold_th0_l2_shift: shift bits of level2 threshold temperature. | |
76 | * @threshold_th0_l3_shift: shift bits of level3 threshold temperature. | |
77 | * @threshold_th1: Register containing second set of rising levels. | |
78 | * @threshold_th1_l0_shift: shift bits of level0 threshold temperature. | |
79 | * @threshold_th1_l1_shift: shift bits of level1 threshold temperature. | |
80 | * @threshold_th1_l2_shift: shift bits of level2 threshold temperature. | |
81 | * @threshold_th1_l3_shift: shift bits of level3 threshold temperature. | |
82 | * @threshold_th2: Register containing third set of rising levels. | |
83 | * @threshold_th2_l0_shift: shift bits of level0 threshold temperature. | |
84 | * @threshold_th3: Register containing fourth set of rising levels. | |
85 | * @threshold_th3_l0_shift: shift bits of level0 threshold temperature. | |
86 | * @tmu_inten: register containing the different threshold interrupt | |
87 | enable bits. | |
88 | * @inten_rise_shift: shift bits of all rising interrupt bits. | |
89 | * @inten_rise_mask: mask bits of all rising interrupt bits. | |
90 | * @inten_fall_shift: shift bits of all rising interrupt bits. | |
91 | * @inten_fall_mask: mask bits of all rising interrupt bits. | |
92 | * @inten_rise0_shift: shift bits of rising 0 interrupt bits. | |
93 | * @inten_rise1_shift: shift bits of rising 1 interrupt bits. | |
94 | * @inten_rise2_shift: shift bits of rising 2 interrupt bits. | |
95 | * @inten_rise3_shift: shift bits of rising 3 interrupt bits. | |
96 | * @inten_fall0_shift: shift bits of falling 0 interrupt bits. | |
97 | * @inten_fall1_shift: shift bits of falling 1 interrupt bits. | |
98 | * @inten_fall2_shift: shift bits of falling 2 interrupt bits. | |
99 | * @inten_fall3_shift: shift bits of falling 3 interrupt bits. | |
100 | * @tmu_intstat: Register containing the interrupt status values. | |
101 | * @tmu_intclear: Register for clearing the raised interrupt status. | |
102 | * @emul_con: TMU emulation controller register. | |
103 | * @emul_temp_shift: shift bits of emulation temperature. | |
104 | * @emul_time_shift: shift bits of emulation time. | |
105 | * @emul_time_mask: mask bits of emulation time. | |
106 | */ | |
107 | struct exynos_tmu_registers { | |
108 | u32 triminfo_data; | |
109 | u32 triminfo_25_shift; | |
110 | u32 triminfo_85_shift; | |
111 | ||
112 | u32 triminfo_ctrl; | |
113 | u32 triminfo_reload_shift; | |
114 | ||
115 | u32 tmu_ctrl; | |
116 | u32 buf_vref_sel_shift; | |
117 | u32 buf_vref_sel_mask; | |
118 | u32 therm_trip_mode_shift; | |
119 | u32 therm_trip_mode_mask; | |
120 | u32 therm_trip_en_shift; | |
121 | u32 buf_slope_sel_shift; | |
122 | u32 buf_slope_sel_mask; | |
123 | u32 therm_trip_tq_en_shift; | |
124 | u32 core_en_shift; | |
125 | ||
126 | u32 tmu_status; | |
127 | ||
128 | u32 tmu_cur_temp; | |
129 | u32 tmu_cur_temp_shift; | |
130 | ||
131 | u32 threshold_temp; | |
132 | ||
133 | u32 threshold_th0; | |
134 | u32 threshold_th0_l0_shift; | |
135 | u32 threshold_th0_l1_shift; | |
136 | u32 threshold_th0_l2_shift; | |
137 | u32 threshold_th0_l3_shift; | |
138 | ||
139 | u32 threshold_th1; | |
140 | u32 threshold_th1_l0_shift; | |
141 | u32 threshold_th1_l1_shift; | |
142 | u32 threshold_th1_l2_shift; | |
143 | u32 threshold_th1_l3_shift; | |
144 | ||
145 | u32 threshold_th2; | |
146 | u32 threshold_th2_l0_shift; | |
147 | ||
148 | u32 threshold_th3; | |
149 | u32 threshold_th3_l0_shift; | |
150 | ||
151 | u32 tmu_inten; | |
152 | u32 inten_rise_shift; | |
153 | u32 inten_rise_mask; | |
154 | u32 inten_fall_shift; | |
155 | u32 inten_fall_mask; | |
156 | u32 inten_rise0_shift; | |
157 | u32 inten_rise1_shift; | |
158 | u32 inten_rise2_shift; | |
159 | u32 inten_rise3_shift; | |
160 | u32 inten_fall0_shift; | |
161 | u32 inten_fall1_shift; | |
162 | u32 inten_fall2_shift; | |
163 | u32 inten_fall3_shift; | |
164 | ||
165 | u32 tmu_intstat; | |
166 | ||
167 | u32 tmu_intclear; | |
168 | ||
169 | u32 emul_con; | |
170 | u32 emul_temp_shift; | |
171 | u32 emul_time_shift; | |
172 | u32 emul_time_mask; | |
173 | }; | |
174 | ||
9d97e5c8 | 175 | /** |
f22d9c03 | 176 | * struct exynos_tmu_platform_data |
9d97e5c8 DK |
177 | * @threshold: basic temperature for generating interrupt |
178 | * 25 <= threshold <= 125 [unit: degree Celsius] | |
4f0a6847 JL |
179 | * @threshold_falling: differntial value for setting threshold |
180 | * of temperature falling interrupt. | |
9d97e5c8 DK |
181 | * @trigger_levels: array for each interrupt levels |
182 | * [unit: degree Celsius] | |
183 | * 0: temperature for trigger_level0 interrupt | |
184 | * condition for trigger_level0 interrupt: | |
185 | * current temperature > threshold + trigger_levels[0] | |
186 | * 1: temperature for trigger_level1 interrupt | |
187 | * condition for trigger_level1 interrupt: | |
188 | * current temperature > threshold + trigger_levels[1] | |
189 | * 2: temperature for trigger_level2 interrupt | |
190 | * condition for trigger_level2 interrupt: | |
191 | * current temperature > threshold + trigger_levels[2] | |
192 | * 3: temperature for trigger_level3 interrupt | |
193 | * condition for trigger_level3 interrupt: | |
194 | * current temperature > threshold + trigger_levels[3] | |
bb34b4c8 ADK |
195 | * @trigger_type: defines the type of trigger. Possible values are, |
196 | * THROTTLE_ACTIVE trigger type | |
197 | * THROTTLE_PASSIVE trigger type | |
198 | * SW_TRIP trigger type | |
199 | * HW_TRIP | |
200 | * @trigger_enable[]: array to denote which trigger levels are enabled. | |
201 | * 1 = enable trigger_level[] interrupt, | |
202 | * 0 = disable trigger_level[] interrupt | |
203 | * @max_trigger_level: max trigger level supported by the TMU | |
9d97e5c8 DK |
204 | * @gain: gain of amplifier in the positive-TC generator block |
205 | * 0 <= gain <= 15 | |
206 | * @reference_voltage: reference voltage of amplifier | |
207 | * in the positive-TC generator block | |
208 | * 0 <= reference_voltage <= 31 | |
f22d9c03 ADK |
209 | * @noise_cancel_mode: noise cancellation mode |
210 | * 000, 100, 101, 110 and 111 can be different modes | |
211 | * @type: determines the type of SOC | |
212 | * @efuse_value: platform defined fuse value | |
bb34b4c8 ADK |
213 | * @min_efuse_value: minimum valid trimming data |
214 | * @max_efuse_value: maximum valid trimming data | |
215 | * @first_point_trim: temp value of the first point trimming | |
216 | * @second_point_trim: temp value of the second point trimming | |
217 | * @default_temp_offset: default temperature offset in case of no trimming | |
9d97e5c8 | 218 | * @cal_type: calibration type for temperature |
bb34b4c8 | 219 | * @cal_mode: calibration mode for temperature |
7e0b55e6 ADK |
220 | * @freq_clip_table: Table representing frequency reduction percentage. |
221 | * @freq_tab_count: Count of the above table as frequency reduction may | |
222 | * applicable to only some of the trigger levels. | |
b8d582b9 ADK |
223 | * @registers: Pointer to structure containing all the TMU controller registers |
224 | * and bitfields shifts and masks. | |
9d97e5c8 | 225 | * |
f22d9c03 | 226 | * This structure is required for configuration of exynos_tmu driver. |
9d97e5c8 | 227 | */ |
f22d9c03 | 228 | struct exynos_tmu_platform_data { |
9d97e5c8 | 229 | u8 threshold; |
4f0a6847 | 230 | u8 threshold_falling; |
bb34b4c8 ADK |
231 | u8 trigger_levels[MAX_TRIP_COUNT]; |
232 | enum trigger_type trigger_type[MAX_TRIP_COUNT]; | |
233 | bool trigger_enable[MAX_TRIP_COUNT]; | |
234 | u8 max_trigger_level; | |
9d97e5c8 DK |
235 | u8 gain; |
236 | u8 reference_voltage; | |
f22d9c03 | 237 | u8 noise_cancel_mode; |
bb34b4c8 | 238 | |
f22d9c03 | 239 | u32 efuse_value; |
bb34b4c8 ADK |
240 | u32 min_efuse_value; |
241 | u32 max_efuse_value; | |
242 | u8 first_point_trim; | |
243 | u8 second_point_trim; | |
244 | u8 default_temp_offset; | |
9d97e5c8 DK |
245 | |
246 | enum calibration_type cal_type; | |
bb34b4c8 | 247 | enum calibration_mode cal_mode; |
f22d9c03 | 248 | enum soc_type type; |
7e0b55e6 ADK |
249 | struct freq_clip_table freq_tab[4]; |
250 | unsigned int freq_tab_count; | |
b8d582b9 | 251 | const struct exynos_tmu_registers *registers; |
9d97e5c8 | 252 | }; |
0c1836a6 | 253 | #endif /* _EXYNOS_TMU_H */ |