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e6b7991e ADK |
1 | /* |
2 | * exynos_tmu_data.h - Samsung EXYNOS tmu data header file | |
3 | * | |
4 | * Copyright (C) 2013 Samsung Electronics | |
5 | * Amit Daniel Kachhap <amit.daniel@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | * | |
21 | */ | |
22 | ||
23 | #ifndef _EXYNOS_TMU_DATA_H | |
24 | #define _EXYNOS_TMU_DATA_H | |
25 | ||
b8d582b9 ADK |
26 | /* Exynos generic registers */ |
27 | #define EXYNOS_TMU_REG_TRIMINFO 0x0 | |
28 | #define EXYNOS_TMU_REG_CONTROL 0x20 | |
29 | #define EXYNOS_TMU_REG_STATUS 0x28 | |
30 | #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 | |
31 | #define EXYNOS_TMU_REG_INTEN 0x70 | |
32 | #define EXYNOS_TMU_REG_INTSTAT 0x74 | |
33 | #define EXYNOS_TMU_REG_INTCLEAR 0x78 | |
34 | ||
35 | #define EXYNOS_TMU_TEMP_MASK 0xff | |
36 | #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 | |
37 | #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f | |
38 | #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf | |
39 | #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 | |
40 | #define EXYNOS_TMU_CORE_EN_SHIFT 0 | |
41 | ||
32a74164 CC |
42 | /* Exynos3250 specific registers */ |
43 | #define EXYNOS_TMU_TRIMINFO_CON1 0x10 | |
44 | ||
b8d582b9 ADK |
45 | /* Exynos4210 specific registers */ |
46 | #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 | |
47 | #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 | |
e8419716 | 48 | |
32a74164 CC |
49 | /* Exynos5250, Exynos4412, Exynos3250 specific registers */ |
50 | #define EXYNOS_TMU_TRIMINFO_CON2 0x14 | |
b8d582b9 ADK |
51 | #define EXYNOS_THD_TEMP_RISE 0x50 |
52 | #define EXYNOS_THD_TEMP_FALL 0x54 | |
53 | #define EXYNOS_EMUL_CON 0x80 | |
54 | ||
56c64da7 | 55 | #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 |
b8d582b9 ADK |
56 | #define EXYNOS_TRIMINFO_25_SHIFT 0 |
57 | #define EXYNOS_TRIMINFO_85_SHIFT 8 | |
b8d582b9 ADK |
58 | #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 |
59 | #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 | |
60 | #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 | |
61 | ||
62 | #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 | |
63 | #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 | |
64 | #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8 | |
65 | #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12 | |
66 | #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 | |
b8d582b9 ADK |
67 | |
68 | #define EXYNOS_EMUL_TIME 0x57F0 | |
69 | #define EXYNOS_EMUL_TIME_MASK 0xffff | |
70 | #define EXYNOS_EMUL_TIME_SHIFT 16 | |
71 | #define EXYNOS_EMUL_DATA_SHIFT 8 | |
72 | #define EXYNOS_EMUL_DATA_MASK 0xFF | |
73 | #define EXYNOS_EMUL_ENABLE 0x1 | |
74 | ||
7ca04e58 ADK |
75 | #define EXYNOS_MAX_TRIGGER_PER_REG 4 |
76 | ||
923488a5 | 77 | /* Exynos5260 specific */ |
923488a5 NKC |
78 | #define EXYNOS5260_TMU_REG_INTEN 0xC0 |
79 | #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 | |
80 | #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 | |
923488a5 NKC |
81 | #define EXYNOS5260_EMUL_CON 0x100 |
82 | ||
86f5362e LM |
83 | /* Exynos4412 specific */ |
84 | #define EXYNOS4412_MUX_ADDR_VALUE 6 | |
85 | #define EXYNOS4412_MUX_ADDR_SHIFT 20 | |
86 | ||
a0395eee ADK |
87 | /*exynos5440 specific registers*/ |
88 | #define EXYNOS5440_TMU_S0_7_TRIM 0x000 | |
89 | #define EXYNOS5440_TMU_S0_7_CTRL 0x020 | |
90 | #define EXYNOS5440_TMU_S0_7_DEBUG 0x040 | |
91 | #define EXYNOS5440_TMU_S0_7_STATUS 0x060 | |
92 | #define EXYNOS5440_TMU_S0_7_TEMP 0x0f0 | |
93 | #define EXYNOS5440_TMU_S0_7_TH0 0x110 | |
94 | #define EXYNOS5440_TMU_S0_7_TH1 0x130 | |
95 | #define EXYNOS5440_TMU_S0_7_TH2 0x150 | |
a0395eee ADK |
96 | #define EXYNOS5440_TMU_S0_7_IRQEN 0x210 |
97 | #define EXYNOS5440_TMU_S0_7_IRQ 0x230 | |
98 | /* exynos5440 common registers */ | |
99 | #define EXYNOS5440_TMU_IRQ_STATUS 0x000 | |
100 | #define EXYNOS5440_TMU_PMIN 0x004 | |
a0395eee | 101 | |
a0395eee ADK |
102 | #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0 |
103 | #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1 | |
104 | #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2 | |
105 | #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3 | |
106 | #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4 | |
a0395eee ADK |
107 | #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24 |
108 | #define EXYNOS5440_EFUSE_SWAP_OFFSET 8 | |
109 | ||
1fe56dc1 CC |
110 | #if defined(CONFIG_SOC_EXYNOS3250) |
111 | extern struct exynos_tmu_init_data const exynos3250_default_tmu_data; | |
112 | #define EXYNOS3250_TMU_DRV_DATA (&exynos3250_default_tmu_data) | |
113 | #else | |
114 | #define EXYNOS3250_TMU_DRV_DATA (NULL) | |
115 | #endif | |
116 | ||
e6b7991e | 117 | #if defined(CONFIG_CPU_EXYNOS4210) |
cebe7373 | 118 | extern struct exynos_tmu_init_data const exynos4210_default_tmu_data; |
e6b7991e ADK |
119 | #define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data) |
120 | #else | |
121 | #define EXYNOS4210_TMU_DRV_DATA (NULL) | |
122 | #endif | |
123 | ||
14ddfaec LM |
124 | #if defined(CONFIG_SOC_EXYNOS4412) |
125 | extern struct exynos_tmu_init_data const exynos4412_default_tmu_data; | |
126 | #define EXYNOS4412_TMU_DRV_DATA (&exynos4412_default_tmu_data) | |
127 | #else | |
128 | #define EXYNOS4412_TMU_DRV_DATA (NULL) | |
129 | #endif | |
130 | ||
131 | #if defined(CONFIG_SOC_EXYNOS5250) | |
cebe7373 | 132 | extern struct exynos_tmu_init_data const exynos5250_default_tmu_data; |
e6b7991e ADK |
133 | #define EXYNOS5250_TMU_DRV_DATA (&exynos5250_default_tmu_data) |
134 | #else | |
135 | #define EXYNOS5250_TMU_DRV_DATA (NULL) | |
136 | #endif | |
137 | ||
923488a5 NKC |
138 | #if defined(CONFIG_SOC_EXYNOS5260) |
139 | extern struct exynos_tmu_init_data const exynos5260_default_tmu_data; | |
140 | #define EXYNOS5260_TMU_DRV_DATA (&exynos5260_default_tmu_data) | |
141 | #else | |
142 | #define EXYNOS5260_TMU_DRV_DATA (NULL) | |
143 | #endif | |
144 | ||
14a11dc7 NKC |
145 | #if defined(CONFIG_SOC_EXYNOS5420) |
146 | extern struct exynos_tmu_init_data const exynos5420_default_tmu_data; | |
147 | #define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data) | |
148 | #else | |
149 | #define EXYNOS5420_TMU_DRV_DATA (NULL) | |
150 | #endif | |
151 | ||
90542546 ADK |
152 | #if defined(CONFIG_SOC_EXYNOS5440) |
153 | extern struct exynos_tmu_init_data const exynos5440_default_tmu_data; | |
154 | #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data) | |
155 | #else | |
156 | #define EXYNOS5440_TMU_DRV_DATA (NULL) | |
157 | #endif | |
158 | ||
e6b7991e | 159 | #endif /*_EXYNOS_TMU_DATA_H*/ |