[mirror_ubuntu-hirsute-kernel.git] / drivers / thunderbolt / eeprom.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Thunderbolt driver - eeprom access
 *
 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
 * Copyright (C) 2018, Intel Corporation
 */

#include <linux/crc32.h>
#include <linux/delay.h>
#include <linux/property.h>
#include <linux/slab.h>
#include "tb.h"

/**
 * tb_eeprom_ctl_write() - write control word
 */
static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
{
	return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
}

/**
 * tb_eeprom_ctl_write() - read control word
 */
static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
{
	return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
}

enum tb_eeprom_transfer {
	TB_EEPROM_IN,
	TB_EEPROM_OUT,
};

/**
 * tb_eeprom_active - enable rom access
 *
 * WARNING: Always disable access after usage. Otherwise the controller will
 * fail to reprobe.
 */
static int tb_eeprom_active(struct tb_switch *sw, bool enable)
{
	struct tb_eeprom_ctl ctl;
	int res = tb_eeprom_ctl_read(sw, &ctl);
	if (res)
		return res;
	if (enable) {
		ctl.access_high = 1;
		res = tb_eeprom_ctl_write(sw, &ctl);
		if (res)
			return res;
		ctl.access_low = 0;
		return tb_eeprom_ctl_write(sw, &ctl);
	} else {
		ctl.access_low = 1;
		res = tb_eeprom_ctl_write(sw, &ctl);
		if (res)
			return res;
		ctl.access_high = 0;
		return tb_eeprom_ctl_write(sw, &ctl);
	}
}

/**
 * tb_eeprom_transfer - transfer one bit
 *
 * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
 * If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
 */
static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
			      enum tb_eeprom_transfer direction)
{
	int res;
	if (direction == TB_EEPROM_OUT) {
		res = tb_eeprom_ctl_write(sw, ctl);
		if (res)
			return res;
	}
	ctl->clock = 1;
	res = tb_eeprom_ctl_write(sw, ctl);
	if (res)
		return res;
	if (direction == TB_EEPROM_IN) {
		res = tb_eeprom_ctl_read(sw, ctl);
		if (res)
			return res;
	}
	ctl->clock = 0;
	return tb_eeprom_ctl_write(sw, ctl);
}

/**
 * tb_eeprom_out - write one byte to the bus
 */
static int tb_eeprom_out(struct tb_switch *sw, u8 val)
{
	struct tb_eeprom_ctl ctl;
	int i;
	int res = tb_eeprom_ctl_read(sw, &ctl);
	if (res)
		return res;
	for (i = 0; i < 8; i++) {
		ctl.data_out = val & 0x80;
		res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
		if (res)
			return res;
		val <<= 1;
	}
	return 0;
}

/**
 * tb_eeprom_in - read one byte from the bus
 */
static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
{
	struct tb_eeprom_ctl ctl;
	int i;
	int res = tb_eeprom_ctl_read(sw, &ctl);
	if (res)
		return res;
	*val = 0;
	for (i = 0; i < 8; i++) {
		*val <<= 1;
		res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
		if (res)
			return res;
		*val |= ctl.data_in;
	}
	return 0;
}

/**
 * tb_eeprom_get_drom_offset - get drom offset within eeprom
 */
static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
{
	struct tb_cap_plug_events cap;
	int res;

	if (!sw->cap_plug_events) {
		tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
		return -ENODEV;
	}
	res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
			     sizeof(cap) / 4);
	if (res)
		return res;

	if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
		tb_sw_warn(sw, "no NVM\n");
		return -ENODEV;
	}

	if (cap.drom_offset > 0xffff) {
		tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
				cap.drom_offset);
		return -ENXIO;
	}
	*offset = cap.drom_offset;
	return 0;
}

/**
 * tb_eeprom_read_n - read count bytes from offset into val
 */
static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
		size_t count)
{
	u16 drom_offset;
	int i, res;

	res = tb_eeprom_get_drom_offset(sw, &drom_offset);
	if (res)
		return res;

	offset += drom_offset;

	res = tb_eeprom_active(sw, true);
	if (res)
		return res;
	res = tb_eeprom_out(sw, 3);
	if (res)
		return res;
	res = tb_eeprom_out(sw, offset >> 8);
	if (res)
		return res;
	res = tb_eeprom_out(sw, offset);
	if (res)
		return res;
	for (i = 0; i < count; i++) {
		res = tb_eeprom_in(sw, val + i);
		if (res)
			return res;
	}
	return tb_eeprom_active(sw, false);
}

static u8 tb_crc8(u8 *data, int len)
{
	int i, j;
	u8 val = 0xff;
	for (i = 0; i < len; i++) {
		val ^= data[i];
		for (j = 0; j < 8; j++)
			val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
	}
	return val;
}

static u32 tb_crc32(void *data, size_t len)
{
	return ~__crc32c_le(~0, data, len);
}

#define TB_DROM_DATA_START 13
struct tb_drom_header {
	/* BYTE 0 */
	u8 uid_crc8; /* checksum for uid */
	/* BYTES 1-8 */
	u64 uid;
	/* BYTES 9-12 */
	u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
	/* BYTE 13 */
	u8 device_rom_revision; /* should be <= 1 */
	u16 data_len:10;
	u8 __unknown1:6;
	/* BYTES 16-21 */
	u16 vendor_id;
	u16 model_id;
	u8 model_rev;
	u8 eeprom_rev;
} __packed;

enum tb_drom_entry_type {
	/* force unsigned to prevent "one-bit signed bitfield" warning */
	TB_DROM_ENTRY_GENERIC = 0U,
	TB_DROM_ENTRY_PORT,
};

struct tb_drom_entry_header {
	u8 len;
	u8 index:6;
	bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
	enum tb_drom_entry_type type:1;
} __packed;

struct tb_drom_entry_generic {
	struct tb_drom_entry_header header;
	u8 data[];
} __packed;

struct tb_drom_entry_port {
	/* BYTES 0-1 */
	struct tb_drom_entry_header header;
	/* BYTE 2 */
	u8 dual_link_port_rid:4;
	u8 link_nr:1;
	u8 unknown1:2;
	bool has_dual_link_port:1;

	/* BYTE 3 */
	u8 dual_link_port_nr:6;
	u8 unknown2:2;

	/* BYTES 4 - 5 TODO decode */
	u8 micro2:4;
	u8 micro1:4;
	u8 micro3;

	/* BYTES 6-7, TODO: verify (find hardware that has these set) */
	u8 peer_port_rid:4;
	u8 unknown3:3;
	bool has_peer_port:1;
	u8 peer_port_nr:6;
	u8 unknown4:2;
} __packed;


/**
 * tb_drom_read_uid_only - read uid directly from drom
 *
 * Does not use the cached copy in sw->drom. Used during resume to check switch
 * identity.
 */
int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
{
	u8 data[9];
	u8 crc;
	int res;

	/* read uid */
	res = tb_eeprom_read_n(sw, 0, data, 9);
	if (res)
		return res;

	crc = tb_crc8(data + 1, 8);
	if (crc != data[0]) {
		tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n",
				data[0], crc);
		return -EIO;
	}

	*uid = *(u64 *)(data+1);
	return 0;
}

static int tb_drom_parse_entry_generic(struct tb_switch *sw,
		struct tb_drom_entry_header *header)
{
	const struct tb_drom_entry_generic *entry =
		(const struct tb_drom_entry_generic *)header;

	switch (header->index) {
	case 1:
		/* Length includes 2 bytes header so remove it before copy */
		sw->vendor_name = kstrndup(entry->data,
			header->len - sizeof(*header), GFP_KERNEL);
		if (!sw->vendor_name)
			return -ENOMEM;
		break;

	case 2:
		sw->device_name = kstrndup(entry->data,
			header->len - sizeof(*header), GFP_KERNEL);
		if (!sw->device_name)
			return -ENOMEM;
		break;
	}

	return 0;
}

static int tb_drom_parse_entry_port(struct tb_switch *sw,
				    struct tb_drom_entry_header *header)
{
	struct tb_port *port;
	int res;
	enum tb_port_type type;

	/*
	 * Some DROMs list more ports than the controller actually has
	 * so we skip those but allow the parser to continue.
	 */
	if (header->index > sw->config.max_port_number) {
		dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n");
		return 0;
	}

	port = &sw->ports[header->index];
	port->disabled = header->port_disabled;
	if (port->disabled)
		return 0;

	res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
	if (res)
		return res;
	type &= 0xffffff;

	if (type == TB_TYPE_PORT) {
		struct tb_drom_entry_port *entry = (void *) header;
		if (header->len != sizeof(*entry)) {
			tb_sw_warn(sw,
				"port entry has size %#x (expected %#zx)\n",
				header->len, sizeof(struct tb_drom_entry_port));
			return -EIO;
		}
		port->link_nr = entry->link_nr;
		if (entry->has_dual_link_port)
			port->dual_link_port =
				&port->sw->ports[entry->dual_link_port_nr];
	}
	return 0;
}

/**
 * tb_drom_parse_entries - parse the linked list of drom entries
 *
 * Drom must have been copied to sw->drom.
 */
static int tb_drom_parse_entries(struct tb_switch *sw)
{
	struct tb_drom_header *header = (void *) sw->drom;
	u16 pos = sizeof(*header);
	u16 drom_size = header->data_len + TB_DROM_DATA_START;
	int res;

	while (pos < drom_size) {
		struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
		if (pos + 1 == drom_size || pos + entry->len > drom_size
				|| !entry->len) {
			tb_sw_warn(sw, "DROM buffer overrun\n");
			return -EILSEQ;
		}

		switch (entry->type) {
		case TB_DROM_ENTRY_GENERIC:
			res = tb_drom_parse_entry_generic(sw, entry);
			break;
		case TB_DROM_ENTRY_PORT:
			res = tb_drom_parse_entry_port(sw, entry);
			break;
		}
		if (res)
			return res;

		pos += entry->len;
	}
	return 0;
}

/**
 * tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
 */
static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size)
{
	struct device *dev = &sw->tb->nhi->pdev->dev;
	int len, res;

	len = device_property_count_u8(dev, "ThunderboltDROM");
	if (len < 0 || len < sizeof(struct tb_drom_header))
		return -EINVAL;

	sw->drom = kmalloc(len, GFP_KERNEL);
	if (!sw->drom)
		return -ENOMEM;

	res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
									len);
	if (res)
		goto err;

	*size = ((struct tb_drom_header *)sw->drom)->data_len +
							  TB_DROM_DATA_START;
	if (*size > len)
		goto err;

	return 0;

err:
	kfree(sw->drom);
	sw->drom = NULL;
	return -EINVAL;
}

static int tb_drom_copy_nvm(struct tb_switch *sw, u16 *size)
{
	u32 drom_offset;
	int ret;

	if (!sw->dma_port)
		return -ENODEV;

	ret = tb_sw_read(sw, &drom_offset, TB_CFG_SWITCH,
			 sw->cap_plug_events + 12, 1);
	if (ret)
		return ret;

	if (!drom_offset)
		return -ENODEV;

	ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size,
				  sizeof(*size));
	if (ret)
		return ret;

	/* Size includes CRC8 + UID + CRC32 */
	*size += 1 + 8 + 4;
	sw->drom = kzalloc(*size, GFP_KERNEL);
	if (!sw->drom)
		return -ENOMEM;

	ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size);
	if (ret)
		goto err_free;

	/*
	 * Read UID from the minimal DROM because the one in NVM is just
	 * a placeholder.
	 */
	tb_drom_read_uid_only(sw, &sw->uid);
	return 0;

err_free:
	kfree(sw->drom);
	sw->drom = NULL;
	return ret;
}

static int usb4_copy_host_drom(struct tb_switch *sw, u16 *size)
{
	int ret;

	ret = usb4_switch_drom_read(sw, 14, size, sizeof(*size));
	if (ret)
		return ret;

	/* Size includes CRC8 + UID + CRC32 */
	*size += 1 + 8 + 4;
	sw->drom = kzalloc(*size, GFP_KERNEL);
	if (!sw->drom)
		return -ENOMEM;

	ret = usb4_switch_drom_read(sw, 0, sw->drom, *size);
	if (ret) {
		kfree(sw->drom);
		sw->drom = NULL;
	}

	return ret;
}

static int tb_drom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
			  size_t count)
{
	if (tb_switch_is_usb4(sw))
		return usb4_switch_drom_read(sw, offset, val, count);
	return tb_eeprom_read_n(sw, offset, val, count);
}

/**
 * tb_drom_read - copy drom to sw->drom and parse it
 */
int tb_drom_read(struct tb_switch *sw)
{
	u16 size;
	u32 crc;
	struct tb_drom_header *header;
	int res, retries = 1;

	if (sw->drom)
		return 0;

	if (tb_route(sw) == 0) {
		/*
		 * Apple's NHI EFI driver supplies a DROM for the root switch
		 * in a device property. Use it if available.
		 */
		if (tb_drom_copy_efi(sw, &size) == 0)
			goto parse;

		/* Non-Apple hardware has the DROM as part of NVM */
		if (tb_drom_copy_nvm(sw, &size) == 0)
			goto parse;

		/*
		 * USB4 hosts may support reading DROM through router
		 * operations.
		 */
		if (tb_switch_is_usb4(sw)) {
			usb4_switch_read_uid(sw, &sw->uid);
			if (!usb4_copy_host_drom(sw, &size))
				goto parse;
		} else {
			/*
			 * The root switch contains only a dummy drom
			 * (header only, no entries). Hardcode the
			 * configuration here.
			 */
			tb_drom_read_uid_only(sw, &sw->uid);
		}

		return 0;
	}

	res = tb_drom_read_n(sw, 14, (u8 *) &size, 2);
	if (res)
		return res;
	size &= 0x3ff;
	size += TB_DROM_DATA_START;
	tb_sw_dbg(sw, "reading drom (length: %#x)\n", size);
	if (size < sizeof(*header)) {
		tb_sw_warn(sw, "drom too small, aborting\n");
		return -EIO;
	}

	sw->drom = kzalloc(size, GFP_KERNEL);
	if (!sw->drom)
		return -ENOMEM;
	res = tb_drom_read_n(sw, 0, sw->drom, size);
	if (res)
		goto err;

parse:
	header = (void *) sw->drom;

	if (header->data_len + TB_DROM_DATA_START != size) {
		tb_sw_warn(sw, "drom size mismatch, aborting\n");
		goto err;
	}

	crc = tb_crc8((u8 *) &header->uid, 8);
	if (crc != header->uid_crc8) {
		tb_sw_warn(sw,
			"drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
			header->uid_crc8, crc);
		goto err;
	}
	if (!sw->uid)
		sw->uid = header->uid;
	sw->vendor = header->vendor_id;
	sw->device = header->model_id;
	tb_check_quirks(sw);

	crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
	if (crc != header->data_crc32) {
		tb_sw_warn(sw,
			"drom data crc32 mismatch (expected: %#x, got: %#x), continuing\n",
			header->data_crc32, crc);
	}

	if (header->device_rom_revision > 2)
		tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
			header->device_rom_revision);

	res = tb_drom_parse_entries(sw);
	/* If the DROM parsing fails, wait a moment and retry once */
	if (res == -EILSEQ && retries--) {
		tb_sw_warn(sw, "parsing DROM failed, retrying\n");
		msleep(100);
		res = tb_drom_read_n(sw, 0, sw->drom, size);
		if (!res)
			goto parse;
	}

	return res;
err:
	kfree(sw->drom);
	sw->drom = NULL;
	return -EIO;

}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
c90553b3	2	/*
15c6784c	3	* Thunderbolt driver - eeprom access
c90553b3 AN	4	*
c90553b3 AN	5	* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
15c6784c	6	* Copyright (C) 2018, Intel Corporation
c90553b3 AN	7	*/
c90553b3 AN	8
cd22e73b	9	#include <linux/crc32.h>
f022ff7b	10	#include <linux/delay.h>
c9cc3aaa	11	#include <linux/property.h>
2b35404e	12	#include <linux/slab.h>
c90553b3 AN	13	#include "tb.h"
	14
	15	/**
	16	* tb_eeprom_ctl_write() - write control word
	17	*/
	18	static int tb_eeprom_ctl_write(struct tb_switch sw, struct tb_eeprom_ctl ctl)
	19	{
	20	return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
	21	}
	22
	23	/**
	24	* tb_eeprom_ctl_write() - read control word
	25	*/
	26	static int tb_eeprom_ctl_read(struct tb_switch sw, struct tb_eeprom_ctl ctl)
	27	{
	28	return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
	29	}
	30
	31	enum tb_eeprom_transfer {
	32	TB_EEPROM_IN,
	33	TB_EEPROM_OUT,
	34	};
	35
	36	/**
	37	* tb_eeprom_active - enable rom access
	38	*
	39	* WARNING: Always disable access after usage. Otherwise the controller will
	40	* fail to reprobe.
	41	*/
	42	static int tb_eeprom_active(struct tb_switch *sw, bool enable)
	43	{
	44	struct tb_eeprom_ctl ctl;
	45	int res = tb_eeprom_ctl_read(sw, &ctl);
	46	if (res)
	47	return res;
	48	if (enable) {
	49	ctl.access_high = 1;
	50	res = tb_eeprom_ctl_write(sw, &ctl);
	51	if (res)
	52	return res;
	53	ctl.access_low = 0;
	54	return tb_eeprom_ctl_write(sw, &ctl);
	55	} else {
	56	ctl.access_low = 1;
	57	res = tb_eeprom_ctl_write(sw, &ctl);
	58	if (res)
	59	return res;
	60	ctl.access_high = 0;
	61	return tb_eeprom_ctl_write(sw, &ctl);
	62	}
	63	}
	64
	65	/**
	66	* tb_eeprom_transfer - transfer one bit
	67	*
	68	* If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
	69	* If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
	70	*/
	71	static int tb_eeprom_transfer(struct tb_switch sw, struct tb_eeprom_ctl ctl,
	72	enum tb_eeprom_transfer direction)
	73	{
	74	int res;
	75	if (direction == TB_EEPROM_OUT) {
	76	res = tb_eeprom_ctl_write(sw, ctl);
77	if (res)
78	return res;
79	}
80	ctl->clock = 1;
81	res = tb_eeprom_ctl_write(sw, ctl);
82	if (res)
83	return res;
84	if (direction == TB_EEPROM_IN) {
85	res = tb_eeprom_ctl_read(sw, ctl);
86	if (res)
87	return res;
88	}
89	ctl->clock = 0;
90	return tb_eeprom_ctl_write(sw, ctl);
91	}
92
93	/**
94	* tb_eeprom_out - write one byte to the bus
95	*/
96	static int tb_eeprom_out(struct tb_switch *sw, u8 val)
97	{
98	struct tb_eeprom_ctl ctl;
99	int i;
100	int res = tb_eeprom_ctl_read(sw, &ctl);
101	if (res)
102	return res;
103	for (i = 0; i < 8; i++) {
104	ctl.data_out = val & 0x80;
105	res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
106	if (res)
107	return res;
108	val <<= 1;
109	}
110	return 0;
111	}
112
113	/**
114	* tb_eeprom_in - read one byte from the bus
115	*/
116	static int tb_eeprom_in(struct tb_switch sw, u8 val)
117	{
118	struct tb_eeprom_ctl ctl;
119	int i;
120	int res = tb_eeprom_ctl_read(sw, &ctl);
121	if (res)
122	return res;
123	*val = 0;
124	for (i = 0; i < 8; i++) {
125	*val <<= 1;
126	res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
127	if (res)
128	return res;
129	*val \|= ctl.data_in;
130	}
131	return 0;
132	}
133
4deb200d MW	134	/**
	135	* tb_eeprom_get_drom_offset - get drom offset within eeprom
	136	*/
	137	static int tb_eeprom_get_drom_offset(struct tb_switch sw, u16 offset)
	138	{
	139	struct tb_cap_plug_events cap;
	140	int res;
	141
	142	if (!sw->cap_plug_events) {
	143	tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
	144	return -ENODEV;
	145	}
	146	res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
	147	sizeof(cap) / 4);
	148	if (res)
	149	return res;
	150
	151	if (!cap.eeprom_ctl.present \|\| cap.eeprom_ctl.not_present) {
	152	tb_sw_warn(sw, "no NVM\n");
	153	return -ENODEV;
	154	}
	155
	156	if (cap.drom_offset > 0xffff) {
	157	tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
	158	cap.drom_offset);
	159	return -ENXIO;
	160	}
	161	*offset = cap.drom_offset;
	162	return 0;
	163	}
	164
c90553b3 AN	165	/**
	166	* tb_eeprom_read_n - read count bytes from offset into val
	167	*/
	168	static int tb_eeprom_read_n(struct tb_switch sw, u16 offset, u8 val,
	169	size_t count)
	170	{
4deb200d	171	u16 drom_offset;
c90553b3	172	int i, res;
4deb200d MW	173
	174	res = tb_eeprom_get_drom_offset(sw, &drom_offset);
	175	if (res)
	176	return res;
	177
	178	offset += drom_offset;
	179
c90553b3 AN	180	res = tb_eeprom_active(sw, true);
	181	if (res)
	182	return res;
	183	res = tb_eeprom_out(sw, 3);
	184	if (res)
	185	return res;
	186	res = tb_eeprom_out(sw, offset >> 8);
	187	if (res)
	188	return res;
	189	res = tb_eeprom_out(sw, offset);
	190	if (res)
	191	return res;
	192	for (i = 0; i < count; i++) {
	193	res = tb_eeprom_in(sw, val + i);
	194	if (res)
	195	return res;
	196	}
	197	return tb_eeprom_active(sw, false);
	198	}
	199
cd22e73b AN	200	static u8 tb_crc8(u8 *data, int len)
	201	{
	202	int i, j;
	203	u8 val = 0xff;
	204	for (i = 0; i < len; i++) {
	205	val ^= data[i];
	206	for (j = 0; j < 8; j++)
	207	val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
	208	}
	209	return val;
	210	}
	211
	212	static u32 tb_crc32(void *data, size_t len)
	213	{
	214	return ~__crc32c_le(~0, data, len);
	215	}
	216
	217	#define TB_DROM_DATA_START 13
	218	struct tb_drom_header {
	219	/* BYTE 0 */
	220	u8 uid_crc8; /* checksum for uid */
	221	/* BYTES 1-8 */
	222	u64 uid;
	223	/* BYTES 9-12 */
	224	u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
	225	/* BYTE 13 */
	226	u8 device_rom_revision; /* should be <= 1 */
	227	u16 data_len:10;
	228	u8 __unknown1:6;
	229	/* BYTES 16-21 */
	230	u16 vendor_id;
	231	u16 model_id;
	232	u8 model_rev;
	233	u8 eeprom_rev;
	234	} __packed;
	235
	236	enum tb_drom_entry_type {
e7120778 AN	237	/* force unsigned to prevent "one-bit signed bitfield" warning */
e7120778 AN	238	TB_DROM_ENTRY_GENERIC = 0U,
cd22e73b AN	239	TB_DROM_ENTRY_PORT,
	240	};
	241
	242	struct tb_drom_entry_header {
	243	u8 len;
	244	u8 index:6;
	245	bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
	246	enum tb_drom_entry_type type:1;
	247	} __packed;
	248
72ee3390 MW	249	struct tb_drom_entry_generic {
72ee3390 MW	250	struct tb_drom_entry_header header;
c2a9fca1	251	u8 data[];
72ee3390 MW	252	} __packed;
72ee3390 MW	253
cd22e73b AN	254	struct tb_drom_entry_port {
	255	/* BYTES 0-1 */
	256	struct tb_drom_entry_header header;
	257	/* BYTE 2 */
	258	u8 dual_link_port_rid:4;
	259	u8 link_nr:1;
	260	u8 unknown1:2;
	261	bool has_dual_link_port:1;
	262
	263	/* BYTE 3 */
	264	u8 dual_link_port_nr:6;
	265	u8 unknown2:2;
	266
	267	/* BYTES 4 - 5 TODO decode */
	268	u8 micro2:4;
	269	u8 micro1:4;
	270	u8 micro3;
	271
aae20bb6	272	/* BYTES 6-7, TODO: verify (find hardware that has these set) */
cd22e73b AN	273	u8 peer_port_rid:4;
	274	u8 unknown3:3;
	275	bool has_peer_port:1;
	276	u8 peer_port_nr:6;
	277	u8 unknown4:2;
	278	} __packed;
	279
	280
cd22e73b AN	281	/**
	282	* tb_drom_read_uid_only - read uid directly from drom
	283	*
	284	* Does not use the cached copy in sw->drom. Used during resume to check switch
	285	* identity.
	286	*/
	287	int tb_drom_read_uid_only(struct tb_switch sw, u64 uid)
	288	{
	289	u8 data[9];
cd22e73b	290	u8 crc;
4deb200d	291	int res;
df1421b5	292
c90553b3	293	/* read uid */
4deb200d	294	res = tb_eeprom_read_n(sw, 0, data, 9);
c90553b3 AN	295	if (res)
c90553b3 AN	296	return res;
cd22e73b AN	297
	298	crc = tb_crc8(data + 1, 8);
	299	if (crc != data[0]) {
eb7bfcce	300	tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n",
cd22e73b AN	301	data[0], crc);
	302	return -EIO;
	303	}
	304
c90553b3 AN	305	uid = (u64 *)(data+1);
	306	return 0;
	307	}
	308
72ee3390 MW	309	static int tb_drom_parse_entry_generic(struct tb_switch *sw,
	310	struct tb_drom_entry_header *header)
	311	{
	312	const struct tb_drom_entry_generic *entry =
	313	(const struct tb_drom_entry_generic *)header;
	314
	315	switch (header->index) {
	316	case 1:
	317	/* Length includes 2 bytes header so remove it before copy */
	318	sw->vendor_name = kstrndup(entry->data,
	319	header->len - sizeof(*header), GFP_KERNEL);
	320	if (!sw->vendor_name)
	321	return -ENOMEM;
	322	break;
	323
	324	case 2:
	325	sw->device_name = kstrndup(entry->data,
	326	header->len - sizeof(*header), GFP_KERNEL);
	327	if (!sw->device_name)
	328	return -ENOMEM;
	329	break;
	330	}
	331
	332	return 0;
	333	}
	334
02b17a41 LW	335	static int tb_drom_parse_entry_port(struct tb_switch *sw,
02b17a41 LW	336	struct tb_drom_entry_header *header)
cd22e73b AN	337	{
	338	struct tb_port *port;
	339	int res;
	340	enum tb_port_type type;
c90553b3	341
1cd65d17 MW	342	/*
	343	* Some DROMs list more ports than the controller actually has
	344	* so we skip those but allow the parser to continue.
	345	*/
	346	if (header->index > sw->config.max_port_number) {
	347	dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n");
	348	return 0;
	349	}
	350
cd22e73b AN	351	port = &sw->ports[header->index];
	352	port->disabled = header->port_disabled;
	353	if (port->disabled)
	354	return 0;
	355
	356	res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
	357	if (res)
	358	return res;
	359	type &= 0xffffff;
	360
	361	if (type == TB_TYPE_PORT) {
	362	struct tb_drom_entry_port entry = (void ) header;
	363	if (header->len != sizeof(*entry)) {
	364	tb_sw_warn(sw,
3543fb77	365	"port entry has size %#x (expected %#zx)\n",
cd22e73b AN	366	header->len, sizeof(struct tb_drom_entry_port));
	367	return -EIO;
	368	}
02b17a41 LW	369	port->link_nr = entry->link_nr;
	370	if (entry->has_dual_link_port)
	371	port->dual_link_port =
	372	&port->sw->ports[entry->dual_link_port_nr];
cd22e73b AN	373	}
	374	return 0;
	375	}
	376
	377	/**
	378	* tb_drom_parse_entries - parse the linked list of drom entries
	379	*
	380	* Drom must have been copied to sw->drom.
	381	*/
	382	static int tb_drom_parse_entries(struct tb_switch *sw)
	383	{
	384	struct tb_drom_header header = (void ) sw->drom;
	385	u16 pos = sizeof(*header);
	386	u16 drom_size = header->data_len + TB_DROM_DATA_START;
02b17a41	387	int res;
cd22e73b AN	388
	389	while (pos < drom_size) {
	390	struct tb_drom_entry_header entry = (void ) (sw->drom + pos);
	391	if (pos + 1 == drom_size \|\| pos + entry->len > drom_size
	392	\|\| !entry->len) {
f022ff7b MW	393	tb_sw_warn(sw, "DROM buffer overrun\n");
f022ff7b MW	394	return -EILSEQ;
cd22e73b AN	395	}
cd22e73b AN	396
02b17a41 LW	397	switch (entry->type) {
02b17a41 LW	398	case TB_DROM_ENTRY_GENERIC:
72ee3390	399	res = tb_drom_parse_entry_generic(sw, entry);
02b17a41 LW	400	break;
	401	case TB_DROM_ENTRY_PORT:
	402	res = tb_drom_parse_entry_port(sw, entry);
	403	break;
	404	}
	405	if (res)
	406	return res;
cd22e73b AN	407
	408	pos += entry->len;
	409	}
	410	return 0;
	411	}
	412
c9cc3aaa LW	413	/**
	414	* tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
	415	*/
	416	static int tb_drom_copy_efi(struct tb_switch sw, u16 size)
	417	{
	418	struct device *dev = &sw->tb->nhi->pdev->dev;
	419	int len, res;
	420
100c12f2	421	len = device_property_count_u8(dev, "ThunderboltDROM");
c9cc3aaa LW	422	if (len < 0 \|\| len < sizeof(struct tb_drom_header))
	423	return -EINVAL;
	424
	425	sw->drom = kmalloc(len, GFP_KERNEL);
	426	if (!sw->drom)
	427	return -ENOMEM;
	428
	429	res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
	430	len);
	431	if (res)
	432	goto err;
	433
	434	size = ((struct tb_drom_header )sw->drom)->data_len +
	435	TB_DROM_DATA_START;
	436	if (*size > len)
	437	goto err;
	438
	439	return 0;
	440
	441	err:
	442	kfree(sw->drom);
	443	sw->drom = NULL;
	444	return -EINVAL;
	445	}
	446
3e136768 MW	447	static int tb_drom_copy_nvm(struct tb_switch sw, u16 size)
	448	{
	449	u32 drom_offset;
	450	int ret;
	451
	452	if (!sw->dma_port)
	453	return -ENODEV;
	454
	455	ret = tb_sw_read(sw, &drom_offset, TB_CFG_SWITCH,
	456	sw->cap_plug_events + 12, 1);
	457	if (ret)
	458	return ret;
	459
	460	if (!drom_offset)
	461	return -ENODEV;
	462
	463	ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size,
	464	sizeof(*size));
	465	if (ret)
	466	return ret;
	467
	468	/* Size includes CRC8 + UID + CRC32 */
	469	*size += 1 + 8 + 4;
	470	sw->drom = kzalloc(*size, GFP_KERNEL);
	471	if (!sw->drom)
	472	return -ENOMEM;
	473
	474	ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size);
	475	if (ret)
	476	goto err_free;
	477
	478	/*
	479	* Read UID from the minimal DROM because the one in NVM is just
	480	* a placeholder.
	481	*/
	482	tb_drom_read_uid_only(sw, &sw->uid);
	483	return 0;
	484
	485	err_free:
	486	kfree(sw->drom);
	487	sw->drom = NULL;
	488	return ret;
	489	}
	490
b0407983 MW	491	static int usb4_copy_host_drom(struct tb_switch sw, u16 size)
	492	{
	493	int ret;
	494
	495	ret = usb4_switch_drom_read(sw, 14, size, sizeof(*size));
	496	if (ret)
	497	return ret;
	498
	499	/* Size includes CRC8 + UID + CRC32 */
	500	*size += 1 + 8 + 4;
	501	sw->drom = kzalloc(*size, GFP_KERNEL);
	502	if (!sw->drom)
	503	return -ENOMEM;
	504
	505	ret = usb4_switch_drom_read(sw, 0, sw->drom, *size);
	506	if (ret) {
	507	kfree(sw->drom);
	508	sw->drom = NULL;
	509	}
	510
	511	return ret;
	512	}
	513
	514	static int tb_drom_read_n(struct tb_switch sw, u16 offset, u8 val,
	515	size_t count)
	516	{
	517	if (tb_switch_is_usb4(sw))
	518	return usb4_switch_drom_read(sw, offset, val, count);
	519	return tb_eeprom_read_n(sw, offset, val, count);
	520	}
	521
cd22e73b AN	522	/**
	523	* tb_drom_read - copy drom to sw->drom and parse it
	524	*/
	525	int tb_drom_read(struct tb_switch *sw)
	526	{
cd22e73b AN	527	u16 size;
	528	u32 crc;
	529	struct tb_drom_header *header;
f022ff7b MW	530	int res, retries = 1;
f022ff7b MW	531
cd22e73b AN	532	if (sw->drom)
	533	return 0;
	534
	535	if (tb_route(sw) == 0) {
c9cc3aaa LW	536	/*
	537	* Apple's NHI EFI driver supplies a DROM for the root switch
	538	* in a device property. Use it if available.
	539	*/
	540	if (tb_drom_copy_efi(sw, &size) == 0)
	541	goto parse;
	542
3e136768 MW	543	/* Non-Apple hardware has the DROM as part of NVM */
	544	if (tb_drom_copy_nvm(sw, &size) == 0)
	545	goto parse;
	546
cd22e73b	547	/*
b0407983 MW	548	* USB4 hosts may support reading DROM through router
b0407983 MW	549	* operations.
cd22e73b	550	*/
b0407983 MW	551	if (tb_switch_is_usb4(sw)) {
	552	usb4_switch_read_uid(sw, &sw->uid);
	553	if (!usb4_copy_host_drom(sw, &size))
	554	goto parse;
	555	} else {
	556	/*
	557	* The root switch contains only a dummy drom
	558	* (header only, no entries). Hardcode the
	559	* configuration here.
	560	*/
	561	tb_drom_read_uid_only(sw, &sw->uid);
	562	}
	563
cd22e73b AN	564	return 0;
	565	}
	566
b0407983	567	res = tb_drom_read_n(sw, 14, (u8 *) &size, 2);
cd22e73b AN	568	if (res)
	569	return res;
	570	size &= 0x3ff;
	571	size += TB_DROM_DATA_START;
daa5140f	572	tb_sw_dbg(sw, "reading drom (length: %#x)\n", size);
cd22e73b AN	573	if (size < sizeof(*header)) {
	574	tb_sw_warn(sw, "drom too small, aborting\n");
	575	return -EIO;
	576	}
	577
	578	sw->drom = kzalloc(size, GFP_KERNEL);
	579	if (!sw->drom)
	580	return -ENOMEM;
b0407983	581	res = tb_drom_read_n(sw, 0, sw->drom, size);
cd22e73b AN	582	if (res)
	583	goto err;
	584
c9cc3aaa	585	parse:
cd22e73b AN	586	header = (void *) sw->drom;
	587
	588	if (header->data_len + TB_DROM_DATA_START != size) {
	589	tb_sw_warn(sw, "drom size mismatch, aborting\n");
	590	goto err;
	591	}
	592
	593	crc = tb_crc8((u8 *) &header->uid, 8);
	594	if (crc != header->uid_crc8) {
	595	tb_sw_warn(sw,
	596	"drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
	597	header->uid_crc8, crc);
	598	goto err;
	599	}
3e136768 MW	600	if (!sw->uid)
3e136768 MW	601	sw->uid = header->uid;
bfe778ac MW	602	sw->vendor = header->vendor_id;
bfe778ac MW	603	sw->device = header->model_id;
1cb36293	604	tb_check_quirks(sw);
cd22e73b AN	605
	606	crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
	607	if (crc != header->data_crc32) {
	608	tb_sw_warn(sw,
39022945	609	"drom data crc32 mismatch (expected: %#x, got: %#x), continuing\n",
cd22e73b	610	header->data_crc32, crc);
cd22e73b AN	611	}
cd22e73b AN	612
b2466355	613	if (header->device_rom_revision > 2)
cd22e73b AN	614	tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
	615	header->device_rom_revision);
	616
f022ff7b MW	617	res = tb_drom_parse_entries(sw);
	618	/* If the DROM parsing fails, wait a moment and retry once */
	619	if (res == -EILSEQ && retries--) {
	620	tb_sw_warn(sw, "parsing DROM failed, retrying\n");
	621	msleep(100);
	622	res = tb_drom_read_n(sw, 0, sw->drom, size);
	623	if (!res)
	624	goto parse;
	625	}
	626
	627	return res;
cd22e73b AN	628	err:
cd22e73b AN	629	kfree(sw->drom);
2ffa9a5d	630	sw->drom = NULL;
cd22e73b AN	631	return -EIO;
	632
	633	}