[mirror_ubuntu-jammy-kernel.git] / drivers / thunderbolt / eeprom.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Thunderbolt driver - eeprom access
 *
 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
 * Copyright (C) 2018, Intel Corporation
 */

#include <linux/crc32.h>
#include <linux/delay.h>
#include <linux/property.h>
#include <linux/slab.h>
#include "tb.h"

/*
 * tb_eeprom_ctl_write() - write control word
 */
static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
{
	return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
}

/*
 * tb_eeprom_ctl_write() - read control word
 */
static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
{
	return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
}

enum tb_eeprom_transfer {
	TB_EEPROM_IN,
	TB_EEPROM_OUT,
};

/*
 * tb_eeprom_active - enable rom access
 *
 * WARNING: Always disable access after usage. Otherwise the controller will
 * fail to reprobe.
 */
static int tb_eeprom_active(struct tb_switch *sw, bool enable)
{
	struct tb_eeprom_ctl ctl;
	int res = tb_eeprom_ctl_read(sw, &ctl);
	if (res)
		return res;
	if (enable) {
		ctl.access_high = 1;
		res = tb_eeprom_ctl_write(sw, &ctl);
		if (res)
			return res;
		ctl.access_low = 0;
		return tb_eeprom_ctl_write(sw, &ctl);
	} else {
		ctl.access_low = 1;
		res = tb_eeprom_ctl_write(sw, &ctl);
		if (res)
			return res;
		ctl.access_high = 0;
		return tb_eeprom_ctl_write(sw, &ctl);
	}
}

/*
 * tb_eeprom_transfer - transfer one bit
 *
 * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
 * If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
 */
static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
			      enum tb_eeprom_transfer direction)
{
	int res;
	if (direction == TB_EEPROM_OUT) {
		res = tb_eeprom_ctl_write(sw, ctl);
		if (res)
			return res;
	}
	ctl->clock = 1;
	res = tb_eeprom_ctl_write(sw, ctl);
	if (res)
		return res;
	if (direction == TB_EEPROM_IN) {
		res = tb_eeprom_ctl_read(sw, ctl);
		if (res)
			return res;
	}
	ctl->clock = 0;
	return tb_eeprom_ctl_write(sw, ctl);
}

/*
 * tb_eeprom_out - write one byte to the bus
 */
static int tb_eeprom_out(struct tb_switch *sw, u8 val)
{
	struct tb_eeprom_ctl ctl;
	int i;
	int res = tb_eeprom_ctl_read(sw, &ctl);
	if (res)
		return res;
	for (i = 0; i < 8; i++) {
		ctl.data_out = val & 0x80;
		res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
		if (res)
			return res;
		val <<= 1;
	}
	return 0;
}

/*
 * tb_eeprom_in - read one byte from the bus
 */
static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
{
	struct tb_eeprom_ctl ctl;
	int i;
	int res = tb_eeprom_ctl_read(sw, &ctl);
	if (res)
		return res;
	*val = 0;
	for (i = 0; i < 8; i++) {
		*val <<= 1;
		res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
		if (res)
			return res;
		*val |= ctl.data_in;
	}
	return 0;
}

/*
 * tb_eeprom_get_drom_offset - get drom offset within eeprom
 */
static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
{
	struct tb_cap_plug_events cap;
	int res;

	if (!sw->cap_plug_events) {
		tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
		return -ENODEV;
	}
	res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
			     sizeof(cap) / 4);
	if (res)
		return res;

	if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
		tb_sw_warn(sw, "no NVM\n");
		return -ENODEV;
	}

	if (cap.drom_offset > 0xffff) {
		tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
				cap.drom_offset);
		return -ENXIO;
	}
	*offset = cap.drom_offset;
	return 0;
}

/*
 * tb_eeprom_read_n - read count bytes from offset into val
 */
static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
		size_t count)
{
	u16 drom_offset;
	int i, res;

	res = tb_eeprom_get_drom_offset(sw, &drom_offset);
	if (res)
		return res;

	offset += drom_offset;

	res = tb_eeprom_active(sw, true);
	if (res)
		return res;
	res = tb_eeprom_out(sw, 3);
	if (res)
		return res;
	res = tb_eeprom_out(sw, offset >> 8);
	if (res)
		return res;
	res = tb_eeprom_out(sw, offset);
	if (res)
		return res;
	for (i = 0; i < count; i++) {
		res = tb_eeprom_in(sw, val + i);
		if (res)
			return res;
	}
	return tb_eeprom_active(sw, false);
}

static u8 tb_crc8(u8 *data, int len)
{
	int i, j;
	u8 val = 0xff;
	for (i = 0; i < len; i++) {
		val ^= data[i];
		for (j = 0; j < 8; j++)
			val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
	}
	return val;
}

static u32 tb_crc32(void *data, size_t len)
{
	return ~__crc32c_le(~0, data, len);
}

#define TB_DROM_DATA_START		13
#define TB_DROM_HEADER_SIZE		22
#define USB4_DROM_HEADER_SIZE		16

struct tb_drom_header {
	/* BYTE 0 */
	u8 uid_crc8; /* checksum for uid */
	/* BYTES 1-8 */
	u64 uid;
	/* BYTES 9-12 */
	u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
	/* BYTE 13 */
	u8 device_rom_revision; /* should be <= 1 */
	u16 data_len:12;
	u8 reserved:4;
	/* BYTES 16-21 - Only for TBT DROM, nonexistent in USB4 DROM */
	u16 vendor_id;
	u16 model_id;
	u8 model_rev;
	u8 eeprom_rev;
} __packed;

enum tb_drom_entry_type {
	/* force unsigned to prevent "one-bit signed bitfield" warning */
	TB_DROM_ENTRY_GENERIC = 0U,
	TB_DROM_ENTRY_PORT,
};

struct tb_drom_entry_header {
	u8 len;
	u8 index:6;
	bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
	enum tb_drom_entry_type type:1;
} __packed;

struct tb_drom_entry_generic {
	struct tb_drom_entry_header header;
	u8 data[];
} __packed;

struct tb_drom_entry_port {
	/* BYTES 0-1 */
	struct tb_drom_entry_header header;
	/* BYTE 2 */
	u8 dual_link_port_rid:4;
	u8 link_nr:1;
	u8 unknown1:2;
	bool has_dual_link_port:1;

	/* BYTE 3 */
	u8 dual_link_port_nr:6;
	u8 unknown2:2;

	/* BYTES 4 - 5 TODO decode */
	u8 micro2:4;
	u8 micro1:4;
	u8 micro3;

	/* BYTES 6-7, TODO: verify (find hardware that has these set) */
	u8 peer_port_rid:4;
	u8 unknown3:3;
	bool has_peer_port:1;
	u8 peer_port_nr:6;
	u8 unknown4:2;
} __packed;

/* USB4 product descriptor */
struct tb_drom_entry_desc {
	struct tb_drom_entry_header header;
	u16 bcdUSBSpec;
	u16 idVendor;
	u16 idProduct;
	u16 bcdProductFWRevision;
	u32 TID;
	u8 productHWRevision;
};

/**
 * tb_drom_read_uid_only() - Read UID directly from DROM
 * @sw: Router whose UID to read
 * @uid: UID is placed here
 *
 * Does not use the cached copy in sw->drom. Used during resume to check switch
 * identity.
 */
int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
{
	u8 data[9];
	u8 crc;
	int res;

	/* read uid */
	res = tb_eeprom_read_n(sw, 0, data, 9);
	if (res)
		return res;

	crc = tb_crc8(data + 1, 8);
	if (crc != data[0]) {
		tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n",
				data[0], crc);
		return -EIO;
	}

	*uid = *(u64 *)(data+1);
	return 0;
}

static int tb_drom_parse_entry_generic(struct tb_switch *sw,
		struct tb_drom_entry_header *header)
{
	const struct tb_drom_entry_generic *entry =
		(const struct tb_drom_entry_generic *)header;

	switch (header->index) {
	case 1:
		/* Length includes 2 bytes header so remove it before copy */
		sw->vendor_name = kstrndup(entry->data,
			header->len - sizeof(*header), GFP_KERNEL);
		if (!sw->vendor_name)
			return -ENOMEM;
		break;

	case 2:
		sw->device_name = kstrndup(entry->data,
			header->len - sizeof(*header), GFP_KERNEL);
		if (!sw->device_name)
			return -ENOMEM;
		break;
	case 9: {
		const struct tb_drom_entry_desc *desc =
			(const struct tb_drom_entry_desc *)entry;

		if (!sw->vendor && !sw->device) {
			sw->vendor = desc->idVendor;
			sw->device = desc->idProduct;
		}
		break;
	}
	}

	return 0;
}

static int tb_drom_parse_entry_port(struct tb_switch *sw,
				    struct tb_drom_entry_header *header)
{
	struct tb_port *port;
	int res;
	enum tb_port_type type;

	/*
	 * Some DROMs list more ports than the controller actually has
	 * so we skip those but allow the parser to continue.
	 */
	if (header->index > sw->config.max_port_number) {
		dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n");
		return 0;
	}

	port = &sw->ports[header->index];
	port->disabled = header->port_disabled;
	if (port->disabled)
		return 0;

	res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
	if (res)
		return res;
	type &= 0xffffff;

	if (type == TB_TYPE_PORT) {
		struct tb_drom_entry_port *entry = (void *) header;
		if (header->len != sizeof(*entry)) {
			tb_sw_warn(sw,
				"port entry has size %#x (expected %#zx)\n",
				header->len, sizeof(struct tb_drom_entry_port));
			return -EIO;
		}
		port->link_nr = entry->link_nr;
		if (entry->has_dual_link_port)
			port->dual_link_port =
				&port->sw->ports[entry->dual_link_port_nr];
	}
	return 0;
}

/*
 * tb_drom_parse_entries - parse the linked list of drom entries
 *
 * Drom must have been copied to sw->drom.
 */
static int tb_drom_parse_entries(struct tb_switch *sw, size_t header_size)
{
	struct tb_drom_header *header = (void *) sw->drom;
	u16 pos = header_size;
	u16 drom_size = header->data_len + TB_DROM_DATA_START;
	int res;

	while (pos < drom_size) {
		struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
		if (pos + 1 == drom_size || pos + entry->len > drom_size
				|| !entry->len) {
			tb_sw_warn(sw, "DROM buffer overrun\n");
			return -EILSEQ;
		}

		switch (entry->type) {
		case TB_DROM_ENTRY_GENERIC:
			res = tb_drom_parse_entry_generic(sw, entry);
			break;
		case TB_DROM_ENTRY_PORT:
			res = tb_drom_parse_entry_port(sw, entry);
			break;
		}
		if (res)
			return res;

		pos += entry->len;
	}
	return 0;
}

/*
 * tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
 */
static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size)
{
	struct device *dev = &sw->tb->nhi->pdev->dev;
	int len, res;

	len = device_property_count_u8(dev, "ThunderboltDROM");
	if (len < 0 || len < sizeof(struct tb_drom_header))
		return -EINVAL;

	sw->drom = kmalloc(len, GFP_KERNEL);
	if (!sw->drom)
		return -ENOMEM;

	res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
									len);
	if (res)
		goto err;

	*size = ((struct tb_drom_header *)sw->drom)->data_len +
							  TB_DROM_DATA_START;
	if (*size > len)
		goto err;

	return 0;

err:
	kfree(sw->drom);
	sw->drom = NULL;
	return -EINVAL;
}

static int tb_drom_copy_nvm(struct tb_switch *sw, u16 *size)
{
	u32 drom_offset;
	int ret;

	if (!sw->dma_port)
		return -ENODEV;

	ret = tb_sw_read(sw, &drom_offset, TB_CFG_SWITCH,
			 sw->cap_plug_events + 12, 1);
	if (ret)
		return ret;

	if (!drom_offset)
		return -ENODEV;

	ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size,
				  sizeof(*size));
	if (ret)
		return ret;

	/* Size includes CRC8 + UID + CRC32 */
	*size += 1 + 8 + 4;
	sw->drom = kzalloc(*size, GFP_KERNEL);
	if (!sw->drom)
		return -ENOMEM;

	ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size);
	if (ret)
		goto err_free;

	/*
	 * Read UID from the minimal DROM because the one in NVM is just
	 * a placeholder.
	 */
	tb_drom_read_uid_only(sw, &sw->uid);
	return 0;

err_free:
	kfree(sw->drom);
	sw->drom = NULL;
	return ret;
}

static int usb4_copy_host_drom(struct tb_switch *sw, u16 *size)
{
	int ret;

	ret = usb4_switch_drom_read(sw, 14, size, sizeof(*size));
	if (ret)
		return ret;

	/* Size includes CRC8 + UID + CRC32 */
	*size += 1 + 8 + 4;
	sw->drom = kzalloc(*size, GFP_KERNEL);
	if (!sw->drom)
		return -ENOMEM;

	ret = usb4_switch_drom_read(sw, 0, sw->drom, *size);
	if (ret) {
		kfree(sw->drom);
		sw->drom = NULL;
	}

	return ret;
}

static int tb_drom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
			  size_t count)
{
	if (tb_switch_is_usb4(sw))
		return usb4_switch_drom_read(sw, offset, val, count);
	return tb_eeprom_read_n(sw, offset, val, count);
}

static int tb_drom_parse(struct tb_switch *sw)
{
	const struct tb_drom_header *header =
		(const struct tb_drom_header *)sw->drom;
	u32 crc;

	crc = tb_crc8((u8 *) &header->uid, 8);
	if (crc != header->uid_crc8) {
		tb_sw_warn(sw,
			"DROM UID CRC8 mismatch (expected: %#x, got: %#x), aborting\n",
			header->uid_crc8, crc);
		return -EINVAL;
	}
	if (!sw->uid)
		sw->uid = header->uid;
	sw->vendor = header->vendor_id;
	sw->device = header->model_id;

	crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
	if (crc != header->data_crc32) {
		tb_sw_warn(sw,
			"DROM data CRC32 mismatch (expected: %#x, got: %#x), continuing\n",
			header->data_crc32, crc);
	}

	return tb_drom_parse_entries(sw, TB_DROM_HEADER_SIZE);
}

static int usb4_drom_parse(struct tb_switch *sw)
{
	const struct tb_drom_header *header =
		(const struct tb_drom_header *)sw->drom;
	u32 crc;

	crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
	if (crc != header->data_crc32) {
		tb_sw_warn(sw,
			   "DROM data CRC32 mismatch (expected: %#x, got: %#x), aborting\n",
			   header->data_crc32, crc);
		return -EINVAL;
	}

	return tb_drom_parse_entries(sw, USB4_DROM_HEADER_SIZE);
}

/**
 * tb_drom_read() - Copy DROM to sw->drom and parse it
 * @sw: Router whose DROM to read and parse
 *
 * This function reads router DROM and if successful parses the entries and
 * populates the fields in @sw accordingly. Can be called for any router
 * generation.
 *
 * Returns %0 in case of success and negative errno otherwise.
 */
int tb_drom_read(struct tb_switch *sw)
{
	u16 size;
	struct tb_drom_header *header;
	int res, retries = 1;

	if (sw->drom)
		return 0;

	if (tb_route(sw) == 0) {
		/*
		 * Apple's NHI EFI driver supplies a DROM for the root switch
		 * in a device property. Use it if available.
		 */
		if (tb_drom_copy_efi(sw, &size) == 0)
			goto parse;

		/* Non-Apple hardware has the DROM as part of NVM */
		if (tb_drom_copy_nvm(sw, &size) == 0)
			goto parse;

		/*
		 * USB4 hosts may support reading DROM through router
		 * operations.
		 */
		if (tb_switch_is_usb4(sw)) {
			usb4_switch_read_uid(sw, &sw->uid);
			if (!usb4_copy_host_drom(sw, &size))
				goto parse;
		} else {
			/*
			 * The root switch contains only a dummy drom
			 * (header only, no entries). Hardcode the
			 * configuration here.
			 */
			tb_drom_read_uid_only(sw, &sw->uid);
		}

		return 0;
	}

	res = tb_drom_read_n(sw, 14, (u8 *) &size, 2);
	if (res)
		return res;
	size &= 0x3ff;
	size += TB_DROM_DATA_START;
	tb_sw_dbg(sw, "reading drom (length: %#x)\n", size);
	if (size < sizeof(*header)) {
		tb_sw_warn(sw, "drom too small, aborting\n");
		return -EIO;
	}

	sw->drom = kzalloc(size, GFP_KERNEL);
	if (!sw->drom)
		return -ENOMEM;
	res = tb_drom_read_n(sw, 0, sw->drom, size);
	if (res)
		goto err;

parse:
	header = (void *) sw->drom;

	if (header->data_len + TB_DROM_DATA_START != size) {
		tb_sw_warn(sw, "drom size mismatch, aborting\n");
		goto err;
	}

	tb_sw_dbg(sw, "DROM version: %d\n", header->device_rom_revision);

	switch (header->device_rom_revision) {
	case 3:
		res = usb4_drom_parse(sw);
		break;
	default:
		tb_sw_warn(sw, "DROM device_rom_revision %#x unknown\n",
			   header->device_rom_revision);
		fallthrough;
	case 1:
		res = tb_drom_parse(sw);
		break;
	}

	/* If the DROM parsing fails, wait a moment and retry once */
	if (res == -EILSEQ && retries--) {
		tb_sw_warn(sw, "parsing DROM failed, retrying\n");
		msleep(100);
		res = tb_drom_read_n(sw, 0, sw->drom, size);
		if (!res)
			goto parse;
	}

	if (!res)
		return 0;

err:
	kfree(sw->drom);
	sw->drom = NULL;
	return -EIO;
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
c90553b3	2	/*
15c6784c	3	* Thunderbolt driver - eeprom access
c90553b3 AN	4	*
c90553b3 AN	5	* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
15c6784c	6	* Copyright (C) 2018, Intel Corporation
c90553b3 AN	7	*/
c90553b3 AN	8
cd22e73b	9	#include <linux/crc32.h>
f022ff7b	10	#include <linux/delay.h>
c9cc3aaa	11	#include <linux/property.h>
2b35404e	12	#include <linux/slab.h>
c90553b3 AN	13	#include "tb.h"
c90553b3 AN	14
ff48bc44	15	/*
c90553b3 AN	16	* tb_eeprom_ctl_write() - write control word
	17	*/
	18	static int tb_eeprom_ctl_write(struct tb_switch sw, struct tb_eeprom_ctl ctl)
	19	{
	20	return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
	21	}
	22
ff48bc44	23	/*
c90553b3 AN	24	* tb_eeprom_ctl_write() - read control word
	25	*/
	26	static int tb_eeprom_ctl_read(struct tb_switch sw, struct tb_eeprom_ctl ctl)
	27	{
	28	return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
	29	}
	30
	31	enum tb_eeprom_transfer {
	32	TB_EEPROM_IN,
	33	TB_EEPROM_OUT,
	34	};
	35
ff48bc44	36	/*
c90553b3 AN	37	* tb_eeprom_active - enable rom access
	38	*
	39	* WARNING: Always disable access after usage. Otherwise the controller will
	40	* fail to reprobe.
	41	*/
	42	static int tb_eeprom_active(struct tb_switch *sw, bool enable)
	43	{
	44	struct tb_eeprom_ctl ctl;
	45	int res = tb_eeprom_ctl_read(sw, &ctl);
	46	if (res)
	47	return res;
	48	if (enable) {
	49	ctl.access_high = 1;
	50	res = tb_eeprom_ctl_write(sw, &ctl);
	51	if (res)
	52	return res;
	53	ctl.access_low = 0;
	54	return tb_eeprom_ctl_write(sw, &ctl);
	55	} else {
	56	ctl.access_low = 1;
	57	res = tb_eeprom_ctl_write(sw, &ctl);
	58	if (res)
	59	return res;
	60	ctl.access_high = 0;
	61	return tb_eeprom_ctl_write(sw, &ctl);
	62	}
	63	}
	64
ff48bc44	65	/*
c90553b3 AN	66	* tb_eeprom_transfer - transfer one bit
	67	*
	68	* If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
	69	* If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
	70	*/
	71	static int tb_eeprom_transfer(struct tb_switch sw, struct tb_eeprom_ctl ctl,
	72	enum tb_eeprom_transfer direction)
	73	{
	74	int res;
	75	if (direction == TB_EEPROM_OUT) {
	76	res = tb_eeprom_ctl_write(sw, ctl);
	77	if (res)
	78	return res;
	79	}
	80	ctl->clock = 1;
	81	res = tb_eeprom_ctl_write(sw, ctl);
	82	if (res)
	83	return res;
	84	if (direction == TB_EEPROM_IN) {
	85	res = tb_eeprom_ctl_read(sw, ctl);
	86	if (res)
	87	return res;
	88	}
	89	ctl->clock = 0;
	90	return tb_eeprom_ctl_write(sw, ctl);
	91	}
	92
ff48bc44	93	/*
c90553b3 AN	94	* tb_eeprom_out - write one byte to the bus
	95	*/
	96	static int tb_eeprom_out(struct tb_switch *sw, u8 val)
	97	{
	98	struct tb_eeprom_ctl ctl;
	99	int i;
	100	int res = tb_eeprom_ctl_read(sw, &ctl);
	101	if (res)
	102	return res;
	103	for (i = 0; i < 8; i++) {
	104	ctl.data_out = val & 0x80;
	105	res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
	106	if (res)
	107	return res;
	108	val <<= 1;
	109	}
	110	return 0;
	111	}
	112
ff48bc44	113	/*
c90553b3 AN	114	* tb_eeprom_in - read one byte from the bus
	115	*/
	116	static int tb_eeprom_in(struct tb_switch sw, u8 val)
	117	{
	118	struct tb_eeprom_ctl ctl;
	119	int i;
	120	int res = tb_eeprom_ctl_read(sw, &ctl);
	121	if (res)
	122	return res;
	123	*val = 0;
	124	for (i = 0; i < 8; i++) {
	125	*val <<= 1;
	126	res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
	127	if (res)
	128	return res;
	129	*val \|= ctl.data_in;
	130	}
	131	return 0;
	132	}
	133
ff48bc44	134	/*
4deb200d MW	135	* tb_eeprom_get_drom_offset - get drom offset within eeprom
	136	*/
	137	static int tb_eeprom_get_drom_offset(struct tb_switch sw, u16 offset)
	138	{
	139	struct tb_cap_plug_events cap;
	140	int res;
	141
	142	if (!sw->cap_plug_events) {
	143	tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
	144	return -ENODEV;
	145	}
	146	res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
	147	sizeof(cap) / 4);
	148	if (res)
	149	return res;
	150
	151	if (!cap.eeprom_ctl.present \|\| cap.eeprom_ctl.not_present) {
	152	tb_sw_warn(sw, "no NVM\n");
	153	return -ENODEV;
	154	}
	155
	156	if (cap.drom_offset > 0xffff) {
	157	tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
	158	cap.drom_offset);
	159	return -ENXIO;
	160	}
	161	*offset = cap.drom_offset;
	162	return 0;
	163	}
	164
ff48bc44	165	/*
c90553b3 AN	166	* tb_eeprom_read_n - read count bytes from offset into val
	167	*/
	168	static int tb_eeprom_read_n(struct tb_switch sw, u16 offset, u8 val,
	169	size_t count)
	170	{
4deb200d	171	u16 drom_offset;
c90553b3	172	int i, res;
4deb200d MW	173
	174	res = tb_eeprom_get_drom_offset(sw, &drom_offset);
	175	if (res)
	176	return res;
	177
	178	offset += drom_offset;
	179
c90553b3 AN	180	res = tb_eeprom_active(sw, true);
	181	if (res)
	182	return res;
	183	res = tb_eeprom_out(sw, 3);
	184	if (res)
	185	return res;
	186	res = tb_eeprom_out(sw, offset >> 8);
	187	if (res)
	188	return res;
	189	res = tb_eeprom_out(sw, offset);
	190	if (res)
	191	return res;
	192	for (i = 0; i < count; i++) {
	193	res = tb_eeprom_in(sw, val + i);
	194	if (res)
	195	return res;
	196	}
	197	return tb_eeprom_active(sw, false);
	198	}
	199
cd22e73b AN	200	static u8 tb_crc8(u8 *data, int len)
	201	{
	202	int i, j;
	203	u8 val = 0xff;
	204	for (i = 0; i < len; i++) {
	205	val ^= data[i];
	206	for (j = 0; j < 8; j++)
	207	val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
	208	}
	209	return val;
	210	}
	211
	212	static u32 tb_crc32(void *data, size_t len)
	213	{
	214	return ~__crc32c_le(~0, data, len);
	215	}
	216
b18f9013 GF	217	#define TB_DROM_DATA_START 13
	218	#define TB_DROM_HEADER_SIZE 22
	219	#define USB4_DROM_HEADER_SIZE 16
	220
cd22e73b AN	221	struct tb_drom_header {
	222	/* BYTE 0 */
	223	u8 uid_crc8; /* checksum for uid */
	224	/* BYTES 1-8 */
	225	u64 uid;
	226	/* BYTES 9-12 */
	227	u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
	228	/* BYTE 13 */
	229	u8 device_rom_revision; /* should be <= 1 */
b18f9013 GF	230	u16 data_len:12;
	231	u8 reserved:4;
	232	/* BYTES 16-21 - Only for TBT DROM, nonexistent in USB4 DROM */
cd22e73b AN	233	u16 vendor_id;
	234	u16 model_id;
	235	u8 model_rev;
	236	u8 eeprom_rev;
	237	} __packed;
	238
	239	enum tb_drom_entry_type {
e7120778 AN	240	/* force unsigned to prevent "one-bit signed bitfield" warning */
e7120778 AN	241	TB_DROM_ENTRY_GENERIC = 0U,
cd22e73b AN	242	TB_DROM_ENTRY_PORT,
	243	};
	244
	245	struct tb_drom_entry_header {
	246	u8 len;
	247	u8 index:6;
	248	bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
	249	enum tb_drom_entry_type type:1;
	250	} __packed;
	251
72ee3390 MW	252	struct tb_drom_entry_generic {
72ee3390 MW	253	struct tb_drom_entry_header header;
c2a9fca1	254	u8 data[];
72ee3390 MW	255	} __packed;
72ee3390 MW	256
cd22e73b AN	257	struct tb_drom_entry_port {
	258	/* BYTES 0-1 */
	259	struct tb_drom_entry_header header;
	260	/* BYTE 2 */
	261	u8 dual_link_port_rid:4;
	262	u8 link_nr:1;
	263	u8 unknown1:2;
	264	bool has_dual_link_port:1;
	265
	266	/* BYTE 3 */
	267	u8 dual_link_port_nr:6;
	268	u8 unknown2:2;
	269
	270	/* BYTES 4 - 5 TODO decode */
	271	u8 micro2:4;
	272	u8 micro1:4;
	273	u8 micro3;
	274
aae20bb6	275	/* BYTES 6-7, TODO: verify (find hardware that has these set) */
cd22e73b AN	276	u8 peer_port_rid:4;
	277	u8 unknown3:3;
	278	bool has_peer_port:1;
	279	u8 peer_port_nr:6;
	280	u8 unknown4:2;
	281	} __packed;
	282
3231307e MW	283	/* USB4 product descriptor */
	284	struct tb_drom_entry_desc {
	285	struct tb_drom_entry_header header;
	286	u16 bcdUSBSpec;
	287	u16 idVendor;
	288	u16 idProduct;
	289	u16 bcdProductFWRevision;
	290	u32 TID;
	291	u8 productHWRevision;
	292	};
cd22e73b	293
cd22e73b	294	/**
b12e4824 MW	295	* tb_drom_read_uid_only() - Read UID directly from DROM
	296	* @sw: Router whose UID to read
	297	* @uid: UID is placed here
cd22e73b AN	298	*
	299	* Does not use the cached copy in sw->drom. Used during resume to check switch
	300	* identity.
	301	*/
	302	int tb_drom_read_uid_only(struct tb_switch sw, u64 uid)
	303	{
	304	u8 data[9];
cd22e73b	305	u8 crc;
4deb200d	306	int res;
df1421b5	307
c90553b3	308	/* read uid */
4deb200d	309	res = tb_eeprom_read_n(sw, 0, data, 9);
c90553b3 AN	310	if (res)
c90553b3 AN	311	return res;
cd22e73b AN	312
	313	crc = tb_crc8(data + 1, 8);
	314	if (crc != data[0]) {
eb7bfcce	315	tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n",
cd22e73b AN	316	data[0], crc);
	317	return -EIO;
	318	}
	319
c90553b3 AN	320	uid = (u64 *)(data+1);
	321	return 0;
	322	}
	323
72ee3390 MW	324	static int tb_drom_parse_entry_generic(struct tb_switch *sw,
	325	struct tb_drom_entry_header *header)
	326	{
	327	const struct tb_drom_entry_generic *entry =
	328	(const struct tb_drom_entry_generic *)header;
	329
	330	switch (header->index) {
	331	case 1:
	332	/* Length includes 2 bytes header so remove it before copy */
	333	sw->vendor_name = kstrndup(entry->data,
	334	header->len - sizeof(*header), GFP_KERNEL);
	335	if (!sw->vendor_name)
	336	return -ENOMEM;
	337	break;
	338
	339	case 2:
	340	sw->device_name = kstrndup(entry->data,
	341	header->len - sizeof(*header), GFP_KERNEL);
	342	if (!sw->device_name)
	343	return -ENOMEM;
	344	break;
3231307e MW	345	case 9: {
	346	const struct tb_drom_entry_desc *desc =
	347	(const struct tb_drom_entry_desc *)entry;
	348
	349	if (!sw->vendor && !sw->device) {
	350	sw->vendor = desc->idVendor;
	351	sw->device = desc->idProduct;
	352	}
	353	break;
	354	}
72ee3390 MW	355	}
	356
	357	return 0;
	358	}
	359
02b17a41 LW	360	static int tb_drom_parse_entry_port(struct tb_switch *sw,
02b17a41 LW	361	struct tb_drom_entry_header *header)
cd22e73b AN	362	{
	363	struct tb_port *port;
	364	int res;
	365	enum tb_port_type type;
c90553b3	366
1cd65d17 MW	367	/*
	368	* Some DROMs list more ports than the controller actually has
	369	* so we skip those but allow the parser to continue.
	370	*/
	371	if (header->index > sw->config.max_port_number) {
	372	dev_info_once(&sw->dev, "ignoring unnecessary extra entries in DROM\n");
	373	return 0;
	374	}
	375
cd22e73b AN	376	port = &sw->ports[header->index];
	377	port->disabled = header->port_disabled;
	378	if (port->disabled)
	379	return 0;
	380
	381	res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
	382	if (res)
	383	return res;
	384	type &= 0xffffff;
	385
	386	if (type == TB_TYPE_PORT) {
	387	struct tb_drom_entry_port entry = (void ) header;
	388	if (header->len != sizeof(*entry)) {
	389	tb_sw_warn(sw,
3543fb77	390	"port entry has size %#x (expected %#zx)\n",
cd22e73b AN	391	header->len, sizeof(struct tb_drom_entry_port));
	392	return -EIO;
	393	}
02b17a41 LW	394	port->link_nr = entry->link_nr;
	395	if (entry->has_dual_link_port)
	396	port->dual_link_port =
	397	&port->sw->ports[entry->dual_link_port_nr];
cd22e73b AN	398	}
	399	return 0;
	400	}
	401
ff48bc44	402	/*
cd22e73b AN	403	* tb_drom_parse_entries - parse the linked list of drom entries
	404	*
	405	* Drom must have been copied to sw->drom.
	406	*/
b18f9013	407	static int tb_drom_parse_entries(struct tb_switch *sw, size_t header_size)
cd22e73b AN	408	{
cd22e73b AN	409	struct tb_drom_header header = (void ) sw->drom;
b18f9013	410	u16 pos = header_size;
cd22e73b	411	u16 drom_size = header->data_len + TB_DROM_DATA_START;
02b17a41	412	int res;
cd22e73b AN	413
	414	while (pos < drom_size) {
	415	struct tb_drom_entry_header entry = (void ) (sw->drom + pos);
	416	if (pos + 1 == drom_size \|\| pos + entry->len > drom_size
	417	\|\| !entry->len) {
f022ff7b MW	418	tb_sw_warn(sw, "DROM buffer overrun\n");
f022ff7b MW	419	return -EILSEQ;
cd22e73b AN	420	}
cd22e73b AN	421
02b17a41 LW	422	switch (entry->type) {
02b17a41 LW	423	case TB_DROM_ENTRY_GENERIC:
72ee3390	424	res = tb_drom_parse_entry_generic(sw, entry);
02b17a41 LW	425	break;
	426	case TB_DROM_ENTRY_PORT:
	427	res = tb_drom_parse_entry_port(sw, entry);
	428	break;
	429	}
	430	if (res)
	431	return res;
cd22e73b AN	432
	433	pos += entry->len;
	434	}
	435	return 0;
	436	}
	437
ff48bc44	438	/*
c9cc3aaa LW	439	* tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
	440	*/
	441	static int tb_drom_copy_efi(struct tb_switch sw, u16 size)
	442	{
	443	struct device *dev = &sw->tb->nhi->pdev->dev;
	444	int len, res;
	445
100c12f2	446	len = device_property_count_u8(dev, "ThunderboltDROM");
c9cc3aaa LW	447	if (len < 0 \|\| len < sizeof(struct tb_drom_header))
	448	return -EINVAL;
	449
	450	sw->drom = kmalloc(len, GFP_KERNEL);
	451	if (!sw->drom)
	452	return -ENOMEM;
	453
	454	res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
	455	len);
	456	if (res)
	457	goto err;
	458
	459	size = ((struct tb_drom_header )sw->drom)->data_len +
	460	TB_DROM_DATA_START;
	461	if (*size > len)
	462	goto err;
	463
	464	return 0;
	465
	466	err:
	467	kfree(sw->drom);
	468	sw->drom = NULL;
	469	return -EINVAL;
	470	}
	471
3e136768 MW	472	static int tb_drom_copy_nvm(struct tb_switch sw, u16 size)
	473	{
	474	u32 drom_offset;
	475	int ret;
	476
	477	if (!sw->dma_port)
	478	return -ENODEV;
	479
	480	ret = tb_sw_read(sw, &drom_offset, TB_CFG_SWITCH,
	481	sw->cap_plug_events + 12, 1);
	482	if (ret)
	483	return ret;
	484
	485	if (!drom_offset)
	486	return -ENODEV;
	487
	488	ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size,
	489	sizeof(*size));
	490	if (ret)
	491	return ret;
	492
	493	/* Size includes CRC8 + UID + CRC32 */
	494	*size += 1 + 8 + 4;
	495	sw->drom = kzalloc(*size, GFP_KERNEL);
	496	if (!sw->drom)
	497	return -ENOMEM;
	498
	499	ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size);
	500	if (ret)
	501	goto err_free;
	502
	503	/*
	504	* Read UID from the minimal DROM because the one in NVM is just
	505	* a placeholder.
	506	*/
	507	tb_drom_read_uid_only(sw, &sw->uid);
	508	return 0;
	509
	510	err_free:
	511	kfree(sw->drom);
	512	sw->drom = NULL;
	513	return ret;
	514	}
	515
b0407983 MW	516	static int usb4_copy_host_drom(struct tb_switch sw, u16 size)
	517	{
	518	int ret;
	519
	520	ret = usb4_switch_drom_read(sw, 14, size, sizeof(*size));
	521	if (ret)
	522	return ret;
	523
	524	/* Size includes CRC8 + UID + CRC32 */
	525	*size += 1 + 8 + 4;
	526	sw->drom = kzalloc(*size, GFP_KERNEL);
	527	if (!sw->drom)
	528	return -ENOMEM;
	529
	530	ret = usb4_switch_drom_read(sw, 0, sw->drom, *size);
	531	if (ret) {
	532	kfree(sw->drom);
	533	sw->drom = NULL;
	534	}
	535
	536	return ret;
	537	}
	538
	539	static int tb_drom_read_n(struct tb_switch sw, u16 offset, u8 val,
	540	size_t count)
	541	{
	542	if (tb_switch_is_usb4(sw))
	543	return usb4_switch_drom_read(sw, offset, val, count);
	544	return tb_eeprom_read_n(sw, offset, val, count);
	545	}
	546
3231307e MW	547	static int tb_drom_parse(struct tb_switch *sw)
	548	{
	549	const struct tb_drom_header *header =
	550	(const struct tb_drom_header *)sw->drom;
	551	u32 crc;
	552
	553	crc = tb_crc8((u8 *) &header->uid, 8);
	554	if (crc != header->uid_crc8) {
	555	tb_sw_warn(sw,
	556	"DROM UID CRC8 mismatch (expected: %#x, got: %#x), aborting\n",
	557	header->uid_crc8, crc);
	558	return -EINVAL;
	559	}
	560	if (!sw->uid)
	561	sw->uid = header->uid;
	562	sw->vendor = header->vendor_id;
	563	sw->device = header->model_id;
	564
	565	crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
	566	if (crc != header->data_crc32) {
	567	tb_sw_warn(sw,
	568	"DROM data CRC32 mismatch (expected: %#x, got: %#x), continuing\n",
	569	header->data_crc32, crc);
	570	}
	571
b18f9013	572	return tb_drom_parse_entries(sw, TB_DROM_HEADER_SIZE);
3231307e MW	573	}
	574
	575	static int usb4_drom_parse(struct tb_switch *sw)
	576	{
	577	const struct tb_drom_header *header =
	578	(const struct tb_drom_header *)sw->drom;
	579	u32 crc;
	580
	581	crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
	582	if (crc != header->data_crc32) {
	583	tb_sw_warn(sw,
	584	"DROM data CRC32 mismatch (expected: %#x, got: %#x), aborting\n",
	585	header->data_crc32, crc);
	586	return -EINVAL;
	587	}
	588
b18f9013	589	return tb_drom_parse_entries(sw, USB4_DROM_HEADER_SIZE);
3231307e MW	590	}
3231307e MW	591
cd22e73b	592	/**
b12e4824 MW	593	* tb_drom_read() - Copy DROM to sw->drom and parse it
	594	* @sw: Router whose DROM to read and parse
	595	*
	596	* This function reads router DROM and if successful parses the entries and
	597	* populates the fields in @sw accordingly. Can be called for any router
	598	* generation.
	599	*
	600	* Returns %0 in case of success and negative errno otherwise.
cd22e73b AN	601	*/
	602	int tb_drom_read(struct tb_switch *sw)
	603	{
cd22e73b	604	u16 size;
cd22e73b	605	struct tb_drom_header *header;
f022ff7b MW	606	int res, retries = 1;
f022ff7b MW	607
cd22e73b AN	608	if (sw->drom)
	609	return 0;
	610
	611	if (tb_route(sw) == 0) {
c9cc3aaa LW	612	/*
	613	* Apple's NHI EFI driver supplies a DROM for the root switch
	614	* in a device property. Use it if available.
	615	*/
	616	if (tb_drom_copy_efi(sw, &size) == 0)
	617	goto parse;
	618
3e136768 MW	619	/* Non-Apple hardware has the DROM as part of NVM */
	620	if (tb_drom_copy_nvm(sw, &size) == 0)
	621	goto parse;
	622
cd22e73b	623	/*
b0407983 MW	624	* USB4 hosts may support reading DROM through router
b0407983 MW	625	* operations.
cd22e73b	626	*/
b0407983 MW	627	if (tb_switch_is_usb4(sw)) {
	628	usb4_switch_read_uid(sw, &sw->uid);
	629	if (!usb4_copy_host_drom(sw, &size))
	630	goto parse;
	631	} else {
	632	/*
	633	* The root switch contains only a dummy drom
	634	* (header only, no entries). Hardcode the
	635	* configuration here.
	636	*/
	637	tb_drom_read_uid_only(sw, &sw->uid);
	638	}
	639
cd22e73b AN	640	return 0;
	641	}
	642
b0407983	643	res = tb_drom_read_n(sw, 14, (u8 *) &size, 2);
cd22e73b AN	644	if (res)
	645	return res;
	646	size &= 0x3ff;
	647	size += TB_DROM_DATA_START;
daa5140f	648	tb_sw_dbg(sw, "reading drom (length: %#x)\n", size);
cd22e73b AN	649	if (size < sizeof(*header)) {
	650	tb_sw_warn(sw, "drom too small, aborting\n");
	651	return -EIO;
	652	}
	653
	654	sw->drom = kzalloc(size, GFP_KERNEL);
	655	if (!sw->drom)
	656	return -ENOMEM;
b0407983	657	res = tb_drom_read_n(sw, 0, sw->drom, size);
cd22e73b AN	658	if (res)
	659	goto err;
	660
c9cc3aaa	661	parse:
cd22e73b AN	662	header = (void *) sw->drom;
	663
	664	if (header->data_len + TB_DROM_DATA_START != size) {
	665	tb_sw_warn(sw, "drom size mismatch, aborting\n");
	666	goto err;
	667	}
	668
3231307e	669	tb_sw_dbg(sw, "DROM version: %d\n", header->device_rom_revision);
cd22e73b	670
3231307e MW	671	switch (header->device_rom_revision) {
	672	case 3:
	673	res = usb4_drom_parse(sw);
	674	break;
	675	default:
	676	tb_sw_warn(sw, "DROM device_rom_revision %#x unknown\n",
	677	header->device_rom_revision);
	678	fallthrough;
	679	case 1:
	680	res = tb_drom_parse(sw);
	681	break;
cd22e73b AN	682	}
cd22e73b AN	683
f022ff7b MW	684	/* If the DROM parsing fails, wait a moment and retry once */
	685	if (res == -EILSEQ && retries--) {
	686	tb_sw_warn(sw, "parsing DROM failed, retrying\n");
	687	msleep(100);
	688	res = tb_drom_read_n(sw, 0, sw->drom, size);
	689	if (!res)
	690	goto parse;
	691	}
	692
3231307e MW	693	if (!res)
	694	return 0;
	695
cd22e73b AN	696	err:
cd22e73b AN	697	kfree(sw->drom);
2ffa9a5d	698	sw->drom = NULL;
cd22e73b	699	return -EIO;
cd22e73b	700	}