[mirror_ubuntu-jammy-kernel.git] / drivers / thunderbolt / eeprom.c

/*
 * Thunderbolt Cactus Ridge driver - eeprom access
 *
 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
 */

#include <linux/crc32.h>
#include <linux/property.h>
#include <linux/slab.h>
#include "tb.h"

/**
 * tb_eeprom_ctl_write() - write control word
 */
static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
{
	return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
}

/**
 * tb_eeprom_ctl_write() - read control word
 */
static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
{
	return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
}

enum tb_eeprom_transfer {
	TB_EEPROM_IN,
	TB_EEPROM_OUT,
};

/**
 * tb_eeprom_active - enable rom access
 *
 * WARNING: Always disable access after usage. Otherwise the controller will
 * fail to reprobe.
 */
static int tb_eeprom_active(struct tb_switch *sw, bool enable)
{
	struct tb_eeprom_ctl ctl;
	int res = tb_eeprom_ctl_read(sw, &ctl);
	if (res)
		return res;
	if (enable) {
		ctl.access_high = 1;
		res = tb_eeprom_ctl_write(sw, &ctl);
		if (res)
			return res;
		ctl.access_low = 0;
		return tb_eeprom_ctl_write(sw, &ctl);
	} else {
		ctl.access_low = 1;
		res = tb_eeprom_ctl_write(sw, &ctl);
		if (res)
			return res;
		ctl.access_high = 0;
		return tb_eeprom_ctl_write(sw, &ctl);
	}
}

/**
 * tb_eeprom_transfer - transfer one bit
 *
 * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
 * If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
 */
static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
			      enum tb_eeprom_transfer direction)
{
	int res;
	if (direction == TB_EEPROM_OUT) {
		res = tb_eeprom_ctl_write(sw, ctl);
		if (res)
			return res;
	}
	ctl->clock = 1;
	res = tb_eeprom_ctl_write(sw, ctl);
	if (res)
		return res;
	if (direction == TB_EEPROM_IN) {
		res = tb_eeprom_ctl_read(sw, ctl);
		if (res)
			return res;
	}
	ctl->clock = 0;
	return tb_eeprom_ctl_write(sw, ctl);
}

/**
 * tb_eeprom_out - write one byte to the bus
 */
static int tb_eeprom_out(struct tb_switch *sw, u8 val)
{
	struct tb_eeprom_ctl ctl;
	int i;
	int res = tb_eeprom_ctl_read(sw, &ctl);
	if (res)
		return res;
	for (i = 0; i < 8; i++) {
		ctl.data_out = val & 0x80;
		res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
		if (res)
			return res;
		val <<= 1;
	}
	return 0;
}

/**
 * tb_eeprom_in - read one byte from the bus
 */
static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
{
	struct tb_eeprom_ctl ctl;
	int i;
	int res = tb_eeprom_ctl_read(sw, &ctl);
	if (res)
		return res;
	*val = 0;
	for (i = 0; i < 8; i++) {
		*val <<= 1;
		res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
		if (res)
			return res;
		*val |= ctl.data_in;
	}
	return 0;
}

/**
 * tb_eeprom_read_n - read count bytes from offset into val
 */
static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
		size_t count)
{
	int i, res;
	res = tb_eeprom_active(sw, true);
	if (res)
		return res;
	res = tb_eeprom_out(sw, 3);
	if (res)
		return res;
	res = tb_eeprom_out(sw, offset >> 8);
	if (res)
		return res;
	res = tb_eeprom_out(sw, offset);
	if (res)
		return res;
	for (i = 0; i < count; i++) {
		res = tb_eeprom_in(sw, val + i);
		if (res)
			return res;
	}
	return tb_eeprom_active(sw, false);
}

static u8 tb_crc8(u8 *data, int len)
{
	int i, j;
	u8 val = 0xff;
	for (i = 0; i < len; i++) {
		val ^= data[i];
		for (j = 0; j < 8; j++)
			val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
	}
	return val;
}

static u32 tb_crc32(void *data, size_t len)
{
	return ~__crc32c_le(~0, data, len);
}

#define TB_DROM_DATA_START 13
struct tb_drom_header {
	/* BYTE 0 */
	u8 uid_crc8; /* checksum for uid */
	/* BYTES 1-8 */
	u64 uid;
	/* BYTES 9-12 */
	u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
	/* BYTE 13 */
	u8 device_rom_revision; /* should be <= 1 */
	u16 data_len:10;
	u8 __unknown1:6;
	/* BYTES 16-21 */
	u16 vendor_id;
	u16 model_id;
	u8 model_rev;
	u8 eeprom_rev;
} __packed;

enum tb_drom_entry_type {
	/* force unsigned to prevent "one-bit signed bitfield" warning */
	TB_DROM_ENTRY_GENERIC = 0U,
	TB_DROM_ENTRY_PORT,
};

struct tb_drom_entry_header {
	u8 len;
	u8 index:6;
	bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
	enum tb_drom_entry_type type:1;
} __packed;

struct tb_drom_entry_port {
	/* BYTES 0-1 */
	struct tb_drom_entry_header header;
	/* BYTE 2 */
	u8 dual_link_port_rid:4;
	u8 link_nr:1;
	u8 unknown1:2;
	bool has_dual_link_port:1;

	/* BYTE 3 */
	u8 dual_link_port_nr:6;
	u8 unknown2:2;

	/* BYTES 4 - 5 TODO decode */
	u8 micro2:4;
	u8 micro1:4;
	u8 micro3;

	/* BYTES 6-7, TODO: verify (find hardware that has these set) */
	u8 peer_port_rid:4;
	u8 unknown3:3;
	bool has_peer_port:1;
	u8 peer_port_nr:6;
	u8 unknown4:2;
} __packed;


/**
 * tb_eeprom_get_drom_offset - get drom offset within eeprom
 */
static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
{
	struct tb_cap_plug_events cap;
	int res;
	if (!sw->cap_plug_events) {
		tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
		return -ENOSYS;
	}
	res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
			     sizeof(cap) / 4);
	if (res)
		return res;

	if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
		tb_sw_warn(sw, "no NVM\n");
		return -ENOSYS;
	}

	if (cap.drom_offset > 0xffff) {
		tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
				cap.drom_offset);
		return -ENXIO;
	}
	*offset = cap.drom_offset;
	return 0;
}

/**
 * tb_drom_read_uid_only - read uid directly from drom
 *
 * Does not use the cached copy in sw->drom. Used during resume to check switch
 * identity.
 */
int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
{
	u8 data[9];
	u16 drom_offset;
	u8 crc;
	int res = tb_eeprom_get_drom_offset(sw, &drom_offset);
	if (res)
		return res;

	if (drom_offset == 0)
		return -ENODEV;

	/* read uid */
	res = tb_eeprom_read_n(sw, drom_offset, data, 9);
	if (res)
		return res;

	crc = tb_crc8(data + 1, 8);
	if (crc != data[0]) {
		tb_sw_warn(sw, "uid crc8 missmatch (expected: %#x, got: %#x)\n",
				data[0], crc);
		return -EIO;
	}

	*uid = *(u64 *)(data+1);
	return 0;
}

static void tb_drom_parse_port_entry(struct tb_port *port,
		struct tb_drom_entry_port *entry)
{
	port->link_nr = entry->link_nr;
	if (entry->has_dual_link_port)
		port->dual_link_port =
				&port->sw->ports[entry->dual_link_port_nr];
}

static int tb_drom_parse_entry(struct tb_switch *sw,
		struct tb_drom_entry_header *header)
{
	struct tb_port *port;
	int res;
	enum tb_port_type type;

	if (header->type != TB_DROM_ENTRY_PORT)
		return 0;

	port = &sw->ports[header->index];
	port->disabled = header->port_disabled;
	if (port->disabled)
		return 0;

	res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
	if (res)
		return res;
	type &= 0xffffff;

	if (type == TB_TYPE_PORT) {
		struct tb_drom_entry_port *entry = (void *) header;
		if (header->len != sizeof(*entry)) {
			tb_sw_warn(sw,
				"port entry has size %#x (expected %#zx)\n",
				header->len, sizeof(struct tb_drom_entry_port));
			return -EIO;
		}
		tb_drom_parse_port_entry(port, entry);
	}
	return 0;
}

/**
 * tb_drom_parse_entries - parse the linked list of drom entries
 *
 * Drom must have been copied to sw->drom.
 */
static int tb_drom_parse_entries(struct tb_switch *sw)
{
	struct tb_drom_header *header = (void *) sw->drom;
	u16 pos = sizeof(*header);
	u16 drom_size = header->data_len + TB_DROM_DATA_START;

	while (pos < drom_size) {
		struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
		if (pos + 1 == drom_size || pos + entry->len > drom_size
				|| !entry->len) {
			tb_sw_warn(sw, "drom buffer overrun, aborting\n");
			return -EIO;
		}

		tb_drom_parse_entry(sw, entry);

		pos += entry->len;
	}
	return 0;
}

/**
 * tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
 */
static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size)
{
	struct device *dev = &sw->tb->nhi->pdev->dev;
	int len, res;

	len = device_property_read_u8_array(dev, "ThunderboltDROM", NULL, 0);
	if (len < 0 || len < sizeof(struct tb_drom_header))
		return -EINVAL;

	sw->drom = kmalloc(len, GFP_KERNEL);
	if (!sw->drom)
		return -ENOMEM;

	res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
									len);
	if (res)
		goto err;

	*size = ((struct tb_drom_header *)sw->drom)->data_len +
							  TB_DROM_DATA_START;
	if (*size > len)
		goto err;

	return 0;

err:
	kfree(sw->drom);
	sw->drom = NULL;
	return -EINVAL;
}

/**
 * tb_drom_read - copy drom to sw->drom and parse it
 */
int tb_drom_read(struct tb_switch *sw)
{
	u16 drom_offset;
	u16 size;
	u32 crc;
	struct tb_drom_header *header;
	int res;
	if (sw->drom)
		return 0;

	if (tb_route(sw) == 0) {
		/*
		 * Apple's NHI EFI driver supplies a DROM for the root switch
		 * in a device property. Use it if available.
		 */
		if (tb_drom_copy_efi(sw, &size) == 0)
			goto parse;

		/*
		 * The root switch contains only a dummy drom (header only,
		 * no entries). Hardcode the configuration here.
		 */
		tb_drom_read_uid_only(sw, &sw->uid);

		sw->ports[1].link_nr = 0;
		sw->ports[2].link_nr = 1;
		sw->ports[1].dual_link_port = &sw->ports[2];
		sw->ports[2].dual_link_port = &sw->ports[1];

		sw->ports[3].link_nr = 0;
		sw->ports[4].link_nr = 1;
		sw->ports[3].dual_link_port = &sw->ports[4];
		sw->ports[4].dual_link_port = &sw->ports[3];

		/* Port 5 is inaccessible on this gen 1 controller */
		if (sw->config.device_id == PCI_DEVICE_ID_INTEL_LIGHT_RIDGE)
			sw->ports[5].disabled = true;

		return 0;
	}

	res = tb_eeprom_get_drom_offset(sw, &drom_offset);
	if (res)
		return res;

	res = tb_eeprom_read_n(sw, drom_offset + 14, (u8 *) &size, 2);
	if (res)
		return res;
	size &= 0x3ff;
	size += TB_DROM_DATA_START;
	tb_sw_info(sw, "reading drom (length: %#x)\n", size);
	if (size < sizeof(*header)) {
		tb_sw_warn(sw, "drom too small, aborting\n");
		return -EIO;
	}

	sw->drom = kzalloc(size, GFP_KERNEL);
	if (!sw->drom)
		return -ENOMEM;
	res = tb_eeprom_read_n(sw, drom_offset, sw->drom, size);
	if (res)
		goto err;

parse:
	header = (void *) sw->drom;

	if (header->data_len + TB_DROM_DATA_START != size) {
		tb_sw_warn(sw, "drom size mismatch, aborting\n");
		goto err;
	}

	crc = tb_crc8((u8 *) &header->uid, 8);
	if (crc != header->uid_crc8) {
		tb_sw_warn(sw,
			"drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
			header->uid_crc8, crc);
		goto err;
	}
	sw->uid = header->uid;

	crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
	if (crc != header->data_crc32) {
		tb_sw_warn(sw,
			"drom data crc32 mismatch (expected: %#x, got: %#x), aborting\n",
			header->data_crc32, crc);
		goto err;
	}

	if (header->device_rom_revision > 2)
		tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
			header->device_rom_revision);

	return tb_drom_parse_entries(sw);
err:
	kfree(sw->drom);
	sw->drom = NULL;
	return -EIO;

}
Commit	Line	Data
c90553b3 AN	1	/*
	2	* Thunderbolt Cactus Ridge driver - eeprom access
	3	*
	4	* Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
	5	*/
	6
cd22e73b	7	#include <linux/crc32.h>
c9cc3aaa	8	#include <linux/property.h>
2b35404e	9	#include <linux/slab.h>
c90553b3 AN	10	#include "tb.h"
	11
	12	/**
	13	* tb_eeprom_ctl_write() - write control word
	14	*/
	15	static int tb_eeprom_ctl_write(struct tb_switch sw, struct tb_eeprom_ctl ctl)
	16	{
	17	return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
	18	}
	19
	20	/**
	21	* tb_eeprom_ctl_write() - read control word
	22	*/
	23	static int tb_eeprom_ctl_read(struct tb_switch sw, struct tb_eeprom_ctl ctl)
	24	{
	25	return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
	26	}
	27
	28	enum tb_eeprom_transfer {
	29	TB_EEPROM_IN,
	30	TB_EEPROM_OUT,
	31	};
	32
	33	/**
	34	* tb_eeprom_active - enable rom access
	35	*
	36	* WARNING: Always disable access after usage. Otherwise the controller will
	37	* fail to reprobe.
	38	*/
	39	static int tb_eeprom_active(struct tb_switch *sw, bool enable)
	40	{
	41	struct tb_eeprom_ctl ctl;
	42	int res = tb_eeprom_ctl_read(sw, &ctl);
	43	if (res)
	44	return res;
	45	if (enable) {
	46	ctl.access_high = 1;
	47	res = tb_eeprom_ctl_write(sw, &ctl);
	48	if (res)
	49	return res;
	50	ctl.access_low = 0;
	51	return tb_eeprom_ctl_write(sw, &ctl);
	52	} else {
	53	ctl.access_low = 1;
	54	res = tb_eeprom_ctl_write(sw, &ctl);
	55	if (res)
	56	return res;
	57	ctl.access_high = 0;
	58	return tb_eeprom_ctl_write(sw, &ctl);
	59	}
	60	}
	61
	62	/**
	63	* tb_eeprom_transfer - transfer one bit
	64	*
	65	* If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
	66	* If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
	67	*/
	68	static int tb_eeprom_transfer(struct tb_switch sw, struct tb_eeprom_ctl ctl,
	69	enum tb_eeprom_transfer direction)
	70	{
	71	int res;
	72	if (direction == TB_EEPROM_OUT) {
	73	res = tb_eeprom_ctl_write(sw, ctl);
74	if (res)
75	return res;
76	}
77	ctl->clock = 1;
78	res = tb_eeprom_ctl_write(sw, ctl);
79	if (res)
80	return res;
81	if (direction == TB_EEPROM_IN) {
82	res = tb_eeprom_ctl_read(sw, ctl);
83	if (res)
84	return res;
85	}
86	ctl->clock = 0;
87	return tb_eeprom_ctl_write(sw, ctl);
88	}
89
90	/**
91	* tb_eeprom_out - write one byte to the bus
92	*/
93	static int tb_eeprom_out(struct tb_switch *sw, u8 val)
94	{
95	struct tb_eeprom_ctl ctl;
96	int i;
97	int res = tb_eeprom_ctl_read(sw, &ctl);
98	if (res)
99	return res;
100	for (i = 0; i < 8; i++) {
101	ctl.data_out = val & 0x80;
102	res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
103	if (res)
104	return res;
105	val <<= 1;
106	}
107	return 0;
108	}
109
110	/**
111	* tb_eeprom_in - read one byte from the bus
112	*/
113	static int tb_eeprom_in(struct tb_switch sw, u8 val)
114	{
115	struct tb_eeprom_ctl ctl;
116	int i;
117	int res = tb_eeprom_ctl_read(sw, &ctl);
118	if (res)
119	return res;
120	*val = 0;
121	for (i = 0; i < 8; i++) {
122	*val <<= 1;
123	res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
124	if (res)
125	return res;
126	*val \|= ctl.data_in;
127	}
128	return 0;
129	}
130
131	/**
132	* tb_eeprom_read_n - read count bytes from offset into val
133	*/
134	static int tb_eeprom_read_n(struct tb_switch sw, u16 offset, u8 val,
135	size_t count)
136	{
137	int i, res;
138	res = tb_eeprom_active(sw, true);
139	if (res)
140	return res;
141	res = tb_eeprom_out(sw, 3);
142	if (res)
143	return res;
144	res = tb_eeprom_out(sw, offset >> 8);
145	if (res)
146	return res;
147	res = tb_eeprom_out(sw, offset);
148	if (res)
149	return res;
150	for (i = 0; i < count; i++) {
151	res = tb_eeprom_in(sw, val + i);
152	if (res)
153	return res;
154	}
155	return tb_eeprom_active(sw, false);
156	}
157
cd22e73b AN	158	static u8 tb_crc8(u8 *data, int len)
	159	{
	160	int i, j;
	161	u8 val = 0xff;
	162	for (i = 0; i < len; i++) {
	163	val ^= data[i];
	164	for (j = 0; j < 8; j++)
	165	val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
	166	}
	167	return val;
	168	}
	169
	170	static u32 tb_crc32(void *data, size_t len)
	171	{
	172	return ~__crc32c_le(~0, data, len);
	173	}
	174
	175	#define TB_DROM_DATA_START 13
	176	struct tb_drom_header {
	177	/* BYTE 0 */
	178	u8 uid_crc8; /* checksum for uid */
	179	/* BYTES 1-8 */
	180	u64 uid;
	181	/* BYTES 9-12 */
	182	u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
	183	/* BYTE 13 */
	184	u8 device_rom_revision; /* should be <= 1 */
	185	u16 data_len:10;
	186	u8 __unknown1:6;
	187	/* BYTES 16-21 */
	188	u16 vendor_id;
	189	u16 model_id;
	190	u8 model_rev;
	191	u8 eeprom_rev;
	192	} __packed;
	193
	194	enum tb_drom_entry_type {
e7120778 AN	195	/* force unsigned to prevent "one-bit signed bitfield" warning */
e7120778 AN	196	TB_DROM_ENTRY_GENERIC = 0U,
cd22e73b AN	197	TB_DROM_ENTRY_PORT,
	198	};
	199
	200	struct tb_drom_entry_header {
	201	u8 len;
	202	u8 index:6;
	203	bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
	204	enum tb_drom_entry_type type:1;
	205	} __packed;
	206
	207	struct tb_drom_entry_port {
	208	/* BYTES 0-1 */
	209	struct tb_drom_entry_header header;
	210	/* BYTE 2 */
	211	u8 dual_link_port_rid:4;
	212	u8 link_nr:1;
	213	u8 unknown1:2;
	214	bool has_dual_link_port:1;
	215
	216	/* BYTE 3 */
	217	u8 dual_link_port_nr:6;
	218	u8 unknown2:2;
	219
	220	/* BYTES 4 - 5 TODO decode */
	221	u8 micro2:4;
	222	u8 micro1:4;
	223	u8 micro3;
	224
aae20bb6	225	/* BYTES 6-7, TODO: verify (find hardware that has these set) */
cd22e73b AN	226	u8 peer_port_rid:4;
	227	u8 unknown3:3;
	228	bool has_peer_port:1;
	229	u8 peer_port_nr:6;
	230	u8 unknown4:2;
	231	} __packed;
	232
	233
	234	/**
	235	* tb_eeprom_get_drom_offset - get drom offset within eeprom
	236	*/
e0f55014	237	static int tb_eeprom_get_drom_offset(struct tb_switch sw, u16 offset)
c90553b3	238	{
c90553b3 AN	239	struct tb_cap_plug_events cap;
	240	int res;
	241	if (!sw->cap_plug_events) {
	242	tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
	243	return -ENOSYS;
	244	}
	245	res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
	246	sizeof(cap) / 4);
	247	if (res)
	248	return res;
cd22e73b	249
c90553b3 AN	250	if (!cap.eeprom_ctl.present \|\| cap.eeprom_ctl.not_present) {
	251	tb_sw_warn(sw, "no NVM\n");
	252	return -ENOSYS;
	253	}
	254
	255	if (cap.drom_offset > 0xffff) {
	256	tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
	257	cap.drom_offset);
	258	return -ENXIO;
	259	}
cd22e73b AN	260	*offset = cap.drom_offset;
	261	return 0;
	262	}
	263
	264	/**
	265	* tb_drom_read_uid_only - read uid directly from drom
	266	*
	267	* Does not use the cached copy in sw->drom. Used during resume to check switch
	268	* identity.
	269	*/
	270	int tb_drom_read_uid_only(struct tb_switch sw, u64 uid)
	271	{
	272	u8 data[9];
	273	u16 drom_offset;
	274	u8 crc;
	275	int res = tb_eeprom_get_drom_offset(sw, &drom_offset);
	276	if (res)
	277	return res;
c90553b3	278
df1421b5 MW	279	if (drom_offset == 0)
	280	return -ENODEV;
	281
c90553b3	282	/* read uid */
cd22e73b	283	res = tb_eeprom_read_n(sw, drom_offset, data, 9);
c90553b3 AN	284	if (res)
c90553b3 AN	285	return res;
cd22e73b AN	286
	287	crc = tb_crc8(data + 1, 8);
	288	if (crc != data[0]) {
	289	tb_sw_warn(sw, "uid crc8 missmatch (expected: %#x, got: %#x)\n",
	290	data[0], crc);
	291	return -EIO;
	292	}
	293
c90553b3 AN	294	uid = (u64 *)(data+1);
	295	return 0;
	296	}
	297
cd22e73b AN	298	static void tb_drom_parse_port_entry(struct tb_port *port,
	299	struct tb_drom_entry_port *entry)
	300	{
	301	port->link_nr = entry->link_nr;
	302	if (entry->has_dual_link_port)
	303	port->dual_link_port =
	304	&port->sw->ports[entry->dual_link_port_nr];
	305	}
	306
	307	static int tb_drom_parse_entry(struct tb_switch *sw,
	308	struct tb_drom_entry_header *header)
	309	{
	310	struct tb_port *port;
	311	int res;
	312	enum tb_port_type type;
c90553b3	313
cd22e73b AN	314	if (header->type != TB_DROM_ENTRY_PORT)
cd22e73b AN	315	return 0;
c90553b3	316
cd22e73b AN	317	port = &sw->ports[header->index];
	318	port->disabled = header->port_disabled;
	319	if (port->disabled)
	320	return 0;
	321
	322	res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
	323	if (res)
	324	return res;
	325	type &= 0xffffff;
	326
	327	if (type == TB_TYPE_PORT) {
	328	struct tb_drom_entry_port entry = (void ) header;
	329	if (header->len != sizeof(*entry)) {
	330	tb_sw_warn(sw,
3543fb77	331	"port entry has size %#x (expected %#zx)\n",
cd22e73b AN	332	header->len, sizeof(struct tb_drom_entry_port));
	333	return -EIO;
	334	}
	335	tb_drom_parse_port_entry(port, entry);
	336	}
	337	return 0;
	338	}
	339
	340	/**
	341	* tb_drom_parse_entries - parse the linked list of drom entries
	342	*
	343	* Drom must have been copied to sw->drom.
	344	*/
	345	static int tb_drom_parse_entries(struct tb_switch *sw)
	346	{
	347	struct tb_drom_header header = (void ) sw->drom;
	348	u16 pos = sizeof(*header);
	349	u16 drom_size = header->data_len + TB_DROM_DATA_START;
	350
	351	while (pos < drom_size) {
	352	struct tb_drom_entry_header entry = (void ) (sw->drom + pos);
	353	if (pos + 1 == drom_size \|\| pos + entry->len > drom_size
	354	\|\| !entry->len) {
	355	tb_sw_warn(sw, "drom buffer overrun, aborting\n");
	356	return -EIO;
	357	}
	358
	359	tb_drom_parse_entry(sw, entry);
	360
	361	pos += entry->len;
	362	}
	363	return 0;
	364	}
	365
c9cc3aaa LW	366	/**
	367	* tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
	368	*/
	369	static int tb_drom_copy_efi(struct tb_switch sw, u16 size)
	370	{
	371	struct device *dev = &sw->tb->nhi->pdev->dev;
	372	int len, res;
	373
	374	len = device_property_read_u8_array(dev, "ThunderboltDROM", NULL, 0);
	375	if (len < 0 \|\| len < sizeof(struct tb_drom_header))
	376	return -EINVAL;
	377
	378	sw->drom = kmalloc(len, GFP_KERNEL);
	379	if (!sw->drom)
	380	return -ENOMEM;
	381
	382	res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
	383	len);
	384	if (res)
	385	goto err;
	386
	387	size = ((struct tb_drom_header )sw->drom)->data_len +
	388	TB_DROM_DATA_START;
	389	if (*size > len)
	390	goto err;
	391
	392	return 0;
	393
	394	err:
	395	kfree(sw->drom);
	396	sw->drom = NULL;
	397	return -EINVAL;
	398	}
	399
cd22e73b AN	400	/**
	401	* tb_drom_read - copy drom to sw->drom and parse it
	402	*/
	403	int tb_drom_read(struct tb_switch *sw)
	404	{
	405	u16 drom_offset;
	406	u16 size;
	407	u32 crc;
	408	struct tb_drom_header *header;
	409	int res;
	410	if (sw->drom)
	411	return 0;
	412
	413	if (tb_route(sw) == 0) {
c9cc3aaa LW	414	/*
	415	* Apple's NHI EFI driver supplies a DROM for the root switch
	416	* in a device property. Use it if available.
	417	*/
	418	if (tb_drom_copy_efi(sw, &size) == 0)
	419	goto parse;
	420
cd22e73b AN	421	/*
	422	* The root switch contains only a dummy drom (header only,
	423	* no entries). Hardcode the configuration here.
	424	*/
	425	tb_drom_read_uid_only(sw, &sw->uid);
	426
	427	sw->ports[1].link_nr = 0;
	428	sw->ports[2].link_nr = 1;
	429	sw->ports[1].dual_link_port = &sw->ports[2];
	430	sw->ports[2].dual_link_port = &sw->ports[1];
	431
	432	sw->ports[3].link_nr = 0;
	433	sw->ports[4].link_nr = 1;
	434	sw->ports[3].dual_link_port = &sw->ports[4];
	435	sw->ports[4].dual_link_port = &sw->ports[3];
19bf4d4f LW	436
	437	/* Port 5 is inaccessible on this gen 1 controller */
	438	if (sw->config.device_id == PCI_DEVICE_ID_INTEL_LIGHT_RIDGE)
	439	sw->ports[5].disabled = true;
	440
cd22e73b AN	441	return 0;
	442	}
	443
	444	res = tb_eeprom_get_drom_offset(sw, &drom_offset);
	445	if (res)
	446	return res;
	447
	448	res = tb_eeprom_read_n(sw, drom_offset + 14, (u8 *) &size, 2);
	449	if (res)
	450	return res;
	451	size &= 0x3ff;
	452	size += TB_DROM_DATA_START;
	453	tb_sw_info(sw, "reading drom (length: %#x)\n", size);
	454	if (size < sizeof(*header)) {
	455	tb_sw_warn(sw, "drom too small, aborting\n");
	456	return -EIO;
	457	}
	458
	459	sw->drom = kzalloc(size, GFP_KERNEL);
	460	if (!sw->drom)
	461	return -ENOMEM;
	462	res = tb_eeprom_read_n(sw, drom_offset, sw->drom, size);
	463	if (res)
	464	goto err;
	465
c9cc3aaa	466	parse:
cd22e73b AN	467	header = (void *) sw->drom;
	468
	469	if (header->data_len + TB_DROM_DATA_START != size) {
	470	tb_sw_warn(sw, "drom size mismatch, aborting\n");
	471	goto err;
	472	}
	473
	474	crc = tb_crc8((u8 *) &header->uid, 8);
	475	if (crc != header->uid_crc8) {
	476	tb_sw_warn(sw,
	477	"drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
	478	header->uid_crc8, crc);
	479	goto err;
	480	}
	481	sw->uid = header->uid;
	482
	483	crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
	484	if (crc != header->data_crc32) {
	485	tb_sw_warn(sw,
	486	"drom data crc32 mismatch (expected: %#x, got: %#x), aborting\n",
	487	header->data_crc32, crc);
	488	goto err;
	489	}
	490
b2466355	491	if (header->device_rom_revision > 2)
cd22e73b AN	492	tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
	493	header->device_rom_revision);
	494
	495	return tb_drom_parse_entries(sw);
	496	err:
	497	kfree(sw->drom);
2ffa9a5d	498	sw->drom = NULL;
cd22e73b AN	499	return -EIO;
	500
	501	}