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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
16603153 | 2 | /* |
15c6784c | 3 | * Thunderbolt driver - NHI driver |
16603153 AN |
4 | * |
5 | * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> | |
15c6784c | 6 | * Copyright (C) 2018, Intel Corporation |
16603153 AN |
7 | */ |
8 | ||
9 | #ifndef DSL3510_H_ | |
10 | #define DSL3510_H_ | |
11 | ||
3b3d9f4d | 12 | #include <linux/thunderbolt.h> |
16603153 | 13 | |
cd446ee2 MW |
14 | enum nhi_fw_mode { |
15 | NHI_FW_SAFE_MODE, | |
16 | NHI_FW_AUTH_MODE, | |
17 | NHI_FW_EP_MODE, | |
18 | NHI_FW_CM_MODE, | |
19 | }; | |
20 | ||
21 | enum nhi_mailbox_cmd { | |
22 | NHI_MAILBOX_SAVE_DEVS = 0x05, | |
e6b245cc | 23 | NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06, |
cd446ee2 | 24 | NHI_MAILBOX_DRV_UNLOADS = 0x07, |
d1ff7024 MW |
25 | NHI_MAILBOX_DISCONNECT_PA = 0x10, |
26 | NHI_MAILBOX_DISCONNECT_PB = 0x11, | |
cd446ee2 MW |
27 | NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23, |
28 | }; | |
29 | ||
30 | int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data); | |
31 | enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi); | |
32 | ||
3cdb9446 MW |
33 | /** |
34 | * struct tb_nhi_ops - NHI specific optional operations | |
35 | * @init: NHI specific initialization | |
36 | * @suspend_noirq: NHI specific suspend_noirq hook | |
37 | * @resume_noirq: NHI specific resume_noirq hook | |
38 | * @runtime_suspend: NHI specific runtime_suspend hook | |
39 | * @runtime_resume: NHI specific runtime_resume hook | |
40 | * @shutdown: NHI specific shutdown | |
41 | */ | |
42 | struct tb_nhi_ops { | |
43 | int (*init)(struct tb_nhi *nhi); | |
44 | int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup); | |
45 | int (*resume_noirq)(struct tb_nhi *nhi); | |
46 | int (*runtime_suspend)(struct tb_nhi *nhi); | |
47 | int (*runtime_resume)(struct tb_nhi *nhi); | |
48 | void (*shutdown)(struct tb_nhi *nhi); | |
49 | }; | |
50 | ||
51 | extern const struct tb_nhi_ops icl_nhi_ops; | |
52 | ||
5e2781bc MW |
53 | /* |
54 | * PCI IDs used in this driver from Win Ridge forward. There is no | |
55 | * need for the PCI quirk anymore as we will use ICM also on Apple | |
56 | * hardware. | |
57 | */ | |
58 | #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d | |
59 | #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e | |
60 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf | |
61 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0 | |
62 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2 | |
63 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3 | |
64 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9 | |
65 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da | |
66 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc | |
67 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd | |
68 | #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de | |
4bac471d RM |
69 | #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7 |
70 | #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8 | |
71 | #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea | |
72 | #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb | |
73 | #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef | |
3cdb9446 MW |
74 | #define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d |
75 | #define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a17 | |
5e2781bc | 76 | |
16603153 | 77 | #endif |