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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
a25c8b2f | 2 | /* |
15c6784c | 3 | * Thunderbolt driver - switch/port utility functions |
a25c8b2f AN |
4 | * |
5 | * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> | |
15c6784c | 6 | * Copyright (C) 2018, Intel Corporation |
a25c8b2f AN |
7 | */ |
8 | ||
9 | #include <linux/delay.h> | |
e6b245cc MW |
10 | #include <linux/idr.h> |
11 | #include <linux/nvmem-provider.h> | |
2d8ff0b5 | 12 | #include <linux/pm_runtime.h> |
09f11b6c | 13 | #include <linux/sched/signal.h> |
e6b245cc | 14 | #include <linux/sizes.h> |
10fefe56 | 15 | #include <linux/slab.h> |
e6b245cc | 16 | #include <linux/vmalloc.h> |
a25c8b2f AN |
17 | |
18 | #include "tb.h" | |
19 | ||
e6b245cc MW |
20 | /* Switch NVM support */ |
21 | ||
22 | #define NVM_DEVID 0x05 | |
23 | #define NVM_VERSION 0x08 | |
24 | #define NVM_CSS 0x10 | |
25 | #define NVM_FLASH_SIZE 0x45 | |
26 | ||
27 | #define NVM_MIN_SIZE SZ_32K | |
28 | #define NVM_MAX_SIZE SZ_512K | |
29 | ||
30 | static DEFINE_IDA(nvm_ida); | |
31 | ||
32 | struct nvm_auth_status { | |
33 | struct list_head list; | |
7c39ffe7 | 34 | uuid_t uuid; |
e6b245cc MW |
35 | u32 status; |
36 | }; | |
37 | ||
38 | /* | |
39 | * Hold NVM authentication failure status per switch This information | |
40 | * needs to stay around even when the switch gets power cycled so we | |
41 | * keep it separately. | |
42 | */ | |
43 | static LIST_HEAD(nvm_auth_status_cache); | |
44 | static DEFINE_MUTEX(nvm_auth_status_lock); | |
45 | ||
46 | static struct nvm_auth_status *__nvm_get_auth_status(const struct tb_switch *sw) | |
47 | { | |
48 | struct nvm_auth_status *st; | |
49 | ||
50 | list_for_each_entry(st, &nvm_auth_status_cache, list) { | |
7c39ffe7 | 51 | if (uuid_equal(&st->uuid, sw->uuid)) |
e6b245cc MW |
52 | return st; |
53 | } | |
54 | ||
55 | return NULL; | |
56 | } | |
57 | ||
58 | static void nvm_get_auth_status(const struct tb_switch *sw, u32 *status) | |
59 | { | |
60 | struct nvm_auth_status *st; | |
61 | ||
62 | mutex_lock(&nvm_auth_status_lock); | |
63 | st = __nvm_get_auth_status(sw); | |
64 | mutex_unlock(&nvm_auth_status_lock); | |
65 | ||
66 | *status = st ? st->status : 0; | |
67 | } | |
68 | ||
69 | static void nvm_set_auth_status(const struct tb_switch *sw, u32 status) | |
70 | { | |
71 | struct nvm_auth_status *st; | |
72 | ||
73 | if (WARN_ON(!sw->uuid)) | |
74 | return; | |
75 | ||
76 | mutex_lock(&nvm_auth_status_lock); | |
77 | st = __nvm_get_auth_status(sw); | |
78 | ||
79 | if (!st) { | |
80 | st = kzalloc(sizeof(*st), GFP_KERNEL); | |
81 | if (!st) | |
82 | goto unlock; | |
83 | ||
84 | memcpy(&st->uuid, sw->uuid, sizeof(st->uuid)); | |
85 | INIT_LIST_HEAD(&st->list); | |
86 | list_add_tail(&st->list, &nvm_auth_status_cache); | |
87 | } | |
88 | ||
89 | st->status = status; | |
90 | unlock: | |
91 | mutex_unlock(&nvm_auth_status_lock); | |
92 | } | |
93 | ||
94 | static void nvm_clear_auth_status(const struct tb_switch *sw) | |
95 | { | |
96 | struct nvm_auth_status *st; | |
97 | ||
98 | mutex_lock(&nvm_auth_status_lock); | |
99 | st = __nvm_get_auth_status(sw); | |
100 | if (st) { | |
101 | list_del(&st->list); | |
102 | kfree(st); | |
103 | } | |
104 | mutex_unlock(&nvm_auth_status_lock); | |
105 | } | |
106 | ||
107 | static int nvm_validate_and_write(struct tb_switch *sw) | |
108 | { | |
109 | unsigned int image_size, hdr_size; | |
110 | const u8 *buf = sw->nvm->buf; | |
111 | u16 ds_size; | |
112 | int ret; | |
113 | ||
114 | if (!buf) | |
115 | return -EINVAL; | |
116 | ||
117 | image_size = sw->nvm->buf_data_size; | |
118 | if (image_size < NVM_MIN_SIZE || image_size > NVM_MAX_SIZE) | |
119 | return -EINVAL; | |
120 | ||
121 | /* | |
122 | * FARB pointer must point inside the image and must at least | |
123 | * contain parts of the digital section we will be reading here. | |
124 | */ | |
125 | hdr_size = (*(u32 *)buf) & 0xffffff; | |
126 | if (hdr_size + NVM_DEVID + 2 >= image_size) | |
127 | return -EINVAL; | |
128 | ||
129 | /* Digital section start should be aligned to 4k page */ | |
130 | if (!IS_ALIGNED(hdr_size, SZ_4K)) | |
131 | return -EINVAL; | |
132 | ||
133 | /* | |
134 | * Read digital section size and check that it also fits inside | |
135 | * the image. | |
136 | */ | |
137 | ds_size = *(u16 *)(buf + hdr_size); | |
138 | if (ds_size >= image_size) | |
139 | return -EINVAL; | |
140 | ||
141 | if (!sw->safe_mode) { | |
142 | u16 device_id; | |
143 | ||
144 | /* | |
145 | * Make sure the device ID in the image matches the one | |
146 | * we read from the switch config space. | |
147 | */ | |
148 | device_id = *(u16 *)(buf + hdr_size + NVM_DEVID); | |
149 | if (device_id != sw->config.device_id) | |
150 | return -EINVAL; | |
151 | ||
152 | if (sw->generation < 3) { | |
153 | /* Write CSS headers first */ | |
154 | ret = dma_port_flash_write(sw->dma_port, | |
155 | DMA_PORT_CSS_ADDRESS, buf + NVM_CSS, | |
156 | DMA_PORT_CSS_MAX_SIZE); | |
157 | if (ret) | |
158 | return ret; | |
159 | } | |
160 | ||
161 | /* Skip headers in the image */ | |
162 | buf += hdr_size; | |
163 | image_size -= hdr_size; | |
164 | } | |
165 | ||
166 | return dma_port_flash_write(sw->dma_port, 0, buf, image_size); | |
167 | } | |
168 | ||
169 | static int nvm_authenticate_host(struct tb_switch *sw) | |
170 | { | |
171 | int ret; | |
172 | ||
173 | /* | |
174 | * Root switch NVM upgrade requires that we disconnect the | |
d1ff7024 | 175 | * existing paths first (in case it is not in safe mode |
e6b245cc MW |
176 | * already). |
177 | */ | |
178 | if (!sw->safe_mode) { | |
d1ff7024 | 179 | ret = tb_domain_disconnect_all_paths(sw->tb); |
e6b245cc MW |
180 | if (ret) |
181 | return ret; | |
182 | /* | |
183 | * The host controller goes away pretty soon after this if | |
184 | * everything goes well so getting timeout is expected. | |
185 | */ | |
186 | ret = dma_port_flash_update_auth(sw->dma_port); | |
187 | return ret == -ETIMEDOUT ? 0 : ret; | |
188 | } | |
189 | ||
190 | /* | |
191 | * From safe mode we can get out by just power cycling the | |
192 | * switch. | |
193 | */ | |
194 | dma_port_power_cycle(sw->dma_port); | |
195 | return 0; | |
196 | } | |
197 | ||
198 | static int nvm_authenticate_device(struct tb_switch *sw) | |
199 | { | |
200 | int ret, retries = 10; | |
201 | ||
202 | ret = dma_port_flash_update_auth(sw->dma_port); | |
203 | if (ret && ret != -ETIMEDOUT) | |
204 | return ret; | |
205 | ||
206 | /* | |
207 | * Poll here for the authentication status. It takes some time | |
208 | * for the device to respond (we get timeout for a while). Once | |
209 | * we get response the device needs to be power cycled in order | |
210 | * to the new NVM to be taken into use. | |
211 | */ | |
212 | do { | |
213 | u32 status; | |
214 | ||
215 | ret = dma_port_flash_update_auth_status(sw->dma_port, &status); | |
216 | if (ret < 0 && ret != -ETIMEDOUT) | |
217 | return ret; | |
218 | if (ret > 0) { | |
219 | if (status) { | |
220 | tb_sw_warn(sw, "failed to authenticate NVM\n"); | |
221 | nvm_set_auth_status(sw, status); | |
222 | } | |
223 | ||
224 | tb_sw_info(sw, "power cycling the switch now\n"); | |
225 | dma_port_power_cycle(sw->dma_port); | |
226 | return 0; | |
227 | } | |
228 | ||
229 | msleep(500); | |
230 | } while (--retries); | |
231 | ||
232 | return -ETIMEDOUT; | |
233 | } | |
234 | ||
235 | static int tb_switch_nvm_read(void *priv, unsigned int offset, void *val, | |
236 | size_t bytes) | |
237 | { | |
238 | struct tb_switch *sw = priv; | |
2d8ff0b5 MW |
239 | int ret; |
240 | ||
241 | pm_runtime_get_sync(&sw->dev); | |
242 | ret = dma_port_flash_read(sw->dma_port, offset, val, bytes); | |
243 | pm_runtime_mark_last_busy(&sw->dev); | |
244 | pm_runtime_put_autosuspend(&sw->dev); | |
e6b245cc | 245 | |
2d8ff0b5 | 246 | return ret; |
e6b245cc MW |
247 | } |
248 | ||
249 | static int tb_switch_nvm_write(void *priv, unsigned int offset, void *val, | |
250 | size_t bytes) | |
251 | { | |
252 | struct tb_switch *sw = priv; | |
253 | int ret = 0; | |
254 | ||
09f11b6c MW |
255 | if (!mutex_trylock(&sw->tb->lock)) |
256 | return restart_syscall(); | |
e6b245cc MW |
257 | |
258 | /* | |
259 | * Since writing the NVM image might require some special steps, | |
260 | * for example when CSS headers are written, we cache the image | |
261 | * locally here and handle the special cases when the user asks | |
262 | * us to authenticate the image. | |
263 | */ | |
264 | if (!sw->nvm->buf) { | |
265 | sw->nvm->buf = vmalloc(NVM_MAX_SIZE); | |
266 | if (!sw->nvm->buf) { | |
267 | ret = -ENOMEM; | |
268 | goto unlock; | |
269 | } | |
270 | } | |
271 | ||
272 | sw->nvm->buf_data_size = offset + bytes; | |
273 | memcpy(sw->nvm->buf + offset, val, bytes); | |
274 | ||
275 | unlock: | |
09f11b6c | 276 | mutex_unlock(&sw->tb->lock); |
e6b245cc MW |
277 | |
278 | return ret; | |
279 | } | |
280 | ||
281 | static struct nvmem_device *register_nvmem(struct tb_switch *sw, int id, | |
282 | size_t size, bool active) | |
283 | { | |
284 | struct nvmem_config config; | |
285 | ||
286 | memset(&config, 0, sizeof(config)); | |
287 | ||
288 | if (active) { | |
289 | config.name = "nvm_active"; | |
290 | config.reg_read = tb_switch_nvm_read; | |
800161bd | 291 | config.read_only = true; |
e6b245cc MW |
292 | } else { |
293 | config.name = "nvm_non_active"; | |
294 | config.reg_write = tb_switch_nvm_write; | |
800161bd | 295 | config.root_only = true; |
e6b245cc MW |
296 | } |
297 | ||
298 | config.id = id; | |
299 | config.stride = 4; | |
300 | config.word_size = 4; | |
301 | config.size = size; | |
302 | config.dev = &sw->dev; | |
303 | config.owner = THIS_MODULE; | |
e6b245cc MW |
304 | config.priv = sw; |
305 | ||
306 | return nvmem_register(&config); | |
307 | } | |
308 | ||
309 | static int tb_switch_nvm_add(struct tb_switch *sw) | |
310 | { | |
311 | struct nvmem_device *nvm_dev; | |
312 | struct tb_switch_nvm *nvm; | |
313 | u32 val; | |
314 | int ret; | |
315 | ||
316 | if (!sw->dma_port) | |
317 | return 0; | |
318 | ||
319 | nvm = kzalloc(sizeof(*nvm), GFP_KERNEL); | |
320 | if (!nvm) | |
321 | return -ENOMEM; | |
322 | ||
323 | nvm->id = ida_simple_get(&nvm_ida, 0, 0, GFP_KERNEL); | |
324 | ||
325 | /* | |
326 | * If the switch is in safe-mode the only accessible portion of | |
327 | * the NVM is the non-active one where userspace is expected to | |
328 | * write new functional NVM. | |
329 | */ | |
330 | if (!sw->safe_mode) { | |
331 | u32 nvm_size, hdr_size; | |
332 | ||
333 | ret = dma_port_flash_read(sw->dma_port, NVM_FLASH_SIZE, &val, | |
334 | sizeof(val)); | |
335 | if (ret) | |
336 | goto err_ida; | |
337 | ||
338 | hdr_size = sw->generation < 3 ? SZ_8K : SZ_16K; | |
339 | nvm_size = (SZ_1M << (val & 7)) / 8; | |
340 | nvm_size = (nvm_size - hdr_size) / 2; | |
341 | ||
342 | ret = dma_port_flash_read(sw->dma_port, NVM_VERSION, &val, | |
343 | sizeof(val)); | |
344 | if (ret) | |
345 | goto err_ida; | |
346 | ||
347 | nvm->major = val >> 16; | |
348 | nvm->minor = val >> 8; | |
349 | ||
350 | nvm_dev = register_nvmem(sw, nvm->id, nvm_size, true); | |
351 | if (IS_ERR(nvm_dev)) { | |
352 | ret = PTR_ERR(nvm_dev); | |
353 | goto err_ida; | |
354 | } | |
355 | nvm->active = nvm_dev; | |
356 | } | |
357 | ||
358 | nvm_dev = register_nvmem(sw, nvm->id, NVM_MAX_SIZE, false); | |
359 | if (IS_ERR(nvm_dev)) { | |
360 | ret = PTR_ERR(nvm_dev); | |
361 | goto err_nvm_active; | |
362 | } | |
363 | nvm->non_active = nvm_dev; | |
364 | ||
e6b245cc | 365 | sw->nvm = nvm; |
e6b245cc MW |
366 | return 0; |
367 | ||
368 | err_nvm_active: | |
369 | if (nvm->active) | |
370 | nvmem_unregister(nvm->active); | |
371 | err_ida: | |
372 | ida_simple_remove(&nvm_ida, nvm->id); | |
373 | kfree(nvm); | |
374 | ||
375 | return ret; | |
376 | } | |
377 | ||
378 | static void tb_switch_nvm_remove(struct tb_switch *sw) | |
379 | { | |
380 | struct tb_switch_nvm *nvm; | |
381 | ||
e6b245cc MW |
382 | nvm = sw->nvm; |
383 | sw->nvm = NULL; | |
e6b245cc MW |
384 | |
385 | if (!nvm) | |
386 | return; | |
387 | ||
388 | /* Remove authentication status in case the switch is unplugged */ | |
389 | if (!nvm->authenticating) | |
390 | nvm_clear_auth_status(sw); | |
391 | ||
392 | nvmem_unregister(nvm->non_active); | |
393 | if (nvm->active) | |
394 | nvmem_unregister(nvm->active); | |
395 | ida_simple_remove(&nvm_ida, nvm->id); | |
396 | vfree(nvm->buf); | |
397 | kfree(nvm); | |
398 | } | |
399 | ||
a25c8b2f AN |
400 | /* port utility functions */ |
401 | ||
402 | static const char *tb_port_type(struct tb_regs_port_header *port) | |
403 | { | |
404 | switch (port->type >> 16) { | |
405 | case 0: | |
406 | switch ((u8) port->type) { | |
407 | case 0: | |
408 | return "Inactive"; | |
409 | case 1: | |
410 | return "Port"; | |
411 | case 2: | |
412 | return "NHI"; | |
413 | default: | |
414 | return "unknown"; | |
415 | } | |
416 | case 0x2: | |
417 | return "Ethernet"; | |
418 | case 0x8: | |
419 | return "SATA"; | |
420 | case 0xe: | |
421 | return "DP/HDMI"; | |
422 | case 0x10: | |
423 | return "PCIe"; | |
424 | case 0x20: | |
425 | return "USB"; | |
426 | default: | |
427 | return "unknown"; | |
428 | } | |
429 | } | |
430 | ||
431 | static void tb_dump_port(struct tb *tb, struct tb_regs_port_header *port) | |
432 | { | |
daa5140f MW |
433 | tb_dbg(tb, |
434 | " Port %d: %x:%x (Revision: %d, TB Version: %d, Type: %s (%#x))\n", | |
435 | port->port_number, port->vendor_id, port->device_id, | |
436 | port->revision, port->thunderbolt_version, tb_port_type(port), | |
437 | port->type); | |
438 | tb_dbg(tb, " Max hop id (in/out): %d/%d\n", | |
439 | port->max_in_hop_id, port->max_out_hop_id); | |
440 | tb_dbg(tb, " Max counters: %d\n", port->max_counters); | |
441 | tb_dbg(tb, " NFC Credits: %#x\n", port->nfc_credits); | |
a25c8b2f AN |
442 | } |
443 | ||
9da672a4 AN |
444 | /** |
445 | * tb_port_state() - get connectedness state of a port | |
446 | * | |
447 | * The port must have a TB_CAP_PHY (i.e. it should be a real port). | |
448 | * | |
449 | * Return: Returns an enum tb_port_state on success or an error code on failure. | |
450 | */ | |
451 | static int tb_port_state(struct tb_port *port) | |
452 | { | |
453 | struct tb_cap_phy phy; | |
454 | int res; | |
455 | if (port->cap_phy == 0) { | |
456 | tb_port_WARN(port, "does not have a PHY\n"); | |
457 | return -EINVAL; | |
458 | } | |
459 | res = tb_port_read(port, &phy, TB_CFG_PORT, port->cap_phy, 2); | |
460 | if (res) | |
461 | return res; | |
462 | return phy.state; | |
463 | } | |
464 | ||
465 | /** | |
466 | * tb_wait_for_port() - wait for a port to become ready | |
467 | * | |
468 | * Wait up to 1 second for a port to reach state TB_PORT_UP. If | |
469 | * wait_if_unplugged is set then we also wait if the port is in state | |
470 | * TB_PORT_UNPLUGGED (it takes a while for the device to be registered after | |
471 | * switch resume). Otherwise we only wait if a device is registered but the link | |
472 | * has not yet been established. | |
473 | * | |
474 | * Return: Returns an error code on failure. Returns 0 if the port is not | |
475 | * connected or failed to reach state TB_PORT_UP within one second. Returns 1 | |
476 | * if the port is connected and in state TB_PORT_UP. | |
477 | */ | |
478 | int tb_wait_for_port(struct tb_port *port, bool wait_if_unplugged) | |
479 | { | |
480 | int retries = 10; | |
481 | int state; | |
482 | if (!port->cap_phy) { | |
483 | tb_port_WARN(port, "does not have PHY\n"); | |
484 | return -EINVAL; | |
485 | } | |
486 | if (tb_is_upstream_port(port)) { | |
487 | tb_port_WARN(port, "is the upstream port\n"); | |
488 | return -EINVAL; | |
489 | } | |
490 | ||
491 | while (retries--) { | |
492 | state = tb_port_state(port); | |
493 | if (state < 0) | |
494 | return state; | |
495 | if (state == TB_PORT_DISABLED) { | |
496 | tb_port_info(port, "is disabled (state: 0)\n"); | |
497 | return 0; | |
498 | } | |
499 | if (state == TB_PORT_UNPLUGGED) { | |
500 | if (wait_if_unplugged) { | |
501 | /* used during resume */ | |
502 | tb_port_info(port, | |
503 | "is unplugged (state: 7), retrying...\n"); | |
504 | msleep(100); | |
505 | continue; | |
506 | } | |
507 | tb_port_info(port, "is unplugged (state: 7)\n"); | |
508 | return 0; | |
509 | } | |
510 | if (state == TB_PORT_UP) { | |
511 | tb_port_info(port, | |
512 | "is connected, link is up (state: 2)\n"); | |
513 | return 1; | |
514 | } | |
515 | ||
516 | /* | |
517 | * After plug-in the state is TB_PORT_CONNECTING. Give it some | |
518 | * time. | |
519 | */ | |
520 | tb_port_info(port, | |
521 | "is connected, link is not up (state: %d), retrying...\n", | |
522 | state); | |
523 | msleep(100); | |
524 | } | |
525 | tb_port_warn(port, | |
526 | "failed to reach state TB_PORT_UP. Ignoring port...\n"); | |
527 | return 0; | |
528 | } | |
529 | ||
520b6702 AN |
530 | /** |
531 | * tb_port_add_nfc_credits() - add/remove non flow controlled credits to port | |
532 | * | |
533 | * Change the number of NFC credits allocated to @port by @credits. To remove | |
534 | * NFC credits pass a negative amount of credits. | |
535 | * | |
536 | * Return: Returns 0 on success or an error code on failure. | |
537 | */ | |
538 | int tb_port_add_nfc_credits(struct tb_port *port, int credits) | |
539 | { | |
540 | if (credits == 0) | |
541 | return 0; | |
542 | tb_port_info(port, | |
543 | "adding %#x NFC credits (%#x -> %#x)", | |
544 | credits, | |
545 | port->config.nfc_credits, | |
546 | port->config.nfc_credits + credits); | |
547 | port->config.nfc_credits += credits; | |
548 | return tb_port_write(port, &port->config.nfc_credits, | |
549 | TB_CFG_PORT, 4, 1); | |
550 | } | |
551 | ||
552 | /** | |
553 | * tb_port_clear_counter() - clear a counter in TB_CFG_COUNTER | |
554 | * | |
555 | * Return: Returns 0 on success or an error code on failure. | |
556 | */ | |
557 | int tb_port_clear_counter(struct tb_port *port, int counter) | |
558 | { | |
559 | u32 zero[3] = { 0, 0, 0 }; | |
560 | tb_port_info(port, "clearing counter %d\n", counter); | |
561 | return tb_port_write(port, zero, TB_CFG_COUNTERS, 3 * counter, 3); | |
562 | } | |
563 | ||
a25c8b2f AN |
564 | /** |
565 | * tb_init_port() - initialize a port | |
566 | * | |
567 | * This is a helper method for tb_switch_alloc. Does not check or initialize | |
568 | * any downstream switches. | |
569 | * | |
570 | * Return: Returns 0 on success or an error code on failure. | |
571 | */ | |
343fcb8c | 572 | static int tb_init_port(struct tb_port *port) |
a25c8b2f AN |
573 | { |
574 | int res; | |
9da672a4 | 575 | int cap; |
343fcb8c | 576 | |
a25c8b2f AN |
577 | res = tb_port_read(port, &port->config, TB_CFG_PORT, 0, 8); |
578 | if (res) | |
579 | return res; | |
580 | ||
9da672a4 | 581 | /* Port 0 is the switch itself and has no PHY. */ |
343fcb8c | 582 | if (port->config.type == TB_TYPE_PORT && port->port != 0) { |
da2da04b | 583 | cap = tb_port_find_cap(port, TB_PORT_CAP_PHY); |
9da672a4 AN |
584 | |
585 | if (cap > 0) | |
586 | port->cap_phy = cap; | |
587 | else | |
588 | tb_port_WARN(port, "non switch port without a PHY\n"); | |
56183c88 MW |
589 | } else if (port->port != 0) { |
590 | cap = tb_port_find_cap(port, TB_PORT_CAP_ADAP); | |
591 | if (cap > 0) | |
592 | port->cap_adap = cap; | |
9da672a4 AN |
593 | } |
594 | ||
343fcb8c | 595 | tb_dump_port(port->sw->tb, &port->config); |
a25c8b2f AN |
596 | |
597 | /* TODO: Read dual link port, DP port and more from EEPROM. */ | |
598 | return 0; | |
599 | ||
600 | } | |
601 | ||
93f36ade MW |
602 | /** |
603 | * tb_pci_port_enable() - Enable PCIe adapter port | |
604 | * @port: PCIe port to enable | |
605 | * @enable: Enable/disable the PCIe adapter | |
606 | */ | |
607 | int tb_pci_port_enable(struct tb_port *port, bool enable) | |
608 | { | |
609 | u32 word = enable ? TB_PCI_EN : 0x0; | |
610 | if (!port->cap_adap) | |
611 | return -ENXIO; | |
612 | return tb_port_write(port, &word, TB_CFG_PORT, port->cap_adap, 1); | |
613 | } | |
614 | ||
a25c8b2f AN |
615 | /* switch utility functions */ |
616 | ||
617 | static void tb_dump_switch(struct tb *tb, struct tb_regs_switch_header *sw) | |
618 | { | |
daa5140f MW |
619 | tb_dbg(tb, " Switch: %x:%x (Revision: %d, TB Version: %d)\n", |
620 | sw->vendor_id, sw->device_id, sw->revision, | |
621 | sw->thunderbolt_version); | |
622 | tb_dbg(tb, " Max Port Number: %d\n", sw->max_port_number); | |
623 | tb_dbg(tb, " Config:\n"); | |
624 | tb_dbg(tb, | |
a25c8b2f | 625 | " Upstream Port Number: %d Depth: %d Route String: %#llx Enabled: %d, PlugEventsDelay: %dms\n", |
daa5140f MW |
626 | sw->upstream_port_number, sw->depth, |
627 | (((u64) sw->route_hi) << 32) | sw->route_lo, | |
628 | sw->enabled, sw->plug_events_delay); | |
629 | tb_dbg(tb, " unknown1: %#x unknown4: %#x\n", | |
630 | sw->__unknown1, sw->__unknown4); | |
a25c8b2f AN |
631 | } |
632 | ||
23dd5bb4 AN |
633 | /** |
634 | * reset_switch() - reconfigure route, enable and send TB_CFG_PKG_RESET | |
635 | * | |
636 | * Return: Returns 0 on success or an error code on failure. | |
637 | */ | |
638 | int tb_switch_reset(struct tb *tb, u64 route) | |
639 | { | |
640 | struct tb_cfg_result res; | |
641 | struct tb_regs_switch_header header = { | |
642 | header.route_hi = route >> 32, | |
643 | header.route_lo = route, | |
644 | header.enabled = true, | |
645 | }; | |
daa5140f | 646 | tb_dbg(tb, "resetting switch at %llx\n", route); |
23dd5bb4 AN |
647 | res.err = tb_cfg_write(tb->ctl, ((u32 *) &header) + 2, route, |
648 | 0, 2, 2, 2); | |
649 | if (res.err) | |
650 | return res.err; | |
651 | res = tb_cfg_reset(tb->ctl, route, TB_CFG_DEFAULT_TIMEOUT); | |
652 | if (res.err > 0) | |
653 | return -EIO; | |
654 | return res.err; | |
655 | } | |
656 | ||
ca389f71 AN |
657 | /** |
658 | * tb_plug_events_active() - enable/disable plug events on a switch | |
659 | * | |
660 | * Also configures a sane plug_events_delay of 255ms. | |
661 | * | |
662 | * Return: Returns 0 on success or an error code on failure. | |
663 | */ | |
664 | static int tb_plug_events_active(struct tb_switch *sw, bool active) | |
665 | { | |
666 | u32 data; | |
667 | int res; | |
668 | ||
bfe778ac MW |
669 | if (!sw->config.enabled) |
670 | return 0; | |
671 | ||
ca389f71 AN |
672 | sw->config.plug_events_delay = 0xff; |
673 | res = tb_sw_write(sw, ((u32 *) &sw->config) + 4, TB_CFG_SWITCH, 4, 1); | |
674 | if (res) | |
675 | return res; | |
676 | ||
677 | res = tb_sw_read(sw, &data, TB_CFG_SWITCH, sw->cap_plug_events + 1, 1); | |
678 | if (res) | |
679 | return res; | |
680 | ||
681 | if (active) { | |
682 | data = data & 0xFFFFFF83; | |
683 | switch (sw->config.device_id) { | |
1d111406 LW |
684 | case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE: |
685 | case PCI_DEVICE_ID_INTEL_EAGLE_RIDGE: | |
686 | case PCI_DEVICE_ID_INTEL_PORT_RIDGE: | |
ca389f71 AN |
687 | break; |
688 | default: | |
689 | data |= 4; | |
690 | } | |
691 | } else { | |
692 | data = data | 0x7c; | |
693 | } | |
694 | return tb_sw_write(sw, &data, TB_CFG_SWITCH, | |
695 | sw->cap_plug_events + 1, 1); | |
696 | } | |
697 | ||
f67cf491 MW |
698 | static ssize_t authorized_show(struct device *dev, |
699 | struct device_attribute *attr, | |
700 | char *buf) | |
701 | { | |
702 | struct tb_switch *sw = tb_to_switch(dev); | |
703 | ||
704 | return sprintf(buf, "%u\n", sw->authorized); | |
705 | } | |
706 | ||
707 | static int tb_switch_set_authorized(struct tb_switch *sw, unsigned int val) | |
708 | { | |
709 | int ret = -EINVAL; | |
710 | ||
09f11b6c MW |
711 | if (!mutex_trylock(&sw->tb->lock)) |
712 | return restart_syscall(); | |
f67cf491 MW |
713 | |
714 | if (sw->authorized) | |
715 | goto unlock; | |
716 | ||
a03e8289 MW |
717 | /* |
718 | * Make sure there is no PCIe rescan ongoing when a new PCIe | |
719 | * tunnel is created. Otherwise the PCIe rescan code might find | |
720 | * the new tunnel too early. | |
721 | */ | |
722 | pci_lock_rescan_remove(); | |
2d8ff0b5 | 723 | pm_runtime_get_sync(&sw->dev); |
a03e8289 | 724 | |
f67cf491 MW |
725 | switch (val) { |
726 | /* Approve switch */ | |
727 | case 1: | |
728 | if (sw->key) | |
729 | ret = tb_domain_approve_switch_key(sw->tb, sw); | |
730 | else | |
731 | ret = tb_domain_approve_switch(sw->tb, sw); | |
732 | break; | |
733 | ||
734 | /* Challenge switch */ | |
735 | case 2: | |
736 | if (sw->key) | |
737 | ret = tb_domain_challenge_switch_key(sw->tb, sw); | |
738 | break; | |
739 | ||
740 | default: | |
741 | break; | |
742 | } | |
743 | ||
2d8ff0b5 MW |
744 | pm_runtime_mark_last_busy(&sw->dev); |
745 | pm_runtime_put_autosuspend(&sw->dev); | |
a03e8289 MW |
746 | pci_unlock_rescan_remove(); |
747 | ||
f67cf491 MW |
748 | if (!ret) { |
749 | sw->authorized = val; | |
750 | /* Notify status change to the userspace */ | |
751 | kobject_uevent(&sw->dev.kobj, KOBJ_CHANGE); | |
752 | } | |
753 | ||
754 | unlock: | |
09f11b6c | 755 | mutex_unlock(&sw->tb->lock); |
f67cf491 MW |
756 | return ret; |
757 | } | |
758 | ||
759 | static ssize_t authorized_store(struct device *dev, | |
760 | struct device_attribute *attr, | |
761 | const char *buf, size_t count) | |
762 | { | |
763 | struct tb_switch *sw = tb_to_switch(dev); | |
764 | unsigned int val; | |
765 | ssize_t ret; | |
766 | ||
767 | ret = kstrtouint(buf, 0, &val); | |
768 | if (ret) | |
769 | return ret; | |
770 | if (val > 2) | |
771 | return -EINVAL; | |
772 | ||
773 | ret = tb_switch_set_authorized(sw, val); | |
774 | ||
775 | return ret ? ret : count; | |
776 | } | |
777 | static DEVICE_ATTR_RW(authorized); | |
778 | ||
14862ee3 YB |
779 | static ssize_t boot_show(struct device *dev, struct device_attribute *attr, |
780 | char *buf) | |
781 | { | |
782 | struct tb_switch *sw = tb_to_switch(dev); | |
783 | ||
784 | return sprintf(buf, "%u\n", sw->boot); | |
785 | } | |
786 | static DEVICE_ATTR_RO(boot); | |
787 | ||
bfe778ac MW |
788 | static ssize_t device_show(struct device *dev, struct device_attribute *attr, |
789 | char *buf) | |
790 | { | |
791 | struct tb_switch *sw = tb_to_switch(dev); | |
ca389f71 | 792 | |
bfe778ac MW |
793 | return sprintf(buf, "%#x\n", sw->device); |
794 | } | |
795 | static DEVICE_ATTR_RO(device); | |
796 | ||
72ee3390 MW |
797 | static ssize_t |
798 | device_name_show(struct device *dev, struct device_attribute *attr, char *buf) | |
799 | { | |
800 | struct tb_switch *sw = tb_to_switch(dev); | |
801 | ||
802 | return sprintf(buf, "%s\n", sw->device_name ? sw->device_name : ""); | |
803 | } | |
804 | static DEVICE_ATTR_RO(device_name); | |
805 | ||
f67cf491 MW |
806 | static ssize_t key_show(struct device *dev, struct device_attribute *attr, |
807 | char *buf) | |
808 | { | |
809 | struct tb_switch *sw = tb_to_switch(dev); | |
810 | ssize_t ret; | |
811 | ||
09f11b6c MW |
812 | if (!mutex_trylock(&sw->tb->lock)) |
813 | return restart_syscall(); | |
f67cf491 MW |
814 | |
815 | if (sw->key) | |
816 | ret = sprintf(buf, "%*phN\n", TB_SWITCH_KEY_SIZE, sw->key); | |
817 | else | |
818 | ret = sprintf(buf, "\n"); | |
819 | ||
09f11b6c | 820 | mutex_unlock(&sw->tb->lock); |
f67cf491 MW |
821 | return ret; |
822 | } | |
823 | ||
824 | static ssize_t key_store(struct device *dev, struct device_attribute *attr, | |
825 | const char *buf, size_t count) | |
826 | { | |
827 | struct tb_switch *sw = tb_to_switch(dev); | |
828 | u8 key[TB_SWITCH_KEY_SIZE]; | |
829 | ssize_t ret = count; | |
e545f0d8 | 830 | bool clear = false; |
f67cf491 | 831 | |
e545f0d8 BY |
832 | if (!strcmp(buf, "\n")) |
833 | clear = true; | |
834 | else if (hex2bin(key, buf, sizeof(key))) | |
f67cf491 MW |
835 | return -EINVAL; |
836 | ||
09f11b6c MW |
837 | if (!mutex_trylock(&sw->tb->lock)) |
838 | return restart_syscall(); | |
f67cf491 MW |
839 | |
840 | if (sw->authorized) { | |
841 | ret = -EBUSY; | |
842 | } else { | |
843 | kfree(sw->key); | |
e545f0d8 BY |
844 | if (clear) { |
845 | sw->key = NULL; | |
846 | } else { | |
847 | sw->key = kmemdup(key, sizeof(key), GFP_KERNEL); | |
848 | if (!sw->key) | |
849 | ret = -ENOMEM; | |
850 | } | |
f67cf491 MW |
851 | } |
852 | ||
09f11b6c | 853 | mutex_unlock(&sw->tb->lock); |
f67cf491 MW |
854 | return ret; |
855 | } | |
0956e411 | 856 | static DEVICE_ATTR(key, 0600, key_show, key_store); |
f67cf491 | 857 | |
1830b6ee MW |
858 | static void nvm_authenticate_start(struct tb_switch *sw) |
859 | { | |
860 | struct pci_dev *root_port; | |
861 | ||
862 | /* | |
863 | * During host router NVM upgrade we should not allow root port to | |
864 | * go into D3cold because some root ports cannot trigger PME | |
865 | * itself. To be on the safe side keep the root port in D0 during | |
866 | * the whole upgrade process. | |
867 | */ | |
868 | root_port = pci_find_pcie_root_port(sw->tb->nhi->pdev); | |
869 | if (root_port) | |
870 | pm_runtime_get_noresume(&root_port->dev); | |
871 | } | |
872 | ||
873 | static void nvm_authenticate_complete(struct tb_switch *sw) | |
874 | { | |
875 | struct pci_dev *root_port; | |
876 | ||
877 | root_port = pci_find_pcie_root_port(sw->tb->nhi->pdev); | |
878 | if (root_port) | |
879 | pm_runtime_put(&root_port->dev); | |
880 | } | |
881 | ||
e6b245cc MW |
882 | static ssize_t nvm_authenticate_show(struct device *dev, |
883 | struct device_attribute *attr, char *buf) | |
884 | { | |
885 | struct tb_switch *sw = tb_to_switch(dev); | |
886 | u32 status; | |
887 | ||
888 | nvm_get_auth_status(sw, &status); | |
889 | return sprintf(buf, "%#x\n", status); | |
890 | } | |
891 | ||
892 | static ssize_t nvm_authenticate_store(struct device *dev, | |
893 | struct device_attribute *attr, const char *buf, size_t count) | |
894 | { | |
895 | struct tb_switch *sw = tb_to_switch(dev); | |
896 | bool val; | |
897 | int ret; | |
898 | ||
09f11b6c MW |
899 | if (!mutex_trylock(&sw->tb->lock)) |
900 | return restart_syscall(); | |
e6b245cc MW |
901 | |
902 | /* If NVMem devices are not yet added */ | |
903 | if (!sw->nvm) { | |
904 | ret = -EAGAIN; | |
905 | goto exit_unlock; | |
906 | } | |
907 | ||
908 | ret = kstrtobool(buf, &val); | |
909 | if (ret) | |
910 | goto exit_unlock; | |
911 | ||
912 | /* Always clear the authentication status */ | |
913 | nvm_clear_auth_status(sw); | |
914 | ||
915 | if (val) { | |
2d8ff0b5 MW |
916 | if (!sw->nvm->buf) { |
917 | ret = -EINVAL; | |
918 | goto exit_unlock; | |
919 | } | |
920 | ||
921 | pm_runtime_get_sync(&sw->dev); | |
e6b245cc | 922 | ret = nvm_validate_and_write(sw); |
2d8ff0b5 MW |
923 | if (ret) { |
924 | pm_runtime_mark_last_busy(&sw->dev); | |
925 | pm_runtime_put_autosuspend(&sw->dev); | |
e6b245cc | 926 | goto exit_unlock; |
2d8ff0b5 | 927 | } |
e6b245cc MW |
928 | |
929 | sw->nvm->authenticating = true; | |
930 | ||
1830b6ee MW |
931 | if (!tb_route(sw)) { |
932 | /* | |
933 | * Keep root port from suspending as long as the | |
934 | * NVM upgrade process is running. | |
935 | */ | |
936 | nvm_authenticate_start(sw); | |
e6b245cc | 937 | ret = nvm_authenticate_host(sw); |
1830b6ee MW |
938 | if (ret) |
939 | nvm_authenticate_complete(sw); | |
940 | } else { | |
e6b245cc | 941 | ret = nvm_authenticate_device(sw); |
1830b6ee | 942 | } |
2d8ff0b5 MW |
943 | pm_runtime_mark_last_busy(&sw->dev); |
944 | pm_runtime_put_autosuspend(&sw->dev); | |
e6b245cc MW |
945 | } |
946 | ||
947 | exit_unlock: | |
09f11b6c | 948 | mutex_unlock(&sw->tb->lock); |
e6b245cc MW |
949 | |
950 | if (ret) | |
951 | return ret; | |
952 | return count; | |
953 | } | |
954 | static DEVICE_ATTR_RW(nvm_authenticate); | |
955 | ||
956 | static ssize_t nvm_version_show(struct device *dev, | |
957 | struct device_attribute *attr, char *buf) | |
958 | { | |
959 | struct tb_switch *sw = tb_to_switch(dev); | |
960 | int ret; | |
961 | ||
09f11b6c MW |
962 | if (!mutex_trylock(&sw->tb->lock)) |
963 | return restart_syscall(); | |
e6b245cc MW |
964 | |
965 | if (sw->safe_mode) | |
966 | ret = -ENODATA; | |
967 | else if (!sw->nvm) | |
968 | ret = -EAGAIN; | |
969 | else | |
970 | ret = sprintf(buf, "%x.%x\n", sw->nvm->major, sw->nvm->minor); | |
971 | ||
09f11b6c | 972 | mutex_unlock(&sw->tb->lock); |
e6b245cc MW |
973 | |
974 | return ret; | |
975 | } | |
976 | static DEVICE_ATTR_RO(nvm_version); | |
977 | ||
bfe778ac MW |
978 | static ssize_t vendor_show(struct device *dev, struct device_attribute *attr, |
979 | char *buf) | |
a25c8b2f | 980 | { |
bfe778ac | 981 | struct tb_switch *sw = tb_to_switch(dev); |
a25c8b2f | 982 | |
bfe778ac MW |
983 | return sprintf(buf, "%#x\n", sw->vendor); |
984 | } | |
985 | static DEVICE_ATTR_RO(vendor); | |
986 | ||
72ee3390 MW |
987 | static ssize_t |
988 | vendor_name_show(struct device *dev, struct device_attribute *attr, char *buf) | |
989 | { | |
990 | struct tb_switch *sw = tb_to_switch(dev); | |
991 | ||
992 | return sprintf(buf, "%s\n", sw->vendor_name ? sw->vendor_name : ""); | |
993 | } | |
994 | static DEVICE_ATTR_RO(vendor_name); | |
995 | ||
bfe778ac MW |
996 | static ssize_t unique_id_show(struct device *dev, struct device_attribute *attr, |
997 | char *buf) | |
998 | { | |
999 | struct tb_switch *sw = tb_to_switch(dev); | |
1000 | ||
1001 | return sprintf(buf, "%pUb\n", sw->uuid); | |
1002 | } | |
1003 | static DEVICE_ATTR_RO(unique_id); | |
1004 | ||
1005 | static struct attribute *switch_attrs[] = { | |
f67cf491 | 1006 | &dev_attr_authorized.attr, |
14862ee3 | 1007 | &dev_attr_boot.attr, |
bfe778ac | 1008 | &dev_attr_device.attr, |
72ee3390 | 1009 | &dev_attr_device_name.attr, |
f67cf491 | 1010 | &dev_attr_key.attr, |
e6b245cc MW |
1011 | &dev_attr_nvm_authenticate.attr, |
1012 | &dev_attr_nvm_version.attr, | |
bfe778ac | 1013 | &dev_attr_vendor.attr, |
72ee3390 | 1014 | &dev_attr_vendor_name.attr, |
bfe778ac MW |
1015 | &dev_attr_unique_id.attr, |
1016 | NULL, | |
1017 | }; | |
1018 | ||
f67cf491 MW |
1019 | static umode_t switch_attr_is_visible(struct kobject *kobj, |
1020 | struct attribute *attr, int n) | |
1021 | { | |
1022 | struct device *dev = container_of(kobj, struct device, kobj); | |
1023 | struct tb_switch *sw = tb_to_switch(dev); | |
1024 | ||
1025 | if (attr == &dev_attr_key.attr) { | |
1026 | if (tb_route(sw) && | |
1027 | sw->tb->security_level == TB_SECURITY_SECURE && | |
1028 | sw->security_level == TB_SECURITY_SECURE) | |
1029 | return attr->mode; | |
1030 | return 0; | |
e6b245cc MW |
1031 | } else if (attr == &dev_attr_nvm_authenticate.attr || |
1032 | attr == &dev_attr_nvm_version.attr) { | |
1033 | if (sw->dma_port) | |
1034 | return attr->mode; | |
1035 | return 0; | |
14862ee3 YB |
1036 | } else if (attr == &dev_attr_boot.attr) { |
1037 | if (tb_route(sw)) | |
1038 | return attr->mode; | |
1039 | return 0; | |
f67cf491 MW |
1040 | } |
1041 | ||
e6b245cc | 1042 | return sw->safe_mode ? 0 : attr->mode; |
f67cf491 MW |
1043 | } |
1044 | ||
bfe778ac | 1045 | static struct attribute_group switch_group = { |
f67cf491 | 1046 | .is_visible = switch_attr_is_visible, |
bfe778ac MW |
1047 | .attrs = switch_attrs, |
1048 | }; | |
ca389f71 | 1049 | |
bfe778ac MW |
1050 | static const struct attribute_group *switch_groups[] = { |
1051 | &switch_group, | |
1052 | NULL, | |
1053 | }; | |
1054 | ||
1055 | static void tb_switch_release(struct device *dev) | |
1056 | { | |
1057 | struct tb_switch *sw = tb_to_switch(dev); | |
1058 | ||
3e136768 MW |
1059 | dma_port_free(sw->dma_port); |
1060 | ||
bfe778ac | 1061 | kfree(sw->uuid); |
72ee3390 MW |
1062 | kfree(sw->device_name); |
1063 | kfree(sw->vendor_name); | |
a25c8b2f | 1064 | kfree(sw->ports); |
343fcb8c | 1065 | kfree(sw->drom); |
f67cf491 | 1066 | kfree(sw->key); |
a25c8b2f AN |
1067 | kfree(sw); |
1068 | } | |
1069 | ||
2d8ff0b5 MW |
1070 | /* |
1071 | * Currently only need to provide the callbacks. Everything else is handled | |
1072 | * in the connection manager. | |
1073 | */ | |
1074 | static int __maybe_unused tb_switch_runtime_suspend(struct device *dev) | |
1075 | { | |
1076 | return 0; | |
1077 | } | |
1078 | ||
1079 | static int __maybe_unused tb_switch_runtime_resume(struct device *dev) | |
1080 | { | |
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | static const struct dev_pm_ops tb_switch_pm_ops = { | |
1085 | SET_RUNTIME_PM_OPS(tb_switch_runtime_suspend, tb_switch_runtime_resume, | |
1086 | NULL) | |
1087 | }; | |
1088 | ||
bfe778ac MW |
1089 | struct device_type tb_switch_type = { |
1090 | .name = "thunderbolt_device", | |
1091 | .release = tb_switch_release, | |
2d8ff0b5 | 1092 | .pm = &tb_switch_pm_ops, |
bfe778ac MW |
1093 | }; |
1094 | ||
2c3c4197 MW |
1095 | static int tb_switch_get_generation(struct tb_switch *sw) |
1096 | { | |
1097 | switch (sw->config.device_id) { | |
1098 | case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE: | |
1099 | case PCI_DEVICE_ID_INTEL_EAGLE_RIDGE: | |
1100 | case PCI_DEVICE_ID_INTEL_LIGHT_PEAK: | |
1101 | case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_2C: | |
1102 | case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C: | |
1103 | case PCI_DEVICE_ID_INTEL_PORT_RIDGE: | |
1104 | case PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_BRIDGE: | |
1105 | case PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_BRIDGE: | |
1106 | return 1; | |
1107 | ||
1108 | case PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE: | |
1109 | case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE: | |
1110 | case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE: | |
1111 | return 2; | |
1112 | ||
1113 | case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE: | |
1114 | case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE: | |
1115 | case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE: | |
1116 | case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE: | |
1117 | case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE: | |
4bac471d RM |
1118 | case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE: |
1119 | case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE: | |
1120 | case PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE: | |
2c3c4197 MW |
1121 | return 3; |
1122 | ||
1123 | default: | |
1124 | /* | |
1125 | * For unknown switches assume generation to be 1 to be | |
1126 | * on the safe side. | |
1127 | */ | |
1128 | tb_sw_warn(sw, "unsupported switch device id %#x\n", | |
1129 | sw->config.device_id); | |
1130 | return 1; | |
1131 | } | |
1132 | } | |
1133 | ||
a25c8b2f | 1134 | /** |
bfe778ac MW |
1135 | * tb_switch_alloc() - allocate a switch |
1136 | * @tb: Pointer to the owning domain | |
1137 | * @parent: Parent device for this switch | |
1138 | * @route: Route string for this switch | |
a25c8b2f | 1139 | * |
bfe778ac MW |
1140 | * Allocates and initializes a switch. Will not upload configuration to |
1141 | * the switch. For that you need to call tb_switch_configure() | |
1142 | * separately. The returned switch should be released by calling | |
1143 | * tb_switch_put(). | |
1144 | * | |
1145 | * Return: Pointer to the allocated switch or %NULL in case of failure | |
a25c8b2f | 1146 | */ |
bfe778ac MW |
1147 | struct tb_switch *tb_switch_alloc(struct tb *tb, struct device *parent, |
1148 | u64 route) | |
a25c8b2f | 1149 | { |
a25c8b2f | 1150 | struct tb_switch *sw; |
f0342e75 MW |
1151 | int upstream_port; |
1152 | int i, cap, depth; | |
1153 | ||
1154 | /* Make sure we do not exceed maximum topology limit */ | |
1155 | depth = tb_route_length(route); | |
1156 | if (depth > TB_SWITCH_MAX_DEPTH) | |
1157 | return NULL; | |
1158 | ||
1159 | upstream_port = tb_cfg_get_upstream_port(tb->ctl, route); | |
a25c8b2f AN |
1160 | if (upstream_port < 0) |
1161 | return NULL; | |
1162 | ||
1163 | sw = kzalloc(sizeof(*sw), GFP_KERNEL); | |
1164 | if (!sw) | |
1165 | return NULL; | |
1166 | ||
1167 | sw->tb = tb; | |
aae20bb6 | 1168 | if (tb_cfg_read(tb->ctl, &sw->config, route, 0, TB_CFG_SWITCH, 0, 5)) |
bfe778ac MW |
1169 | goto err_free_sw_ports; |
1170 | ||
daa5140f | 1171 | tb_dbg(tb, "current switch config:\n"); |
a25c8b2f AN |
1172 | tb_dump_switch(tb, &sw->config); |
1173 | ||
1174 | /* configure switch */ | |
1175 | sw->config.upstream_port_number = upstream_port; | |
f0342e75 MW |
1176 | sw->config.depth = depth; |
1177 | sw->config.route_hi = upper_32_bits(route); | |
1178 | sw->config.route_lo = lower_32_bits(route); | |
bfe778ac | 1179 | sw->config.enabled = 0; |
a25c8b2f AN |
1180 | |
1181 | /* initialize ports */ | |
1182 | sw->ports = kcalloc(sw->config.max_port_number + 1, sizeof(*sw->ports), | |
343fcb8c | 1183 | GFP_KERNEL); |
a25c8b2f | 1184 | if (!sw->ports) |
bfe778ac | 1185 | goto err_free_sw_ports; |
a25c8b2f AN |
1186 | |
1187 | for (i = 0; i <= sw->config.max_port_number; i++) { | |
343fcb8c AN |
1188 | /* minimum setup for tb_find_cap and tb_drom_read to work */ |
1189 | sw->ports[i].sw = sw; | |
1190 | sw->ports[i].port = i; | |
a25c8b2f AN |
1191 | } |
1192 | ||
2c3c4197 MW |
1193 | sw->generation = tb_switch_get_generation(sw); |
1194 | ||
da2da04b | 1195 | cap = tb_switch_find_vse_cap(sw, TB_VSE_CAP_PLUG_EVENTS); |
ca389f71 | 1196 | if (cap < 0) { |
da2da04b | 1197 | tb_sw_warn(sw, "cannot find TB_VSE_CAP_PLUG_EVENTS aborting\n"); |
bfe778ac | 1198 | goto err_free_sw_ports; |
ca389f71 AN |
1199 | } |
1200 | sw->cap_plug_events = cap; | |
1201 | ||
a9be5582 MW |
1202 | cap = tb_switch_find_vse_cap(sw, TB_VSE_CAP_LINK_CONTROLLER); |
1203 | if (cap > 0) | |
1204 | sw->cap_lc = cap; | |
1205 | ||
f67cf491 MW |
1206 | /* Root switch is always authorized */ |
1207 | if (!route) | |
1208 | sw->authorized = true; | |
1209 | ||
bfe778ac MW |
1210 | device_initialize(&sw->dev); |
1211 | sw->dev.parent = parent; | |
1212 | sw->dev.bus = &tb_bus_type; | |
1213 | sw->dev.type = &tb_switch_type; | |
1214 | sw->dev.groups = switch_groups; | |
1215 | dev_set_name(&sw->dev, "%u-%llx", tb->index, tb_route(sw)); | |
1216 | ||
1217 | return sw; | |
1218 | ||
1219 | err_free_sw_ports: | |
1220 | kfree(sw->ports); | |
1221 | kfree(sw); | |
1222 | ||
1223 | return NULL; | |
1224 | } | |
1225 | ||
e6b245cc MW |
1226 | /** |
1227 | * tb_switch_alloc_safe_mode() - allocate a switch that is in safe mode | |
1228 | * @tb: Pointer to the owning domain | |
1229 | * @parent: Parent device for this switch | |
1230 | * @route: Route string for this switch | |
1231 | * | |
1232 | * This creates a switch in safe mode. This means the switch pretty much | |
1233 | * lacks all capabilities except DMA configuration port before it is | |
1234 | * flashed with a valid NVM firmware. | |
1235 | * | |
1236 | * The returned switch must be released by calling tb_switch_put(). | |
1237 | * | |
1238 | * Return: Pointer to the allocated switch or %NULL in case of failure | |
1239 | */ | |
1240 | struct tb_switch * | |
1241 | tb_switch_alloc_safe_mode(struct tb *tb, struct device *parent, u64 route) | |
1242 | { | |
1243 | struct tb_switch *sw; | |
1244 | ||
1245 | sw = kzalloc(sizeof(*sw), GFP_KERNEL); | |
1246 | if (!sw) | |
1247 | return NULL; | |
1248 | ||
1249 | sw->tb = tb; | |
1250 | sw->config.depth = tb_route_length(route); | |
1251 | sw->config.route_hi = upper_32_bits(route); | |
1252 | sw->config.route_lo = lower_32_bits(route); | |
1253 | sw->safe_mode = true; | |
1254 | ||
1255 | device_initialize(&sw->dev); | |
1256 | sw->dev.parent = parent; | |
1257 | sw->dev.bus = &tb_bus_type; | |
1258 | sw->dev.type = &tb_switch_type; | |
1259 | sw->dev.groups = switch_groups; | |
1260 | dev_set_name(&sw->dev, "%u-%llx", tb->index, tb_route(sw)); | |
1261 | ||
1262 | return sw; | |
1263 | } | |
1264 | ||
bfe778ac MW |
1265 | /** |
1266 | * tb_switch_configure() - Uploads configuration to the switch | |
1267 | * @sw: Switch to configure | |
1268 | * | |
1269 | * Call this function before the switch is added to the system. It will | |
1270 | * upload configuration to the switch and makes it available for the | |
1271 | * connection manager to use. | |
1272 | * | |
1273 | * Return: %0 in case of success and negative errno in case of failure | |
1274 | */ | |
1275 | int tb_switch_configure(struct tb_switch *sw) | |
1276 | { | |
1277 | struct tb *tb = sw->tb; | |
1278 | u64 route; | |
1279 | int ret; | |
1280 | ||
1281 | route = tb_route(sw); | |
daa5140f MW |
1282 | tb_dbg(tb, "initializing Switch at %#llx (depth: %d, up port: %d)\n", |
1283 | route, tb_route_length(route), sw->config.upstream_port_number); | |
bfe778ac MW |
1284 | |
1285 | if (sw->config.vendor_id != PCI_VENDOR_ID_INTEL) | |
1286 | tb_sw_warn(sw, "unknown switch vendor id %#x\n", | |
1287 | sw->config.vendor_id); | |
1288 | ||
bfe778ac MW |
1289 | sw->config.enabled = 1; |
1290 | ||
1291 | /* upload configuration */ | |
1292 | ret = tb_sw_write(sw, 1 + (u32 *)&sw->config, TB_CFG_SWITCH, 1, 3); | |
1293 | if (ret) | |
1294 | return ret; | |
1295 | ||
e879a709 MW |
1296 | ret = tb_lc_configure_link(sw); |
1297 | if (ret) | |
1298 | return ret; | |
1299 | ||
bfe778ac MW |
1300 | return tb_plug_events_active(sw, true); |
1301 | } | |
1302 | ||
2cc12751 | 1303 | static int tb_switch_set_uuid(struct tb_switch *sw) |
bfe778ac MW |
1304 | { |
1305 | u32 uuid[4]; | |
a9be5582 | 1306 | int ret; |
bfe778ac MW |
1307 | |
1308 | if (sw->uuid) | |
a9be5582 | 1309 | return 0; |
bfe778ac MW |
1310 | |
1311 | /* | |
1312 | * The newer controllers include fused UUID as part of link | |
1313 | * controller specific registers | |
1314 | */ | |
a9be5582 MW |
1315 | ret = tb_lc_read_uuid(sw, uuid); |
1316 | if (ret) { | |
bfe778ac MW |
1317 | /* |
1318 | * ICM generates UUID based on UID and fills the upper | |
1319 | * two words with ones. This is not strictly following | |
1320 | * UUID format but we want to be compatible with it so | |
1321 | * we do the same here. | |
1322 | */ | |
1323 | uuid[0] = sw->uid & 0xffffffff; | |
1324 | uuid[1] = (sw->uid >> 32) & 0xffffffff; | |
1325 | uuid[2] = 0xffffffff; | |
1326 | uuid[3] = 0xffffffff; | |
1327 | } | |
1328 | ||
1329 | sw->uuid = kmemdup(uuid, sizeof(uuid), GFP_KERNEL); | |
2cc12751 | 1330 | if (!sw->uuid) |
a9be5582 MW |
1331 | return -ENOMEM; |
1332 | return 0; | |
bfe778ac MW |
1333 | } |
1334 | ||
e6b245cc | 1335 | static int tb_switch_add_dma_port(struct tb_switch *sw) |
3e136768 | 1336 | { |
e6b245cc MW |
1337 | u32 status; |
1338 | int ret; | |
1339 | ||
3e136768 MW |
1340 | switch (sw->generation) { |
1341 | case 3: | |
1342 | break; | |
1343 | ||
1344 | case 2: | |
1345 | /* Only root switch can be upgraded */ | |
1346 | if (tb_route(sw)) | |
e6b245cc | 1347 | return 0; |
3e136768 MW |
1348 | break; |
1349 | ||
1350 | default: | |
e6b245cc MW |
1351 | /* |
1352 | * DMA port is the only thing available when the switch | |
1353 | * is in safe mode. | |
1354 | */ | |
1355 | if (!sw->safe_mode) | |
1356 | return 0; | |
1357 | break; | |
3e136768 MW |
1358 | } |
1359 | ||
e6b245cc MW |
1360 | if (sw->no_nvm_upgrade) |
1361 | return 0; | |
1362 | ||
3e136768 | 1363 | sw->dma_port = dma_port_alloc(sw); |
e6b245cc MW |
1364 | if (!sw->dma_port) |
1365 | return 0; | |
1366 | ||
1367 | /* | |
1368 | * Check status of the previous flash authentication. If there | |
1369 | * is one we need to power cycle the switch in any case to make | |
1370 | * it functional again. | |
1371 | */ | |
1372 | ret = dma_port_flash_update_auth_status(sw->dma_port, &status); | |
1373 | if (ret <= 0) | |
1374 | return ret; | |
1375 | ||
1830b6ee MW |
1376 | /* Now we can allow root port to suspend again */ |
1377 | if (!tb_route(sw)) | |
1378 | nvm_authenticate_complete(sw); | |
1379 | ||
e6b245cc MW |
1380 | if (status) { |
1381 | tb_sw_info(sw, "switch flash authentication failed\n"); | |
2cc12751 AP |
1382 | ret = tb_switch_set_uuid(sw); |
1383 | if (ret) | |
1384 | return ret; | |
e6b245cc MW |
1385 | nvm_set_auth_status(sw, status); |
1386 | } | |
1387 | ||
1388 | tb_sw_info(sw, "power cycling the switch now\n"); | |
1389 | dma_port_power_cycle(sw->dma_port); | |
1390 | ||
1391 | /* | |
1392 | * We return error here which causes the switch adding failure. | |
1393 | * It should appear back after power cycle is complete. | |
1394 | */ | |
1395 | return -ESHUTDOWN; | |
3e136768 MW |
1396 | } |
1397 | ||
bfe778ac MW |
1398 | /** |
1399 | * tb_switch_add() - Add a switch to the domain | |
1400 | * @sw: Switch to add | |
1401 | * | |
1402 | * This is the last step in adding switch to the domain. It will read | |
1403 | * identification information from DROM and initializes ports so that | |
1404 | * they can be used to connect other switches. The switch will be | |
1405 | * exposed to the userspace when this function successfully returns. To | |
1406 | * remove and release the switch, call tb_switch_remove(). | |
1407 | * | |
1408 | * Return: %0 in case of success and negative errno in case of failure | |
1409 | */ | |
1410 | int tb_switch_add(struct tb_switch *sw) | |
1411 | { | |
1412 | int i, ret; | |
1413 | ||
3e136768 MW |
1414 | /* |
1415 | * Initialize DMA control port now before we read DROM. Recent | |
1416 | * host controllers have more complete DROM on NVM that includes | |
1417 | * vendor and model identification strings which we then expose | |
1418 | * to the userspace. NVM can be accessed through DMA | |
1419 | * configuration based mailbox. | |
1420 | */ | |
e6b245cc MW |
1421 | ret = tb_switch_add_dma_port(sw); |
1422 | if (ret) | |
f53e7676 | 1423 | return ret; |
343fcb8c | 1424 | |
e6b245cc MW |
1425 | if (!sw->safe_mode) { |
1426 | /* read drom */ | |
1427 | ret = tb_drom_read(sw); | |
1428 | if (ret) { | |
1429 | tb_sw_warn(sw, "tb_eeprom_read_rom failed\n"); | |
1430 | return ret; | |
1431 | } | |
daa5140f | 1432 | tb_sw_dbg(sw, "uid: %#llx\n", sw->uid); |
bfe778ac | 1433 | |
2cc12751 AP |
1434 | ret = tb_switch_set_uuid(sw); |
1435 | if (ret) | |
1436 | return ret; | |
e6b245cc MW |
1437 | |
1438 | for (i = 0; i <= sw->config.max_port_number; i++) { | |
1439 | if (sw->ports[i].disabled) { | |
daa5140f | 1440 | tb_port_dbg(&sw->ports[i], "disabled by eeprom\n"); |
e6b245cc MW |
1441 | continue; |
1442 | } | |
1443 | ret = tb_init_port(&sw->ports[i]); | |
1444 | if (ret) | |
1445 | return ret; | |
343fcb8c | 1446 | } |
343fcb8c AN |
1447 | } |
1448 | ||
e6b245cc MW |
1449 | ret = device_add(&sw->dev); |
1450 | if (ret) | |
1451 | return ret; | |
1452 | ||
a83bc4a5 MW |
1453 | if (tb_route(sw)) { |
1454 | dev_info(&sw->dev, "new device found, vendor=%#x device=%#x\n", | |
1455 | sw->vendor, sw->device); | |
1456 | if (sw->vendor_name && sw->device_name) | |
1457 | dev_info(&sw->dev, "%s %s\n", sw->vendor_name, | |
1458 | sw->device_name); | |
1459 | } | |
1460 | ||
e6b245cc | 1461 | ret = tb_switch_nvm_add(sw); |
2d8ff0b5 | 1462 | if (ret) { |
e6b245cc | 1463 | device_del(&sw->dev); |
2d8ff0b5 MW |
1464 | return ret; |
1465 | } | |
e6b245cc | 1466 | |
2d8ff0b5 MW |
1467 | pm_runtime_set_active(&sw->dev); |
1468 | if (sw->rpm) { | |
1469 | pm_runtime_set_autosuspend_delay(&sw->dev, TB_AUTOSUSPEND_DELAY); | |
1470 | pm_runtime_use_autosuspend(&sw->dev); | |
1471 | pm_runtime_mark_last_busy(&sw->dev); | |
1472 | pm_runtime_enable(&sw->dev); | |
1473 | pm_request_autosuspend(&sw->dev); | |
1474 | } | |
1475 | ||
1476 | return 0; | |
bfe778ac | 1477 | } |
c90553b3 | 1478 | |
bfe778ac MW |
1479 | /** |
1480 | * tb_switch_remove() - Remove and release a switch | |
1481 | * @sw: Switch to remove | |
1482 | * | |
1483 | * This will remove the switch from the domain and release it after last | |
1484 | * reference count drops to zero. If there are switches connected below | |
1485 | * this switch, they will be removed as well. | |
1486 | */ | |
1487 | void tb_switch_remove(struct tb_switch *sw) | |
1488 | { | |
1489 | int i; | |
ca389f71 | 1490 | |
2d8ff0b5 MW |
1491 | if (sw->rpm) { |
1492 | pm_runtime_get_sync(&sw->dev); | |
1493 | pm_runtime_disable(&sw->dev); | |
1494 | } | |
1495 | ||
bfe778ac MW |
1496 | /* port 0 is the switch itself and never has a remote */ |
1497 | for (i = 1; i <= sw->config.max_port_number; i++) { | |
1498 | if (tb_is_upstream_port(&sw->ports[i])) | |
1499 | continue; | |
1500 | if (sw->ports[i].remote) | |
1501 | tb_switch_remove(sw->ports[i].remote->sw); | |
1502 | sw->ports[i].remote = NULL; | |
d1ff7024 MW |
1503 | if (sw->ports[i].xdomain) |
1504 | tb_xdomain_remove(sw->ports[i].xdomain); | |
1505 | sw->ports[i].xdomain = NULL; | |
bfe778ac MW |
1506 | } |
1507 | ||
1508 | if (!sw->is_unplugged) | |
1509 | tb_plug_events_active(sw, false); | |
e879a709 | 1510 | tb_lc_unconfigure_link(sw); |
bfe778ac | 1511 | |
e6b245cc | 1512 | tb_switch_nvm_remove(sw); |
a83bc4a5 MW |
1513 | |
1514 | if (tb_route(sw)) | |
1515 | dev_info(&sw->dev, "device disconnected\n"); | |
bfe778ac | 1516 | device_unregister(&sw->dev); |
a25c8b2f AN |
1517 | } |
1518 | ||
053596d9 | 1519 | /** |
aae20bb6 | 1520 | * tb_sw_set_unplugged() - set is_unplugged on switch and downstream switches |
053596d9 | 1521 | */ |
aae20bb6 | 1522 | void tb_sw_set_unplugged(struct tb_switch *sw) |
053596d9 AN |
1523 | { |
1524 | int i; | |
1525 | if (sw == sw->tb->root_switch) { | |
1526 | tb_sw_WARN(sw, "cannot unplug root switch\n"); | |
1527 | return; | |
1528 | } | |
1529 | if (sw->is_unplugged) { | |
1530 | tb_sw_WARN(sw, "is_unplugged already set\n"); | |
1531 | return; | |
1532 | } | |
1533 | sw->is_unplugged = true; | |
1534 | for (i = 0; i <= sw->config.max_port_number; i++) { | |
1535 | if (!tb_is_upstream_port(&sw->ports[i]) && sw->ports[i].remote) | |
aae20bb6 | 1536 | tb_sw_set_unplugged(sw->ports[i].remote->sw); |
053596d9 AN |
1537 | } |
1538 | } | |
1539 | ||
23dd5bb4 AN |
1540 | int tb_switch_resume(struct tb_switch *sw) |
1541 | { | |
1542 | int i, err; | |
daa5140f | 1543 | tb_sw_dbg(sw, "resuming switch\n"); |
23dd5bb4 | 1544 | |
08a5e4ce MW |
1545 | /* |
1546 | * Check for UID of the connected switches except for root | |
1547 | * switch which we assume cannot be removed. | |
1548 | */ | |
1549 | if (tb_route(sw)) { | |
1550 | u64 uid; | |
1551 | ||
1552 | err = tb_drom_read_uid_only(sw, &uid); | |
1553 | if (err) { | |
1554 | tb_sw_warn(sw, "uid read failed\n"); | |
1555 | return err; | |
1556 | } | |
1557 | if (sw->uid != uid) { | |
1558 | tb_sw_info(sw, | |
1559 | "changed while suspended (uid %#llx -> %#llx)\n", | |
1560 | sw->uid, uid); | |
1561 | return -ENODEV; | |
1562 | } | |
23dd5bb4 AN |
1563 | } |
1564 | ||
1565 | /* upload configuration */ | |
1566 | err = tb_sw_write(sw, 1 + (u32 *) &sw->config, TB_CFG_SWITCH, 1, 3); | |
1567 | if (err) | |
1568 | return err; | |
1569 | ||
e879a709 MW |
1570 | err = tb_lc_configure_link(sw); |
1571 | if (err) | |
1572 | return err; | |
1573 | ||
23dd5bb4 AN |
1574 | err = tb_plug_events_active(sw, true); |
1575 | if (err) | |
1576 | return err; | |
1577 | ||
1578 | /* check for surviving downstream switches */ | |
1579 | for (i = 1; i <= sw->config.max_port_number; i++) { | |
1580 | struct tb_port *port = &sw->ports[i]; | |
1581 | if (tb_is_upstream_port(port)) | |
1582 | continue; | |
1583 | if (!port->remote) | |
1584 | continue; | |
1585 | if (tb_wait_for_port(port, true) <= 0 | |
1586 | || tb_switch_resume(port->remote->sw)) { | |
1587 | tb_port_warn(port, | |
1588 | "lost during suspend, disconnecting\n"); | |
aae20bb6 | 1589 | tb_sw_set_unplugged(port->remote->sw); |
23dd5bb4 AN |
1590 | } |
1591 | } | |
1592 | return 0; | |
1593 | } | |
1594 | ||
1595 | void tb_switch_suspend(struct tb_switch *sw) | |
1596 | { | |
1597 | int i, err; | |
1598 | err = tb_plug_events_active(sw, false); | |
1599 | if (err) | |
1600 | return; | |
1601 | ||
1602 | for (i = 1; i <= sw->config.max_port_number; i++) { | |
1603 | if (!tb_is_upstream_port(&sw->ports[i]) && sw->ports[i].remote) | |
1604 | tb_switch_suspend(sw->ports[i].remote->sw); | |
1605 | } | |
5480dfc2 MW |
1606 | |
1607 | tb_lc_set_sleep(sw); | |
23dd5bb4 | 1608 | } |
f67cf491 MW |
1609 | |
1610 | struct tb_sw_lookup { | |
1611 | struct tb *tb; | |
1612 | u8 link; | |
1613 | u8 depth; | |
7c39ffe7 | 1614 | const uuid_t *uuid; |
8e9267bb | 1615 | u64 route; |
f67cf491 MW |
1616 | }; |
1617 | ||
1618 | static int tb_switch_match(struct device *dev, void *data) | |
1619 | { | |
1620 | struct tb_switch *sw = tb_to_switch(dev); | |
1621 | struct tb_sw_lookup *lookup = data; | |
1622 | ||
1623 | if (!sw) | |
1624 | return 0; | |
1625 | if (sw->tb != lookup->tb) | |
1626 | return 0; | |
1627 | ||
1628 | if (lookup->uuid) | |
1629 | return !memcmp(sw->uuid, lookup->uuid, sizeof(*lookup->uuid)); | |
1630 | ||
8e9267bb RM |
1631 | if (lookup->route) { |
1632 | return sw->config.route_lo == lower_32_bits(lookup->route) && | |
1633 | sw->config.route_hi == upper_32_bits(lookup->route); | |
1634 | } | |
1635 | ||
f67cf491 MW |
1636 | /* Root switch is matched only by depth */ |
1637 | if (!lookup->depth) | |
1638 | return !sw->depth; | |
1639 | ||
1640 | return sw->link == lookup->link && sw->depth == lookup->depth; | |
1641 | } | |
1642 | ||
1643 | /** | |
1644 | * tb_switch_find_by_link_depth() - Find switch by link and depth | |
1645 | * @tb: Domain the switch belongs | |
1646 | * @link: Link number the switch is connected | |
1647 | * @depth: Depth of the switch in link | |
1648 | * | |
1649 | * Returned switch has reference count increased so the caller needs to | |
1650 | * call tb_switch_put() when done with the switch. | |
1651 | */ | |
1652 | struct tb_switch *tb_switch_find_by_link_depth(struct tb *tb, u8 link, u8 depth) | |
1653 | { | |
1654 | struct tb_sw_lookup lookup; | |
1655 | struct device *dev; | |
1656 | ||
1657 | memset(&lookup, 0, sizeof(lookup)); | |
1658 | lookup.tb = tb; | |
1659 | lookup.link = link; | |
1660 | lookup.depth = depth; | |
1661 | ||
1662 | dev = bus_find_device(&tb_bus_type, NULL, &lookup, tb_switch_match); | |
1663 | if (dev) | |
1664 | return tb_to_switch(dev); | |
1665 | ||
1666 | return NULL; | |
1667 | } | |
1668 | ||
1669 | /** | |
432019d6 | 1670 | * tb_switch_find_by_uuid() - Find switch by UUID |
f67cf491 MW |
1671 | * @tb: Domain the switch belongs |
1672 | * @uuid: UUID to look for | |
1673 | * | |
1674 | * Returned switch has reference count increased so the caller needs to | |
1675 | * call tb_switch_put() when done with the switch. | |
1676 | */ | |
7c39ffe7 | 1677 | struct tb_switch *tb_switch_find_by_uuid(struct tb *tb, const uuid_t *uuid) |
f67cf491 MW |
1678 | { |
1679 | struct tb_sw_lookup lookup; | |
1680 | struct device *dev; | |
1681 | ||
1682 | memset(&lookup, 0, sizeof(lookup)); | |
1683 | lookup.tb = tb; | |
1684 | lookup.uuid = uuid; | |
1685 | ||
1686 | dev = bus_find_device(&tb_bus_type, NULL, &lookup, tb_switch_match); | |
1687 | if (dev) | |
1688 | return tb_to_switch(dev); | |
1689 | ||
1690 | return NULL; | |
1691 | } | |
e6b245cc | 1692 | |
8e9267bb RM |
1693 | /** |
1694 | * tb_switch_find_by_route() - Find switch by route string | |
1695 | * @tb: Domain the switch belongs | |
1696 | * @route: Route string to look for | |
1697 | * | |
1698 | * Returned switch has reference count increased so the caller needs to | |
1699 | * call tb_switch_put() when done with the switch. | |
1700 | */ | |
1701 | struct tb_switch *tb_switch_find_by_route(struct tb *tb, u64 route) | |
1702 | { | |
1703 | struct tb_sw_lookup lookup; | |
1704 | struct device *dev; | |
1705 | ||
1706 | if (!route) | |
1707 | return tb_switch_get(tb->root_switch); | |
1708 | ||
1709 | memset(&lookup, 0, sizeof(lookup)); | |
1710 | lookup.tb = tb; | |
1711 | lookup.route = route; | |
1712 | ||
1713 | dev = bus_find_device(&tb_bus_type, NULL, &lookup, tb_switch_match); | |
1714 | if (dev) | |
1715 | return tb_to_switch(dev); | |
1716 | ||
1717 | return NULL; | |
1718 | } | |
1719 | ||
e6b245cc MW |
1720 | void tb_switch_exit(void) |
1721 | { | |
1722 | ida_destroy(&nvm_ida); | |
1723 | } |