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32af9434 MW |
1 | /* |
2 | * Thunderbolt control channel messages | |
3 | * | |
4 | * Copyright (C) 2014 Andreas Noever <andreas.noever@gmail.com> | |
5 | * Copyright (C) 2017, Intel Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #ifndef _TB_MSGS | |
13 | #define _TB_MSGS | |
14 | ||
15 | #include <linux/types.h> | |
f67cf491 | 16 | #include <linux/uuid.h> |
32af9434 | 17 | |
32af9434 MW |
18 | enum tb_cfg_space { |
19 | TB_CFG_HOPS = 0, | |
20 | TB_CFG_PORT = 1, | |
21 | TB_CFG_SWITCH = 2, | |
22 | TB_CFG_COUNTERS = 3, | |
23 | }; | |
24 | ||
25 | enum tb_cfg_error { | |
26 | TB_CFG_ERROR_PORT_NOT_CONNECTED = 0, | |
27 | TB_CFG_ERROR_LINK_ERROR = 1, | |
28 | TB_CFG_ERROR_INVALID_CONFIG_SPACE = 2, | |
29 | TB_CFG_ERROR_NO_SUCH_PORT = 4, | |
30 | TB_CFG_ERROR_ACK_PLUG_EVENT = 7, /* send as reply to TB_CFG_PKG_EVENT */ | |
31 | TB_CFG_ERROR_LOOP = 8, | |
32 | TB_CFG_ERROR_HEC_ERROR_DETECTED = 12, | |
33 | TB_CFG_ERROR_FLOW_CONTROL_ERROR = 13, | |
34 | }; | |
35 | ||
36 | /* common header */ | |
37 | struct tb_cfg_header { | |
38 | u32 route_hi:22; | |
39 | u32 unknown:10; /* highest order bit is set on replies */ | |
40 | u32 route_lo; | |
41 | } __packed; | |
42 | ||
43 | /* additional header for read/write packets */ | |
44 | struct tb_cfg_address { | |
45 | u32 offset:13; /* in dwords */ | |
46 | u32 length:6; /* in dwords */ | |
47 | u32 port:6; | |
48 | enum tb_cfg_space space:2; | |
49 | u32 seq:2; /* sequence number */ | |
50 | u32 zero:3; | |
51 | } __packed; | |
52 | ||
53 | /* TB_CFG_PKG_READ, response for TB_CFG_PKG_WRITE */ | |
54 | struct cfg_read_pkg { | |
55 | struct tb_cfg_header header; | |
56 | struct tb_cfg_address addr; | |
57 | } __packed; | |
58 | ||
59 | /* TB_CFG_PKG_WRITE, response for TB_CFG_PKG_READ */ | |
60 | struct cfg_write_pkg { | |
61 | struct tb_cfg_header header; | |
62 | struct tb_cfg_address addr; | |
63 | u32 data[64]; /* maximum size, tb_cfg_address.length has 6 bits */ | |
64 | } __packed; | |
65 | ||
66 | /* TB_CFG_PKG_ERROR */ | |
67 | struct cfg_error_pkg { | |
68 | struct tb_cfg_header header; | |
69 | enum tb_cfg_error error:4; | |
70 | u32 zero1:4; | |
71 | u32 port:6; | |
72 | u32 zero2:2; /* Both should be zero, still they are different fields. */ | |
73 | u32 zero3:16; | |
74 | } __packed; | |
75 | ||
76 | /* TB_CFG_PKG_EVENT */ | |
77 | struct cfg_event_pkg { | |
78 | struct tb_cfg_header header; | |
79 | u32 port:6; | |
80 | u32 zero:25; | |
81 | bool unplug:1; | |
82 | } __packed; | |
83 | ||
84 | /* TB_CFG_PKG_RESET */ | |
85 | struct cfg_reset_pkg { | |
86 | struct tb_cfg_header header; | |
87 | } __packed; | |
88 | ||
89 | /* TB_CFG_PKG_PREPARE_TO_SLEEP */ | |
90 | struct cfg_pts_pkg { | |
91 | struct tb_cfg_header header; | |
92 | u32 data; | |
93 | } __packed; | |
94 | ||
f67cf491 MW |
95 | /* ICM messages */ |
96 | ||
97 | enum icm_pkg_code { | |
98 | ICM_GET_TOPOLOGY = 0x1, | |
99 | ICM_DRIVER_READY = 0x3, | |
100 | ICM_APPROVE_DEVICE = 0x4, | |
101 | ICM_CHALLENGE_DEVICE = 0x5, | |
102 | ICM_ADD_DEVICE_KEY = 0x6, | |
103 | ICM_GET_ROUTE = 0xa, | |
d1ff7024 | 104 | ICM_APPROVE_XDOMAIN = 0x10, |
d1d8b263 | 105 | ICM_DISCONNECT_XDOMAIN = 0x11, |
afa11ff5 | 106 | ICM_PREBOOT_ACL = 0x18, |
f67cf491 MW |
107 | }; |
108 | ||
109 | enum icm_event_code { | |
110 | ICM_EVENT_DEVICE_CONNECTED = 3, | |
111 | ICM_EVENT_DEVICE_DISCONNECTED = 4, | |
d1ff7024 MW |
112 | ICM_EVENT_XDOMAIN_CONNECTED = 6, |
113 | ICM_EVENT_XDOMAIN_DISCONNECTED = 7, | |
f67cf491 MW |
114 | }; |
115 | ||
116 | struct icm_pkg_header { | |
117 | u8 code; | |
118 | u8 flags; | |
119 | u8 packet_id; | |
120 | u8 total_packets; | |
80671708 | 121 | }; |
f67cf491 MW |
122 | |
123 | #define ICM_FLAGS_ERROR BIT(0) | |
124 | #define ICM_FLAGS_NO_KEY BIT(1) | |
125 | #define ICM_FLAGS_SLEVEL_SHIFT 3 | |
126 | #define ICM_FLAGS_SLEVEL_MASK GENMASK(4, 3) | |
afa11ff5 | 127 | #define ICM_FLAGS_WRITE BIT(7) |
f67cf491 MW |
128 | |
129 | struct icm_pkg_driver_ready { | |
130 | struct icm_pkg_header hdr; | |
80671708 | 131 | }; |
f67cf491 | 132 | |
afa11ff5 | 133 | /* Falcon Ridge only messages */ |
c1c79d65 MW |
134 | |
135 | struct icm_fr_pkg_driver_ready_response { | |
f67cf491 MW |
136 | struct icm_pkg_header hdr; |
137 | u8 romver; | |
138 | u8 ramver; | |
139 | u16 security_level; | |
80671708 | 140 | }; |
f67cf491 | 141 | |
c1c79d65 | 142 | #define ICM_FR_SLEVEL_MASK 0xf |
f67cf491 | 143 | |
afa11ff5 MW |
144 | /* Falcon Ridge & Alpine Ridge common messages */ |
145 | ||
f67cf491 MW |
146 | struct icm_fr_pkg_get_topology { |
147 | struct icm_pkg_header hdr; | |
80671708 | 148 | }; |
f67cf491 MW |
149 | |
150 | #define ICM_GET_TOPOLOGY_PACKETS 14 | |
151 | ||
152 | struct icm_fr_pkg_get_topology_response { | |
153 | struct icm_pkg_header hdr; | |
154 | u32 route_lo; | |
155 | u32 route_hi; | |
156 | u8 first_data; | |
157 | u8 second_data; | |
158 | u8 drom_i2c_address_index; | |
159 | u8 switch_index; | |
160 | u32 reserved[2]; | |
161 | u32 ports[16]; | |
162 | u32 port_hop_info[16]; | |
80671708 | 163 | }; |
f67cf491 MW |
164 | |
165 | #define ICM_SWITCH_USED BIT(0) | |
166 | #define ICM_SWITCH_UPSTREAM_PORT_MASK GENMASK(7, 1) | |
167 | #define ICM_SWITCH_UPSTREAM_PORT_SHIFT 1 | |
168 | ||
169 | #define ICM_PORT_TYPE_MASK GENMASK(23, 0) | |
170 | #define ICM_PORT_INDEX_SHIFT 24 | |
171 | #define ICM_PORT_INDEX_MASK GENMASK(31, 24) | |
172 | ||
173 | struct icm_fr_event_device_connected { | |
174 | struct icm_pkg_header hdr; | |
7c39ffe7 | 175 | uuid_t ep_uuid; |
f67cf491 MW |
176 | u8 connection_key; |
177 | u8 connection_id; | |
178 | u16 link_info; | |
179 | u32 ep_name[55]; | |
80671708 | 180 | }; |
f67cf491 MW |
181 | |
182 | #define ICM_LINK_INFO_LINK_MASK 0x7 | |
183 | #define ICM_LINK_INFO_DEPTH_SHIFT 4 | |
184 | #define ICM_LINK_INFO_DEPTH_MASK GENMASK(7, 4) | |
185 | #define ICM_LINK_INFO_APPROVED BIT(8) | |
38604142 | 186 | #define ICM_LINK_INFO_REJECTED BIT(9) |
269f6def | 187 | #define ICM_LINK_INFO_BOOT BIT(10) |
f67cf491 MW |
188 | |
189 | struct icm_fr_pkg_approve_device { | |
190 | struct icm_pkg_header hdr; | |
7c39ffe7 | 191 | uuid_t ep_uuid; |
f67cf491 MW |
192 | u8 connection_key; |
193 | u8 connection_id; | |
194 | u16 reserved; | |
80671708 | 195 | }; |
f67cf491 MW |
196 | |
197 | struct icm_fr_event_device_disconnected { | |
198 | struct icm_pkg_header hdr; | |
199 | u16 reserved; | |
200 | u16 link_info; | |
80671708 | 201 | }; |
f67cf491 | 202 | |
d1ff7024 MW |
203 | struct icm_fr_event_xdomain_connected { |
204 | struct icm_pkg_header hdr; | |
205 | u16 reserved; | |
206 | u16 link_info; | |
207 | uuid_t remote_uuid; | |
208 | uuid_t local_uuid; | |
209 | u32 local_route_hi; | |
210 | u32 local_route_lo; | |
211 | u32 remote_route_hi; | |
212 | u32 remote_route_lo; | |
213 | }; | |
214 | ||
215 | struct icm_fr_event_xdomain_disconnected { | |
216 | struct icm_pkg_header hdr; | |
217 | u16 reserved; | |
218 | u16 link_info; | |
219 | uuid_t remote_uuid; | |
220 | }; | |
221 | ||
f67cf491 MW |
222 | struct icm_fr_pkg_add_device_key { |
223 | struct icm_pkg_header hdr; | |
7c39ffe7 | 224 | uuid_t ep_uuid; |
f67cf491 MW |
225 | u8 connection_key; |
226 | u8 connection_id; | |
227 | u16 reserved; | |
228 | u32 key[8]; | |
80671708 | 229 | }; |
f67cf491 MW |
230 | |
231 | struct icm_fr_pkg_add_device_key_response { | |
232 | struct icm_pkg_header hdr; | |
7c39ffe7 | 233 | uuid_t ep_uuid; |
f67cf491 MW |
234 | u8 connection_key; |
235 | u8 connection_id; | |
236 | u16 reserved; | |
80671708 | 237 | }; |
f67cf491 MW |
238 | |
239 | struct icm_fr_pkg_challenge_device { | |
240 | struct icm_pkg_header hdr; | |
7c39ffe7 | 241 | uuid_t ep_uuid; |
f67cf491 MW |
242 | u8 connection_key; |
243 | u8 connection_id; | |
244 | u16 reserved; | |
245 | u32 challenge[8]; | |
80671708 | 246 | }; |
f67cf491 MW |
247 | |
248 | struct icm_fr_pkg_challenge_device_response { | |
249 | struct icm_pkg_header hdr; | |
7c39ffe7 | 250 | uuid_t ep_uuid; |
f67cf491 MW |
251 | u8 connection_key; |
252 | u8 connection_id; | |
253 | u16 reserved; | |
254 | u32 challenge[8]; | |
255 | u32 response[8]; | |
80671708 | 256 | }; |
f67cf491 | 257 | |
d1ff7024 MW |
258 | struct icm_fr_pkg_approve_xdomain { |
259 | struct icm_pkg_header hdr; | |
260 | u16 reserved; | |
261 | u16 link_info; | |
262 | uuid_t remote_uuid; | |
263 | u16 transmit_path; | |
264 | u16 transmit_ring; | |
265 | u16 receive_path; | |
266 | u16 receive_ring; | |
267 | }; | |
268 | ||
269 | struct icm_fr_pkg_approve_xdomain_response { | |
270 | struct icm_pkg_header hdr; | |
271 | u16 reserved; | |
272 | u16 link_info; | |
273 | uuid_t remote_uuid; | |
274 | u16 transmit_path; | |
275 | u16 transmit_ring; | |
276 | u16 receive_path; | |
277 | u16 receive_ring; | |
278 | }; | |
279 | ||
f67cf491 MW |
280 | /* Alpine Ridge only messages */ |
281 | ||
afa11ff5 MW |
282 | struct icm_ar_pkg_driver_ready_response { |
283 | struct icm_pkg_header hdr; | |
284 | u8 romver; | |
285 | u8 ramver; | |
286 | u16 info; | |
287 | }; | |
288 | ||
2de98e05 MW |
289 | #define ICM_AR_FLAGS_RTD3 BIT(6) |
290 | ||
afa11ff5 MW |
291 | #define ICM_AR_INFO_SLEVEL_MASK GENMASK(3, 0) |
292 | #define ICM_AR_INFO_BOOT_ACL_SHIFT 7 | |
293 | #define ICM_AR_INFO_BOOT_ACL_MASK GENMASK(11, 7) | |
294 | #define ICM_AR_INFO_BOOT_ACL_SUPPORTED BIT(13) | |
295 | ||
f67cf491 MW |
296 | struct icm_ar_pkg_get_route { |
297 | struct icm_pkg_header hdr; | |
298 | u16 reserved; | |
299 | u16 link_info; | |
80671708 | 300 | }; |
f67cf491 MW |
301 | |
302 | struct icm_ar_pkg_get_route_response { | |
303 | struct icm_pkg_header hdr; | |
304 | u16 reserved; | |
305 | u16 link_info; | |
306 | u32 route_hi; | |
307 | u32 route_lo; | |
80671708 | 308 | }; |
f67cf491 | 309 | |
afa11ff5 MW |
310 | struct icm_ar_boot_acl_entry { |
311 | u32 uuid_lo; | |
312 | u32 uuid_hi; | |
313 | }; | |
314 | ||
315 | #define ICM_AR_PREBOOT_ACL_ENTRIES 16 | |
316 | ||
317 | struct icm_ar_pkg_preboot_acl { | |
318 | struct icm_pkg_header hdr; | |
319 | struct icm_ar_boot_acl_entry acl[ICM_AR_PREBOOT_ACL_ENTRIES]; | |
320 | }; | |
321 | ||
322 | struct icm_ar_pkg_preboot_acl_response { | |
323 | struct icm_pkg_header hdr; | |
324 | struct icm_ar_boot_acl_entry acl[ICM_AR_PREBOOT_ACL_ENTRIES]; | |
325 | }; | |
326 | ||
d1d8b263 RM |
327 | /* Titan Ridge messages */ |
328 | ||
329 | struct icm_tr_pkg_driver_ready_response { | |
330 | struct icm_pkg_header hdr; | |
331 | u16 reserved1; | |
332 | u16 info; | |
333 | u32 nvm_version; | |
334 | u16 device_id; | |
335 | u16 reserved2; | |
336 | }; | |
337 | ||
2de98e05 MW |
338 | #define ICM_TR_FLAGS_RTD3 BIT(6) |
339 | ||
d1d8b263 RM |
340 | #define ICM_TR_INFO_SLEVEL_MASK GENMASK(2, 0) |
341 | #define ICM_TR_INFO_BOOT_ACL_SHIFT 7 | |
342 | #define ICM_TR_INFO_BOOT_ACL_MASK GENMASK(12, 7) | |
343 | ||
344 | struct icm_tr_event_device_connected { | |
345 | struct icm_pkg_header hdr; | |
346 | uuid_t ep_uuid; | |
347 | u32 route_hi; | |
348 | u32 route_lo; | |
349 | u8 connection_id; | |
350 | u8 reserved; | |
351 | u16 link_info; | |
352 | u32 ep_name[55]; | |
353 | }; | |
354 | ||
355 | struct icm_tr_event_device_disconnected { | |
356 | struct icm_pkg_header hdr; | |
357 | u32 route_hi; | |
358 | u32 route_lo; | |
359 | }; | |
360 | ||
361 | struct icm_tr_event_xdomain_connected { | |
362 | struct icm_pkg_header hdr; | |
363 | u16 reserved; | |
364 | u16 link_info; | |
365 | uuid_t remote_uuid; | |
366 | uuid_t local_uuid; | |
367 | u32 local_route_hi; | |
368 | u32 local_route_lo; | |
369 | u32 remote_route_hi; | |
370 | u32 remote_route_lo; | |
371 | }; | |
372 | ||
373 | struct icm_tr_event_xdomain_disconnected { | |
374 | struct icm_pkg_header hdr; | |
375 | u32 route_hi; | |
376 | u32 route_lo; | |
377 | uuid_t remote_uuid; | |
378 | }; | |
379 | ||
380 | struct icm_tr_pkg_approve_device { | |
381 | struct icm_pkg_header hdr; | |
382 | uuid_t ep_uuid; | |
383 | u32 route_hi; | |
384 | u32 route_lo; | |
385 | u8 connection_id; | |
386 | u8 reserved1[3]; | |
387 | }; | |
388 | ||
389 | struct icm_tr_pkg_add_device_key { | |
390 | struct icm_pkg_header hdr; | |
391 | uuid_t ep_uuid; | |
392 | u32 route_hi; | |
393 | u32 route_lo; | |
394 | u8 connection_id; | |
395 | u8 reserved[3]; | |
396 | u32 key[8]; | |
397 | }; | |
398 | ||
399 | struct icm_tr_pkg_challenge_device { | |
400 | struct icm_pkg_header hdr; | |
401 | uuid_t ep_uuid; | |
402 | u32 route_hi; | |
403 | u32 route_lo; | |
404 | u8 connection_id; | |
405 | u8 reserved[3]; | |
406 | u32 challenge[8]; | |
407 | }; | |
408 | ||
409 | struct icm_tr_pkg_approve_xdomain { | |
410 | struct icm_pkg_header hdr; | |
411 | u32 route_hi; | |
412 | u32 route_lo; | |
413 | uuid_t remote_uuid; | |
414 | u16 transmit_path; | |
415 | u16 transmit_ring; | |
416 | u16 receive_path; | |
417 | u16 receive_ring; | |
418 | }; | |
419 | ||
420 | struct icm_tr_pkg_disconnect_xdomain { | |
421 | struct icm_pkg_header hdr; | |
422 | u8 stage; | |
423 | u8 reserved[3]; | |
424 | u32 route_hi; | |
425 | u32 route_lo; | |
426 | uuid_t remote_uuid; | |
427 | }; | |
428 | ||
429 | struct icm_tr_pkg_challenge_device_response { | |
430 | struct icm_pkg_header hdr; | |
431 | uuid_t ep_uuid; | |
432 | u32 route_hi; | |
433 | u32 route_lo; | |
434 | u8 connection_id; | |
435 | u8 reserved[3]; | |
436 | u32 challenge[8]; | |
437 | u32 response[8]; | |
438 | }; | |
439 | ||
440 | struct icm_tr_pkg_add_device_key_response { | |
441 | struct icm_pkg_header hdr; | |
442 | uuid_t ep_uuid; | |
443 | u32 route_hi; | |
444 | u32 route_lo; | |
445 | u8 connection_id; | |
446 | u8 reserved[3]; | |
447 | }; | |
448 | ||
449 | struct icm_tr_pkg_approve_xdomain_response { | |
450 | struct icm_pkg_header hdr; | |
451 | u32 route_hi; | |
452 | u32 route_lo; | |
453 | uuid_t remote_uuid; | |
454 | u16 transmit_path; | |
455 | u16 transmit_ring; | |
456 | u16 receive_path; | |
457 | u16 receive_ring; | |
458 | }; | |
459 | ||
460 | struct icm_tr_pkg_disconnect_xdomain_response { | |
461 | struct icm_pkg_header hdr; | |
462 | u8 stage; | |
463 | u8 reserved[3]; | |
464 | u32 route_hi; | |
465 | u32 route_lo; | |
466 | uuid_t remote_uuid; | |
467 | }; | |
468 | ||
d1ff7024 MW |
469 | /* XDomain messages */ |
470 | ||
471 | struct tb_xdomain_header { | |
472 | u32 route_hi; | |
473 | u32 route_lo; | |
474 | u32 length_sn; | |
475 | }; | |
476 | ||
477 | #define TB_XDOMAIN_LENGTH_MASK GENMASK(5, 0) | |
478 | #define TB_XDOMAIN_SN_MASK GENMASK(28, 27) | |
479 | #define TB_XDOMAIN_SN_SHIFT 27 | |
480 | ||
481 | enum tb_xdp_type { | |
482 | UUID_REQUEST_OLD = 1, | |
483 | UUID_RESPONSE = 2, | |
484 | PROPERTIES_REQUEST, | |
485 | PROPERTIES_RESPONSE, | |
486 | PROPERTIES_CHANGED_REQUEST, | |
487 | PROPERTIES_CHANGED_RESPONSE, | |
488 | ERROR_RESPONSE, | |
489 | UUID_REQUEST = 12, | |
490 | }; | |
491 | ||
492 | struct tb_xdp_header { | |
493 | struct tb_xdomain_header xd_hdr; | |
494 | uuid_t uuid; | |
495 | u32 type; | |
496 | }; | |
497 | ||
498 | struct tb_xdp_properties { | |
499 | struct tb_xdp_header hdr; | |
500 | uuid_t src_uuid; | |
501 | uuid_t dst_uuid; | |
502 | u16 offset; | |
503 | u16 reserved; | |
504 | }; | |
505 | ||
506 | struct tb_xdp_properties_response { | |
507 | struct tb_xdp_header hdr; | |
508 | uuid_t src_uuid; | |
509 | uuid_t dst_uuid; | |
510 | u16 offset; | |
511 | u16 data_length; | |
512 | u32 generation; | |
513 | u32 data[0]; | |
514 | }; | |
515 | ||
516 | /* | |
517 | * Max length of data array single XDomain property response is allowed | |
518 | * to carry. | |
519 | */ | |
520 | #define TB_XDP_PROPERTIES_MAX_DATA_LENGTH \ | |
521 | (((256 - 4 - sizeof(struct tb_xdp_properties_response))) / 4) | |
522 | ||
523 | /* Maximum size of the total property block in dwords we allow */ | |
524 | #define TB_XDP_PROPERTIES_MAX_LENGTH 500 | |
525 | ||
526 | struct tb_xdp_properties_changed { | |
527 | struct tb_xdp_header hdr; | |
528 | uuid_t src_uuid; | |
529 | }; | |
530 | ||
531 | struct tb_xdp_properties_changed_response { | |
532 | struct tb_xdp_header hdr; | |
533 | }; | |
534 | ||
535 | enum tb_xdp_error { | |
536 | ERROR_SUCCESS, | |
537 | ERROR_UNKNOWN_PACKET, | |
538 | ERROR_UNKNOWN_DOMAIN, | |
539 | ERROR_NOT_SUPPORTED, | |
540 | ERROR_NOT_READY, | |
541 | }; | |
542 | ||
543 | struct tb_xdp_error_response { | |
544 | struct tb_xdp_header hdr; | |
545 | u32 error; | |
546 | }; | |
547 | ||
32af9434 | 548 | #endif |