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Merge tag 's390-5.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/s390/linux
[mirror_ubuntu-jammy-kernel.git] / drivers / tty / mxser.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1da177e4
LT		 2/*
3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver.
4 *
80ff8a80
JS		 5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com).
6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com>
1da177e4 7 *
1c45607a
JS		 8 * This code is loosely based on the 1.8 moxa driver which is based on
9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and
10 * others.
1da177e4 11 *
1da177e4 12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox
8eb04cf3
AC		 13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on
14 * www.moxa.com.
1da177e4 15 * - Fixed x86_64 cleanness
1da177e4
LT		 16 */
17
1da177e4 18#include <linux/module.h>
1da177e4
LT		 19#include <linux/errno.h>
20#include <linux/signal.h>
21#include <linux/sched.h>
22#include <linux/timer.h>
23#include <linux/interrupt.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/serial.h>
27#include <linux/serial_reg.h>
28#include <linux/major.h>
29#include <linux/string.h>
30#include <linux/fcntl.h>
31#include <linux/ptrace.h>
1da177e4
LT		 32#include <linux/ioport.h>
33#include <linux/mm.h>
1da177e4
LT		 34#include <linux/delay.h>
35#include <linux/pci.h>
1977f032 36#include <linux/bitops.h>
5a0e3ad6 37#include <linux/slab.h>
5a3c6b25 38#include <linux/ratelimit.h>
1da177e4 39
1da177e4
LT		 40#include <asm/io.h>
41#include <asm/irq.h>
7c0f6ba6 42#include <linux/uaccess.h>
1da177e4
LT		 43
44#include "mxser.h"
45
502f295f 46#define MXSER_VERSION "2.0.5" /* 1.14 */
1da177e4 47#define MXSERMAJOR 174
1da177e4 48
1da177e4 49#define MXSER_BOARDS 4 /* Max. boards */
1da177e4 50#define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */
1c45607a
JS		 51#define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD)
52#define MXSER_ISR_PASS_LIMIT 100
1da177e4 53
1c45607a
JS		 54/*CheckIsMoxaMust return value*/
55#define MOXA_OTHER_UART 0x00
56#define MOXA_MUST_MU150_HWID 0x01
57#define MOXA_MUST_MU860_HWID 0x02
58
1da177e4
LT		 59#define WAKEUP_CHARS 256
60
61#define UART_MCR_AFE 0x20
62#define UART_LSR_SPECIAL 0x1E
63
e129deff 64#define PCI_DEVICE_ID_POS104UL 0x1044
1c45607a 65#define PCI_DEVICE_ID_CB108 0x1080
e129deff 66#define PCI_DEVICE_ID_CP102UF 0x1023
502f295f 67#define PCI_DEVICE_ID_CP112UL 0x1120
1c45607a 68#define PCI_DEVICE_ID_CB114 0x1142
80ff8a80 69#define PCI_DEVICE_ID_CP114UL 0x1143
1c45607a
JS		 70#define PCI_DEVICE_ID_CB134I 0x1341
71#define PCI_DEVICE_ID_CP138U 0x1380
1da177e4 72
1da177e4
LT		 73
74#define C168_ASIC_ID 1
75#define C104_ASIC_ID 2
76#define C102_ASIC_ID 0xB
77#define CI132_ASIC_ID 4
78#define CI134_ASIC_ID 3
79#define CI104J_ASIC_ID 5
80
1c45607a
JS		 81#define MXSER_HIGHBAUD 1
82#define MXSER_HAS2 2
1da177e4 83
8ea2c2ec 84/* This is only for PCI */
1c45607a 85static const struct {
1da177e4
LT		 86 int type;
87 int tx_fifo;
88 int rx_fifo;
89 int xmit_fifo_size;
90 int rx_high_water;
91 int rx_trigger;
92 int rx_low_water;
93 long max_baud;
1c45607a 94} Gpci_uart_info[] = {
1da177e4
LT		 95 {MOXA_OTHER_UART, 16, 16, 16, 14, 14, 1, 921600L},
96 {MOXA_MUST_MU150_HWID, 64, 64, 64, 48, 48, 16, 230400L},
97 {MOXA_MUST_MU860_HWID, 128, 128, 128, 96, 96, 32, 921600L}
98};
1c45607a 99#define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info)
1da177e4 100
1c45607a
JS		 101struct mxser_cardinfo {
102 char *name;
103 unsigned int nports;
104 unsigned int flags;
105};
1da177e4 106
1c45607a
JS		 107static const struct mxser_cardinfo mxser_cards[] = {
108/* 0*/ { "C168 series", 8, },
109 { "C104 series", 4, },
110 { "CI-104J series", 4, },
111 { "C168H/PCI series", 8, },
112 { "C104H/PCI series", 4, },
113/* 5*/ { "C102 series", 4, MXSER_HAS2 }, /* C102-ISA */
114 { "CI-132 series", 4, MXSER_HAS2 },
115 { "CI-134 series", 4, },
116 { "CP-132 series", 2, },
117 { "CP-114 series", 4, },
118/*10*/ { "CT-114 series", 4, },
119 { "CP-102 series", 2, MXSER_HIGHBAUD },
120 { "CP-104U series", 4, },
121 { "CP-168U series", 8, },
122 { "CP-132U series", 2, },
123/*15*/ { "CP-134U series", 4, },
124 { "CP-104JU series", 4, },
125 { "Moxa UC7000 Serial", 8, }, /* RC7000 */
126 { "CP-118U series", 8, },
127 { "CP-102UL series", 2, },
128/*20*/ { "CP-102U series", 2, },
129 { "CP-118EL series", 8, },
130 { "CP-168EL series", 8, },
131 { "CP-104EL series", 4, },
132 { "CB-108 series", 8, },
133/*25*/ { "CB-114 series", 4, },
134 { "CB-134I series", 4, },
135 { "CP-138U series", 8, },
80ff8a80 136 { "POS-104UL series", 4, },
e129deff 137 { "CP-114UL series", 4, },
502f295f
JS		 138/*30*/ { "CP-102UF series", 2, },
139 { "CP-112UL series", 2, },
1c45607a 140};
1da177e4 141
1c45607a
JS		 142/* driver_data correspond to the lines in the structure above
143 see also ISA probe function before you change something */
3385ecf8 144static const struct pci_device_id mxser_pcibrds[] = {
1c45607a
JS		 145 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 3 },
146 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 },
147 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 8 },
148 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 9 },
149 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 10 },
150 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 11 },
151 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 12 },
152 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 13 },
153 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 14 },
154 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 15 },
155 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 16 },
156 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 17 },
157 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 18 },
158 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 19 },
159 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 20 },
160 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 21 },
161 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 22 },
162 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 23 },
163 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 24 },
164 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 25 },
165 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 26 },
166 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 27 },
167 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 28 },
80ff8a80 168 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 29 },
e129deff 169 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 30 },
502f295f 170 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL), .driver_data = 31 },
1c45607a 171 { }
1da177e4 172};
1da177e4
LT		 173MODULE_DEVICE_TABLE(pci, mxser_pcibrds);
174
1df00924 175static unsigned long ioaddr[MXSER_BOARDS];
1da177e4 176static int ttymajor = MXSERMAJOR;
1da177e4
LT		 177
178/* Variables for insmod */
179
180MODULE_AUTHOR("Casper Yang");
181MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver");
3b60daf8 182module_param_hw_array(ioaddr, ulong, ioport, NULL, 0);
1df00924 183MODULE_PARM_DESC(ioaddr, "ISA io addresses to look for a moxa board");
8d3b33f6 184module_param(ttymajor, int, 0);
1da177e4
LT		 185MODULE_LICENSE("GPL");
186
187struct mxser_log {
188 int tick;
189 unsigned long rxcnt[MXSER_PORTS];
190 unsigned long txcnt[MXSER_PORTS];
191};
192
1da177e4
LT		 193struct mxser_mon {
194 unsigned long rxcnt;
195 unsigned long txcnt;
196 unsigned long up_rxcnt;
197 unsigned long up_txcnt;
198 int modem_status;
199 unsigned char hold_reason;
200};
201
202struct mxser_mon_ext {
203 unsigned long rx_cnt[32];
204 unsigned long tx_cnt[32];
205 unsigned long up_rxcnt[32];
206 unsigned long up_txcnt[32];
207 int modem_status[32];
208
209 long baudrate[32];
210 int databits[32];
211 int stopbits[32];
212 int parity[32];
213 int flowctrl[32];
214 int fifo[32];
215 int iftype[32];
216};
8ea2c2ec 217
1c45607a
JS		 218struct mxser_board;
219
220struct mxser_port {
0ad9e7d1 221 struct tty_port port;
1c45607a 222 struct mxser_board *board;
1c45607a
JS		 223
224 unsigned long ioaddr;
225 unsigned long opmode_ioaddr;
226 int max_baud;
1da177e4 227
1da177e4
LT		 228 int rx_high_water;
229 int rx_trigger; /* Rx fifo trigger level */
230 int rx_low_water;
231 int baud_base; /* max. speed */
1da177e4 232 int type; /* UART type */
1c45607a 233
1da177e4 234 int x_char; /* xon/xoff character */
1da177e4
LT		 235 int IER; /* Interrupt Enable Register */
236 int MCR; /* Modem control register */
1c45607a
JS		 237
238 unsigned char stop_rx;
239 unsigned char ldisc_stop_rx;
240
241 int custom_divisor;
1c45607a 242 unsigned char err_shadow;
1c45607a 243
1c45607a 244 struct async_icount icount; /* kernel counters for 4 input interrupts */
104583b5 245 unsigned int timeout;
1c45607a
JS		 246
247 int read_status_mask;
248 int ignore_status_mask;
104583b5 249 unsigned int xmit_fifo_size;
1da177e4
LT		 250 int xmit_head;
251 int xmit_tail;
252 int xmit_cnt;
cd7b4b39 253 int closing;
1c45607a 254
606d099c 255 struct ktermios normal_termios;
1c45607a 256
1da177e4 257 struct mxser_mon mon_data;
1c45607a 258
1da177e4 259 spinlock_t slock;
1c45607a
JS		 260};
261
262struct mxser_board {
263 unsigned int idx;
264 int irq;
265 const struct mxser_cardinfo *info;
266 unsigned long vector;
267 unsigned long vector_mask;
268
269 int chip_flag;
270 int uart_type;
271
272 struct mxser_port ports[MXSER_PORTS_PER_BOARD];
1da177e4
LT		 273};
274
1da177e4
LT		 275struct mxser_mstatus {
276 tcflag_t cflag;
277 int cts;
278 int dsr;
279 int ri;
280 int dcd;
281};
282
1c45607a 283static struct mxser_board mxser_boards[MXSER_BOARDS];
1da177e4 284static struct tty_driver *mxvar_sdriver;
1da177e4 285static struct mxser_log mxvar_log;
1da177e4 286static int mxser_set_baud_method[MXSER_PORTS + 1];
1da177e4 287
148ff86b
CH		 288static void mxser_enable_must_enchance_mode(unsigned long baseio)
289{
290 u8 oldlcr;
291 u8 efr;
292
293 oldlcr = inb(baseio + UART_LCR);
294 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
295
296 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
297 efr |= MOXA_MUST_EFR_EFRB_ENABLE;
298
299 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
300 outb(oldlcr, baseio + UART_LCR);
301}
302
e89d67cf 303#ifdef CONFIG_PCI
148ff86b
CH		 304static void mxser_disable_must_enchance_mode(unsigned long baseio)
305{
306 u8 oldlcr;
307 u8 efr;
308
309 oldlcr = inb(baseio + UART_LCR);
310 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
311
312 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
313 efr &= ~MOXA_MUST_EFR_EFRB_ENABLE;
314
315 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
316 outb(oldlcr, baseio + UART_LCR);
317}
e89d67cf 318#endif
148ff86b
CH		 319
320static void mxser_set_must_xon1_value(unsigned long baseio, u8 value)
321{
322 u8 oldlcr;
323 u8 efr;
324
325 oldlcr = inb(baseio + UART_LCR);
326 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
327
328 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
329 efr &= ~MOXA_MUST_EFR_BANK_MASK;
330 efr |= MOXA_MUST_EFR_BANK0;
331
332 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
333 outb(value, baseio + MOXA_MUST_XON1_REGISTER);
334 outb(oldlcr, baseio + UART_LCR);
335}
336
337static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value)
338{
339 u8 oldlcr;
340 u8 efr;
341
342 oldlcr = inb(baseio + UART_LCR);
343 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
344
345 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
346 efr &= ~MOXA_MUST_EFR_BANK_MASK;
347 efr |= MOXA_MUST_EFR_BANK0;
348
349 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
350 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER);
351 outb(oldlcr, baseio + UART_LCR);
352}
353
354static void mxser_set_must_fifo_value(struct mxser_port *info)
355{
356 u8 oldlcr;
357 u8 efr;
358
359 oldlcr = inb(info->ioaddr + UART_LCR);
360 outb(MOXA_MUST_ENTER_ENCHANCE, info->ioaddr + UART_LCR);
361
362 efr = inb(info->ioaddr + MOXA_MUST_EFR_REGISTER);
363 efr &= ~MOXA_MUST_EFR_BANK_MASK;
364 efr |= MOXA_MUST_EFR_BANK1;
365
366 outb(efr, info->ioaddr + MOXA_MUST_EFR_REGISTER);
367 outb((u8)info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER);
368 outb((u8)info->rx_trigger, info->ioaddr + MOXA_MUST_RBRTI_REGISTER);
369 outb((u8)info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER);
370 outb(oldlcr, info->ioaddr + UART_LCR);
371}
372
373static void mxser_set_must_enum_value(unsigned long baseio, u8 value)
374{
375 u8 oldlcr;
376 u8 efr;
377
378 oldlcr = inb(baseio + UART_LCR);
379 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
380
381 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
382 efr &= ~MOXA_MUST_EFR_BANK_MASK;
383 efr |= MOXA_MUST_EFR_BANK2;
384
385 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
386 outb(value, baseio + MOXA_MUST_ENUM_REGISTER);
387 outb(oldlcr, baseio + UART_LCR);
388}
389
e89d67cf 390#ifdef CONFIG_PCI
148ff86b
CH		 391static void mxser_get_must_hardware_id(unsigned long baseio, u8 *pId)
392{
393 u8 oldlcr;
394 u8 efr;
395
396 oldlcr = inb(baseio + UART_LCR);
397 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
398
399 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
400 efr &= ~MOXA_MUST_EFR_BANK_MASK;
401 efr |= MOXA_MUST_EFR_BANK2;
402
403 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
404 *pId = inb(baseio + MOXA_MUST_HWID_REGISTER);
405 outb(oldlcr, baseio + UART_LCR);
406}
e89d67cf 407#endif
148ff86b
CH		 408
409static void SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(unsigned long baseio)
410{
411 u8 oldlcr;
412 u8 efr;
413
414 oldlcr = inb(baseio + UART_LCR);
415 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
416
417 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
418 efr &= ~MOXA_MUST_EFR_SF_MASK;
419
420 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
421 outb(oldlcr, baseio + UART_LCR);
422}
423
424static void mxser_enable_must_tx_software_flow_control(unsigned long baseio)
425{
426 u8 oldlcr;
427 u8 efr;
428
429 oldlcr = inb(baseio + UART_LCR);
430 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
431
432 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
433 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
434 efr |= MOXA_MUST_EFR_SF_TX1;
435
436 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
437 outb(oldlcr, baseio + UART_LCR);
438}
439
440static void mxser_disable_must_tx_software_flow_control(unsigned long baseio)
441{
442 u8 oldlcr;
443 u8 efr;
444
445 oldlcr = inb(baseio + UART_LCR);
446 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
447
448 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
449 efr &= ~MOXA_MUST_EFR_SF_TX_MASK;
450
451 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
452 outb(oldlcr, baseio + UART_LCR);
453}
454
455static void mxser_enable_must_rx_software_flow_control(unsigned long baseio)
456{
457 u8 oldlcr;
458 u8 efr;
459
460 oldlcr = inb(baseio + UART_LCR);
461 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
462
463 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
464 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
465 efr |= MOXA_MUST_EFR_SF_RX1;
466
467 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
468 outb(oldlcr, baseio + UART_LCR);
469}
470
471static void mxser_disable_must_rx_software_flow_control(unsigned long baseio)
472{
473 u8 oldlcr;
474 u8 efr;
475
476 oldlcr = inb(baseio + UART_LCR);
477 outb(MOXA_MUST_ENTER_ENCHANCE, baseio + UART_LCR);
478
479 efr = inb(baseio + MOXA_MUST_EFR_REGISTER);
480 efr &= ~MOXA_MUST_EFR_SF_RX_MASK;
481
482 outb(efr, baseio + MOXA_MUST_EFR_REGISTER);
483 outb(oldlcr, baseio + UART_LCR);
484}
485
b8cc5549 486#ifdef CONFIG_PCI
9671f099 487static int CheckIsMoxaMust(unsigned long io)
1da177e4
LT		 488{
489 u8 oldmcr, hwid;
490 int i;
491
492 outb(0, io + UART_LCR);
148ff86b 493 mxser_disable_must_enchance_mode(io);
1da177e4
LT		 494 oldmcr = inb(io + UART_MCR);
495 outb(0, io + UART_MCR);
148ff86b 496 mxser_set_must_xon1_value(io, 0x11);
1da177e4
LT		 497 if ((hwid = inb(io + UART_MCR)) != 0) {
498 outb(oldmcr, io + UART_MCR);
8ea2c2ec 499 return MOXA_OTHER_UART;
1da177e4
LT		 500 }
501
148ff86b 502 mxser_get_must_hardware_id(io, &hwid);
1c45607a
JS		 503 for (i = 1; i < UART_INFO_NUM; i++) { /* 0 = OTHER_UART */
504 if (hwid == Gpci_uart_info[i].type)
8ea2c2ec 505 return (int)hwid;
1da177e4
LT		 506 }
507 return MOXA_OTHER_UART;
508}
b8cc5549 509#endif
1da177e4 510
1c45607a 511static void process_txrx_fifo(struct mxser_port *info)
1da177e4
LT		 512{
513 int i;
514
515 if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
516 info->rx_trigger = 1;
517 info->rx_high_water = 1;
518 info->rx_low_water = 1;
519 info->xmit_fifo_size = 1;
1c45607a
JS		 520 } else
521 for (i = 0; i < UART_INFO_NUM; i++)
522 if (info->board->chip_flag == Gpci_uart_info[i].type) {
1da177e4
LT		 523 info->rx_trigger = Gpci_uart_info[i].rx_trigger;
524 info->rx_low_water = Gpci_uart_info[i].rx_low_water;
525 info->rx_high_water = Gpci_uart_info[i].rx_high_water;
526 info->xmit_fifo_size = Gpci_uart_info[i].xmit_fifo_size;
527 break;
528 }
1da177e4
LT		 529}
530
1c45607a 531static unsigned char mxser_get_msr(int baseaddr, int mode, int port)
1da177e4 532{
72800df9 533 static unsigned char mxser_msr[MXSER_PORTS + 1];
1c45607a 534 unsigned char status = 0;
1da177e4 535
1c45607a 536 status = inb(baseaddr + UART_MSR);
1da177e4 537
1c45607a
JS		 538 mxser_msr[port] &= 0x0F;
539 mxser_msr[port] |= status;
540 status = mxser_msr[port];
541 if (mode)
542 mxser_msr[port] = 0;
1da177e4 543
1c45607a
JS		 544 return status;
545}
1da177e4 546
31f35939
AC		 547static int mxser_carrier_raised(struct tty_port *port)
548{
549 struct mxser_port *mp = container_of(port, struct mxser_port, port);
550 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0;
551}
552
fcc8ac18 553static void mxser_dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 554{
555 struct mxser_port *mp = container_of(port, struct mxser_port, port);
556 unsigned long flags;
557
558 spin_lock_irqsave(&mp->slock, flags);
fcc8ac18
AC		 559 if (on)
560 outb(inb(mp->ioaddr + UART_MCR) |
561 UART_MCR_DTR | UART_MCR_RTS, mp->ioaddr + UART_MCR);
562 else
563 outb(inb(mp->ioaddr + UART_MCR)&~(UART_MCR_DTR | UART_MCR_RTS),
564 mp->ioaddr + UART_MCR);
5d951fb4
AC		 565 spin_unlock_irqrestore(&mp->slock, flags);
566}
567
216ba023 568static int mxser_set_baud(struct tty_struct *tty, long newspd)
1da177e4 569{
216ba023 570 struct mxser_port *info = tty->driver_data;
104583b5 571 unsigned int quot = 0, baud;
1c45607a 572 unsigned char cval;
104583b5 573 u64 timeout;
1da177e4 574
216ba023 575 if (!info->ioaddr)
1c45607a 576 return -1;
1da177e4 577
1c45607a
JS		 578 if (newspd > info->max_baud)
579 return -1;
1da177e4 580
1c45607a
JS		 581 if (newspd == 134) {
582 quot = 2 * info->baud_base / 269;
216ba023 583 tty_encode_baud_rate(tty, 134, 134);
1c45607a
JS		 584 } else if (newspd) {
585 quot = info->baud_base / newspd;
586 if (quot == 0)
587 quot = 1;
588 baud = info->baud_base/quot;
216ba023 589 tty_encode_baud_rate(tty, baud, baud);
1c45607a
JS		 590 } else {
591 quot = 0;
592 }
1da177e4 593
104583b5
JS		 594 /*
595 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the
596 * u64 domain
597 */
598 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot;
599 do_div(timeout, info->baud_base);
600 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */
1da177e4 601
1c45607a
JS		 602 if (quot) {
603 info->MCR |= UART_MCR_DTR;
604 outb(info->MCR, info->ioaddr + UART_MCR);
605 } else {
606 info->MCR &= ~UART_MCR_DTR;
607 outb(info->MCR, info->ioaddr + UART_MCR);
608 return 0;
609 }
1da177e4 610
1c45607a 611 cval = inb(info->ioaddr + UART_LCR);
1da177e4 612
1c45607a 613 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */
1da177e4 614
1c45607a
JS		 615 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */
616 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */
617 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */
1da177e4 618
1c45607a 619#ifdef BOTHER
216ba023 620 if (C_BAUD(tty) == BOTHER) {
1c45607a
JS		 621 quot = info->baud_base % newspd;
622 quot *= 8;
623 if (quot % newspd > newspd / 2) {
624 quot /= newspd;
625 quot++;
626 } else
627 quot /= newspd;
628
148ff86b 629 mxser_set_must_enum_value(info->ioaddr, quot);
1c45607a
JS		 630 } else
631#endif
148ff86b 632 mxser_set_must_enum_value(info->ioaddr, 0);
1da177e4 633
8ea2c2ec 634 return 0;
1da177e4 635}
1da177e4 636
1c45607a
JS		 637/*
638 * This routine is called to set the UART divisor registers to match
639 * the specified baud rate for a serial port.
640 */
beca62c4 641static void mxser_change_speed(struct tty_struct *tty)
1da177e4 642{
216ba023 643 struct mxser_port *info = tty->driver_data;
1c45607a 644 unsigned cflag, cval, fcr;
1c45607a 645 unsigned char status;
1da177e4 646
adc8d746 647 cflag = tty->termios.c_cflag;
216ba023 648 if (!info->ioaddr)
beca62c4 649 return;
1da177e4 650
216ba023
AC		 651 if (mxser_set_baud_method[tty->index] == 0)
652 mxser_set_baud(tty, tty_get_baud_rate(tty));
1da177e4 653
1c45607a
JS		 654 /* byte size and parity */
655 switch (cflag & CSIZE) {
656 case CS5:
657 cval = 0x00;
658 break;
659 case CS6:
660 cval = 0x01;
661 break;
662 case CS7:
663 cval = 0x02;
664 break;
665 case CS8:
666 cval = 0x03;
667 break;
668 default:
669 cval = 0x00;
670 break; /* too keep GCC shut... */
671 }
672 if (cflag & CSTOPB)
673 cval |= 0x04;
674 if (cflag & PARENB)
675 cval |= UART_LCR_PARITY;
676 if (!(cflag & PARODD))
677 cval |= UART_LCR_EPAR;
678 if (cflag & CMSPAR)
679 cval |= UART_LCR_SPAR;
1da177e4 680
1c45607a
JS		 681 if ((info->type == PORT_8250) || (info->type == PORT_16450)) {
682 if (info->board->chip_flag) {
683 fcr = UART_FCR_ENABLE_FIFO;
684 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 685 mxser_set_must_fifo_value(info);
1c45607a
JS		 686 } else
687 fcr = 0;
688 } else {
689 fcr = UART_FCR_ENABLE_FIFO;
690 if (info->board->chip_flag) {
691 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE;
148ff86b 692 mxser_set_must_fifo_value(info);
1c45607a
JS		 693 } else {
694 switch (info->rx_trigger) {
695 case 1:
696 fcr |= UART_FCR_TRIGGER_1;
697 break;
698 case 4:
699 fcr |= UART_FCR_TRIGGER_4;
700 break;
701 case 8:
702 fcr |= UART_FCR_TRIGGER_8;
703 break;
704 default:
705 fcr |= UART_FCR_TRIGGER_14;
706 break;
707 }
1da177e4 708 }
1da177e4
LT		 709 }
710
1c45607a
JS		 711 /* CTS flow control flag and modem status interrupts */
712 info->IER &= ~UART_IER_MSI;
713 info->MCR &= ~UART_MCR_AFE;
5604a98e 714 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
1c45607a 715 if (cflag & CRTSCTS) {
1c45607a
JS		 716 info->IER |= UART_IER_MSI;
717 if ((info->type == PORT_16550A) || (info->board->chip_flag)) {
718 info->MCR |= UART_MCR_AFE;
719 } else {
720 status = inb(info->ioaddr + UART_MSR);
216ba023 721 if (tty->hw_stopped) {
1c45607a 722 if (status & UART_MSR_CTS) {
216ba023 723 tty->hw_stopped = 0;
1c45607a
JS		 724 if (info->type != PORT_16550A &&
725 !info->board->chip_flag) {
726 outb(info->IER & ~UART_IER_THRI,
727 info->ioaddr +
728 UART_IER);
729 info->IER |= UART_IER_THRI;
730 outb(info->IER, info->ioaddr +
731 UART_IER);
732 }
216ba023 733 tty_wakeup(tty);
1c45607a
JS		 734 }
735 } else {
736 if (!(status & UART_MSR_CTS)) {
216ba023 737 tty->hw_stopped = 1;
1c45607a
JS		 738 if ((info->type != PORT_16550A) &&
739 (!info->board->chip_flag)) {
740 info->IER &= ~UART_IER_THRI;
741 outb(info->IER, info->ioaddr +
742 UART_IER);
743 }
744 }
745 }
1da177e4 746 }
1c45607a
JS		 747 }
748 outb(info->MCR, info->ioaddr + UART_MCR);
2d68655d
PH		 749 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
750 if (~cflag & CLOCAL)
1c45607a 751 info->IER |= UART_IER_MSI;
1c45607a
JS		 752 outb(info->IER, info->ioaddr + UART_IER);
753
754 /*
755 * Set up parity check flag
756 */
757 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
216ba023 758 if (I_INPCK(tty))
1c45607a 759 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
216ba023 760 if (I_BRKINT(tty) || I_PARMRK(tty))
1c45607a 761 info->read_status_mask |= UART_LSR_BI;
1da177e4 762
1c45607a 763 info->ignore_status_mask = 0;
1da177e4 764
216ba023 765 if (I_IGNBRK(tty)) {
1c45607a
JS		 766 info->ignore_status_mask |= UART_LSR_BI;
767 info->read_status_mask |= UART_LSR_BI;
8ea2c2ec 768 /*
1c45607a
JS		 769 * If we're ignore parity and break indicators, ignore
770 * overruns too. (For real raw support).
8ea2c2ec 771 */
216ba023 772 if (I_IGNPAR(tty)) {
1c45607a
JS		 773 info->ignore_status_mask |=
774 UART_LSR_OE |
775 UART_LSR_PE |
776 UART_LSR_FE;
777 info->read_status_mask |=
778 UART_LSR_OE |
779 UART_LSR_PE |
780 UART_LSR_FE;
781 }
1da177e4 782 }
1c45607a 783 if (info->board->chip_flag) {
216ba023
AC		 784 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty));
785 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty));
786 if (I_IXON(tty)) {
148ff86b
CH		 787 mxser_enable_must_rx_software_flow_control(
788 info->ioaddr);
1c45607a 789 } else {
148ff86b
CH		 790 mxser_disable_must_rx_software_flow_control(
791 info->ioaddr);
1da177e4 792 }
216ba023 793 if (I_IXOFF(tty)) {
148ff86b
CH		 794 mxser_enable_must_tx_software_flow_control(
795 info->ioaddr);
1c45607a 796 } else {
148ff86b
CH		 797 mxser_disable_must_tx_software_flow_control(
798 info->ioaddr);
1da177e4
LT		 799 }
800 }
1da177e4 801
1da177e4 802
1c45607a
JS		 803 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */
804 outb(cval, info->ioaddr + UART_LCR);
1da177e4
LT		 805}
806
216ba023
AC		 807static void mxser_check_modem_status(struct tty_struct *tty,
808 struct mxser_port *port, int status)
1da177e4 809{
1c45607a
JS		 810 /* update input line counters */
811 if (status & UART_MSR_TERI)
812 port->icount.rng++;
813 if (status & UART_MSR_DDSR)
814 port->icount.dsr++;
815 if (status & UART_MSR_DDCD)
816 port->icount.dcd++;
817 if (status & UART_MSR_DCTS)
818 port->icount.cts++;
819 port->mon_data.modem_status = status;
bdc04e31 820 wake_up_interruptible(&port->port.delta_msr_wait);
1da177e4 821
2d68655d 822 if (tty_port_check_carrier(&port->port) && (status & UART_MSR_DDCD)) {
1c45607a 823 if (status & UART_MSR_DCD)
0ad9e7d1 824 wake_up_interruptible(&port->port.open_wait);
1c45607a 825 }
1da177e4 826
f21ec3d2 827 if (tty_port_cts_enabled(&port->port)) {
216ba023 828 if (tty->hw_stopped) {
1c45607a 829 if (status & UART_MSR_CTS) {
216ba023 830 tty->hw_stopped = 0;
1c45607a
JS		 831
832 if ((port->type != PORT_16550A) &&
833 (!port->board->chip_flag)) {
834 outb(port->IER & ~UART_IER_THRI,
835 port->ioaddr + UART_IER);
836 port->IER |= UART_IER_THRI;
837 outb(port->IER, port->ioaddr +
838 UART_IER);
839 }
216ba023 840 tty_wakeup(tty);
1c45607a
JS		 841 }
842 } else {
843 if (!(status & UART_MSR_CTS)) {
216ba023 844 tty->hw_stopped = 1;
1c45607a
JS		 845 if (port->type != PORT_16550A &&
846 !port->board->chip_flag) {
847 port->IER &= ~UART_IER_THRI;
848 outb(port->IER, port->ioaddr +
849 UART_IER);
850 }
851 }
852 }
1da177e4
LT		 853 }
854}
855
6769140d 856static int mxser_activate(struct tty_port *port, struct tty_struct *tty)
1da177e4 857{
6769140d 858 struct mxser_port *info = container_of(port, struct mxser_port, port);
1c45607a
JS		 859 unsigned long page;
860 unsigned long flags;
1da177e4 861
1c45607a
JS		 862 page = __get_free_page(GFP_KERNEL);
863 if (!page)
864 return -ENOMEM;
1da177e4 865
1c45607a 866 spin_lock_irqsave(&info->slock, flags);
1da177e4 867
1c45607a 868 if (!info->ioaddr || !info->type) {
216ba023 869 set_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 870 free_page(page);
871 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 872 return 0;
1c45607a 873 }
6769140d 874 info->port.xmit_buf = (unsigned char *) page;
1da177e4 875
1da177e4 876 /*
1c45607a
JS		 877 * Clear the FIFO buffers and disable them
878 * (they will be reenabled in mxser_change_speed())
1da177e4 879 */
1c45607a
JS		 880 if (info->board->chip_flag)
881 outb((UART_FCR_CLEAR_RCVR |
882 UART_FCR_CLEAR_XMIT |
883 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR);
884 else
885 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
886 info->ioaddr + UART_FCR);
1da177e4 887
1c45607a
JS		 888 /*
889 * At this point there's no way the LSR could still be 0xFF;
890 * if it is, then bail out, because there's likely no UART
891 * here.
892 */
893 if (inb(info->ioaddr + UART_LSR) == 0xff) {
894 spin_unlock_irqrestore(&info->slock, flags);
895 if (capable(CAP_SYS_ADMIN)) {
f43a510d 896 set_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 897 return 0;
898 } else
899 return -ENODEV;
900 }
1da177e4 901
1c45607a
JS		 902 /*
903 * Clear the interrupt registers.
904 */
905 (void) inb(info->ioaddr + UART_LSR);
906 (void) inb(info->ioaddr + UART_RX);
907 (void) inb(info->ioaddr + UART_IIR);
908 (void) inb(info->ioaddr + UART_MSR);
909
910 /*
911 * Now, initialize the UART
912 */
913 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */
914 info->MCR = UART_MCR_DTR | UART_MCR_RTS;
915 outb(info->MCR, info->ioaddr + UART_MCR);
916
917 /*
918 * Finally, enable interrupts
919 */
920 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI;
921
922 if (info->board->chip_flag)
923 info->IER |= MOXA_MUST_IER_EGDAI;
924 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */
925
926 /*
927 * And clear the interrupt registers again for luck.
928 */
929 (void) inb(info->ioaddr + UART_LSR);
930 (void) inb(info->ioaddr + UART_RX);
931 (void) inb(info->ioaddr + UART_IIR);
932 (void) inb(info->ioaddr + UART_MSR);
933
216ba023 934 clear_bit(TTY_IO_ERROR, &tty->flags);
1c45607a
JS		 935 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
936
937 /*
938 * and set the speed of the serial port
939 */
2799707f 940 mxser_change_speed(tty);
1c45607a
JS		 941 spin_unlock_irqrestore(&info->slock, flags);
942
943 return 0;
944}
945
946/*
6769140d 947 * This routine will shutdown a serial port
1c45607a 948 */
6769140d 949static void mxser_shutdown_port(struct tty_port *port)
1c45607a 950{
6769140d 951 struct mxser_port *info = container_of(port, struct mxser_port, port);
1c45607a
JS		 952 unsigned long flags;
953
1c45607a
JS		 954 spin_lock_irqsave(&info->slock, flags);
955
956 /*
957 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq
958 * here so the queue might never be waken up
959 */
bdc04e31 960 wake_up_interruptible(&info->port.delta_msr_wait);
1c45607a
JS		 961
962 /*
6769140d 963 * Free the xmit buffer, if necessary
1c45607a 964 */
0ad9e7d1
AC		 965 if (info->port.xmit_buf) {
966 free_page((unsigned long) info->port.xmit_buf);
967 info->port.xmit_buf = NULL;
1da177e4
LT		 968 }
969
1c45607a
JS		 970 info->IER = 0;
971 outb(0x00, info->ioaddr + UART_IER);
972
1c45607a
JS		 973 /* clear Rx/Tx FIFO's */
974 if (info->board->chip_flag)
975 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT |
976 MOXA_MUST_FCR_GDA_MODE_ENABLE,
977 info->ioaddr + UART_FCR);
978 else
979 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
980 info->ioaddr + UART_FCR);
981
982 /* read data port to reset things */
983 (void) inb(info->ioaddr + UART_RX);
984
1c45607a
JS		 985
986 if (info->board->chip_flag)
987 SET_MOXA_MUST_NO_SOFTWARE_FLOW_CONTROL(info->ioaddr);
988
989 spin_unlock_irqrestore(&info->slock, flags);
990}
991
992/*
993 * This routine is called whenever a serial port is opened. It
994 * enables interrupts for a serial port, linking in its async structure into
995 * the IRQ chain. It also performs the serial-specific
996 * initialization for the tty structure.
997 */
998static int mxser_open(struct tty_struct *tty, struct file *filp)
999{
1000 struct mxser_port *info;
6769140d 1001 int line;
1c45607a
JS		 1002
1003 line = tty->index;
1004 if (line == MXSER_PORTS)
1005 return 0;
1c45607a
JS		 1006 info = &mxser_boards[line / MXSER_PORTS_PER_BOARD].ports[line % MXSER_PORTS_PER_BOARD];
1007 if (!info->ioaddr)
1008 return -ENODEV;
1009
a2d1e351 1010 tty->driver_data = info;
6769140d 1011 return tty_port_open(&info->port, tty, filp);
1da177e4
LT		 1012}
1013
978e595f
AC		 1014static void mxser_flush_buffer(struct tty_struct *tty)
1015{
1016 struct mxser_port *info = tty->driver_data;
1017 char fcr;
1018 unsigned long flags;
1019
1020
1021 spin_lock_irqsave(&info->slock, flags);
1022 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1023
1024 fcr = inb(info->ioaddr + UART_FCR);
1025 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT),
1026 info->ioaddr + UART_FCR);
1027 outb(fcr, info->ioaddr + UART_FCR);
1028
1029 spin_unlock_irqrestore(&info->slock, flags);
1030
1031 tty_wakeup(tty);
1032}
1033
1034
6769140d 1035static void mxser_close_port(struct tty_port *port)
1da177e4 1036{
1e2b0254 1037 struct mxser_port *info = container_of(port, struct mxser_port, port);
1da177e4 1038 unsigned long timeout;
1da177e4
LT		 1039 /*
1040 * At this point we stop accepting input. To do this, we
1041 * disable the receive line status interrupts, and tell the
1042 * interrupt driver to stop checking the data ready bit in the
1043 * line status register.
1044 */
1045 info->IER &= ~UART_IER_RLSI;
1c45607a 1046 if (info->board->chip_flag)
1da177e4 1047 info->IER &= ~MOXA_MUST_RECV_ISR;
1c45607a 1048
6769140d
AC		 1049 outb(info->IER, info->ioaddr + UART_IER);
1050 /*
1051 * Before we drop DTR, make sure the UART transmitter
1052 * has completely drained; this is especially
1053 * important if there is a transmit FIFO!
1054 */
1055 timeout = jiffies + HZ;
1056 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) {
1057 schedule_timeout_interruptible(5);
1058 if (time_after(jiffies, timeout))
1059 break;
1da177e4 1060 }
1e2b0254
AC		 1061}
1062
1063/*
1064 * This routine is called when the serial port gets closed. First, we
1065 * wait for the last remaining data to be sent. Then, we unlink its
1066 * async structure from the interrupt chain if necessary, and we free
1067 * that IRQ if nothing is left in the chain.
1068 */
1069static void mxser_close(struct tty_struct *tty, struct file *filp)
1070{
1071 struct mxser_port *info = tty->driver_data;
1072 struct tty_port *port = &info->port;
1073
a2d1e351 1074 if (tty->index == MXSER_PORTS || info == NULL)
1e2b0254
AC		 1075 return;
1076 if (tty_port_close_start(port, tty, filp) == 0)
1077 return;
cd7b4b39 1078 info->closing = 1;
6769140d
AC		 1079 mutex_lock(&port->mutex);
1080 mxser_close_port(port);
1e2b0254 1081 mxser_flush_buffer(tty);
d41861ca
PH		 1082 if (tty_port_initialized(port) && C_HUPCL(tty))
1083 tty_port_lower_dtr_rts(port);
6769140d 1084 mxser_shutdown_port(port);
d41861ca 1085 tty_port_set_initialized(port, 0);
6769140d 1086 mutex_unlock(&port->mutex);
cd7b4b39 1087 info->closing = 0;
a6614999
AC		 1088 /* Right now the tty_port set is done outside of the close_end helper
1089 as we don't yet have everyone using refcounts */
1090 tty_port_close_end(port, tty);
1091 tty_port_tty_set(port, NULL);
1da177e4
LT		 1092}
1093
1094static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count)
1095{
1096 int c, total = 0;
1c45607a 1097 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1098 unsigned long flags;
1099
0ad9e7d1 1100 if (!info->port.xmit_buf)
8ea2c2ec 1101 return 0;
1da177e4
LT		 1102
1103 while (1) {
8ea2c2ec
JJ		 1104 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
1105 SERIAL_XMIT_SIZE - info->xmit_head));
1da177e4
LT		 1106 if (c <= 0)
1107 break;
1108
0ad9e7d1 1109 memcpy(info->port.xmit_buf + info->xmit_head, buf, c);
1da177e4 1110 spin_lock_irqsave(&info->slock, flags);
8ea2c2ec
JJ		 1111 info->xmit_head = (info->xmit_head + c) &
1112 (SERIAL_XMIT_SIZE - 1);
1da177e4
LT		 1113 info->xmit_cnt += c;
1114 spin_unlock_irqrestore(&info->slock, flags);
1115
1116 buf += c;
1117 count -= c;
1118 total += c;
1da177e4
LT		 1119 }
1120
1c45607a 1121 if (info->xmit_cnt && !tty->stopped) {
8ea2c2ec
JJ		 1122 if (!tty->hw_stopped ||
1123 (info->type == PORT_16550A) ||
1c45607a 1124 (info->board->chip_flag)) {
1da177e4 1125 spin_lock_irqsave(&info->slock, flags);
1c45607a
JS		 1126 outb(info->IER & ~UART_IER_THRI, info->ioaddr +
1127 UART_IER);
1da177e4 1128 info->IER |= UART_IER_THRI;
1c45607a 1129 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1130 spin_unlock_irqrestore(&info->slock, flags);
1131 }
1132 }
1133 return total;
1134}
1135
0be2eade 1136static int mxser_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1137{
1c45607a 1138 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1139 unsigned long flags;
1140
0ad9e7d1 1141 if (!info->port.xmit_buf)
0be2eade 1142 return 0;
1da177e4
LT		 1143
1144 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1)
0be2eade 1145 return 0;
1da177e4
LT		 1146
1147 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1148 info->port.xmit_buf[info->xmit_head++] = ch;
1da177e4
LT		 1149 info->xmit_head &= SERIAL_XMIT_SIZE - 1;
1150 info->xmit_cnt++;
1151 spin_unlock_irqrestore(&info->slock, flags);
1c45607a 1152 if (!tty->stopped) {
8ea2c2ec
JJ		 1153 if (!tty->hw_stopped ||
1154 (info->type == PORT_16550A) ||
1c45607a 1155 info->board->chip_flag) {
1da177e4 1156 spin_lock_irqsave(&info->slock, flags);
1c45607a 1157 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1158 info->IER |= UART_IER_THRI;
1c45607a 1159 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1160 spin_unlock_irqrestore(&info->slock, flags);
1161 }
1162 }
0be2eade 1163 return 1;
1da177e4
LT		 1164}
1165
1166
1167static void mxser_flush_chars(struct tty_struct *tty)
1168{
1c45607a 1169 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1170 unsigned long flags;
1171
ace7dd96
JS		 1172 if (info->xmit_cnt <= 0 || tty->stopped || !info->port.xmit_buf ||
1173 (tty->hw_stopped && info->type != PORT_16550A &&
1174 !info->board->chip_flag))
1da177e4
LT		 1175 return;
1176
1177 spin_lock_irqsave(&info->slock, flags);
1178
1c45607a 1179 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1180 info->IER |= UART_IER_THRI;
1c45607a 1181 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1182
1183 spin_unlock_irqrestore(&info->slock, flags);
1184}
1185
1186static int mxser_write_room(struct tty_struct *tty)
1187{
1c45607a 1188 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1189 int ret;
1190
1191 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
ace7dd96 1192 return ret < 0 ? 0 : ret;
1da177e4
LT		 1193}
1194
1195static int mxser_chars_in_buffer(struct tty_struct *tty)
1196{
1c45607a 1197 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1198 return info->xmit_cnt;
1199}
1200
1c45607a
JS		 1201/*
1202 * ------------------------------------------------------------
1203 * friends of mxser_ioctl()
1204 * ------------------------------------------------------------
1205 */
216ba023 1206static int mxser_get_serial_info(struct tty_struct *tty,
6da5b587 1207 struct serial_struct *ss)
1c45607a 1208{
216ba023 1209 struct mxser_port *info = tty->driver_data;
6da5b587 1210 struct tty_port *port = &info->port;
be6cf583 1211 unsigned int closing_wait, close_delay;
6da5b587
AV		 1212
1213 if (tty->index == MXSER_PORTS)
1214 return -ENOTTY;
1215
1216 mutex_lock(&port->mutex);
be6cf583
JH		 1217
1218 close_delay = jiffies_to_msecs(info->port.close_delay) / 10;
1219 closing_wait = info->port.closing_wait;
1220 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1221 closing_wait = jiffies_to_msecs(closing_wait) / 10;
1222
6da5b587
AV		 1223 ss->type = info->type,
1224 ss->line = tty->index,
1225 ss->port = info->ioaddr,
1226 ss->irq = info->board->irq,
1227 ss->flags = info->port.flags,
1228 ss->baud_base = info->baud_base,
be6cf583
JH		 1229 ss->close_delay = close_delay;
1230 ss->closing_wait = closing_wait;
6da5b587
AV		 1231 ss->custom_divisor = info->custom_divisor,
1232 mutex_unlock(&port->mutex);
1c45607a
JS		 1233 return 0;
1234}
1235
216ba023 1236static int mxser_set_serial_info(struct tty_struct *tty,
6da5b587 1237 struct serial_struct *ss)
1da177e4 1238{
216ba023 1239 struct mxser_port *info = tty->driver_data;
07f86c03 1240 struct tty_port *port = &info->port;
80ff8a80 1241 speed_t baud;
1c45607a 1242 unsigned long sl_flags;
be6cf583 1243 unsigned int flags, close_delay, closing_wait;
1c45607a 1244 int retval = 0;
1da177e4 1245
6da5b587
AV		 1246 if (tty->index == MXSER_PORTS)
1247 return -ENOTTY;
1248 if (tty_io_error(tty))
1249 return -EIO;
1250
1251 mutex_lock(&port->mutex);
1252 if (!info->ioaddr) {
1253 mutex_unlock(&port->mutex);
80ff8a80 1254 return -ENODEV;
6da5b587 1255 }
1da177e4 1256
6da5b587
AV		 1257 if (ss->irq != info->board->irq ||
1258 ss->port != info->ioaddr) {
1259 mutex_unlock(&port->mutex);
80ff8a80 1260 return -EINVAL;
6da5b587 1261 }
1da177e4 1262
07f86c03 1263 flags = port->flags & ASYNC_SPD_MASK;
1da177e4 1264
be6cf583
JH		 1265 close_delay = msecs_to_jiffies(ss->close_delay * 10);
1266 closing_wait = ss->closing_wait;
1267 if (closing_wait != ASYNC_CLOSING_WAIT_NONE)
1268 closing_wait = msecs_to_jiffies(closing_wait * 10);
1269
1c45607a 1270 if (!capable(CAP_SYS_ADMIN)) {
6da5b587 1271 if ((ss->baud_base != info->baud_base) ||
be6cf583 1272 (close_delay != info->port.close_delay) ||
b91cfb25 1273 (closing_wait != info->port.closing_wait) ||
6da5b587
AV		 1274 ((ss->flags & ~ASYNC_USR_MASK) != (info->port.flags & ~ASYNC_USR_MASK))) {
1275 mutex_unlock(&port->mutex);
1c45607a 1276 return -EPERM;
6da5b587 1277 }
0ad9e7d1 1278 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
6da5b587 1279 (ss->flags & ASYNC_USR_MASK));
1c45607a 1280 } else {
1da177e4 1281 /*
1c45607a
JS		 1282 * OK, past this point, all the error checking has been done.
1283 * At this point, we start making changes.....
1da177e4 1284 */
07f86c03 1285 port->flags = ((port->flags & ~ASYNC_FLAGS) |
6da5b587 1286 (ss->flags & ASYNC_FLAGS));
be6cf583
JH		 1287 port->close_delay = close_delay;
1288 port->closing_wait = closing_wait;
07f86c03 1289 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST &&
6da5b587
AV		 1290 (ss->baud_base != info->baud_base ||
1291 ss->custom_divisor !=
80ff8a80 1292 info->custom_divisor)) {
6da5b587
AV		 1293 if (ss->custom_divisor == 0) {
1294 mutex_unlock(&port->mutex);
07f86c03 1295 return -EINVAL;
6da5b587
AV		 1296 }
1297 baud = ss->baud_base / ss->custom_divisor;
216ba023 1298 tty_encode_baud_rate(tty, baud, baud);
80ff8a80 1299 }
fc83815c 1300
b91cfb25 1301 info->type = ss->type;
1da177e4 1302
b91cfb25
JH		 1303 process_txrx_fifo(info);
1304 }
1c45607a 1305
d41861ca 1306 if (tty_port_initialized(port)) {
07f86c03 1307 if (flags != (port->flags & ASYNC_SPD_MASK)) {
1c45607a 1308 spin_lock_irqsave(&info->slock, sl_flags);
2799707f 1309 mxser_change_speed(tty);
1c45607a 1310 spin_unlock_irqrestore(&info->slock, sl_flags);
1da177e4 1311 }
6769140d 1312 } else {
07f86c03 1313 retval = mxser_activate(port, tty);
6769140d 1314 if (retval == 0)
d41861ca 1315 tty_port_set_initialized(port, 1);
6769140d 1316 }
6da5b587 1317 mutex_unlock(&port->mutex);
1c45607a
JS		 1318 return retval;
1319}
1da177e4 1320
1c45607a
JS		 1321/*
1322 * mxser_get_lsr_info - get line status register info
1323 *
1324 * Purpose: Let user call ioctl() to get info when the UART physically
1325 * is emptied. On bus types like RS485, the transmitter must
1326 * release the bus after transmitting. This must be done when
1327 * the transmit shift register is empty, not be done when the
1328 * transmit holding register is empty. This functionality
1329 * allows an RS485 driver to be written in user space.
1330 */
1331static int mxser_get_lsr_info(struct mxser_port *info,
1332 unsigned int __user *value)
1333{
1334 unsigned char status;
1335 unsigned int result;
1336 unsigned long flags;
1da177e4 1337
1c45607a
JS		 1338 spin_lock_irqsave(&info->slock, flags);
1339 status = inb(info->ioaddr + UART_LSR);
1340 spin_unlock_irqrestore(&info->slock, flags);
1341 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
1342 return put_user(result, value);
1343}
1da177e4 1344
60b33c13 1345static int mxser_tiocmget(struct tty_struct *tty)
1c45607a
JS		 1346{
1347 struct mxser_port *info = tty->driver_data;
1348 unsigned char control, status;
1349 unsigned long flags;
1da177e4 1350
8ea2c2ec 1351
1c45607a
JS		 1352 if (tty->index == MXSER_PORTS)
1353 return -ENOIOCTLCMD;
18900ca6 1354 if (tty_io_error(tty))
1c45607a 1355 return -EIO;
1da177e4 1356
1c45607a 1357 control = info->MCR;
1da177e4 1358
1c45607a
JS		 1359 spin_lock_irqsave(&info->slock, flags);
1360 status = inb(info->ioaddr + UART_MSR);
1361 if (status & UART_MSR_ANY_DELTA)
216ba023 1362 mxser_check_modem_status(tty, info, status);
1c45607a
JS		 1363 spin_unlock_irqrestore(&info->slock, flags);
1364 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) |
1365 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) |
1366 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) |
1367 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) |
1368 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) |
1369 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0);
1370}
1da177e4 1371
20b9d177 1372static int mxser_tiocmset(struct tty_struct *tty,
1c45607a
JS		 1373 unsigned int set, unsigned int clear)
1374{
1375 struct mxser_port *info = tty->driver_data;
1376 unsigned long flags;
1da177e4 1377
1da177e4 1378
1c45607a
JS		 1379 if (tty->index == MXSER_PORTS)
1380 return -ENOIOCTLCMD;
18900ca6 1381 if (tty_io_error(tty))
1c45607a 1382 return -EIO;
1da177e4 1383
1c45607a 1384 spin_lock_irqsave(&info->slock, flags);
1da177e4 1385
1c45607a
JS		 1386 if (set & TIOCM_RTS)
1387 info->MCR |= UART_MCR_RTS;
1388 if (set & TIOCM_DTR)
1389 info->MCR |= UART_MCR_DTR;
1da177e4 1390
1c45607a
JS		 1391 if (clear & TIOCM_RTS)
1392 info->MCR &= ~UART_MCR_RTS;
1393 if (clear & TIOCM_DTR)
1394 info->MCR &= ~UART_MCR_DTR;
8ea2c2ec 1395
1c45607a
JS		 1396 outb(info->MCR, info->ioaddr + UART_MCR);
1397 spin_unlock_irqrestore(&info->slock, flags);
1398 return 0;
1399}
1da177e4 1400
1c45607a
JS		 1401static int __init mxser_program_mode(int port)
1402{
1403 int id, i, j, n;
1404
1405 outb(0, port);
1406 outb(0, port);
1407 outb(0, port);
1408 (void)inb(port);
1409 (void)inb(port);
1410 outb(0, port);
1411 (void)inb(port);
1412
1413 id = inb(port + 1) & 0x1F;
1414 if ((id != C168_ASIC_ID) &&
1415 (id != C104_ASIC_ID) &&
1416 (id != C102_ASIC_ID) &&
1417 (id != CI132_ASIC_ID) &&
1418 (id != CI134_ASIC_ID) &&
1419 (id != CI104J_ASIC_ID))
1420 return -1;
1421 for (i = 0, j = 0; i < 4; i++) {
1422 n = inb(port + 2);
1423 if (n == 'M') {
1424 j = 1;
1425 } else if ((j == 1) && (n == 1)) {
1426 j = 2;
1427 break;
1428 } else
1429 j = 0;
1da177e4 1430 }
1c45607a
JS		 1431 if (j != 2)
1432 id = -2;
1433 return id;
1da177e4
LT		 1434}
1435
1c45607a
JS		 1436static void __init mxser_normal_mode(int port)
1437{
1438 int i, n;
1439
1440 outb(0xA5, port + 1);
1441 outb(0x80, port + 3);
1442 outb(12, port + 0); /* 9600 bps */
1443 outb(0, port + 1);
1444 outb(0x03, port + 3); /* 8 data bits */
1445 outb(0x13, port + 4); /* loop back mode */
1446 for (i = 0; i < 16; i++) {
1447 n = inb(port + 5);
1448 if ((n & 0x61) == 0x60)
1449 break;
1450 if ((n & 1) == 1)
1451 (void)inb(port);
1452 }
1453 outb(0x00, port + 4);
1454}
1455
1456#define CHIP_SK 0x01 /* Serial Data Clock in Eprom */
1457#define CHIP_DO 0x02 /* Serial Data Output in Eprom */
1458#define CHIP_CS 0x04 /* Serial Chip Select in Eprom */
1459#define CHIP_DI 0x08 /* Serial Data Input in Eprom */
1460#define EN_CCMD 0x000 /* Chip's command register */
1461#define EN0_RSARLO 0x008 /* Remote start address reg 0 */
1462#define EN0_RSARHI 0x009 /* Remote start address reg 1 */
1463#define EN0_RCNTLO 0x00A /* Remote byte count reg WR */
1464#define EN0_RCNTHI 0x00B /* Remote byte count reg WR */
1465#define EN0_DCFG 0x00E /* Data configuration reg WR */
1466#define EN0_PORT 0x010 /* Rcv missed frame error counter RD */
1467#define ENC_PAGE0 0x000 /* Select page 0 of chip registers */
1468#define ENC_PAGE3 0x0C0 /* Select page 3 of chip registers */
1469static int __init mxser_read_register(int port, unsigned short *regs)
1470{
1471 int i, k, value, id;
1472 unsigned int j;
1473
1474 id = mxser_program_mode(port);
1475 if (id < 0)
1476 return id;
1477 for (i = 0; i < 14; i++) {
1478 k = (i & 0x3F) | 0x180;
1479 for (j = 0x100; j > 0; j >>= 1) {
1480 outb(CHIP_CS, port);
1481 if (k & j) {
1482 outb(CHIP_CS | CHIP_DO, port);
1483 outb(CHIP_CS | CHIP_DO | CHIP_SK, port); /* A? bit of read */
1484 } else {
1485 outb(CHIP_CS, port);
1486 outb(CHIP_CS | CHIP_SK, port); /* A? bit of read */
1487 }
1488 }
1489 (void)inb(port);
1490 value = 0;
1491 for (k = 0, j = 0x8000; k < 16; k++, j >>= 1) {
1492 outb(CHIP_CS, port);
1493 outb(CHIP_CS | CHIP_SK, port);
1494 if (inb(port) & CHIP_DI)
1495 value |= j;
1496 }
1497 regs[i] = value;
1498 outb(0, port);
1499 }
1500 mxser_normal_mode(port);
1501 return id;
1502}
1da177e4
LT		 1503
1504static int mxser_ioctl_special(unsigned int cmd, void __user *argp)
1505{
07f86c03
AC		 1506 struct mxser_port *ip;
1507 struct tty_port *port;
216ba023 1508 struct tty_struct *tty;
1c45607a
JS		 1509 int result, status;
1510 unsigned int i, j;
9d6d162d 1511 int ret = 0;
1da177e4
LT		 1512
1513 switch (cmd) {
1da177e4 1514 case MOXA_GET_MAJOR:
5a3c6b25 1515 printk_ratelimited(KERN_WARNING "mxser: '%s' uses deprecated ioctl "
8f3d137e
JS		 1516 "%x (GET_MAJOR), fix your userspace\n",
1517 current->comm, cmd);
1c45607a 1518 return put_user(ttymajor, (int __user *)argp);
1da177e4
LT		 1519
1520 case MOXA_CHKPORTENABLE:
1521 result = 0;
1c45607a
JS		 1522 for (i = 0; i < MXSER_BOARDS; i++)
1523 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++)
1524 if (mxser_boards[i].ports[j].ioaddr)
1525 result |= (1 << i);
8ea2c2ec 1526 return put_user(result, (unsigned long __user *)argp);
1da177e4 1527 case MOXA_GETDATACOUNT:
07f86c03
AC		 1528 /* The receive side is locked by port->slock but it isn't
1529 clear that an exact snapshot is worth copying here */
1da177e4 1530 if (copy_to_user(argp, &mxvar_log, sizeof(mxvar_log)))
9d6d162d 1531 ret = -EFAULT;
9d6d162d 1532 return ret;
72800df9
JS		 1533 case MOXA_GETMSTATUS: {
1534 struct mxser_mstatus ms, __user *msu = argp;
1c45607a
JS		 1535 for (i = 0; i < MXSER_BOARDS; i++)
1536 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++) {
07f86c03
AC		 1537 ip = &mxser_boards[i].ports[j];
1538 port = &ip->port;
72800df9 1539 memset(&ms, 0, sizeof(ms));
1c45607a 1540
07f86c03
AC		 1541 mutex_lock(&port->mutex);
1542 if (!ip->ioaddr)
72800df9 1543 goto copy;
216ba023 1544
07f86c03 1545 tty = tty_port_tty_get(port);
1da177e4 1546
adc8d746 1547 if (!tty)
07f86c03 1548 ms.cflag = ip->normal_termios.c_cflag;
1c45607a 1549 else
adc8d746 1550 ms.cflag = tty->termios.c_cflag;
216ba023 1551 tty_kref_put(tty);
07f86c03
AC		 1552 spin_lock_irq(&ip->slock);
1553 status = inb(ip->ioaddr + UART_MSR);
1554 spin_unlock_irq(&ip->slock);
72800df9
JS		 1555 if (status & UART_MSR_DCD)
1556 ms.dcd = 1;
1557 if (status & UART_MSR_DSR)
1558 ms.dsr = 1;
1559 if (status & UART_MSR_CTS)
1560 ms.cts = 1;
1561 copy:
07f86c03
AC		 1562 mutex_unlock(&port->mutex);
1563 if (copy_to_user(msu, &ms, sizeof(ms)))
72800df9 1564 return -EFAULT;
72800df9 1565 msu++;
1c45607a 1566 }
1da177e4 1567 return 0;
72800df9 1568 }
8ea2c2ec 1569 case MOXA_ASPP_MON_EXT: {
72800df9
JS		 1570 struct mxser_mon_ext *me; /* it's 2k, stack unfriendly */
1571 unsigned int cflag, iflag, p;
1572 u8 opmode;
1573
1574 me = kzalloc(sizeof(*me), GFP_KERNEL);
1575 if (!me)
1576 return -ENOMEM;
1c45607a 1577
72800df9
JS		 1578 for (i = 0, p = 0; i < MXSER_BOARDS; i++) {
1579 for (j = 0; j < MXSER_PORTS_PER_BOARD; j++, p++) {
1580 if (p >= ARRAY_SIZE(me->rx_cnt)) {
1581 i = MXSER_BOARDS;
1582 break;
1583 }
07f86c03
AC		 1584 ip = &mxser_boards[i].ports[j];
1585 port = &ip->port;
1586
1587 mutex_lock(&port->mutex);
1588 if (!ip->ioaddr) {
1589 mutex_unlock(&port->mutex);
1da177e4 1590 continue;
07f86c03 1591 }
1da177e4 1592
07f86c03
AC		 1593 spin_lock_irq(&ip->slock);
1594 status = mxser_get_msr(ip->ioaddr, 0, p);
1c45607a 1595
1da177e4 1596 if (status & UART_MSR_TERI)
07f86c03 1597 ip->icount.rng++;
1da177e4 1598 if (status & UART_MSR_DDSR)
07f86c03 1599 ip->icount.dsr++;
1da177e4 1600 if (status & UART_MSR_DDCD)
07f86c03 1601 ip->icount.dcd++;
1da177e4 1602 if (status & UART_MSR_DCTS)
07f86c03 1603 ip->icount.cts++;
1c45607a 1604
07f86c03
AC		 1605 ip->mon_data.modem_status = status;
1606 me->rx_cnt[p] = ip->mon_data.rxcnt;
1607 me->tx_cnt[p] = ip->mon_data.txcnt;
1608 me->up_rxcnt[p] = ip->mon_data.up_rxcnt;
1609 me->up_txcnt[p] = ip->mon_data.up_txcnt;
72800df9 1610 me->modem_status[p] =
07f86c03
AC		 1611 ip->mon_data.modem_status;
1612 spin_unlock_irq(&ip->slock);
1613
1614 tty = tty_port_tty_get(&ip->port);
1c45607a 1615
adc8d746 1616 if (!tty) {
07f86c03
AC		 1617 cflag = ip->normal_termios.c_cflag;
1618 iflag = ip->normal_termios.c_iflag;
1619 me->baudrate[p] = tty_termios_baud_rate(&ip->normal_termios);
1da177e4 1620 } else {
adc8d746
AC		 1621 cflag = tty->termios.c_cflag;
1622 iflag = tty->termios.c_iflag;
216ba023 1623 me->baudrate[p] = tty_get_baud_rate(tty);
1da177e4 1624 }
216ba023 1625 tty_kref_put(tty);
1da177e4 1626
72800df9
JS		 1627 me->databits[p] = cflag & CSIZE;
1628 me->stopbits[p] = cflag & CSTOPB;
1629 me->parity[p] = cflag & (PARENB | PARODD |
1630 CMSPAR);
1da177e4
LT		 1631
1632 if (cflag & CRTSCTS)
72800df9 1633 me->flowctrl[p] |= 0x03;
1da177e4
LT		 1634
1635 if (iflag & (IXON | IXOFF))
72800df9 1636 me->flowctrl[p] |= 0x0C;
1da177e4 1637
07f86c03 1638 if (ip->type == PORT_16550A)
72800df9 1639 me->fifo[p] = 1;
1da177e4 1640
dfc7b837
MK		 1641 if (ip->board->chip_flag == MOXA_MUST_MU860_HWID) {
1642 opmode = inb(ip->opmode_ioaddr)>>((p % 4) * 2);
1643 opmode &= OP_MODE_MASK;
1644 } else {
1645 opmode = RS232_MODE;
1646 }
72800df9 1647 me->iftype[p] = opmode;
07f86c03 1648 mutex_unlock(&port->mutex);
1da177e4 1649 }
9d6d162d 1650 }
72800df9
JS		 1651 if (copy_to_user(argp, me, sizeof(*me)))
1652 ret = -EFAULT;
1653 kfree(me);
1654 return ret;
9d6d162d
AC		 1655 }
1656 default:
1da177e4
LT		 1657 return -ENOIOCTLCMD;
1658 }
1659 return 0;
1660}
1661
1c45607a
JS		 1662static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg,
1663 struct async_icount *cprev)
1da177e4 1664{
1c45607a
JS		 1665 struct async_icount cnow;
1666 unsigned long flags;
1667 int ret;
1da177e4 1668
1c45607a
JS		 1669 spin_lock_irqsave(&info->slock, flags);
1670 cnow = info->icount; /* atomic copy */
1671 spin_unlock_irqrestore(&info->slock, flags);
1da177e4 1672
1c45607a
JS		 1673 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) ||
1674 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) ||
1675 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) ||
1676 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts));
1da177e4 1677
1c45607a
JS		 1678 *cprev = cnow;
1679
1680 return ret;
1681}
1682
6caa76b7 1683static int mxser_ioctl(struct tty_struct *tty,
1c45607a 1684 unsigned int cmd, unsigned long arg)
1da177e4 1685{
1c45607a
JS		 1686 struct mxser_port *info = tty->driver_data;
1687 struct async_icount cnow;
1c45607a
JS		 1688 unsigned long flags;
1689 void __user *argp = (void __user *)arg;
1da177e4 1690
1c45607a
JS		 1691 if (tty->index == MXSER_PORTS)
1692 return mxser_ioctl_special(cmd, argp);
1da177e4 1693
1c45607a
JS		 1694 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) {
1695 int p;
1696 unsigned long opmode;
1697 static unsigned char ModeMask[] = { 0xfc, 0xf3, 0xcf, 0x3f };
1698 int shiftbit;
1699 unsigned char val, mask;
1da177e4 1700
e037f95f
MK		 1701 if (info->board->chip_flag != MOXA_MUST_MU860_HWID)
1702 return -EFAULT;
1703
1c45607a
JS		 1704 p = tty->index % 4;
1705 if (cmd == MOXA_SET_OP_MODE) {
1706 if (get_user(opmode, (int __user *) argp))
1707 return -EFAULT;
1708 if (opmode != RS232_MODE &&
1709 opmode != RS485_2WIRE_MODE &&
1710 opmode != RS422_MODE &&
1711 opmode != RS485_4WIRE_MODE)
1712 return -EFAULT;
1713 mask = ModeMask[p];
1714 shiftbit = p * 2;
07f86c03 1715 spin_lock_irq(&info->slock);
1c45607a
JS		 1716 val = inb(info->opmode_ioaddr);
1717 val &= mask;
1718 val |= (opmode << shiftbit);
1719 outb(val, info->opmode_ioaddr);
07f86c03 1720 spin_unlock_irq(&info->slock);
1c45607a
JS		 1721 } else {
1722 shiftbit = p * 2;
07f86c03 1723 spin_lock_irq(&info->slock);
1c45607a 1724 opmode = inb(info->opmode_ioaddr) >> shiftbit;
07f86c03 1725 spin_unlock_irq(&info->slock);
1c45607a
JS		 1726 opmode &= OP_MODE_MASK;
1727 if (put_user(opmode, (int __user *)argp))
1728 return -EFAULT;
1729 }
1730 return 0;
1731 }
1732
6da5b587 1733 if (cmd != TIOCMIWAIT && tty_io_error(tty))
1c45607a
JS		 1734 return -EIO;
1735
1736 switch (cmd) {
1c45607a 1737 case TIOCSERGETLSR: /* Get line status register */
9d6d162d 1738 return mxser_get_lsr_info(info, argp);
1c45607a
JS		 1739 /*
1740 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
1741 * - mask passed in arg for lines of interest
1742 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
1743 * Caller should use TIOCGICOUNT to see which one it was
1744 */
1745 case TIOCMIWAIT:
1746 spin_lock_irqsave(&info->slock, flags);
1747 cnow = info->icount; /* note the counters on entry */
1748 spin_unlock_irqrestore(&info->slock, flags);
1749
bdc04e31 1750 return wait_event_interruptible(info->port.delta_msr_wait,
1c45607a 1751 mxser_cflags_changed(info, arg, &cnow));
1c45607a
JS		 1752 case MOXA_HighSpeedOn:
1753 return put_user(info->baud_base != 115200 ? 1 : 0, (int __user *)argp);
1754 case MOXA_SDS_RSTICOUNTER:
07f86c03 1755 spin_lock_irq(&info->slock);
1c45607a
JS		 1756 info->mon_data.rxcnt = 0;
1757 info->mon_data.txcnt = 0;
07f86c03 1758 spin_unlock_irq(&info->slock);
1c45607a
JS		 1759 return 0;
1760
1761 case MOXA_ASPP_OQUEUE:{
1762 int len, lsr;
1763
1764 len = mxser_chars_in_buffer(tty);
c6eb69ac 1765 spin_lock_irq(&info->slock);
a75b7b68 1766 lsr = inb(info->ioaddr + UART_LSR) & UART_LSR_THRE;
07f86c03 1767 spin_unlock_irq(&info->slock);
1c45607a
JS		 1768 len += (lsr ? 0 : 1);
1769
1770 return put_user(len, (int __user *)argp);
1771 }
1772 case MOXA_ASPP_MON: {
1773 int mcr, status;
1774
c6eb69ac 1775 spin_lock_irq(&info->slock);
1c45607a 1776 status = mxser_get_msr(info->ioaddr, 1, tty->index);
216ba023 1777 mxser_check_modem_status(tty, info, status);
1c45607a
JS		 1778
1779 mcr = inb(info->ioaddr + UART_MCR);
c6eb69ac 1780 spin_unlock_irq(&info->slock);
07f86c03 1781
1c45607a
JS		 1782 if (mcr & MOXA_MUST_MCR_XON_FLAG)
1783 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFHOLD;
1784 else
1785 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFHOLD;
1786
1787 if (mcr & MOXA_MUST_MCR_TX_XON)
1788 info->mon_data.hold_reason &= ~NPPI_NOTIFY_XOFFXENT;
1789 else
1790 info->mon_data.hold_reason |= NPPI_NOTIFY_XOFFXENT;
1791
216ba023 1792 if (tty->hw_stopped)
1c45607a
JS		 1793 info->mon_data.hold_reason |= NPPI_NOTIFY_CTSHOLD;
1794 else
1795 info->mon_data.hold_reason &= ~NPPI_NOTIFY_CTSHOLD;
07f86c03 1796
1c45607a
JS		 1797 if (copy_to_user(argp, &info->mon_data,
1798 sizeof(struct mxser_mon)))
1799 return -EFAULT;
1800
1801 return 0;
1802 }
1803 case MOXA_ASPP_LSTATUS: {
1804 if (put_user(info->err_shadow, (unsigned char __user *)argp))
1805 return -EFAULT;
1806
1807 info->err_shadow = 0;
1808 return 0;
1809 }
1810 case MOXA_SET_BAUD_METHOD: {
1811 int method;
1812
1813 if (get_user(method, (int __user *)argp))
1814 return -EFAULT;
1815 mxser_set_baud_method[tty->index] = method;
1816 return put_user(method, (int __user *)argp);
1817 }
1818 default:
1819 return -ENOIOCTLCMD;
1820 }
1821 return 0;
1822}
1823
0587102c
AC		 1824 /*
1825 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1826 * Return: write counters to the user passed counter struct
1827 * NB: both 1->0 and 0->1 transitions are counted except for
1828 * RI where only 0->1 is counted.
1829 */
1830
1831static int mxser_get_icount(struct tty_struct *tty,
1832 struct serial_icounter_struct *icount)
1833
1834{
1835 struct mxser_port *info = tty->driver_data;
1836 struct async_icount cnow;
1837 unsigned long flags;
1838
1839 spin_lock_irqsave(&info->slock, flags);
1840 cnow = info->icount;
1841 spin_unlock_irqrestore(&info->slock, flags);
1842
1843 icount->frame = cnow.frame;
1844 icount->brk = cnow.brk;
1845 icount->overrun = cnow.overrun;
1846 icount->buf_overrun = cnow.buf_overrun;
1847 icount->parity = cnow.parity;
1848 icount->rx = cnow.rx;
1849 icount->tx = cnow.tx;
1850 icount->cts = cnow.cts;
1851 icount->dsr = cnow.dsr;
1852 icount->rng = cnow.rng;
1853 icount->dcd = cnow.dcd;
1854 return 0;
1855}
1856
1c45607a
JS		 1857static void mxser_stoprx(struct tty_struct *tty)
1858{
1859 struct mxser_port *info = tty->driver_data;
1860
1861 info->ldisc_stop_rx = 1;
1862 if (I_IXOFF(tty)) {
1863 if (info->board->chip_flag) {
1864 info->IER &= ~MOXA_MUST_RECV_ISR;
1865 outb(info->IER, info->ioaddr + UART_IER);
1866 } else {
1867 info->x_char = STOP_CHAR(tty);
1868 outb(0, info->ioaddr + UART_IER);
1869 info->IER |= UART_IER_THRI;
1870 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1871 }
1872 }
1873
9db276f8 1874 if (C_CRTSCTS(tty)) {
1c45607a
JS		 1875 info->MCR &= ~UART_MCR_RTS;
1876 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 1877 }
1878}
1879
1880/*
1881 * This routine is called by the upper-layer tty layer to signal that
1882 * incoming characters should be throttled.
1883 */
1884static void mxser_throttle(struct tty_struct *tty)
1885{
1da177e4 1886 mxser_stoprx(tty);
1da177e4
LT		 1887}
1888
1889static void mxser_unthrottle(struct tty_struct *tty)
1890{
1c45607a 1891 struct mxser_port *info = tty->driver_data;
1da177e4 1892
1c45607a
JS		 1893 /* startrx */
1894 info->ldisc_stop_rx = 0;
1895 if (I_IXOFF(tty)) {
1896 if (info->x_char)
1897 info->x_char = 0;
1898 else {
1899 if (info->board->chip_flag) {
1900 info->IER |= MOXA_MUST_RECV_ISR;
1901 outb(info->IER, info->ioaddr + UART_IER);
1902 } else {
1903 info->x_char = START_CHAR(tty);
1904 outb(0, info->ioaddr + UART_IER);
1905 info->IER |= UART_IER_THRI;
1906 outb(info->IER, info->ioaddr + UART_IER);
1907 }
1da177e4 1908 }
1c45607a 1909 }
1da177e4 1910
9db276f8 1911 if (C_CRTSCTS(tty)) {
1c45607a
JS		 1912 info->MCR |= UART_MCR_RTS;
1913 outb(info->MCR, info->ioaddr + UART_MCR);
1da177e4
LT		 1914 }
1915}
1916
1917/*
1918 * mxser_stop() and mxser_start()
1919 *
1920 * This routines are called before setting or resetting tty->stopped.
1921 * They enable or disable transmitter interrupts, as necessary.
1922 */
1923static void mxser_stop(struct tty_struct *tty)
1924{
1c45607a 1925 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1926 unsigned long flags;
1927
1928 spin_lock_irqsave(&info->slock, flags);
1929 if (info->IER & UART_IER_THRI) {
1930 info->IER &= ~UART_IER_THRI;
1c45607a 1931 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1932 }
1933 spin_unlock_irqrestore(&info->slock, flags);
1934}
1935
1936static void mxser_start(struct tty_struct *tty)
1937{
1c45607a 1938 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 1939 unsigned long flags;
1940
1941 spin_lock_irqsave(&info->slock, flags);
0ad9e7d1 1942 if (info->xmit_cnt && info->port.xmit_buf) {
1c45607a 1943 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER);
1da177e4 1944 info->IER |= UART_IER_THRI;
1c45607a 1945 outb(info->IER, info->ioaddr + UART_IER);
1da177e4
LT		 1946 }
1947 spin_unlock_irqrestore(&info->slock, flags);
1948}
1949
1c45607a
JS		 1950static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1951{
1952 struct mxser_port *info = tty->driver_data;
1953 unsigned long flags;
1954
1955 spin_lock_irqsave(&info->slock, flags);
2799707f 1956 mxser_change_speed(tty);
1c45607a
JS		 1957 spin_unlock_irqrestore(&info->slock, flags);
1958
9db276f8 1959 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) {
1c45607a
JS		 1960 tty->hw_stopped = 0;
1961 mxser_start(tty);
1962 }
1963
1964 /* Handle sw stopped */
9db276f8 1965 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) {
1c45607a
JS		 1966 tty->stopped = 0;
1967
1968 if (info->board->chip_flag) {
1969 spin_lock_irqsave(&info->slock, flags);
148ff86b
CH		 1970 mxser_disable_must_rx_software_flow_control(
1971 info->ioaddr);
1c45607a
JS		 1972 spin_unlock_irqrestore(&info->slock, flags);
1973 }
1974
1975 mxser_start(tty);
1976 }
1977}
1978
1da177e4
LT		 1979/*
1980 * mxser_wait_until_sent() --- wait until the transmitter is empty
1981 */
1982static void mxser_wait_until_sent(struct tty_struct *tty, int timeout)
1983{
1c45607a 1984 struct mxser_port *info = tty->driver_data;
1da177e4 1985 unsigned long orig_jiffies, char_time;
07f86c03 1986 unsigned long flags;
1da177e4
LT		 1987 int lsr;
1988
1989 if (info->type == PORT_UNKNOWN)
1990 return;
1991
1992 if (info->xmit_fifo_size == 0)
1993 return; /* Just in case.... */
1994
1995 orig_jiffies = jiffies;
1996 /*
1997 * Set the check interval to be 1/5 of the estimated time to
1998 * send a single character, and make it at least 1. The check
1999 * interval should also be less than the timeout.
2000 *
2001 * Note: we have to use pretty tight timings here to satisfy
2002 * the NIST-PCTS.
2003 */
2004 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size;
2005 char_time = char_time / 5;
2006 if (char_time == 0)
2007 char_time = 1;
2008 if (timeout && timeout < char_time)
2009 char_time = timeout;
2010 /*
2011 * If the transmitter hasn't cleared in twice the approximate
2012 * amount of time to send the entire FIFO, it probably won't
2013 * ever clear. This assumes the UART isn't doing flow
2014 * control, which is currently the case. Hence, if it ever
2015 * takes longer than info->timeout, this is probably due to a
2016 * UART bug of some kind. So, we clamp the timeout parameter at
2017 * 2*info->timeout.
2018 */
2019 if (!timeout || timeout > 2 * info->timeout)
2020 timeout = 2 * info->timeout;
8bab534b 2021
07f86c03 2022 spin_lock_irqsave(&info->slock, flags);
1c45607a 2023 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) {
07f86c03 2024 spin_unlock_irqrestore(&info->slock, flags);
da4cd8df 2025 schedule_timeout_interruptible(char_time);
07f86c03 2026 spin_lock_irqsave(&info->slock, flags);
1da177e4 2027 if (signal_pending(current))
1c45607a
JS		 2028 break;
2029 if (timeout && time_after(jiffies, orig_jiffies + timeout))
2030 break;
1da177e4 2031 }
07f86c03 2032 spin_unlock_irqrestore(&info->slock, flags);
1c45607a 2033 set_current_state(TASK_RUNNING);
1c45607a 2034}
1da177e4 2035
1c45607a
JS		 2036/*
2037 * This routine is called by tty_hangup() when a hangup is signaled.
2038 */
2039static void mxser_hangup(struct tty_struct *tty)
2040{
2041 struct mxser_port *info = tty->driver_data;
1da177e4 2042
1c45607a 2043 mxser_flush_buffer(tty);
3b6826b2 2044 tty_port_hangup(&info->port);
1da177e4
LT		 2045}
2046
1c45607a
JS		 2047/*
2048 * mxser_rs_break() --- routine which turns the break handling on or off
2049 */
9e98966c 2050static int mxser_rs_break(struct tty_struct *tty, int break_state)
1da177e4 2051{
1c45607a 2052 struct mxser_port *info = tty->driver_data;
1da177e4
LT		 2053 unsigned long flags;
2054
1c45607a
JS		 2055 spin_lock_irqsave(&info->slock, flags);
2056 if (break_state == -1)
2057 outb(inb(info->ioaddr + UART_LCR) | UART_LCR_SBC,
2058 info->ioaddr + UART_LCR);
2059 else
2060 outb(inb(info->ioaddr + UART_LCR) & ~UART_LCR_SBC,
2061 info->ioaddr + UART_LCR);
2062 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 2063 return 0;
1c45607a 2064}
1da177e4 2065
216ba023
AC		 2066static void mxser_receive_chars(struct tty_struct *tty,
2067 struct mxser_port *port, int *status)
1c45607a 2068{
1c45607a
JS		 2069 unsigned char ch, gdl;
2070 int ignored = 0;
2071 int cnt = 0;
2072 int recv_room;
2073 int max = 256;
1da177e4 2074
1c45607a 2075 recv_room = tty->receive_room;
216ba023 2076 if (recv_room == 0 && !port->ldisc_stop_rx)
1c45607a 2077 mxser_stoprx(tty);
1c45607a 2078 if (port->board->chip_flag != MOXA_OTHER_UART) {
1da177e4 2079
1c45607a
JS		 2080 if (*status & UART_LSR_SPECIAL)
2081 goto intr_old;
2082 if (port->board->chip_flag == MOXA_MUST_MU860_HWID &&
2083 (*status & MOXA_MUST_LSR_RERR))
2084 goto intr_old;
2085 if (*status & MOXA_MUST_LSR_RERR)
2086 goto intr_old;
1da177e4 2087
1c45607a
JS		 2088 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER);
2089
2090 if (port->board->chip_flag == MOXA_MUST_MU150_HWID)
2091 gdl &= MOXA_MUST_GDL_MASK;
2092 if (gdl >= recv_room) {
2093 if (!port->ldisc_stop_rx)
2094 mxser_stoprx(tty);
2095 }
2096 while (gdl--) {
2097 ch = inb(port->ioaddr + UART_RX);
92a19f9c 2098 tty_insert_flip_char(&port->port, ch, 0);
1c45607a
JS		 2099 cnt++;
2100 }
2101 goto end_intr;
1da177e4 2102 }
1c45607a
JS		 2103intr_old:
2104
2105 do {
2106 if (max-- < 0)
2107 break;
1da177e4 2108
1c45607a
JS		 2109 ch = inb(port->ioaddr + UART_RX);
2110 if (port->board->chip_flag && (*status & UART_LSR_OE))
2111 outb(0x23, port->ioaddr + UART_FCR);
2112 *status &= port->read_status_mask;
2113 if (*status & port->ignore_status_mask) {
2114 if (++ignored > 100)
2115 break;
2116 } else {
2117 char flag = 0;
2118 if (*status & UART_LSR_SPECIAL) {
2119 if (*status & UART_LSR_BI) {
2120 flag = TTY_BREAK;
2121 port->icount.brk++;
1da177e4 2122
0ad9e7d1 2123 if (port->port.flags & ASYNC_SAK)
1c45607a
JS		 2124 do_SAK(tty);
2125 } else if (*status & UART_LSR_PE) {
2126 flag = TTY_PARITY;
2127 port->icount.parity++;
2128 } else if (*status & UART_LSR_FE) {
2129 flag = TTY_FRAME;
2130 port->icount.frame++;
2131 } else if (*status & UART_LSR_OE) {
2132 flag = TTY_OVERRUN;
2133 port->icount.overrun++;
2134 } else
2135 flag = TTY_BREAK;
2136 }
92a19f9c 2137 tty_insert_flip_char(&port->port, ch, flag);
1c45607a
JS		 2138 cnt++;
2139 if (cnt >= recv_room) {
2140 if (!port->ldisc_stop_rx)
2141 mxser_stoprx(tty);
2142 break;
2143 }
1da177e4 2144
1c45607a 2145 }
1da177e4 2146
1c45607a
JS		 2147 if (port->board->chip_flag)
2148 break;
1da177e4 2149
1c45607a
JS		 2150 *status = inb(port->ioaddr + UART_LSR);
2151 } while (*status & UART_LSR_DR);
1da177e4 2152
1c45607a 2153end_intr:
216ba023 2154 mxvar_log.rxcnt[tty->index] += cnt;
1c45607a
JS		 2155 port->mon_data.rxcnt += cnt;
2156 port->mon_data.up_rxcnt += cnt;
1da177e4 2157
2e124b4a 2158 tty_flip_buffer_push(&port->port);
1da177e4
LT		 2159}
2160
216ba023 2161static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port)
1da177e4 2162{
1c45607a 2163 int count, cnt;
1da177e4 2164
1c45607a
JS		 2165 if (port->x_char) {
2166 outb(port->x_char, port->ioaddr + UART_TX);
2167 port->x_char = 0;
216ba023 2168 mxvar_log.txcnt[tty->index]++;
1c45607a
JS		 2169 port->mon_data.txcnt++;
2170 port->mon_data.up_txcnt++;
2171 port->icount.tx++;
2172 return;
2173 }
1da177e4 2174
0ad9e7d1 2175 if (port->port.xmit_buf == NULL)
1c45607a 2176 return;
1da177e4 2177
216ba023
AC		 2178 if (port->xmit_cnt <= 0 || tty->stopped ||
2179 (tty->hw_stopped &&
1c45607a
JS		 2180 (port->type != PORT_16550A) &&
2181 (!port->board->chip_flag))) {
2182 port->IER &= ~UART_IER_THRI;
2183 outb(port->IER, port->ioaddr + UART_IER);
2184 return;
1da177e4
LT		 2185 }
2186
1c45607a
JS		 2187 cnt = port->xmit_cnt;
2188 count = port->xmit_fifo_size;
2189 do {
0ad9e7d1 2190 outb(port->port.xmit_buf[port->xmit_tail++],
1c45607a
JS		 2191 port->ioaddr + UART_TX);
2192 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1);
2193 if (--port->xmit_cnt <= 0)
2194 break;
2195 } while (--count > 0);
216ba023 2196 mxvar_log.txcnt[tty->index] += (cnt - port->xmit_cnt);
1da177e4 2197
1c45607a
JS		 2198 port->mon_data.txcnt += (cnt - port->xmit_cnt);
2199 port->mon_data.up_txcnt += (cnt - port->xmit_cnt);
2200 port->icount.tx += (cnt - port->xmit_cnt);
1da177e4 2201
464eb8f5 2202 if (port->xmit_cnt < WAKEUP_CHARS)
216ba023 2203 tty_wakeup(tty);
1c45607a
JS		 2204
2205 if (port->xmit_cnt <= 0) {
2206 port->IER &= ~UART_IER_THRI;
2207 outb(port->IER, port->ioaddr + UART_IER);
1da177e4 2208 }
1da177e4
LT		 2209}
2210
2211/*
1c45607a 2212 * This is the serial driver's generic interrupt routine
1da177e4 2213 */
1c45607a 2214static irqreturn_t mxser_interrupt(int irq, void *dev_id)
1da177e4 2215{
1c45607a
JS		 2216 int status, iir, i;
2217 struct mxser_board *brd = NULL;
2218 struct mxser_port *port;
2219 int max, irqbits, bits, msr;
2220 unsigned int int_cnt, pass_counter = 0;
2221 int handled = IRQ_NONE;
216ba023 2222 struct tty_struct *tty;
1da177e4 2223
1c45607a
JS		 2224 for (i = 0; i < MXSER_BOARDS; i++)
2225 if (dev_id == &mxser_boards[i]) {
2226 brd = dev_id;
2227 break;
2228 }
1da177e4 2229
1c45607a
JS		 2230 if (i == MXSER_BOARDS)
2231 goto irq_stop;
2232 if (brd == NULL)
2233 goto irq_stop;
2234 max = brd->info->nports;
2235 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) {
2236 irqbits = inb(brd->vector) & brd->vector_mask;
2237 if (irqbits == brd->vector_mask)
2238 break;
1da177e4 2239
1c45607a
JS		 2240 handled = IRQ_HANDLED;
2241 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) {
2242 if (irqbits == brd->vector_mask)
2243 break;
2244 if (bits & irqbits)
2245 continue;
2246 port = &brd->ports[i];
2247
2248 int_cnt = 0;
2249 spin_lock(&port->slock);
2250 do {
2251 iir = inb(port->ioaddr + UART_IIR);
2252 if (iir & UART_IIR_NO_INT)
2253 break;
2254 iir &= MOXA_MUST_IIR_MASK;
216ba023 2255 tty = tty_port_tty_get(&port->port);
cd7b4b39 2256 if (!tty || port->closing ||
d41861ca 2257 !tty_port_initialized(&port->port)) {
1c45607a
JS		 2258 status = inb(port->ioaddr + UART_LSR);
2259 outb(0x27, port->ioaddr + UART_FCR);
2260 inb(port->ioaddr + UART_MSR);
216ba023 2261 tty_kref_put(tty);
1c45607a
JS		 2262 break;
2263 }
1da177e4 2264
1c45607a
JS		 2265 status = inb(port->ioaddr + UART_LSR);
2266
2267 if (status & UART_LSR_PE)
2268 port->err_shadow |= NPPI_NOTIFY_PARITY;
2269 if (status & UART_LSR_FE)
2270 port->err_shadow |= NPPI_NOTIFY_FRAMING;
2271 if (status & UART_LSR_OE)
2272 port->err_shadow |=
2273 NPPI_NOTIFY_HW_OVERRUN;
2274 if (status & UART_LSR_BI)
2275 port->err_shadow |= NPPI_NOTIFY_BREAK;
2276
2277 if (port->board->chip_flag) {
2278 if (iir == MOXA_MUST_IIR_GDA ||
2279 iir == MOXA_MUST_IIR_RDA ||
2280 iir == MOXA_MUST_IIR_RTO ||
2281 iir == MOXA_MUST_IIR_LSR)
216ba023 2282 mxser_receive_chars(tty, port,
1c45607a
JS		 2283 &status);
2284
2285 } else {
2286 status &= port->read_status_mask;
2287 if (status & UART_LSR_DR)
216ba023 2288 mxser_receive_chars(tty, port,
1c45607a
JS		 2289 &status);
2290 }
2291 msr = inb(port->ioaddr + UART_MSR);
2292 if (msr & UART_MSR_ANY_DELTA)
216ba023 2293 mxser_check_modem_status(tty, port, msr);
1c45607a
JS		 2294
2295 if (port->board->chip_flag) {
2296 if (iir == 0x02 && (status &
2297 UART_LSR_THRE))
216ba023 2298 mxser_transmit_chars(tty, port);
1c45607a
JS		 2299 } else {
2300 if (status & UART_LSR_THRE)
216ba023 2301 mxser_transmit_chars(tty, port);
1c45607a 2302 }
216ba023 2303 tty_kref_put(tty);
1c45607a
JS		 2304 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT);
2305 spin_unlock(&port->slock);
2306 }
2307 }
1da177e4 2308
1c45607a
JS		 2309irq_stop:
2310 return handled;
2311}
1da177e4 2312
1c45607a
JS		 2313static const struct tty_operations mxser_ops = {
2314 .open = mxser_open,
2315 .close = mxser_close,
2316 .write = mxser_write,
2317 .put_char = mxser_put_char,
2318 .flush_chars = mxser_flush_chars,
2319 .write_room = mxser_write_room,
2320 .chars_in_buffer = mxser_chars_in_buffer,
2321 .flush_buffer = mxser_flush_buffer,
2322 .ioctl = mxser_ioctl,
2323 .throttle = mxser_throttle,
2324 .unthrottle = mxser_unthrottle,
2325 .set_termios = mxser_set_termios,
2326 .stop = mxser_stop,
2327 .start = mxser_start,
2328 .hangup = mxser_hangup,
2329 .break_ctl = mxser_rs_break,
2330 .wait_until_sent = mxser_wait_until_sent,
2331 .tiocmget = mxser_tiocmget,
2332 .tiocmset = mxser_tiocmset,
6da5b587
AV		 2333 .set_serial = mxser_set_serial_info,
2334 .get_serial = mxser_get_serial_info,
0587102c 2335 .get_icount = mxser_get_icount,
1c45607a 2336};
1da177e4 2337
04b757df 2338static const struct tty_port_operations mxser_port_ops = {
31f35939 2339 .carrier_raised = mxser_carrier_raised,
fcc8ac18 2340 .dtr_rts = mxser_dtr_rts,
6769140d
AC		 2341 .activate = mxser_activate,
2342 .shutdown = mxser_shutdown_port,
31f35939
AC		 2343};
2344
1c45607a
JS		 2345/*
2346 * The MOXA Smartio/Industio serial driver boot-time initialization code!
2347 */
1da177e4 2348
38daf88a 2349static bool allow_overlapping_vector;
a342ca1c 2350module_param(allow_overlapping_vector, bool, S_IRUGO);
38daf88a
JS		 2351MODULE_PARM_DESC(allow_overlapping_vector, "whether we allow ISA cards to be configured such that vector overlabs IO ports (default=no)");
2352
2353static bool mxser_overlapping_vector(struct mxser_board *brd)
2354{
2355 return allow_overlapping_vector &&
2356 brd->vector >= brd->ports[0].ioaddr &&
2357 brd->vector < brd->ports[0].ioaddr + 8 * brd->info->nports;
2358}
2359
2360static int mxser_request_vector(struct mxser_board *brd)
2361{
2362 if (mxser_overlapping_vector(brd))
2363 return 0;
2364 return request_region(brd->vector, 1, "mxser(vector)") ? 0 : -EIO;
2365}
2366
2367static void mxser_release_vector(struct mxser_board *brd)
2368{
2369 if (mxser_overlapping_vector(brd))
2370 return;
2371 release_region(brd->vector, 1);
2372}
2373
df480518 2374static void mxser_release_ISA_res(struct mxser_board *brd)
1c45607a 2375{
df480518 2376 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
38daf88a 2377 mxser_release_vector(brd);
1da177e4
LT		 2378}
2379
2799707f 2380static int mxser_initbrd(struct mxser_board *brd)
1da177e4 2381{
1c45607a
JS		 2382 struct mxser_port *info;
2383 unsigned int i;
2384 int retval;
1da177e4 2385
83766bc6
JS		 2386 printk(KERN_INFO "mxser: max. baud rate = %d bps\n",
2387 brd->ports[0].max_baud);
1da177e4 2388
1c45607a
JS		 2389 for (i = 0; i < brd->info->nports; i++) {
2390 info = &brd->ports[i];
44b7d1b3 2391 tty_port_init(&info->port);
31f35939 2392 info->port.ops = &mxser_port_ops;
1c45607a
JS		 2393 info->board = brd;
2394 info->stop_rx = 0;
2395 info->ldisc_stop_rx = 0;
1da177e4 2396
1c45607a
JS		 2397 /* Enhance mode enabled here */
2398 if (brd->chip_flag != MOXA_OTHER_UART)
148ff86b 2399 mxser_enable_must_enchance_mode(info->ioaddr);
1da177e4 2400
1c45607a 2401 info->type = brd->uart_type;
1da177e4 2402
1c45607a 2403 process_txrx_fifo(info);
1da177e4 2404
1c45607a 2405 info->custom_divisor = info->baud_base * 16;
44b7d1b3
AC		 2406 info->port.close_delay = 5 * HZ / 10;
2407 info->port.closing_wait = 30 * HZ;
1c45607a 2408 info->normal_termios = mxvar_sdriver->init_termios;
1c45607a
JS		 2409 memset(&info->mon_data, 0, sizeof(struct mxser_mon));
2410 info->err_shadow = 0;
2411 spin_lock_init(&info->slock);
1da177e4 2412
1c45607a
JS		 2413 /* before set INT ISR, disable all int */
2414 outb(inb(info->ioaddr + UART_IER) & 0xf0,
2415 info->ioaddr + UART_IER);
2416 }
1da177e4 2417
1c45607a
JS		 2418 retval = request_irq(brd->irq, mxser_interrupt, IRQF_SHARED, "mxser",
2419 brd);
191c5f10
JS		 2420 if (retval) {
2421 for (i = 0; i < brd->info->nports; i++)
2422 tty_port_destroy(&brd->ports[i].port);
1c45607a
JS		 2423 printk(KERN_ERR "Board %s: Request irq failed, IRQ (%d) may "
2424 "conflict with another device.\n",
2425 brd->info->name, brd->irq);
191c5f10 2426 }
df480518 2427
1c45607a
JS		 2428 return retval;
2429}
1da177e4 2430
191c5f10
JS		 2431static void mxser_board_remove(struct mxser_board *brd)
2432{
2433 unsigned int i;
2434
2435 for (i = 0; i < brd->info->nports; i++) {
2436 tty_unregister_device(mxvar_sdriver, brd->idx + i);
2437 tty_port_destroy(&brd->ports[i].port);
2438 }
9e17df37 2439 free_irq(brd->irq, brd);
191c5f10
JS		 2440}
2441
1c45607a 2442static int __init mxser_get_ISA_conf(int cap, struct mxser_board *brd)
1da177e4 2443{
38daf88a 2444 int id, i, bits, ret;
1da177e4
LT		 2445 unsigned short regs[16], irq;
2446 unsigned char scratch, scratch2;
2447
1c45607a 2448 brd->chip_flag = MOXA_OTHER_UART;
1da177e4
LT		 2449
2450 id = mxser_read_register(cap, regs);
1c45607a
JS		 2451 switch (id) {
2452 case C168_ASIC_ID:
2453 brd->info = &mxser_cards[0];
2454 break;
2455 case C104_ASIC_ID:
2456 brd->info = &mxser_cards[1];
2457 break;
2458 case CI104J_ASIC_ID:
2459 brd->info = &mxser_cards[2];
2460 break;
2461 case C102_ASIC_ID:
2462 brd->info = &mxser_cards[5];
2463 break;
2464 case CI132_ASIC_ID:
2465 brd->info = &mxser_cards[6];
2466 break;
2467 case CI134_ASIC_ID:
2468 brd->info = &mxser_cards[7];
2469 break;
2470 default:
8ea2c2ec 2471 return 0;
1c45607a 2472 }
1da177e4
LT		 2473
2474 irq = 0;
1c45607a
JS		 2475 /* some ISA cards have 2 ports, but we want to see them as 4-port (why?)
2476 Flag-hack checks if configuration should be read as 2-port here. */
2477 if (brd->info->nports == 2 || (brd->info->flags & MXSER_HAS2)) {
1da177e4
LT		 2478 irq = regs[9] & 0xF000;
2479 irq = irq | (irq >> 4);
2480 if (irq != (regs[9] & 0xFF00))
83766bc6 2481 goto err_irqconflict;
1c45607a 2482 } else if (brd->info->nports == 4) {
1da177e4
LT		 2483 irq = regs[9] & 0xF000;
2484 irq = irq | (irq >> 4);
2485 irq = irq | (irq >> 8);
2486 if (irq != regs[9])
83766bc6 2487 goto err_irqconflict;
1c45607a 2488 } else if (brd->info->nports == 8) {
1da177e4
LT		 2489 irq = regs[9] & 0xF000;
2490 irq = irq | (irq >> 4);
2491 irq = irq | (irq >> 8);
2492 if ((irq != regs[9]) || (irq != regs[10]))
83766bc6 2493 goto err_irqconflict;
1da177e4
LT		 2494 }
2495
83766bc6
JS		 2496 if (!irq) {
2497 printk(KERN_ERR "mxser: interrupt number unset\n");
2498 return -EIO;
2499 }
1c45607a 2500 brd->irq = ((int)(irq & 0xF000) >> 12);
1da177e4 2501 for (i = 0; i < 8; i++)
1c45607a 2502 brd->ports[i].ioaddr = (int) regs[i + 1] & 0xFFF8;
83766bc6
JS		 2503 if ((regs[12] & 0x80) == 0) {
2504 printk(KERN_ERR "mxser: invalid interrupt vector\n");
2505 return -EIO;
2506 }
1c45607a 2507 brd->vector = (int)regs[11]; /* interrupt vector */
1da177e4 2508 if (id == 1)
1c45607a 2509 brd->vector_mask = 0x00FF;
1da177e4 2510 else
1c45607a 2511 brd->vector_mask = 0x000F;
1da177e4
LT		 2512 for (i = 7, bits = 0x0100; i >= 0; i--, bits <<= 1) {
2513 if (regs[12] & bits) {
1c45607a
JS		 2514 brd->ports[i].baud_base = 921600;
2515 brd->ports[i].max_baud = 921600;
1da177e4 2516 } else {
1c45607a
JS		 2517 brd->ports[i].baud_base = 115200;
2518 brd->ports[i].max_baud = 115200;
1da177e4
LT		 2519 }
2520 }
2521 scratch2 = inb(cap + UART_LCR) & (~UART_LCR_DLAB);
2522 outb(scratch2 | UART_LCR_DLAB, cap + UART_LCR);
2523 outb(0, cap + UART_EFR); /* EFR is the same as FCR */
2524 outb(scratch2, cap + UART_LCR);
2525 outb(UART_FCR_ENABLE_FIFO, cap + UART_FCR);
2526 scratch = inb(cap + UART_IIR);
2527
2528 if (scratch & 0xC0)
1c45607a 2529 brd->uart_type = PORT_16550A;
1da177e4 2530 else
1c45607a
JS		 2531 brd->uart_type = PORT_16450;
2532 if (!request_region(brd->ports[0].ioaddr, 8 * brd->info->nports,
83766bc6
JS		 2533 "mxser(IO)")) {
2534 printk(KERN_ERR "mxser: can't request ports I/O region: "
2535 "0x%.8lx-0x%.8lx\n",
2536 brd->ports[0].ioaddr, brd->ports[0].ioaddr +
2537 8 * brd->info->nports - 1);
2538 return -EIO;
2539 }
38daf88a
JS		 2540
2541 ret = mxser_request_vector(brd);
2542 if (ret) {
1c45607a 2543 release_region(brd->ports[0].ioaddr, 8 * brd->info->nports);
83766bc6
JS		 2544 printk(KERN_ERR "mxser: can't request interrupt vector region: "
2545 "0x%.8lx-0x%.8lx\n",
2546 brd->ports[0].ioaddr, brd->ports[0].ioaddr +
2547 8 * brd->info->nports - 1);
38daf88a 2548 return ret;
1c45607a
JS		 2549 }
2550 return brd->info->nports;
83766bc6
JS		 2551
2552err_irqconflict:
2553 printk(KERN_ERR "mxser: invalid interrupt number\n");
2554 return -EIO;
1da177e4
LT		 2555}
2556
9671f099 2557static int mxser_probe(struct pci_dev *pdev,
1c45607a 2558 const struct pci_device_id *ent)
1da177e4 2559{
1c45607a
JS		 2560#ifdef CONFIG_PCI
2561 struct mxser_board *brd;
2562 unsigned int i, j;
2563 unsigned long ioaddress;
9e17df37 2564 struct device *tty_dev;
1c45607a 2565 int retval = -EINVAL;
1da177e4 2566
1c45607a
JS		 2567 for (i = 0; i < MXSER_BOARDS; i++)
2568 if (mxser_boards[i].info == NULL)
2569 break;
2570
2571 if (i >= MXSER_BOARDS) {
83766bc6
JS		 2572 dev_err(&pdev->dev, "too many boards found (maximum %d), board "
2573 "not configured\n", MXSER_BOARDS);
1c45607a
JS		 2574 goto err;
2575 }
2576
2577 brd = &mxser_boards[i];
2578 brd->idx = i * MXSER_PORTS_PER_BOARD;
83766bc6 2579 dev_info(&pdev->dev, "found MOXA %s board (BusNo=%d, DevNo=%d)\n",
1c45607a
JS		 2580 mxser_cards[ent->driver_data].name,
2581 pdev->bus->number, PCI_SLOT(pdev->devfn));
2582
2583 retval = pci_enable_device(pdev);
2584 if (retval) {
83766bc6 2585 dev_err(&pdev->dev, "PCI enable failed\n");
1c45607a
JS		 2586 goto err;
2587 }
2588
2589 /* io address */
2590 ioaddress = pci_resource_start(pdev, 2);
2591 retval = pci_request_region(pdev, 2, "mxser(IO)");
2592 if (retval)
df480518 2593 goto err_dis;
1c45607a
JS		 2594
2595 brd->info = &mxser_cards[ent->driver_data];
2596 for (i = 0; i < brd->info->nports; i++)
2597 brd->ports[i].ioaddr = ioaddress + 8 * i;
2598
2599 /* vector */
2600 ioaddress = pci_resource_start(pdev, 3);
2601 retval = pci_request_region(pdev, 3, "mxser(vector)");
2602 if (retval)
df480518 2603 goto err_zero;
1c45607a
JS		 2604 brd->vector = ioaddress;
2605
2606 /* irq */
2607 brd->irq = pdev->irq;
2608
2609 brd->chip_flag = CheckIsMoxaMust(brd->ports[0].ioaddr);
2610 brd->uart_type = PORT_16550A;
2611 brd->vector_mask = 0;
2612
2613 for (i = 0; i < brd->info->nports; i++) {
2614 for (j = 0; j < UART_INFO_NUM; j++) {
2615 if (Gpci_uart_info[j].type == brd->chip_flag) {
2616 brd->ports[i].max_baud =
2617 Gpci_uart_info[j].max_baud;
2618
2619 /* exception....CP-102 */
2620 if (brd->info->flags & MXSER_HIGHBAUD)
2621 brd->ports[i].max_baud = 921600;
2622 break;
1da177e4
LT		 2623 }
2624 }
1c45607a
JS		 2625 }
2626
2627 if (brd->chip_flag == MOXA_MUST_MU860_HWID) {
2628 for (i = 0; i < brd->info->nports; i++) {
2629 if (i < 4)
2630 brd->ports[i].opmode_ioaddr = ioaddress + 4;
2631 else
2632 brd->ports[i].opmode_ioaddr = ioaddress + 0x0c;
1da177e4 2633 }
1c45607a
JS		 2634 outb(0, ioaddress + 4); /* default set to RS232 mode */
2635 outb(0, ioaddress + 0x0c); /* default set to RS232 mode */
1da177e4 2636 }
1c45607a
JS		 2637
2638 for (i = 0; i < brd->info->nports; i++) {
2639 brd->vector_mask |= (1 << i);
2640 brd->ports[i].baud_base = 921600;
2641 }
2642
2643 /* mxser_initbrd will hook ISR. */
2799707f 2644 retval = mxser_initbrd(brd);
1c45607a 2645 if (retval)
df480518 2646 goto err_rel3;
1c45607a 2647
9e17df37
AK		 2648 for (i = 0; i < brd->info->nports; i++) {
2649 tty_dev = tty_port_register_device(&brd->ports[i].port,
2650 mxvar_sdriver, brd->idx + i, &pdev->dev);
2651 if (IS_ERR(tty_dev)) {
2652 retval = PTR_ERR(tty_dev);
1b581f17 2653 for (; i > 0; i--)
9e17df37 2654 tty_unregister_device(mxvar_sdriver,
1b581f17 2655 brd->idx + i - 1);
9e17df37
AK		 2656 goto err_relbrd;
2657 }
2658 }
1c45607a
JS		 2659
2660 pci_set_drvdata(pdev, brd);
2661
2662 return 0;
9e17df37
AK		 2663err_relbrd:
2664 for (i = 0; i < brd->info->nports; i++)
2665 tty_port_destroy(&brd->ports[i].port);
2666 free_irq(brd->irq, brd);
df480518
JS		 2667err_rel3:
2668 pci_release_region(pdev, 3);
2669err_zero:
1c45607a 2670 brd->info = NULL;
df480518
JS		 2671 pci_release_region(pdev, 2);
2672err_dis:
2673 pci_disable_device(pdev);
1c45607a
JS		 2674err:
2675 return retval;
2676#else
2677 return -ENODEV;
2678#endif
1da177e4
LT		 2679}
2680
ae8d8a14 2681static void mxser_remove(struct pci_dev *pdev)
1da177e4 2682{
df480518 2683#ifdef CONFIG_PCI
1c45607a 2684 struct mxser_board *brd = pci_get_drvdata(pdev);
1da177e4 2685
191c5f10 2686 mxser_board_remove(brd);
1da177e4 2687
df480518
JS		 2688 pci_release_region(pdev, 2);
2689 pci_release_region(pdev, 3);
2690 pci_disable_device(pdev);
1c45607a 2691 brd->info = NULL;
df480518 2692#endif
1da177e4
LT		 2693}
2694
1c45607a
JS		 2695static struct pci_driver mxser_driver = {
2696 .name = "mxser",
2697 .id_table = mxser_pcibrds,
2698 .probe = mxser_probe,
91116cba 2699 .remove = mxser_remove
1c45607a
JS		 2700};
2701
2702static int __init mxser_module_init(void)
1da177e4 2703{
1c45607a 2704 struct mxser_board *brd;
9e17df37 2705 struct device *tty_dev;
1df00924
JS		 2706 unsigned int b, i, m;
2707 int retval;
1da177e4 2708
1c45607a
JS		 2709 mxvar_sdriver = alloc_tty_driver(MXSER_PORTS + 1);
2710 if (!mxvar_sdriver)
2711 return -ENOMEM;
2712
2713 printk(KERN_INFO "MOXA Smartio/Industio family driver version %s\n",
2714 MXSER_VERSION);
2715
2716 /* Initialize the tty_driver structure */
1c45607a
JS		 2717 mxvar_sdriver->name = "ttyMI";
2718 mxvar_sdriver->major = ttymajor;
2719 mxvar_sdriver->minor_start = 0;
1c45607a
JS		 2720 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL;
2721 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL;
2722 mxvar_sdriver->init_termios = tty_std_termios;
2723 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL;
2724 mxvar_sdriver->flags = TTY_DRIVER_REAL_RAW|TTY_DRIVER_DYNAMIC_DEV;
2725 tty_set_operations(mxvar_sdriver, &mxser_ops);
2726
2727 retval = tty_register_driver(mxvar_sdriver);
2728 if (retval) {
2729 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family "
2730 "tty driver !\n");
2731 goto err_put;
1da177e4 2732 }
1c45607a 2733
1c45607a 2734 /* Start finding ISA boards here */
1df00924
JS		 2735 for (m = 0, b = 0; b < MXSER_BOARDS; b++) {
2736 if (!ioaddr[b])
2737 continue;
2738
2739 brd = &mxser_boards[m];
96050dfb 2740 retval = mxser_get_ISA_conf(ioaddr[b], brd);
1df00924
JS		 2741 if (retval <= 0) {
2742 brd->info = NULL;
2743 continue;
2744 }
1c45607a 2745
1df00924
JS		 2746 printk(KERN_INFO "mxser: found MOXA %s board (CAP=0x%lx)\n",
2747 brd->info->name, ioaddr[b]);
83766bc6 2748
1df00924 2749 /* mxser_initbrd will hook ISR. */
2799707f 2750 if (mxser_initbrd(brd) < 0) {
9e17df37 2751 mxser_release_ISA_res(brd);
1df00924
JS		 2752 brd->info = NULL;
2753 continue;
2754 }
1c45607a 2755
1df00924 2756 brd->idx = m * MXSER_PORTS_PER_BOARD;
9e17df37
AK		 2757 for (i = 0; i < brd->info->nports; i++) {
2758 tty_dev = tty_port_register_device(&brd->ports[i].port,
734cc178 2759 mxvar_sdriver, brd->idx + i, NULL);
9e17df37 2760 if (IS_ERR(tty_dev)) {
1b581f17 2761 for (; i > 0; i--)
9e17df37 2762 tty_unregister_device(mxvar_sdriver,
1b581f17 2763 brd->idx + i - 1);
9e17df37
AK		 2764 for (i = 0; i < brd->info->nports; i++)
2765 tty_port_destroy(&brd->ports[i].port);
2766 free_irq(brd->irq, brd);
2767 mxser_release_ISA_res(brd);
2768 brd->info = NULL;
2769 break;
2770 }
2771 }
2772 if (brd->info == NULL)
2773 continue;
1c45607a 2774
1df00924
JS		 2775 m++;
2776 }
1c45607a
JS		 2777
2778 retval = pci_register_driver(&mxser_driver);
2779 if (retval) {
83766bc6 2780 printk(KERN_ERR "mxser: can't register pci driver\n");
1c45607a
JS		 2781 if (!m) {
2782 retval = -ENODEV;
2783 goto err_unr;
2784 } /* else: we have some ISA cards under control */
2785 }
2786
1c45607a
JS		 2787 return 0;
2788err_unr:
2789 tty_unregister_driver(mxvar_sdriver);
2790err_put:
2791 put_tty_driver(mxvar_sdriver);
2792 return retval;
2793}
2794
2795static void __exit mxser_module_exit(void)
2796{
191c5f10 2797 unsigned int i;
1c45607a 2798
1c45607a
JS		 2799 pci_unregister_driver(&mxser_driver);
2800
2801 for (i = 0; i < MXSER_BOARDS; i++) /* ISA remains */
2802 if (mxser_boards[i].info != NULL)
191c5f10 2803 mxser_board_remove(&mxser_boards[i]);
1c45607a
JS		 2804 tty_unregister_driver(mxvar_sdriver);
2805 put_tty_driver(mxvar_sdriver);
2806
2807 for (i = 0; i < MXSER_BOARDS; i++)
2808 if (mxser_boards[i].info != NULL)
df480518 2809 mxser_release_ISA_res(&mxser_boards[i]);
1da177e4
LT		 2810}
2811
2812module_init(mxser_module_init);
2813module_exit(mxser_module_exit);
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