]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/tty/rocket.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'sunxi-fixes-for-4.13-3' of https://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / tty / rocket.c
CommitLineData
1da177e4
LT		 1/*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42/****** Defines ******/
1da177e4
LT		 43#define ROCKET_PARANOIA_CHECK
44#define ROCKET_DISABLE_SIMUSAGE
45
46#undef ROCKET_SOFT_FLOW
47#undef ROCKET_DEBUG_OPEN
48#undef ROCKET_DEBUG_INTR
49#undef ROCKET_DEBUG_WRITE
50#undef ROCKET_DEBUG_FLOW
51#undef ROCKET_DEBUG_THROTTLE
52#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53#undef ROCKET_DEBUG_RECEIVE
54#undef ROCKET_DEBUG_HANGUP
55#undef REV_PCI_ORDER
56#undef ROCKET_DEBUG_IO
57
37c44b52 58#define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
1da177e4
LT		 59
60/****** Kernel includes ******/
61
1da177e4
LT		 62#include <linux/module.h>
63#include <linux/errno.h>
64#include <linux/major.h>
65#include <linux/kernel.h>
66#include <linux/signal.h>
67#include <linux/slab.h>
68#include <linux/mm.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/tty.h>
73#include <linux/tty_driver.h>
74#include <linux/tty_flip.h>
44b7d1b3 75#include <linux/serial.h>
1da177e4
LT		 76#include <linux/string.h>
77#include <linux/fcntl.h>
78#include <linux/ptrace.h>
69f545ea 79#include <linux/mutex.h>
1da177e4
LT		 80#include <linux/ioport.h>
81#include <linux/delay.h>
8cf5a8c5 82#include <linux/completion.h>
1da177e4
LT		 83#include <linux/wait.h>
84#include <linux/pci.h>
44b7d1b3 85#include <linux/uaccess.h>
60063497 86#include <linux/atomic.h>
457fb605 87#include <asm/unaligned.h>
1da177e4
LT		 88#include <linux/bitops.h>
89#include <linux/spinlock.h>
1da177e4
LT		 90#include <linux/init.h>
91
92/****** RocketPort includes ******/
93
94#include "rocket_int.h"
95#include "rocket.h"
96
97#define ROCKET_VERSION "2.09"
98#define ROCKET_DATE "12-June-2003"
99
100/****** RocketPort Local Variables ******/
101
40565f19
JS		 102static void rp_do_poll(unsigned long dummy);
103
1da177e4
LT		 104static struct tty_driver *rocket_driver;
105
106static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
108};
109
110static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113static atomic_t rp_num_ports_open; /* Number of serial ports open */
40565f19 114static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
1da177e4
LT		 115
116static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117static unsigned long board2;
118static unsigned long board3;
119static unsigned long board4;
120static unsigned long controller;
90ab5ee9 121static bool support_low_speed;
1da177e4
LT		 122static unsigned long modem1;
123static unsigned long modem2;
124static unsigned long modem3;
125static unsigned long modem4;
126static unsigned long pc104_1[8];
127static unsigned long pc104_2[8];
128static unsigned long pc104_3[8];
129static unsigned long pc104_4[8];
130static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131
132static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133static unsigned long rcktpt_io_addr[NUM_BOARDS];
134static int rcktpt_type[NUM_BOARDS];
135static int is_PCI[NUM_BOARDS];
136static rocketModel_t rocketModel[NUM_BOARDS];
137static int max_board;
31f35939 138static const struct tty_port_operations rocket_port_ops;
1da177e4
LT		 139
140/*
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
144 */
145
146static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147 AIOP_INTR_BIT_0,
148 AIOP_INTR_BIT_1,
149 AIOP_INTR_BIT_2,
150 AIOP_INTR_BIT_3
151};
152
416187ca 153#ifdef CONFIG_PCI
1da177e4
LT		 154static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
155 UPCI_AIOP_INTR_BIT_0,
156 UPCI_AIOP_INTR_BIT_1,
157 UPCI_AIOP_INTR_BIT_2,
158 UPCI_AIOP_INTR_BIT_3
159};
416187ca 160#endif
1da177e4 161
f15313bf
AB		 162static Byte_t RData[RDATASIZE] = {
163 0x00, 0x09, 0xf6, 0x82,
164 0x02, 0x09, 0x86, 0xfb,
165 0x04, 0x09, 0x00, 0x0a,
166 0x06, 0x09, 0x01, 0x0a,
167 0x08, 0x09, 0x8a, 0x13,
168 0x0a, 0x09, 0xc5, 0x11,
169 0x0c, 0x09, 0x86, 0x85,
170 0x0e, 0x09, 0x20, 0x0a,
171 0x10, 0x09, 0x21, 0x0a,
172 0x12, 0x09, 0x41, 0xff,
173 0x14, 0x09, 0x82, 0x00,
174 0x16, 0x09, 0x82, 0x7b,
175 0x18, 0x09, 0x8a, 0x7d,
176 0x1a, 0x09, 0x88, 0x81,
177 0x1c, 0x09, 0x86, 0x7a,
178 0x1e, 0x09, 0x84, 0x81,
179 0x20, 0x09, 0x82, 0x7c,
180 0x22, 0x09, 0x0a, 0x0a
181};
182
183static Byte_t RRegData[RREGDATASIZE] = {
184 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
197};
198
199static CONTROLLER_T sController[CTL_SIZE] = {
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208};
209
210static Byte_t sBitMapClrTbl[8] = {
211 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212};
213
214static Byte_t sBitMapSetTbl[8] = {
215 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216};
217
218static int sClockPrescale = 0x14;
219
1da177e4
LT		 220/*
221 * Line number is the ttySIx number (x), the Minor number. We
222 * assign them sequentially, starting at zero. The following
223 * array keeps track of the line number assigned to a given board/aiop/channel.
224 */
225static unsigned char lineNumbers[MAX_RP_PORTS];
226static unsigned long nextLineNumber;
227
228/***** RocketPort Static Prototypes *********/
229static int __init init_ISA(int i);
230static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231static void rp_flush_buffer(struct tty_struct *tty);
1da177e4
LT		 232static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
233static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
234static void rp_start(struct tty_struct *tty);
f15313bf
AB		 235static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236 int ChanNum);
237static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
238static void sFlushRxFIFO(CHANNEL_T * ChP);
239static void sFlushTxFIFO(CHANNEL_T * ChP);
240static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
241static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
242static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
243static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
244static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
f15313bf
AB		 245static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
246 ByteIO_t * AiopIOList, int AiopIOListSize,
247 int IRQNum, Byte_t Frequency, int PeriodicOnly);
248static int sReadAiopID(ByteIO_t io);
249static int sReadAiopNumChan(WordIO_t io);
1da177e4 250
1da177e4
LT		 251MODULE_AUTHOR("Theodore Ts'o");
252MODULE_DESCRIPTION("Comtrol RocketPort driver");
3b60daf8 253module_param_hw(board1, ulong, ioport, 0);
1da177e4 254MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
3b60daf8 255module_param_hw(board2, ulong, ioport, 0);
1da177e4 256MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
3b60daf8 257module_param_hw(board3, ulong, ioport, 0);
1da177e4 258MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
3b60daf8 259module_param_hw(board4, ulong, ioport, 0);
1da177e4 260MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
3b60daf8 261module_param_hw(controller, ulong, ioport, 0);
1da177e4
LT		 262MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
263module_param(support_low_speed, bool, 0);
264MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
265module_param(modem1, ulong, 0);
266MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
267module_param(modem2, ulong, 0);
268MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
269module_param(modem3, ulong, 0);
270MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
271module_param(modem4, ulong, 0);
272MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
273module_param_array(pc104_1, ulong, NULL, 0);
274MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
275module_param_array(pc104_2, ulong, NULL, 0);
276MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
277module_param_array(pc104_3, ulong, NULL, 0);
278MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
279module_param_array(pc104_4, ulong, NULL, 0);
280MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
281
d269cdd0 282static int rp_init(void);
1da177e4
LT		 283static void rp_cleanup_module(void);
284
285module_init(rp_init);
286module_exit(rp_cleanup_module);
287
1da177e4 288
1da177e4 289MODULE_LICENSE("Dual BSD/GPL");
1da177e4
LT		 290
291/*************************************************************************/
292/* Module code starts here */
293
294static inline int rocket_paranoia_check(struct r_port *info,
295 const char *routine)
296{
297#ifdef ROCKET_PARANOIA_CHECK
298 if (!info)
299 return 1;
300 if (info->magic != RPORT_MAGIC) {
68562b79
JS		 301 printk(KERN_WARNING "Warning: bad magic number for rocketport "
302 "struct in %s\n", routine);
1da177e4
LT		 303 return 1;
304 }
305#endif
306 return 0;
307}
308
309
310/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
311 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
312 * tty layer.
313 */
2e124b4a
JS		 314static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
315 unsigned int ChanStatus)
1da177e4
LT		 316{
317 unsigned int CharNStat;
cc44a817
PF		 318 int ToRecv, wRecv, space;
319 unsigned char *cbuf;
1da177e4
LT		 320
321 ToRecv = sGetRxCnt(cp);
1da177e4 322#ifdef ROCKET_DEBUG_INTR
68562b79 323 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
1da177e4 324#endif
cc44a817
PF		 325 if (ToRecv == 0)
326 return;
33f0f88f 327
1da177e4
LT		 328 /*
329 * if status indicates there are errored characters in the
330 * FIFO, then enter status mode (a word in FIFO holds
331 * character and status).
332 */
333 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
334 if (!(ChanStatus & STATMODE)) {
335#ifdef ROCKET_DEBUG_RECEIVE
68562b79 336 printk(KERN_INFO "Entering STATMODE...\n");
1da177e4
LT		 337#endif
338 ChanStatus |= STATMODE;
339 sEnRxStatusMode(cp);
340 }
341 }
342
343 /*
344 * if we previously entered status mode, then read down the
345 * FIFO one word at a time, pulling apart the character and
346 * the status. Update error counters depending on status
347 */
348 if (ChanStatus & STATMODE) {
349#ifdef ROCKET_DEBUG_RECEIVE
68562b79
JS		 350 printk(KERN_INFO "Ignore %x, read %x...\n",
351 info->ignore_status_mask, info->read_status_mask);
1da177e4
LT		 352#endif
353 while (ToRecv) {
cc44a817
PF		 354 char flag;
355
1da177e4
LT		 356 CharNStat = sInW(sGetTxRxDataIO(cp));
357#ifdef ROCKET_DEBUG_RECEIVE
68562b79 358 printk(KERN_INFO "%x...\n", CharNStat);
1da177e4
LT		 359#endif
360 if (CharNStat & STMBREAKH)
361 CharNStat &= ~(STMFRAMEH | STMPARITYH);
362 if (CharNStat & info->ignore_status_mask) {
363 ToRecv--;
364 continue;
365 }
366 CharNStat &= info->read_status_mask;
367 if (CharNStat & STMBREAKH)
cc44a817 368 flag = TTY_BREAK;
1da177e4 369 else if (CharNStat & STMPARITYH)
cc44a817 370 flag = TTY_PARITY;
1da177e4 371 else if (CharNStat & STMFRAMEH)
cc44a817 372 flag = TTY_FRAME;
1da177e4 373 else if (CharNStat & STMRCVROVRH)
cc44a817 374 flag = TTY_OVERRUN;
1da177e4 375 else
cc44a817 376 flag = TTY_NORMAL;
92a19f9c
JS		 377 tty_insert_flip_char(&info->port, CharNStat & 0xff,
378 flag);
1da177e4
LT		 379 ToRecv--;
380 }
381
382 /*
383 * after we've emptied the FIFO in status mode, turn
384 * status mode back off
385 */
386 if (sGetRxCnt(cp) == 0) {
387#ifdef ROCKET_DEBUG_RECEIVE
388 printk(KERN_INFO "Status mode off.\n");
389#endif
390 sDisRxStatusMode(cp);
391 }
392 } else {
393 /*
394 * we aren't in status mode, so read down the FIFO two
395 * characters at time by doing repeated word IO
396 * transfer.
397 */
2f693357 398 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
cc44a817
PF		 399 if (space < ToRecv) {
400#ifdef ROCKET_DEBUG_RECEIVE
401 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
402#endif
403 if (space <= 0)
404 return;
405 ToRecv = space;
406 }
1da177e4
LT		 407 wRecv = ToRecv >> 1;
408 if (wRecv)
409 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
410 if (ToRecv & 1)
411 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
1da177e4
LT		 412 }
413 /* Push the data up to the tty layer */
2e124b4a 414 tty_flip_buffer_push(&info->port);
1da177e4
LT		 415}
416
417/*
418 * Serial port transmit data function. Called from the timer polling loop as a
419 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
420 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
421 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
422 */
423static void rp_do_transmit(struct r_port *info)
424{
425 int c;
426 CHANNEL_t *cp = &info->channel;
427 struct tty_struct *tty;
428 unsigned long flags;
429
430#ifdef ROCKET_DEBUG_INTR
68562b79 431 printk(KERN_DEBUG "%s\n", __func__);
1da177e4
LT		 432#endif
433 if (!info)
434 return;
47b01b3a
AC		 435 tty = tty_port_tty_get(&info->port);
436
437 if (tty == NULL) {
438 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
1da177e4
LT		 439 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
440 return;
441 }
442
443 spin_lock_irqsave(&info->slock, flags);
1da177e4
LT		 444 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
445
446 /* Loop sending data to FIFO until done or FIFO full */
447 while (1) {
ee797069 448 if (tty->stopped)
1da177e4 449 break;
709107fc
HH		 450 c = min(info->xmit_fifo_room, info->xmit_cnt);
451 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
1da177e4
LT		 452 if (c <= 0 || info->xmit_fifo_room <= 0)
453 break;
454 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
455 if (c & 1)
456 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
457 info->xmit_tail += c;
458 info->xmit_tail &= XMIT_BUF_SIZE - 1;
459 info->xmit_cnt -= c;
460 info->xmit_fifo_room -= c;
461#ifdef ROCKET_DEBUG_INTR
68562b79 462 printk(KERN_INFO "tx %d chars...\n", c);
1da177e4
LT		 463#endif
464 }
465
466 if (info->xmit_cnt == 0)
467 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
468
469 if (info->xmit_cnt < WAKEUP_CHARS) {
470 tty_wakeup(tty);
1da177e4
LT		 471#ifdef ROCKETPORT_HAVE_POLL_WAIT
472 wake_up_interruptible(&tty->poll_wait);
473#endif
474 }
475
476 spin_unlock_irqrestore(&info->slock, flags);
47b01b3a 477 tty_kref_put(tty);
1da177e4
LT		 478
479#ifdef ROCKET_DEBUG_INTR
68562b79 480 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
1da177e4
LT		 481 info->xmit_tail, info->xmit_fifo_room);
482#endif
483}
484
485/*
486 * Called when a serial port signals it has read data in it's RX FIFO.
487 * It checks what interrupts are pending and services them, including
488 * receiving serial data.
489 */
490static void rp_handle_port(struct r_port *info)
491{
492 CHANNEL_t *cp;
1da177e4
LT		 493 unsigned int IntMask, ChanStatus;
494
495 if (!info)
496 return;
497
d41861ca 498 if (!tty_port_initialized(&info->port)) {
68562b79
JS		 499 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
500 "info->flags & NOT_INIT\n");
1da177e4
LT		 501 return;
502 }
2e124b4a 503
1da177e4 504 cp = &info->channel;
1da177e4
LT		 505
506 IntMask = sGetChanIntID(cp) & info->intmask;
507#ifdef ROCKET_DEBUG_INTR
68562b79 508 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
1da177e4
LT		 509#endif
510 ChanStatus = sGetChanStatus(cp);
511 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
2e124b4a 512 rp_do_receive(info, cp, ChanStatus);
1da177e4
LT		 513 }
514 if (IntMask & DELTA_CD) { /* CD change */
515#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
68562b79 516 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
1da177e4
LT		 517 (ChanStatus & CD_ACT) ? "on" : "off");
518#endif
519 if (!(ChanStatus & CD_ACT) && info->cd_status) {
520#ifdef ROCKET_DEBUG_HANGUP
521 printk(KERN_INFO "CD drop, calling hangup.\n");
522#endif
aa27a094 523 tty_port_tty_hangup(&info->port, false);
1da177e4
LT		 524 }
525 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
e60a1084 526 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 527 }
528#ifdef ROCKET_DEBUG_INTR
529 if (IntMask & DELTA_CTS) { /* CTS change */
530 printk(KERN_INFO "CTS change...\n");
531 }
532 if (IntMask & DELTA_DSR) { /* DSR change */
533 printk(KERN_INFO "DSR change...\n");
534 }
535#endif
536}
537
538/*
539 * The top level polling routine. Repeats every 1/100 HZ (10ms).
540 */
541static void rp_do_poll(unsigned long dummy)
542{
543 CONTROLLER_t *ctlp;
6c0286b1
JS		 544 int ctrl, aiop, ch, line;
545 unsigned int xmitmask, i;
1da177e4
LT		 546 unsigned int CtlMask;
547 unsigned char AiopMask;
548 Word_t bit;
549
550 /* Walk through all the boards (ctrl's) */
551 for (ctrl = 0; ctrl < max_board; ctrl++) {
552 if (rcktpt_io_addr[ctrl] <= 0)
553 continue;
554
555 /* Get a ptr to the board's control struct */
556 ctlp = sCtlNumToCtlPtr(ctrl);
557
3a4fa0a2 558 /* Get the interrupt status from the board */
1da177e4
LT		 559#ifdef CONFIG_PCI
560 if (ctlp->BusType == isPCI)
561 CtlMask = sPCIGetControllerIntStatus(ctlp);
562 else
563#endif
564 CtlMask = sGetControllerIntStatus(ctlp);
565
566 /* Check if any AIOP read bits are set */
567 for (aiop = 0; CtlMask; aiop++) {
568 bit = ctlp->AiopIntrBits[aiop];
569 if (CtlMask & bit) {
570 CtlMask &= ~bit;
571 AiopMask = sGetAiopIntStatus(ctlp, aiop);
572
573 /* Check if any port read bits are set */
574 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
575 if (AiopMask & 1) {
576
577 /* Get the line number (/dev/ttyRx number). */
578 /* Read the data from the port. */
579 line = GetLineNumber(ctrl, aiop, ch);
580 rp_handle_port(rp_table[line]);
581 }
582 }
583 }
584 }
585
586 xmitmask = xmit_flags[ctrl];
587
588 /*
589 * xmit_flags contains bit-significant flags, indicating there is data
590 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
591 * 1, ... (32 total possible). The variable i has the aiop and ch
592 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
593 */
594 if (xmitmask) {
595 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
596 if (xmitmask & (1 << i)) {
597 aiop = (i & 0x18) >> 3;
598 ch = i & 0x07;
599 line = GetLineNumber(ctrl, aiop, ch);
600 rp_do_transmit(rp_table[line]);
601 }
602 }
603 }
604 }
605
606 /*
607 * Reset the timer so we get called at the next clock tick (10ms).
608 */
609 if (atomic_read(&rp_num_ports_open))
610 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
611}
612
613/*
614 * Initializes the r_port structure for a port, as well as enabling the port on
615 * the board.
616 * Inputs: board, aiop, chan numbers
617 */
06ed48b7
JL		 618static void __init
619init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
1da177e4
LT		 620{
621 unsigned rocketMode;
622 struct r_port *info;
623 int line;
624 CONTROLLER_T *ctlp;
625
626 /* Get the next available line number */
627 line = SetLineNumber(board, aiop, chan);
628
629 ctlp = sCtlNumToCtlPtr(board);
630
631 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
dd00cc48 632 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
1da177e4 633 if (!info) {
68562b79
JS		 634 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
635 line);
1da177e4
LT		 636 return;
637 }
1da177e4
LT		 638
639 info->magic = RPORT_MAGIC;
640 info->line = line;
641 info->ctlp = ctlp;
642 info->board = board;
643 info->aiop = aiop;
644 info->chan = chan;
31f35939
AC		 645 tty_port_init(&info->port);
646 info->port.ops = &rocket_port_ops;
1da177e4
LT		 647 info->flags &= ~ROCKET_MODE_MASK;
648 switch (pc104[board][line]) {
649 case 422:
650 info->flags |= ROCKET_MODE_RS422;
651 break;
652 case 485:
653 info->flags |= ROCKET_MODE_RS485;
654 break;
655 case 232:
656 default:
657 info->flags |= ROCKET_MODE_RS232;
658 break;
659 }
660
661 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
662 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
68562b79
JS		 663 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
664 board, aiop, chan);
191c5f10 665 tty_port_destroy(&info->port);
1da177e4
LT		 666 kfree(info);
667 return;
668 }
669
670 rocketMode = info->flags & ROCKET_MODE_MASK;
671
672 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
673 sEnRTSToggle(&info->channel);
674 else
675 sDisRTSToggle(&info->channel);
676
677 if (ctlp->boardType == ROCKET_TYPE_PC104) {
678 switch (rocketMode) {
679 case ROCKET_MODE_RS485:
680 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
681 break;
682 case ROCKET_MODE_RS422:
683 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
684 break;
685 case ROCKET_MODE_RS232:
686 default:
687 if (info->flags & ROCKET_RTS_TOGGLE)
688 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
689 else
690 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
691 break;
692 }
693 }
694 spin_lock_init(&info->slock);
69f545ea 695 mutex_init(&info->write_mtx);
1da177e4 696 rp_table[line] = info;
734cc178
JS		 697 tty_port_register_device(&info->port, rocket_driver, line,
698 pci_dev ? &pci_dev->dev : NULL);
1da177e4
LT		 699}
700
701/*
702 * Configures a rocketport port according to its termio settings. Called from
703 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
704 */
47b01b3a 705static void configure_r_port(struct tty_struct *tty, struct r_port *info,
606d099c 706 struct ktermios *old_termios)
1da177e4
LT		 707{
708 unsigned cflag;
709 unsigned long flags;
710 unsigned rocketMode;
711 int bits, baud, divisor;
712 CHANNEL_t *cp;
adc8d746 713 struct ktermios *t = &tty->termios;
1da177e4 714
1da177e4 715 cp = &info->channel;
6df3526b 716 cflag = t->c_cflag;
1da177e4
LT		 717
718 /* Byte size and parity */
719 if ((cflag & CSIZE) == CS8) {
720 sSetData8(cp);
721 bits = 10;
722 } else {
723 sSetData7(cp);
724 bits = 9;
725 }
726 if (cflag & CSTOPB) {
727 sSetStop2(cp);
728 bits++;
729 } else {
730 sSetStop1(cp);
731 }
732
733 if (cflag & PARENB) {
734 sEnParity(cp);
735 bits++;
736 if (cflag & PARODD) {
737 sSetOddParity(cp);
738 } else {
739 sSetEvenParity(cp);
740 }
741 } else {
742 sDisParity(cp);
743 }
744
745 /* baud rate */
47b01b3a 746 baud = tty_get_baud_rate(tty);
1da177e4
LT		 747 if (!baud)
748 baud = 9600;
749 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
750 if ((divisor >= 8192 || divisor < 0) && old_termios) {
6df3526b 751 baud = tty_termios_baud_rate(old_termios);
1da177e4
LT		 752 if (!baud)
753 baud = 9600;
754 divisor = (rp_baud_base[info->board] / baud) - 1;
755 }
756 if (divisor >= 8192 || divisor < 0) {
757 baud = 9600;
758 divisor = (rp_baud_base[info->board] / baud) - 1;
759 }
760 info->cps = baud / bits;
761 sSetBaud(cp, divisor);
762
6df3526b 763 /* FIXME: Should really back compute a baud rate from the divisor */
47b01b3a 764 tty_encode_baud_rate(tty, baud, baud);
6df3526b 765
1da177e4
LT		 766 if (cflag & CRTSCTS) {
767 info->intmask |= DELTA_CTS;
768 sEnCTSFlowCtl(cp);
769 } else {
770 info->intmask &= ~DELTA_CTS;
771 sDisCTSFlowCtl(cp);
772 }
773 if (cflag & CLOCAL) {
774 info->intmask &= ~DELTA_CD;
775 } else {
776 spin_lock_irqsave(&info->slock, flags);
777 if (sGetChanStatus(cp) & CD_ACT)
778 info->cd_status = 1;
779 else
780 info->cd_status = 0;
781 info->intmask |= DELTA_CD;
782 spin_unlock_irqrestore(&info->slock, flags);
783 }
784
785 /*
786 * Handle software flow control in the board
787 */
788#ifdef ROCKET_SOFT_FLOW
47b01b3a 789 if (I_IXON(tty)) {
1da177e4 790 sEnTxSoftFlowCtl(cp);
47b01b3a 791 if (I_IXANY(tty)) {
1da177e4
LT		 792 sEnIXANY(cp);
793 } else {
794 sDisIXANY(cp);
795 }
47b01b3a
AC		 796 sSetTxXONChar(cp, START_CHAR(tty));
797 sSetTxXOFFChar(cp, STOP_CHAR(tty));
1da177e4
LT		 798 } else {
799 sDisTxSoftFlowCtl(cp);
800 sDisIXANY(cp);
801 sClrTxXOFF(cp);
802 }
803#endif
804
805 /*
806 * Set up ignore/read mask words
807 */
808 info->read_status_mask = STMRCVROVRH | 0xFF;
47b01b3a 809 if (I_INPCK(tty))
1da177e4 810 info->read_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 811 if (I_BRKINT(tty) || I_PARMRK(tty))
1da177e4
LT		 812 info->read_status_mask |= STMBREAKH;
813
814 /*
815 * Characters to ignore
816 */
817 info->ignore_status_mask = 0;
47b01b3a 818 if (I_IGNPAR(tty))
1da177e4 819 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 820 if (I_IGNBRK(tty)) {
1da177e4
LT		 821 info->ignore_status_mask |= STMBREAKH;
822 /*
823 * If we're ignoring parity and break indicators,
824 * ignore overruns too. (For real raw support).
825 */
47b01b3a 826 if (I_IGNPAR(tty))
1da177e4
LT		 827 info->ignore_status_mask |= STMRCVROVRH;
828 }
829
830 rocketMode = info->flags & ROCKET_MODE_MASK;
831
832 if ((info->flags & ROCKET_RTS_TOGGLE)
833 || (rocketMode == ROCKET_MODE_RS485))
834 sEnRTSToggle(cp);
835 else
836 sDisRTSToggle(cp);
837
838 sSetRTS(&info->channel);
839
840 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
841 switch (rocketMode) {
842 case ROCKET_MODE_RS485:
843 sSetInterfaceMode(cp, InterfaceModeRS485);
844 break;
845 case ROCKET_MODE_RS422:
846 sSetInterfaceMode(cp, InterfaceModeRS422);
847 break;
848 case ROCKET_MODE_RS232:
849 default:
850 if (info->flags & ROCKET_RTS_TOGGLE)
851 sSetInterfaceMode(cp, InterfaceModeRS232T);
852 else
853 sSetInterfaceMode(cp, InterfaceModeRS232);
854 break;
855 }
856 }
857}
858
31f35939
AC		 859static int carrier_raised(struct tty_port *port)
860{
861 struct r_port *info = container_of(port, struct r_port, port);
862 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
863}
864
fcc8ac18 865static void dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 866{
867 struct r_port *info = container_of(port, struct r_port, port);
fcc8ac18
AC		 868 if (on) {
869 sSetDTR(&info->channel);
870 sSetRTS(&info->channel);
871 } else {
872 sClrDTR(&info->channel);
873 sClrRTS(&info->channel);
874 }
5d951fb4
AC		 875}
876
1da177e4
LT		 877/*
878 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
879 * port's r_port struct. Initializes the port hardware.
880 */
881static int rp_open(struct tty_struct *tty, struct file *filp)
882{
883 struct r_port *info;
fba85e01 884 struct tty_port *port;
410235fd 885 int retval;
1da177e4
LT		 886 CHANNEL_t *cp;
887 unsigned long page;
888
410235fd
JS		 889 info = rp_table[tty->index];
890 if (info == NULL)
1da177e4 891 return -ENXIO;
fba85e01
AC		 892 port = &info->port;
893
1da177e4
LT		 894 page = __get_free_page(GFP_KERNEL);
895 if (!page)
896 return -ENOMEM;
897
1da177e4
LT		 898 /*
899 * We must not sleep from here until the port is marked fully in use.
900 */
901 if (info->xmit_buf)
902 free_page(page);
903 else
904 info->xmit_buf = (unsigned char *) page;
905
906 tty->driver_data = info;
fba85e01 907 tty_port_tty_set(port, tty);
1da177e4 908
fba85e01 909 if (port->count++ == 0) {
1da177e4
LT		 910 atomic_inc(&rp_num_ports_open);
911
912#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 913 printk(KERN_INFO "rocket mod++ = %d...\n",
914 atomic_read(&rp_num_ports_open));
1da177e4
LT		 915#endif
916 }
917#ifdef ROCKET_DEBUG_OPEN
e60a1084 918 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
1da177e4
LT		 919#endif
920
921 /*
922 * Info->count is now 1; so it's safe to sleep now.
923 */
d41861ca 924 if (!tty_port_initialized(port)) {
1da177e4
LT		 925 cp = &info->channel;
926 sSetRxTrigger(cp, TRIG_1);
927 if (sGetChanStatus(cp) & CD_ACT)
928 info->cd_status = 1;
929 else
930 info->cd_status = 0;
931 sDisRxStatusMode(cp);
932 sFlushRxFIFO(cp);
933 sFlushTxFIFO(cp);
934
935 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
936 sSetRxTrigger(cp, TRIG_1);
937
938 sGetChanStatus(cp);
939 sDisRxStatusMode(cp);
940 sClrTxXOFF(cp);
941
942 sDisCTSFlowCtl(cp);
943 sDisTxSoftFlowCtl(cp);
944
945 sEnRxFIFO(cp);
946 sEnTransmit(cp);
947
d41861ca 948 tty_port_set_initialized(&info->port, 1);
1da177e4 949
47b01b3a 950 configure_r_port(tty, info, NULL);
9db276f8 951 if (C_BAUD(tty)) {
1da177e4
LT		 952 sSetDTR(cp);
953 sSetRTS(cp);
954 }
955 }
956 /* Starts (or resets) the maint polling loop */
957 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
958
fba85e01 959 retval = tty_port_block_til_ready(port, tty, filp);
1da177e4
LT		 960 if (retval) {
961#ifdef ROCKET_DEBUG_OPEN
962 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
963#endif
964 return retval;
965 }
966 return 0;
967}
968
969/*
e60a1084 970 * Exception handler that closes a serial port. info->port.count is considered critical.
1da177e4
LT		 971 */
972static void rp_close(struct tty_struct *tty, struct file *filp)
973{
c9f19e96 974 struct r_port *info = tty->driver_data;
c1314a49 975 struct tty_port *port = &info->port;
1da177e4
LT		 976 int timeout;
977 CHANNEL_t *cp;
978
979 if (rocket_paranoia_check(info, "rp_close"))
980 return;
981
982#ifdef ROCKET_DEBUG_OPEN
e60a1084 983 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1da177e4
LT		 984#endif
985
fba85e01 986 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 987 return;
1da177e4 988
417b6e0e 989 mutex_lock(&port->mutex);
1da177e4 990 cp = &info->channel;
1da177e4
LT		 991 /*
992 * Before we drop DTR, make sure the UART transmitter
993 * has completely drained; this is especially
994 * important if there is a transmit FIFO!
995 */
996 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
997 if (timeout == 0)
998 timeout = 1;
999 rp_wait_until_sent(tty, timeout);
1000 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1001
1002 sDisTransmit(cp);
1003 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1004 sDisCTSFlowCtl(cp);
1005 sDisTxSoftFlowCtl(cp);
1006 sClrTxXOFF(cp);
1007 sFlushRxFIFO(cp);
1008 sFlushTxFIFO(cp);
1009 sClrRTS(cp);
1010 if (C_HUPCL(tty))
1011 sClrDTR(cp);
1012
f6de0c98 1013 rp_flush_buffer(tty);
1da177e4
LT		 1014
1015 tty_ldisc_flush(tty);
1016
1017 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1018
fba85e01
AC		 1019 /* We can't yet use tty_port_close_end as the buffer handling in this
1020 driver is a bit different to the usual */
1021
c1314a49
AC		 1022 if (port->blocked_open) {
1023 if (port->close_delay) {
1024 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1da177e4 1025 }
c1314a49 1026 wake_up_interruptible(&port->open_wait);
1da177e4
LT		 1027 } else {
1028 if (info->xmit_buf) {
1029 free_page((unsigned long) info->xmit_buf);
1030 info->xmit_buf = NULL;
1031 }
1032 }
417b6e0e 1033 spin_lock_irq(&port->lock);
1da177e4 1034 tty->closing = 0;
417b6e0e 1035 spin_unlock_irq(&port->lock);
d41861ca 1036 tty_port_set_initialized(port, 0);
807c8d81 1037 tty_port_set_active(port, 0);
417b6e0e 1038 mutex_unlock(&port->mutex);
fba85e01 1039 tty_port_tty_set(port, NULL);
417b6e0e 1040
1da177e4
LT		 1041 atomic_dec(&rp_num_ports_open);
1042
1043#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1044 printk(KERN_INFO "rocket mod-- = %d...\n",
1045 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1046 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1047#endif
1048
1049}
1050
1051static void rp_set_termios(struct tty_struct *tty,
606d099c 1052 struct ktermios *old_termios)
1da177e4 1053{
c9f19e96 1054 struct r_port *info = tty->driver_data;
1da177e4
LT		 1055 CHANNEL_t *cp;
1056 unsigned cflag;
1057
1058 if (rocket_paranoia_check(info, "rp_set_termios"))
1059 return;
1060
adc8d746 1061 cflag = tty->termios.c_cflag;
1da177e4 1062
1da177e4
LT		 1063 /*
1064 * This driver doesn't support CS5 or CS6
1065 */
1066 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
adc8d746 1067 tty->termios.c_cflag =
1da177e4 1068 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
6df3526b 1069 /* Or CMSPAR */
adc8d746 1070 tty->termios.c_cflag &= ~CMSPAR;
1da177e4 1071
47b01b3a 1072 configure_r_port(tty, info, old_termios);
1da177e4
LT		 1073
1074 cp = &info->channel;
1075
1076 /* Handle transition to B0 status */
9db276f8 1077 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
1da177e4
LT		 1078 sClrDTR(cp);
1079 sClrRTS(cp);
1080 }
1081
1082 /* Handle transition away from B0 status */
9db276f8 1083 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
ee797069 1084 sSetRTS(cp);
1da177e4
LT		 1085 sSetDTR(cp);
1086 }
1087
9db276f8 1088 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
1da177e4 1089 rp_start(tty);
1da177e4
LT		 1090}
1091
9e98966c 1092static int rp_break(struct tty_struct *tty, int break_state)
1da177e4 1093{
c9f19e96 1094 struct r_port *info = tty->driver_data;
1da177e4
LT		 1095 unsigned long flags;
1096
1097 if (rocket_paranoia_check(info, "rp_break"))
9e98966c 1098 return -EINVAL;
1da177e4
LT		 1099
1100 spin_lock_irqsave(&info->slock, flags);
1101 if (break_state == -1)
1102 sSendBreak(&info->channel);
1103 else
1104 sClrBreak(&info->channel);
1105 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 1106 return 0;
1da177e4
LT		 1107}
1108
1109/*
1110 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1111 * the UPCI boards was added, it was decided to make this a function because
1112 * the macro was getting too complicated. All cases except the first one
1113 * (UPCIRingInd) are taken directly from the original macro.
1114 */
1115static int sGetChanRI(CHANNEL_T * ChP)
1116{
1117 CONTROLLER_t *CtlP = ChP->CtlP;
1118 int ChanNum = ChP->ChanNum;
1119 int RingInd = 0;
1120
1121 if (CtlP->UPCIRingInd)
1122 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1123 else if (CtlP->AltChanRingIndicator)
1124 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1125 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1126 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1127
1128 return RingInd;
1129}
1130
1131/********************************************************************************************/
1132/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1133
1134/*
1135 * Returns the state of the serial modem control lines. These next 2 functions
1136 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1137 */
60b33c13 1138static int rp_tiocmget(struct tty_struct *tty)
1da177e4 1139{
c9f19e96 1140 struct r_port *info = tty->driver_data;
1da177e4
LT		 1141 unsigned int control, result, ChanStatus;
1142
1143 ChanStatus = sGetChanStatusLo(&info->channel);
1144 control = info->channel.TxControl[3];
1145 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1146 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1147 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1148 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1149 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1150 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1151
1152 return result;
1153}
1154
1155/*
1156 * Sets the modem control lines
1157 */
20b9d177
AC		 1158static int rp_tiocmset(struct tty_struct *tty,
1159 unsigned int set, unsigned int clear)
1da177e4 1160{
c9f19e96 1161 struct r_port *info = tty->driver_data;
1da177e4
LT		 1162
1163 if (set & TIOCM_RTS)
1164 info->channel.TxControl[3] |= SET_RTS;
1165 if (set & TIOCM_DTR)
1166 info->channel.TxControl[3] |= SET_DTR;
1167 if (clear & TIOCM_RTS)
1168 info->channel.TxControl[3] &= ~SET_RTS;
1169 if (clear & TIOCM_DTR)
1170 info->channel.TxControl[3] &= ~SET_DTR;
1171
457fb605 1172 out32(info->channel.IndexAddr, info->channel.TxControl);
1da177e4
LT		 1173 return 0;
1174}
1175
1176static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1177{
1178 struct rocket_config tmp;
1179
1da177e4 1180 memset(&tmp, 0, sizeof (tmp));
417b6e0e 1181 mutex_lock(&info->port.mutex);
1da177e4
LT		 1182 tmp.line = info->line;
1183 tmp.flags = info->flags;
44b7d1b3
AC		 1184 tmp.close_delay = info->port.close_delay;
1185 tmp.closing_wait = info->port.closing_wait;
1da177e4 1186 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
417b6e0e 1187 mutex_unlock(&info->port.mutex);
1da177e4
LT		 1188
1189 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1190 return -EFAULT;
1191 return 0;
1192}
1193
47b01b3a
AC		 1194static int set_config(struct tty_struct *tty, struct r_port *info,
1195 struct rocket_config __user *new_info)
1da177e4
LT		 1196{
1197 struct rocket_config new_serial;
1198
1199 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1200 return -EFAULT;
1201
417b6e0e 1202 mutex_lock(&info->port.mutex);
1da177e4
LT		 1203 if (!capable(CAP_SYS_ADMIN))
1204 {
417b6e0e
AC		 1205 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1206 mutex_unlock(&info->port.mutex);
1da177e4 1207 return -EPERM;
417b6e0e 1208 }
1da177e4 1209 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
49bf7eaf 1210 mutex_unlock(&info->port.mutex);
1da177e4
LT		 1211 return 0;
1212 }
1213
48a7bd11
JH		 1214 if ((new_serial.flags ^ info->flags) & ROCKET_SPD_MASK) {
1215 /* warn about deprecation, unless clearing */
1216 if (new_serial.flags & ROCKET_SPD_MASK)
1217 dev_warn_ratelimited(tty->dev, "use of SPD flags is deprecated\n");
1218 }
1219
1da177e4 1220 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
44b7d1b3
AC		 1221 info->port.close_delay = new_serial.close_delay;
1222 info->port.closing_wait = new_serial.closing_wait;
1da177e4 1223
417b6e0e 1224 mutex_unlock(&info->port.mutex);
1da177e4 1225
47b01b3a 1226 configure_r_port(tty, info, NULL);
1da177e4
LT		 1227 return 0;
1228}
1229
1230/*
1231 * This function fills in a rocket_ports struct with information
1232 * about what boards/ports are in the system. This info is passed
1233 * to user space. See setrocket.c where the info is used to create
1234 * the /dev/ttyRx ports.
1235 */
1236static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1237{
1238 struct rocket_ports tmp;
1239 int board;
1240
1da177e4
LT		 1241 memset(&tmp, 0, sizeof (tmp));
1242 tmp.tty_major = rocket_driver->major;
1243
1244 for (board = 0; board < 4; board++) {
1245 tmp.rocketModel[board].model = rocketModel[board].model;
1246 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1247 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1248 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1249 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1250 }
1251 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1252 return -EFAULT;
1253 return 0;
1254}
1255
1256static int reset_rm2(struct r_port *info, void __user *arg)
1257{
1258 int reset;
1259
4129a645
AC		 1260 if (!capable(CAP_SYS_ADMIN))
1261 return -EPERM;
1262
1da177e4
LT		 1263 if (copy_from_user(&reset, arg, sizeof (int)))
1264 return -EFAULT;
1265 if (reset)
1266 reset = 1;
1267
1268 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1269 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1270 return -EINVAL;
1271
1272 if (info->ctlp->BusType == isISA)
1273 sModemReset(info->ctlp, info->chan, reset);
1274 else
1275 sPCIModemReset(info->ctlp, info->chan, reset);
1276
1277 return 0;
1278}
1279
1280static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1281{
1282 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1283 return -EFAULT;
1284 return 0;
1285}
1286
1287/* IOCTL call handler into the driver */
6caa76b7 1288static int rp_ioctl(struct tty_struct *tty,
1da177e4
LT		 1289 unsigned int cmd, unsigned long arg)
1290{
c9f19e96 1291 struct r_port *info = tty->driver_data;
1da177e4 1292 void __user *argp = (void __user *)arg;
bdf183aa 1293 int ret = 0;
1da177e4
LT		 1294
1295 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1296 return -ENXIO;
1297
1298 switch (cmd) {
1299 case RCKP_GET_STRUCT:
1300 if (copy_to_user(argp, info, sizeof (struct r_port)))
bdf183aa
AC		 1301 ret = -EFAULT;
1302 break;
1da177e4 1303 case RCKP_GET_CONFIG:
bdf183aa
AC		 1304 ret = get_config(info, argp);
1305 break;
1da177e4 1306 case RCKP_SET_CONFIG:
47b01b3a 1307 ret = set_config(tty, info, argp);
bdf183aa 1308 break;
1da177e4 1309 case RCKP_GET_PORTS:
bdf183aa
AC		 1310 ret = get_ports(info, argp);
1311 break;
1da177e4 1312 case RCKP_RESET_RM2:
bdf183aa
AC		 1313 ret = reset_rm2(info, argp);
1314 break;
1da177e4 1315 case RCKP_GET_VERSION:
bdf183aa
AC		 1316 ret = get_version(info, argp);
1317 break;
1da177e4 1318 default:
bdf183aa 1319 ret = -ENOIOCTLCMD;
1da177e4 1320 }
bdf183aa 1321 return ret;
1da177e4
LT		 1322}
1323
1324static void rp_send_xchar(struct tty_struct *tty, char ch)
1325{
c9f19e96 1326 struct r_port *info = tty->driver_data;
1da177e4
LT		 1327 CHANNEL_t *cp;
1328
1329 if (rocket_paranoia_check(info, "rp_send_xchar"))
1330 return;
1331
1332 cp = &info->channel;
1333 if (sGetTxCnt(cp))
1334 sWriteTxPrioByte(cp, ch);
1335 else
1336 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1337}
1338
1339static void rp_throttle(struct tty_struct *tty)
1340{
c9f19e96 1341 struct r_port *info = tty->driver_data;
1da177e4
LT		 1342
1343#ifdef ROCKET_DEBUG_THROTTLE
fdfb719e 1344 printk(KERN_INFO "throttle %s ....\n", tty->name);
1da177e4
LT		 1345#endif
1346
1347 if (rocket_paranoia_check(info, "rp_throttle"))
1348 return;
1349
1da177e4
LT		 1350 if (I_IXOFF(tty))
1351 rp_send_xchar(tty, STOP_CHAR(tty));
1352
1353 sClrRTS(&info->channel);
1354}
1355
1356static void rp_unthrottle(struct tty_struct *tty)
1357{
c9f19e96 1358 struct r_port *info = tty->driver_data;
1da177e4 1359#ifdef ROCKET_DEBUG_THROTTLE
fdfb719e 1360 printk(KERN_INFO "unthrottle %s ....\n", tty->name);
1da177e4
LT		 1361#endif
1362
e5f50fbe 1363 if (rocket_paranoia_check(info, "rp_unthrottle"))
1da177e4
LT		 1364 return;
1365
1da177e4
LT		 1366 if (I_IXOFF(tty))
1367 rp_send_xchar(tty, START_CHAR(tty));
1368
1369 sSetRTS(&info->channel);
1370}
1371
1372/*
1373 * ------------------------------------------------------------
1374 * rp_stop() and rp_start()
1375 *
1376 * This routines are called before setting or resetting tty->stopped.
1377 * They enable or disable transmitter interrupts, as necessary.
1378 * ------------------------------------------------------------
1379 */
1380static void rp_stop(struct tty_struct *tty)
1381{
c9f19e96 1382 struct r_port *info = tty->driver_data;
1da177e4
LT		 1383
1384#ifdef ROCKET_DEBUG_FLOW
1385 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1386 info->xmit_cnt, info->xmit_fifo_room);
1387#endif
1388
1389 if (rocket_paranoia_check(info, "rp_stop"))
1390 return;
1391
1392 if (sGetTxCnt(&info->channel))
1393 sDisTransmit(&info->channel);
1394}
1395
1396static void rp_start(struct tty_struct *tty)
1397{
c9f19e96 1398 struct r_port *info = tty->driver_data;
1da177e4
LT		 1399
1400#ifdef ROCKET_DEBUG_FLOW
1401 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1402 info->xmit_cnt, info->xmit_fifo_room);
1403#endif
1404
1405 if (rocket_paranoia_check(info, "rp_stop"))
1406 return;
1407
1408 sEnTransmit(&info->channel);
1409 set_bit((info->aiop * 8) + info->chan,
1410 (void *) &xmit_flags[info->board]);
1411}
1412
1413/*
1414 * rp_wait_until_sent() --- wait until the transmitter is empty
1415 */
1416static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1417{
c9f19e96 1418 struct r_port *info = tty->driver_data;
1da177e4
LT		 1419 CHANNEL_t *cp;
1420 unsigned long orig_jiffies;
1421 int check_time, exit_time;
1422 int txcnt;
1423
1424 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1425 return;
1426
1427 cp = &info->channel;
1428
1429 orig_jiffies = jiffies;
1430#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
e5f50fbe 1431 printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1da177e4 1432 jiffies);
68562b79 1433 printk(KERN_INFO "cps=%d...\n", info->cps);
1da177e4
LT		 1434#endif
1435 while (1) {
1436 txcnt = sGetTxCnt(cp);
1437 if (!txcnt) {
1438 if (sGetChanStatusLo(cp) & TXSHRMT)
1439 break;
1440 check_time = (HZ / info->cps) / 5;
1441 } else {
1442 check_time = HZ * txcnt / info->cps;
1443 }
1444 if (timeout) {
1445 exit_time = orig_jiffies + timeout - jiffies;
1446 if (exit_time <= 0)
1447 break;
1448 if (exit_time < check_time)
1449 check_time = exit_time;
1450 }
1451 if (check_time == 0)
1452 check_time = 1;
1453#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79
JS		 1454 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1455 jiffies, check_time);
1da177e4
LT		 1456#endif
1457 msleep_interruptible(jiffies_to_msecs(check_time));
1458 if (signal_pending(current))
1459 break;
1460 }
cc0a8fbb 1461 __set_current_state(TASK_RUNNING);
1da177e4
LT		 1462#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1463 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1464#endif
1465}
1466
1467/*
1468 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1469 */
1470static void rp_hangup(struct tty_struct *tty)
1471{
1472 CHANNEL_t *cp;
c9f19e96 1473 struct r_port *info = tty->driver_data;
417b6e0e 1474 unsigned long flags;
1da177e4
LT		 1475
1476 if (rocket_paranoia_check(info, "rp_hangup"))
1477 return;
1478
1479#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
68562b79 1480 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1da177e4
LT		 1481#endif
1482 rp_flush_buffer(tty);
417b6e0e 1483 spin_lock_irqsave(&info->port.lock, flags);
e60a1084 1484 if (info->port.count)
1da177e4
LT		 1485 atomic_dec(&rp_num_ports_open);
1486 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
417b6e0e 1487 spin_unlock_irqrestore(&info->port.lock, flags);
1da177e4 1488
fba85e01 1489 tty_port_hangup(&info->port);
1da177e4
LT		 1490
1491 cp = &info->channel;
1492 sDisRxFIFO(cp);
1493 sDisTransmit(cp);
1494 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1495 sDisCTSFlowCtl(cp);
1496 sDisTxSoftFlowCtl(cp);
1497 sClrTxXOFF(cp);
d41861ca 1498 tty_port_set_initialized(&info->port, 0);
1da177e4 1499
e60a1084 1500 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1501}
1502
1503/*
1504 * Exception handler - write char routine. The RocketPort driver uses a
1505 * double-buffering strategy, with the twist that if the in-memory CPU
1506 * buffer is empty, and there's space in the transmit FIFO, the
1507 * writing routines will write directly to transmit FIFO.
1508 * Write buffer and counters protected by spinlocks
1509 */
bbbbb96f 1510static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1511{
c9f19e96 1512 struct r_port *info = tty->driver_data;
1da177e4
LT		 1513 CHANNEL_t *cp;
1514 unsigned long flags;
1515
1516 if (rocket_paranoia_check(info, "rp_put_char"))
bbbbb96f 1517 return 0;
1da177e4 1518
69f545ea
MK		 1519 /*
1520 * Grab the port write mutex, locking out other processes that try to
1521 * write to this port
1522 */
1523 mutex_lock(&info->write_mtx);
1da177e4
LT		 1524
1525#ifdef ROCKET_DEBUG_WRITE
68562b79 1526 printk(KERN_INFO "rp_put_char %c...\n", ch);
1da177e4
LT		 1527#endif
1528
1529 spin_lock_irqsave(&info->slock, flags);
1530 cp = &info->channel;
1531
ee797069 1532 if (!tty->stopped && info->xmit_fifo_room == 0)
1da177e4
LT		 1533 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1534
ee797069 1535 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1da177e4
LT		 1536 info->xmit_buf[info->xmit_head++] = ch;
1537 info->xmit_head &= XMIT_BUF_SIZE - 1;
1538 info->xmit_cnt++;
1539 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1540 } else {
1541 sOutB(sGetTxRxDataIO(cp), ch);
1542 info->xmit_fifo_room--;
1543 }
1544 spin_unlock_irqrestore(&info->slock, flags);
69f545ea 1545 mutex_unlock(&info->write_mtx);
bbbbb96f 1546 return 1;
1da177e4
LT		 1547}
1548
1549/*
1550 * Exception handler - write routine, called when user app writes to the device.
69f545ea 1551 * A per port write mutex is used to protect from another process writing to
1da177e4
LT		 1552 * this port at the same time. This other process could be running on the other CPU
1553 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1554 * Spinlocks protect the info xmit members.
1555 */
1556static int rp_write(struct tty_struct *tty,
1557 const unsigned char *buf, int count)
1558{
c9f19e96 1559 struct r_port *info = tty->driver_data;
1da177e4
LT		 1560 CHANNEL_t *cp;
1561 const unsigned char *b;
1562 int c, retval = 0;
1563 unsigned long flags;
1564
1565 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1566 return 0;
1567
1e3e8d91
SS		 1568 if (mutex_lock_interruptible(&info->write_mtx))
1569 return -ERESTARTSYS;
1da177e4
LT		 1570
1571#ifdef ROCKET_DEBUG_WRITE
68562b79 1572 printk(KERN_INFO "rp_write %d chars...\n", count);
1da177e4
LT		 1573#endif
1574 cp = &info->channel;
1575
ee797069 1576 if (!tty->stopped && info->xmit_fifo_room < count)
1da177e4
LT		 1577 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1578
1579 /*
1580 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1581 * into FIFO. Use the write queue for temp storage.
1582 */
ee797069 1583 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1da177e4
LT		 1584 c = min(count, info->xmit_fifo_room);
1585 b = buf;
1586
1587 /* Push data into FIFO, 2 bytes at a time */
1588 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1589
1590 /* If there is a byte remaining, write it */
1591 if (c & 1)
1592 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1593
1594 retval += c;
1595 buf += c;
1596 count -= c;
1597
1598 spin_lock_irqsave(&info->slock, flags);
1599 info->xmit_fifo_room -= c;
1600 spin_unlock_irqrestore(&info->slock, flags);
1601 }
1602
1603 /* If count is zero, we wrote it all and are done */
1604 if (!count)
1605 goto end;
1606
1607 /* Write remaining data into the port's xmit_buf */
1608 while (1) {
47b01b3a 1609 /* Hung up ? */
807c8d81 1610 if (!tty_port_active(&info->port))
1da177e4 1611 goto end;
709107fc
HH		 1612 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1613 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1da177e4
LT		 1614 if (c <= 0)
1615 break;
1616
1617 b = buf;
1618 memcpy(info->xmit_buf + info->xmit_head, b, c);
1619
1620 spin_lock_irqsave(&info->slock, flags);
1621 info->xmit_head =
1622 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1623 info->xmit_cnt += c;
1624 spin_unlock_irqrestore(&info->slock, flags);
1625
1626 buf += c;
1627 count -= c;
1628 retval += c;
1629 }
1630
ee797069 1631 if ((retval > 0) && !tty->stopped)
1da177e4
LT		 1632 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1633
1634end:
1635 if (info->xmit_cnt < WAKEUP_CHARS) {
1636 tty_wakeup(tty);
1da177e4
LT		 1637#ifdef ROCKETPORT_HAVE_POLL_WAIT
1638 wake_up_interruptible(&tty->poll_wait);
1639#endif
1640 }
69f545ea 1641 mutex_unlock(&info->write_mtx);
1da177e4
LT		 1642 return retval;
1643}
1644
1645/*
1646 * Return the number of characters that can be sent. We estimate
1647 * only using the in-memory transmit buffer only, and ignore the
1648 * potential space in the transmit FIFO.
1649 */
1650static int rp_write_room(struct tty_struct *tty)
1651{
c9f19e96 1652 struct r_port *info = tty->driver_data;
1da177e4
LT		 1653 int ret;
1654
1655 if (rocket_paranoia_check(info, "rp_write_room"))
1656 return 0;
1657
1658 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1659 if (ret < 0)
1660 ret = 0;
1661#ifdef ROCKET_DEBUG_WRITE
68562b79 1662 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1da177e4
LT		 1663#endif
1664 return ret;
1665}
1666
1667/*
1668 * Return the number of characters in the buffer. Again, this only
1669 * counts those characters in the in-memory transmit buffer.
1670 */
1671static int rp_chars_in_buffer(struct tty_struct *tty)
1672{
c9f19e96 1673 struct r_port *info = tty->driver_data;
1da177e4
LT		 1674
1675 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1676 return 0;
1677
1da177e4 1678#ifdef ROCKET_DEBUG_WRITE
68562b79 1679 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1da177e4
LT		 1680#endif
1681 return info->xmit_cnt;
1682}
1683
1684/*
1685 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1686 * r_port struct for the port. Note that spinlock are used to protect info members,
1687 * do not call this function if the spinlock is already held.
1688 */
1689static void rp_flush_buffer(struct tty_struct *tty)
1690{
c9f19e96 1691 struct r_port *info = tty->driver_data;
1da177e4
LT		 1692 CHANNEL_t *cp;
1693 unsigned long flags;
1694
1695 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1696 return;
1697
1698 spin_lock_irqsave(&info->slock, flags);
1699 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1700 spin_unlock_irqrestore(&info->slock, flags);
1701
1da177e4
LT		 1702#ifdef ROCKETPORT_HAVE_POLL_WAIT
1703 wake_up_interruptible(&tty->poll_wait);
1704#endif
1705 tty_wakeup(tty);
1706
1707 cp = &info->channel;
1708 sFlushTxFIFO(cp);
1709}
1710
1711#ifdef CONFIG_PCI
1712
311df74a 1713static const struct pci_device_id rocket_pci_ids[] = {
b9d42395
KC		 1714 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1715 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1716 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1717 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1718 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1719 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1720 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1721 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1722 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1723 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1724 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1725 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1726 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1727 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1728 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1729 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1730 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1731 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1732 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1733 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1734 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1735 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
8d5916d3
JS		 1736 { }
1737};
1738MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1739
416187ca
JS		 1740/* Resets the speaker controller on RocketModem II and III devices */
1741static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1742{
1743 ByteIO_t addr;
1744
1745 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1746 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1747 addr = CtlP->AiopIO[0] + 0x4F;
1748 sOutB(addr, 0);
1749 }
1750
1751 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1752 if ((model == MODEL_UPCI_RM3_8PORT)
1753 || (model == MODEL_UPCI_RM3_4PORT)) {
1754 addr = CtlP->AiopIO[0] + 0x88;
1755 sOutB(addr, 0);
1756 }
1757}
1758
1759/***************************************************************************
1760Function: sPCIInitController
1761Purpose: Initialization of controller global registers and controller
1762 structure.
1763Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1764 IRQNum,Frequency,PeriodicOnly)
1765 CONTROLLER_T *CtlP; Ptr to controller structure
1766 int CtlNum; Controller number
1767 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1768 This list must be in the order the AIOPs will be found on the
1769 controller. Once an AIOP in the list is not found, it is
1770 assumed that there are no more AIOPs on the controller.
1771 int AiopIOListSize; Number of addresses in AiopIOList
1772 int IRQNum; Interrupt Request number. Can be any of the following:
1773 0: Disable global interrupts
1774 3: IRQ 3
1775 4: IRQ 4
1776 5: IRQ 5
1777 9: IRQ 9
1778 10: IRQ 10
1779 11: IRQ 11
1780 12: IRQ 12
1781 15: IRQ 15
1782 Byte_t Frequency: A flag identifying the frequency
1783 of the periodic interrupt, can be any one of the following:
1784 FREQ_DIS - periodic interrupt disabled
1785 FREQ_137HZ - 137 Hertz
1786 FREQ_69HZ - 69 Hertz
1787 FREQ_34HZ - 34 Hertz
1788 FREQ_17HZ - 17 Hertz
1789 FREQ_9HZ - 9 Hertz
1790 FREQ_4HZ - 4 Hertz
1791 If IRQNum is set to 0 the Frequency parameter is
1792 overidden, it is forced to a value of FREQ_DIS.
1793 int PeriodicOnly: 1 if all interrupts except the periodic
1794 interrupt are to be blocked.
1795 0 is both the periodic interrupt and
1796 other channel interrupts are allowed.
1797 If IRQNum is set to 0 the PeriodicOnly parameter is
1798 overidden, it is forced to a value of 0.
1799Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
1800 initialization failed.
1801
1802Comments:
1803 If periodic interrupts are to be disabled but AIOP interrupts
1804 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1805
1806 If interrupts are to be completely disabled set IRQNum to 0.
1807
1808 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1809 invalid combination.
1810
1811 This function performs initialization of global interrupt modes,
1812 but it does not actually enable global interrupts. To enable
1813 and disable global interrupts use functions sEnGlobalInt() and
1814 sDisGlobalInt(). Enabling of global interrupts is normally not
1815 done until all other initializations are complete.
1816
1817 Even if interrupts are globally enabled, they must also be
1818 individually enabled for each channel that is to generate
1819 interrupts.
1820
1821Warnings: No range checking on any of the parameters is done.
1822
1823 No context switches are allowed while executing this function.
1824
1825 After this function all AIOPs on the controller are disabled,
1826 they can be enabled with sEnAiop().
1827*/
1828static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1829 ByteIO_t * AiopIOList, int AiopIOListSize,
1830 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1831 int PeriodicOnly, int altChanRingIndicator,
1832 int UPCIRingInd)
1833{
1834 int i;
1835 ByteIO_t io;
1836
1837 CtlP->AltChanRingIndicator = altChanRingIndicator;
1838 CtlP->UPCIRingInd = UPCIRingInd;
1839 CtlP->CtlNum = CtlNum;
1840 CtlP->CtlID = CTLID_0001; /* controller release 1 */
1841 CtlP->BusType = isPCI; /* controller release 1 */
1842
1843 if (ConfigIO) {
1844 CtlP->isUPCI = 1;
1845 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1846 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1847 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1848 } else {
1849 CtlP->isUPCI = 0;
1850 CtlP->PCIIO =
1851 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1852 CtlP->AiopIntrBits = aiop_intr_bits;
1853 }
1854
1855 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
1856 /* Init AIOPs */
1857 CtlP->NumAiop = 0;
1858 for (i = 0; i < AiopIOListSize; i++) {
1859 io = AiopIOList[i];
1860 CtlP->AiopIO[i] = (WordIO_t) io;
1861 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1862
1863 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
1864 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
1865 break; /* done looking for AIOPs */
1866
1867 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1868 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
1869 sOutB(io + _INDX_DATA, sClockPrescale);
1870 CtlP->NumAiop++; /* bump count of AIOPs */
1871 }
1872
1873 if (CtlP->NumAiop == 0)
1874 return (-1);
1875 else
1876 return (CtlP->NumAiop);
1877}
1878
1da177e4
LT		 1879/*
1880 * Called when a PCI card is found. Retrieves and stores model information,
1881 * init's aiopic and serial port hardware.
1882 * Inputs: i is the board number (0-n)
1883 */
f15313bf 1884static __init int register_PCI(int i, struct pci_dev *dev)
1da177e4
LT		 1885{
1886 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1887 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1da177e4
LT		 1888 CONTROLLER_t *ctlp;
1889
1890 int fast_clock = 0;
1891 int altChanRingIndicator = 0;
1892 int ports_per_aiop = 8;
1da177e4
LT		 1893 WordIO_t ConfigIO = 0;
1894 ByteIO_t UPCIRingInd = 0;
1895
b9d42395
KC		 1896 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1897 pci_enable_device(dev))
1da177e4
LT		 1898 return 0;
1899
1900 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1da177e4
LT		 1901
1902 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1903 rocketModel[i].loadrm2 = 0;
1904 rocketModel[i].startingPortNumber = nextLineNumber;
1905
1906 /* Depending on the model, set up some config variables */
1907 switch (dev->device) {
1908 case PCI_DEVICE_ID_RP4QUAD:
1da177e4
LT		 1909 max_num_aiops = 1;
1910 ports_per_aiop = 4;
1911 rocketModel[i].model = MODEL_RP4QUAD;
1912 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1913 rocketModel[i].numPorts = 4;
1914 break;
1915 case PCI_DEVICE_ID_RP8OCTA:
1da177e4
LT		 1916 max_num_aiops = 1;
1917 rocketModel[i].model = MODEL_RP8OCTA;
1918 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1919 rocketModel[i].numPorts = 8;
1920 break;
1921 case PCI_DEVICE_ID_URP8OCTA:
1da177e4
LT		 1922 max_num_aiops = 1;
1923 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1924 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1925 rocketModel[i].numPorts = 8;
1926 break;
1927 case PCI_DEVICE_ID_RP8INTF:
1da177e4
LT		 1928 max_num_aiops = 1;
1929 rocketModel[i].model = MODEL_RP8INTF;
1930 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1931 rocketModel[i].numPorts = 8;
1932 break;
1933 case PCI_DEVICE_ID_URP8INTF:
1da177e4
LT		 1934 max_num_aiops = 1;
1935 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1936 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1937 rocketModel[i].numPorts = 8;
1938 break;
1939 case PCI_DEVICE_ID_RP8J:
1da177e4
LT		 1940 max_num_aiops = 1;
1941 rocketModel[i].model = MODEL_RP8J;
1942 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1943 rocketModel[i].numPorts = 8;
1944 break;
1945 case PCI_DEVICE_ID_RP4J:
1da177e4
LT		 1946 max_num_aiops = 1;
1947 ports_per_aiop = 4;
1948 rocketModel[i].model = MODEL_RP4J;
1949 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1950 rocketModel[i].numPorts = 4;
1951 break;
1952 case PCI_DEVICE_ID_RP8SNI:
1da177e4
LT		 1953 max_num_aiops = 1;
1954 rocketModel[i].model = MODEL_RP8SNI;
1955 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1956 rocketModel[i].numPorts = 8;
1957 break;
1958 case PCI_DEVICE_ID_RP16SNI:
1da177e4
LT		 1959 max_num_aiops = 2;
1960 rocketModel[i].model = MODEL_RP16SNI;
1961 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1962 rocketModel[i].numPorts = 16;
1963 break;
1964 case PCI_DEVICE_ID_RP16INTF:
1da177e4
LT		 1965 max_num_aiops = 2;
1966 rocketModel[i].model = MODEL_RP16INTF;
1967 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1968 rocketModel[i].numPorts = 16;
1969 break;
1970 case PCI_DEVICE_ID_URP16INTF:
1da177e4
LT		 1971 max_num_aiops = 2;
1972 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1973 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1974 rocketModel[i].numPorts = 16;
1975 break;
1976 case PCI_DEVICE_ID_CRP16INTF:
1da177e4
LT		 1977 max_num_aiops = 2;
1978 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1979 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1980 rocketModel[i].numPorts = 16;
1981 break;
1982 case PCI_DEVICE_ID_RP32INTF:
1da177e4
LT		 1983 max_num_aiops = 4;
1984 rocketModel[i].model = MODEL_RP32INTF;
1985 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1986 rocketModel[i].numPorts = 32;
1987 break;
1988 case PCI_DEVICE_ID_URP32INTF:
1da177e4
LT		 1989 max_num_aiops = 4;
1990 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1991 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1992 rocketModel[i].numPorts = 32;
1993 break;
1994 case PCI_DEVICE_ID_RPP4:
1da177e4
LT		 1995 max_num_aiops = 1;
1996 ports_per_aiop = 4;
1997 altChanRingIndicator++;
1998 fast_clock++;
1999 rocketModel[i].model = MODEL_RPP4;
2000 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2001 rocketModel[i].numPorts = 4;
2002 break;
2003 case PCI_DEVICE_ID_RPP8:
1da177e4
LT		 2004 max_num_aiops = 2;
2005 ports_per_aiop = 4;
2006 altChanRingIndicator++;
2007 fast_clock++;
2008 rocketModel[i].model = MODEL_RPP8;
2009 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2010 rocketModel[i].numPorts = 8;
2011 break;
2012 case PCI_DEVICE_ID_RP2_232:
1da177e4
LT		 2013 max_num_aiops = 1;
2014 ports_per_aiop = 2;
2015 altChanRingIndicator++;
2016 fast_clock++;
2017 rocketModel[i].model = MODEL_RP2_232;
2018 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2019 rocketModel[i].numPorts = 2;
2020 break;
2021 case PCI_DEVICE_ID_RP2_422:
1da177e4
LT		 2022 max_num_aiops = 1;
2023 ports_per_aiop = 2;
2024 altChanRingIndicator++;
2025 fast_clock++;
2026 rocketModel[i].model = MODEL_RP2_422;
2027 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2028 rocketModel[i].numPorts = 2;
2029 break;
2030 case PCI_DEVICE_ID_RP6M:
2031
2032 max_num_aiops = 1;
2033 ports_per_aiop = 6;
1da177e4 2034
57fedc7a
JS		 2035 /* If revision is 1, the rocketmodem flash must be loaded.
2036 * If it is 2 it is a "socketed" version. */
2037 if (dev->revision == 1) {
1da177e4
LT		 2038 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2039 rocketModel[i].loadrm2 = 1;
2040 } else {
2041 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2042 }
2043
2044 rocketModel[i].model = MODEL_RP6M;
2045 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2046 rocketModel[i].numPorts = 6;
2047 break;
2048 case PCI_DEVICE_ID_RP4M:
2049 max_num_aiops = 1;
2050 ports_per_aiop = 4;
57fedc7a 2051 if (dev->revision == 1) {
1da177e4
LT		 2052 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2053 rocketModel[i].loadrm2 = 1;
2054 } else {
2055 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2056 }
2057
2058 rocketModel[i].model = MODEL_RP4M;
2059 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2060 rocketModel[i].numPorts = 4;
2061 break;
2062 default:
1da177e4
LT		 2063 max_num_aiops = 0;
2064 break;
2065 }
2066
2067 /*
2068 * Check for UPCI boards.
2069 */
2070
2071 switch (dev->device) {
2072 case PCI_DEVICE_ID_URP32INTF:
2073 case PCI_DEVICE_ID_URP8INTF:
2074 case PCI_DEVICE_ID_URP16INTF:
2075 case PCI_DEVICE_ID_CRP16INTF:
2076 case PCI_DEVICE_ID_URP8OCTA:
2077 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2078 ConfigIO = pci_resource_start(dev, 1);
2079 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2080 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2081
2082 /*
2083 * Check for octa or quad cable.
2084 */
2085 if (!
2086 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2087 PCI_GPIO_CTRL_8PORT)) {
1da177e4
LT		 2088 ports_per_aiop = 4;
2089 rocketModel[i].numPorts = 4;
2090 }
2091 }
2092 break;
2093 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
1da177e4
LT		 2094 max_num_aiops = 1;
2095 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2096 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2097 rocketModel[i].numPorts = 8;
2098 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2099 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2100 ConfigIO = pci_resource_start(dev, 1);
2101 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2102 break;
2103 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
1da177e4
LT		 2104 max_num_aiops = 1;
2105 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2106 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2107 rocketModel[i].numPorts = 4;
2108 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2109 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2110 ConfigIO = pci_resource_start(dev, 1);
2111 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2112 break;
2113 default:
2114 break;
2115 }
2116
1da177e4
LT		 2117 if (fast_clock) {
2118 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2119 rp_baud_base[i] = 921600;
2120 } else {
2121 /*
2122 * If support_low_speed is set, use the slow clock
2123 * prescale, which supports 50 bps
2124 */
2125 if (support_low_speed) {
2126 /* mod 9 (divide by 10) prescale */
2127 sClockPrescale = 0x19;
2128 rp_baud_base[i] = 230400;
2129 } else {
25985edc 2130 /* mod 4 (divide by 5) prescale */
1da177e4
LT		 2131 sClockPrescale = 0x14;
2132 rp_baud_base[i] = 460800;
2133 }
2134 }
2135
2136 for (aiop = 0; aiop < max_num_aiops; aiop++)
2137 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2138 ctlp = sCtlNumToCtlPtr(i);
2139 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2140 for (aiop = 0; aiop < max_num_aiops; aiop++)
2141 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2142
68562b79
JS		 2143 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2144 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2145 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2146 rocketModel[i].startingPortNumber,
2147 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
1da177e4
LT		 2148
2149 if (num_aiops <= 0) {
2150 rcktpt_io_addr[i] = 0;
2151 return (0);
2152 }
2153 is_PCI[i] = 1;
2154
2155 /* Reset the AIOPIC, init the serial ports */
2156 for (aiop = 0; aiop < num_aiops; aiop++) {
2157 sResetAiopByNum(ctlp, aiop);
2158 num_chan = ports_per_aiop;
2159 for (chan = 0; chan < num_chan; chan++)
2160 init_r_port(i, aiop, chan, dev);
2161 }
2162
2163 /* Rocket modems must be reset */
2164 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2165 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2166 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2167 num_chan = ports_per_aiop;
2168 for (chan = 0; chan < num_chan; chan++)
2169 sPCIModemReset(ctlp, chan, 1);
48a67f5d 2170 msleep(500);
1da177e4
LT		 2171 for (chan = 0; chan < num_chan; chan++)
2172 sPCIModemReset(ctlp, chan, 0);
48a67f5d 2173 msleep(500);
1da177e4
LT		 2174 rmSpeakerReset(ctlp, rocketModel[i].model);
2175 }
2176 return (1);
2177}
2178
2179/*
2180 * Probes for PCI cards, inits them if found
2181 * Input: board_found = number of ISA boards already found, or the
2182 * starting board number
2183 * Returns: Number of PCI boards found
2184 */
2185static int __init init_PCI(int boards_found)
2186{
2187 struct pci_dev *dev = NULL;
2188 int count = 0;
2189
2190 /* Work through the PCI device list, pulling out ours */
606d099c 2191 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
1da177e4
LT		 2192 if (register_PCI(count + boards_found, dev))
2193 count++;
2194 }
2195 return (count);
2196}
2197
2198#endif /* CONFIG_PCI */
2199
2200/*
2201 * Probes for ISA cards
2202 * Input: i = the board number to look for
2203 * Returns: 1 if board found, 0 else
2204 */
2205static int __init init_ISA(int i)
2206{
2207 int num_aiops, num_chan = 0, total_num_chan = 0;
2208 int aiop, chan;
2209 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2210 CONTROLLER_t *ctlp;
2211 char *type_string;
2212
2213 /* If io_addr is zero, no board configured */
2214 if (rcktpt_io_addr[i] == 0)
2215 return (0);
2216
2217 /* Reserve the IO region */
2218 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
68562b79
JS		 2219 printk(KERN_ERR "Unable to reserve IO region for configured "
2220 "ISA RocketPort at address 0x%lx, board not "
2221 "installed...\n", rcktpt_io_addr[i]);
1da177e4
LT		 2222 rcktpt_io_addr[i] = 0;
2223 return (0);
2224 }
2225
2226 ctlp = sCtlNumToCtlPtr(i);
2227
2228 ctlp->boardType = rcktpt_type[i];
2229
2230 switch (rcktpt_type[i]) {
2231 case ROCKET_TYPE_PC104:
2232 type_string = "(PC104)";
2233 break;
2234 case ROCKET_TYPE_MODEM:
2235 type_string = "(RocketModem)";
2236 break;
2237 case ROCKET_TYPE_MODEMII:
2238 type_string = "(RocketModem II)";
2239 break;
2240 default:
2241 type_string = "";
2242 break;
2243 }
2244
2245 /*
2246 * If support_low_speed is set, use the slow clock prescale,
2247 * which supports 50 bps
2248 */
2249 if (support_low_speed) {
2250 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2251 rp_baud_base[i] = 230400;
2252 } else {
25985edc 2253 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
1da177e4
LT		 2254 rp_baud_base[i] = 460800;
2255 }
2256
2257 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2258 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2259
2260 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2261
2262 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2263 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2264 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2265 }
2266
2267 /* If something went wrong initing the AIOP's release the ISA IO memory */
2268 if (num_aiops <= 0) {
2269 release_region(rcktpt_io_addr[i], 64);
2270 rcktpt_io_addr[i] = 0;
2271 return (0);
2272 }
2273
2274 rocketModel[i].startingPortNumber = nextLineNumber;
2275
2276 for (aiop = 0; aiop < num_aiops; aiop++) {
2277 sResetAiopByNum(ctlp, aiop);
2278 sEnAiop(ctlp, aiop);
2279 num_chan = sGetAiopNumChan(ctlp, aiop);
2280 total_num_chan += num_chan;
2281 for (chan = 0; chan < num_chan; chan++)
2282 init_r_port(i, aiop, chan, NULL);
2283 }
2284 is_PCI[i] = 0;
2285 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2286 num_chan = sGetAiopNumChan(ctlp, 0);
2287 total_num_chan = num_chan;
2288 for (chan = 0; chan < num_chan; chan++)
2289 sModemReset(ctlp, chan, 1);
48a67f5d 2290 msleep(500);
1da177e4
LT		 2291 for (chan = 0; chan < num_chan; chan++)
2292 sModemReset(ctlp, chan, 0);
48a67f5d 2293 msleep(500);
1da177e4
LT		 2294 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2295 } else {
2296 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2297 }
2298 rocketModel[i].numPorts = total_num_chan;
2299 rocketModel[i].model = MODEL_ISA;
2300
2301 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2302 i, rcktpt_io_addr[i], num_aiops, type_string);
2303
2304 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2305 rocketModel[i].modelString,
2306 rocketModel[i].startingPortNumber,
2307 rocketModel[i].startingPortNumber +
2308 rocketModel[i].numPorts - 1);
2309
2310 return (1);
2311}
2312
b68e31d0 2313static const struct tty_operations rocket_ops = {
1da177e4
LT		 2314 .open = rp_open,
2315 .close = rp_close,
2316 .write = rp_write,
2317 .put_char = rp_put_char,
2318 .write_room = rp_write_room,
2319 .chars_in_buffer = rp_chars_in_buffer,
2320 .flush_buffer = rp_flush_buffer,
2321 .ioctl = rp_ioctl,
2322 .throttle = rp_throttle,
2323 .unthrottle = rp_unthrottle,
2324 .set_termios = rp_set_termios,
2325 .stop = rp_stop,
2326 .start = rp_start,
2327 .hangup = rp_hangup,
2328 .break_ctl = rp_break,
2329 .send_xchar = rp_send_xchar,
2330 .wait_until_sent = rp_wait_until_sent,
2331 .tiocmget = rp_tiocmget,
2332 .tiocmset = rp_tiocmset,
2333};
2334
31f35939
AC		 2335static const struct tty_port_operations rocket_port_ops = {
2336 .carrier_raised = carrier_raised,
fcc8ac18 2337 .dtr_rts = dtr_rts,
31f35939
AC		 2338};
2339
1da177e4
LT		 2340/*
2341 * The module "startup" routine; it's run when the module is loaded.
2342 */
d269cdd0 2343static int __init rp_init(void)
1da177e4 2344{
4384a3fa 2345 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
1da177e4
LT		 2346
2347 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2348 ROCKET_VERSION, ROCKET_DATE);
2349
2350 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2351 if (!rocket_driver)
4384a3fa 2352 goto err;
1da177e4 2353
1da177e4
LT		 2354 /*
2355 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2356 * zero, use the default controller IO address of board1 + 0x40.
2357 */
2358 if (board1) {
2359 if (controller == 0)
2360 controller = board1 + 0x40;
2361 } else {
2362 controller = 0; /* Used as a flag, meaning no ISA boards */
2363 }
2364
2365 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2366 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
4384a3fa
JS		 2367 printk(KERN_ERR "Unable to reserve IO region for first "
2368 "configured ISA RocketPort controller 0x%lx. "
2369 "Driver exiting\n", controller);
2370 ret = -EBUSY;
2371 goto err_tty;
1da177e4
LT		 2372 }
2373
2374 /* Store ISA variable retrieved from command line or .conf file. */
2375 rcktpt_io_addr[0] = board1;
2376 rcktpt_io_addr[1] = board2;
2377 rcktpt_io_addr[2] = board3;
2378 rcktpt_io_addr[3] = board4;
2379
2380 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2381 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2382 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2383 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2384 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2385 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2386 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2387 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2388
2389 /*
2390 * Set up the tty driver structure and then register this
2391 * driver with the tty layer.
2392 */
2393
331b8319 2394 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 2395 rocket_driver->name = "ttyR";
2396 rocket_driver->driver_name = "Comtrol RocketPort";
2397 rocket_driver->major = TTY_ROCKET_MAJOR;
2398 rocket_driver->minor_start = 0;
2399 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2400 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2401 rocket_driver->init_termios = tty_std_termios;
2402 rocket_driver->init_termios.c_cflag =
2403 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 2404 rocket_driver->init_termios.c_ispeed = 9600;
2405 rocket_driver->init_termios.c_ospeed = 9600;
1da177e4 2406#ifdef ROCKET_SOFT_FLOW
ac6aec2f 2407 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
1da177e4
LT		 2408#endif
2409 tty_set_operations(rocket_driver, &rocket_ops);
2410
4384a3fa
JS		 2411 ret = tty_register_driver(rocket_driver);
2412 if (ret < 0) {
2413 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
713efa9a 2414 goto err_controller;
1da177e4
LT		 2415 }
2416
2417#ifdef ROCKET_DEBUG_OPEN
2418 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2419#endif
2420
2421 /*
2422 * OK, let's probe each of the controllers looking for boards. Any boards found
2423 * will be initialized here.
2424 */
2425 isa_boards_found = 0;
2426 pci_boards_found = 0;
2427
2428 for (i = 0; i < NUM_BOARDS; i++) {
2429 if (init_ISA(i))
2430 isa_boards_found++;
2431 }
2432
2433#ifdef CONFIG_PCI
2434 if (isa_boards_found < NUM_BOARDS)
2435 pci_boards_found = init_PCI(isa_boards_found);
2436#endif
2437
2438 max_board = pci_boards_found + isa_boards_found;
2439
2440 if (max_board == 0) {
4384a3fa
JS		 2441 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2442 ret = -ENXIO;
2443 goto err_ttyu;
1da177e4
LT		 2444 }
2445
2446 return 0;
4384a3fa
JS		 2447err_ttyu:
2448 tty_unregister_driver(rocket_driver);
713efa9a
DC		 2449err_controller:
2450 if (controller)
2451 release_region(controller, 4);
4384a3fa
JS		 2452err_tty:
2453 put_tty_driver(rocket_driver);
2454err:
2455 return ret;
1da177e4
LT		 2456}
2457
1da177e4
LT		 2458
2459static void rp_cleanup_module(void)
2460{
2461 int retval;
2462 int i;
2463
2464 del_timer_sync(&rocket_timer);
2465
2466 retval = tty_unregister_driver(rocket_driver);
2467 if (retval)
68562b79 2468 printk(KERN_ERR "Error %d while trying to unregister "
1da177e4 2469 "rocketport driver\n", -retval);
1da177e4 2470
735d5661 2471 for (i = 0; i < MAX_RP_PORTS; i++)
ac6aec2f
JS		 2472 if (rp_table[i]) {
2473 tty_unregister_device(rocket_driver, i);
191c5f10 2474 tty_port_destroy(&rp_table[i]->port);
ac6aec2f
JS		 2475 kfree(rp_table[i]);
2476 }
2477
2478 put_tty_driver(rocket_driver);
1da177e4
LT		 2479
2480 for (i = 0; i < NUM_BOARDS; i++) {
2481 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2482 continue;
2483 release_region(rcktpt_io_addr[i], 64);
2484 }
2485 if (controller)
2486 release_region(controller, 4);
2487}
1da177e4 2488
1da177e4
LT		 2489/***************************************************************************
2490Function: sInitController
2491Purpose: Initialization of controller global registers and controller
2492 structure.
2493Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2494 IRQNum,Frequency,PeriodicOnly)
2495 CONTROLLER_T *CtlP; Ptr to controller structure
2496 int CtlNum; Controller number
2497 ByteIO_t MudbacIO; Mudbac base I/O address.
2498 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2499 This list must be in the order the AIOPs will be found on the
2500 controller. Once an AIOP in the list is not found, it is
2501 assumed that there are no more AIOPs on the controller.
2502 int AiopIOListSize; Number of addresses in AiopIOList
2503 int IRQNum; Interrupt Request number. Can be any of the following:
2504 0: Disable global interrupts
2505 3: IRQ 3
2506 4: IRQ 4
2507 5: IRQ 5
2508 9: IRQ 9
2509 10: IRQ 10
2510 11: IRQ 11
2511 12: IRQ 12
2512 15: IRQ 15
2513 Byte_t Frequency: A flag identifying the frequency
2514 of the periodic interrupt, can be any one of the following:
2515 FREQ_DIS - periodic interrupt disabled
2516 FREQ_137HZ - 137 Hertz
2517 FREQ_69HZ - 69 Hertz
2518 FREQ_34HZ - 34 Hertz
2519 FREQ_17HZ - 17 Hertz
2520 FREQ_9HZ - 9 Hertz
2521 FREQ_4HZ - 4 Hertz
2522 If IRQNum is set to 0 the Frequency parameter is
2523 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2524 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2525 interrupt are to be blocked.
f15313bf 2526 0 is both the periodic interrupt and
1da177e4
LT		 2527 other channel interrupts are allowed.
2528 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2529 overidden, it is forced to a value of 0.
1da177e4
LT		 2530Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2531 initialization failed.
2532
2533Comments:
2534 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2535 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2536
2537 If interrupts are to be completely disabled set IRQNum to 0.
2538
f15313bf 2539 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2540 invalid combination.
2541
2542 This function performs initialization of global interrupt modes,
2543 but it does not actually enable global interrupts. To enable
2544 and disable global interrupts use functions sEnGlobalInt() and
2545 sDisGlobalInt(). Enabling of global interrupts is normally not
2546 done until all other initializations are complete.
2547
2548 Even if interrupts are globally enabled, they must also be
2549 individually enabled for each channel that is to generate
2550 interrupts.
2551
2552Warnings: No range checking on any of the parameters is done.
2553
2554 No context switches are allowed while executing this function.
2555
2556 After this function all AIOPs on the controller are disabled,
2557 they can be enabled with sEnAiop().
2558*/
f15313bf
AB		 2559static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2560 ByteIO_t * AiopIOList, int AiopIOListSize,
2561 int IRQNum, Byte_t Frequency, int PeriodicOnly)
1da177e4
LT		 2562{
2563 int i;
2564 ByteIO_t io;
2565 int done;
2566
2567 CtlP->AiopIntrBits = aiop_intr_bits;
2568 CtlP->AltChanRingIndicator = 0;
2569 CtlP->CtlNum = CtlNum;
2570 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2571 CtlP->BusType = isISA;
2572 CtlP->MBaseIO = MudbacIO;
2573 CtlP->MReg1IO = MudbacIO + 1;
2574 CtlP->MReg2IO = MudbacIO + 2;
2575 CtlP->MReg3IO = MudbacIO + 3;
2576#if 1
2577 CtlP->MReg2 = 0; /* interrupt disable */
2578 CtlP->MReg3 = 0; /* no periodic interrupts */
2579#else
2580 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2581 CtlP->MReg2 = 0; /* interrupt disable */
2582 CtlP->MReg3 = 0; /* no periodic interrupts */
2583 } else {
2584 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2585 CtlP->MReg3 = Frequency; /* set frequency */
2586 if (PeriodicOnly) { /* periodic interrupt only */
2587 CtlP->MReg3 |= PERIODIC_ONLY;
2588 }
2589 }
2590#endif
2591 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2592 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2593 sControllerEOI(CtlP); /* clear EOI if warm init */
2594 /* Init AIOPs */
2595 CtlP->NumAiop = 0;
2596 for (i = done = 0; i < AiopIOListSize; i++) {
2597 io = AiopIOList[i];
2598 CtlP->AiopIO[i] = (WordIO_t) io;
2599 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2600 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2601 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2602 if (done)
2603 continue;
2604 sEnAiop(CtlP, i); /* enable the AIOP */
2605 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2606 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2607 done = 1; /* done looking for AIOPs */
2608 else {
2609 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2610 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2611 sOutB(io + _INDX_DATA, sClockPrescale);
2612 CtlP->NumAiop++; /* bump count of AIOPs */
2613 }
2614 sDisAiop(CtlP, i); /* disable AIOP */
2615 }
2616
2617 if (CtlP->NumAiop == 0)
2618 return (-1);
2619 else
2620 return (CtlP->NumAiop);
2621}
2622
1da177e4
LT		 2623/***************************************************************************
2624Function: sReadAiopID
2625Purpose: Read the AIOP idenfication number directly from an AIOP.
2626Call: sReadAiopID(io)
2627 ByteIO_t io: AIOP base I/O address
2628Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2629 is replace by an identifying number.
2630 Flag AIOPID_NULL if no valid AIOP is found
2631Warnings: No context switches are allowed while executing this function.
2632
2633*/
f15313bf 2634static int sReadAiopID(ByteIO_t io)
1da177e4
LT		 2635{
2636 Byte_t AiopID; /* ID byte from AIOP */
2637
2638 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2639 sOutB(io + _CMD_REG, 0x0);
2640 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2641 if (AiopID == 0x06)
2642 return (1);
2643 else /* AIOP does not exist */
2644 return (-1);
2645}
2646
2647/***************************************************************************
2648Function: sReadAiopNumChan
2649Purpose: Read the number of channels available in an AIOP directly from
2650 an AIOP.
2651Call: sReadAiopNumChan(io)
2652 WordIO_t io: AIOP base I/O address
2653Return: int: The number of channels available
2654Comments: The number of channels is determined by write/reads from identical
2655 offsets within the SRAM address spaces for channels 0 and 4.
2656 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2657 AIOP, otherwise it is an 8 channel.
2658Warnings: No context switches are allowed while executing this function.
2659*/
f15313bf 2660static int sReadAiopNumChan(WordIO_t io)
1da177e4
LT		 2661{
2662 Word_t x;
2663 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2664
2665 /* write to chan 0 SRAM */
457fb605 2666 out32((DWordIO_t) io + _INDX_ADDR, R);
1da177e4
LT		 2667 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2668 x = sInW(io + _INDX_DATA);
2669 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2670 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2671 return (8);
2672 else
2673 return (4);
2674}
2675
2676/***************************************************************************
2677Function: sInitChan
2678Purpose: Initialization of a channel and channel structure
2679Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2680 CONTROLLER_T *CtlP; Ptr to controller structure
2681 CHANNEL_T *ChP; Ptr to channel structure
2682 int AiopNum; AIOP number within controller
2683 int ChanNum; Channel number within AIOP
f15313bf 2684Return: int: 1 if initialization succeeded, 0 if it fails because channel
1da177e4
LT		 2685 number exceeds number of channels available in AIOP.
2686Comments: This function must be called before a channel can be used.
2687Warnings: No range checking on any of the parameters is done.
2688
2689 No context switches are allowed while executing this function.
2690*/
f15313bf
AB		 2691static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2692 int ChanNum)
1da177e4
LT		 2693{
2694 int i;
2695 WordIO_t AiopIO;
2696 WordIO_t ChIOOff;
2697 Byte_t *ChR;
2698 Word_t ChOff;
2699 static Byte_t R[4];
2700 int brd9600;
2701
2702 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
f15313bf 2703 return 0; /* exceeds num chans in AIOP */
1da177e4
LT		 2704
2705 /* Channel, AIOP, and controller identifiers */
2706 ChP->CtlP = CtlP;
2707 ChP->ChanID = CtlP->AiopID[AiopNum];
2708 ChP->AiopNum = AiopNum;
2709 ChP->ChanNum = ChanNum;
2710
2711 /* Global direct addresses */
2712 AiopIO = CtlP->AiopIO[AiopNum];
2713 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2714 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2715 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2716 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2717 ChP->IndexData = AiopIO + _INDX_DATA;
2718
2719 /* Channel direct addresses */
2720 ChIOOff = AiopIO + ChP->ChanNum * 2;
2721 ChP->TxRxData = ChIOOff + _TD0;
2722 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2723 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2724 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2725
2726 /* Initialize the channel from the RData array */
2727 for (i = 0; i < RDATASIZE; i += 4) {
2728 R[0] = RData[i];
2729 R[1] = RData[i + 1] + 0x10 * ChanNum;
2730 R[2] = RData[i + 2];
2731 R[3] = RData[i + 3];
457fb605 2732 out32(ChP->IndexAddr, R);
1da177e4
LT		 2733 }
2734
2735 ChR = ChP->R;
2736 for (i = 0; i < RREGDATASIZE; i += 4) {
2737 ChR[i] = RRegData[i];
2738 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2739 ChR[i + 2] = RRegData[i + 2];
2740 ChR[i + 3] = RRegData[i + 3];
2741 }
2742
2743 /* Indexed registers */
2744 ChOff = (Word_t) ChanNum *0x1000;
2745
2746 if (sClockPrescale == 0x14)
2747 brd9600 = 47;
2748 else
2749 brd9600 = 23;
2750
2751 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2752 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2753 ChP->BaudDiv[2] = (Byte_t) brd9600;
2754 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
457fb605 2755 out32(ChP->IndexAddr, ChP->BaudDiv);
1da177e4
LT		 2756
2757 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2758 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2759 ChP->TxControl[2] = 0;
2760 ChP->TxControl[3] = 0;
457fb605 2761 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 2762
2763 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2764 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2765 ChP->RxControl[2] = 0;
2766 ChP->RxControl[3] = 0;
457fb605 2767 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 2768
2769 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2770 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2771 ChP->TxEnables[2] = 0;
2772 ChP->TxEnables[3] = 0;
457fb605 2773 out32(ChP->IndexAddr, ChP->TxEnables);
1da177e4
LT		 2774
2775 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2776 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2777 ChP->TxCompare[2] = 0;
2778 ChP->TxCompare[3] = 0;
457fb605 2779 out32(ChP->IndexAddr, ChP->TxCompare);
1da177e4
LT		 2780
2781 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2782 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2783 ChP->TxReplace1[2] = 0;
2784 ChP->TxReplace1[3] = 0;
457fb605 2785 out32(ChP->IndexAddr, ChP->TxReplace1);
1da177e4
LT		 2786
2787 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2788 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2789 ChP->TxReplace2[2] = 0;
2790 ChP->TxReplace2[3] = 0;
457fb605 2791 out32(ChP->IndexAddr, ChP->TxReplace2);
1da177e4
LT		 2792
2793 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2794 ChP->TxFIFO = ChOff + _TX_FIFO;
2795
2796 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2797 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2798 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2799 sOutW(ChP->IndexData, 0);
2800 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2801 ChP->RxFIFO = ChOff + _RX_FIFO;
2802
2803 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2804 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2805 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2806 sOutW(ChP->IndexData, 0);
2807 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2808 sOutW(ChP->IndexData, 0);
2809 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2810 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2811 sOutB(ChP->IndexData, 0);
2812 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2813 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2814 sOutB(ChP->IndexData, 0);
2815 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2816 sEnRxProcessor(ChP); /* start the Rx processor */
2817
f15313bf 2818 return 1;
1da177e4
LT		 2819}
2820
2821/***************************************************************************
2822Function: sStopRxProcessor
2823Purpose: Stop the receive processor from processing a channel.
2824Call: sStopRxProcessor(ChP)
2825 CHANNEL_T *ChP; Ptr to channel structure
2826
2827Comments: The receive processor can be started again with sStartRxProcessor().
2828 This function causes the receive processor to skip over the
2829 stopped channel. It does not stop it from processing other channels.
2830
2831Warnings: No context switches are allowed while executing this function.
2832
2833 Do not leave the receive processor stopped for more than one
2834 character time.
2835
2836 After calling this function a delay of 4 uS is required to ensure
2837 that the receive processor is no longer processing this channel.
2838*/
f15313bf 2839static void sStopRxProcessor(CHANNEL_T * ChP)
1da177e4
LT		 2840{
2841 Byte_t R[4];
2842
2843 R[0] = ChP->R[0];
2844 R[1] = ChP->R[1];
2845 R[2] = 0x0a;
2846 R[3] = ChP->R[3];
457fb605 2847 out32(ChP->IndexAddr, R);
1da177e4
LT		 2848}
2849
2850/***************************************************************************
2851Function: sFlushRxFIFO
2852Purpose: Flush the Rx FIFO
2853Call: sFlushRxFIFO(ChP)
2854 CHANNEL_T *ChP; Ptr to channel structure
2855Return: void
2856Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2857 while it is being flushed the receive processor is stopped
2858 and the transmitter is disabled. After these operations a
2859 4 uS delay is done before clearing the pointers to allow
2860 the receive processor to stop. These items are handled inside
2861 this function.
2862Warnings: No context switches are allowed while executing this function.
2863*/
f15313bf 2864static void sFlushRxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2865{
2866 int i;
2867 Byte_t Ch; /* channel number within AIOP */
f15313bf 2868 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
1da177e4
LT		 2869
2870 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2871 return; /* don't need to flush */
2872
f15313bf 2873 RxFIFOEnabled = 0;
1da177e4 2874 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
f15313bf 2875 RxFIFOEnabled = 1;
1da177e4
LT		 2876 sDisRxFIFO(ChP); /* disable it */
2877 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2878 sInB(ChP->IntChan); /* depends on bus i/o timing */
2879 }
2880 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2881 Ch = (Byte_t) sGetChanNum(ChP);
2882 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2883 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2884 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2885 sOutW(ChP->IndexData, 0);
2886 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2887 sOutW(ChP->IndexData, 0);
2888 if (RxFIFOEnabled)
2889 sEnRxFIFO(ChP); /* enable Rx FIFO */
2890}
2891
2892/***************************************************************************
2893Function: sFlushTxFIFO
2894Purpose: Flush the Tx FIFO
2895Call: sFlushTxFIFO(ChP)
2896 CHANNEL_T *ChP; Ptr to channel structure
2897Return: void
2898Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2899 while it is being flushed the receive processor is stopped
2900 and the transmitter is disabled. After these operations a
2901 4 uS delay is done before clearing the pointers to allow
2902 the receive processor to stop. These items are handled inside
2903 this function.
2904Warnings: No context switches are allowed while executing this function.
2905*/
f15313bf 2906static void sFlushTxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2907{
2908 int i;
2909 Byte_t Ch; /* channel number within AIOP */
f15313bf 2910 int TxEnabled; /* 1 if transmitter enabled */
1da177e4
LT		 2911
2912 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2913 return; /* don't need to flush */
2914
f15313bf 2915 TxEnabled = 0;
1da177e4 2916 if (ChP->TxControl[3] & TX_ENABLE) {
f15313bf 2917 TxEnabled = 1;
1da177e4
LT		 2918 sDisTransmit(ChP); /* disable transmitter */
2919 }
2920 sStopRxProcessor(ChP); /* stop Rx processor */
2921 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2922 sInB(ChP->IntChan); /* depends on bus i/o timing */
2923 Ch = (Byte_t) sGetChanNum(ChP);
2924 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2925 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2926 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2927 sOutW(ChP->IndexData, 0);
2928 if (TxEnabled)
2929 sEnTransmit(ChP); /* enable transmitter */
2930 sStartRxProcessor(ChP); /* restart Rx processor */
2931}
2932
2933/***************************************************************************
2934Function: sWriteTxPrioByte
2935Purpose: Write a byte of priority transmit data to a channel
2936Call: sWriteTxPrioByte(ChP,Data)
2937 CHANNEL_T *ChP; Ptr to channel structure
2938 Byte_t Data; The transmit data byte
2939
2940Return: int: 1 if the bytes is successfully written, otherwise 0.
2941
2942Comments: The priority byte is transmitted before any data in the Tx FIFO.
2943
2944Warnings: No context switches are allowed while executing this function.
2945*/
f15313bf 2946static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
1da177e4
LT		 2947{
2948 Byte_t DWBuf[4]; /* buffer for double word writes */
2949 Word_t *WordPtr; /* must be far because Win SS != DS */
2950 register DWordIO_t IndexAddr;
2951
2952 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2953 IndexAddr = ChP->IndexAddr;
2954 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2955 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2956 return (0); /* nothing sent */
2957
2958 WordPtr = (Word_t *) (&DWBuf[0]);
2959 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2960
2961 DWBuf[2] = Data; /* data byte value */
457fb605 2962 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 2963
2964 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2965
2966 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2967 DWBuf[3] = 0; /* priority buffer pointer */
457fb605 2968 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 2969 } else { /* write it to Tx FIFO */
2970
2971 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2972 }
2973 return (1); /* 1 byte sent */
2974}
2975
2976/***************************************************************************
2977Function: sEnInterrupts
2978Purpose: Enable one or more interrupts for a channel
2979Call: sEnInterrupts(ChP,Flags)
2980 CHANNEL_T *ChP; Ptr to channel structure
2981 Word_t Flags: Interrupt enable flags, can be any combination
2982 of the following flags:
2983 TXINT_EN: Interrupt on Tx FIFO empty
2984 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
2985 sSetRxTrigger())
2986 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
2987 MCINT_EN: Interrupt on modem input change
2988 CHANINT_EN: Allow channel interrupt signal to the AIOP's
2989 Interrupt Channel Register.
2990Return: void
2991Comments: If an interrupt enable flag is set in Flags, that interrupt will be
2992 enabled. If an interrupt enable flag is not set in Flags, that
2993 interrupt will not be changed. Interrupts can be disabled with
2994 function sDisInterrupts().
2995
2996 This function sets the appropriate bit for the channel in the AIOP's
2997 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
2998 this channel's bit to be set in the AIOP's Interrupt Channel Register.
2999
3000 Interrupts must also be globally enabled before channel interrupts
3001 will be passed on to the host. This is done with function
3002 sEnGlobalInt().
3003
3004 In some cases it may be desirable to disable interrupts globally but
3005 enable channel interrupts. This would allow the global interrupt
3006 status register to be used to determine which AIOPs need service.
3007*/
f15313bf 3008static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3009{
3010 Byte_t Mask; /* Interrupt Mask Register */
3011
3012 ChP->RxControl[2] |=
3013 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3014
457fb605 3015 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 3016
3017 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3018
457fb605 3019 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3020
3021 if (Flags & CHANINT_EN) {
3022 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3023 sOutB(ChP->IntMask, Mask);
3024 }
3025}
3026
3027/***************************************************************************
3028Function: sDisInterrupts
3029Purpose: Disable one or more interrupts for a channel
3030Call: sDisInterrupts(ChP,Flags)
3031 CHANNEL_T *ChP; Ptr to channel structure
3032 Word_t Flags: Interrupt flags, can be any combination
3033 of the following flags:
3034 TXINT_EN: Interrupt on Tx FIFO empty
3035 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3036 sSetRxTrigger())
3037 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3038 MCINT_EN: Interrupt on modem input change
3039 CHANINT_EN: Disable channel interrupt signal to the
3040 AIOP's Interrupt Channel Register.
3041Return: void
3042Comments: If an interrupt flag is set in Flags, that interrupt will be
3043 disabled. If an interrupt flag is not set in Flags, that
3044 interrupt will not be changed. Interrupts can be enabled with
3045 function sEnInterrupts().
3046
3047 This function clears the appropriate bit for the channel in the AIOP's
3048 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3049 this channel's bit from being set in the AIOP's Interrupt Channel
3050 Register.
3051*/
f15313bf 3052static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3053{
3054 Byte_t Mask; /* Interrupt Mask Register */
3055
3056 ChP->RxControl[2] &=
3057 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
457fb605 3058 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4 3059 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
457fb605 3060 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3061
3062 if (Flags & CHANINT_EN) {
3063 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3064 sOutB(ChP->IntMask, Mask);
3065 }
3066}
3067
f15313bf 3068static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
1da177e4
LT		 3069{
3070 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3071}
3072
3073/*
3074 * Not an official SSCI function, but how to reset RocketModems.
3075 * ISA bus version
3076 */
f15313bf 3077static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3078{
3079 ByteIO_t addr;
3080 Byte_t val;
3081
3082 addr = CtlP->AiopIO[0] + 0x400;
3083 val = sInB(CtlP->MReg3IO);
3084 /* if AIOP[1] is not enabled, enable it */
3085 if ((val & 2) == 0) {
3086 val = sInB(CtlP->MReg2IO);
3087 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3088 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3089 }
3090
3091 sEnAiop(CtlP, 1);
3092 if (!on)
3093 addr += 8;
3094 sOutB(addr + chan, 0); /* apply or remove reset */
3095 sDisAiop(CtlP, 1);
3096}
3097
3098/*
3099 * Not an official SSCI function, but how to reset RocketModems.
3100 * PCI bus version
3101 */
f15313bf 3102static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3103{
3104 ByteIO_t addr;
3105
3106 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3107 if (!on)
3108 addr += 8;
3109 sOutB(addr + chan, 0); /* apply or remove reset */
3110}
3111
1da177e4
LT		 3112/* Returns the line number given the controller (board), aiop and channel number */
3113static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3114{
3115 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3116}
3117
3118/*
3119 * Stores the line number associated with a given controller (board), aiop
3120 * and channel number.
3121 * Returns: The line number assigned
3122 */
3123static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3124{
3125 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3126 return (nextLineNumber - 1);
3127}
Ubuntu Artful kernel mirror