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TTY: switch tty_buffer_request_room to tty_port
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / rocket.c
CommitLineData
1da177e4
LT		 1/*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42/****** Defines ******/
1da177e4
LT		 43#define ROCKET_PARANOIA_CHECK
44#define ROCKET_DISABLE_SIMUSAGE
45
46#undef ROCKET_SOFT_FLOW
47#undef ROCKET_DEBUG_OPEN
48#undef ROCKET_DEBUG_INTR
49#undef ROCKET_DEBUG_WRITE
50#undef ROCKET_DEBUG_FLOW
51#undef ROCKET_DEBUG_THROTTLE
52#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53#undef ROCKET_DEBUG_RECEIVE
54#undef ROCKET_DEBUG_HANGUP
55#undef REV_PCI_ORDER
56#undef ROCKET_DEBUG_IO
57
58#define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
59
60/****** Kernel includes ******/
61
1da177e4
LT		 62#include <linux/module.h>
63#include <linux/errno.h>
64#include <linux/major.h>
65#include <linux/kernel.h>
66#include <linux/signal.h>
67#include <linux/slab.h>
68#include <linux/mm.h>
69#include <linux/sched.h>
70#include <linux/timer.h>
71#include <linux/interrupt.h>
72#include <linux/tty.h>
73#include <linux/tty_driver.h>
74#include <linux/tty_flip.h>
44b7d1b3 75#include <linux/serial.h>
1da177e4
LT		 76#include <linux/string.h>
77#include <linux/fcntl.h>
78#include <linux/ptrace.h>
69f545ea 79#include <linux/mutex.h>
1da177e4
LT		 80#include <linux/ioport.h>
81#include <linux/delay.h>
8cf5a8c5 82#include <linux/completion.h>
1da177e4
LT		 83#include <linux/wait.h>
84#include <linux/pci.h>
44b7d1b3 85#include <linux/uaccess.h>
60063497 86#include <linux/atomic.h>
457fb605 87#include <asm/unaligned.h>
1da177e4
LT		 88#include <linux/bitops.h>
89#include <linux/spinlock.h>
1da177e4
LT		 90#include <linux/init.h>
91
92/****** RocketPort includes ******/
93
94#include "rocket_int.h"
95#include "rocket.h"
96
97#define ROCKET_VERSION "2.09"
98#define ROCKET_DATE "12-June-2003"
99
100/****** RocketPort Local Variables ******/
101
40565f19
JS		 102static void rp_do_poll(unsigned long dummy);
103
1da177e4
LT		 104static struct tty_driver *rocket_driver;
105
106static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
108};
109
110static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113static atomic_t rp_num_ports_open; /* Number of serial ports open */
40565f19 114static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
1da177e4
LT		 115
116static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117static unsigned long board2;
118static unsigned long board3;
119static unsigned long board4;
120static unsigned long controller;
90ab5ee9 121static bool support_low_speed;
1da177e4
LT		 122static unsigned long modem1;
123static unsigned long modem2;
124static unsigned long modem3;
125static unsigned long modem4;
126static unsigned long pc104_1[8];
127static unsigned long pc104_2[8];
128static unsigned long pc104_3[8];
129static unsigned long pc104_4[8];
130static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131
132static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133static unsigned long rcktpt_io_addr[NUM_BOARDS];
134static int rcktpt_type[NUM_BOARDS];
135static int is_PCI[NUM_BOARDS];
136static rocketModel_t rocketModel[NUM_BOARDS];
137static int max_board;
31f35939 138static const struct tty_port_operations rocket_port_ops;
1da177e4
LT		 139
140/*
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
144 */
145
146static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147 AIOP_INTR_BIT_0,
148 AIOP_INTR_BIT_1,
149 AIOP_INTR_BIT_2,
150 AIOP_INTR_BIT_3
151};
152
153static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
154 UPCI_AIOP_INTR_BIT_0,
155 UPCI_AIOP_INTR_BIT_1,
156 UPCI_AIOP_INTR_BIT_2,
157 UPCI_AIOP_INTR_BIT_3
158};
159
f15313bf
AB		 160static Byte_t RData[RDATASIZE] = {
161 0x00, 0x09, 0xf6, 0x82,
162 0x02, 0x09, 0x86, 0xfb,
163 0x04, 0x09, 0x00, 0x0a,
164 0x06, 0x09, 0x01, 0x0a,
165 0x08, 0x09, 0x8a, 0x13,
166 0x0a, 0x09, 0xc5, 0x11,
167 0x0c, 0x09, 0x86, 0x85,
168 0x0e, 0x09, 0x20, 0x0a,
169 0x10, 0x09, 0x21, 0x0a,
170 0x12, 0x09, 0x41, 0xff,
171 0x14, 0x09, 0x82, 0x00,
172 0x16, 0x09, 0x82, 0x7b,
173 0x18, 0x09, 0x8a, 0x7d,
174 0x1a, 0x09, 0x88, 0x81,
175 0x1c, 0x09, 0x86, 0x7a,
176 0x1e, 0x09, 0x84, 0x81,
177 0x20, 0x09, 0x82, 0x7c,
178 0x22, 0x09, 0x0a, 0x0a
179};
180
181static Byte_t RRegData[RREGDATASIZE] = {
182 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
183 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
184 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
185 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
186 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
187 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
188 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
189 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
190 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
191 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
192 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
193 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
194 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
195};
196
197static CONTROLLER_T sController[CTL_SIZE] = {
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
206};
207
208static Byte_t sBitMapClrTbl[8] = {
209 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
210};
211
212static Byte_t sBitMapSetTbl[8] = {
213 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
214};
215
216static int sClockPrescale = 0x14;
217
1da177e4
LT		 218/*
219 * Line number is the ttySIx number (x), the Minor number. We
220 * assign them sequentially, starting at zero. The following
221 * array keeps track of the line number assigned to a given board/aiop/channel.
222 */
223static unsigned char lineNumbers[MAX_RP_PORTS];
224static unsigned long nextLineNumber;
225
226/***** RocketPort Static Prototypes *********/
227static int __init init_ISA(int i);
228static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
229static void rp_flush_buffer(struct tty_struct *tty);
230static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
231static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
232static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
233static void rp_start(struct tty_struct *tty);
f15313bf
AB		 234static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
235 int ChanNum);
236static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
237static void sFlushRxFIFO(CHANNEL_T * ChP);
238static void sFlushTxFIFO(CHANNEL_T * ChP);
239static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
240static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
241static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
242static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
243static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
244static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
245 ByteIO_t * AiopIOList, int AiopIOListSize,
246 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
247 int PeriodicOnly, int altChanRingIndicator,
248 int UPCIRingInd);
249static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
250 ByteIO_t * AiopIOList, int AiopIOListSize,
251 int IRQNum, Byte_t Frequency, int PeriodicOnly);
252static int sReadAiopID(ByteIO_t io);
253static int sReadAiopNumChan(WordIO_t io);
1da177e4 254
1da177e4
LT		 255MODULE_AUTHOR("Theodore Ts'o");
256MODULE_DESCRIPTION("Comtrol RocketPort driver");
257module_param(board1, ulong, 0);
258MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
259module_param(board2, ulong, 0);
260MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
261module_param(board3, ulong, 0);
262MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
263module_param(board4, ulong, 0);
264MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
265module_param(controller, ulong, 0);
266MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
267module_param(support_low_speed, bool, 0);
268MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
269module_param(modem1, ulong, 0);
270MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
271module_param(modem2, ulong, 0);
272MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
273module_param(modem3, ulong, 0);
274MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
275module_param(modem4, ulong, 0);
276MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
277module_param_array(pc104_1, ulong, NULL, 0);
278MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
279module_param_array(pc104_2, ulong, NULL, 0);
280MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
281module_param_array(pc104_3, ulong, NULL, 0);
282MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
283module_param_array(pc104_4, ulong, NULL, 0);
284MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
285
d269cdd0 286static int rp_init(void);
1da177e4
LT		 287static void rp_cleanup_module(void);
288
289module_init(rp_init);
290module_exit(rp_cleanup_module);
291
1da177e4 292
1da177e4 293MODULE_LICENSE("Dual BSD/GPL");
1da177e4
LT		 294
295/*************************************************************************/
296/* Module code starts here */
297
298static inline int rocket_paranoia_check(struct r_port *info,
299 const char *routine)
300{
301#ifdef ROCKET_PARANOIA_CHECK
302 if (!info)
303 return 1;
304 if (info->magic != RPORT_MAGIC) {
68562b79
JS		 305 printk(KERN_WARNING "Warning: bad magic number for rocketport "
306 "struct in %s\n", routine);
1da177e4
LT		 307 return 1;
308 }
309#endif
310 return 0;
311}
312
313
314/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
315 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
316 * tty layer.
317 */
318static void rp_do_receive(struct r_port *info,
319 struct tty_struct *tty,
320 CHANNEL_t * cp, unsigned int ChanStatus)
321{
322 unsigned int CharNStat;
cc44a817
PF		 323 int ToRecv, wRecv, space;
324 unsigned char *cbuf;
1da177e4
LT		 325
326 ToRecv = sGetRxCnt(cp);
1da177e4 327#ifdef ROCKET_DEBUG_INTR
68562b79 328 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
1da177e4 329#endif
cc44a817
PF		 330 if (ToRecv == 0)
331 return;
33f0f88f 332
1da177e4
LT		 333 /*
334 * if status indicates there are errored characters in the
335 * FIFO, then enter status mode (a word in FIFO holds
336 * character and status).
337 */
338 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
339 if (!(ChanStatus & STATMODE)) {
340#ifdef ROCKET_DEBUG_RECEIVE
68562b79 341 printk(KERN_INFO "Entering STATMODE...\n");
1da177e4
LT		 342#endif
343 ChanStatus |= STATMODE;
344 sEnRxStatusMode(cp);
345 }
346 }
347
348 /*
349 * if we previously entered status mode, then read down the
350 * FIFO one word at a time, pulling apart the character and
351 * the status. Update error counters depending on status
352 */
353 if (ChanStatus & STATMODE) {
354#ifdef ROCKET_DEBUG_RECEIVE
68562b79
JS		 355 printk(KERN_INFO "Ignore %x, read %x...\n",
356 info->ignore_status_mask, info->read_status_mask);
1da177e4
LT		 357#endif
358 while (ToRecv) {
cc44a817
PF		 359 char flag;
360
1da177e4
LT		 361 CharNStat = sInW(sGetTxRxDataIO(cp));
362#ifdef ROCKET_DEBUG_RECEIVE
68562b79 363 printk(KERN_INFO "%x...\n", CharNStat);
1da177e4
LT		 364#endif
365 if (CharNStat & STMBREAKH)
366 CharNStat &= ~(STMFRAMEH | STMPARITYH);
367 if (CharNStat & info->ignore_status_mask) {
368 ToRecv--;
369 continue;
370 }
371 CharNStat &= info->read_status_mask;
372 if (CharNStat & STMBREAKH)
cc44a817 373 flag = TTY_BREAK;
1da177e4 374 else if (CharNStat & STMPARITYH)
cc44a817 375 flag = TTY_PARITY;
1da177e4 376 else if (CharNStat & STMFRAMEH)
cc44a817 377 flag = TTY_FRAME;
1da177e4 378 else if (CharNStat & STMRCVROVRH)
cc44a817 379 flag = TTY_OVERRUN;
1da177e4 380 else
cc44a817
PF		 381 flag = TTY_NORMAL;
382 tty_insert_flip_char(tty, CharNStat & 0xff, flag);
1da177e4
LT		 383 ToRecv--;
384 }
385
386 /*
387 * after we've emptied the FIFO in status mode, turn
388 * status mode back off
389 */
390 if (sGetRxCnt(cp) == 0) {
391#ifdef ROCKET_DEBUG_RECEIVE
392 printk(KERN_INFO "Status mode off.\n");
393#endif
394 sDisRxStatusMode(cp);
395 }
396 } else {
397 /*
398 * we aren't in status mode, so read down the FIFO two
399 * characters at time by doing repeated word IO
400 * transfer.
401 */
cc44a817
PF		 402 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
403 if (space < ToRecv) {
404#ifdef ROCKET_DEBUG_RECEIVE
405 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
406#endif
407 if (space <= 0)
408 return;
409 ToRecv = space;
410 }
1da177e4
LT		 411 wRecv = ToRecv >> 1;
412 if (wRecv)
413 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
414 if (ToRecv & 1)
415 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
1da177e4
LT		 416 }
417 /* Push the data up to the tty layer */
cc44a817 418 tty_flip_buffer_push(tty);
1da177e4
LT		 419}
420
421/*
422 * Serial port transmit data function. Called from the timer polling loop as a
423 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
424 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
425 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
426 */
427static void rp_do_transmit(struct r_port *info)
428{
429 int c;
430 CHANNEL_t *cp = &info->channel;
431 struct tty_struct *tty;
432 unsigned long flags;
433
434#ifdef ROCKET_DEBUG_INTR
68562b79 435 printk(KERN_DEBUG "%s\n", __func__);
1da177e4
LT		 436#endif
437 if (!info)
438 return;
47b01b3a
AC		 439 tty = tty_port_tty_get(&info->port);
440
441 if (tty == NULL) {
442 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
1da177e4
LT		 443 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
444 return;
445 }
446
447 spin_lock_irqsave(&info->slock, flags);
1da177e4
LT		 448 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
449
450 /* Loop sending data to FIFO until done or FIFO full */
451 while (1) {
452 if (tty->stopped || tty->hw_stopped)
453 break;
709107fc
HH		 454 c = min(info->xmit_fifo_room, info->xmit_cnt);
455 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
1da177e4
LT		 456 if (c <= 0 || info->xmit_fifo_room <= 0)
457 break;
458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
459 if (c & 1)
460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
461 info->xmit_tail += c;
462 info->xmit_tail &= XMIT_BUF_SIZE - 1;
463 info->xmit_cnt -= c;
464 info->xmit_fifo_room -= c;
465#ifdef ROCKET_DEBUG_INTR
68562b79 466 printk(KERN_INFO "tx %d chars...\n", c);
1da177e4
LT		 467#endif
468 }
469
470 if (info->xmit_cnt == 0)
471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
472
473 if (info->xmit_cnt < WAKEUP_CHARS) {
474 tty_wakeup(tty);
1da177e4
LT		 475#ifdef ROCKETPORT_HAVE_POLL_WAIT
476 wake_up_interruptible(&tty->poll_wait);
477#endif
478 }
479
480 spin_unlock_irqrestore(&info->slock, flags);
47b01b3a 481 tty_kref_put(tty);
1da177e4
LT		 482
483#ifdef ROCKET_DEBUG_INTR
68562b79 484 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
1da177e4
LT		 485 info->xmit_tail, info->xmit_fifo_room);
486#endif
487}
488
489/*
490 * Called when a serial port signals it has read data in it's RX FIFO.
491 * It checks what interrupts are pending and services them, including
492 * receiving serial data.
493 */
494static void rp_handle_port(struct r_port *info)
495{
496 CHANNEL_t *cp;
497 struct tty_struct *tty;
498 unsigned int IntMask, ChanStatus;
499
500 if (!info)
501 return;
502
21bed701 503 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
68562b79
JS		 504 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
505 "info->flags & NOT_INIT\n");
1da177e4
LT		 506 return;
507 }
47b01b3a
AC		 508 tty = tty_port_tty_get(&info->port);
509 if (!tty) {
68562b79 510 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
47b01b3a 511 "tty==NULL\n");
1da177e4
LT		 512 return;
513 }
514 cp = &info->channel;
1da177e4
LT		 515
516 IntMask = sGetChanIntID(cp) & info->intmask;
517#ifdef ROCKET_DEBUG_INTR
68562b79 518 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
1da177e4
LT		 519#endif
520 ChanStatus = sGetChanStatus(cp);
521 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
522 rp_do_receive(info, tty, cp, ChanStatus);
523 }
524 if (IntMask & DELTA_CD) { /* CD change */
525#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
68562b79 526 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
1da177e4
LT		 527 (ChanStatus & CD_ACT) ? "on" : "off");
528#endif
529 if (!(ChanStatus & CD_ACT) && info->cd_status) {
530#ifdef ROCKET_DEBUG_HANGUP
531 printk(KERN_INFO "CD drop, calling hangup.\n");
532#endif
533 tty_hangup(tty);
534 }
535 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
e60a1084 536 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 537 }
538#ifdef ROCKET_DEBUG_INTR
539 if (IntMask & DELTA_CTS) { /* CTS change */
540 printk(KERN_INFO "CTS change...\n");
541 }
542 if (IntMask & DELTA_DSR) { /* DSR change */
543 printk(KERN_INFO "DSR change...\n");
544 }
545#endif
47b01b3a 546 tty_kref_put(tty);
1da177e4
LT		 547}
548
549/*
550 * The top level polling routine. Repeats every 1/100 HZ (10ms).
551 */
552static void rp_do_poll(unsigned long dummy)
553{
554 CONTROLLER_t *ctlp;
6c0286b1
JS		 555 int ctrl, aiop, ch, line;
556 unsigned int xmitmask, i;
1da177e4
LT		 557 unsigned int CtlMask;
558 unsigned char AiopMask;
559 Word_t bit;
560
561 /* Walk through all the boards (ctrl's) */
562 for (ctrl = 0; ctrl < max_board; ctrl++) {
563 if (rcktpt_io_addr[ctrl] <= 0)
564 continue;
565
566 /* Get a ptr to the board's control struct */
567 ctlp = sCtlNumToCtlPtr(ctrl);
568
3a4fa0a2 569 /* Get the interrupt status from the board */
1da177e4
LT		 570#ifdef CONFIG_PCI
571 if (ctlp->BusType == isPCI)
572 CtlMask = sPCIGetControllerIntStatus(ctlp);
573 else
574#endif
575 CtlMask = sGetControllerIntStatus(ctlp);
576
577 /* Check if any AIOP read bits are set */
578 for (aiop = 0; CtlMask; aiop++) {
579 bit = ctlp->AiopIntrBits[aiop];
580 if (CtlMask & bit) {
581 CtlMask &= ~bit;
582 AiopMask = sGetAiopIntStatus(ctlp, aiop);
583
584 /* Check if any port read bits are set */
585 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
586 if (AiopMask & 1) {
587
588 /* Get the line number (/dev/ttyRx number). */
589 /* Read the data from the port. */
590 line = GetLineNumber(ctrl, aiop, ch);
591 rp_handle_port(rp_table[line]);
592 }
593 }
594 }
595 }
596
597 xmitmask = xmit_flags[ctrl];
598
599 /*
600 * xmit_flags contains bit-significant flags, indicating there is data
601 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
602 * 1, ... (32 total possible). The variable i has the aiop and ch
603 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
604 */
605 if (xmitmask) {
606 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
607 if (xmitmask & (1 << i)) {
608 aiop = (i & 0x18) >> 3;
609 ch = i & 0x07;
610 line = GetLineNumber(ctrl, aiop, ch);
611 rp_do_transmit(rp_table[line]);
612 }
613 }
614 }
615 }
616
617 /*
618 * Reset the timer so we get called at the next clock tick (10ms).
619 */
620 if (atomic_read(&rp_num_ports_open))
621 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
622}
623
624/*
625 * Initializes the r_port structure for a port, as well as enabling the port on
626 * the board.
627 * Inputs: board, aiop, chan numbers
628 */
629static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
630{
631 unsigned rocketMode;
632 struct r_port *info;
633 int line;
634 CONTROLLER_T *ctlp;
635
636 /* Get the next available line number */
637 line = SetLineNumber(board, aiop, chan);
638
639 ctlp = sCtlNumToCtlPtr(board);
640
641 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
dd00cc48 642 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
1da177e4 643 if (!info) {
68562b79
JS		 644 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
645 line);
1da177e4
LT		 646 return;
647 }
1da177e4
LT		 648
649 info->magic = RPORT_MAGIC;
650 info->line = line;
651 info->ctlp = ctlp;
652 info->board = board;
653 info->aiop = aiop;
654 info->chan = chan;
31f35939
AC		 655 tty_port_init(&info->port);
656 info->port.ops = &rocket_port_ops;
8cf5a8c5 657 init_completion(&info->close_wait);
1da177e4
LT		 658 info->flags &= ~ROCKET_MODE_MASK;
659 switch (pc104[board][line]) {
660 case 422:
661 info->flags |= ROCKET_MODE_RS422;
662 break;
663 case 485:
664 info->flags |= ROCKET_MODE_RS485;
665 break;
666 case 232:
667 default:
668 info->flags |= ROCKET_MODE_RS232;
669 break;
670 }
671
672 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
673 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
68562b79
JS		 674 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
675 board, aiop, chan);
191c5f10 676 tty_port_destroy(&info->port);
1da177e4
LT		 677 kfree(info);
678 return;
679 }
680
681 rocketMode = info->flags & ROCKET_MODE_MASK;
682
683 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
684 sEnRTSToggle(&info->channel);
685 else
686 sDisRTSToggle(&info->channel);
687
688 if (ctlp->boardType == ROCKET_TYPE_PC104) {
689 switch (rocketMode) {
690 case ROCKET_MODE_RS485:
691 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
692 break;
693 case ROCKET_MODE_RS422:
694 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
695 break;
696 case ROCKET_MODE_RS232:
697 default:
698 if (info->flags & ROCKET_RTS_TOGGLE)
699 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
700 else
701 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
702 break;
703 }
704 }
705 spin_lock_init(&info->slock);
69f545ea 706 mutex_init(&info->write_mtx);
1da177e4 707 rp_table[line] = info;
734cc178
JS		 708 tty_port_register_device(&info->port, rocket_driver, line,
709 pci_dev ? &pci_dev->dev : NULL);
1da177e4
LT		 710}
711
712/*
713 * Configures a rocketport port according to its termio settings. Called from
714 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
715 */
47b01b3a 716static void configure_r_port(struct tty_struct *tty, struct r_port *info,
606d099c 717 struct ktermios *old_termios)
1da177e4
LT		 718{
719 unsigned cflag;
720 unsigned long flags;
721 unsigned rocketMode;
722 int bits, baud, divisor;
723 CHANNEL_t *cp;
adc8d746 724 struct ktermios *t = &tty->termios;
1da177e4 725
1da177e4 726 cp = &info->channel;
6df3526b 727 cflag = t->c_cflag;
1da177e4
LT		 728
729 /* Byte size and parity */
730 if ((cflag & CSIZE) == CS8) {
731 sSetData8(cp);
732 bits = 10;
733 } else {
734 sSetData7(cp);
735 bits = 9;
736 }
737 if (cflag & CSTOPB) {
738 sSetStop2(cp);
739 bits++;
740 } else {
741 sSetStop1(cp);
742 }
743
744 if (cflag & PARENB) {
745 sEnParity(cp);
746 bits++;
747 if (cflag & PARODD) {
748 sSetOddParity(cp);
749 } else {
750 sSetEvenParity(cp);
751 }
752 } else {
753 sDisParity(cp);
754 }
755
756 /* baud rate */
47b01b3a 757 baud = tty_get_baud_rate(tty);
1da177e4
LT		 758 if (!baud)
759 baud = 9600;
760 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
761 if ((divisor >= 8192 || divisor < 0) && old_termios) {
6df3526b 762 baud = tty_termios_baud_rate(old_termios);
1da177e4
LT		 763 if (!baud)
764 baud = 9600;
765 divisor = (rp_baud_base[info->board] / baud) - 1;
766 }
767 if (divisor >= 8192 || divisor < 0) {
768 baud = 9600;
769 divisor = (rp_baud_base[info->board] / baud) - 1;
770 }
771 info->cps = baud / bits;
772 sSetBaud(cp, divisor);
773
6df3526b 774 /* FIXME: Should really back compute a baud rate from the divisor */
47b01b3a 775 tty_encode_baud_rate(tty, baud, baud);
6df3526b 776
1da177e4
LT		 777 if (cflag & CRTSCTS) {
778 info->intmask |= DELTA_CTS;
779 sEnCTSFlowCtl(cp);
780 } else {
781 info->intmask &= ~DELTA_CTS;
782 sDisCTSFlowCtl(cp);
783 }
784 if (cflag & CLOCAL) {
785 info->intmask &= ~DELTA_CD;
786 } else {
787 spin_lock_irqsave(&info->slock, flags);
788 if (sGetChanStatus(cp) & CD_ACT)
789 info->cd_status = 1;
790 else
791 info->cd_status = 0;
792 info->intmask |= DELTA_CD;
793 spin_unlock_irqrestore(&info->slock, flags);
794 }
795
796 /*
797 * Handle software flow control in the board
798 */
799#ifdef ROCKET_SOFT_FLOW
47b01b3a 800 if (I_IXON(tty)) {
1da177e4 801 sEnTxSoftFlowCtl(cp);
47b01b3a 802 if (I_IXANY(tty)) {
1da177e4
LT		 803 sEnIXANY(cp);
804 } else {
805 sDisIXANY(cp);
806 }
47b01b3a
AC		 807 sSetTxXONChar(cp, START_CHAR(tty));
808 sSetTxXOFFChar(cp, STOP_CHAR(tty));
1da177e4
LT		 809 } else {
810 sDisTxSoftFlowCtl(cp);
811 sDisIXANY(cp);
812 sClrTxXOFF(cp);
813 }
814#endif
815
816 /*
817 * Set up ignore/read mask words
818 */
819 info->read_status_mask = STMRCVROVRH | 0xFF;
47b01b3a 820 if (I_INPCK(tty))
1da177e4 821 info->read_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 822 if (I_BRKINT(tty) || I_PARMRK(tty))
1da177e4
LT		 823 info->read_status_mask |= STMBREAKH;
824
825 /*
826 * Characters to ignore
827 */
828 info->ignore_status_mask = 0;
47b01b3a 829 if (I_IGNPAR(tty))
1da177e4 830 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
47b01b3a 831 if (I_IGNBRK(tty)) {
1da177e4
LT		 832 info->ignore_status_mask |= STMBREAKH;
833 /*
834 * If we're ignoring parity and break indicators,
835 * ignore overruns too. (For real raw support).
836 */
47b01b3a 837 if (I_IGNPAR(tty))
1da177e4
LT		 838 info->ignore_status_mask |= STMRCVROVRH;
839 }
840
841 rocketMode = info->flags & ROCKET_MODE_MASK;
842
843 if ((info->flags & ROCKET_RTS_TOGGLE)
844 || (rocketMode == ROCKET_MODE_RS485))
845 sEnRTSToggle(cp);
846 else
847 sDisRTSToggle(cp);
848
849 sSetRTS(&info->channel);
850
851 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
852 switch (rocketMode) {
853 case ROCKET_MODE_RS485:
854 sSetInterfaceMode(cp, InterfaceModeRS485);
855 break;
856 case ROCKET_MODE_RS422:
857 sSetInterfaceMode(cp, InterfaceModeRS422);
858 break;
859 case ROCKET_MODE_RS232:
860 default:
861 if (info->flags & ROCKET_RTS_TOGGLE)
862 sSetInterfaceMode(cp, InterfaceModeRS232T);
863 else
864 sSetInterfaceMode(cp, InterfaceModeRS232);
865 break;
866 }
867 }
868}
869
31f35939
AC		 870static int carrier_raised(struct tty_port *port)
871{
872 struct r_port *info = container_of(port, struct r_port, port);
873 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
874}
875
fcc8ac18 876static void dtr_rts(struct tty_port *port, int on)
5d951fb4
AC		 877{
878 struct r_port *info = container_of(port, struct r_port, port);
fcc8ac18
AC		 879 if (on) {
880 sSetDTR(&info->channel);
881 sSetRTS(&info->channel);
882 } else {
883 sClrDTR(&info->channel);
884 sClrRTS(&info->channel);
885 }
5d951fb4
AC		 886}
887
1da177e4
LT		 888/*
889 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
890 * port's r_port struct. Initializes the port hardware.
891 */
892static int rp_open(struct tty_struct *tty, struct file *filp)
893{
894 struct r_port *info;
fba85e01 895 struct tty_port *port;
410235fd 896 int retval;
1da177e4
LT		 897 CHANNEL_t *cp;
898 unsigned long page;
899
410235fd
JS		 900 info = rp_table[tty->index];
901 if (info == NULL)
1da177e4 902 return -ENXIO;
fba85e01
AC		 903 port = &info->port;
904
1da177e4
LT		 905 page = __get_free_page(GFP_KERNEL);
906 if (!page)
907 return -ENOMEM;
908
fba85e01 909 if (port->flags & ASYNC_CLOSING) {
8cf5a8c5 910 retval = wait_for_completion_interruptible(&info->close_wait);
1da177e4 911 free_page(page);
8cf5a8c5
JS		 912 if (retval)
913 return retval;
fba85e01 914 return ((port->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
1da177e4
LT		 915 }
916
917 /*
918 * We must not sleep from here until the port is marked fully in use.
919 */
920 if (info->xmit_buf)
921 free_page(page);
922 else
923 info->xmit_buf = (unsigned char *) page;
924
925 tty->driver_data = info;
fba85e01 926 tty_port_tty_set(port, tty);
1da177e4 927
fba85e01 928 if (port->count++ == 0) {
1da177e4
LT		 929 atomic_inc(&rp_num_ports_open);
930
931#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 932 printk(KERN_INFO "rocket mod++ = %d...\n",
933 atomic_read(&rp_num_ports_open));
1da177e4
LT		 934#endif
935 }
936#ifdef ROCKET_DEBUG_OPEN
e60a1084 937 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
1da177e4
LT		 938#endif
939
940 /*
941 * Info->count is now 1; so it's safe to sleep now.
942 */
a391ad0f 943 if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
1da177e4
LT		 944 cp = &info->channel;
945 sSetRxTrigger(cp, TRIG_1);
946 if (sGetChanStatus(cp) & CD_ACT)
947 info->cd_status = 1;
948 else
949 info->cd_status = 0;
950 sDisRxStatusMode(cp);
951 sFlushRxFIFO(cp);
952 sFlushTxFIFO(cp);
953
954 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
955 sSetRxTrigger(cp, TRIG_1);
956
957 sGetChanStatus(cp);
958 sDisRxStatusMode(cp);
959 sClrTxXOFF(cp);
960
961 sDisCTSFlowCtl(cp);
962 sDisTxSoftFlowCtl(cp);
963
964 sEnRxFIFO(cp);
965 sEnTransmit(cp);
966
a391ad0f 967 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
1da177e4
LT		 968
969 /*
970 * Set up the tty->alt_speed kludge
971 */
972 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
47b01b3a 973 tty->alt_speed = 57600;
1da177e4 974 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
47b01b3a 975 tty->alt_speed = 115200;
1da177e4 976 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
47b01b3a 977 tty->alt_speed = 230400;
1da177e4 978 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
47b01b3a 979 tty->alt_speed = 460800;
1da177e4 980
47b01b3a 981 configure_r_port(tty, info, NULL);
adc8d746 982 if (tty->termios.c_cflag & CBAUD) {
1da177e4
LT		 983 sSetDTR(cp);
984 sSetRTS(cp);
985 }
986 }
987 /* Starts (or resets) the maint polling loop */
988 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
989
fba85e01 990 retval = tty_port_block_til_ready(port, tty, filp);
1da177e4
LT		 991 if (retval) {
992#ifdef ROCKET_DEBUG_OPEN
993 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
994#endif
995 return retval;
996 }
997 return 0;
998}
999
1000/*
e60a1084 1001 * Exception handler that closes a serial port. info->port.count is considered critical.
1da177e4
LT		 1002 */
1003static void rp_close(struct tty_struct *tty, struct file *filp)
1004{
c9f19e96 1005 struct r_port *info = tty->driver_data;
c1314a49 1006 struct tty_port *port = &info->port;
1da177e4
LT		 1007 int timeout;
1008 CHANNEL_t *cp;
1009
1010 if (rocket_paranoia_check(info, "rp_close"))
1011 return;
1012
1013#ifdef ROCKET_DEBUG_OPEN
e60a1084 1014 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1da177e4
LT		 1015#endif
1016
fba85e01 1017 if (tty_port_close_start(port, tty, filp) == 0)
1da177e4 1018 return;
1da177e4 1019
417b6e0e 1020 mutex_lock(&port->mutex);
1da177e4 1021 cp = &info->channel;
1da177e4
LT		 1022 /*
1023 * Before we drop DTR, make sure the UART transmitter
1024 * has completely drained; this is especially
1025 * important if there is a transmit FIFO!
1026 */
1027 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1028 if (timeout == 0)
1029 timeout = 1;
1030 rp_wait_until_sent(tty, timeout);
1031 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1032
1033 sDisTransmit(cp);
1034 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1035 sDisCTSFlowCtl(cp);
1036 sDisTxSoftFlowCtl(cp);
1037 sClrTxXOFF(cp);
1038 sFlushRxFIFO(cp);
1039 sFlushTxFIFO(cp);
1040 sClrRTS(cp);
1041 if (C_HUPCL(tty))
1042 sClrDTR(cp);
1043
f6de0c98 1044 rp_flush_buffer(tty);
1da177e4
LT		 1045
1046 tty_ldisc_flush(tty);
1047
1048 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1049
fba85e01
AC		 1050 /* We can't yet use tty_port_close_end as the buffer handling in this
1051 driver is a bit different to the usual */
1052
c1314a49
AC		 1053 if (port->blocked_open) {
1054 if (port->close_delay) {
1055 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1da177e4 1056 }
c1314a49 1057 wake_up_interruptible(&port->open_wait);
1da177e4
LT		 1058 } else {
1059 if (info->xmit_buf) {
1060 free_page((unsigned long) info->xmit_buf);
1061 info->xmit_buf = NULL;
1062 }
1063 }
417b6e0e 1064 spin_lock_irq(&port->lock);
21bed701 1065 info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1da177e4 1066 tty->closing = 0;
417b6e0e
AC		 1067 spin_unlock_irq(&port->lock);
1068 mutex_unlock(&port->mutex);
fba85e01 1069 tty_port_tty_set(port, NULL);
417b6e0e 1070
fba85e01 1071 wake_up_interruptible(&port->close_wait);
8cf5a8c5 1072 complete_all(&info->close_wait);
1da177e4
LT		 1073 atomic_dec(&rp_num_ports_open);
1074
1075#ifdef ROCKET_DEBUG_OPEN
68562b79
JS		 1076 printk(KERN_INFO "rocket mod-- = %d...\n",
1077 atomic_read(&rp_num_ports_open));
1da177e4
LT		 1078 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1079#endif
1080
1081}
1082
1083static void rp_set_termios(struct tty_struct *tty,
606d099c 1084 struct ktermios *old_termios)
1da177e4 1085{
c9f19e96 1086 struct r_port *info = tty->driver_data;
1da177e4
LT		 1087 CHANNEL_t *cp;
1088 unsigned cflag;
1089
1090 if (rocket_paranoia_check(info, "rp_set_termios"))
1091 return;
1092
adc8d746 1093 cflag = tty->termios.c_cflag;
1da177e4 1094
1da177e4
LT		 1095 /*
1096 * This driver doesn't support CS5 or CS6
1097 */
1098 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
adc8d746 1099 tty->termios.c_cflag =
1da177e4 1100 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
6df3526b 1101 /* Or CMSPAR */
adc8d746 1102 tty->termios.c_cflag &= ~CMSPAR;
1da177e4 1103
47b01b3a 1104 configure_r_port(tty, info, old_termios);
1da177e4
LT		 1105
1106 cp = &info->channel;
1107
1108 /* Handle transition to B0 status */
adc8d746 1109 if ((old_termios->c_cflag & CBAUD) && !(tty->termios.c_cflag & CBAUD)) {
1da177e4
LT		 1110 sClrDTR(cp);
1111 sClrRTS(cp);
1112 }
1113
1114 /* Handle transition away from B0 status */
adc8d746
AC		 1115 if (!(old_termios->c_cflag & CBAUD) && (tty->termios.c_cflag & CBAUD)) {
1116 if (!tty->hw_stopped || !(tty->termios.c_cflag & CRTSCTS))
1da177e4
LT		 1117 sSetRTS(cp);
1118 sSetDTR(cp);
1119 }
1120
adc8d746 1121 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios.c_cflag & CRTSCTS)) {
1da177e4
LT		 1122 tty->hw_stopped = 0;
1123 rp_start(tty);
1124 }
1125}
1126
9e98966c 1127static int rp_break(struct tty_struct *tty, int break_state)
1da177e4 1128{
c9f19e96 1129 struct r_port *info = tty->driver_data;
1da177e4
LT		 1130 unsigned long flags;
1131
1132 if (rocket_paranoia_check(info, "rp_break"))
9e98966c 1133 return -EINVAL;
1da177e4
LT		 1134
1135 spin_lock_irqsave(&info->slock, flags);
1136 if (break_state == -1)
1137 sSendBreak(&info->channel);
1138 else
1139 sClrBreak(&info->channel);
1140 spin_unlock_irqrestore(&info->slock, flags);
9e98966c 1141 return 0;
1da177e4
LT		 1142}
1143
1144/*
1145 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1146 * the UPCI boards was added, it was decided to make this a function because
1147 * the macro was getting too complicated. All cases except the first one
1148 * (UPCIRingInd) are taken directly from the original macro.
1149 */
1150static int sGetChanRI(CHANNEL_T * ChP)
1151{
1152 CONTROLLER_t *CtlP = ChP->CtlP;
1153 int ChanNum = ChP->ChanNum;
1154 int RingInd = 0;
1155
1156 if (CtlP->UPCIRingInd)
1157 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1158 else if (CtlP->AltChanRingIndicator)
1159 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1160 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1161 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1162
1163 return RingInd;
1164}
1165
1166/********************************************************************************************/
1167/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1168
1169/*
1170 * Returns the state of the serial modem control lines. These next 2 functions
1171 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1172 */
60b33c13 1173static int rp_tiocmget(struct tty_struct *tty)
1da177e4 1174{
c9f19e96 1175 struct r_port *info = tty->driver_data;
1da177e4
LT		 1176 unsigned int control, result, ChanStatus;
1177
1178 ChanStatus = sGetChanStatusLo(&info->channel);
1179 control = info->channel.TxControl[3];
1180 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1181 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1182 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1183 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1184 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1185 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1186
1187 return result;
1188}
1189
1190/*
1191 * Sets the modem control lines
1192 */
20b9d177
AC		 1193static int rp_tiocmset(struct tty_struct *tty,
1194 unsigned int set, unsigned int clear)
1da177e4 1195{
c9f19e96 1196 struct r_port *info = tty->driver_data;
1da177e4
LT		 1197
1198 if (set & TIOCM_RTS)
1199 info->channel.TxControl[3] |= SET_RTS;
1200 if (set & TIOCM_DTR)
1201 info->channel.TxControl[3] |= SET_DTR;
1202 if (clear & TIOCM_RTS)
1203 info->channel.TxControl[3] &= ~SET_RTS;
1204 if (clear & TIOCM_DTR)
1205 info->channel.TxControl[3] &= ~SET_DTR;
1206
457fb605 1207 out32(info->channel.IndexAddr, info->channel.TxControl);
1da177e4
LT		 1208 return 0;
1209}
1210
1211static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1212{
1213 struct rocket_config tmp;
1214
1215 if (!retinfo)
1216 return -EFAULT;
1217 memset(&tmp, 0, sizeof (tmp));
417b6e0e 1218 mutex_lock(&info->port.mutex);
1da177e4
LT		 1219 tmp.line = info->line;
1220 tmp.flags = info->flags;
44b7d1b3
AC		 1221 tmp.close_delay = info->port.close_delay;
1222 tmp.closing_wait = info->port.closing_wait;
1da177e4 1223 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
417b6e0e 1224 mutex_unlock(&info->port.mutex);
1da177e4
LT		 1225
1226 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1227 return -EFAULT;
1228 return 0;
1229}
1230
47b01b3a
AC		 1231static int set_config(struct tty_struct *tty, struct r_port *info,
1232 struct rocket_config __user *new_info)
1da177e4
LT		 1233{
1234 struct rocket_config new_serial;
1235
1236 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1237 return -EFAULT;
1238
417b6e0e 1239 mutex_lock(&info->port.mutex);
1da177e4
LT		 1240 if (!capable(CAP_SYS_ADMIN))
1241 {
417b6e0e
AC		 1242 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1243 mutex_unlock(&info->port.mutex);
1da177e4 1244 return -EPERM;
417b6e0e 1245 }
1da177e4 1246 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
47b01b3a 1247 configure_r_port(tty, info, NULL);
49bf7eaf 1248 mutex_unlock(&info->port.mutex);
1da177e4
LT		 1249 return 0;
1250 }
1251
1252 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
44b7d1b3
AC		 1253 info->port.close_delay = new_serial.close_delay;
1254 info->port.closing_wait = new_serial.closing_wait;
1da177e4
LT		 1255
1256 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
47b01b3a 1257 tty->alt_speed = 57600;
1da177e4 1258 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
47b01b3a 1259 tty->alt_speed = 115200;
1da177e4 1260 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
47b01b3a 1261 tty->alt_speed = 230400;
1da177e4 1262 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
47b01b3a 1263 tty->alt_speed = 460800;
417b6e0e 1264 mutex_unlock(&info->port.mutex);
1da177e4 1265
47b01b3a 1266 configure_r_port(tty, info, NULL);
1da177e4
LT		 1267 return 0;
1268}
1269
1270/*
1271 * This function fills in a rocket_ports struct with information
1272 * about what boards/ports are in the system. This info is passed
1273 * to user space. See setrocket.c where the info is used to create
1274 * the /dev/ttyRx ports.
1275 */
1276static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1277{
1278 struct rocket_ports tmp;
1279 int board;
1280
1281 if (!retports)
1282 return -EFAULT;
1283 memset(&tmp, 0, sizeof (tmp));
1284 tmp.tty_major = rocket_driver->major;
1285
1286 for (board = 0; board < 4; board++) {
1287 tmp.rocketModel[board].model = rocketModel[board].model;
1288 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1289 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1290 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1291 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1292 }
1293 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1294 return -EFAULT;
1295 return 0;
1296}
1297
1298static int reset_rm2(struct r_port *info, void __user *arg)
1299{
1300 int reset;
1301
4129a645
AC		 1302 if (!capable(CAP_SYS_ADMIN))
1303 return -EPERM;
1304
1da177e4
LT		 1305 if (copy_from_user(&reset, arg, sizeof (int)))
1306 return -EFAULT;
1307 if (reset)
1308 reset = 1;
1309
1310 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1311 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1312 return -EINVAL;
1313
1314 if (info->ctlp->BusType == isISA)
1315 sModemReset(info->ctlp, info->chan, reset);
1316 else
1317 sPCIModemReset(info->ctlp, info->chan, reset);
1318
1319 return 0;
1320}
1321
1322static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1323{
1324 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1325 return -EFAULT;
1326 return 0;
1327}
1328
1329/* IOCTL call handler into the driver */
6caa76b7 1330static int rp_ioctl(struct tty_struct *tty,
1da177e4
LT		 1331 unsigned int cmd, unsigned long arg)
1332{
c9f19e96 1333 struct r_port *info = tty->driver_data;
1da177e4 1334 void __user *argp = (void __user *)arg;
bdf183aa 1335 int ret = 0;
1da177e4
LT		 1336
1337 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1338 return -ENXIO;
1339
1340 switch (cmd) {
1341 case RCKP_GET_STRUCT:
1342 if (copy_to_user(argp, info, sizeof (struct r_port)))
bdf183aa
AC		 1343 ret = -EFAULT;
1344 break;
1da177e4 1345 case RCKP_GET_CONFIG:
bdf183aa
AC		 1346 ret = get_config(info, argp);
1347 break;
1da177e4 1348 case RCKP_SET_CONFIG:
47b01b3a 1349 ret = set_config(tty, info, argp);
bdf183aa 1350 break;
1da177e4 1351 case RCKP_GET_PORTS:
bdf183aa
AC		 1352 ret = get_ports(info, argp);
1353 break;
1da177e4 1354 case RCKP_RESET_RM2:
bdf183aa
AC		 1355 ret = reset_rm2(info, argp);
1356 break;
1da177e4 1357 case RCKP_GET_VERSION:
bdf183aa
AC		 1358 ret = get_version(info, argp);
1359 break;
1da177e4 1360 default:
bdf183aa 1361 ret = -ENOIOCTLCMD;
1da177e4 1362 }
bdf183aa 1363 return ret;
1da177e4
LT		 1364}
1365
1366static void rp_send_xchar(struct tty_struct *tty, char ch)
1367{
c9f19e96 1368 struct r_port *info = tty->driver_data;
1da177e4
LT		 1369 CHANNEL_t *cp;
1370
1371 if (rocket_paranoia_check(info, "rp_send_xchar"))
1372 return;
1373
1374 cp = &info->channel;
1375 if (sGetTxCnt(cp))
1376 sWriteTxPrioByte(cp, ch);
1377 else
1378 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1379}
1380
1381static void rp_throttle(struct tty_struct *tty)
1382{
c9f19e96 1383 struct r_port *info = tty->driver_data;
1da177e4
LT		 1384
1385#ifdef ROCKET_DEBUG_THROTTLE
1386 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1387 tty->ldisc.chars_in_buffer(tty));
1388#endif
1389
1390 if (rocket_paranoia_check(info, "rp_throttle"))
1391 return;
1392
1da177e4
LT		 1393 if (I_IXOFF(tty))
1394 rp_send_xchar(tty, STOP_CHAR(tty));
1395
1396 sClrRTS(&info->channel);
1397}
1398
1399static void rp_unthrottle(struct tty_struct *tty)
1400{
c9f19e96 1401 struct r_port *info = tty->driver_data;
1da177e4
LT		 1402#ifdef ROCKET_DEBUG_THROTTLE
1403 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1404 tty->ldisc.chars_in_buffer(tty));
1405#endif
1406
1407 if (rocket_paranoia_check(info, "rp_throttle"))
1408 return;
1409
1da177e4
LT		 1410 if (I_IXOFF(tty))
1411 rp_send_xchar(tty, START_CHAR(tty));
1412
1413 sSetRTS(&info->channel);
1414}
1415
1416/*
1417 * ------------------------------------------------------------
1418 * rp_stop() and rp_start()
1419 *
1420 * This routines are called before setting or resetting tty->stopped.
1421 * They enable or disable transmitter interrupts, as necessary.
1422 * ------------------------------------------------------------
1423 */
1424static void rp_stop(struct tty_struct *tty)
1425{
c9f19e96 1426 struct r_port *info = tty->driver_data;
1da177e4
LT		 1427
1428#ifdef ROCKET_DEBUG_FLOW
1429 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1430 info->xmit_cnt, info->xmit_fifo_room);
1431#endif
1432
1433 if (rocket_paranoia_check(info, "rp_stop"))
1434 return;
1435
1436 if (sGetTxCnt(&info->channel))
1437 sDisTransmit(&info->channel);
1438}
1439
1440static void rp_start(struct tty_struct *tty)
1441{
c9f19e96 1442 struct r_port *info = tty->driver_data;
1da177e4
LT		 1443
1444#ifdef ROCKET_DEBUG_FLOW
1445 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1446 info->xmit_cnt, info->xmit_fifo_room);
1447#endif
1448
1449 if (rocket_paranoia_check(info, "rp_stop"))
1450 return;
1451
1452 sEnTransmit(&info->channel);
1453 set_bit((info->aiop * 8) + info->chan,
1454 (void *) &xmit_flags[info->board]);
1455}
1456
1457/*
1458 * rp_wait_until_sent() --- wait until the transmitter is empty
1459 */
1460static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1461{
c9f19e96 1462 struct r_port *info = tty->driver_data;
1da177e4
LT		 1463 CHANNEL_t *cp;
1464 unsigned long orig_jiffies;
1465 int check_time, exit_time;
1466 int txcnt;
1467
1468 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1469 return;
1470
1471 cp = &info->channel;
1472
1473 orig_jiffies = jiffies;
1474#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79 1475 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1da177e4 1476 jiffies);
68562b79 1477 printk(KERN_INFO "cps=%d...\n", info->cps);
1da177e4
LT		 1478#endif
1479 while (1) {
1480 txcnt = sGetTxCnt(cp);
1481 if (!txcnt) {
1482 if (sGetChanStatusLo(cp) & TXSHRMT)
1483 break;
1484 check_time = (HZ / info->cps) / 5;
1485 } else {
1486 check_time = HZ * txcnt / info->cps;
1487 }
1488 if (timeout) {
1489 exit_time = orig_jiffies + timeout - jiffies;
1490 if (exit_time <= 0)
1491 break;
1492 if (exit_time < check_time)
1493 check_time = exit_time;
1494 }
1495 if (check_time == 0)
1496 check_time = 1;
1497#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
68562b79
JS		 1498 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1499 jiffies, check_time);
1da177e4
LT		 1500#endif
1501 msleep_interruptible(jiffies_to_msecs(check_time));
1502 if (signal_pending(current))
1503 break;
1504 }
cc0a8fbb 1505 __set_current_state(TASK_RUNNING);
1da177e4
LT		 1506#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1507 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1508#endif
1509}
1510
1511/*
1512 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1513 */
1514static void rp_hangup(struct tty_struct *tty)
1515{
1516 CHANNEL_t *cp;
c9f19e96 1517 struct r_port *info = tty->driver_data;
417b6e0e 1518 unsigned long flags;
1da177e4
LT		 1519
1520 if (rocket_paranoia_check(info, "rp_hangup"))
1521 return;
1522
1523#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
68562b79 1524 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1da177e4
LT		 1525#endif
1526 rp_flush_buffer(tty);
417b6e0e
AC		 1527 spin_lock_irqsave(&info->port.lock, flags);
1528 if (info->port.flags & ASYNC_CLOSING) {
1529 spin_unlock_irqrestore(&info->port.lock, flags);
1da177e4 1530 return;
417b6e0e 1531 }
e60a1084 1532 if (info->port.count)
1da177e4
LT		 1533 atomic_dec(&rp_num_ports_open);
1534 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
417b6e0e 1535 spin_unlock_irqrestore(&info->port.lock, flags);
1da177e4 1536
fba85e01 1537 tty_port_hangup(&info->port);
1da177e4
LT		 1538
1539 cp = &info->channel;
1540 sDisRxFIFO(cp);
1541 sDisTransmit(cp);
1542 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1543 sDisCTSFlowCtl(cp);
1544 sDisTxSoftFlowCtl(cp);
1545 sClrTxXOFF(cp);
417b6e0e 1546 clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1da177e4 1547
e60a1084 1548 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 1549}
1550
1551/*
1552 * Exception handler - write char routine. The RocketPort driver uses a
1553 * double-buffering strategy, with the twist that if the in-memory CPU
1554 * buffer is empty, and there's space in the transmit FIFO, the
1555 * writing routines will write directly to transmit FIFO.
1556 * Write buffer and counters protected by spinlocks
1557 */
bbbbb96f 1558static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1da177e4 1559{
c9f19e96 1560 struct r_port *info = tty->driver_data;
1da177e4
LT		 1561 CHANNEL_t *cp;
1562 unsigned long flags;
1563
1564 if (rocket_paranoia_check(info, "rp_put_char"))
bbbbb96f 1565 return 0;
1da177e4 1566
69f545ea
MK		 1567 /*
1568 * Grab the port write mutex, locking out other processes that try to
1569 * write to this port
1570 */
1571 mutex_lock(&info->write_mtx);
1da177e4
LT		 1572
1573#ifdef ROCKET_DEBUG_WRITE
68562b79 1574 printk(KERN_INFO "rp_put_char %c...\n", ch);
1da177e4
LT		 1575#endif
1576
1577 spin_lock_irqsave(&info->slock, flags);
1578 cp = &info->channel;
1579
1580 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1581 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1582
1583 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1584 info->xmit_buf[info->xmit_head++] = ch;
1585 info->xmit_head &= XMIT_BUF_SIZE - 1;
1586 info->xmit_cnt++;
1587 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1588 } else {
1589 sOutB(sGetTxRxDataIO(cp), ch);
1590 info->xmit_fifo_room--;
1591 }
1592 spin_unlock_irqrestore(&info->slock, flags);
69f545ea 1593 mutex_unlock(&info->write_mtx);
bbbbb96f 1594 return 1;
1da177e4
LT		 1595}
1596
1597/*
1598 * Exception handler - write routine, called when user app writes to the device.
69f545ea 1599 * A per port write mutex is used to protect from another process writing to
1da177e4
LT		 1600 * this port at the same time. This other process could be running on the other CPU
1601 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1602 * Spinlocks protect the info xmit members.
1603 */
1604static int rp_write(struct tty_struct *tty,
1605 const unsigned char *buf, int count)
1606{
c9f19e96 1607 struct r_port *info = tty->driver_data;
1da177e4
LT		 1608 CHANNEL_t *cp;
1609 const unsigned char *b;
1610 int c, retval = 0;
1611 unsigned long flags;
1612
1613 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1614 return 0;
1615
1e3e8d91
SS		 1616 if (mutex_lock_interruptible(&info->write_mtx))
1617 return -ERESTARTSYS;
1da177e4
LT		 1618
1619#ifdef ROCKET_DEBUG_WRITE
68562b79 1620 printk(KERN_INFO "rp_write %d chars...\n", count);
1da177e4
LT		 1621#endif
1622 cp = &info->channel;
1623
1624 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1625 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1626
1627 /*
1628 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1629 * into FIFO. Use the write queue for temp storage.
1630 */
1631 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1632 c = min(count, info->xmit_fifo_room);
1633 b = buf;
1634
1635 /* Push data into FIFO, 2 bytes at a time */
1636 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1637
1638 /* If there is a byte remaining, write it */
1639 if (c & 1)
1640 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1641
1642 retval += c;
1643 buf += c;
1644 count -= c;
1645
1646 spin_lock_irqsave(&info->slock, flags);
1647 info->xmit_fifo_room -= c;
1648 spin_unlock_irqrestore(&info->slock, flags);
1649 }
1650
1651 /* If count is zero, we wrote it all and are done */
1652 if (!count)
1653 goto end;
1654
1655 /* Write remaining data into the port's xmit_buf */
1656 while (1) {
47b01b3a 1657 /* Hung up ? */
a391ad0f 1658 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1da177e4 1659 goto end;
709107fc
HH		 1660 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1661 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1da177e4
LT		 1662 if (c <= 0)
1663 break;
1664
1665 b = buf;
1666 memcpy(info->xmit_buf + info->xmit_head, b, c);
1667
1668 spin_lock_irqsave(&info->slock, flags);
1669 info->xmit_head =
1670 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1671 info->xmit_cnt += c;
1672 spin_unlock_irqrestore(&info->slock, flags);
1673
1674 buf += c;
1675 count -= c;
1676 retval += c;
1677 }
1678
1679 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1680 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1681
1682end:
1683 if (info->xmit_cnt < WAKEUP_CHARS) {
1684 tty_wakeup(tty);
1da177e4
LT		 1685#ifdef ROCKETPORT_HAVE_POLL_WAIT
1686 wake_up_interruptible(&tty->poll_wait);
1687#endif
1688 }
69f545ea 1689 mutex_unlock(&info->write_mtx);
1da177e4
LT		 1690 return retval;
1691}
1692
1693/*
1694 * Return the number of characters that can be sent. We estimate
1695 * only using the in-memory transmit buffer only, and ignore the
1696 * potential space in the transmit FIFO.
1697 */
1698static int rp_write_room(struct tty_struct *tty)
1699{
c9f19e96 1700 struct r_port *info = tty->driver_data;
1da177e4
LT		 1701 int ret;
1702
1703 if (rocket_paranoia_check(info, "rp_write_room"))
1704 return 0;
1705
1706 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1707 if (ret < 0)
1708 ret = 0;
1709#ifdef ROCKET_DEBUG_WRITE
68562b79 1710 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1da177e4
LT		 1711#endif
1712 return ret;
1713}
1714
1715/*
1716 * Return the number of characters in the buffer. Again, this only
1717 * counts those characters in the in-memory transmit buffer.
1718 */
1719static int rp_chars_in_buffer(struct tty_struct *tty)
1720{
c9f19e96 1721 struct r_port *info = tty->driver_data;
1da177e4
LT		 1722
1723 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1724 return 0;
1725
1da177e4 1726#ifdef ROCKET_DEBUG_WRITE
68562b79 1727 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1da177e4
LT		 1728#endif
1729 return info->xmit_cnt;
1730}
1731
1732/*
1733 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1734 * r_port struct for the port. Note that spinlock are used to protect info members,
1735 * do not call this function if the spinlock is already held.
1736 */
1737static void rp_flush_buffer(struct tty_struct *tty)
1738{
c9f19e96 1739 struct r_port *info = tty->driver_data;
1da177e4
LT		 1740 CHANNEL_t *cp;
1741 unsigned long flags;
1742
1743 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1744 return;
1745
1746 spin_lock_irqsave(&info->slock, flags);
1747 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1748 spin_unlock_irqrestore(&info->slock, flags);
1749
1da177e4
LT		 1750#ifdef ROCKETPORT_HAVE_POLL_WAIT
1751 wake_up_interruptible(&tty->poll_wait);
1752#endif
1753 tty_wakeup(tty);
1754
1755 cp = &info->channel;
1756 sFlushTxFIFO(cp);
1757}
1758
1759#ifdef CONFIG_PCI
1760
de88b340 1761static struct pci_device_id __used rocket_pci_ids[] = {
8d5916d3
JS		 1762 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1763 { }
1764};
1765MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1766
1da177e4
LT		 1767/*
1768 * Called when a PCI card is found. Retrieves and stores model information,
1769 * init's aiopic and serial port hardware.
1770 * Inputs: i is the board number (0-n)
1771 */
f15313bf 1772static __init int register_PCI(int i, struct pci_dev *dev)
1da177e4
LT		 1773{
1774 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1775 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1da177e4
LT		 1776 CONTROLLER_t *ctlp;
1777
1778 int fast_clock = 0;
1779 int altChanRingIndicator = 0;
1780 int ports_per_aiop = 8;
1da177e4
LT		 1781 WordIO_t ConfigIO = 0;
1782 ByteIO_t UPCIRingInd = 0;
1783
1784 if (!dev || pci_enable_device(dev))
1785 return 0;
1786
1787 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1da177e4
LT		 1788
1789 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1790 rocketModel[i].loadrm2 = 0;
1791 rocketModel[i].startingPortNumber = nextLineNumber;
1792
1793 /* Depending on the model, set up some config variables */
1794 switch (dev->device) {
1795 case PCI_DEVICE_ID_RP4QUAD:
1da177e4
LT		 1796 max_num_aiops = 1;
1797 ports_per_aiop = 4;
1798 rocketModel[i].model = MODEL_RP4QUAD;
1799 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1800 rocketModel[i].numPorts = 4;
1801 break;
1802 case PCI_DEVICE_ID_RP8OCTA:
1da177e4
LT		 1803 max_num_aiops = 1;
1804 rocketModel[i].model = MODEL_RP8OCTA;
1805 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1806 rocketModel[i].numPorts = 8;
1807 break;
1808 case PCI_DEVICE_ID_URP8OCTA:
1da177e4
LT		 1809 max_num_aiops = 1;
1810 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1811 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1812 rocketModel[i].numPorts = 8;
1813 break;
1814 case PCI_DEVICE_ID_RP8INTF:
1da177e4
LT		 1815 max_num_aiops = 1;
1816 rocketModel[i].model = MODEL_RP8INTF;
1817 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1818 rocketModel[i].numPorts = 8;
1819 break;
1820 case PCI_DEVICE_ID_URP8INTF:
1da177e4
LT		 1821 max_num_aiops = 1;
1822 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1823 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1824 rocketModel[i].numPorts = 8;
1825 break;
1826 case PCI_DEVICE_ID_RP8J:
1da177e4
LT		 1827 max_num_aiops = 1;
1828 rocketModel[i].model = MODEL_RP8J;
1829 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1830 rocketModel[i].numPorts = 8;
1831 break;
1832 case PCI_DEVICE_ID_RP4J:
1da177e4
LT		 1833 max_num_aiops = 1;
1834 ports_per_aiop = 4;
1835 rocketModel[i].model = MODEL_RP4J;
1836 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1837 rocketModel[i].numPorts = 4;
1838 break;
1839 case PCI_DEVICE_ID_RP8SNI:
1da177e4
LT		 1840 max_num_aiops = 1;
1841 rocketModel[i].model = MODEL_RP8SNI;
1842 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1843 rocketModel[i].numPorts = 8;
1844 break;
1845 case PCI_DEVICE_ID_RP16SNI:
1da177e4
LT		 1846 max_num_aiops = 2;
1847 rocketModel[i].model = MODEL_RP16SNI;
1848 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1849 rocketModel[i].numPorts = 16;
1850 break;
1851 case PCI_DEVICE_ID_RP16INTF:
1da177e4
LT		 1852 max_num_aiops = 2;
1853 rocketModel[i].model = MODEL_RP16INTF;
1854 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1855 rocketModel[i].numPorts = 16;
1856 break;
1857 case PCI_DEVICE_ID_URP16INTF:
1da177e4
LT		 1858 max_num_aiops = 2;
1859 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1860 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1861 rocketModel[i].numPorts = 16;
1862 break;
1863 case PCI_DEVICE_ID_CRP16INTF:
1da177e4
LT		 1864 max_num_aiops = 2;
1865 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1866 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1867 rocketModel[i].numPorts = 16;
1868 break;
1869 case PCI_DEVICE_ID_RP32INTF:
1da177e4
LT		 1870 max_num_aiops = 4;
1871 rocketModel[i].model = MODEL_RP32INTF;
1872 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1873 rocketModel[i].numPorts = 32;
1874 break;
1875 case PCI_DEVICE_ID_URP32INTF:
1da177e4
LT		 1876 max_num_aiops = 4;
1877 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1878 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1879 rocketModel[i].numPorts = 32;
1880 break;
1881 case PCI_DEVICE_ID_RPP4:
1da177e4
LT		 1882 max_num_aiops = 1;
1883 ports_per_aiop = 4;
1884 altChanRingIndicator++;
1885 fast_clock++;
1886 rocketModel[i].model = MODEL_RPP4;
1887 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1888 rocketModel[i].numPorts = 4;
1889 break;
1890 case PCI_DEVICE_ID_RPP8:
1da177e4
LT		 1891 max_num_aiops = 2;
1892 ports_per_aiop = 4;
1893 altChanRingIndicator++;
1894 fast_clock++;
1895 rocketModel[i].model = MODEL_RPP8;
1896 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1897 rocketModel[i].numPorts = 8;
1898 break;
1899 case PCI_DEVICE_ID_RP2_232:
1da177e4
LT		 1900 max_num_aiops = 1;
1901 ports_per_aiop = 2;
1902 altChanRingIndicator++;
1903 fast_clock++;
1904 rocketModel[i].model = MODEL_RP2_232;
1905 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
1906 rocketModel[i].numPorts = 2;
1907 break;
1908 case PCI_DEVICE_ID_RP2_422:
1da177e4
LT		 1909 max_num_aiops = 1;
1910 ports_per_aiop = 2;
1911 altChanRingIndicator++;
1912 fast_clock++;
1913 rocketModel[i].model = MODEL_RP2_422;
1914 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
1915 rocketModel[i].numPorts = 2;
1916 break;
1917 case PCI_DEVICE_ID_RP6M:
1918
1919 max_num_aiops = 1;
1920 ports_per_aiop = 6;
1da177e4 1921
57fedc7a
JS		 1922 /* If revision is 1, the rocketmodem flash must be loaded.
1923 * If it is 2 it is a "socketed" version. */
1924 if (dev->revision == 1) {
1da177e4
LT		 1925 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1926 rocketModel[i].loadrm2 = 1;
1927 } else {
1928 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1929 }
1930
1931 rocketModel[i].model = MODEL_RP6M;
1932 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
1933 rocketModel[i].numPorts = 6;
1934 break;
1935 case PCI_DEVICE_ID_RP4M:
1936 max_num_aiops = 1;
1937 ports_per_aiop = 4;
57fedc7a 1938 if (dev->revision == 1) {
1da177e4
LT		 1939 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1940 rocketModel[i].loadrm2 = 1;
1941 } else {
1942 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1943 }
1944
1945 rocketModel[i].model = MODEL_RP4M;
1946 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
1947 rocketModel[i].numPorts = 4;
1948 break;
1949 default:
1da177e4
LT		 1950 max_num_aiops = 0;
1951 break;
1952 }
1953
1954 /*
1955 * Check for UPCI boards.
1956 */
1957
1958 switch (dev->device) {
1959 case PCI_DEVICE_ID_URP32INTF:
1960 case PCI_DEVICE_ID_URP8INTF:
1961 case PCI_DEVICE_ID_URP16INTF:
1962 case PCI_DEVICE_ID_CRP16INTF:
1963 case PCI_DEVICE_ID_URP8OCTA:
1964 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1965 ConfigIO = pci_resource_start(dev, 1);
1966 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
1967 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1968
1969 /*
1970 * Check for octa or quad cable.
1971 */
1972 if (!
1973 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
1974 PCI_GPIO_CTRL_8PORT)) {
1da177e4
LT		 1975 ports_per_aiop = 4;
1976 rocketModel[i].numPorts = 4;
1977 }
1978 }
1979 break;
1980 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
1da177e4
LT		 1981 max_num_aiops = 1;
1982 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
1983 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
1984 rocketModel[i].numPorts = 8;
1985 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1986 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1987 ConfigIO = pci_resource_start(dev, 1);
1988 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
1989 break;
1990 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
1da177e4
LT		 1991 max_num_aiops = 1;
1992 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
1993 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
1994 rocketModel[i].numPorts = 4;
1995 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1996 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1997 ConfigIO = pci_resource_start(dev, 1);
1998 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
1999 break;
2000 default:
2001 break;
2002 }
2003
1da177e4
LT		 2004 if (fast_clock) {
2005 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2006 rp_baud_base[i] = 921600;
2007 } else {
2008 /*
2009 * If support_low_speed is set, use the slow clock
2010 * prescale, which supports 50 bps
2011 */
2012 if (support_low_speed) {
2013 /* mod 9 (divide by 10) prescale */
2014 sClockPrescale = 0x19;
2015 rp_baud_base[i] = 230400;
2016 } else {
25985edc 2017 /* mod 4 (divide by 5) prescale */
1da177e4
LT		 2018 sClockPrescale = 0x14;
2019 rp_baud_base[i] = 460800;
2020 }
2021 }
2022
2023 for (aiop = 0; aiop < max_num_aiops; aiop++)
2024 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2025 ctlp = sCtlNumToCtlPtr(i);
2026 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2027 for (aiop = 0; aiop < max_num_aiops; aiop++)
2028 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2029
68562b79
JS		 2030 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2031 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2032 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2033 rocketModel[i].startingPortNumber,
2034 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
1da177e4
LT		 2035
2036 if (num_aiops <= 0) {
2037 rcktpt_io_addr[i] = 0;
2038 return (0);
2039 }
2040 is_PCI[i] = 1;
2041
2042 /* Reset the AIOPIC, init the serial ports */
2043 for (aiop = 0; aiop < num_aiops; aiop++) {
2044 sResetAiopByNum(ctlp, aiop);
2045 num_chan = ports_per_aiop;
2046 for (chan = 0; chan < num_chan; chan++)
2047 init_r_port(i, aiop, chan, dev);
2048 }
2049
2050 /* Rocket modems must be reset */
2051 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2052 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2053 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2054 num_chan = ports_per_aiop;
2055 for (chan = 0; chan < num_chan; chan++)
2056 sPCIModemReset(ctlp, chan, 1);
48a67f5d 2057 msleep(500);
1da177e4
LT		 2058 for (chan = 0; chan < num_chan; chan++)
2059 sPCIModemReset(ctlp, chan, 0);
48a67f5d 2060 msleep(500);
1da177e4
LT		 2061 rmSpeakerReset(ctlp, rocketModel[i].model);
2062 }
2063 return (1);
2064}
2065
2066/*
2067 * Probes for PCI cards, inits them if found
2068 * Input: board_found = number of ISA boards already found, or the
2069 * starting board number
2070 * Returns: Number of PCI boards found
2071 */
2072static int __init init_PCI(int boards_found)
2073{
2074 struct pci_dev *dev = NULL;
2075 int count = 0;
2076
2077 /* Work through the PCI device list, pulling out ours */
606d099c 2078 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
1da177e4
LT		 2079 if (register_PCI(count + boards_found, dev))
2080 count++;
2081 }
2082 return (count);
2083}
2084
2085#endif /* CONFIG_PCI */
2086
2087/*
2088 * Probes for ISA cards
2089 * Input: i = the board number to look for
2090 * Returns: 1 if board found, 0 else
2091 */
2092static int __init init_ISA(int i)
2093{
2094 int num_aiops, num_chan = 0, total_num_chan = 0;
2095 int aiop, chan;
2096 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2097 CONTROLLER_t *ctlp;
2098 char *type_string;
2099
2100 /* If io_addr is zero, no board configured */
2101 if (rcktpt_io_addr[i] == 0)
2102 return (0);
2103
2104 /* Reserve the IO region */
2105 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
68562b79
JS		 2106 printk(KERN_ERR "Unable to reserve IO region for configured "
2107 "ISA RocketPort at address 0x%lx, board not "
2108 "installed...\n", rcktpt_io_addr[i]);
1da177e4
LT		 2109 rcktpt_io_addr[i] = 0;
2110 return (0);
2111 }
2112
2113 ctlp = sCtlNumToCtlPtr(i);
2114
2115 ctlp->boardType = rcktpt_type[i];
2116
2117 switch (rcktpt_type[i]) {
2118 case ROCKET_TYPE_PC104:
2119 type_string = "(PC104)";
2120 break;
2121 case ROCKET_TYPE_MODEM:
2122 type_string = "(RocketModem)";
2123 break;
2124 case ROCKET_TYPE_MODEMII:
2125 type_string = "(RocketModem II)";
2126 break;
2127 default:
2128 type_string = "";
2129 break;
2130 }
2131
2132 /*
2133 * If support_low_speed is set, use the slow clock prescale,
2134 * which supports 50 bps
2135 */
2136 if (support_low_speed) {
2137 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2138 rp_baud_base[i] = 230400;
2139 } else {
25985edc 2140 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
1da177e4
LT		 2141 rp_baud_base[i] = 460800;
2142 }
2143
2144 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2145 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2146
2147 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2148
2149 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2150 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2151 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2152 }
2153
2154 /* If something went wrong initing the AIOP's release the ISA IO memory */
2155 if (num_aiops <= 0) {
2156 release_region(rcktpt_io_addr[i], 64);
2157 rcktpt_io_addr[i] = 0;
2158 return (0);
2159 }
2160
2161 rocketModel[i].startingPortNumber = nextLineNumber;
2162
2163 for (aiop = 0; aiop < num_aiops; aiop++) {
2164 sResetAiopByNum(ctlp, aiop);
2165 sEnAiop(ctlp, aiop);
2166 num_chan = sGetAiopNumChan(ctlp, aiop);
2167 total_num_chan += num_chan;
2168 for (chan = 0; chan < num_chan; chan++)
2169 init_r_port(i, aiop, chan, NULL);
2170 }
2171 is_PCI[i] = 0;
2172 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2173 num_chan = sGetAiopNumChan(ctlp, 0);
2174 total_num_chan = num_chan;
2175 for (chan = 0; chan < num_chan; chan++)
2176 sModemReset(ctlp, chan, 1);
48a67f5d 2177 msleep(500);
1da177e4
LT		 2178 for (chan = 0; chan < num_chan; chan++)
2179 sModemReset(ctlp, chan, 0);
48a67f5d 2180 msleep(500);
1da177e4
LT		 2181 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2182 } else {
2183 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2184 }
2185 rocketModel[i].numPorts = total_num_chan;
2186 rocketModel[i].model = MODEL_ISA;
2187
2188 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2189 i, rcktpt_io_addr[i], num_aiops, type_string);
2190
2191 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2192 rocketModel[i].modelString,
2193 rocketModel[i].startingPortNumber,
2194 rocketModel[i].startingPortNumber +
2195 rocketModel[i].numPorts - 1);
2196
2197 return (1);
2198}
2199
b68e31d0 2200static const struct tty_operations rocket_ops = {
1da177e4
LT		 2201 .open = rp_open,
2202 .close = rp_close,
2203 .write = rp_write,
2204 .put_char = rp_put_char,
2205 .write_room = rp_write_room,
2206 .chars_in_buffer = rp_chars_in_buffer,
2207 .flush_buffer = rp_flush_buffer,
2208 .ioctl = rp_ioctl,
2209 .throttle = rp_throttle,
2210 .unthrottle = rp_unthrottle,
2211 .set_termios = rp_set_termios,
2212 .stop = rp_stop,
2213 .start = rp_start,
2214 .hangup = rp_hangup,
2215 .break_ctl = rp_break,
2216 .send_xchar = rp_send_xchar,
2217 .wait_until_sent = rp_wait_until_sent,
2218 .tiocmget = rp_tiocmget,
2219 .tiocmset = rp_tiocmset,
2220};
2221
31f35939
AC		 2222static const struct tty_port_operations rocket_port_ops = {
2223 .carrier_raised = carrier_raised,
fcc8ac18 2224 .dtr_rts = dtr_rts,
31f35939
AC		 2225};
2226
1da177e4
LT		 2227/*
2228 * The module "startup" routine; it's run when the module is loaded.
2229 */
d269cdd0 2230static int __init rp_init(void)
1da177e4 2231{
4384a3fa 2232 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
1da177e4
LT		 2233
2234 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2235 ROCKET_VERSION, ROCKET_DATE);
2236
2237 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2238 if (!rocket_driver)
4384a3fa 2239 goto err;
1da177e4 2240
1da177e4
LT		 2241 /*
2242 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2243 * zero, use the default controller IO address of board1 + 0x40.
2244 */
2245 if (board1) {
2246 if (controller == 0)
2247 controller = board1 + 0x40;
2248 } else {
2249 controller = 0; /* Used as a flag, meaning no ISA boards */
2250 }
2251
2252 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2253 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
4384a3fa
JS		 2254 printk(KERN_ERR "Unable to reserve IO region for first "
2255 "configured ISA RocketPort controller 0x%lx. "
2256 "Driver exiting\n", controller);
2257 ret = -EBUSY;
2258 goto err_tty;
1da177e4
LT		 2259 }
2260
2261 /* Store ISA variable retrieved from command line or .conf file. */
2262 rcktpt_io_addr[0] = board1;
2263 rcktpt_io_addr[1] = board2;
2264 rcktpt_io_addr[2] = board3;
2265 rcktpt_io_addr[3] = board4;
2266
2267 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2268 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2269 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2270 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2271 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2272 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2273 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2274 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2275
2276 /*
2277 * Set up the tty driver structure and then register this
2278 * driver with the tty layer.
2279 */
2280
331b8319 2281 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
1da177e4
LT		 2282 rocket_driver->name = "ttyR";
2283 rocket_driver->driver_name = "Comtrol RocketPort";
2284 rocket_driver->major = TTY_ROCKET_MAJOR;
2285 rocket_driver->minor_start = 0;
2286 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2287 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2288 rocket_driver->init_termios = tty_std_termios;
2289 rocket_driver->init_termios.c_cflag =
2290 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
606d099c
AC		 2291 rocket_driver->init_termios.c_ispeed = 9600;
2292 rocket_driver->init_termios.c_ospeed = 9600;
1da177e4 2293#ifdef ROCKET_SOFT_FLOW
ac6aec2f 2294 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
1da177e4
LT		 2295#endif
2296 tty_set_operations(rocket_driver, &rocket_ops);
2297
4384a3fa
JS		 2298 ret = tty_register_driver(rocket_driver);
2299 if (ret < 0) {
2300 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
713efa9a 2301 goto err_controller;
1da177e4
LT		 2302 }
2303
2304#ifdef ROCKET_DEBUG_OPEN
2305 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2306#endif
2307
2308 /*
2309 * OK, let's probe each of the controllers looking for boards. Any boards found
2310 * will be initialized here.
2311 */
2312 isa_boards_found = 0;
2313 pci_boards_found = 0;
2314
2315 for (i = 0; i < NUM_BOARDS; i++) {
2316 if (init_ISA(i))
2317 isa_boards_found++;
2318 }
2319
2320#ifdef CONFIG_PCI
2321 if (isa_boards_found < NUM_BOARDS)
2322 pci_boards_found = init_PCI(isa_boards_found);
2323#endif
2324
2325 max_board = pci_boards_found + isa_boards_found;
2326
2327 if (max_board == 0) {
4384a3fa
JS		 2328 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2329 ret = -ENXIO;
2330 goto err_ttyu;
1da177e4
LT		 2331 }
2332
2333 return 0;
4384a3fa
JS		 2334err_ttyu:
2335 tty_unregister_driver(rocket_driver);
713efa9a
DC		 2336err_controller:
2337 if (controller)
2338 release_region(controller, 4);
4384a3fa
JS		 2339err_tty:
2340 put_tty_driver(rocket_driver);
2341err:
2342 return ret;
1da177e4
LT		 2343}
2344
1da177e4
LT		 2345
2346static void rp_cleanup_module(void)
2347{
2348 int retval;
2349 int i;
2350
2351 del_timer_sync(&rocket_timer);
2352
2353 retval = tty_unregister_driver(rocket_driver);
2354 if (retval)
68562b79 2355 printk(KERN_ERR "Error %d while trying to unregister "
1da177e4 2356 "rocketport driver\n", -retval);
1da177e4 2357
735d5661 2358 for (i = 0; i < MAX_RP_PORTS; i++)
ac6aec2f
JS		 2359 if (rp_table[i]) {
2360 tty_unregister_device(rocket_driver, i);
191c5f10 2361 tty_port_destroy(&rp_table[i]->port);
ac6aec2f
JS		 2362 kfree(rp_table[i]);
2363 }
2364
2365 put_tty_driver(rocket_driver);
1da177e4
LT		 2366
2367 for (i = 0; i < NUM_BOARDS; i++) {
2368 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2369 continue;
2370 release_region(rcktpt_io_addr[i], 64);
2371 }
2372 if (controller)
2373 release_region(controller, 4);
2374}
1da177e4 2375
1da177e4
LT		 2376/***************************************************************************
2377Function: sInitController
2378Purpose: Initialization of controller global registers and controller
2379 structure.
2380Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2381 IRQNum,Frequency,PeriodicOnly)
2382 CONTROLLER_T *CtlP; Ptr to controller structure
2383 int CtlNum; Controller number
2384 ByteIO_t MudbacIO; Mudbac base I/O address.
2385 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2386 This list must be in the order the AIOPs will be found on the
2387 controller. Once an AIOP in the list is not found, it is
2388 assumed that there are no more AIOPs on the controller.
2389 int AiopIOListSize; Number of addresses in AiopIOList
2390 int IRQNum; Interrupt Request number. Can be any of the following:
2391 0: Disable global interrupts
2392 3: IRQ 3
2393 4: IRQ 4
2394 5: IRQ 5
2395 9: IRQ 9
2396 10: IRQ 10
2397 11: IRQ 11
2398 12: IRQ 12
2399 15: IRQ 15
2400 Byte_t Frequency: A flag identifying the frequency
2401 of the periodic interrupt, can be any one of the following:
2402 FREQ_DIS - periodic interrupt disabled
2403 FREQ_137HZ - 137 Hertz
2404 FREQ_69HZ - 69 Hertz
2405 FREQ_34HZ - 34 Hertz
2406 FREQ_17HZ - 17 Hertz
2407 FREQ_9HZ - 9 Hertz
2408 FREQ_4HZ - 4 Hertz
2409 If IRQNum is set to 0 the Frequency parameter is
2410 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2411 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2412 interrupt are to be blocked.
f15313bf 2413 0 is both the periodic interrupt and
1da177e4
LT		 2414 other channel interrupts are allowed.
2415 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2416 overidden, it is forced to a value of 0.
1da177e4
LT		 2417Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2418 initialization failed.
2419
2420Comments:
2421 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2422 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2423
2424 If interrupts are to be completely disabled set IRQNum to 0.
2425
f15313bf 2426 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2427 invalid combination.
2428
2429 This function performs initialization of global interrupt modes,
2430 but it does not actually enable global interrupts. To enable
2431 and disable global interrupts use functions sEnGlobalInt() and
2432 sDisGlobalInt(). Enabling of global interrupts is normally not
2433 done until all other initializations are complete.
2434
2435 Even if interrupts are globally enabled, they must also be
2436 individually enabled for each channel that is to generate
2437 interrupts.
2438
2439Warnings: No range checking on any of the parameters is done.
2440
2441 No context switches are allowed while executing this function.
2442
2443 After this function all AIOPs on the controller are disabled,
2444 they can be enabled with sEnAiop().
2445*/
f15313bf
AB		 2446static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2447 ByteIO_t * AiopIOList, int AiopIOListSize,
2448 int IRQNum, Byte_t Frequency, int PeriodicOnly)
1da177e4
LT		 2449{
2450 int i;
2451 ByteIO_t io;
2452 int done;
2453
2454 CtlP->AiopIntrBits = aiop_intr_bits;
2455 CtlP->AltChanRingIndicator = 0;
2456 CtlP->CtlNum = CtlNum;
2457 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2458 CtlP->BusType = isISA;
2459 CtlP->MBaseIO = MudbacIO;
2460 CtlP->MReg1IO = MudbacIO + 1;
2461 CtlP->MReg2IO = MudbacIO + 2;
2462 CtlP->MReg3IO = MudbacIO + 3;
2463#if 1
2464 CtlP->MReg2 = 0; /* interrupt disable */
2465 CtlP->MReg3 = 0; /* no periodic interrupts */
2466#else
2467 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2468 CtlP->MReg2 = 0; /* interrupt disable */
2469 CtlP->MReg3 = 0; /* no periodic interrupts */
2470 } else {
2471 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2472 CtlP->MReg3 = Frequency; /* set frequency */
2473 if (PeriodicOnly) { /* periodic interrupt only */
2474 CtlP->MReg3 |= PERIODIC_ONLY;
2475 }
2476 }
2477#endif
2478 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2479 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2480 sControllerEOI(CtlP); /* clear EOI if warm init */
2481 /* Init AIOPs */
2482 CtlP->NumAiop = 0;
2483 for (i = done = 0; i < AiopIOListSize; i++) {
2484 io = AiopIOList[i];
2485 CtlP->AiopIO[i] = (WordIO_t) io;
2486 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2487 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2488 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2489 if (done)
2490 continue;
2491 sEnAiop(CtlP, i); /* enable the AIOP */
2492 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2493 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2494 done = 1; /* done looking for AIOPs */
2495 else {
2496 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2497 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2498 sOutB(io + _INDX_DATA, sClockPrescale);
2499 CtlP->NumAiop++; /* bump count of AIOPs */
2500 }
2501 sDisAiop(CtlP, i); /* disable AIOP */
2502 }
2503
2504 if (CtlP->NumAiop == 0)
2505 return (-1);
2506 else
2507 return (CtlP->NumAiop);
2508}
2509
2510/***************************************************************************
2511Function: sPCIInitController
2512Purpose: Initialization of controller global registers and controller
2513 structure.
2514Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2515 IRQNum,Frequency,PeriodicOnly)
2516 CONTROLLER_T *CtlP; Ptr to controller structure
2517 int CtlNum; Controller number
2518 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2519 This list must be in the order the AIOPs will be found on the
2520 controller. Once an AIOP in the list is not found, it is
2521 assumed that there are no more AIOPs on the controller.
2522 int AiopIOListSize; Number of addresses in AiopIOList
2523 int IRQNum; Interrupt Request number. Can be any of the following:
2524 0: Disable global interrupts
2525 3: IRQ 3
2526 4: IRQ 4
2527 5: IRQ 5
2528 9: IRQ 9
2529 10: IRQ 10
2530 11: IRQ 11
2531 12: IRQ 12
2532 15: IRQ 15
2533 Byte_t Frequency: A flag identifying the frequency
2534 of the periodic interrupt, can be any one of the following:
2535 FREQ_DIS - periodic interrupt disabled
2536 FREQ_137HZ - 137 Hertz
2537 FREQ_69HZ - 69 Hertz
2538 FREQ_34HZ - 34 Hertz
2539 FREQ_17HZ - 17 Hertz
2540 FREQ_9HZ - 9 Hertz
2541 FREQ_4HZ - 4 Hertz
2542 If IRQNum is set to 0 the Frequency parameter is
2543 overidden, it is forced to a value of FREQ_DIS.
f15313bf 2544 int PeriodicOnly: 1 if all interrupts except the periodic
1da177e4 2545 interrupt are to be blocked.
f15313bf 2546 0 is both the periodic interrupt and
1da177e4
LT		 2547 other channel interrupts are allowed.
2548 If IRQNum is set to 0 the PeriodicOnly parameter is
f15313bf 2549 overidden, it is forced to a value of 0.
1da177e4
LT		 2550Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2551 initialization failed.
2552
2553Comments:
2554 If periodic interrupts are to be disabled but AIOP interrupts
f15313bf 2555 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1da177e4
LT		 2556
2557 If interrupts are to be completely disabled set IRQNum to 0.
2558
f15313bf 2559 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1da177e4
LT		 2560 invalid combination.
2561
2562 This function performs initialization of global interrupt modes,
2563 but it does not actually enable global interrupts. To enable
2564 and disable global interrupts use functions sEnGlobalInt() and
2565 sDisGlobalInt(). Enabling of global interrupts is normally not
2566 done until all other initializations are complete.
2567
2568 Even if interrupts are globally enabled, they must also be
2569 individually enabled for each channel that is to generate
2570 interrupts.
2571
2572Warnings: No range checking on any of the parameters is done.
2573
2574 No context switches are allowed while executing this function.
2575
2576 After this function all AIOPs on the controller are disabled,
2577 they can be enabled with sEnAiop().
2578*/
f15313bf
AB		 2579static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2580 ByteIO_t * AiopIOList, int AiopIOListSize,
2581 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2582 int PeriodicOnly, int altChanRingIndicator,
2583 int UPCIRingInd)
1da177e4
LT		 2584{
2585 int i;
2586 ByteIO_t io;
2587
2588 CtlP->AltChanRingIndicator = altChanRingIndicator;
2589 CtlP->UPCIRingInd = UPCIRingInd;
2590 CtlP->CtlNum = CtlNum;
2591 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2592 CtlP->BusType = isPCI; /* controller release 1 */
2593
2594 if (ConfigIO) {
2595 CtlP->isUPCI = 1;
2596 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2597 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2598 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2599 } else {
2600 CtlP->isUPCI = 0;
2601 CtlP->PCIIO =
2602 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2603 CtlP->AiopIntrBits = aiop_intr_bits;
2604 }
2605
2606 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2607 /* Init AIOPs */
2608 CtlP->NumAiop = 0;
2609 for (i = 0; i < AiopIOListSize; i++) {
2610 io = AiopIOList[i];
2611 CtlP->AiopIO[i] = (WordIO_t) io;
2612 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2613
2614 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2615 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2616 break; /* done looking for AIOPs */
2617
2618 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2619 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2620 sOutB(io + _INDX_DATA, sClockPrescale);
2621 CtlP->NumAiop++; /* bump count of AIOPs */
2622 }
2623
2624 if (CtlP->NumAiop == 0)
2625 return (-1);
2626 else
2627 return (CtlP->NumAiop);
2628}
2629
2630/***************************************************************************
2631Function: sReadAiopID
2632Purpose: Read the AIOP idenfication number directly from an AIOP.
2633Call: sReadAiopID(io)
2634 ByteIO_t io: AIOP base I/O address
2635Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2636 is replace by an identifying number.
2637 Flag AIOPID_NULL if no valid AIOP is found
2638Warnings: No context switches are allowed while executing this function.
2639
2640*/
f15313bf 2641static int sReadAiopID(ByteIO_t io)
1da177e4
LT		 2642{
2643 Byte_t AiopID; /* ID byte from AIOP */
2644
2645 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2646 sOutB(io + _CMD_REG, 0x0);
2647 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2648 if (AiopID == 0x06)
2649 return (1);
2650 else /* AIOP does not exist */
2651 return (-1);
2652}
2653
2654/***************************************************************************
2655Function: sReadAiopNumChan
2656Purpose: Read the number of channels available in an AIOP directly from
2657 an AIOP.
2658Call: sReadAiopNumChan(io)
2659 WordIO_t io: AIOP base I/O address
2660Return: int: The number of channels available
2661Comments: The number of channels is determined by write/reads from identical
2662 offsets within the SRAM address spaces for channels 0 and 4.
2663 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2664 AIOP, otherwise it is an 8 channel.
2665Warnings: No context switches are allowed while executing this function.
2666*/
f15313bf 2667static int sReadAiopNumChan(WordIO_t io)
1da177e4
LT		 2668{
2669 Word_t x;
2670 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2671
2672 /* write to chan 0 SRAM */
457fb605 2673 out32((DWordIO_t) io + _INDX_ADDR, R);
1da177e4
LT		 2674 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2675 x = sInW(io + _INDX_DATA);
2676 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2677 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2678 return (8);
2679 else
2680 return (4);
2681}
2682
2683/***************************************************************************
2684Function: sInitChan
2685Purpose: Initialization of a channel and channel structure
2686Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2687 CONTROLLER_T *CtlP; Ptr to controller structure
2688 CHANNEL_T *ChP; Ptr to channel structure
2689 int AiopNum; AIOP number within controller
2690 int ChanNum; Channel number within AIOP
f15313bf 2691Return: int: 1 if initialization succeeded, 0 if it fails because channel
1da177e4
LT		 2692 number exceeds number of channels available in AIOP.
2693Comments: This function must be called before a channel can be used.
2694Warnings: No range checking on any of the parameters is done.
2695
2696 No context switches are allowed while executing this function.
2697*/
f15313bf
AB		 2698static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2699 int ChanNum)
1da177e4
LT		 2700{
2701 int i;
2702 WordIO_t AiopIO;
2703 WordIO_t ChIOOff;
2704 Byte_t *ChR;
2705 Word_t ChOff;
2706 static Byte_t R[4];
2707 int brd9600;
2708
2709 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
f15313bf 2710 return 0; /* exceeds num chans in AIOP */
1da177e4
LT		 2711
2712 /* Channel, AIOP, and controller identifiers */
2713 ChP->CtlP = CtlP;
2714 ChP->ChanID = CtlP->AiopID[AiopNum];
2715 ChP->AiopNum = AiopNum;
2716 ChP->ChanNum = ChanNum;
2717
2718 /* Global direct addresses */
2719 AiopIO = CtlP->AiopIO[AiopNum];
2720 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2721 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2722 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2723 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2724 ChP->IndexData = AiopIO + _INDX_DATA;
2725
2726 /* Channel direct addresses */
2727 ChIOOff = AiopIO + ChP->ChanNum * 2;
2728 ChP->TxRxData = ChIOOff + _TD0;
2729 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2730 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2731 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2732
2733 /* Initialize the channel from the RData array */
2734 for (i = 0; i < RDATASIZE; i += 4) {
2735 R[0] = RData[i];
2736 R[1] = RData[i + 1] + 0x10 * ChanNum;
2737 R[2] = RData[i + 2];
2738 R[3] = RData[i + 3];
457fb605 2739 out32(ChP->IndexAddr, R);
1da177e4
LT		 2740 }
2741
2742 ChR = ChP->R;
2743 for (i = 0; i < RREGDATASIZE; i += 4) {
2744 ChR[i] = RRegData[i];
2745 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2746 ChR[i + 2] = RRegData[i + 2];
2747 ChR[i + 3] = RRegData[i + 3];
2748 }
2749
2750 /* Indexed registers */
2751 ChOff = (Word_t) ChanNum *0x1000;
2752
2753 if (sClockPrescale == 0x14)
2754 brd9600 = 47;
2755 else
2756 brd9600 = 23;
2757
2758 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2759 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2760 ChP->BaudDiv[2] = (Byte_t) brd9600;
2761 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
457fb605 2762 out32(ChP->IndexAddr, ChP->BaudDiv);
1da177e4
LT		 2763
2764 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2765 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2766 ChP->TxControl[2] = 0;
2767 ChP->TxControl[3] = 0;
457fb605 2768 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 2769
2770 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2771 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2772 ChP->RxControl[2] = 0;
2773 ChP->RxControl[3] = 0;
457fb605 2774 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 2775
2776 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2777 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2778 ChP->TxEnables[2] = 0;
2779 ChP->TxEnables[3] = 0;
457fb605 2780 out32(ChP->IndexAddr, ChP->TxEnables);
1da177e4
LT		 2781
2782 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2783 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2784 ChP->TxCompare[2] = 0;
2785 ChP->TxCompare[3] = 0;
457fb605 2786 out32(ChP->IndexAddr, ChP->TxCompare);
1da177e4
LT		 2787
2788 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2789 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2790 ChP->TxReplace1[2] = 0;
2791 ChP->TxReplace1[3] = 0;
457fb605 2792 out32(ChP->IndexAddr, ChP->TxReplace1);
1da177e4
LT		 2793
2794 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2795 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2796 ChP->TxReplace2[2] = 0;
2797 ChP->TxReplace2[3] = 0;
457fb605 2798 out32(ChP->IndexAddr, ChP->TxReplace2);
1da177e4
LT		 2799
2800 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2801 ChP->TxFIFO = ChOff + _TX_FIFO;
2802
2803 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2804 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2805 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2806 sOutW(ChP->IndexData, 0);
2807 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2808 ChP->RxFIFO = ChOff + _RX_FIFO;
2809
2810 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2811 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2812 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2813 sOutW(ChP->IndexData, 0);
2814 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2815 sOutW(ChP->IndexData, 0);
2816 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2817 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2818 sOutB(ChP->IndexData, 0);
2819 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2820 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2821 sOutB(ChP->IndexData, 0);
2822 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2823 sEnRxProcessor(ChP); /* start the Rx processor */
2824
f15313bf 2825 return 1;
1da177e4
LT		 2826}
2827
2828/***************************************************************************
2829Function: sStopRxProcessor
2830Purpose: Stop the receive processor from processing a channel.
2831Call: sStopRxProcessor(ChP)
2832 CHANNEL_T *ChP; Ptr to channel structure
2833
2834Comments: The receive processor can be started again with sStartRxProcessor().
2835 This function causes the receive processor to skip over the
2836 stopped channel. It does not stop it from processing other channels.
2837
2838Warnings: No context switches are allowed while executing this function.
2839
2840 Do not leave the receive processor stopped for more than one
2841 character time.
2842
2843 After calling this function a delay of 4 uS is required to ensure
2844 that the receive processor is no longer processing this channel.
2845*/
f15313bf 2846static void sStopRxProcessor(CHANNEL_T * ChP)
1da177e4
LT		 2847{
2848 Byte_t R[4];
2849
2850 R[0] = ChP->R[0];
2851 R[1] = ChP->R[1];
2852 R[2] = 0x0a;
2853 R[3] = ChP->R[3];
457fb605 2854 out32(ChP->IndexAddr, R);
1da177e4
LT		 2855}
2856
2857/***************************************************************************
2858Function: sFlushRxFIFO
2859Purpose: Flush the Rx FIFO
2860Call: sFlushRxFIFO(ChP)
2861 CHANNEL_T *ChP; Ptr to channel structure
2862Return: void
2863Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2864 while it is being flushed the receive processor is stopped
2865 and the transmitter is disabled. After these operations a
2866 4 uS delay is done before clearing the pointers to allow
2867 the receive processor to stop. These items are handled inside
2868 this function.
2869Warnings: No context switches are allowed while executing this function.
2870*/
f15313bf 2871static void sFlushRxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2872{
2873 int i;
2874 Byte_t Ch; /* channel number within AIOP */
f15313bf 2875 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
1da177e4
LT		 2876
2877 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2878 return; /* don't need to flush */
2879
f15313bf 2880 RxFIFOEnabled = 0;
1da177e4 2881 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
f15313bf 2882 RxFIFOEnabled = 1;
1da177e4
LT		 2883 sDisRxFIFO(ChP); /* disable it */
2884 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2885 sInB(ChP->IntChan); /* depends on bus i/o timing */
2886 }
2887 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2888 Ch = (Byte_t) sGetChanNum(ChP);
2889 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2890 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2891 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2892 sOutW(ChP->IndexData, 0);
2893 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2894 sOutW(ChP->IndexData, 0);
2895 if (RxFIFOEnabled)
2896 sEnRxFIFO(ChP); /* enable Rx FIFO */
2897}
2898
2899/***************************************************************************
2900Function: sFlushTxFIFO
2901Purpose: Flush the Tx FIFO
2902Call: sFlushTxFIFO(ChP)
2903 CHANNEL_T *ChP; Ptr to channel structure
2904Return: void
2905Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2906 while it is being flushed the receive processor is stopped
2907 and the transmitter is disabled. After these operations a
2908 4 uS delay is done before clearing the pointers to allow
2909 the receive processor to stop. These items are handled inside
2910 this function.
2911Warnings: No context switches are allowed while executing this function.
2912*/
f15313bf 2913static void sFlushTxFIFO(CHANNEL_T * ChP)
1da177e4
LT		 2914{
2915 int i;
2916 Byte_t Ch; /* channel number within AIOP */
f15313bf 2917 int TxEnabled; /* 1 if transmitter enabled */
1da177e4
LT		 2918
2919 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2920 return; /* don't need to flush */
2921
f15313bf 2922 TxEnabled = 0;
1da177e4 2923 if (ChP->TxControl[3] & TX_ENABLE) {
f15313bf 2924 TxEnabled = 1;
1da177e4
LT		 2925 sDisTransmit(ChP); /* disable transmitter */
2926 }
2927 sStopRxProcessor(ChP); /* stop Rx processor */
2928 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2929 sInB(ChP->IntChan); /* depends on bus i/o timing */
2930 Ch = (Byte_t) sGetChanNum(ChP);
2931 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2932 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2933 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2934 sOutW(ChP->IndexData, 0);
2935 if (TxEnabled)
2936 sEnTransmit(ChP); /* enable transmitter */
2937 sStartRxProcessor(ChP); /* restart Rx processor */
2938}
2939
2940/***************************************************************************
2941Function: sWriteTxPrioByte
2942Purpose: Write a byte of priority transmit data to a channel
2943Call: sWriteTxPrioByte(ChP,Data)
2944 CHANNEL_T *ChP; Ptr to channel structure
2945 Byte_t Data; The transmit data byte
2946
2947Return: int: 1 if the bytes is successfully written, otherwise 0.
2948
2949Comments: The priority byte is transmitted before any data in the Tx FIFO.
2950
2951Warnings: No context switches are allowed while executing this function.
2952*/
f15313bf 2953static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
1da177e4
LT		 2954{
2955 Byte_t DWBuf[4]; /* buffer for double word writes */
2956 Word_t *WordPtr; /* must be far because Win SS != DS */
2957 register DWordIO_t IndexAddr;
2958
2959 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2960 IndexAddr = ChP->IndexAddr;
2961 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2962 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2963 return (0); /* nothing sent */
2964
2965 WordPtr = (Word_t *) (&DWBuf[0]);
2966 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2967
2968 DWBuf[2] = Data; /* data byte value */
457fb605 2969 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 2970
2971 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2972
2973 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2974 DWBuf[3] = 0; /* priority buffer pointer */
457fb605 2975 out32(IndexAddr, DWBuf); /* write it out */
1da177e4
LT		 2976 } else { /* write it to Tx FIFO */
2977
2978 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2979 }
2980 return (1); /* 1 byte sent */
2981}
2982
2983/***************************************************************************
2984Function: sEnInterrupts
2985Purpose: Enable one or more interrupts for a channel
2986Call: sEnInterrupts(ChP,Flags)
2987 CHANNEL_T *ChP; Ptr to channel structure
2988 Word_t Flags: Interrupt enable flags, can be any combination
2989 of the following flags:
2990 TXINT_EN: Interrupt on Tx FIFO empty
2991 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
2992 sSetRxTrigger())
2993 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
2994 MCINT_EN: Interrupt on modem input change
2995 CHANINT_EN: Allow channel interrupt signal to the AIOP's
2996 Interrupt Channel Register.
2997Return: void
2998Comments: If an interrupt enable flag is set in Flags, that interrupt will be
2999 enabled. If an interrupt enable flag is not set in Flags, that
3000 interrupt will not be changed. Interrupts can be disabled with
3001 function sDisInterrupts().
3002
3003 This function sets the appropriate bit for the channel in the AIOP's
3004 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3005 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3006
3007 Interrupts must also be globally enabled before channel interrupts
3008 will be passed on to the host. This is done with function
3009 sEnGlobalInt().
3010
3011 In some cases it may be desirable to disable interrupts globally but
3012 enable channel interrupts. This would allow the global interrupt
3013 status register to be used to determine which AIOPs need service.
3014*/
f15313bf 3015static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3016{
3017 Byte_t Mask; /* Interrupt Mask Register */
3018
3019 ChP->RxControl[2] |=
3020 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3021
457fb605 3022 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4
LT		 3023
3024 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3025
457fb605 3026 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3027
3028 if (Flags & CHANINT_EN) {
3029 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3030 sOutB(ChP->IntMask, Mask);
3031 }
3032}
3033
3034/***************************************************************************
3035Function: sDisInterrupts
3036Purpose: Disable one or more interrupts for a channel
3037Call: sDisInterrupts(ChP,Flags)
3038 CHANNEL_T *ChP; Ptr to channel structure
3039 Word_t Flags: Interrupt flags, can be any combination
3040 of the following flags:
3041 TXINT_EN: Interrupt on Tx FIFO empty
3042 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3043 sSetRxTrigger())
3044 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3045 MCINT_EN: Interrupt on modem input change
3046 CHANINT_EN: Disable channel interrupt signal to the
3047 AIOP's Interrupt Channel Register.
3048Return: void
3049Comments: If an interrupt flag is set in Flags, that interrupt will be
3050 disabled. If an interrupt flag is not set in Flags, that
3051 interrupt will not be changed. Interrupts can be enabled with
3052 function sEnInterrupts().
3053
3054 This function clears the appropriate bit for the channel in the AIOP's
3055 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3056 this channel's bit from being set in the AIOP's Interrupt Channel
3057 Register.
3058*/
f15313bf 3059static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
1da177e4
LT		 3060{
3061 Byte_t Mask; /* Interrupt Mask Register */
3062
3063 ChP->RxControl[2] &=
3064 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
457fb605 3065 out32(ChP->IndexAddr, ChP->RxControl);
1da177e4 3066 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
457fb605 3067 out32(ChP->IndexAddr, ChP->TxControl);
1da177e4
LT		 3068
3069 if (Flags & CHANINT_EN) {
3070 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3071 sOutB(ChP->IntMask, Mask);
3072 }
3073}
3074
f15313bf 3075static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
1da177e4
LT		 3076{
3077 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3078}
3079
3080/*
3081 * Not an official SSCI function, but how to reset RocketModems.
3082 * ISA bus version
3083 */
f15313bf 3084static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3085{
3086 ByteIO_t addr;
3087 Byte_t val;
3088
3089 addr = CtlP->AiopIO[0] + 0x400;
3090 val = sInB(CtlP->MReg3IO);
3091 /* if AIOP[1] is not enabled, enable it */
3092 if ((val & 2) == 0) {
3093 val = sInB(CtlP->MReg2IO);
3094 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3095 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3096 }
3097
3098 sEnAiop(CtlP, 1);
3099 if (!on)
3100 addr += 8;
3101 sOutB(addr + chan, 0); /* apply or remove reset */
3102 sDisAiop(CtlP, 1);
3103}
3104
3105/*
3106 * Not an official SSCI function, but how to reset RocketModems.
3107 * PCI bus version
3108 */
f15313bf 3109static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
1da177e4
LT		 3110{
3111 ByteIO_t addr;
3112
3113 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3114 if (!on)
3115 addr += 8;
3116 sOutB(addr + chan, 0); /* apply or remove reset */
3117}
3118
3119/* Resets the speaker controller on RocketModem II and III devices */
3120static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3121{
3122 ByteIO_t addr;
3123
3124 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3125 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3126 addr = CtlP->AiopIO[0] + 0x4F;
3127 sOutB(addr, 0);
3128 }
3129
3130 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3131 if ((model == MODEL_UPCI_RM3_8PORT)
3132 || (model == MODEL_UPCI_RM3_4PORT)) {
3133 addr = CtlP->AiopIO[0] + 0x88;
3134 sOutB(addr, 0);
3135 }
3136}
3137
3138/* Returns the line number given the controller (board), aiop and channel number */
3139static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3140{
3141 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3142}
3143
3144/*
3145 * Stores the line number associated with a given controller (board), aiop
3146 * and channel number.
3147 * Returns: The line number assigned
3148 */
3149static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3150{
3151 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3152 return (nextLineNumber - 1);
3153}
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