[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / 8250 / 8250.h

/*
 *  Driver for 8250/16550-type serial ports
 *
 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
 *
 *  Copyright (C) 2001 Russell King.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/dmaengine.h>

#include "../serial_mctrl_gpio.h"

struct uart_8250_dma {
	int (*tx_dma)(struct uart_8250_port *p);
	int (*rx_dma)(struct uart_8250_port *p);

	/* Filter function */
	dma_filter_fn		fn;
	/* Parameter to the filter function */
	void			*rx_param;
	void			*tx_param;

	struct dma_slave_config	rxconf;
	struct dma_slave_config	txconf;

	struct dma_chan		*rxchan;
	struct dma_chan		*txchan;

	dma_addr_t		rx_addr;
	dma_addr_t		tx_addr;

	dma_cookie_t		rx_cookie;
	dma_cookie_t		tx_cookie;

	void			*rx_buf;

	size_t			rx_size;
	size_t			tx_size;

	unsigned char		tx_running;
	unsigned char		tx_err;
	unsigned char		rx_running;
};

struct old_serial_port {
	unsigned int uart;
	unsigned int baud_base;
	unsigned int port;
	unsigned int irq;
	upf_t        flags;
	unsigned char io_type;
	unsigned char __iomem *iomem_base;
	unsigned short iomem_reg_shift;
};

struct serial8250_config {
	const char	*name;
	unsigned short	fifo_size;
	unsigned short	tx_loadsz;
	unsigned char	fcr;
	unsigned char	rxtrig_bytes[UART_FCR_R_TRIG_MAX_STATE];
	unsigned int	flags;
};

#define UART_CAP_FIFO	(1 << 8)	/* UART has FIFO */
#define UART_CAP_EFR	(1 << 9)	/* UART has EFR */
#define UART_CAP_SLEEP	(1 << 10)	/* UART has IER sleep */
#define UART_CAP_AFE	(1 << 11)	/* MCR-based hw flow control */
#define UART_CAP_UUE	(1 << 12)	/* UART needs IER bit 6 set (Xscale) */
#define UART_CAP_RTOIE	(1 << 13)	/* UART needs IER bit 4 set (Xscale, Tegra) */
#define UART_CAP_HFIFO	(1 << 14)	/* UART has a "hidden" FIFO */
#define UART_CAP_RPM	(1 << 15)	/* Runtime PM is active while idle */

#define UART_BUG_QUOT	(1 << 0)	/* UART has buggy quot LSB */
#define UART_BUG_TXEN	(1 << 1)	/* UART has buggy TX IIR status */
#define UART_BUG_NOMSR	(1 << 2)	/* UART has buggy MSR status bits (Au1x00) */
#define UART_BUG_THRE	(1 << 3)	/* UART has buggy THRE reassertion */
#define UART_BUG_PARITY	(1 << 4)	/* UART mishandles parity if FIFO enabled */


#ifdef CONFIG_SERIAL_8250_SHARE_IRQ
#define SERIAL8250_SHARE_IRQS 1
#else
#define SERIAL8250_SHARE_IRQS 0
#endif

#define SERIAL8250_PORT_FLAGS(_base, _irq, _flags)		\
	{							\
		.iobase		= _base,			\
		.irq		= _irq,				\
		.uartclk	= 1843200,			\
		.iotype		= UPIO_PORT,			\
		.flags		= UPF_BOOT_AUTOCONF | (_flags),	\
	}

#define SERIAL8250_PORT(_base, _irq) SERIAL8250_PORT_FLAGS(_base, _irq, 0)


static inline int serial_in(struct uart_8250_port *up, int offset)
{
	return up->port.serial_in(&up->port, offset);
}

static inline void serial_out(struct uart_8250_port *up, int offset, int value)
{
	up->port.serial_out(&up->port, offset, value);
}

void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p);

static inline int serial_dl_read(struct uart_8250_port *up)
{
	return up->dl_read(up);
}

static inline void serial_dl_write(struct uart_8250_port *up, int value)
{
	up->dl_write(up, value);
}

struct uart_8250_port *serial8250_get_port(int line);
void serial8250_rpm_get(struct uart_8250_port *p);
void serial8250_rpm_put(struct uart_8250_port *p);
int serial8250_em485_init(struct uart_8250_port *p);
void serial8250_em485_destroy(struct uart_8250_port *p);

static inline void serial8250_out_MCR(struct uart_8250_port *up, int value)
{
	int mctrl_gpio = 0;

	serial_out(up, UART_MCR, value);

	if (value & UART_MCR_RTS)
		mctrl_gpio |= TIOCM_RTS;
	if (value & UART_MCR_DTR)
		mctrl_gpio |= TIOCM_DTR;

	mctrl_gpio_set(up->gpios, mctrl_gpio);
}

static inline int serial8250_in_MCR(struct uart_8250_port *up)
{
	int mctrl, mctrl_gpio = 0;

	mctrl = serial_in(up, UART_MCR);

	/* save current MCR values */
	if (mctrl & UART_MCR_RTS)
		mctrl_gpio |= TIOCM_RTS;
	if (mctrl & UART_MCR_DTR)
		mctrl_gpio |= TIOCM_DTR;

	mctrl_gpio = mctrl_gpio_get_outputs(up->gpios, &mctrl_gpio);

	if (mctrl_gpio & TIOCM_RTS)
		mctrl |= UART_MCR_RTS;
	else
		mctrl &= ~UART_MCR_RTS;

	if (mctrl_gpio & TIOCM_DTR)
		mctrl |= UART_MCR_DTR;
	else
		mctrl &= ~UART_MCR_DTR;

	return mctrl;
}

#if defined(__alpha__) && !defined(CONFIG_PCI)
/*
 * Digital did something really horribly wrong with the OUT1 and OUT2
 * lines on at least some ALPHA's.  The failure mode is that if either
 * is cleared, the machine locks up with endless interrupts.
 */
#define ALPHA_KLUDGE_MCR  (UART_MCR_OUT2 | UART_MCR_OUT1)
#else
#define ALPHA_KLUDGE_MCR 0
#endif

#ifdef CONFIG_SERIAL_8250_PNP
int serial8250_pnp_init(void);
void serial8250_pnp_exit(void);
#else
static inline int serial8250_pnp_init(void) { return 0; }
static inline void serial8250_pnp_exit(void) { }
#endif

#ifdef CONFIG_SERIAL_8250_FINTEK
int fintek_8250_probe(struct uart_8250_port *uart);
#else
static inline int fintek_8250_probe(struct uart_8250_port *uart) { return 0; }
#endif

#ifdef CONFIG_ARCH_OMAP1
static inline int is_omap1_8250(struct uart_8250_port *pt)
{
	int res;

	switch (pt->port.mapbase) {
	case OMAP1_UART1_BASE:
	case OMAP1_UART2_BASE:
	case OMAP1_UART3_BASE:
		res = 1;
		break;
	default:
		res = 0;
		break;
	}

	return res;
}

static inline int is_omap1510_8250(struct uart_8250_port *pt)
{
	if (!cpu_is_omap1510())
		return 0;

	return is_omap1_8250(pt);
}
#else
static inline int is_omap1_8250(struct uart_8250_port *pt)
{
	return 0;
}
static inline int is_omap1510_8250(struct uart_8250_port *pt)
{
	return 0;
}
#endif

#ifdef CONFIG_SERIAL_8250_DMA
extern int serial8250_tx_dma(struct uart_8250_port *);
extern int serial8250_rx_dma(struct uart_8250_port *);
extern void serial8250_rx_dma_flush(struct uart_8250_port *);
extern int serial8250_request_dma(struct uart_8250_port *);
extern void serial8250_release_dma(struct uart_8250_port *);
#else
static inline int serial8250_tx_dma(struct uart_8250_port *p)
{
	return -1;
}
static inline int serial8250_rx_dma(struct uart_8250_port *p)
{
	return -1;
}
static inline void serial8250_rx_dma_flush(struct uart_8250_port *p) { }
static inline int serial8250_request_dma(struct uart_8250_port *p)
{
	return -1;
}
static inline void serial8250_release_dma(struct uart_8250_port *p) { }
#endif

static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
{
	unsigned char status;

	status = serial_in(up, 0x04); /* EXCR2 */
#define PRESL(x) ((x) & 0x30)
	if (PRESL(status) == 0x10) {
		/* already in high speed mode */
		return 0;
	} else {
		status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
		status |= 0x10;  /* 1.625 divisor for baud_base --> 921600 */
		serial_out(up, 0x04, status);
	}
	return 1;
}

static inline int serial_index(struct uart_port *port)
{
	return port->minor - 64;
}
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Driver for 8250/16550-type serial ports
	3	*
	4	* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
	5	*
	6	* Copyright (C) 2001 Russell King.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
1da177e4 LT	12	*/
1da177e4 LT	13
bc49a661	14	#include <linux/serial_8250.h>
aef9a7bd	15	#include <linux/serial_reg.h>
9ee4b83e HK	16	#include <linux/dmaengine.h>
9ee4b83e HK	17
4ef03d32 YY	18	#include "../serial_mctrl_gpio.h"
4ef03d32 YY	19
9ee4b83e	20	struct uart_8250_dma {
f1a297bb	21	int (tx_dma)(struct uart_8250_port p);
33d9b8b2	22	int (rx_dma)(struct uart_8250_port p);
f1a297bb	23
9a1870ce	24	/* Filter function */
9ee4b83e	25	dma_filter_fn fn;
9a1870ce	26	/* Parameter to the filter function */
9ee4b83e HK	27	void *rx_param;
	28	void *tx_param;
	29
9ee4b83e HK	30	struct dma_slave_config rxconf;
	31	struct dma_slave_config txconf;
	32
	33	struct dma_chan *rxchan;
	34	struct dma_chan *txchan;
	35
	36	dma_addr_t rx_addr;
	37	dma_addr_t tx_addr;
	38
	39	dma_cookie_t rx_cookie;
	40	dma_cookie_t tx_cookie;
	41
	42	void *rx_buf;
	43
	44	size_t rx_size;
	45	size_t tx_size;
	46
eafb9eea JO	47	unsigned char tx_running;
	48	unsigned char tx_err;
	49	unsigned char rx_running;
9ee4b83e	50	};
1da177e4 LT	51
	52	struct old_serial_port {
	53	unsigned int uart;
	54	unsigned int baud_base;
	55	unsigned int port;
	56	unsigned int irq;
079119a2	57	upf_t flags;
1da177e4	58	unsigned char io_type;
7f1dc2f3	59	unsigned char __iomem *iomem_base;
1da177e4 LT	60	unsigned short iomem_reg_shift;
	61	};
	62
1da177e4 LT	63	struct serial8250_config {
	64	const char *name;
	65	unsigned short fifo_size;
	66	unsigned short tx_loadsz;
	67	unsigned char fcr;
aef9a7bd	68	unsigned char rxtrig_bytes[UART_FCR_R_TRIG_MAX_STATE];
1da177e4 LT	69	unsigned int flags;
	70	};
	71
	72	#define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
	73	#define UART_CAP_EFR (1 << 9) /* UART has EFR */
	74	#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
	75	#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
	76	#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
4539c24f	77	#define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
ebebd49a	78	#define UART_CAP_HFIFO (1 << 14) /* UART has a "hidden" FIFO */
d74d5d1b	79	#define UART_CAP_RPM (1 << 15) /* Runtime PM is active while idle */
1da177e4	80
4ba5e35d	81	#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
55d3b282	82	#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
21c614a7	83	#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
363f66fe	84	#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
eb26dfe8	85	#define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */
4ba5e35d	86
1da177e4 LT	87
	88	#ifdef CONFIG_SERIAL_8250_SHARE_IRQ
	89	#define SERIAL8250_SHARE_IRQS 1
	90	#else
	91	#define SERIAL8250_SHARE_IRQS 0
	92	#endif
	93
b3bd6668 AW	94	#define SERIAL8250_PORT_FLAGS(_base, _irq, _flags) \
	95	{ \
	96	.iobase = _base, \
	97	.irq = _irq, \
	98	.uartclk = 1843200, \
	99	.iotype = UPIO_PORT, \
	100	.flags = UPF_BOOT_AUTOCONF \| (_flags), \
	101	}
	102
	103	#define SERIAL8250_PORT(_base, _irq) SERIAL8250_PORT_FLAGS(_base, _irq, 0)
	104
	105
3f0ab327 PG	106	static inline int serial_in(struct uart_8250_port *up, int offset)
	107	{
	108	return up->port.serial_in(&up->port, offset);
	109	}
	110
	111	static inline void serial_out(struct uart_8250_port *up, int offset, int value)
	112	{
	113	up->port.serial_out(&up->port, offset, value);
	114	}
	115
0ad372b9 SM	116	void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p);
0ad372b9 SM	117
cc419fa0 MD	118	static inline int serial_dl_read(struct uart_8250_port *up)
	119	{
	120	return up->dl_read(up);
	121	}
	122
	123	static inline void serial_dl_write(struct uart_8250_port *up, int value)
	124	{
	125	up->dl_write(up, value);
	126	}
	127
ae14a795	128	struct uart_8250_port *serial8250_get_port(int line);
77285243 SAS	129	void serial8250_rpm_get(struct uart_8250_port *p);
77285243 SAS	130	void serial8250_rpm_put(struct uart_8250_port *p);
e490c914 MK	131	int serial8250_em485_init(struct uart_8250_port *p);
e490c914 MK	132	void serial8250_em485_destroy(struct uart_8250_port *p);
ae14a795	133
36fd95b1 YY	134	static inline void serial8250_out_MCR(struct uart_8250_port *up, int value)
36fd95b1 YY	135	{
4ef03d32 YY	136	int mctrl_gpio = 0;
4ef03d32 YY	137
36fd95b1	138	serial_out(up, UART_MCR, value);
4ef03d32 YY	139
	140	if (value & UART_MCR_RTS)
	141	mctrl_gpio \|= TIOCM_RTS;
	142	if (value & UART_MCR_DTR)
	143	mctrl_gpio \|= TIOCM_DTR;
	144
	145	mctrl_gpio_set(up->gpios, mctrl_gpio);
36fd95b1 YY	146	}
	147
	148	static inline int serial8250_in_MCR(struct uart_8250_port *up)
	149	{
4ef03d32 YY	150	int mctrl, mctrl_gpio = 0;
	151
	152	mctrl = serial_in(up, UART_MCR);
	153
	154	/* save current MCR values */
	155	if (mctrl & UART_MCR_RTS)
	156	mctrl_gpio \|= TIOCM_RTS;
	157	if (mctrl & UART_MCR_DTR)
	158	mctrl_gpio \|= TIOCM_DTR;
	159
	160	mctrl_gpio = mctrl_gpio_get_outputs(up->gpios, &mctrl_gpio);
	161
	162	if (mctrl_gpio & TIOCM_RTS)
	163	mctrl \|= UART_MCR_RTS;
	164	else
	165	mctrl &= ~UART_MCR_RTS;
	166
	167	if (mctrl_gpio & TIOCM_DTR)
	168	mctrl \|= UART_MCR_DTR;
	169	else
	170	mctrl &= ~UART_MCR_DTR;
	171
	172	return mctrl;
36fd95b1 YY	173	}
36fd95b1 YY	174
1da177e4 LT	175	#if defined(__alpha__) && !defined(CONFIG_PCI)
	176	/*
	177	* Digital did something really horribly wrong with the OUT1 and OUT2
	178	* lines on at least some ALPHA's. The failure mode is that if either
	179	* is cleared, the machine locks up with endless interrupts.
	180	*/
	181	#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 \| UART_MCR_OUT1)
1da177e4 LT	182	#else
	183	#define ALPHA_KLUDGE_MCR 0
	184	#endif
835d844d SY	185
	186	#ifdef CONFIG_SERIAL_8250_PNP
	187	int serial8250_pnp_init(void);
	188	void serial8250_pnp_exit(void);
	189	#else
	190	static inline int serial8250_pnp_init(void) { return 0; }
	191	static inline void serial8250_pnp_exit(void) { }
	192	#endif
	193
fa01e2ca RRD	194	#ifdef CONFIG_SERIAL_8250_FINTEK
	195	int fintek_8250_probe(struct uart_8250_port *uart);
	196	#else
	197	static inline int fintek_8250_probe(struct uart_8250_port *uart) { return 0; }
	198	#endif
	199
54ec52b6 TL	200	#ifdef CONFIG_ARCH_OMAP1
	201	static inline int is_omap1_8250(struct uart_8250_port *pt)
	202	{
	203	int res;
	204
	205	switch (pt->port.mapbase) {
	206	case OMAP1_UART1_BASE:
	207	case OMAP1_UART2_BASE:
	208	case OMAP1_UART3_BASE:
	209	res = 1;
	210	break;
	211	default:
	212	res = 0;
	213	break;
	214	}
	215
	216	return res;
	217	}
	218
	219	static inline int is_omap1510_8250(struct uart_8250_port *pt)
	220	{
	221	if (!cpu_is_omap1510())
	222	return 0;
	223
	224	return is_omap1_8250(pt);
	225	}
	226	#else
	227	static inline int is_omap1_8250(struct uart_8250_port *pt)
	228	{
	229	return 0;
	230	}
	231	static inline int is_omap1510_8250(struct uart_8250_port *pt)
	232	{
	233	return 0;
	234	}
	235	#endif
9ee4b83e HK	236
	237	#ifdef CONFIG_SERIAL_8250_DMA
	238	extern int serial8250_tx_dma(struct uart_8250_port *);
33d9b8b2 PH	239	extern int serial8250_rx_dma(struct uart_8250_port *);
33d9b8b2 PH	240	extern void serial8250_rx_dma_flush(struct uart_8250_port *);
9ee4b83e HK	241	extern int serial8250_request_dma(struct uart_8250_port *);
	242	extern void serial8250_release_dma(struct uart_8250_port *);
	243	#else
	244	static inline int serial8250_tx_dma(struct uart_8250_port *p)
	245	{
	246	return -1;
	247	}
33d9b8b2	248	static inline int serial8250_rx_dma(struct uart_8250_port *p)
9ee4b83e HK	249	{
	250	return -1;
	251	}
33d9b8b2	252	static inline void serial8250_rx_dma_flush(struct uart_8250_port *p) { }
9ee4b83e HK	253	static inline int serial8250_request_dma(struct uart_8250_port *p)
	254	{
	255	return -1;
	256	}
	257	static inline void serial8250_release_dma(struct uart_8250_port *p) { }
	258	#endif
d81e50f6 PH	259
	260	static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
	261	{
	262	unsigned char status;
	263
	264	status = serial_in(up, 0x04); /* EXCR2 */
	265	#define PRESL(x) ((x) & 0x30)
	266	if (PRESL(status) == 0x10) {
	267	/* already in high speed mode */
	268	return 0;
	269	} else {
	270	status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
	271	status \|= 0x10; /* 1.625 divisor for baud_base --> 921600 */
	272	serial_out(up, 0x04, status);
	273	}
	274	return 1;
	275	}
b6830f6d PH	276
	277	static inline int serial_index(struct uart_port *port)
	278	{
	279	return port->minor - 64;
	280	}