[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / 8250 / 8250.h

/*
 *  Driver for 8250/16550-type serial ports
 *
 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
 *
 *  Copyright (C) 2001 Russell King.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/serial_8250.h>
#include <linux/serial_reg.h>
#include <linux/dmaengine.h>

struct uart_8250_dma {
	int (*tx_dma)(struct uart_8250_port *p);
	int (*rx_dma)(struct uart_8250_port *p);

	/* Filter function */
	dma_filter_fn		fn;
	/* Parameter to the filter function */
	void			*rx_param;
	void			*tx_param;

	struct dma_slave_config	rxconf;
	struct dma_slave_config	txconf;

	struct dma_chan		*rxchan;
	struct dma_chan		*txchan;

	dma_addr_t		rx_addr;
	dma_addr_t		tx_addr;

	dma_cookie_t		rx_cookie;
	dma_cookie_t		tx_cookie;

	void			*rx_buf;

	size_t			rx_size;
	size_t			tx_size;

	unsigned char		tx_running;
	unsigned char		tx_err;
	unsigned char		rx_running;
};

struct old_serial_port {
	unsigned int uart;
	unsigned int baud_base;
	unsigned int port;
	unsigned int irq;
	upf_t        flags;
	unsigned char io_type;
	unsigned char __iomem *iomem_base;
	unsigned short iomem_reg_shift;
};

struct serial8250_config {
	const char	*name;
	unsigned short	fifo_size;
	unsigned short	tx_loadsz;
	unsigned char	fcr;
	unsigned char	rxtrig_bytes[UART_FCR_R_TRIG_MAX_STATE];
	unsigned int	flags;
};

#define UART_CAP_FIFO	(1 << 8)	/* UART has FIFO */
#define UART_CAP_EFR	(1 << 9)	/* UART has EFR */
#define UART_CAP_SLEEP	(1 << 10)	/* UART has IER sleep */
#define UART_CAP_AFE	(1 << 11)	/* MCR-based hw flow control */
#define UART_CAP_UUE	(1 << 12)	/* UART needs IER bit 6 set (Xscale) */
#define UART_CAP_RTOIE	(1 << 13)	/* UART needs IER bit 4 set (Xscale, Tegra) */
#define UART_CAP_HFIFO	(1 << 14)	/* UART has a "hidden" FIFO */
#define UART_CAP_RPM	(1 << 15)	/* Runtime PM is active while idle */

#define UART_BUG_QUOT	(1 << 0)	/* UART has buggy quot LSB */
#define UART_BUG_TXEN	(1 << 1)	/* UART has buggy TX IIR status */
#define UART_BUG_NOMSR	(1 << 2)	/* UART has buggy MSR status bits (Au1x00) */
#define UART_BUG_THRE	(1 << 3)	/* UART has buggy THRE reassertion */
#define UART_BUG_PARITY	(1 << 4)	/* UART mishandles parity if FIFO enabled */


#ifdef CONFIG_SERIAL_8250_SHARE_IRQ
#define SERIAL8250_SHARE_IRQS 1
#else
#define SERIAL8250_SHARE_IRQS 0
#endif

#define SERIAL8250_PORT_FLAGS(_base, _irq, _flags)		\
	{							\
		.iobase		= _base,			\
		.irq		= _irq,				\
		.uartclk	= 1843200,			\
		.iotype		= UPIO_PORT,			\
		.flags		= UPF_BOOT_AUTOCONF | (_flags),	\
	}

#define SERIAL8250_PORT(_base, _irq) SERIAL8250_PORT_FLAGS(_base, _irq, 0)


static inline int serial_in(struct uart_8250_port *up, int offset)
{
	return up->port.serial_in(&up->port, offset);
}

static inline void serial_out(struct uart_8250_port *up, int offset, int value)
{
	up->port.serial_out(&up->port, offset, value);
}

void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p);

static inline int serial_dl_read(struct uart_8250_port *up)
{
	return up->dl_read(up);
}

static inline void serial_dl_write(struct uart_8250_port *up, int value)
{
	up->dl_write(up, value);
}

struct uart_8250_port *serial8250_get_port(int line);
void serial8250_rpm_get(struct uart_8250_port *p);
void serial8250_rpm_put(struct uart_8250_port *p);
int serial8250_em485_init(struct uart_8250_port *p);
void serial8250_em485_destroy(struct uart_8250_port *p);

#if defined(__alpha__) && !defined(CONFIG_PCI)
/*
 * Digital did something really horribly wrong with the OUT1 and OUT2
 * lines on at least some ALPHA's.  The failure mode is that if either
 * is cleared, the machine locks up with endless interrupts.
 */
#define ALPHA_KLUDGE_MCR  (UART_MCR_OUT2 | UART_MCR_OUT1)
#else
#define ALPHA_KLUDGE_MCR 0
#endif

#ifdef CONFIG_SERIAL_8250_PNP
int serial8250_pnp_init(void);
void serial8250_pnp_exit(void);
#else
static inline int serial8250_pnp_init(void) { return 0; }
static inline void serial8250_pnp_exit(void) { }
#endif

#ifdef CONFIG_SERIAL_8250_FINTEK
int fintek_8250_probe(struct uart_8250_port *uart);
#else
static inline int fintek_8250_probe(struct uart_8250_port *uart) { return 0; }
#endif

#ifdef CONFIG_ARCH_OMAP1
static inline int is_omap1_8250(struct uart_8250_port *pt)
{
	int res;

	switch (pt->port.mapbase) {
	case OMAP1_UART1_BASE:
	case OMAP1_UART2_BASE:
	case OMAP1_UART3_BASE:
		res = 1;
		break;
	default:
		res = 0;
		break;
	}

	return res;
}

static inline int is_omap1510_8250(struct uart_8250_port *pt)
{
	if (!cpu_is_omap1510())
		return 0;

	return is_omap1_8250(pt);
}
#else
static inline int is_omap1_8250(struct uart_8250_port *pt)
{
	return 0;
}
static inline int is_omap1510_8250(struct uart_8250_port *pt)
{
	return 0;
}
#endif

#ifdef CONFIG_SERIAL_8250_DMA
extern int serial8250_tx_dma(struct uart_8250_port *);
extern int serial8250_rx_dma(struct uart_8250_port *);
extern void serial8250_rx_dma_flush(struct uart_8250_port *);
extern int serial8250_request_dma(struct uart_8250_port *);
extern void serial8250_release_dma(struct uart_8250_port *);
#else
static inline int serial8250_tx_dma(struct uart_8250_port *p)
{
	return -1;
}
static inline int serial8250_rx_dma(struct uart_8250_port *p)
{
	return -1;
}
static inline void serial8250_rx_dma_flush(struct uart_8250_port *p) { }
static inline int serial8250_request_dma(struct uart_8250_port *p)
{
	return -1;
}
static inline void serial8250_release_dma(struct uart_8250_port *p) { }
#endif

static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
{
	unsigned char status;

	status = serial_in(up, 0x04); /* EXCR2 */
#define PRESL(x) ((x) & 0x30)
	if (PRESL(status) == 0x10) {
		/* already in high speed mode */
		return 0;
	} else {
		status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
		status |= 0x10;  /* 1.625 divisor for baud_base --> 921600 */
		serial_out(up, 0x04, status);
	}
	return 1;
}

static inline int serial_index(struct uart_port *port)
{
	return port->minor - 64;
}

#if 0
#define DEBUG_INTR(fmt...)	printk(fmt)
#else
#define DEBUG_INTR(fmt...)	do { } while (0)
#endif
Commit	Line	Data
1da177e4	1	/*
1da177e4 LT	2	* Driver for 8250/16550-type serial ports
	3	*
	4	* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
	5	*
	6	* Copyright (C) 2001 Russell King.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
1da177e4 LT	12	*/
1da177e4 LT	13
bc49a661	14	#include <linux/serial_8250.h>
aef9a7bd	15	#include <linux/serial_reg.h>
9ee4b83e HK	16	#include <linux/dmaengine.h>
	17
	18	struct uart_8250_dma {
f1a297bb	19	int (tx_dma)(struct uart_8250_port p);
33d9b8b2	20	int (rx_dma)(struct uart_8250_port p);
f1a297bb	21
9a1870ce	22	/* Filter function */
9ee4b83e	23	dma_filter_fn fn;
9a1870ce	24	/* Parameter to the filter function */
9ee4b83e HK	25	void *rx_param;
	26	void *tx_param;
	27
9ee4b83e HK	28	struct dma_slave_config rxconf;
	29	struct dma_slave_config txconf;
	30
	31	struct dma_chan *rxchan;
	32	struct dma_chan *txchan;
	33
	34	dma_addr_t rx_addr;
	35	dma_addr_t tx_addr;
	36
	37	dma_cookie_t rx_cookie;
	38	dma_cookie_t tx_cookie;
	39
	40	void *rx_buf;
	41
	42	size_t rx_size;
	43	size_t tx_size;
	44
eafb9eea JO	45	unsigned char tx_running;
	46	unsigned char tx_err;
	47	unsigned char rx_running;
9ee4b83e	48	};
1da177e4 LT	49
	50	struct old_serial_port {
	51	unsigned int uart;
	52	unsigned int baud_base;
	53	unsigned int port;
	54	unsigned int irq;
079119a2	55	upf_t flags;
1da177e4	56	unsigned char io_type;
7f1dc2f3	57	unsigned char __iomem *iomem_base;
1da177e4 LT	58	unsigned short iomem_reg_shift;
	59	};
	60
1da177e4 LT	61	struct serial8250_config {
	62	const char *name;
	63	unsigned short fifo_size;
	64	unsigned short tx_loadsz;
	65	unsigned char fcr;
aef9a7bd	66	unsigned char rxtrig_bytes[UART_FCR_R_TRIG_MAX_STATE];
1da177e4 LT	67	unsigned int flags;
	68	};
	69
	70	#define UART_CAP_FIFO (1 << 8) /* UART has FIFO */
	71	#define UART_CAP_EFR (1 << 9) /* UART has EFR */
	72	#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
	73	#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
	74	#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
4539c24f	75	#define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
ebebd49a	76	#define UART_CAP_HFIFO (1 << 14) /* UART has a "hidden" FIFO */
d74d5d1b	77	#define UART_CAP_RPM (1 << 15) /* Runtime PM is active while idle */
1da177e4	78
4ba5e35d	79	#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
55d3b282	80	#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
21c614a7	81	#define UART_BUG_NOMSR (1 << 2) /* UART has buggy MSR status bits (Au1x00) */
363f66fe	82	#define UART_BUG_THRE (1 << 3) /* UART has buggy THRE reassertion */
eb26dfe8	83	#define UART_BUG_PARITY (1 << 4) /* UART mishandles parity if FIFO enabled */
4ba5e35d	84
1da177e4 LT	85
	86	#ifdef CONFIG_SERIAL_8250_SHARE_IRQ
	87	#define SERIAL8250_SHARE_IRQS 1
	88	#else
	89	#define SERIAL8250_SHARE_IRQS 0
	90	#endif
	91
b3bd6668 AW	92	#define SERIAL8250_PORT_FLAGS(_base, _irq, _flags) \
	93	{ \
	94	.iobase = _base, \
	95	.irq = _irq, \
	96	.uartclk = 1843200, \
	97	.iotype = UPIO_PORT, \
	98	.flags = UPF_BOOT_AUTOCONF \| (_flags), \
	99	}
	100
	101	#define SERIAL8250_PORT(_base, _irq) SERIAL8250_PORT_FLAGS(_base, _irq, 0)
	102
	103
3f0ab327 PG	104	static inline int serial_in(struct uart_8250_port *up, int offset)
	105	{
	106	return up->port.serial_in(&up->port, offset);
	107	}
	108
	109	static inline void serial_out(struct uart_8250_port *up, int offset, int value)
	110	{
	111	up->port.serial_out(&up->port, offset, value);
	112	}
	113
0ad372b9 SM	114	void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p);
0ad372b9 SM	115
cc419fa0 MD	116	static inline int serial_dl_read(struct uart_8250_port *up)
	117	{
	118	return up->dl_read(up);
	119	}
	120
	121	static inline void serial_dl_write(struct uart_8250_port *up, int value)
	122	{
	123	up->dl_write(up, value);
	124	}
	125
ae14a795	126	struct uart_8250_port *serial8250_get_port(int line);
77285243 SAS	127	void serial8250_rpm_get(struct uart_8250_port *p);
77285243 SAS	128	void serial8250_rpm_put(struct uart_8250_port *p);
e490c914 MK	129	int serial8250_em485_init(struct uart_8250_port *p);
e490c914 MK	130	void serial8250_em485_destroy(struct uart_8250_port *p);
ae14a795	131
1da177e4 LT	132	#if defined(__alpha__) && !defined(CONFIG_PCI)
	133	/*
	134	* Digital did something really horribly wrong with the OUT1 and OUT2
	135	* lines on at least some ALPHA's. The failure mode is that if either
	136	* is cleared, the machine locks up with endless interrupts.
	137	*/
	138	#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2 \| UART_MCR_OUT1)
1da177e4 LT	139	#else
	140	#define ALPHA_KLUDGE_MCR 0
	141	#endif
835d844d SY	142
	143	#ifdef CONFIG_SERIAL_8250_PNP
	144	int serial8250_pnp_init(void);
	145	void serial8250_pnp_exit(void);
	146	#else
	147	static inline int serial8250_pnp_init(void) { return 0; }
	148	static inline void serial8250_pnp_exit(void) { }
	149	#endif
	150
fa01e2ca RRD	151	#ifdef CONFIG_SERIAL_8250_FINTEK
	152	int fintek_8250_probe(struct uart_8250_port *uart);
	153	#else
	154	static inline int fintek_8250_probe(struct uart_8250_port *uart) { return 0; }
	155	#endif
	156
54ec52b6 TL	157	#ifdef CONFIG_ARCH_OMAP1
	158	static inline int is_omap1_8250(struct uart_8250_port *pt)
	159	{
	160	int res;
	161
	162	switch (pt->port.mapbase) {
	163	case OMAP1_UART1_BASE:
	164	case OMAP1_UART2_BASE:
	165	case OMAP1_UART3_BASE:
	166	res = 1;
	167	break;
	168	default:
	169	res = 0;
	170	break;
	171	}
	172
	173	return res;
	174	}
	175
	176	static inline int is_omap1510_8250(struct uart_8250_port *pt)
	177	{
	178	if (!cpu_is_omap1510())
	179	return 0;
	180
	181	return is_omap1_8250(pt);
	182	}
	183	#else
	184	static inline int is_omap1_8250(struct uart_8250_port *pt)
	185	{
	186	return 0;
	187	}
	188	static inline int is_omap1510_8250(struct uart_8250_port *pt)
	189	{
	190	return 0;
	191	}
	192	#endif
9ee4b83e HK	193
	194	#ifdef CONFIG_SERIAL_8250_DMA
	195	extern int serial8250_tx_dma(struct uart_8250_port *);
33d9b8b2 PH	196	extern int serial8250_rx_dma(struct uart_8250_port *);
33d9b8b2 PH	197	extern void serial8250_rx_dma_flush(struct uart_8250_port *);
9ee4b83e HK	198	extern int serial8250_request_dma(struct uart_8250_port *);
	199	extern void serial8250_release_dma(struct uart_8250_port *);
	200	#else
	201	static inline int serial8250_tx_dma(struct uart_8250_port *p)
	202	{
	203	return -1;
	204	}
33d9b8b2	205	static inline int serial8250_rx_dma(struct uart_8250_port *p)
9ee4b83e HK	206	{
	207	return -1;
	208	}
33d9b8b2	209	static inline void serial8250_rx_dma_flush(struct uart_8250_port *p) { }
9ee4b83e HK	210	static inline int serial8250_request_dma(struct uart_8250_port *p)
	211	{
	212	return -1;
	213	}
	214	static inline void serial8250_release_dma(struct uart_8250_port *p) { }
	215	#endif
d81e50f6 PH	216
	217	static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
	218	{
	219	unsigned char status;
	220
	221	status = serial_in(up, 0x04); /* EXCR2 */
	222	#define PRESL(x) ((x) & 0x30)
	223	if (PRESL(status) == 0x10) {
	224	/* already in high speed mode */
	225	return 0;
	226	} else {
	227	status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
	228	status \|= 0x10; /* 1.625 divisor for baud_base --> 921600 */
	229	serial_out(up, 0x04, status);
	230	}
	231	return 1;
	232	}
b6830f6d PH	233
	234	static inline int serial_index(struct uart_port *port)
	235	{
	236	return port->minor - 64;
	237	}
	238
	239	#if 0
	240	#define DEBUG_INTR(fmt...) printk(fmt)
	241	#else
	242	#define DEBUG_INTR(fmt...) do { } while (0)
	243	#endif