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Commit | Line | Data |
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7d4008eb JI |
1 | /* |
2 | * Synopsys DesignWare 8250 driver. | |
3 | * | |
4 | * Copyright 2011 Picochip, Jamie Iles. | |
6a7320c4 | 5 | * Copyright 2013 Intel Corporation |
7d4008eb JI |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the | |
13 | * LCR is written whilst busy. If it is, then a busy detect interrupt is | |
14 | * raised, the LCR needs to be rewritten and the uart status register read. | |
15 | */ | |
16 | #include <linux/device.h> | |
7d4008eb JI |
17 | #include <linux/io.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/serial_8250.h> | |
7d4008eb JI |
20 | #include <linux/serial_reg.h> |
21 | #include <linux/of.h> | |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/of_platform.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/slab.h> | |
6a7320c4 | 26 | #include <linux/acpi.h> |
e302cd93 | 27 | #include <linux/clk.h> |
7fe090bf | 28 | #include <linux/reset.h> |
ffc3ae6d | 29 | #include <linux/pm_runtime.h> |
7d4008eb | 30 | |
d5f1af7e DD |
31 | #include <asm/byteorder.h> |
32 | ||
7277b2a1 HK |
33 | #include "8250.h" |
34 | ||
30046df2 HK |
35 | /* Offsets for the DesignWare specific registers */ |
36 | #define DW_UART_USR 0x1f /* UART Status Register */ | |
37 | #define DW_UART_CPR 0xf4 /* Component Parameter Register */ | |
38 | #define DW_UART_UCV 0xf8 /* UART Component Version */ | |
39 | ||
40 | /* Component Parameter Register bits */ | |
41 | #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) | |
42 | #define DW_UART_CPR_AFCE_MODE (1 << 4) | |
43 | #define DW_UART_CPR_THRE_MODE (1 << 5) | |
44 | #define DW_UART_CPR_SIR_MODE (1 << 6) | |
45 | #define DW_UART_CPR_SIR_LP_MODE (1 << 7) | |
46 | #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) | |
47 | #define DW_UART_CPR_FIFO_ACCESS (1 << 9) | |
48 | #define DW_UART_CPR_FIFO_STAT (1 << 10) | |
49 | #define DW_UART_CPR_SHADOW (1 << 11) | |
50 | #define DW_UART_CPR_ENCODED_PARMS (1 << 12) | |
51 | #define DW_UART_CPR_DMA_EXTRA (1 << 13) | |
52 | #define DW_UART_CPR_FIFO_MODE (0xff << 16) | |
53 | /* Helper for fifo size calculation */ | |
54 | #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) | |
55 | ||
0e0b989e EB |
56 | /* DesignWare specific register fields */ |
57 | #define DW_UART_MCR_SIRE BIT(6) | |
30046df2 | 58 | |
7d4008eb | 59 | struct dw8250_data { |
fe958555 | 60 | u8 usr_reg; |
fe958555 | 61 | int line; |
dfd37668 DL |
62 | int msr_mask_on; |
63 | int msr_mask_off; | |
fe958555 | 64 | struct clk *clk; |
7d78cbef | 65 | struct clk *pclk; |
7fe090bf | 66 | struct reset_control *rst; |
fe958555 | 67 | struct uart_8250_dma dma; |
4f042054 HK |
68 | |
69 | unsigned int skip_autocfg:1; | |
c73942e2 | 70 | unsigned int uart_16550_compatible:1; |
7d4008eb JI |
71 | }; |
72 | ||
33acbb82 TK |
73 | static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) |
74 | { | |
75 | struct dw8250_data *d = p->private_data; | |
76 | ||
dfd37668 DL |
77 | /* Override any modem control signals if needed */ |
78 | if (offset == UART_MSR) { | |
79 | value |= d->msr_mask_on; | |
80 | value &= ~d->msr_mask_off; | |
81 | } | |
82 | ||
33acbb82 TK |
83 | return value; |
84 | } | |
85 | ||
c49436b6 TK |
86 | static void dw8250_force_idle(struct uart_port *p) |
87 | { | |
b1261c86 AS |
88 | struct uart_8250_port *up = up_to_u8250p(p); |
89 | ||
90 | serial8250_clear_and_reinit_fifos(up); | |
c49436b6 TK |
91 | (void)p->serial_in(p, UART_RX); |
92 | } | |
93 | ||
cdcea058 | 94 | static void dw8250_check_lcr(struct uart_port *p, int value) |
7d4008eb | 95 | { |
cdcea058 NC |
96 | void __iomem *offset = p->membase + (UART_LCR << p->regshift); |
97 | int tries = 1000; | |
c49436b6 TK |
98 | |
99 | /* Make sure LCR write wasn't ignored */ | |
cdcea058 NC |
100 | while (tries--) { |
101 | unsigned int lcr = p->serial_in(p, UART_LCR); | |
102 | ||
103 | if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) | |
104 | return; | |
105 | ||
106 | dw8250_force_idle(p); | |
107 | ||
108 | #ifdef CONFIG_64BIT | |
6550be9f KW |
109 | if (p->type == PORT_OCTEON) |
110 | __raw_writeq(value & 0xff, offset); | |
111 | else | |
112 | #endif | |
cdcea058 NC |
113 | if (p->iotype == UPIO_MEM32) |
114 | writel(value, offset); | |
5a43140c NC |
115 | else if (p->iotype == UPIO_MEM32BE) |
116 | iowrite32be(value, offset); | |
cdcea058 NC |
117 | else |
118 | writeb(value, offset); | |
c49436b6 | 119 | } |
cdcea058 NC |
120 | /* |
121 | * FIXME: this deadlocks if port->lock is already held | |
122 | * dev_err(p->dev, "Couldn't set LCR to %d\n", value); | |
123 | */ | |
124 | } | |
125 | ||
126 | static void dw8250_serial_out(struct uart_port *p, int offset, int value) | |
127 | { | |
128 | struct dw8250_data *d = p->private_data; | |
129 | ||
130 | writeb(value, p->membase + (offset << p->regshift)); | |
131 | ||
132 | if (offset == UART_LCR && !d->uart_16550_compatible) | |
133 | dw8250_check_lcr(p, value); | |
7d4008eb JI |
134 | } |
135 | ||
136 | static unsigned int dw8250_serial_in(struct uart_port *p, int offset) | |
137 | { | |
33acbb82 | 138 | unsigned int value = readb(p->membase + (offset << p->regshift)); |
7d4008eb | 139 | |
33acbb82 | 140 | return dw8250_modify_msr(p, offset, value); |
7d4008eb JI |
141 | } |
142 | ||
bca2092d DD |
143 | #ifdef CONFIG_64BIT |
144 | static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) | |
d5f1af7e | 145 | { |
bca2092d DD |
146 | unsigned int value; |
147 | ||
148 | value = (u8)__raw_readq(p->membase + (offset << p->regshift)); | |
149 | ||
150 | return dw8250_modify_msr(p, offset, value); | |
d5f1af7e DD |
151 | } |
152 | ||
bca2092d DD |
153 | static void dw8250_serial_outq(struct uart_port *p, int offset, int value) |
154 | { | |
cdcea058 NC |
155 | struct dw8250_data *d = p->private_data; |
156 | ||
bca2092d DD |
157 | value &= 0xff; |
158 | __raw_writeq(value, p->membase + (offset << p->regshift)); | |
159 | /* Read back to ensure register write ordering. */ | |
160 | __raw_readq(p->membase + (UART_LCR << p->regshift)); | |
161 | ||
cdcea058 NC |
162 | if (offset == UART_LCR && !d->uart_16550_compatible) |
163 | dw8250_check_lcr(p, value); | |
bca2092d DD |
164 | } |
165 | #endif /* CONFIG_64BIT */ | |
166 | ||
7d4008eb JI |
167 | static void dw8250_serial_out32(struct uart_port *p, int offset, int value) |
168 | { | |
cdcea058 NC |
169 | struct dw8250_data *d = p->private_data; |
170 | ||
33acbb82 | 171 | writel(value, p->membase + (offset << p->regshift)); |
c49436b6 | 172 | |
cdcea058 NC |
173 | if (offset == UART_LCR && !d->uart_16550_compatible) |
174 | dw8250_check_lcr(p, value); | |
7d4008eb JI |
175 | } |
176 | ||
177 | static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) | |
178 | { | |
33acbb82 | 179 | unsigned int value = readl(p->membase + (offset << p->regshift)); |
7d4008eb | 180 | |
33acbb82 | 181 | return dw8250_modify_msr(p, offset, value); |
7d4008eb JI |
182 | } |
183 | ||
46250901 NC |
184 | static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) |
185 | { | |
186 | struct dw8250_data *d = p->private_data; | |
187 | ||
188 | iowrite32be(value, p->membase + (offset << p->regshift)); | |
189 | ||
190 | if (offset == UART_LCR && !d->uart_16550_compatible) | |
191 | dw8250_check_lcr(p, value); | |
192 | } | |
193 | ||
194 | static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) | |
195 | { | |
196 | unsigned int value = ioread32be(p->membase + (offset << p->regshift)); | |
197 | ||
198 | return dw8250_modify_msr(p, offset, value); | |
199 | } | |
200 | ||
201 | ||
7d4008eb JI |
202 | static int dw8250_handle_irq(struct uart_port *p) |
203 | { | |
424d7918 | 204 | struct uart_8250_port *up = up_to_u8250p(p); |
7d4008eb JI |
205 | struct dw8250_data *d = p->private_data; |
206 | unsigned int iir = p->serial_in(p, UART_IIR); | |
424d7918 DA |
207 | unsigned int status; |
208 | unsigned long flags; | |
209 | ||
210 | /* | |
211 | * There are ways to get Designware-based UARTs into a state where | |
212 | * they are asserting UART_IIR_RX_TIMEOUT but there is no actual | |
213 | * data available. If we see such a case then we'll do a bogus | |
214 | * read. If we don't do this then the "RX TIMEOUT" interrupt will | |
215 | * fire forever. | |
216 | * | |
217 | * This problem has only been observed so far when not in DMA mode | |
218 | * so we limit the workaround only to non-DMA mode. | |
219 | */ | |
220 | if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { | |
221 | spin_lock_irqsave(&p->lock, flags); | |
222 | status = p->serial_in(p, UART_LSR); | |
223 | ||
224 | if (!(status & (UART_LSR_DR | UART_LSR_BI))) | |
225 | (void) p->serial_in(p, UART_RX); | |
226 | ||
227 | spin_unlock_irqrestore(&p->lock, flags); | |
228 | } | |
7d4008eb | 229 | |
34eefb59 | 230 | if (serial8250_handle_irq(p, iir)) |
7d4008eb | 231 | return 1; |
34eefb59 AS |
232 | |
233 | if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { | |
c49436b6 | 234 | /* Clear the USR */ |
d5f1af7e | 235 | (void)p->serial_in(p, d->usr_reg); |
7d4008eb JI |
236 | |
237 | return 1; | |
238 | } | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
ffc3ae6d HK |
243 | static void |
244 | dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) | |
245 | { | |
246 | if (!state) | |
247 | pm_runtime_get_sync(port->dev); | |
248 | ||
249 | serial8250_do_pm(port, state, old); | |
250 | ||
251 | if (state) | |
252 | pm_runtime_put_sync_suspend(port->dev); | |
253 | } | |
254 | ||
4e26b134 HK |
255 | static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, |
256 | struct ktermios *old) | |
257 | { | |
258 | unsigned int baud = tty_termios_baud_rate(termios); | |
259 | struct dw8250_data *d = p->private_data; | |
09498087 | 260 | long rate; |
4e26b134 HK |
261 | int ret; |
262 | ||
263 | if (IS_ERR(d->clk) || !old) | |
264 | goto out; | |
265 | ||
4e26b134 HK |
266 | clk_disable_unprepare(d->clk); |
267 | rate = clk_round_rate(d->clk, baud * 16); | |
09498087 HS |
268 | if (rate < 0) |
269 | ret = rate; | |
b15bfbe6 JH |
270 | else if (rate == 0) |
271 | ret = -ENOENT; | |
09498087 HS |
272 | else |
273 | ret = clk_set_rate(d->clk, rate); | |
4e26b134 HK |
274 | clk_prepare_enable(d->clk); |
275 | ||
276 | if (!ret) | |
277 | p->uartclk = rate; | |
0a6c301a | 278 | |
6a171b29 | 279 | out: |
0a6c301a QZ |
280 | p->status &= ~UPSTAT_AUTOCTS; |
281 | if (termios->c_cflag & CRTSCTS) | |
282 | p->status |= UPSTAT_AUTOCTS; | |
283 | ||
4e26b134 HK |
284 | serial8250_do_set_termios(p, termios, old); |
285 | } | |
286 | ||
0e0b989e EB |
287 | static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) |
288 | { | |
289 | struct uart_8250_port *up = up_to_u8250p(p); | |
290 | unsigned int mcr = p->serial_in(p, UART_MCR); | |
291 | ||
292 | if (up->capabilities & UART_CAP_IRDA) { | |
293 | if (termios->c_line == N_IRDA) | |
294 | mcr |= DW_UART_MCR_SIRE; | |
295 | else | |
296 | mcr &= ~DW_UART_MCR_SIRE; | |
297 | ||
298 | p->serial_out(p, UART_MCR, mcr); | |
299 | } | |
300 | serial8250_do_set_ldisc(p, termios); | |
301 | } | |
302 | ||
1edb3cf2 HK |
303 | /* |
304 | * dw8250_fallback_dma_filter will prevent the UART from getting just any free | |
305 | * channel on platforms that have DMA engines, but don't have any channels | |
306 | * assigned to the UART. | |
307 | * | |
308 | * REVISIT: This is a work around for limitation in the DMA Engine API. Once the | |
309 | * core problem is fixed, this function is no longer needed. | |
310 | */ | |
311 | static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) | |
7fb8c56c | 312 | { |
9a1870ce | 313 | return false; |
7fb8c56c HK |
314 | } |
315 | ||
0788c39b HK |
316 | static bool dw8250_idma_filter(struct dma_chan *chan, void *param) |
317 | { | |
83ce95ef | 318 | return param == chan->device->dev->parent; |
0788c39b HK |
319 | } |
320 | ||
9e08fa50 | 321 | static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) |
6a7320c4 | 322 | { |
9e08fa50 HK |
323 | if (p->dev->of_node) { |
324 | struct device_node *np = p->dev->of_node; | |
325 | int id; | |
326 | ||
327 | /* get index of serial line, if found in DT aliases */ | |
328 | id = of_alias_get_id(np, "serial"); | |
329 | if (id >= 0) | |
330 | p->line = id; | |
331 | #ifdef CONFIG_64BIT | |
332 | if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { | |
333 | p->serial_in = dw8250_serial_inq; | |
334 | p->serial_out = dw8250_serial_outq; | |
335 | p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; | |
336 | p->type = PORT_OCTEON; | |
337 | data->usr_reg = 0x27; | |
338 | data->skip_autocfg = true; | |
339 | } | |
340 | #endif | |
46250901 NC |
341 | if (of_device_is_big_endian(p->dev->of_node)) { |
342 | p->iotype = UPIO_MEM32BE; | |
343 | p->serial_in = dw8250_serial_in32be; | |
344 | p->serial_out = dw8250_serial_out32be; | |
345 | } | |
9e08fa50 | 346 | } else if (has_acpi_companion(p->dev)) { |
20a875e2 HK |
347 | const struct acpi_device_id *id; |
348 | ||
349 | id = acpi_match_device(p->dev->driver->acpi_match_table, | |
350 | p->dev); | |
351 | if (id && !strcmp(id->id, "APMC0D08")) { | |
352 | p->iotype = UPIO_MEM32; | |
353 | p->regshift = 2; | |
354 | p->serial_in = dw8250_serial_in32; | |
355 | data->uart_16550_compatible = true; | |
356 | } | |
9e08fa50 | 357 | } |
aea02e87 | 358 | |
0788c39b | 359 | /* Platforms with iDMA */ |
9e08fa50 | 360 | if (platform_get_resource_byname(to_platform_device(p->dev), |
0788c39b | 361 | IORESOURCE_MEM, "lpss_priv")) { |
9e08fa50 HK |
362 | data->dma.rx_param = p->dev->parent; |
363 | data->dma.tx_param = p->dev->parent; | |
0788c39b HK |
364 | data->dma.fn = dw8250_idma_filter; |
365 | } | |
6a7320c4 HK |
366 | } |
367 | ||
2338a75e HK |
368 | static void dw8250_setup_port(struct uart_port *p) |
369 | { | |
370 | struct uart_8250_port *up = up_to_u8250p(p); | |
371 | u32 reg; | |
372 | ||
373 | /* | |
374 | * If the Component Version Register returns zero, we know that | |
375 | * ADDITIONAL_FEATURES are not enabled. No need to go any further. | |
376 | */ | |
5a43140c NC |
377 | if (p->iotype == UPIO_MEM32BE) |
378 | reg = ioread32be(p->membase + DW_UART_UCV); | |
379 | else | |
380 | reg = readl(p->membase + DW_UART_UCV); | |
2338a75e HK |
381 | if (!reg) |
382 | return; | |
383 | ||
384 | dev_dbg(p->dev, "Designware UART version %c.%c%c\n", | |
385 | (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); | |
386 | ||
5a43140c NC |
387 | if (p->iotype == UPIO_MEM32BE) |
388 | reg = ioread32be(p->membase + DW_UART_CPR); | |
389 | else | |
390 | reg = readl(p->membase + DW_UART_CPR); | |
2338a75e HK |
391 | if (!reg) |
392 | return; | |
393 | ||
394 | /* Select the type based on fifo */ | |
395 | if (reg & DW_UART_CPR_FIFO_MODE) { | |
396 | p->type = PORT_16550A; | |
397 | p->flags |= UPF_FIXED_TYPE; | |
398 | p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); | |
399 | up->capabilities = UART_CAP_FIFO; | |
400 | } | |
401 | ||
402 | if (reg & DW_UART_CPR_AFCE_MODE) | |
403 | up->capabilities |= UART_CAP_AFE; | |
0e0b989e EB |
404 | |
405 | if (reg & DW_UART_CPR_SIR_MODE) | |
406 | up->capabilities |= UART_CAP_IRDA; | |
2338a75e HK |
407 | } |
408 | ||
9671f099 | 409 | static int dw8250_probe(struct platform_device *pdev) |
7d4008eb | 410 | { |
2655a2c7 | 411 | struct uart_8250_port uart = {}; |
7d4008eb | 412 | struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
833b1f7b | 413 | int irq = platform_get_irq(pdev, 0); |
78d3da75 | 414 | struct uart_port *p = &uart.port; |
2cb78eab | 415 | struct device *dev = &pdev->dev; |
7d4008eb | 416 | struct dw8250_data *data; |
a7260c8c | 417 | int err; |
1bd8edba | 418 | u32 val; |
7d4008eb | 419 | |
833b1f7b | 420 | if (!regs) { |
2cb78eab | 421 | dev_err(dev, "no registers defined\n"); |
7d4008eb JI |
422 | return -EINVAL; |
423 | } | |
424 | ||
833b1f7b AB |
425 | if (irq < 0) { |
426 | if (irq != -EPROBE_DEFER) | |
2cb78eab | 427 | dev_err(dev, "cannot get irq\n"); |
833b1f7b AB |
428 | return irq; |
429 | } | |
430 | ||
78d3da75 HK |
431 | spin_lock_init(&p->lock); |
432 | p->mapbase = regs->start; | |
433 | p->irq = irq; | |
434 | p->handle_irq = dw8250_handle_irq; | |
435 | p->pm = dw8250_do_pm; | |
436 | p->type = PORT_8250; | |
7693c79c | 437 | p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; |
2cb78eab | 438 | p->dev = dev; |
78d3da75 HK |
439 | p->iotype = UPIO_MEM; |
440 | p->serial_in = dw8250_serial_in; | |
441 | p->serial_out = dw8250_serial_out; | |
0e0b989e | 442 | p->set_ldisc = dw8250_set_ldisc; |
6a171b29 | 443 | p->set_termios = dw8250_set_termios; |
78d3da75 | 444 | |
2cb78eab | 445 | p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); |
78d3da75 | 446 | if (!p->membase) |
f93366ff HK |
447 | return -ENOMEM; |
448 | ||
2cb78eab | 449 | data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); |
e302cd93 EL |
450 | if (!data) |
451 | return -ENOMEM; | |
452 | ||
1edb3cf2 | 453 | data->dma.fn = dw8250_fallback_dma_filter; |
d5f1af7e | 454 | data->usr_reg = DW_UART_USR; |
78d3da75 | 455 | p->private_data = data; |
23f5b3fd | 456 | |
2cb78eab | 457 | data->uart_16550_compatible = device_property_read_bool(dev, |
c73942e2 HK |
458 | "snps,uart-16550-compatible"); |
459 | ||
2cb78eab | 460 | err = device_property_read_u32(dev, "reg-shift", &val); |
1bd8edba HK |
461 | if (!err) |
462 | p->regshift = val; | |
463 | ||
2cb78eab | 464 | err = device_property_read_u32(dev, "reg-io-width", &val); |
1bd8edba HK |
465 | if (!err && val == 4) { |
466 | p->iotype = UPIO_MEM32; | |
467 | p->serial_in = dw8250_serial_in32; | |
468 | p->serial_out = dw8250_serial_out32; | |
469 | } | |
470 | ||
2cb78eab | 471 | if (device_property_read_bool(dev, "dcd-override")) { |
1bd8edba HK |
472 | /* Always report DCD as active */ |
473 | data->msr_mask_on |= UART_MSR_DCD; | |
474 | data->msr_mask_off |= UART_MSR_DDCD; | |
475 | } | |
476 | ||
2cb78eab | 477 | if (device_property_read_bool(dev, "dsr-override")) { |
1bd8edba HK |
478 | /* Always report DSR as active */ |
479 | data->msr_mask_on |= UART_MSR_DSR; | |
480 | data->msr_mask_off |= UART_MSR_DDSR; | |
481 | } | |
482 | ||
2cb78eab | 483 | if (device_property_read_bool(dev, "cts-override")) { |
1bd8edba HK |
484 | /* Always report CTS as active */ |
485 | data->msr_mask_on |= UART_MSR_CTS; | |
486 | data->msr_mask_off |= UART_MSR_DCTS; | |
487 | } | |
488 | ||
2cb78eab | 489 | if (device_property_read_bool(dev, "ri-override")) { |
1bd8edba HK |
490 | /* Always report Ring indicator as inactive */ |
491 | data->msr_mask_off |= UART_MSR_RI; | |
492 | data->msr_mask_off |= UART_MSR_TERI; | |
493 | } | |
494 | ||
23f5b3fd | 495 | /* Always ask for fixed clock rate from a property. */ |
2cb78eab | 496 | device_property_read_u32(dev, "clock-frequency", &p->uartclk); |
23f5b3fd HK |
497 | |
498 | /* If there is separate baudclk, get the rate from it. */ | |
2cb78eab | 499 | data->clk = devm_clk_get(dev, "baudclk"); |
c8ed99d4 | 500 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) |
2cb78eab | 501 | data->clk = devm_clk_get(dev, NULL); |
c8ed99d4 CYT |
502 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) |
503 | return -EPROBE_DEFER; | |
23f5b3fd | 504 | if (!IS_ERR_OR_NULL(data->clk)) { |
7d78cbef HS |
505 | err = clk_prepare_enable(data->clk); |
506 | if (err) | |
2cb78eab | 507 | dev_warn(dev, "could not enable optional baudclk: %d\n", |
7d78cbef HS |
508 | err); |
509 | else | |
78d3da75 | 510 | p->uartclk = clk_get_rate(data->clk); |
7d78cbef HS |
511 | } |
512 | ||
23f5b3fd | 513 | /* If no clock rate is defined, fail. */ |
78d3da75 | 514 | if (!p->uartclk) { |
2cb78eab | 515 | dev_err(dev, "clock rate not defined\n"); |
23f5b3fd HK |
516 | return -EINVAL; |
517 | } | |
518 | ||
2cb78eab | 519 | data->pclk = devm_clk_get(dev, "apb_pclk"); |
e16b46f1 | 520 | if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) { |
c8ed99d4 CYT |
521 | err = -EPROBE_DEFER; |
522 | goto err_clk; | |
523 | } | |
7d78cbef HS |
524 | if (!IS_ERR(data->pclk)) { |
525 | err = clk_prepare_enable(data->pclk); | |
526 | if (err) { | |
2cb78eab | 527 | dev_err(dev, "could not enable apb_pclk\n"); |
c8ed99d4 | 528 | goto err_clk; |
7d78cbef | 529 | } |
e302cd93 EL |
530 | } |
531 | ||
2cb78eab | 532 | data->rst = devm_reset_control_get_optional(dev, NULL); |
c8ed99d4 CYT |
533 | if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) { |
534 | err = -EPROBE_DEFER; | |
535 | goto err_pclk; | |
536 | } | |
7fe090bf CYT |
537 | if (!IS_ERR(data->rst)) |
538 | reset_control_deassert(data->rst); | |
539 | ||
9e08fa50 | 540 | dw8250_quirks(p, data); |
7d4008eb | 541 | |
c73942e2 | 542 | /* If the Busy Functionality is not implemented, don't handle it */ |
cdcea058 | 543 | if (data->uart_16550_compatible) |
c73942e2 | 544 | p->handle_irq = NULL; |
c73942e2 | 545 | |
4f042054 | 546 | if (!data->skip_autocfg) |
2338a75e | 547 | dw8250_setup_port(p); |
4f042054 | 548 | |
2559318c HK |
549 | /* If we have a valid fifosize, try hooking up DMA */ |
550 | if (p->fifosize) { | |
551 | data->dma.rxconf.src_maxburst = p->fifosize / 4; | |
552 | data->dma.txconf.dst_maxburst = p->fifosize / 4; | |
553 | uart.dma = &data->dma; | |
554 | } | |
555 | ||
2655a2c7 | 556 | data->line = serial8250_register_8250_port(&uart); |
c8ed99d4 CYT |
557 | if (data->line < 0) { |
558 | err = data->line; | |
559 | goto err_reset; | |
560 | } | |
7d4008eb JI |
561 | |
562 | platform_set_drvdata(pdev, data); | |
563 | ||
2cb78eab KW |
564 | pm_runtime_set_active(dev); |
565 | pm_runtime_enable(dev); | |
ffc3ae6d | 566 | |
7d4008eb | 567 | return 0; |
c8ed99d4 CYT |
568 | |
569 | err_reset: | |
570 | if (!IS_ERR(data->rst)) | |
571 | reset_control_assert(data->rst); | |
572 | ||
573 | err_pclk: | |
574 | if (!IS_ERR(data->pclk)) | |
575 | clk_disable_unprepare(data->pclk); | |
576 | ||
577 | err_clk: | |
578 | if (!IS_ERR(data->clk)) | |
579 | clk_disable_unprepare(data->clk); | |
580 | ||
581 | return err; | |
7d4008eb JI |
582 | } |
583 | ||
ae8d8a14 | 584 | static int dw8250_remove(struct platform_device *pdev) |
7d4008eb JI |
585 | { |
586 | struct dw8250_data *data = platform_get_drvdata(pdev); | |
587 | ||
ffc3ae6d HK |
588 | pm_runtime_get_sync(&pdev->dev); |
589 | ||
7d4008eb JI |
590 | serial8250_unregister_port(data->line); |
591 | ||
7fe090bf CYT |
592 | if (!IS_ERR(data->rst)) |
593 | reset_control_assert(data->rst); | |
594 | ||
7d78cbef HS |
595 | if (!IS_ERR(data->pclk)) |
596 | clk_disable_unprepare(data->pclk); | |
597 | ||
e302cd93 EL |
598 | if (!IS_ERR(data->clk)) |
599 | clk_disable_unprepare(data->clk); | |
600 | ||
ffc3ae6d HK |
601 | pm_runtime_disable(&pdev->dev); |
602 | pm_runtime_put_noidle(&pdev->dev); | |
603 | ||
7d4008eb JI |
604 | return 0; |
605 | } | |
606 | ||
13b949f0 | 607 | #ifdef CONFIG_PM_SLEEP |
ffc3ae6d | 608 | static int dw8250_suspend(struct device *dev) |
b61c5ed5 | 609 | { |
ffc3ae6d | 610 | struct dw8250_data *data = dev_get_drvdata(dev); |
b61c5ed5 JH |
611 | |
612 | serial8250_suspend_port(data->line); | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
ffc3ae6d | 617 | static int dw8250_resume(struct device *dev) |
b61c5ed5 | 618 | { |
ffc3ae6d | 619 | struct dw8250_data *data = dev_get_drvdata(dev); |
b61c5ed5 JH |
620 | |
621 | serial8250_resume_port(data->line); | |
622 | ||
623 | return 0; | |
624 | } | |
13b949f0 | 625 | #endif /* CONFIG_PM_SLEEP */ |
b61c5ed5 | 626 | |
d39fe4e5 | 627 | #ifdef CONFIG_PM |
ffc3ae6d HK |
628 | static int dw8250_runtime_suspend(struct device *dev) |
629 | { | |
630 | struct dw8250_data *data = dev_get_drvdata(dev); | |
631 | ||
dbd2df85 EG |
632 | if (!IS_ERR(data->clk)) |
633 | clk_disable_unprepare(data->clk); | |
ffc3ae6d | 634 | |
7d78cbef HS |
635 | if (!IS_ERR(data->pclk)) |
636 | clk_disable_unprepare(data->pclk); | |
637 | ||
ffc3ae6d HK |
638 | return 0; |
639 | } | |
640 | ||
641 | static int dw8250_runtime_resume(struct device *dev) | |
642 | { | |
643 | struct dw8250_data *data = dev_get_drvdata(dev); | |
644 | ||
7d78cbef HS |
645 | if (!IS_ERR(data->pclk)) |
646 | clk_prepare_enable(data->pclk); | |
647 | ||
dbd2df85 EG |
648 | if (!IS_ERR(data->clk)) |
649 | clk_prepare_enable(data->clk); | |
ffc3ae6d HK |
650 | |
651 | return 0; | |
652 | } | |
653 | #endif | |
654 | ||
655 | static const struct dev_pm_ops dw8250_pm_ops = { | |
656 | SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) | |
657 | SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) | |
658 | }; | |
659 | ||
a7260c8c | 660 | static const struct of_device_id dw8250_of_match[] = { |
7d4008eb | 661 | { .compatible = "snps,dw-apb-uart" }, |
d5f1af7e | 662 | { .compatible = "cavium,octeon-3860-uart" }, |
7d4008eb JI |
663 | { /* Sentinel */ } |
664 | }; | |
a7260c8c | 665 | MODULE_DEVICE_TABLE(of, dw8250_of_match); |
7d4008eb | 666 | |
6a7320c4 | 667 | static const struct acpi_device_id dw8250_acpi_match[] = { |
aea02e87 HK |
668 | { "INT33C4", 0 }, |
669 | { "INT33C5", 0 }, | |
d24c195f MW |
670 | { "INT3434", 0 }, |
671 | { "INT3435", 0 }, | |
4e26b134 | 672 | { "80860F0A", 0 }, |
f174442e | 673 | { "8086228A", 0 }, |
5e1aeea5 | 674 | { "APMC0D08", 0}, |
5ef86b74 | 675 | { "AMD0020", 0 }, |
204e986d | 676 | { "AMDI0020", 0 }, |
e06b6b85 | 677 | { "HISI0031", 0 }, |
6a7320c4 HK |
678 | { }, |
679 | }; | |
680 | MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); | |
681 | ||
7d4008eb JI |
682 | static struct platform_driver dw8250_platform_driver = { |
683 | .driver = { | |
684 | .name = "dw-apb-uart", | |
ffc3ae6d | 685 | .pm = &dw8250_pm_ops, |
a7260c8c | 686 | .of_match_table = dw8250_of_match, |
6a7320c4 | 687 | .acpi_match_table = ACPI_PTR(dw8250_acpi_match), |
7d4008eb JI |
688 | }, |
689 | .probe = dw8250_probe, | |
2d47b716 | 690 | .remove = dw8250_remove, |
7d4008eb JI |
691 | }; |
692 | ||
c8381c15 | 693 | module_platform_driver(dw8250_platform_driver); |
7d4008eb JI |
694 | |
695 | MODULE_AUTHOR("Jamie Iles"); | |
696 | MODULE_LICENSE("GPL"); | |
697 | MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); | |
f3ac3fc2 | 698 | MODULE_ALIAS("platform:dw-apb-uart"); |