]>
Commit | Line | Data |
---|---|---|
7d4008eb JI |
1 | /* |
2 | * Synopsys DesignWare 8250 driver. | |
3 | * | |
4 | * Copyright 2011 Picochip, Jamie Iles. | |
6a7320c4 | 5 | * Copyright 2013 Intel Corporation |
7d4008eb JI |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the | |
13 | * LCR is written whilst busy. If it is, then a busy detect interrupt is | |
14 | * raised, the LCR needs to be rewritten and the uart status register read. | |
15 | */ | |
16 | #include <linux/device.h> | |
7d4008eb JI |
17 | #include <linux/io.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/serial_8250.h> | |
7d4008eb JI |
20 | #include <linux/serial_reg.h> |
21 | #include <linux/of.h> | |
22 | #include <linux/of_irq.h> | |
23 | #include <linux/of_platform.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/slab.h> | |
6a7320c4 | 26 | #include <linux/acpi.h> |
e302cd93 | 27 | #include <linux/clk.h> |
7fe090bf | 28 | #include <linux/reset.h> |
ffc3ae6d | 29 | #include <linux/pm_runtime.h> |
7d4008eb | 30 | |
d5f1af7e DD |
31 | #include <asm/byteorder.h> |
32 | ||
7277b2a1 HK |
33 | #include "8250.h" |
34 | ||
30046df2 HK |
35 | /* Offsets for the DesignWare specific registers */ |
36 | #define DW_UART_USR 0x1f /* UART Status Register */ | |
37 | #define DW_UART_CPR 0xf4 /* Component Parameter Register */ | |
38 | #define DW_UART_UCV 0xf8 /* UART Component Version */ | |
39 | ||
40 | /* Component Parameter Register bits */ | |
41 | #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) | |
42 | #define DW_UART_CPR_AFCE_MODE (1 << 4) | |
43 | #define DW_UART_CPR_THRE_MODE (1 << 5) | |
44 | #define DW_UART_CPR_SIR_MODE (1 << 6) | |
45 | #define DW_UART_CPR_SIR_LP_MODE (1 << 7) | |
46 | #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) | |
47 | #define DW_UART_CPR_FIFO_ACCESS (1 << 9) | |
48 | #define DW_UART_CPR_FIFO_STAT (1 << 10) | |
49 | #define DW_UART_CPR_SHADOW (1 << 11) | |
50 | #define DW_UART_CPR_ENCODED_PARMS (1 << 12) | |
51 | #define DW_UART_CPR_DMA_EXTRA (1 << 13) | |
52 | #define DW_UART_CPR_FIFO_MODE (0xff << 16) | |
53 | /* Helper for fifo size calculation */ | |
54 | #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) | |
55 | ||
56 | ||
7d4008eb | 57 | struct dw8250_data { |
fe958555 | 58 | u8 usr_reg; |
fe958555 | 59 | int line; |
dfd37668 DL |
60 | int msr_mask_on; |
61 | int msr_mask_off; | |
fe958555 | 62 | struct clk *clk; |
7d78cbef | 63 | struct clk *pclk; |
7fe090bf | 64 | struct reset_control *rst; |
fe958555 | 65 | struct uart_8250_dma dma; |
7d4008eb JI |
66 | }; |
67 | ||
c439c33d LP |
68 | #define BYT_PRV_CLK 0x800 |
69 | #define BYT_PRV_CLK_EN (1 << 0) | |
70 | #define BYT_PRV_CLK_M_VAL_SHIFT 1 | |
71 | #define BYT_PRV_CLK_N_VAL_SHIFT 16 | |
72 | #define BYT_PRV_CLK_UPDATE (1 << 31) | |
73 | ||
33acbb82 TK |
74 | static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) |
75 | { | |
76 | struct dw8250_data *d = p->private_data; | |
77 | ||
dfd37668 DL |
78 | /* Override any modem control signals if needed */ |
79 | if (offset == UART_MSR) { | |
80 | value |= d->msr_mask_on; | |
81 | value &= ~d->msr_mask_off; | |
82 | } | |
83 | ||
33acbb82 TK |
84 | return value; |
85 | } | |
86 | ||
c49436b6 TK |
87 | static void dw8250_force_idle(struct uart_port *p) |
88 | { | |
b1261c86 AS |
89 | struct uart_8250_port *up = up_to_u8250p(p); |
90 | ||
91 | serial8250_clear_and_reinit_fifos(up); | |
c49436b6 TK |
92 | (void)p->serial_in(p, UART_RX); |
93 | } | |
94 | ||
7d4008eb JI |
95 | static void dw8250_serial_out(struct uart_port *p, int offset, int value) |
96 | { | |
33acbb82 | 97 | writeb(value, p->membase + (offset << p->regshift)); |
c49436b6 TK |
98 | |
99 | /* Make sure LCR write wasn't ignored */ | |
100 | if (offset == UART_LCR) { | |
101 | int tries = 1000; | |
102 | while (tries--) { | |
6979f8d2 JH |
103 | unsigned int lcr = p->serial_in(p, UART_LCR); |
104 | if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) | |
c49436b6 TK |
105 | return; |
106 | dw8250_force_idle(p); | |
107 | writeb(value, p->membase + (UART_LCR << p->regshift)); | |
108 | } | |
7fd6f640 PH |
109 | /* |
110 | * FIXME: this deadlocks if port->lock is already held | |
111 | * dev_err(p->dev, "Couldn't set LCR to %d\n", value); | |
112 | */ | |
c49436b6 | 113 | } |
7d4008eb JI |
114 | } |
115 | ||
116 | static unsigned int dw8250_serial_in(struct uart_port *p, int offset) | |
117 | { | |
33acbb82 | 118 | unsigned int value = readb(p->membase + (offset << p->regshift)); |
7d4008eb | 119 | |
33acbb82 | 120 | return dw8250_modify_msr(p, offset, value); |
7d4008eb JI |
121 | } |
122 | ||
bca2092d DD |
123 | #ifdef CONFIG_64BIT |
124 | static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) | |
d5f1af7e | 125 | { |
bca2092d DD |
126 | unsigned int value; |
127 | ||
128 | value = (u8)__raw_readq(p->membase + (offset << p->regshift)); | |
129 | ||
130 | return dw8250_modify_msr(p, offset, value); | |
d5f1af7e DD |
131 | } |
132 | ||
bca2092d DD |
133 | static void dw8250_serial_outq(struct uart_port *p, int offset, int value) |
134 | { | |
bca2092d DD |
135 | value &= 0xff; |
136 | __raw_writeq(value, p->membase + (offset << p->regshift)); | |
137 | /* Read back to ensure register write ordering. */ | |
138 | __raw_readq(p->membase + (UART_LCR << p->regshift)); | |
139 | ||
140 | /* Make sure LCR write wasn't ignored */ | |
141 | if (offset == UART_LCR) { | |
142 | int tries = 1000; | |
143 | while (tries--) { | |
144 | unsigned int lcr = p->serial_in(p, UART_LCR); | |
145 | if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) | |
146 | return; | |
147 | dw8250_force_idle(p); | |
148 | __raw_writeq(value & 0xff, | |
149 | p->membase + (UART_LCR << p->regshift)); | |
150 | } | |
7fd6f640 PH |
151 | /* |
152 | * FIXME: this deadlocks if port->lock is already held | |
153 | * dev_err(p->dev, "Couldn't set LCR to %d\n", value); | |
154 | */ | |
bca2092d DD |
155 | } |
156 | } | |
157 | #endif /* CONFIG_64BIT */ | |
158 | ||
7d4008eb JI |
159 | static void dw8250_serial_out32(struct uart_port *p, int offset, int value) |
160 | { | |
33acbb82 | 161 | writel(value, p->membase + (offset << p->regshift)); |
c49436b6 TK |
162 | |
163 | /* Make sure LCR write wasn't ignored */ | |
164 | if (offset == UART_LCR) { | |
165 | int tries = 1000; | |
166 | while (tries--) { | |
6979f8d2 JH |
167 | unsigned int lcr = p->serial_in(p, UART_LCR); |
168 | if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) | |
c49436b6 TK |
169 | return; |
170 | dw8250_force_idle(p); | |
171 | writel(value, p->membase + (UART_LCR << p->regshift)); | |
172 | } | |
7fd6f640 PH |
173 | /* |
174 | * FIXME: this deadlocks if port->lock is already held | |
175 | * dev_err(p->dev, "Couldn't set LCR to %d\n", value); | |
176 | */ | |
c49436b6 | 177 | } |
7d4008eb JI |
178 | } |
179 | ||
180 | static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) | |
181 | { | |
33acbb82 | 182 | unsigned int value = readl(p->membase + (offset << p->regshift)); |
7d4008eb | 183 | |
33acbb82 | 184 | return dw8250_modify_msr(p, offset, value); |
7d4008eb JI |
185 | } |
186 | ||
7d4008eb JI |
187 | static int dw8250_handle_irq(struct uart_port *p) |
188 | { | |
189 | struct dw8250_data *d = p->private_data; | |
190 | unsigned int iir = p->serial_in(p, UART_IIR); | |
191 | ||
192 | if (serial8250_handle_irq(p, iir)) { | |
193 | return 1; | |
194 | } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { | |
c49436b6 | 195 | /* Clear the USR */ |
d5f1af7e | 196 | (void)p->serial_in(p, d->usr_reg); |
7d4008eb JI |
197 | |
198 | return 1; | |
199 | } | |
200 | ||
201 | return 0; | |
202 | } | |
203 | ||
ffc3ae6d HK |
204 | static void |
205 | dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) | |
206 | { | |
207 | if (!state) | |
208 | pm_runtime_get_sync(port->dev); | |
209 | ||
210 | serial8250_do_pm(port, state, old); | |
211 | ||
212 | if (state) | |
213 | pm_runtime_put_sync_suspend(port->dev); | |
214 | } | |
215 | ||
4e26b134 HK |
216 | static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, |
217 | struct ktermios *old) | |
218 | { | |
219 | unsigned int baud = tty_termios_baud_rate(termios); | |
220 | struct dw8250_data *d = p->private_data; | |
221 | unsigned int rate; | |
222 | int ret; | |
223 | ||
224 | if (IS_ERR(d->clk) || !old) | |
225 | goto out; | |
226 | ||
227 | /* Not requesting clock rates below 1.8432Mhz */ | |
228 | if (baud < 115200) | |
229 | baud = 115200; | |
230 | ||
231 | clk_disable_unprepare(d->clk); | |
232 | rate = clk_round_rate(d->clk, baud * 16); | |
233 | ret = clk_set_rate(d->clk, rate); | |
234 | clk_prepare_enable(d->clk); | |
235 | ||
236 | if (!ret) | |
237 | p->uartclk = rate; | |
0a6c301a QZ |
238 | |
239 | p->status &= ~UPSTAT_AUTOCTS; | |
240 | if (termios->c_cflag & CRTSCTS) | |
241 | p->status |= UPSTAT_AUTOCTS; | |
242 | ||
4e26b134 HK |
243 | out: |
244 | serial8250_do_set_termios(p, termios, old); | |
245 | } | |
246 | ||
7fb8c56c HK |
247 | static bool dw8250_dma_filter(struct dma_chan *chan, void *param) |
248 | { | |
9a1870ce | 249 | return false; |
7fb8c56c HK |
250 | } |
251 | ||
d5f1af7e DD |
252 | static void dw8250_setup_port(struct uart_8250_port *up) |
253 | { | |
254 | struct uart_port *p = &up->port; | |
255 | u32 reg = readl(p->membase + DW_UART_UCV); | |
256 | ||
257 | /* | |
258 | * If the Component Version Register returns zero, we know that | |
259 | * ADDITIONAL_FEATURES are not enabled. No need to go any further. | |
260 | */ | |
261 | if (!reg) | |
262 | return; | |
263 | ||
264 | dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n", | |
265 | (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); | |
266 | ||
267 | reg = readl(p->membase + DW_UART_CPR); | |
268 | if (!reg) | |
269 | return; | |
270 | ||
271 | /* Select the type based on fifo */ | |
272 | if (reg & DW_UART_CPR_FIFO_MODE) { | |
273 | p->type = PORT_16550A; | |
274 | p->flags |= UPF_FIXED_TYPE; | |
275 | p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); | |
276 | up->tx_loadsz = p->fifosize; | |
277 | up->capabilities = UART_CAP_FIFO; | |
278 | } | |
279 | ||
280 | if (reg & DW_UART_CPR_AFCE_MODE) | |
281 | up->capabilities |= UART_CAP_AFE; | |
282 | } | |
283 | ||
284 | static int dw8250_probe_of(struct uart_port *p, | |
285 | struct dw8250_data *data) | |
a7260c8c HK |
286 | { |
287 | struct device_node *np = p->dev->of_node; | |
b1261c86 | 288 | struct uart_8250_port *up = up_to_u8250p(p); |
a7260c8c | 289 | u32 val; |
d5f1af7e | 290 | bool has_ucv = true; |
f77d55a3 | 291 | int id; |
d5f1af7e | 292 | |
bca2092d | 293 | #ifdef CONFIG_64BIT |
d5f1af7e | 294 | if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { |
bca2092d DD |
295 | p->serial_in = dw8250_serial_inq; |
296 | p->serial_out = dw8250_serial_outq; | |
d8782c74 | 297 | p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; |
d5f1af7e DD |
298 | p->type = PORT_OCTEON; |
299 | data->usr_reg = 0x27; | |
300 | has_ucv = false; | |
bca2092d DD |
301 | } else |
302 | #endif | |
303 | if (!of_property_read_u32(np, "reg-io-width", &val)) { | |
a7260c8c HK |
304 | switch (val) { |
305 | case 1: | |
306 | break; | |
307 | case 4: | |
308 | p->iotype = UPIO_MEM32; | |
309 | p->serial_in = dw8250_serial_in32; | |
310 | p->serial_out = dw8250_serial_out32; | |
311 | break; | |
312 | default: | |
313 | dev_err(p->dev, "unsupported reg-io-width (%u)\n", val); | |
314 | return -EINVAL; | |
315 | } | |
316 | } | |
d5f1af7e | 317 | if (has_ucv) |
b1261c86 | 318 | dw8250_setup_port(up); |
a7260c8c | 319 | |
a8b26e1a RJ |
320 | /* if we have a valid fifosize, try hooking up DMA here */ |
321 | if (p->fifosize) { | |
322 | up->dma = &data->dma; | |
323 | ||
324 | up->dma->rxconf.src_maxburst = p->fifosize / 4; | |
325 | up->dma->txconf.dst_maxburst = p->fifosize / 4; | |
326 | } | |
327 | ||
a7260c8c HK |
328 | if (!of_property_read_u32(np, "reg-shift", &val)) |
329 | p->regshift = val; | |
330 | ||
f77d55a3 JC |
331 | /* get index of serial line, if found in DT aliases */ |
332 | id = of_alias_get_id(np, "serial"); | |
333 | if (id >= 0) | |
334 | p->line = id; | |
335 | ||
dfd37668 DL |
336 | if (of_property_read_bool(np, "dcd-override")) { |
337 | /* Always report DCD as active */ | |
338 | data->msr_mask_on |= UART_MSR_DCD; | |
339 | data->msr_mask_off |= UART_MSR_DDCD; | |
340 | } | |
341 | ||
342 | if (of_property_read_bool(np, "dsr-override")) { | |
343 | /* Always report DSR as active */ | |
344 | data->msr_mask_on |= UART_MSR_DSR; | |
345 | data->msr_mask_off |= UART_MSR_DDSR; | |
346 | } | |
347 | ||
348 | if (of_property_read_bool(np, "cts-override")) { | |
da29169e DT |
349 | /* Always report CTS as active */ |
350 | data->msr_mask_on |= UART_MSR_CTS; | |
351 | data->msr_mask_off |= UART_MSR_DCTS; | |
dfd37668 DL |
352 | } |
353 | ||
354 | if (of_property_read_bool(np, "ri-override")) { | |
355 | /* Always report Ring indicator as inactive */ | |
356 | data->msr_mask_off |= UART_MSR_RI; | |
357 | data->msr_mask_off |= UART_MSR_TERI; | |
358 | } | |
359 | ||
a7260c8c HK |
360 | return 0; |
361 | } | |
362 | ||
0788c39b HK |
363 | static bool dw8250_idma_filter(struct dma_chan *chan, void *param) |
364 | { | |
365 | struct device *dev = param; | |
366 | ||
367 | if (dev != chan->device->dev->parent) | |
368 | return false; | |
369 | ||
370 | return true; | |
371 | } | |
372 | ||
fe958555 HK |
373 | static int dw8250_probe_acpi(struct uart_8250_port *up, |
374 | struct dw8250_data *data) | |
6a7320c4 | 375 | { |
94b2b47c | 376 | struct uart_port *p = &up->port; |
6a7320c4 | 377 | |
d5f1af7e DD |
378 | dw8250_setup_port(up); |
379 | ||
6a7320c4 HK |
380 | p->iotype = UPIO_MEM32; |
381 | p->serial_in = dw8250_serial_in32; | |
382 | p->serial_out = dw8250_serial_out32; | |
383 | p->regshift = 2; | |
aea02e87 | 384 | |
0788c39b HK |
385 | /* Platforms with iDMA */ |
386 | if (platform_get_resource_byname(to_platform_device(up->port.dev), | |
387 | IORESOURCE_MEM, "lpss_priv")) { | |
388 | data->dma.rx_param = up->port.dev->parent; | |
389 | data->dma.tx_param = up->port.dev->parent; | |
390 | data->dma.fn = dw8250_idma_filter; | |
391 | } | |
94b2b47c | 392 | |
0788c39b | 393 | up->dma = &data->dma; |
94b2b47c HK |
394 | up->dma->rxconf.src_maxburst = p->fifosize / 4; |
395 | up->dma->txconf.dst_maxburst = p->fifosize / 4; | |
7277b2a1 | 396 | |
4e26b134 | 397 | up->port.set_termios = dw8250_set_termios; |
c439c33d | 398 | |
6a7320c4 HK |
399 | return 0; |
400 | } | |
401 | ||
9671f099 | 402 | static int dw8250_probe(struct platform_device *pdev) |
7d4008eb | 403 | { |
2655a2c7 | 404 | struct uart_8250_port uart = {}; |
7d4008eb | 405 | struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
833b1f7b | 406 | int irq = platform_get_irq(pdev, 0); |
7d4008eb | 407 | struct dw8250_data *data; |
a7260c8c | 408 | int err; |
7d4008eb | 409 | |
833b1f7b AB |
410 | if (!regs) { |
411 | dev_err(&pdev->dev, "no registers defined\n"); | |
7d4008eb JI |
412 | return -EINVAL; |
413 | } | |
414 | ||
833b1f7b AB |
415 | if (irq < 0) { |
416 | if (irq != -EPROBE_DEFER) | |
417 | dev_err(&pdev->dev, "cannot get irq\n"); | |
418 | return irq; | |
419 | } | |
420 | ||
2655a2c7 AC |
421 | spin_lock_init(&uart.port.lock); |
422 | uart.port.mapbase = regs->start; | |
833b1f7b | 423 | uart.port.irq = irq; |
2655a2c7 | 424 | uart.port.handle_irq = dw8250_handle_irq; |
ffc3ae6d | 425 | uart.port.pm = dw8250_do_pm; |
2655a2c7 | 426 | uart.port.type = PORT_8250; |
f93366ff | 427 | uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT; |
2655a2c7 | 428 | uart.port.dev = &pdev->dev; |
7d4008eb | 429 | |
b88d0826 HK |
430 | uart.port.membase = devm_ioremap(&pdev->dev, regs->start, |
431 | resource_size(regs)); | |
f93366ff HK |
432 | if (!uart.port.membase) |
433 | return -ENOMEM; | |
434 | ||
e302cd93 EL |
435 | data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); |
436 | if (!data) | |
437 | return -ENOMEM; | |
438 | ||
d5f1af7e | 439 | data->usr_reg = DW_UART_USR; |
23f5b3fd HK |
440 | |
441 | /* Always ask for fixed clock rate from a property. */ | |
442 | device_property_read_u32(&pdev->dev, "clock-frequency", | |
443 | &uart.port.uartclk); | |
444 | ||
445 | /* If there is separate baudclk, get the rate from it. */ | |
7d78cbef | 446 | data->clk = devm_clk_get(&pdev->dev, "baudclk"); |
c8ed99d4 | 447 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) |
7d78cbef | 448 | data->clk = devm_clk_get(&pdev->dev, NULL); |
c8ed99d4 CYT |
449 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) |
450 | return -EPROBE_DEFER; | |
23f5b3fd | 451 | if (!IS_ERR_OR_NULL(data->clk)) { |
7d78cbef HS |
452 | err = clk_prepare_enable(data->clk); |
453 | if (err) | |
454 | dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n", | |
455 | err); | |
456 | else | |
457 | uart.port.uartclk = clk_get_rate(data->clk); | |
458 | } | |
459 | ||
23f5b3fd HK |
460 | /* If no clock rate is defined, fail. */ |
461 | if (!uart.port.uartclk) { | |
462 | dev_err(&pdev->dev, "clock rate not defined\n"); | |
463 | return -EINVAL; | |
464 | } | |
465 | ||
7d78cbef | 466 | data->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); |
c8ed99d4 CYT |
467 | if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) { |
468 | err = -EPROBE_DEFER; | |
469 | goto err_clk; | |
470 | } | |
7d78cbef HS |
471 | if (!IS_ERR(data->pclk)) { |
472 | err = clk_prepare_enable(data->pclk); | |
473 | if (err) { | |
474 | dev_err(&pdev->dev, "could not enable apb_pclk\n"); | |
c8ed99d4 | 475 | goto err_clk; |
7d78cbef | 476 | } |
e302cd93 EL |
477 | } |
478 | ||
7fe090bf | 479 | data->rst = devm_reset_control_get_optional(&pdev->dev, NULL); |
c8ed99d4 CYT |
480 | if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) { |
481 | err = -EPROBE_DEFER; | |
482 | goto err_pclk; | |
483 | } | |
7fe090bf CYT |
484 | if (!IS_ERR(data->rst)) |
485 | reset_control_deassert(data->rst); | |
486 | ||
7fb8c56c HK |
487 | data->dma.rx_param = data; |
488 | data->dma.tx_param = data; | |
489 | data->dma.fn = dw8250_dma_filter; | |
490 | ||
2655a2c7 AC |
491 | uart.port.iotype = UPIO_MEM; |
492 | uart.port.serial_in = dw8250_serial_in; | |
493 | uart.port.serial_out = dw8250_serial_out; | |
e302cd93 | 494 | uart.port.private_data = data; |
a7260c8c HK |
495 | |
496 | if (pdev->dev.of_node) { | |
d5f1af7e | 497 | err = dw8250_probe_of(&uart.port, data); |
a7260c8c | 498 | if (err) |
c8ed99d4 | 499 | goto err_reset; |
6a7320c4 | 500 | } else if (ACPI_HANDLE(&pdev->dev)) { |
fe958555 | 501 | err = dw8250_probe_acpi(&uart, data); |
6a7320c4 | 502 | if (err) |
c8ed99d4 | 503 | goto err_reset; |
a7260c8c | 504 | } else { |
c8ed99d4 CYT |
505 | err = -ENODEV; |
506 | goto err_reset; | |
7d4008eb JI |
507 | } |
508 | ||
2655a2c7 | 509 | data->line = serial8250_register_8250_port(&uart); |
c8ed99d4 CYT |
510 | if (data->line < 0) { |
511 | err = data->line; | |
512 | goto err_reset; | |
513 | } | |
7d4008eb JI |
514 | |
515 | platform_set_drvdata(pdev, data); | |
516 | ||
ffc3ae6d HK |
517 | pm_runtime_set_active(&pdev->dev); |
518 | pm_runtime_enable(&pdev->dev); | |
519 | ||
7d4008eb | 520 | return 0; |
c8ed99d4 CYT |
521 | |
522 | err_reset: | |
523 | if (!IS_ERR(data->rst)) | |
524 | reset_control_assert(data->rst); | |
525 | ||
526 | err_pclk: | |
527 | if (!IS_ERR(data->pclk)) | |
528 | clk_disable_unprepare(data->pclk); | |
529 | ||
530 | err_clk: | |
531 | if (!IS_ERR(data->clk)) | |
532 | clk_disable_unprepare(data->clk); | |
533 | ||
534 | return err; | |
7d4008eb JI |
535 | } |
536 | ||
ae8d8a14 | 537 | static int dw8250_remove(struct platform_device *pdev) |
7d4008eb JI |
538 | { |
539 | struct dw8250_data *data = platform_get_drvdata(pdev); | |
540 | ||
ffc3ae6d HK |
541 | pm_runtime_get_sync(&pdev->dev); |
542 | ||
7d4008eb JI |
543 | serial8250_unregister_port(data->line); |
544 | ||
7fe090bf CYT |
545 | if (!IS_ERR(data->rst)) |
546 | reset_control_assert(data->rst); | |
547 | ||
7d78cbef HS |
548 | if (!IS_ERR(data->pclk)) |
549 | clk_disable_unprepare(data->pclk); | |
550 | ||
e302cd93 EL |
551 | if (!IS_ERR(data->clk)) |
552 | clk_disable_unprepare(data->clk); | |
553 | ||
ffc3ae6d HK |
554 | pm_runtime_disable(&pdev->dev); |
555 | pm_runtime_put_noidle(&pdev->dev); | |
556 | ||
7d4008eb JI |
557 | return 0; |
558 | } | |
559 | ||
13b949f0 | 560 | #ifdef CONFIG_PM_SLEEP |
ffc3ae6d | 561 | static int dw8250_suspend(struct device *dev) |
b61c5ed5 | 562 | { |
ffc3ae6d | 563 | struct dw8250_data *data = dev_get_drvdata(dev); |
b61c5ed5 JH |
564 | |
565 | serial8250_suspend_port(data->line); | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
ffc3ae6d | 570 | static int dw8250_resume(struct device *dev) |
b61c5ed5 | 571 | { |
ffc3ae6d | 572 | struct dw8250_data *data = dev_get_drvdata(dev); |
b61c5ed5 JH |
573 | |
574 | serial8250_resume_port(data->line); | |
575 | ||
576 | return 0; | |
577 | } | |
13b949f0 | 578 | #endif /* CONFIG_PM_SLEEP */ |
b61c5ed5 | 579 | |
d39fe4e5 | 580 | #ifdef CONFIG_PM |
ffc3ae6d HK |
581 | static int dw8250_runtime_suspend(struct device *dev) |
582 | { | |
583 | struct dw8250_data *data = dev_get_drvdata(dev); | |
584 | ||
dbd2df85 EG |
585 | if (!IS_ERR(data->clk)) |
586 | clk_disable_unprepare(data->clk); | |
ffc3ae6d | 587 | |
7d78cbef HS |
588 | if (!IS_ERR(data->pclk)) |
589 | clk_disable_unprepare(data->pclk); | |
590 | ||
ffc3ae6d HK |
591 | return 0; |
592 | } | |
593 | ||
594 | static int dw8250_runtime_resume(struct device *dev) | |
595 | { | |
596 | struct dw8250_data *data = dev_get_drvdata(dev); | |
597 | ||
7d78cbef HS |
598 | if (!IS_ERR(data->pclk)) |
599 | clk_prepare_enable(data->pclk); | |
600 | ||
dbd2df85 EG |
601 | if (!IS_ERR(data->clk)) |
602 | clk_prepare_enable(data->clk); | |
ffc3ae6d HK |
603 | |
604 | return 0; | |
605 | } | |
606 | #endif | |
607 | ||
608 | static const struct dev_pm_ops dw8250_pm_ops = { | |
609 | SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) | |
610 | SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) | |
611 | }; | |
612 | ||
a7260c8c | 613 | static const struct of_device_id dw8250_of_match[] = { |
7d4008eb | 614 | { .compatible = "snps,dw-apb-uart" }, |
d5f1af7e | 615 | { .compatible = "cavium,octeon-3860-uart" }, |
7d4008eb JI |
616 | { /* Sentinel */ } |
617 | }; | |
a7260c8c | 618 | MODULE_DEVICE_TABLE(of, dw8250_of_match); |
7d4008eb | 619 | |
6a7320c4 | 620 | static const struct acpi_device_id dw8250_acpi_match[] = { |
aea02e87 HK |
621 | { "INT33C4", 0 }, |
622 | { "INT33C5", 0 }, | |
d24c195f MW |
623 | { "INT3434", 0 }, |
624 | { "INT3435", 0 }, | |
4e26b134 | 625 | { "80860F0A", 0 }, |
f174442e | 626 | { "8086228A", 0 }, |
5e1aeea5 | 627 | { "APMC0D08", 0}, |
5ef86b74 | 628 | { "AMD0020", 0 }, |
6a7320c4 HK |
629 | { }, |
630 | }; | |
631 | MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); | |
632 | ||
7d4008eb JI |
633 | static struct platform_driver dw8250_platform_driver = { |
634 | .driver = { | |
635 | .name = "dw-apb-uart", | |
ffc3ae6d | 636 | .pm = &dw8250_pm_ops, |
a7260c8c | 637 | .of_match_table = dw8250_of_match, |
6a7320c4 | 638 | .acpi_match_table = ACPI_PTR(dw8250_acpi_match), |
7d4008eb JI |
639 | }, |
640 | .probe = dw8250_probe, | |
2d47b716 | 641 | .remove = dw8250_remove, |
7d4008eb JI |
642 | }; |
643 | ||
c8381c15 | 644 | module_platform_driver(dw8250_platform_driver); |
7d4008eb JI |
645 | |
646 | MODULE_AUTHOR("Jamie Iles"); | |
647 | MODULE_LICENSE("GPL"); | |
648 | MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); | |
f3ac3fc2 | 649 | MODULE_ALIAS("platform:dw-apb-uart"); |