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d9eda9ba HK |
1 | /* |
2 | * 8250_mid.c - Driver for UART on Intel Penwell and various other Intel SOCs | |
3 | * | |
4 | * Copyright (C) 2015 Intel Corporation | |
5 | * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
dea5ac3a | 12 | #include <linux/bitops.h> |
d9eda9ba HK |
13 | #include <linux/module.h> |
14 | #include <linux/pci.h> | |
dea5ac3a | 15 | #include <linux/rational.h> |
d9eda9ba HK |
16 | |
17 | #include <linux/dma/hsu.h> | |
107e15fc | 18 | #include <linux/8250_pci.h> |
d9eda9ba HK |
19 | |
20 | #include "8250.h" | |
21 | ||
22 | #define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b | |
23 | #define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c | |
24 | #define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d | |
25 | #define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191 | |
6ede6dcd | 26 | #define PCI_DEVICE_ID_INTEL_DNV_UART 0x19d8 |
d9eda9ba HK |
27 | |
28 | /* Intel MID Specific registers */ | |
c42850f1 | 29 | #define INTEL_MID_UART_DNV_FISR 0x08 |
d9eda9ba HK |
30 | #define INTEL_MID_UART_PS 0x30 |
31 | #define INTEL_MID_UART_MUL 0x34 | |
32 | #define INTEL_MID_UART_DIV 0x38 | |
33 | ||
34 | struct mid8250; | |
35 | ||
36 | struct mid8250_board { | |
107e15fc | 37 | unsigned int flags; |
d9eda9ba HK |
38 | unsigned long freq; |
39 | unsigned int base_baud; | |
40 | int (*setup)(struct mid8250 *, struct uart_port *p); | |
6ede6dcd | 41 | void (*exit)(struct mid8250 *); |
d9eda9ba HK |
42 | }; |
43 | ||
44 | struct mid8250 { | |
45 | int line; | |
46 | int dma_index; | |
47 | struct pci_dev *dma_dev; | |
48 | struct uart_8250_dma dma; | |
49 | struct mid8250_board *board; | |
6ede6dcd | 50 | struct hsu_dma_chip dma_chip; |
d9eda9ba HK |
51 | }; |
52 | ||
53 | /*****************************************************************************/ | |
54 | ||
55 | static int pnw_setup(struct mid8250 *mid, struct uart_port *p) | |
56 | { | |
57 | struct pci_dev *pdev = to_pci_dev(p->dev); | |
58 | ||
59 | switch (pdev->device) { | |
60 | case PCI_DEVICE_ID_INTEL_PNW_UART1: | |
61 | mid->dma_index = 0; | |
62 | break; | |
63 | case PCI_DEVICE_ID_INTEL_PNW_UART2: | |
64 | mid->dma_index = 1; | |
65 | break; | |
66 | case PCI_DEVICE_ID_INTEL_PNW_UART3: | |
67 | mid->dma_index = 2; | |
68 | break; | |
69 | default: | |
70 | return -EINVAL; | |
71 | } | |
72 | ||
73 | mid->dma_dev = pci_get_slot(pdev->bus, | |
74 | PCI_DEVFN(PCI_SLOT(pdev->devfn), 3)); | |
75 | return 0; | |
76 | } | |
77 | ||
78 | static int tng_setup(struct mid8250 *mid, struct uart_port *p) | |
79 | { | |
80 | struct pci_dev *pdev = to_pci_dev(p->dev); | |
81 | int index = PCI_FUNC(pdev->devfn); | |
82 | ||
ceeafb8e AS |
83 | /* |
84 | * Device 0000:00:04.0 is not a real HSU port. It provides a global | |
85 | * register set for all HSU ports, although it has the same PCI ID. | |
86 | * Skip it here. | |
87 | */ | |
d9eda9ba HK |
88 | if (index-- == 0) |
89 | return -ENODEV; | |
90 | ||
91 | mid->dma_index = index; | |
92 | mid->dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0)); | |
93 | return 0; | |
94 | } | |
95 | ||
6ede6dcd HK |
96 | static int dnv_handle_irq(struct uart_port *p) |
97 | { | |
98 | struct mid8250 *mid = p->private_data; | |
692aa190 | 99 | struct uart_8250_port *up = up_to_u8250p(p); |
c42850f1 | 100 | unsigned int fisr = serial_port_in(p, INTEL_MID_UART_DNV_FISR); |
c6f82787 | 101 | u32 status; |
c42850f1 | 102 | int ret = IRQ_NONE; |
c6f82787 CKT |
103 | int err; |
104 | ||
105 | if (fisr & BIT(2)) { | |
106 | err = hsu_dma_get_status(&mid->dma_chip, 1, &status); | |
692aa190 CKT |
107 | if (err > 0) { |
108 | serial8250_rx_dma_flush(up); | |
c6f82787 | 109 | ret |= IRQ_HANDLED; |
692aa190 | 110 | } else if (err == 0) |
c6f82787 CKT |
111 | ret |= hsu_dma_do_irq(&mid->dma_chip, 1, status); |
112 | } | |
113 | if (fisr & BIT(1)) { | |
114 | err = hsu_dma_get_status(&mid->dma_chip, 0, &status); | |
115 | if (err > 0) | |
116 | ret |= IRQ_HANDLED; | |
117 | else if (err == 0) | |
118 | ret |= hsu_dma_do_irq(&mid->dma_chip, 0, status); | |
119 | } | |
c42850f1 AS |
120 | if (fisr & BIT(0)) |
121 | ret |= serial8250_handle_irq(p, serial_port_in(p, UART_IIR)); | |
122 | return ret; | |
6ede6dcd HK |
123 | } |
124 | ||
125 | #define DNV_DMA_CHAN_OFFSET 0x80 | |
126 | ||
127 | static int dnv_setup(struct mid8250 *mid, struct uart_port *p) | |
128 | { | |
129 | struct hsu_dma_chip *chip = &mid->dma_chip; | |
130 | struct pci_dev *pdev = to_pci_dev(p->dev); | |
107e15fc | 131 | unsigned int bar = FL_GET_BASE(mid->board->flags); |
6ede6dcd HK |
132 | int ret; |
133 | ||
134 | chip->dev = &pdev->dev; | |
135 | chip->irq = pdev->irq; | |
136 | chip->regs = p->membase; | |
107e15fc | 137 | chip->length = pci_resource_len(pdev, bar); |
6ede6dcd HK |
138 | chip->offset = DNV_DMA_CHAN_OFFSET; |
139 | ||
140 | /* Falling back to PIO mode if DMA probing fails */ | |
141 | ret = hsu_dma_probe(chip); | |
142 | if (ret) | |
143 | return 0; | |
144 | ||
145 | mid->dma_dev = pdev; | |
146 | ||
147 | p->handle_irq = dnv_handle_irq; | |
148 | return 0; | |
149 | } | |
150 | ||
151 | static void dnv_exit(struct mid8250 *mid) | |
152 | { | |
153 | if (!mid->dma_dev) | |
154 | return; | |
155 | hsu_dma_remove(&mid->dma_chip); | |
156 | } | |
157 | ||
d9eda9ba HK |
158 | /*****************************************************************************/ |
159 | ||
160 | static void mid8250_set_termios(struct uart_port *p, | |
161 | struct ktermios *termios, | |
162 | struct ktermios *old) | |
163 | { | |
164 | unsigned int baud = tty_termios_baud_rate(termios); | |
165 | struct mid8250 *mid = p->private_data; | |
166 | unsigned short ps = 16; | |
167 | unsigned long fuart = baud * ps; | |
168 | unsigned long w = BIT(24) - 1; | |
169 | unsigned long mul, div; | |
170 | ||
47b34d2e AS |
171 | /* Gracefully handle the B0 case: fall back to B9600 */ |
172 | fuart = fuart ? fuart : 9600 * 16; | |
173 | ||
d9eda9ba HK |
174 | if (mid->board->freq < fuart) { |
175 | /* Find prescaler value that satisfies Fuart < Fref */ | |
176 | if (mid->board->freq > baud) | |
177 | ps = mid->board->freq / baud; /* baud rate too high */ | |
178 | else | |
179 | ps = 1; /* PLL case */ | |
180 | fuart = baud * ps; | |
181 | } else { | |
182 | /* Get Fuart closer to Fref */ | |
183 | fuart *= rounddown_pow_of_two(mid->board->freq / fuart); | |
184 | } | |
185 | ||
186 | rational_best_approximation(fuart, mid->board->freq, w, w, &mul, &div); | |
187 | p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */ | |
188 | ||
189 | writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */ | |
190 | writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */ | |
191 | writel(div, p->membase + INTEL_MID_UART_DIV); | |
192 | ||
193 | serial8250_do_set_termios(p, termios, old); | |
194 | } | |
195 | ||
196 | static bool mid8250_dma_filter(struct dma_chan *chan, void *param) | |
197 | { | |
198 | struct hsu_dma_slave *s = param; | |
199 | ||
200 | if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id) | |
201 | return false; | |
202 | ||
203 | chan->private = s; | |
204 | return true; | |
205 | } | |
206 | ||
207 | static int mid8250_dma_setup(struct mid8250 *mid, struct uart_8250_port *port) | |
208 | { | |
209 | struct uart_8250_dma *dma = &mid->dma; | |
210 | struct device *dev = port->port.dev; | |
211 | struct hsu_dma_slave *rx_param; | |
212 | struct hsu_dma_slave *tx_param; | |
213 | ||
6ede6dcd HK |
214 | if (!mid->dma_dev) |
215 | return 0; | |
216 | ||
d9eda9ba HK |
217 | rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL); |
218 | if (!rx_param) | |
219 | return -ENOMEM; | |
220 | ||
221 | tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL); | |
222 | if (!tx_param) | |
223 | return -ENOMEM; | |
224 | ||
225 | rx_param->chan_id = mid->dma_index * 2 + 1; | |
226 | tx_param->chan_id = mid->dma_index * 2; | |
227 | ||
228 | dma->rxconf.src_maxburst = 64; | |
229 | dma->txconf.dst_maxburst = 64; | |
230 | ||
231 | rx_param->dma_dev = &mid->dma_dev->dev; | |
232 | tx_param->dma_dev = &mid->dma_dev->dev; | |
233 | ||
234 | dma->fn = mid8250_dma_filter; | |
235 | dma->rx_param = rx_param; | |
236 | dma->tx_param = tx_param; | |
237 | ||
238 | port->dma = dma; | |
239 | return 0; | |
240 | } | |
241 | ||
242 | static int mid8250_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
243 | { | |
244 | struct uart_8250_port uart; | |
245 | struct mid8250 *mid; | |
107e15fc | 246 | unsigned int bar; |
d9eda9ba HK |
247 | int ret; |
248 | ||
249 | ret = pcim_enable_device(pdev); | |
250 | if (ret) | |
251 | return ret; | |
252 | ||
253 | pci_set_master(pdev); | |
254 | ||
255 | mid = devm_kzalloc(&pdev->dev, sizeof(*mid), GFP_KERNEL); | |
256 | if (!mid) | |
257 | return -ENOMEM; | |
258 | ||
259 | mid->board = (struct mid8250_board *)id->driver_data; | |
107e15fc | 260 | bar = FL_GET_BASE(mid->board->flags); |
d9eda9ba HK |
261 | |
262 | memset(&uart, 0, sizeof(struct uart_8250_port)); | |
263 | ||
264 | uart.port.dev = &pdev->dev; | |
265 | uart.port.irq = pdev->irq; | |
266 | uart.port.private_data = mid; | |
267 | uart.port.type = PORT_16750; | |
268 | uart.port.iotype = UPIO_MEM; | |
269 | uart.port.uartclk = mid->board->base_baud * 16; | |
270 | uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE; | |
271 | uart.port.set_termios = mid8250_set_termios; | |
272 | ||
107e15fc AS |
273 | uart.port.mapbase = pci_resource_start(pdev, bar); |
274 | uart.port.membase = pcim_iomap(pdev, bar, 0); | |
d9eda9ba HK |
275 | if (!uart.port.membase) |
276 | return -ENOMEM; | |
277 | ||
278 | if (mid->board->setup) { | |
279 | ret = mid->board->setup(mid, &uart.port); | |
280 | if (ret) | |
281 | return ret; | |
282 | } | |
283 | ||
284 | ret = mid8250_dma_setup(mid, &uart); | |
285 | if (ret) | |
6ede6dcd | 286 | goto err; |
d9eda9ba HK |
287 | |
288 | ret = serial8250_register_8250_port(&uart); | |
289 | if (ret < 0) | |
6ede6dcd | 290 | goto err; |
d9eda9ba HK |
291 | |
292 | mid->line = ret; | |
293 | ||
294 | pci_set_drvdata(pdev, mid); | |
295 | return 0; | |
6ede6dcd HK |
296 | err: |
297 | if (mid->board->exit) | |
298 | mid->board->exit(mid); | |
299 | return ret; | |
d9eda9ba HK |
300 | } |
301 | ||
302 | static void mid8250_remove(struct pci_dev *pdev) | |
303 | { | |
304 | struct mid8250 *mid = pci_get_drvdata(pdev); | |
305 | ||
6ede6dcd HK |
306 | if (mid->board->exit) |
307 | mid->board->exit(mid); | |
308 | ||
d9eda9ba HK |
309 | serial8250_unregister_port(mid->line); |
310 | } | |
311 | ||
312 | static const struct mid8250_board pnw_board = { | |
107e15fc | 313 | .flags = FL_BASE0, |
d9eda9ba HK |
314 | .freq = 50000000, |
315 | .base_baud = 115200, | |
316 | .setup = pnw_setup, | |
317 | }; | |
318 | ||
319 | static const struct mid8250_board tng_board = { | |
107e15fc | 320 | .flags = FL_BASE0, |
d9eda9ba HK |
321 | .freq = 38400000, |
322 | .base_baud = 1843200, | |
323 | .setup = tng_setup, | |
324 | }; | |
325 | ||
6ede6dcd | 326 | static const struct mid8250_board dnv_board = { |
107e15fc | 327 | .flags = FL_BASE1, |
6ede6dcd HK |
328 | .freq = 133333333, |
329 | .base_baud = 115200, | |
330 | .setup = dnv_setup, | |
331 | .exit = dnv_exit, | |
332 | }; | |
333 | ||
d9eda9ba HK |
334 | #define MID_DEVICE(id, board) { PCI_VDEVICE(INTEL, id), (kernel_ulong_t)&board } |
335 | ||
336 | static const struct pci_device_id pci_ids[] = { | |
337 | MID_DEVICE(PCI_DEVICE_ID_INTEL_PNW_UART1, pnw_board), | |
338 | MID_DEVICE(PCI_DEVICE_ID_INTEL_PNW_UART2, pnw_board), | |
339 | MID_DEVICE(PCI_DEVICE_ID_INTEL_PNW_UART3, pnw_board), | |
340 | MID_DEVICE(PCI_DEVICE_ID_INTEL_TNG_UART, tng_board), | |
6ede6dcd | 341 | MID_DEVICE(PCI_DEVICE_ID_INTEL_DNV_UART, dnv_board), |
d9eda9ba HK |
342 | { }, |
343 | }; | |
344 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
345 | ||
346 | static struct pci_driver mid8250_pci_driver = { | |
347 | .name = "8250_mid", | |
348 | .id_table = pci_ids, | |
349 | .probe = mid8250_probe, | |
350 | .remove = mid8250_remove, | |
351 | }; | |
352 | ||
353 | module_pci_driver(mid8250_pci_driver); | |
354 | ||
355 | MODULE_AUTHOR("Intel Corporation"); | |
356 | MODULE_LICENSE("GPL v2"); | |
357 | MODULE_DESCRIPTION("Intel MID UART driver"); |