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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
61929cf0 SAS |
2 | /* |
3 | * 8250-core based driver for the OMAP internal UART | |
4 | * | |
5 | * based on omap-serial.c, Copyright (C) 2010 Texas Instruments. | |
6 | * | |
7 | * Copyright (C) 2014 Sebastian Andrzej Siewior | |
8 | * | |
9 | */ | |
10 | ||
596f63da DA |
11 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
12 | #define SUPPORT_SYSRQ | |
13 | #endif | |
14 | ||
7d470ebf | 15 | #include <linux/clk.h> |
61929cf0 SAS |
16 | #include <linux/device.h> |
17 | #include <linux/io.h> | |
18 | #include <linux/module.h> | |
19 | #include <linux/serial_8250.h> | |
61929cf0 | 20 | #include <linux/serial_reg.h> |
77285243 | 21 | #include <linux/tty_flip.h> |
61929cf0 SAS |
22 | #include <linux/platform_device.h> |
23 | #include <linux/slab.h> | |
24 | #include <linux/of.h> | |
4fcdff9b | 25 | #include <linux/of_device.h> |
61929cf0 SAS |
26 | #include <linux/of_gpio.h> |
27 | #include <linux/of_irq.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/console.h> | |
31 | #include <linux/pm_qos.h> | |
a3e362f1 | 32 | #include <linux/pm_wakeirq.h> |
31a17132 | 33 | #include <linux/dma-mapping.h> |
61929cf0 SAS |
34 | |
35 | #include "8250.h" | |
36 | ||
37 | #define DEFAULT_CLK_SPEED 48000000 | |
38 | ||
39 | #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0) | |
40 | #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1) | |
31a17132 | 41 | #define OMAP_DMA_TX_KICK (1 << 2) |
cdb929e4 SN |
42 | /* |
43 | * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015. | |
44 | * The same errata is applicable to AM335x and DRA7x processors too. | |
45 | */ | |
46 | #define UART_ERRATA_CLOCK_DISABLE (1 << 3) | |
61929cf0 SAS |
47 | |
48 | #define OMAP_UART_FCR_RX_TRIG 6 | |
49 | #define OMAP_UART_FCR_TX_TRIG 4 | |
50 | ||
51 | /* SCR register bitmasks */ | |
52 | #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) | |
53 | #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) | |
54 | #define OMAP_UART_SCR_TX_EMPTY (1 << 3) | |
55 | #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1) | |
56 | #define OMAP_UART_SCR_DMAMODE_1 (1 << 1) | |
57 | #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0) | |
58 | ||
59 | /* MVR register bitmasks */ | |
60 | #define OMAP_UART_MVR_SCHEME_SHIFT 30 | |
61 | #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 | |
62 | #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 | |
63 | #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f | |
64 | #define OMAP_UART_MVR_MAJ_MASK 0x700 | |
65 | #define OMAP_UART_MVR_MAJ_SHIFT 8 | |
66 | #define OMAP_UART_MVR_MIN_MASK 0x3f | |
67 | ||
cdb929e4 SN |
68 | /* SYSC register bitmasks */ |
69 | #define OMAP_UART_SYSC_SOFTRESET (1 << 1) | |
70 | ||
71 | /* SYSS register bitmasks */ | |
72 | #define OMAP_UART_SYSS_RESETDONE (1 << 0) | |
73 | ||
61929cf0 SAS |
74 | #define UART_TI752_TLR_TX 0 |
75 | #define UART_TI752_TLR_RX 4 | |
76 | ||
77 | #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2) | |
78 | #define TRIGGER_FCR_MASK(x) (x & 3) | |
79 | ||
80 | /* Enable XON/XOFF flow control on output */ | |
81 | #define OMAP_UART_SW_TX 0x08 | |
82 | /* Enable XON/XOFF flow control on input */ | |
83 | #define OMAP_UART_SW_RX 0x02 | |
84 | ||
85 | #define OMAP_UART_WER_MOD_WKUP 0x7f | |
86 | #define OMAP_UART_TX_WAKEUP_EN (1 << 7) | |
87 | ||
88 | #define TX_TRIGGER 1 | |
89 | #define RX_TRIGGER 48 | |
90 | ||
91 | #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4) | |
92 | #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0) | |
93 | ||
94 | #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) | |
95 | ||
96 | #define OMAP_UART_REV_46 0x0406 | |
97 | #define OMAP_UART_REV_52 0x0502 | |
98 | #define OMAP_UART_REV_63 0x0603 | |
99 | ||
100 | struct omap8250_priv { | |
101 | int line; | |
102 | u8 habit; | |
103 | u8 mdr1; | |
104 | u8 efr; | |
105 | u8 scr; | |
106 | u8 wer; | |
107 | u8 xon; | |
108 | u8 xoff; | |
0a0661dd | 109 | u8 delayed_restore; |
61929cf0 SAS |
110 | u16 quot; |
111 | ||
112 | bool is_suspending; | |
113 | int wakeirq; | |
114 | int wakeups_enabled; | |
115 | u32 latency; | |
116 | u32 calc_latency; | |
117 | struct pm_qos_request pm_qos_request; | |
118 | struct work_struct qos_work; | |
119 | struct uart_8250_dma omap8250_dma; | |
eda0cd35 | 120 | spinlock_t rx_dma_lock; |
830acf9e | 121 | bool rx_dma_broken; |
08fb00c6 | 122 | bool throttled; |
61929cf0 SAS |
123 | }; |
124 | ||
33d9b8b2 PH |
125 | #ifdef CONFIG_SERIAL_8250_DMA |
126 | static void omap_8250_rx_dma_flush(struct uart_8250_port *p); | |
127 | #else | |
128 | static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { } | |
129 | #endif | |
130 | ||
61929cf0 SAS |
131 | static u32 uart_read(struct uart_8250_port *up, u32 reg) |
132 | { | |
133 | return readl(up->port.membase + (reg << up->port.regshift)); | |
134 | } | |
135 | ||
4bf4ea9d PH |
136 | static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl) |
137 | { | |
138 | struct uart_8250_port *up = up_to_u8250p(port); | |
139 | struct omap8250_priv *priv = up->port.private_data; | |
140 | u8 lcr; | |
141 | ||
142 | serial8250_do_set_mctrl(port, mctrl); | |
143 | ||
fc64f7ab | 144 | if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) { |
4a96895f YY |
145 | /* |
146 | * Turn off autoRTS if RTS is lowered and restore autoRTS | |
147 | * setting if RTS is raised | |
148 | */ | |
149 | lcr = serial_in(up, UART_LCR); | |
150 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
151 | if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) | |
152 | priv->efr |= UART_EFR_RTS; | |
153 | else | |
154 | priv->efr &= ~UART_EFR_RTS; | |
155 | serial_out(up, UART_EFR, priv->efr); | |
156 | serial_out(up, UART_LCR, lcr); | |
157 | } | |
4bf4ea9d PH |
158 | } |
159 | ||
61929cf0 SAS |
160 | /* |
161 | * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) | |
162 | * The access to uart register after MDR1 Access | |
163 | * causes UART to corrupt data. | |
164 | * | |
165 | * Need a delay = | |
166 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) | |
167 | * give 10 times as much | |
168 | */ | |
169 | static void omap_8250_mdr1_errataset(struct uart_8250_port *up, | |
170 | struct omap8250_priv *priv) | |
171 | { | |
172 | u8 timeout = 255; | |
61929cf0 SAS |
173 | |
174 | serial_out(up, UART_OMAP_MDR1, priv->mdr1); | |
175 | udelay(2); | |
176 | serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | | |
177 | UART_FCR_CLEAR_RCVR); | |
178 | /* | |
179 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and | |
180 | * TX_FIFO_E bit is 1. | |
181 | */ | |
182 | while (UART_LSR_THRE != (serial_in(up, UART_LSR) & | |
183 | (UART_LSR_THRE | UART_LSR_DR))) { | |
184 | timeout--; | |
185 | if (!timeout) { | |
186 | /* Should *never* happen. we warn and carry on */ | |
187 | dev_crit(up->port.dev, "Errata i202: timedout %x\n", | |
188 | serial_in(up, UART_LSR)); | |
189 | break; | |
190 | } | |
191 | udelay(1); | |
192 | } | |
193 | } | |
194 | ||
195 | static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud, | |
196 | struct omap8250_priv *priv) | |
197 | { | |
198 | unsigned int uartclk = port->uartclk; | |
199 | unsigned int div_13, div_16; | |
200 | unsigned int abs_d13, abs_d16; | |
201 | ||
202 | /* | |
203 | * Old custom speed handling. | |
204 | */ | |
205 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) { | |
6263368c | 206 | priv->quot = port->custom_divisor & UART_DIV_MAX; |
61929cf0 SAS |
207 | /* |
208 | * I assume that nobody is using this. But hey, if somebody | |
209 | * would like to specify the divisor _and_ the mode then the | |
210 | * driver is ready and waiting for it. | |
211 | */ | |
212 | if (port->custom_divisor & (1 << 16)) | |
213 | priv->mdr1 = UART_OMAP_MDR1_13X_MODE; | |
214 | else | |
215 | priv->mdr1 = UART_OMAP_MDR1_16X_MODE; | |
216 | return; | |
217 | } | |
218 | div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud); | |
219 | div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud); | |
220 | ||
221 | if (!div_13) | |
222 | div_13 = 1; | |
223 | if (!div_16) | |
224 | div_16 = 1; | |
225 | ||
226 | abs_d13 = abs(baud - uartclk / 13 / div_13); | |
227 | abs_d16 = abs(baud - uartclk / 16 / div_16); | |
228 | ||
229 | if (abs_d13 >= abs_d16) { | |
230 | priv->mdr1 = UART_OMAP_MDR1_16X_MODE; | |
231 | priv->quot = div_16; | |
232 | } else { | |
233 | priv->mdr1 = UART_OMAP_MDR1_13X_MODE; | |
234 | priv->quot = div_13; | |
235 | } | |
236 | } | |
237 | ||
238 | static void omap8250_update_scr(struct uart_8250_port *up, | |
239 | struct omap8250_priv *priv) | |
240 | { | |
241 | u8 old_scr; | |
242 | ||
243 | old_scr = serial_in(up, UART_OMAP_SCR); | |
244 | if (old_scr == priv->scr) | |
245 | return; | |
246 | ||
247 | /* | |
248 | * The manual recommends not to enable the DMA mode selector in the SCR | |
249 | * (instead of the FCR) register _and_ selecting the DMA mode as one | |
250 | * register write because this may lead to malfunction. | |
251 | */ | |
252 | if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK) | |
253 | serial_out(up, UART_OMAP_SCR, | |
254 | priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK); | |
255 | serial_out(up, UART_OMAP_SCR, priv->scr); | |
256 | } | |
257 | ||
6f03541f SN |
258 | static void omap8250_update_mdr1(struct uart_8250_port *up, |
259 | struct omap8250_priv *priv) | |
260 | { | |
261 | if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS) | |
262 | omap_8250_mdr1_errataset(up, priv); | |
263 | else | |
264 | serial_out(up, UART_OMAP_MDR1, priv->mdr1); | |
265 | } | |
266 | ||
61929cf0 SAS |
267 | static void omap8250_restore_regs(struct uart_8250_port *up) |
268 | { | |
269 | struct omap8250_priv *priv = up->port.private_data; | |
0a0661dd SAS |
270 | struct uart_8250_dma *dma = up->dma; |
271 | ||
272 | if (dma && dma->tx_running) { | |
273 | /* | |
274 | * TCSANOW requests the change to occur immediately however if | |
275 | * we have a TX-DMA operation in progress then it has been | |
276 | * observed that it might stall and never complete. Therefore we | |
277 | * delay DMA completes to prevent this hang from happen. | |
278 | */ | |
279 | priv->delayed_restore = 1; | |
280 | return; | |
281 | } | |
61929cf0 SAS |
282 | |
283 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
284 | serial_out(up, UART_EFR, UART_EFR_ECB); | |
285 | ||
286 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
36fd95b1 | 287 | serial8250_out_MCR(up, UART_MCR_TCRTLR); |
61929cf0 SAS |
288 | serial_out(up, UART_FCR, up->fcr); |
289 | ||
290 | omap8250_update_scr(up, priv); | |
291 | ||
292 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
293 | ||
294 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) | | |
295 | OMAP_UART_TCR_HALT(52)); | |
296 | serial_out(up, UART_TI752_TLR, | |
297 | TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX | | |
298 | TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX); | |
299 | ||
300 | serial_out(up, UART_LCR, 0); | |
301 | ||
302 | /* drop TCR + TLR access, we setup XON/XOFF later */ | |
36fd95b1 | 303 | serial8250_out_MCR(up, up->mcr); |
61929cf0 SAS |
304 | serial_out(up, UART_IER, up->ier); |
305 | ||
306 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
307 | serial_dl_write(up, priv->quot); | |
308 | ||
9719acce | 309 | serial_out(up, UART_EFR, priv->efr); |
61929cf0 SAS |
310 | |
311 | /* Configure flow control */ | |
312 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
313 | serial_out(up, UART_XON1, priv->xon); | |
314 | serial_out(up, UART_XOFF1, priv->xoff); | |
315 | ||
316 | serial_out(up, UART_LCR, up->lcr); | |
6f03541f SN |
317 | |
318 | omap8250_update_mdr1(up, priv); | |
319 | ||
61929cf0 SAS |
320 | up->port.ops->set_mctrl(&up->port, up->port.mctrl); |
321 | } | |
322 | ||
323 | /* | |
324 | * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have | |
325 | * some differences in how we want to handle flow control. | |
326 | */ | |
327 | static void omap_8250_set_termios(struct uart_port *port, | |
328 | struct ktermios *termios, | |
329 | struct ktermios *old) | |
330 | { | |
013e3586 | 331 | struct uart_8250_port *up = up_to_u8250p(port); |
61929cf0 SAS |
332 | struct omap8250_priv *priv = up->port.private_data; |
333 | unsigned char cval = 0; | |
334 | unsigned int baud; | |
335 | ||
336 | switch (termios->c_cflag & CSIZE) { | |
337 | case CS5: | |
338 | cval = UART_LCR_WLEN5; | |
339 | break; | |
340 | case CS6: | |
341 | cval = UART_LCR_WLEN6; | |
342 | break; | |
343 | case CS7: | |
344 | cval = UART_LCR_WLEN7; | |
345 | break; | |
346 | default: | |
347 | case CS8: | |
348 | cval = UART_LCR_WLEN8; | |
349 | break; | |
350 | } | |
351 | ||
352 | if (termios->c_cflag & CSTOPB) | |
353 | cval |= UART_LCR_STOP; | |
354 | if (termios->c_cflag & PARENB) | |
355 | cval |= UART_LCR_PARITY; | |
356 | if (!(termios->c_cflag & PARODD)) | |
357 | cval |= UART_LCR_EPAR; | |
358 | if (termios->c_cflag & CMSPAR) | |
359 | cval |= UART_LCR_SPAR; | |
360 | ||
361 | /* | |
362 | * Ask the core to calculate the divisor for us. | |
363 | */ | |
364 | baud = uart_get_baud_rate(port, termios, old, | |
6263368c | 365 | port->uartclk / 16 / UART_DIV_MAX, |
61929cf0 SAS |
366 | port->uartclk / 13); |
367 | omap_8250_get_divisor(port, baud, priv); | |
368 | ||
369 | /* | |
370 | * Ok, we're now changing the port state. Do it with | |
371 | * interrupts disabled. | |
372 | */ | |
373 | pm_runtime_get_sync(port->dev); | |
374 | spin_lock_irq(&port->lock); | |
375 | ||
376 | /* | |
377 | * Update the per-port timeout. | |
378 | */ | |
379 | uart_update_timeout(port, termios->c_cflag, baud); | |
380 | ||
381 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
382 | if (termios->c_iflag & INPCK) | |
383 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
384 | if (termios->c_iflag & (IGNBRK | PARMRK)) | |
385 | up->port.read_status_mask |= UART_LSR_BI; | |
386 | ||
387 | /* | |
388 | * Characters to ignore | |
389 | */ | |
390 | up->port.ignore_status_mask = 0; | |
391 | if (termios->c_iflag & IGNPAR) | |
392 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
393 | if (termios->c_iflag & IGNBRK) { | |
394 | up->port.ignore_status_mask |= UART_LSR_BI; | |
395 | /* | |
396 | * If we're ignoring parity and break indicators, | |
397 | * ignore overruns too (for real raw support). | |
398 | */ | |
399 | if (termios->c_iflag & IGNPAR) | |
400 | up->port.ignore_status_mask |= UART_LSR_OE; | |
401 | } | |
402 | ||
403 | /* | |
404 | * ignore all characters if CREAD is not set | |
405 | */ | |
406 | if ((termios->c_cflag & CREAD) == 0) | |
407 | up->port.ignore_status_mask |= UART_LSR_DR; | |
408 | ||
409 | /* | |
410 | * Modem status interrupts | |
411 | */ | |
412 | up->ier &= ~UART_IER_MSI; | |
413 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
414 | up->ier |= UART_IER_MSI; | |
415 | ||
416 | up->lcr = cval; | |
417 | /* Up to here it was mostly serial8250_do_set_termios() */ | |
418 | ||
419 | /* | |
93ad8673 | 420 | * We enable TRIG_GRANU for RX and TX and additionally we set |
61929cf0 SAS |
421 | * SCR_TX_EMPTY bit. The result is the following: |
422 | * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt. | |
423 | * - less than RX_TRIGGER number of bytes will also cause an interrupt | |
424 | * once the UART decides that there no new bytes arriving. | |
425 | * - Once THRE is enabled, the interrupt will be fired once the FIFO is | |
426 | * empty - the trigger level is ignored here. | |
427 | * | |
428 | * Once DMA is enabled: | |
429 | * - UART will assert the TX DMA line once there is room for TX_TRIGGER | |
430 | * bytes in the TX FIFO. On each assert the DMA engine will move | |
431 | * TX_TRIGGER bytes into the FIFO. | |
432 | * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in | |
433 | * the FIFO and move RX_TRIGGER bytes. | |
434 | * This is because threshold and trigger values are the same. | |
435 | */ | |
436 | up->fcr = UART_FCR_ENABLE_FIFO; | |
437 | up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG; | |
438 | up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG; | |
439 | ||
440 | priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY | | |
441 | OMAP_UART_SCR_TX_TRIG_GRANU1_MASK; | |
442 | ||
0a0661dd SAS |
443 | if (up->dma) |
444 | priv->scr |= OMAP_UART_SCR_DMAMODE_1 | | |
445 | OMAP_UART_SCR_DMAMODE_CTL; | |
446 | ||
61929cf0 SAS |
447 | priv->xon = termios->c_cc[VSTART]; |
448 | priv->xoff = termios->c_cc[VSTOP]; | |
449 | ||
450 | priv->efr = 0; | |
391f93f2 PH |
451 | up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); |
452 | ||
4a96895f | 453 | if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW && |
fc64f7ab AF |
454 | !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) && |
455 | !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) { | |
9719acce | 456 | /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ |
391f93f2 | 457 | up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; |
9719acce | 458 | priv->efr |= UART_EFR_CTS; |
61929cf0 SAS |
459 | } else if (up->port.flags & UPF_SOFT_FLOW) { |
460 | /* | |
5bac4b3d PH |
461 | * OMAP rx s/w flow control is borked; the transmitter remains |
462 | * stuck off even if rx flow control is subsequently disabled | |
61929cf0 | 463 | */ |
61929cf0 SAS |
464 | |
465 | /* | |
466 | * IXOFF Flag: | |
467 | * Enable XON/XOFF flow control on output. | |
468 | * Transmit XON1, XOFF1 | |
469 | */ | |
391f93f2 PH |
470 | if (termios->c_iflag & IXOFF) { |
471 | up->port.status |= UPSTAT_AUTOXOFF; | |
61929cf0 | 472 | priv->efr |= OMAP_UART_SW_TX; |
391f93f2 | 473 | } |
61929cf0 SAS |
474 | } |
475 | omap8250_restore_regs(up); | |
476 | ||
477 | spin_unlock_irq(&up->port.lock); | |
478 | pm_runtime_mark_last_busy(port->dev); | |
479 | pm_runtime_put_autosuspend(port->dev); | |
480 | ||
481 | /* calculate wakeup latency constraint */ | |
482 | priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud; | |
483 | priv->latency = priv->calc_latency; | |
484 | ||
485 | schedule_work(&priv->qos_work); | |
486 | ||
487 | /* Don't rewrite B0 */ | |
488 | if (tty_termios_baud_rate(termios)) | |
489 | tty_termios_encode_baud_rate(termios, baud, baud); | |
490 | } | |
491 | ||
492 | /* same as 8250 except that we may have extra flow bits set in EFR */ | |
493 | static void omap_8250_pm(struct uart_port *port, unsigned int state, | |
494 | unsigned int oldstate) | |
495 | { | |
3e29af27 PH |
496 | struct uart_8250_port *up = up_to_u8250p(port); |
497 | u8 efr; | |
61929cf0 SAS |
498 | |
499 | pm_runtime_get_sync(port->dev); | |
500 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
3e29af27 PH |
501 | efr = serial_in(up, UART_EFR); |
502 | serial_out(up, UART_EFR, efr | UART_EFR_ECB); | |
61929cf0 SAS |
503 | serial_out(up, UART_LCR, 0); |
504 | ||
505 | serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); | |
506 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
3e29af27 | 507 | serial_out(up, UART_EFR, efr); |
61929cf0 SAS |
508 | serial_out(up, UART_LCR, 0); |
509 | ||
510 | pm_runtime_mark_last_busy(port->dev); | |
511 | pm_runtime_put_autosuspend(port->dev); | |
512 | } | |
513 | ||
514 | static void omap_serial_fill_features_erratas(struct uart_8250_port *up, | |
515 | struct omap8250_priv *priv) | |
516 | { | |
517 | u32 mvr, scheme; | |
518 | u16 revision, major, minor; | |
519 | ||
520 | mvr = uart_read(up, UART_OMAP_MVER); | |
521 | ||
522 | /* Check revision register scheme */ | |
523 | scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; | |
524 | ||
525 | switch (scheme) { | |
526 | case 0: /* Legacy Scheme: OMAP2/3 */ | |
527 | /* MINOR_REV[0:4], MAJOR_REV[4:7] */ | |
528 | major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> | |
529 | OMAP_UART_LEGACY_MVR_MAJ_SHIFT; | |
530 | minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); | |
531 | break; | |
532 | case 1: | |
533 | /* New Scheme: OMAP4+ */ | |
534 | /* MINOR_REV[0:5], MAJOR_REV[8:10] */ | |
535 | major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> | |
536 | OMAP_UART_MVR_MAJ_SHIFT; | |
537 | minor = (mvr & OMAP_UART_MVR_MIN_MASK); | |
538 | break; | |
539 | default: | |
540 | dev_warn(up->port.dev, | |
541 | "Unknown revision, defaulting to highest\n"); | |
542 | /* highest possible revision */ | |
543 | major = 0xff; | |
544 | minor = 0xff; | |
545 | } | |
546 | /* normalize revision for the driver */ | |
547 | revision = UART_BUILD_REVISION(major, minor); | |
548 | ||
549 | switch (revision) { | |
550 | case OMAP_UART_REV_46: | |
4fcdff9b | 551 | priv->habit |= UART_ERRATA_i202_MDR1_ACCESS; |
61929cf0 SAS |
552 | break; |
553 | case OMAP_UART_REV_52: | |
4fcdff9b | 554 | priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | |
61929cf0 SAS |
555 | OMAP_UART_WER_HAS_TX_WAKEUP; |
556 | break; | |
557 | case OMAP_UART_REV_63: | |
4fcdff9b | 558 | priv->habit |= UART_ERRATA_i202_MDR1_ACCESS | |
61929cf0 SAS |
559 | OMAP_UART_WER_HAS_TX_WAKEUP; |
560 | break; | |
561 | default: | |
562 | break; | |
563 | } | |
564 | } | |
565 | ||
566 | static void omap8250_uart_qos_work(struct work_struct *work) | |
567 | { | |
568 | struct omap8250_priv *priv; | |
569 | ||
570 | priv = container_of(work, struct omap8250_priv, qos_work); | |
571 | pm_qos_update_request(&priv->pm_qos_request, priv->latency); | |
572 | } | |
573 | ||
9e91597f SAS |
574 | #ifdef CONFIG_SERIAL_8250_DMA |
575 | static int omap_8250_dma_handle_irq(struct uart_port *port); | |
576 | #endif | |
577 | ||
578 | static irqreturn_t omap8250_irq(int irq, void *dev_id) | |
579 | { | |
580 | struct uart_port *port = dev_id; | |
581 | struct uart_8250_port *up = up_to_u8250p(port); | |
582 | unsigned int iir; | |
583 | int ret; | |
584 | ||
585 | #ifdef CONFIG_SERIAL_8250_DMA | |
586 | if (up->dma) { | |
587 | ret = omap_8250_dma_handle_irq(port); | |
588 | return IRQ_RETVAL(ret); | |
589 | } | |
590 | #endif | |
591 | ||
592 | serial8250_rpm_get(up); | |
593 | iir = serial_port_in(port, UART_IIR); | |
594 | ret = serial8250_handle_irq(port, iir); | |
595 | serial8250_rpm_put(up); | |
596 | ||
597 | return IRQ_RETVAL(ret); | |
598 | } | |
599 | ||
61929cf0 SAS |
600 | static int omap_8250_startup(struct uart_port *port) |
601 | { | |
9e91597f | 602 | struct uart_8250_port *up = up_to_u8250p(port); |
61929cf0 | 603 | struct omap8250_priv *priv = port->private_data; |
61929cf0 SAS |
604 | int ret; |
605 | ||
606 | if (priv->wakeirq) { | |
a3e362f1 | 607 | ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq); |
61929cf0 SAS |
608 | if (ret) |
609 | return ret; | |
61929cf0 SAS |
610 | } |
611 | ||
612 | pm_runtime_get_sync(port->dev); | |
613 | ||
9e91597f SAS |
614 | up->mcr = 0; |
615 | serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
616 | ||
617 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
618 | ||
619 | up->lsr_saved_flags = 0; | |
620 | up->msr_saved_flags = 0; | |
621 | ||
84b40e3b V |
622 | /* Disable DMA for console UART */ |
623 | if (uart_console(port)) | |
624 | up->dma = NULL; | |
625 | ||
9e91597f SAS |
626 | if (up->dma) { |
627 | ret = serial8250_request_dma(up); | |
628 | if (ret) { | |
629 | dev_warn_ratelimited(port->dev, | |
630 | "failed to request DMA\n"); | |
631 | up->dma = NULL; | |
632 | } | |
633 | } | |
634 | ||
635 | ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED, | |
636 | dev_name(port->dev), port); | |
637 | if (ret < 0) | |
61929cf0 SAS |
638 | goto err; |
639 | ||
9e91597f SAS |
640 | up->ier = UART_IER_RLSI | UART_IER_RDI; |
641 | serial_out(up, UART_IER, up->ier); | |
642 | ||
71504e51 | 643 | #ifdef CONFIG_PM |
61929cf0 SAS |
644 | up->capabilities |= UART_CAP_RPM; |
645 | #endif | |
646 | ||
647 | /* Enable module level wake up */ | |
648 | priv->wer = OMAP_UART_WER_MOD_WKUP; | |
649 | if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP) | |
650 | priv->wer |= OMAP_UART_TX_WAKEUP_EN; | |
651 | serial_out(up, UART_OMAP_WER, priv->wer); | |
652 | ||
0a0661dd | 653 | if (up->dma) |
33d9b8b2 | 654 | up->dma->rx_dma(up); |
0a0661dd | 655 | |
61929cf0 SAS |
656 | pm_runtime_mark_last_busy(port->dev); |
657 | pm_runtime_put_autosuspend(port->dev); | |
658 | return 0; | |
659 | err: | |
660 | pm_runtime_mark_last_busy(port->dev); | |
661 | pm_runtime_put_autosuspend(port->dev); | |
a3e362f1 | 662 | dev_pm_clear_wake_irq(port->dev); |
61929cf0 SAS |
663 | return ret; |
664 | } | |
665 | ||
666 | static void omap_8250_shutdown(struct uart_port *port) | |
667 | { | |
9e91597f | 668 | struct uart_8250_port *up = up_to_u8250p(port); |
61929cf0 SAS |
669 | struct omap8250_priv *priv = port->private_data; |
670 | ||
671 | flush_work(&priv->qos_work); | |
0a0661dd | 672 | if (up->dma) |
33d9b8b2 | 673 | omap_8250_rx_dma_flush(up); |
61929cf0 SAS |
674 | |
675 | pm_runtime_get_sync(port->dev); | |
676 | ||
677 | serial_out(up, UART_OMAP_WER, 0); | |
9e91597f SAS |
678 | |
679 | up->ier = 0; | |
680 | serial_out(up, UART_IER, 0); | |
681 | ||
682 | if (up->dma) | |
683 | serial8250_release_dma(up); | |
684 | ||
685 | /* | |
686 | * Disable break condition and FIFOs | |
687 | */ | |
688 | if (up->lcr & UART_LCR_SBC) | |
689 | serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC); | |
690 | serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
61929cf0 SAS |
691 | |
692 | pm_runtime_mark_last_busy(port->dev); | |
693 | pm_runtime_put_autosuspend(port->dev); | |
9e91597f | 694 | free_irq(port->irq, port); |
a3e362f1 | 695 | dev_pm_clear_wake_irq(port->dev); |
61929cf0 SAS |
696 | } |
697 | ||
698 | static void omap_8250_throttle(struct uart_port *port) | |
699 | { | |
08fb00c6 | 700 | struct omap8250_priv *priv = port->private_data; |
013e3586 | 701 | struct uart_8250_port *up = up_to_u8250p(port); |
61929cf0 | 702 | unsigned long flags; |
61929cf0 SAS |
703 | |
704 | pm_runtime_get_sync(port->dev); | |
705 | ||
706 | spin_lock_irqsave(&port->lock, flags); | |
707 | up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); | |
708 | serial_out(up, UART_IER, up->ier); | |
08fb00c6 | 709 | priv->throttled = true; |
61929cf0 SAS |
710 | spin_unlock_irqrestore(&port->lock, flags); |
711 | ||
712 | pm_runtime_mark_last_busy(port->dev); | |
713 | pm_runtime_put_autosuspend(port->dev); | |
714 | } | |
715 | ||
344cee24 MK |
716 | static int omap_8250_rs485_config(struct uart_port *port, |
717 | struct serial_rs485 *rs485) | |
718 | { | |
719 | struct uart_8250_port *up = up_to_u8250p(port); | |
720 | ||
721 | /* Clamp the delays to [0, 100ms] */ | |
722 | rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U); | |
723 | rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U); | |
724 | ||
725 | port->rs485 = *rs485; | |
726 | ||
727 | /* | |
728 | * Both serial8250_em485_init and serial8250_em485_destroy | |
729 | * are idempotent | |
730 | */ | |
731 | if (rs485->flags & SER_RS485_ENABLED) { | |
732 | int ret = serial8250_em485_init(up); | |
733 | ||
734 | if (ret) { | |
735 | rs485->flags &= ~SER_RS485_ENABLED; | |
736 | port->rs485.flags &= ~SER_RS485_ENABLED; | |
737 | } | |
738 | return ret; | |
739 | } | |
740 | ||
741 | serial8250_em485_destroy(up); | |
742 | ||
743 | return 0; | |
744 | } | |
745 | ||
61929cf0 SAS |
746 | static void omap_8250_unthrottle(struct uart_port *port) |
747 | { | |
08fb00c6 | 748 | struct omap8250_priv *priv = port->private_data; |
013e3586 | 749 | struct uart_8250_port *up = up_to_u8250p(port); |
61929cf0 | 750 | unsigned long flags; |
61929cf0 SAS |
751 | |
752 | pm_runtime_get_sync(port->dev); | |
753 | ||
754 | spin_lock_irqsave(&port->lock, flags); | |
08fb00c6 V |
755 | priv->throttled = false; |
756 | if (up->dma) | |
757 | up->dma->rx_dma(up); | |
61929cf0 SAS |
758 | up->ier |= UART_IER_RLSI | UART_IER_RDI; |
759 | serial_out(up, UART_IER, up->ier); | |
760 | spin_unlock_irqrestore(&port->lock, flags); | |
761 | ||
762 | pm_runtime_mark_last_busy(port->dev); | |
763 | pm_runtime_put_autosuspend(port->dev); | |
764 | } | |
765 | ||
31a17132 | 766 | #ifdef CONFIG_SERIAL_8250_DMA |
33d9b8b2 | 767 | static int omap_8250_rx_dma(struct uart_8250_port *p); |
0e31c8d1 | 768 | |
b74fdd23 | 769 | static void __dma_rx_do_complete(struct uart_8250_port *p) |
0e31c8d1 | 770 | { |
eda0cd35 | 771 | struct omap8250_priv *priv = p->port.private_data; |
0e31c8d1 SAS |
772 | struct uart_8250_dma *dma = p->dma; |
773 | struct tty_port *tty_port = &p->port.state->port; | |
774 | struct dma_tx_state state; | |
775 | int count; | |
eda0cd35 | 776 | unsigned long flags; |
658e2ebc | 777 | int ret; |
0e31c8d1 | 778 | |
eda0cd35 JO |
779 | spin_lock_irqsave(&priv->rx_dma_lock, flags); |
780 | ||
781 | if (!dma->rx_running) | |
782 | goto unlock; | |
783 | ||
0e31c8d1 SAS |
784 | dma->rx_running = 0; |
785 | dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); | |
0e31c8d1 SAS |
786 | |
787 | count = dma->rx_size - state.residue; | |
066b0129 VR |
788 | if (count < dma->rx_size) |
789 | dmaengine_terminate_async(dma->rxchan); | |
790 | if (!count) | |
791 | goto unlock; | |
658e2ebc SAS |
792 | ret = tty_insert_flip_string(tty_port, dma->rx_buf, count); |
793 | ||
794 | p->port.icount.rx += ret; | |
795 | p->port.icount.buf_overrun += count - ret; | |
eda0cd35 JO |
796 | unlock: |
797 | spin_unlock_irqrestore(&priv->rx_dma_lock, flags); | |
798 | ||
0e31c8d1 SAS |
799 | tty_flip_buffer_push(tty_port); |
800 | } | |
801 | ||
802 | static void __dma_rx_complete(void *param) | |
803 | { | |
a1bfb6eb | 804 | struct uart_8250_port *p = param; |
08fb00c6 | 805 | struct omap8250_priv *priv = p->port.private_data; |
a1bfb6eb V |
806 | struct uart_8250_dma *dma = p->dma; |
807 | struct dma_tx_state state; | |
808 | unsigned long flags; | |
809 | ||
810 | spin_lock_irqsave(&p->port.lock, flags); | |
811 | ||
812 | /* | |
813 | * If the tx status is not DMA_COMPLETE, then this is a delayed | |
814 | * completion callback. A previous RX timeout flush would have | |
815 | * already pushed the data, so exit. | |
816 | */ | |
817 | if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != | |
818 | DMA_COMPLETE) { | |
819 | spin_unlock_irqrestore(&p->port.lock, flags); | |
820 | return; | |
821 | } | |
822 | __dma_rx_do_complete(p); | |
08fb00c6 V |
823 | if (!priv->throttled) |
824 | omap_8250_rx_dma(p); | |
a1bfb6eb V |
825 | |
826 | spin_unlock_irqrestore(&p->port.lock, flags); | |
0e31c8d1 SAS |
827 | } |
828 | ||
eda0cd35 JO |
829 | static void omap_8250_rx_dma_flush(struct uart_8250_port *p) |
830 | { | |
831 | struct omap8250_priv *priv = p->port.private_data; | |
832 | struct uart_8250_dma *dma = p->dma; | |
75f54acc | 833 | struct dma_tx_state state; |
eda0cd35 | 834 | unsigned long flags; |
830acf9e | 835 | int ret; |
eda0cd35 JO |
836 | |
837 | spin_lock_irqsave(&priv->rx_dma_lock, flags); | |
838 | ||
839 | if (!dma->rx_running) { | |
840 | spin_unlock_irqrestore(&priv->rx_dma_lock, flags); | |
841 | return; | |
842 | } | |
843 | ||
75f54acc V |
844 | ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); |
845 | if (ret == DMA_IN_PROGRESS) { | |
846 | ret = dmaengine_pause(dma->rxchan); | |
847 | if (WARN_ON_ONCE(ret)) | |
848 | priv->rx_dma_broken = true; | |
849 | } | |
eda0cd35 JO |
850 | spin_unlock_irqrestore(&priv->rx_dma_lock, flags); |
851 | ||
b74fdd23 | 852 | __dma_rx_do_complete(p); |
eda0cd35 JO |
853 | } |
854 | ||
33d9b8b2 | 855 | static int omap_8250_rx_dma(struct uart_8250_port *p) |
0e31c8d1 | 856 | { |
eda0cd35 | 857 | struct omap8250_priv *priv = p->port.private_data; |
0e31c8d1 | 858 | struct uart_8250_dma *dma = p->dma; |
eda0cd35 | 859 | int err = 0; |
0e31c8d1 | 860 | struct dma_async_tx_descriptor *desc; |
eda0cd35 | 861 | unsigned long flags; |
0e31c8d1 | 862 | |
830acf9e SAS |
863 | if (priv->rx_dma_broken) |
864 | return -EINVAL; | |
865 | ||
eda0cd35 JO |
866 | spin_lock_irqsave(&priv->rx_dma_lock, flags); |
867 | ||
0e31c8d1 | 868 | if (dma->rx_running) |
eda0cd35 | 869 | goto out; |
0e31c8d1 SAS |
870 | |
871 | desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr, | |
872 | dma->rx_size, DMA_DEV_TO_MEM, | |
873 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
eda0cd35 JO |
874 | if (!desc) { |
875 | err = -EBUSY; | |
876 | goto out; | |
877 | } | |
0e31c8d1 SAS |
878 | |
879 | dma->rx_running = 1; | |
880 | desc->callback = __dma_rx_complete; | |
881 | desc->callback_param = p; | |
882 | ||
883 | dma->rx_cookie = dmaengine_submit(desc); | |
884 | ||
0e31c8d1 | 885 | dma_async_issue_pending(dma->rxchan); |
eda0cd35 JO |
886 | out: |
887 | spin_unlock_irqrestore(&priv->rx_dma_lock, flags); | |
888 | return err; | |
0e31c8d1 SAS |
889 | } |
890 | ||
31a17132 SAS |
891 | static int omap_8250_tx_dma(struct uart_8250_port *p); |
892 | ||
893 | static void omap_8250_dma_tx_complete(void *param) | |
894 | { | |
895 | struct uart_8250_port *p = param; | |
896 | struct uart_8250_dma *dma = p->dma; | |
897 | struct circ_buf *xmit = &p->port.state->xmit; | |
898 | unsigned long flags; | |
899 | bool en_thri = false; | |
0a0661dd | 900 | struct omap8250_priv *priv = p->port.private_data; |
31a17132 SAS |
901 | |
902 | dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, | |
903 | UART_XMIT_SIZE, DMA_TO_DEVICE); | |
904 | ||
905 | spin_lock_irqsave(&p->port.lock, flags); | |
906 | ||
907 | dma->tx_running = 0; | |
908 | ||
909 | xmit->tail += dma->tx_size; | |
910 | xmit->tail &= UART_XMIT_SIZE - 1; | |
911 | p->port.icount.tx += dma->tx_size; | |
912 | ||
0a0661dd SAS |
913 | if (priv->delayed_restore) { |
914 | priv->delayed_restore = 0; | |
915 | omap8250_restore_regs(p); | |
916 | } | |
917 | ||
31a17132 SAS |
918 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
919 | uart_write_wakeup(&p->port); | |
920 | ||
921 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) { | |
922 | int ret; | |
923 | ||
924 | ret = omap_8250_tx_dma(p); | |
925 | if (ret) | |
926 | en_thri = true; | |
31a17132 SAS |
927 | } else if (p->capabilities & UART_CAP_RPM) { |
928 | en_thri = true; | |
929 | } | |
930 | ||
931 | if (en_thri) { | |
932 | dma->tx_err = 1; | |
7e267b29 | 933 | serial8250_set_THRI(p); |
31a17132 SAS |
934 | } |
935 | ||
936 | spin_unlock_irqrestore(&p->port.lock, flags); | |
937 | } | |
938 | ||
939 | static int omap_8250_tx_dma(struct uart_8250_port *p) | |
940 | { | |
941 | struct uart_8250_dma *dma = p->dma; | |
942 | struct omap8250_priv *priv = p->port.private_data; | |
943 | struct circ_buf *xmit = &p->port.state->xmit; | |
944 | struct dma_async_tx_descriptor *desc; | |
945 | unsigned int skip_byte = 0; | |
946 | int ret; | |
947 | ||
948 | if (dma->tx_running) | |
949 | return 0; | |
950 | if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) { | |
951 | ||
952 | /* | |
953 | * Even if no data, we need to return an error for the two cases | |
954 | * below so serial8250_tx_chars() is invoked and properly clears | |
955 | * THRI and/or runtime suspend. | |
956 | */ | |
957 | if (dma->tx_err || p->capabilities & UART_CAP_RPM) { | |
958 | ret = -EBUSY; | |
959 | goto err; | |
960 | } | |
7e267b29 | 961 | serial8250_clear_THRI(p); |
31a17132 SAS |
962 | return 0; |
963 | } | |
964 | ||
965 | dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
966 | if (priv->habit & OMAP_DMA_TX_KICK) { | |
967 | u8 tx_lvl; | |
968 | ||
969 | /* | |
970 | * We need to put the first byte into the FIFO in order to start | |
971 | * the DMA transfer. For transfers smaller than four bytes we | |
972 | * don't bother doing DMA at all. It seem not matter if there | |
973 | * are still bytes in the FIFO from the last transfer (in case | |
974 | * we got here directly from omap_8250_dma_tx_complete()). Bytes | |
975 | * leaving the FIFO seem not to trigger the DMA transfer. It is | |
976 | * really the byte that we put into the FIFO. | |
977 | * If the FIFO is already full then we most likely got here from | |
978 | * omap_8250_dma_tx_complete(). And this means the DMA engine | |
979 | * just completed its work. We don't have to wait the complete | |
980 | * 86us at 115200,8n1 but around 60us (not to mention lower | |
981 | * baudrates). So in that case we take the interrupt and try | |
982 | * again with an empty FIFO. | |
983 | */ | |
984 | tx_lvl = serial_in(p, UART_OMAP_TX_LVL); | |
985 | if (tx_lvl == p->tx_loadsz) { | |
986 | ret = -EBUSY; | |
987 | goto err; | |
988 | } | |
989 | if (dma->tx_size < 4) { | |
990 | ret = -EINVAL; | |
991 | goto err; | |
992 | } | |
993 | skip_byte = 1; | |
994 | } | |
995 | ||
996 | desc = dmaengine_prep_slave_single(dma->txchan, | |
997 | dma->tx_addr + xmit->tail + skip_byte, | |
998 | dma->tx_size - skip_byte, DMA_MEM_TO_DEV, | |
999 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1000 | if (!desc) { | |
1001 | ret = -EBUSY; | |
1002 | goto err; | |
1003 | } | |
1004 | ||
1005 | dma->tx_running = 1; | |
1006 | ||
1007 | desc->callback = omap_8250_dma_tx_complete; | |
1008 | desc->callback_param = p; | |
1009 | ||
1010 | dma->tx_cookie = dmaengine_submit(desc); | |
1011 | ||
1012 | dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr, | |
1013 | UART_XMIT_SIZE, DMA_TO_DEVICE); | |
1014 | ||
1015 | dma_async_issue_pending(dma->txchan); | |
1016 | if (dma->tx_err) | |
1017 | dma->tx_err = 0; | |
1018 | ||
7e267b29 | 1019 | serial8250_clear_THRI(p); |
31a17132 SAS |
1020 | if (skip_byte) |
1021 | serial_out(p, UART_TX, xmit->buf[xmit->tail]); | |
1022 | return 0; | |
1023 | err: | |
1024 | dma->tx_err = 1; | |
1025 | return ret; | |
1026 | } | |
1027 | ||
33d9b8b2 PH |
1028 | static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) |
1029 | { | |
1030 | switch (iir & 0x3f) { | |
1031 | case UART_IIR_RLSI: | |
1032 | case UART_IIR_RX_TIMEOUT: | |
1033 | case UART_IIR_RDI: | |
1034 | omap_8250_rx_dma_flush(up); | |
1035 | return true; | |
1036 | } | |
1037 | return omap_8250_rx_dma(up); | |
1038 | } | |
1039 | ||
77285243 SAS |
1040 | /* |
1041 | * This is mostly serial8250_handle_irq(). We have a slightly different DMA | |
1042 | * hoook for RX/TX and need different logic for them in the ISR. Therefore we | |
1043 | * use the default routine in the non-DMA case and this one for with DMA. | |
1044 | */ | |
1045 | static int omap_8250_dma_handle_irq(struct uart_port *port) | |
1046 | { | |
1047 | struct uart_8250_port *up = up_to_u8250p(port); | |
1048 | unsigned char status; | |
1049 | unsigned long flags; | |
1050 | u8 iir; | |
77285243 SAS |
1051 | |
1052 | serial8250_rpm_get(up); | |
1053 | ||
1054 | iir = serial_port_in(port, UART_IIR); | |
1055 | if (iir & UART_IIR_NO_INT) { | |
1056 | serial8250_rpm_put(up); | |
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | spin_lock_irqsave(&port->lock, flags); | |
1061 | ||
1062 | status = serial_port_in(port, UART_LSR); | |
1063 | ||
1064 | if (status & (UART_LSR_DR | UART_LSR_BI)) { | |
33d9b8b2 | 1065 | if (handle_rx_dma(up, iir)) { |
77285243 | 1066 | status = serial8250_rx_chars(up, status); |
33d9b8b2 | 1067 | omap_8250_rx_dma(up); |
77285243 SAS |
1068 | } |
1069 | } | |
1070 | serial8250_modem_status(up); | |
1071 | if (status & UART_LSR_THRE && up->dma->tx_err) { | |
1072 | if (uart_tx_stopped(&up->port) || | |
1073 | uart_circ_empty(&up->port.state->xmit)) { | |
1074 | up->dma->tx_err = 0; | |
1075 | serial8250_tx_chars(up); | |
1076 | } else { | |
1077 | /* | |
1078 | * try again due to an earlier failer which | |
1079 | * might have been resolved by now. | |
1080 | */ | |
a86f50ed | 1081 | if (omap_8250_tx_dma(up)) |
77285243 SAS |
1082 | serial8250_tx_chars(up); |
1083 | } | |
1084 | } | |
1085 | ||
596f63da | 1086 | uart_unlock_and_check_sysrq(port, flags); |
77285243 SAS |
1087 | serial8250_rpm_put(up); |
1088 | return 1; | |
1089 | } | |
0a0661dd SAS |
1090 | |
1091 | static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param) | |
1092 | { | |
1093 | return false; | |
1094 | } | |
1095 | ||
1096 | #else | |
1097 | ||
33d9b8b2 | 1098 | static inline int omap_8250_rx_dma(struct uart_8250_port *p) |
0a0661dd SAS |
1099 | { |
1100 | return -EINVAL; | |
1101 | } | |
31a17132 SAS |
1102 | #endif |
1103 | ||
9e91597f SAS |
1104 | static int omap8250_no_handle_irq(struct uart_port *port) |
1105 | { | |
1106 | /* IRQ has not been requested but handling irq? */ | |
1107 | WARN_ONCE(1, "Unexpected irq handling before port startup\n"); | |
1108 | return 0; | |
1109 | } | |
1110 | ||
13dc04d0 | 1111 | static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE; |
cdb929e4 | 1112 | static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE; |
b6ffcf21 | 1113 | static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE; |
4fcdff9b SN |
1114 | |
1115 | static const struct of_device_id omap8250_dt_ids[] = { | |
be708744 | 1116 | { .compatible = "ti,am654-uart" }, |
4fcdff9b SN |
1117 | { .compatible = "ti,omap2-uart" }, |
1118 | { .compatible = "ti,omap3-uart" }, | |
13dc04d0 | 1119 | { .compatible = "ti,omap4-uart", .data = &omap4_habit, }, |
4fcdff9b | 1120 | { .compatible = "ti,am3352-uart", .data = &am3352_habit, }, |
b6ffcf21 V |
1121 | { .compatible = "ti,am4372-uart", .data = &am3352_habit, }, |
1122 | { .compatible = "ti,dra742-uart", .data = &dra742_habit, }, | |
4fcdff9b SN |
1123 | {}, |
1124 | }; | |
1125 | MODULE_DEVICE_TABLE(of, omap8250_dt_ids); | |
1126 | ||
61929cf0 SAS |
1127 | static int omap8250_probe(struct platform_device *pdev) |
1128 | { | |
1129 | struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1130 | struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
d6ce4ec0 | 1131 | struct device_node *np = pdev->dev.of_node; |
61929cf0 SAS |
1132 | struct omap8250_priv *priv; |
1133 | struct uart_8250_port up; | |
1134 | int ret; | |
1135 | void __iomem *membase; | |
d6ce4ec0 | 1136 | const struct of_device_id *id; |
61929cf0 SAS |
1137 | |
1138 | if (!regs || !irq) { | |
1139 | dev_err(&pdev->dev, "missing registers or irq\n"); | |
1140 | return -EINVAL; | |
1141 | } | |
1142 | ||
1143 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); | |
1144 | if (!priv) | |
1145 | return -ENOMEM; | |
1146 | ||
1147 | membase = devm_ioremap_nocache(&pdev->dev, regs->start, | |
1148 | resource_size(regs)); | |
1149 | if (!membase) | |
1150 | return -ENODEV; | |
1151 | ||
1152 | memset(&up, 0, sizeof(up)); | |
1153 | up.port.dev = &pdev->dev; | |
1154 | up.port.mapbase = regs->start; | |
1155 | up.port.membase = membase; | |
1156 | up.port.irq = irq->start; | |
1157 | /* | |
1158 | * It claims to be 16C750 compatible however it is a little different. | |
1159 | * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to | |
1160 | * have) is enabled via EFR instead of MCR. The type is set here 8250 | |
1161 | * just to get things going. UNKNOWN does not work for a few reasons and | |
1162 | * we don't need our own type since we don't use 8250's set_termios() | |
1163 | * or pm callback. | |
1164 | */ | |
1165 | up.port.type = PORT_8250; | |
1166 | up.port.iotype = UPIO_MEM; | |
1167 | up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW | | |
1168 | UPF_HARD_FLOW; | |
1169 | up.port.private_data = priv; | |
1170 | ||
1171 | up.port.regshift = 2; | |
1172 | up.port.fifosize = 64; | |
1173 | up.tx_loadsz = 64; | |
1174 | up.capabilities = UART_CAP_FIFO; | |
71504e51 | 1175 | #ifdef CONFIG_PM |
61929cf0 | 1176 | /* |
71504e51 | 1177 | * Runtime PM is mostly transparent. However to do it right we need to a |
61929cf0 | 1178 | * TX empty interrupt before we can put the device to auto idle. So if |
71504e51 RW |
1179 | * PM is not enabled we don't add that flag and can spare that one extra |
1180 | * interrupt in the TX path. | |
61929cf0 SAS |
1181 | */ |
1182 | up.capabilities |= UART_CAP_RPM; | |
1183 | #endif | |
1184 | up.port.set_termios = omap_8250_set_termios; | |
4bf4ea9d | 1185 | up.port.set_mctrl = omap8250_set_mctrl; |
61929cf0 SAS |
1186 | up.port.pm = omap_8250_pm; |
1187 | up.port.startup = omap_8250_startup; | |
1188 | up.port.shutdown = omap_8250_shutdown; | |
1189 | up.port.throttle = omap_8250_throttle; | |
1190 | up.port.unthrottle = omap_8250_unthrottle; | |
344cee24 | 1191 | up.port.rs485_config = omap_8250_rs485_config; |
61929cf0 | 1192 | |
d6ce4ec0 | 1193 | ret = of_alias_get_id(np, "serial"); |
54178fe6 | 1194 | if (ret < 0) { |
d6ce4ec0 | 1195 | dev_err(&pdev->dev, "failed to get alias\n"); |
54178fe6 | 1196 | return ret; |
61929cf0 | 1197 | } |
54178fe6 SAS |
1198 | up.port.line = ret; |
1199 | ||
7d470ebf V |
1200 | if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) { |
1201 | struct clk *clk; | |
1202 | ||
1203 | clk = devm_clk_get(&pdev->dev, NULL); | |
1204 | if (IS_ERR(clk)) { | |
1205 | if (PTR_ERR(clk) == -EPROBE_DEFER) | |
1206 | return -EPROBE_DEFER; | |
1207 | } else { | |
1208 | up.port.uartclk = clk_get_rate(clk); | |
1209 | } | |
1210 | } | |
1211 | ||
d6ce4ec0 V |
1212 | priv->wakeirq = irq_of_parse_and_map(np, 1); |
1213 | ||
1214 | id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev); | |
1215 | if (id && id->data) | |
1216 | priv->habit |= *(u8 *)id->data; | |
1217 | ||
61929cf0 SAS |
1218 | if (!up.port.uartclk) { |
1219 | up.port.uartclk = DEFAULT_CLK_SPEED; | |
1220 | dev_warn(&pdev->dev, | |
1221 | "No clock speed specified: using default: %d\n", | |
1222 | DEFAULT_CLK_SPEED); | |
1223 | } | |
1224 | ||
1225 | priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; | |
1226 | priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; | |
1227 | pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY, | |
1228 | priv->latency); | |
1229 | INIT_WORK(&priv->qos_work, omap8250_uart_qos_work); | |
1230 | ||
eda0cd35 JO |
1231 | spin_lock_init(&priv->rx_dma_lock); |
1232 | ||
61929cf0 | 1233 | device_init_wakeup(&pdev->dev, true); |
4a914531 | 1234 | pm_runtime_enable(&pdev->dev); |
61929cf0 | 1235 | pm_runtime_use_autosuspend(&pdev->dev); |
627a545c TL |
1236 | |
1237 | /* | |
1238 | * Disable runtime PM until autosuspend delay unless specifically | |
1239 | * enabled by the user via sysfs. This is the historic way to | |
1240 | * prevent an unsafe default policy with lossy characters on wake-up. | |
1241 | * For serdev devices this is not needed, the policy can be managed by | |
1242 | * the serdev driver. | |
1243 | */ | |
1244 | if (!of_get_available_child_count(pdev->dev.of_node)) | |
1245 | pm_runtime_set_autosuspend_delay(&pdev->dev, -1); | |
61929cf0 SAS |
1246 | |
1247 | pm_runtime_irq_safe(&pdev->dev); | |
61929cf0 SAS |
1248 | |
1249 | pm_runtime_get_sync(&pdev->dev); | |
1250 | ||
1251 | omap_serial_fill_features_erratas(&up, priv); | |
9e91597f | 1252 | up.port.handle_irq = omap8250_no_handle_irq; |
0a0661dd | 1253 | #ifdef CONFIG_SERIAL_8250_DMA |
d6ce4ec0 V |
1254 | /* |
1255 | * Oh DMA support. If there are no DMA properties in the DT then | |
1256 | * we will fall back to a generic DMA channel which does not | |
1257 | * really work here. To ensure that we do not get a generic DMA | |
1258 | * channel assigned, we have the the_no_dma_filter_fn() here. | |
1259 | * To avoid "failed to request DMA" messages we check for DMA | |
1260 | * properties in DT. | |
1261 | */ | |
1262 | ret = of_property_count_strings(np, "dma-names"); | |
1263 | if (ret == 2) { | |
1264 | up.dma = &priv->omap8250_dma; | |
1265 | priv->omap8250_dma.fn = the_no_dma_filter_fn; | |
1266 | priv->omap8250_dma.tx_dma = omap_8250_tx_dma; | |
1267 | priv->omap8250_dma.rx_dma = omap_8250_rx_dma; | |
1268 | priv->omap8250_dma.rx_size = RX_TRIGGER; | |
1269 | priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER; | |
1270 | priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER; | |
0a0661dd SAS |
1271 | } |
1272 | #endif | |
61929cf0 SAS |
1273 | ret = serial8250_register_8250_port(&up); |
1274 | if (ret < 0) { | |
1275 | dev_err(&pdev->dev, "unable to register 8250 port\n"); | |
1276 | goto err; | |
1277 | } | |
1278 | priv->line = ret; | |
1279 | platform_set_drvdata(pdev, priv); | |
1280 | pm_runtime_mark_last_busy(&pdev->dev); | |
1281 | pm_runtime_put_autosuspend(&pdev->dev); | |
1282 | return 0; | |
1283 | err: | |
4e0f5cc6 TL |
1284 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
1285 | pm_runtime_put_sync(&pdev->dev); | |
61929cf0 SAS |
1286 | pm_runtime_disable(&pdev->dev); |
1287 | return ret; | |
1288 | } | |
1289 | ||
1290 | static int omap8250_remove(struct platform_device *pdev) | |
1291 | { | |
1292 | struct omap8250_priv *priv = platform_get_drvdata(pdev); | |
1293 | ||
4e0f5cc6 | 1294 | pm_runtime_dont_use_autosuspend(&pdev->dev); |
61929cf0 SAS |
1295 | pm_runtime_put_sync(&pdev->dev); |
1296 | pm_runtime_disable(&pdev->dev); | |
1297 | serial8250_unregister_port(priv->line); | |
1298 | pm_qos_remove_request(&priv->pm_qos_request); | |
1299 | device_init_wakeup(&pdev->dev, false); | |
1300 | return 0; | |
1301 | } | |
1302 | ||
61929cf0 SAS |
1303 | #ifdef CONFIG_PM_SLEEP |
1304 | static int omap8250_prepare(struct device *dev) | |
1305 | { | |
1306 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
1307 | ||
1308 | if (!priv) | |
1309 | return 0; | |
1310 | priv->is_suspending = true; | |
1311 | return 0; | |
1312 | } | |
1313 | ||
1314 | static void omap8250_complete(struct device *dev) | |
1315 | { | |
1316 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
1317 | ||
1318 | if (!priv) | |
1319 | return; | |
1320 | priv->is_suspending = false; | |
1321 | } | |
1322 | ||
1323 | static int omap8250_suspend(struct device *dev) | |
1324 | { | |
1325 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
09d8b2bd | 1326 | struct uart_8250_port *up = serial8250_get_port(priv->line); |
61929cf0 SAS |
1327 | |
1328 | serial8250_suspend_port(priv->line); | |
09d8b2bd V |
1329 | |
1330 | pm_runtime_get_sync(dev); | |
1331 | if (!device_may_wakeup(dev)) | |
1332 | priv->wer = 0; | |
1333 | serial_out(up, UART_OMAP_WER, priv->wer); | |
1334 | pm_runtime_mark_last_busy(dev); | |
1335 | pm_runtime_put_autosuspend(dev); | |
1336 | ||
61929cf0 | 1337 | flush_work(&priv->qos_work); |
61929cf0 SAS |
1338 | return 0; |
1339 | } | |
1340 | ||
1341 | static int omap8250_resume(struct device *dev) | |
1342 | { | |
1343 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
1344 | ||
61929cf0 SAS |
1345 | serial8250_resume_port(priv->line); |
1346 | return 0; | |
1347 | } | |
1348 | #else | |
1349 | #define omap8250_prepare NULL | |
1350 | #define omap8250_complete NULL | |
1351 | #endif | |
1352 | ||
71504e51 | 1353 | #ifdef CONFIG_PM |
61929cf0 SAS |
1354 | static int omap8250_lost_context(struct uart_8250_port *up) |
1355 | { | |
1356 | u32 val; | |
1357 | ||
cdb929e4 | 1358 | val = serial_in(up, UART_OMAP_SCR); |
61929cf0 | 1359 | /* |
cdb929e4 SN |
1360 | * If we lose context, then SCR is set to its reset value of zero. |
1361 | * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1, | |
1362 | * among other bits, to never set the register back to zero again. | |
61929cf0 | 1363 | */ |
cdb929e4 | 1364 | if (!val) |
61929cf0 SAS |
1365 | return 1; |
1366 | return 0; | |
1367 | } | |
1368 | ||
cdb929e4 SN |
1369 | /* TODO: in future, this should happen via API in drivers/reset/ */ |
1370 | static int omap8250_soft_reset(struct device *dev) | |
1371 | { | |
1372 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
1373 | struct uart_8250_port *up = serial8250_get_port(priv->line); | |
1374 | int timeout = 100; | |
1375 | int sysc; | |
1376 | int syss; | |
1377 | ||
13dc04d0 TL |
1378 | /* |
1379 | * At least on omap4, unused uarts may not idle after reset without | |
1380 | * a basic scr dma configuration even with no dma in use. The | |
1381 | * module clkctrl status bits will be 1 instead of 3 blocking idle | |
1382 | * for the whole clockdomain. The softreset below will clear scr, | |
1383 | * and we restore it on resume so this is safe to do on all SoCs | |
1384 | * needing omap8250_soft_reset() quirk. Do it in two writes as | |
1385 | * recommended in the comment for omap8250_update_scr(). | |
1386 | */ | |
1387 | serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1); | |
1388 | serial_out(up, UART_OMAP_SCR, | |
1389 | OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL); | |
1390 | ||
cdb929e4 SN |
1391 | sysc = serial_in(up, UART_OMAP_SYSC); |
1392 | ||
1393 | /* softreset the UART */ | |
1394 | sysc |= OMAP_UART_SYSC_SOFTRESET; | |
1395 | serial_out(up, UART_OMAP_SYSC, sysc); | |
1396 | ||
1397 | /* By experiments, 1us enough for reset complete on AM335x */ | |
1398 | do { | |
1399 | udelay(1); | |
1400 | syss = serial_in(up, UART_OMAP_SYSS); | |
1401 | } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE)); | |
1402 | ||
1403 | if (!timeout) { | |
1404 | dev_err(dev, "timed out waiting for reset done\n"); | |
1405 | return -ETIMEDOUT; | |
1406 | } | |
1407 | ||
1408 | return 0; | |
1409 | } | |
1410 | ||
61929cf0 SAS |
1411 | static int omap8250_runtime_suspend(struct device *dev) |
1412 | { | |
1413 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
1414 | struct uart_8250_port *up; | |
1415 | ||
4e0f5cc6 TL |
1416 | /* In case runtime-pm tries this before we are setup */ |
1417 | if (!priv) | |
1418 | return 0; | |
1419 | ||
61929cf0 SAS |
1420 | up = serial8250_get_port(priv->line); |
1421 | /* | |
1422 | * When using 'no_console_suspend', the console UART must not be | |
1423 | * suspended. Since driver suspend is managed by runtime suspend, | |
1424 | * preventing runtime suspend (by returning error) will keep device | |
1425 | * active during suspend. | |
1426 | */ | |
1427 | if (priv->is_suspending && !console_suspend_enabled) { | |
1428 | if (uart_console(&up->port)) | |
1429 | return -EBUSY; | |
1430 | } | |
1431 | ||
cdb929e4 SN |
1432 | if (priv->habit & UART_ERRATA_CLOCK_DISABLE) { |
1433 | int ret; | |
1434 | ||
1435 | ret = omap8250_soft_reset(dev); | |
1436 | if (ret) | |
1437 | return ret; | |
1438 | ||
1439 | /* Restore to UART mode after reset (for wakeup) */ | |
1440 | omap8250_update_mdr1(up, priv); | |
09d8b2bd V |
1441 | /* Restore wakeup enable register */ |
1442 | serial_out(up, UART_OMAP_WER, priv->wer); | |
cdb929e4 SN |
1443 | } |
1444 | ||
727fd8ab | 1445 | if (up->dma && up->dma->rxchan) |
33d9b8b2 | 1446 | omap_8250_rx_dma_flush(up); |
61929cf0 SAS |
1447 | |
1448 | priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; | |
1449 | schedule_work(&priv->qos_work); | |
1450 | ||
1451 | return 0; | |
1452 | } | |
1453 | ||
1454 | static int omap8250_runtime_resume(struct device *dev) | |
1455 | { | |
1456 | struct omap8250_priv *priv = dev_get_drvdata(dev); | |
1457 | struct uart_8250_port *up; | |
61929cf0 SAS |
1458 | |
1459 | /* In case runtime-pm tries this before we are setup */ | |
1460 | if (!priv) | |
1461 | return 0; | |
1462 | ||
1463 | up = serial8250_get_port(priv->line); | |
61929cf0 | 1464 | |
f56f0a54 | 1465 | if (omap8250_lost_context(up)) |
61929cf0 SAS |
1466 | omap8250_restore_regs(up); |
1467 | ||
727fd8ab | 1468 | if (up->dma && up->dma->rxchan) |
33d9b8b2 | 1469 | omap_8250_rx_dma(up); |
0a0661dd | 1470 | |
61929cf0 SAS |
1471 | priv->latency = priv->calc_latency; |
1472 | schedule_work(&priv->qos_work); | |
1473 | return 0; | |
1474 | } | |
1475 | #endif | |
1476 | ||
00648d02 SAS |
1477 | #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP |
1478 | static int __init omap8250_console_fixup(void) | |
1479 | { | |
1480 | char *omap_str; | |
1481 | char *options; | |
1482 | u8 idx; | |
1483 | ||
1484 | if (strstr(boot_command_line, "console=ttyS")) | |
1485 | /* user set a ttyS based name for the console */ | |
1486 | return 0; | |
1487 | ||
1488 | omap_str = strstr(boot_command_line, "console=ttyO"); | |
1489 | if (!omap_str) | |
1490 | /* user did not set ttyO based console, so we don't care */ | |
1491 | return 0; | |
1492 | ||
1493 | omap_str += 12; | |
1494 | if ('0' <= *omap_str && *omap_str <= '9') | |
1495 | idx = *omap_str - '0'; | |
1496 | else | |
1497 | return 0; | |
1498 | ||
1499 | omap_str++; | |
1500 | if (omap_str[0] == ',') { | |
1501 | omap_str++; | |
1502 | options = omap_str; | |
1503 | } else { | |
1504 | options = NULL; | |
1505 | } | |
1506 | ||
1507 | add_preferred_console("ttyS", idx, options); | |
1508 | pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n", | |
1509 | idx, idx); | |
1510 | pr_err("This ensures that you still see kernel messages. Please\n"); | |
1511 | pr_err("update your kernel commandline.\n"); | |
1512 | return 0; | |
1513 | } | |
1514 | console_initcall(omap8250_console_fixup); | |
1515 | #endif | |
1516 | ||
61929cf0 SAS |
1517 | static const struct dev_pm_ops omap8250_dev_pm_ops = { |
1518 | SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume) | |
1519 | SET_RUNTIME_PM_OPS(omap8250_runtime_suspend, | |
1520 | omap8250_runtime_resume, NULL) | |
1521 | .prepare = omap8250_prepare, | |
1522 | .complete = omap8250_complete, | |
1523 | }; | |
1524 | ||
61929cf0 SAS |
1525 | static struct platform_driver omap8250_platform_driver = { |
1526 | .driver = { | |
1527 | .name = "omap8250", | |
1528 | .pm = &omap8250_dev_pm_ops, | |
1529 | .of_match_table = omap8250_dt_ids, | |
61929cf0 SAS |
1530 | }, |
1531 | .probe = omap8250_probe, | |
1532 | .remove = omap8250_remove, | |
1533 | }; | |
1534 | module_platform_driver(omap8250_platform_driver); | |
1535 | ||
1536 | MODULE_AUTHOR("Sebastian Andrzej Siewior"); | |
1537 | MODULE_DESCRIPTION("OMAP 8250 Driver"); | |
1538 | MODULE_LICENSE("GPL v2"); |