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Commit | Line | Data |
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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * Probe module for 8250/16550-type PCI serial ports. |
4 | * | |
5 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
6 | * | |
7 | * Copyright (C) 2001 Russell King, All Rights Reserved. | |
1da177e4 | 8 | */ |
af8c5b8d | 9 | #undef DEBUG |
1da177e4 | 10 | #include <linux/module.h> |
1da177e4 | 11 | #include <linux/pci.h> |
1da177e4 LT |
12 | #include <linux/string.h> |
13 | #include <linux/kernel.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/tty.h> | |
0ad372b9 | 17 | #include <linux/serial_reg.h> |
1da177e4 LT |
18 | #include <linux/serial_core.h> |
19 | #include <linux/8250_pci.h> | |
20 | #include <linux/bitops.h> | |
21 | ||
22 | #include <asm/byteorder.h> | |
23 | #include <asm/io.h> | |
24 | ||
25 | #include "8250.h" | |
26 | ||
1da177e4 LT |
27 | /* |
28 | * init function returns: | |
29 | * > 0 - number of ports | |
30 | * = 0 - use board->num_ports | |
31 | * < 0 - error | |
32 | */ | |
33 | struct pci_serial_quirk { | |
34 | u32 vendor; | |
35 | u32 device; | |
36 | u32 subvendor; | |
37 | u32 subdevice; | |
5bf8f501 | 38 | int (*probe)(struct pci_dev *dev); |
1da177e4 | 39 | int (*init)(struct pci_dev *dev); |
975a1a7d RK |
40 | int (*setup)(struct serial_private *, |
41 | const struct pciserial_board *, | |
2655a2c7 | 42 | struct uart_8250_port *, int); |
1da177e4 LT |
43 | void (*exit)(struct pci_dev *dev); |
44 | }; | |
45 | ||
46 | #define PCI_NUM_BAR_RESOURCES 6 | |
47 | ||
48 | struct serial_private { | |
70db3d91 | 49 | struct pci_dev *dev; |
1da177e4 | 50 | unsigned int nr; |
1da177e4 | 51 | struct pci_serial_quirk *quirk; |
f209fa03 | 52 | const struct pciserial_board *board; |
1da177e4 LT |
53 | int line[0]; |
54 | }; | |
55 | ||
7808edcd | 56 | static int pci_default_setup(struct serial_private*, |
2655a2c7 | 57 | const struct pciserial_board*, struct uart_8250_port *, int); |
7808edcd | 58 | |
1da177e4 LT |
59 | static void moan_device(const char *str, struct pci_dev *dev) |
60 | { | |
af8c5b8d | 61 | dev_err(&dev->dev, |
ad361c98 JP |
62 | "%s: %s\n" |
63 | "Please send the output of lspci -vv, this\n" | |
64 | "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" | |
65 | "manufacturer and name of serial board or\n" | |
f2e0ea86 | 66 | "modem board to <linux-serial@vger.kernel.org>.\n", |
1da177e4 LT |
67 | pci_name(dev), str, dev->vendor, dev->device, |
68 | dev->subsystem_vendor, dev->subsystem_device); | |
69 | } | |
70 | ||
71 | static int | |
2655a2c7 | 72 | setup_port(struct serial_private *priv, struct uart_8250_port *port, |
1da177e4 LT |
73 | int bar, int offset, int regshift) |
74 | { | |
70db3d91 | 75 | struct pci_dev *dev = priv->dev; |
1da177e4 LT |
76 | |
77 | if (bar >= PCI_NUM_BAR_RESOURCES) | |
78 | return -EINVAL; | |
79 | ||
80 | if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) { | |
3f64b1d3 | 81 | if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev)) |
1da177e4 LT |
82 | return -ENOMEM; |
83 | ||
2655a2c7 AC |
84 | port->port.iotype = UPIO_MEM; |
85 | port->port.iobase = 0; | |
398a9db6 | 86 | port->port.mapbase = pci_resource_start(dev, bar) + offset; |
3f64b1d3 | 87 | port->port.membase = pcim_iomap_table(dev)[bar] + offset; |
2655a2c7 | 88 | port->port.regshift = regshift; |
1da177e4 | 89 | } else { |
2655a2c7 | 90 | port->port.iotype = UPIO_PORT; |
398a9db6 | 91 | port->port.iobase = pci_resource_start(dev, bar) + offset; |
2655a2c7 AC |
92 | port->port.mapbase = 0; |
93 | port->port.membase = NULL; | |
94 | port->port.regshift = 0; | |
1da177e4 LT |
95 | } |
96 | return 0; | |
97 | } | |
98 | ||
02c9b5cf KJ |
99 | /* |
100 | * ADDI-DATA GmbH communication cards <info@addi-data.com> | |
101 | */ | |
102 | static int addidata_apci7800_setup(struct serial_private *priv, | |
975a1a7d | 103 | const struct pciserial_board *board, |
2655a2c7 | 104 | struct uart_8250_port *port, int idx) |
02c9b5cf KJ |
105 | { |
106 | unsigned int bar = 0, offset = board->first_offset; | |
107 | bar = FL_GET_BASE(board->flags); | |
108 | ||
109 | if (idx < 2) { | |
110 | offset += idx * board->uart_offset; | |
111 | } else if ((idx >= 2) && (idx < 4)) { | |
112 | bar += 1; | |
113 | offset += ((idx - 2) * board->uart_offset); | |
114 | } else if ((idx >= 4) && (idx < 6)) { | |
115 | bar += 2; | |
116 | offset += ((idx - 4) * board->uart_offset); | |
117 | } else if (idx >= 6) { | |
118 | bar += 3; | |
119 | offset += ((idx - 6) * board->uart_offset); | |
120 | } | |
121 | ||
122 | return setup_port(priv, port, bar, offset, board->reg_shift); | |
123 | } | |
124 | ||
1da177e4 LT |
125 | /* |
126 | * AFAVLAB uses a different mixture of BARs and offsets | |
127 | * Not that ugly ;) -- HW | |
128 | */ | |
129 | static int | |
975a1a7d | 130 | afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, |
2655a2c7 | 131 | struct uart_8250_port *port, int idx) |
1da177e4 LT |
132 | { |
133 | unsigned int bar, offset = board->first_offset; | |
5756ee99 | 134 | |
1da177e4 LT |
135 | bar = FL_GET_BASE(board->flags); |
136 | if (idx < 4) | |
137 | bar += idx; | |
138 | else { | |
139 | bar = 4; | |
140 | offset += (idx - 4) * board->uart_offset; | |
141 | } | |
142 | ||
70db3d91 | 143 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
144 | } |
145 | ||
146 | /* | |
147 | * HP's Remote Management Console. The Diva chip came in several | |
148 | * different versions. N-class, L2000 and A500 have two Diva chips, each | |
149 | * with 3 UARTs (the third UART on the second chip is unused). Superdome | |
150 | * and Keystone have one Diva chip with 3 UARTs. Some later machines have | |
151 | * one Diva chip, but it has been expanded to 5 UARTs. | |
152 | */ | |
61a116ef | 153 | static int pci_hp_diva_init(struct pci_dev *dev) |
1da177e4 LT |
154 | { |
155 | int rc = 0; | |
156 | ||
157 | switch (dev->subsystem_device) { | |
158 | case PCI_DEVICE_ID_HP_DIVA_TOSCA1: | |
159 | case PCI_DEVICE_ID_HP_DIVA_HALFDOME: | |
160 | case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: | |
161 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: | |
162 | rc = 3; | |
163 | break; | |
164 | case PCI_DEVICE_ID_HP_DIVA_TOSCA2: | |
165 | rc = 2; | |
166 | break; | |
167 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: | |
168 | rc = 4; | |
169 | break; | |
170 | case PCI_DEVICE_ID_HP_DIVA_POWERBAR: | |
551f8f0e | 171 | case PCI_DEVICE_ID_HP_DIVA_HURRICANE: |
1da177e4 LT |
172 | rc = 1; |
173 | break; | |
174 | } | |
175 | ||
176 | return rc; | |
177 | } | |
178 | ||
179 | /* | |
180 | * HP's Diva chip puts the 4th/5th serial port further out, and | |
181 | * some serial ports are supposed to be hidden on certain models. | |
182 | */ | |
183 | static int | |
975a1a7d RK |
184 | pci_hp_diva_setup(struct serial_private *priv, |
185 | const struct pciserial_board *board, | |
2655a2c7 | 186 | struct uart_8250_port *port, int idx) |
1da177e4 LT |
187 | { |
188 | unsigned int offset = board->first_offset; | |
189 | unsigned int bar = FL_GET_BASE(board->flags); | |
190 | ||
70db3d91 | 191 | switch (priv->dev->subsystem_device) { |
1da177e4 LT |
192 | case PCI_DEVICE_ID_HP_DIVA_MAESTRO: |
193 | if (idx == 3) | |
194 | idx++; | |
195 | break; | |
196 | case PCI_DEVICE_ID_HP_DIVA_EVEREST: | |
197 | if (idx > 0) | |
198 | idx++; | |
199 | if (idx > 2) | |
200 | idx++; | |
201 | break; | |
202 | } | |
203 | if (idx > 2) | |
204 | offset = 0x18; | |
205 | ||
206 | offset += idx * board->uart_offset; | |
207 | ||
70db3d91 | 208 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
209 | } |
210 | ||
211 | /* | |
212 | * Added for EKF Intel i960 serial boards | |
213 | */ | |
61a116ef | 214 | static int pci_inteli960ni_init(struct pci_dev *dev) |
1da177e4 | 215 | { |
0a0d412a | 216 | u32 oldval; |
1da177e4 LT |
217 | |
218 | if (!(dev->subsystem_device & 0x1000)) | |
219 | return -ENODEV; | |
220 | ||
221 | /* is firmware started? */ | |
0a0d412a | 222 | pci_read_config_dword(dev, 0x44, &oldval); |
5756ee99 | 223 | if (oldval == 0x00001000L) { /* RESET value */ |
af8c5b8d | 224 | dev_dbg(&dev->dev, "Local i960 firmware missing\n"); |
1da177e4 LT |
225 | return -ENODEV; |
226 | } | |
227 | return 0; | |
228 | } | |
229 | ||
230 | /* | |
231 | * Some PCI serial cards using the PLX 9050 PCI interface chip require | |
232 | * that the card interrupt be explicitly enabled or disabled. This | |
233 | * seems to be mainly needed on card using the PLX which also use I/O | |
234 | * mapped memory. | |
235 | */ | |
61a116ef | 236 | static int pci_plx9050_init(struct pci_dev *dev) |
1da177e4 LT |
237 | { |
238 | u8 irq_config; | |
239 | void __iomem *p; | |
240 | ||
241 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { | |
242 | moan_device("no memory in bar 0", dev); | |
243 | return 0; | |
244 | } | |
245 | ||
246 | irq_config = 0x41; | |
add7b58e | 247 | if (dev->vendor == PCI_VENDOR_ID_PANACOM || |
5756ee99 | 248 | dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) |
1da177e4 | 249 | irq_config = 0x43; |
5756ee99 | 250 | |
1da177e4 | 251 | if ((dev->vendor == PCI_VENDOR_ID_PLX) && |
5756ee99 | 252 | (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) |
1da177e4 LT |
253 | /* |
254 | * As the megawolf cards have the int pins active | |
255 | * high, and have 2 UART chips, both ints must be | |
256 | * enabled on the 9050. Also, the UARTS are set in | |
257 | * 16450 mode by default, so we have to enable the | |
258 | * 16C950 'enhanced' mode so that we can use the | |
259 | * deep FIFOs | |
260 | */ | |
261 | irq_config = 0x5b; | |
1da177e4 LT |
262 | /* |
263 | * enable/disable interrupts | |
264 | */ | |
6f441fe9 | 265 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); |
1da177e4 LT |
266 | if (p == NULL) |
267 | return -ENOMEM; | |
268 | writel(irq_config, p + 0x4c); | |
269 | ||
270 | /* | |
271 | * Read the register back to ensure that it took effect. | |
272 | */ | |
273 | readl(p + 0x4c); | |
274 | iounmap(p); | |
275 | ||
276 | return 0; | |
277 | } | |
278 | ||
ae8d8a14 | 279 | static void pci_plx9050_exit(struct pci_dev *dev) |
1da177e4 LT |
280 | { |
281 | u8 __iomem *p; | |
282 | ||
283 | if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) | |
284 | return; | |
285 | ||
286 | /* | |
287 | * disable interrupts | |
288 | */ | |
6f441fe9 | 289 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); |
1da177e4 LT |
290 | if (p != NULL) { |
291 | writel(0, p + 0x4c); | |
292 | ||
293 | /* | |
294 | * Read the register back to ensure that it took effect. | |
295 | */ | |
296 | readl(p + 0x4c); | |
297 | iounmap(p); | |
298 | } | |
299 | } | |
300 | ||
04bf7e74 WP |
301 | #define NI8420_INT_ENABLE_REG 0x38 |
302 | #define NI8420_INT_ENABLE_BIT 0x2000 | |
303 | ||
ae8d8a14 | 304 | static void pci_ni8420_exit(struct pci_dev *dev) |
04bf7e74 WP |
305 | { |
306 | void __iomem *p; | |
04bf7e74 WP |
307 | unsigned int bar = 0; |
308 | ||
309 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | |
310 | moan_device("no memory in bar", dev); | |
311 | return; | |
312 | } | |
313 | ||
398a9db6 | 314 | p = pci_ioremap_bar(dev, bar); |
04bf7e74 WP |
315 | if (p == NULL) |
316 | return; | |
317 | ||
318 | /* Disable the CPU Interrupt */ | |
319 | writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), | |
320 | p + NI8420_INT_ENABLE_REG); | |
321 | iounmap(p); | |
322 | } | |
323 | ||
324 | ||
46a0fac9 SB |
325 | /* MITE registers */ |
326 | #define MITE_IOWBSR1 0xc4 | |
327 | #define MITE_IOWCR1 0xf4 | |
328 | #define MITE_LCIMR1 0x08 | |
329 | #define MITE_LCIMR2 0x10 | |
330 | ||
331 | #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) | |
332 | ||
ae8d8a14 | 333 | static void pci_ni8430_exit(struct pci_dev *dev) |
46a0fac9 SB |
334 | { |
335 | void __iomem *p; | |
46a0fac9 SB |
336 | unsigned int bar = 0; |
337 | ||
338 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | |
339 | moan_device("no memory in bar", dev); | |
340 | return; | |
341 | } | |
342 | ||
398a9db6 | 343 | p = pci_ioremap_bar(dev, bar); |
46a0fac9 SB |
344 | if (p == NULL) |
345 | return; | |
346 | ||
347 | /* Disable the CPU Interrupt */ | |
348 | writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); | |
349 | iounmap(p); | |
350 | } | |
351 | ||
1da177e4 LT |
352 | /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ |
353 | static int | |
975a1a7d | 354 | sbs_setup(struct serial_private *priv, const struct pciserial_board *board, |
2655a2c7 | 355 | struct uart_8250_port *port, int idx) |
1da177e4 LT |
356 | { |
357 | unsigned int bar, offset = board->first_offset; | |
358 | ||
359 | bar = 0; | |
360 | ||
361 | if (idx < 4) { | |
362 | /* first four channels map to 0, 0x100, 0x200, 0x300 */ | |
363 | offset += idx * board->uart_offset; | |
364 | } else if (idx < 8) { | |
365 | /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ | |
366 | offset += idx * board->uart_offset + 0xC00; | |
367 | } else /* we have only 8 ports on PMC-OCTALPRO */ | |
368 | return 1; | |
369 | ||
70db3d91 | 370 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
371 | } |
372 | ||
373 | /* | |
374 | * This does initialization for PMC OCTALPRO cards: | |
375 | * maps the device memory, resets the UARTs (needed, bc | |
376 | * if the module is removed and inserted again, the card | |
377 | * is in the sleep mode) and enables global interrupt. | |
378 | */ | |
379 | ||
380 | /* global control register offset for SBS PMC-OctalPro */ | |
381 | #define OCT_REG_CR_OFF 0x500 | |
382 | ||
61a116ef | 383 | static int sbs_init(struct pci_dev *dev) |
1da177e4 LT |
384 | { |
385 | u8 __iomem *p; | |
386 | ||
24ed3aba | 387 | p = pci_ioremap_bar(dev, 0); |
1da177e4 LT |
388 | |
389 | if (p == NULL) | |
390 | return -ENOMEM; | |
391 | /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ | |
5756ee99 | 392 | writeb(0x10, p + OCT_REG_CR_OFF); |
1da177e4 | 393 | udelay(50); |
5756ee99 | 394 | writeb(0x0, p + OCT_REG_CR_OFF); |
1da177e4 LT |
395 | |
396 | /* Set bit-2 (INTENABLE) of Control Register */ | |
397 | writeb(0x4, p + OCT_REG_CR_OFF); | |
398 | iounmap(p); | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
403 | /* | |
404 | * Disables the global interrupt of PMC-OctalPro | |
405 | */ | |
406 | ||
ae8d8a14 | 407 | static void sbs_exit(struct pci_dev *dev) |
1da177e4 LT |
408 | { |
409 | u8 __iomem *p; | |
410 | ||
24ed3aba | 411 | p = pci_ioremap_bar(dev, 0); |
5756ee99 AC |
412 | /* FIXME: What if resource_len < OCT_REG_CR_OFF */ |
413 | if (p != NULL) | |
1da177e4 | 414 | writeb(0, p + OCT_REG_CR_OFF); |
1da177e4 LT |
415 | iounmap(p); |
416 | } | |
417 | ||
418 | /* | |
419 | * SIIG serial cards have an PCI interface chip which also controls | |
420 | * the UART clocking frequency. Each UART can be clocked independently | |
25985edc | 421 | * (except cards equipped with 4 UARTs) and initial clocking settings |
1da177e4 LT |
422 | * are stored in the EEPROM chip. It can cause problems because this |
423 | * version of serial driver doesn't support differently clocked UART's | |
424 | * on single PCI card. To prevent this, initialization functions set | |
425 | * high frequency clocking for all UART's on given card. It is safe (I | |
426 | * hope) because it doesn't touch EEPROM settings to prevent conflicts | |
427 | * with other OSes (like M$ DOS). | |
428 | * | |
429 | * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 | |
5756ee99 | 430 | * |
1da177e4 LT |
431 | * There is two family of SIIG serial cards with different PCI |
432 | * interface chip and different configuration methods: | |
433 | * - 10x cards have control registers in IO and/or memory space; | |
434 | * - 20x cards have control registers in standard PCI configuration space. | |
435 | * | |
67d74b87 RK |
436 | * Note: all 10x cards have PCI device ids 0x10.. |
437 | * all 20x cards have PCI device ids 0x20.. | |
438 | * | |
fbc0dc0d AP |
439 | * There are also Quartet Serial cards which use Oxford Semiconductor |
440 | * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. | |
441 | * | |
1da177e4 LT |
442 | * Note: some SIIG cards are probed by the parport_serial object. |
443 | */ | |
444 | ||
445 | #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) | |
446 | #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) | |
447 | ||
448 | static int pci_siig10x_init(struct pci_dev *dev) | |
449 | { | |
450 | u16 data; | |
451 | void __iomem *p; | |
452 | ||
453 | switch (dev->device & 0xfff8) { | |
454 | case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ | |
455 | data = 0xffdf; | |
456 | break; | |
457 | case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ | |
458 | data = 0xf7ff; | |
459 | break; | |
460 | default: /* 1S1P, 4S */ | |
461 | data = 0xfffb; | |
462 | break; | |
463 | } | |
464 | ||
6f441fe9 | 465 | p = ioremap_nocache(pci_resource_start(dev, 0), 0x80); |
1da177e4 LT |
466 | if (p == NULL) |
467 | return -ENOMEM; | |
468 | ||
469 | writew(readw(p + 0x28) & data, p + 0x28); | |
470 | readw(p + 0x28); | |
471 | iounmap(p); | |
472 | return 0; | |
473 | } | |
474 | ||
475 | #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) | |
476 | #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) | |
477 | ||
478 | static int pci_siig20x_init(struct pci_dev *dev) | |
479 | { | |
480 | u8 data; | |
481 | ||
482 | /* Change clock frequency for the first UART. */ | |
483 | pci_read_config_byte(dev, 0x6f, &data); | |
484 | pci_write_config_byte(dev, 0x6f, data & 0xef); | |
485 | ||
486 | /* If this card has 2 UART, we have to do the same with second UART. */ | |
487 | if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || | |
488 | ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { | |
489 | pci_read_config_byte(dev, 0x73, &data); | |
490 | pci_write_config_byte(dev, 0x73, data & 0xef); | |
491 | } | |
492 | return 0; | |
493 | } | |
494 | ||
67d74b87 RK |
495 | static int pci_siig_init(struct pci_dev *dev) |
496 | { | |
497 | unsigned int type = dev->device & 0xff00; | |
498 | ||
499 | if (type == 0x1000) | |
500 | return pci_siig10x_init(dev); | |
501 | else if (type == 0x2000) | |
502 | return pci_siig20x_init(dev); | |
503 | ||
504 | moan_device("Unknown SIIG card", dev); | |
505 | return -ENODEV; | |
506 | } | |
507 | ||
3ec9c594 | 508 | static int pci_siig_setup(struct serial_private *priv, |
975a1a7d | 509 | const struct pciserial_board *board, |
2655a2c7 | 510 | struct uart_8250_port *port, int idx) |
3ec9c594 AP |
511 | { |
512 | unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; | |
513 | ||
514 | if (idx > 3) { | |
515 | bar = 4; | |
516 | offset = (idx - 4) * 8; | |
517 | } | |
518 | ||
519 | return setup_port(priv, port, bar, offset, 0); | |
520 | } | |
521 | ||
1da177e4 LT |
522 | /* |
523 | * Timedia has an explosion of boards, and to avoid the PCI table from | |
524 | * growing *huge*, we use this function to collapse some 70 entries | |
525 | * in the PCI table into one, for sanity's and compactness's sake. | |
526 | */ | |
e9422e09 | 527 | static const unsigned short timedia_single_port[] = { |
1da177e4 LT |
528 | 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 |
529 | }; | |
530 | ||
e9422e09 | 531 | static const unsigned short timedia_dual_port[] = { |
1da177e4 | 532 | 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, |
5756ee99 AC |
533 | 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, |
534 | 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, | |
1da177e4 LT |
535 | 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, |
536 | 0xD079, 0 | |
537 | }; | |
538 | ||
e9422e09 | 539 | static const unsigned short timedia_quad_port[] = { |
5756ee99 AC |
540 | 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, |
541 | 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, | |
1da177e4 LT |
542 | 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, |
543 | 0xB157, 0 | |
544 | }; | |
545 | ||
e9422e09 | 546 | static const unsigned short timedia_eight_port[] = { |
5756ee99 | 547 | 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, |
1da177e4 LT |
548 | 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 |
549 | }; | |
550 | ||
cb3592be | 551 | static const struct timedia_struct { |
1da177e4 | 552 | int num; |
e9422e09 | 553 | const unsigned short *ids; |
1da177e4 LT |
554 | } timedia_data[] = { |
555 | { 1, timedia_single_port }, | |
556 | { 2, timedia_dual_port }, | |
557 | { 4, timedia_quad_port }, | |
e9422e09 | 558 | { 8, timedia_eight_port } |
1da177e4 LT |
559 | }; |
560 | ||
b9b24558 FB |
561 | /* |
562 | * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of | |
563 | * listing them individually, this driver merely grabs them all with | |
564 | * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, | |
565 | * and should be left free to be claimed by parport_serial instead. | |
566 | */ | |
567 | static int pci_timedia_probe(struct pci_dev *dev) | |
568 | { | |
569 | /* | |
570 | * Check the third digit of the subdevice ID | |
571 | * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) | |
572 | */ | |
573 | if ((dev->subsystem_device & 0x00f0) >= 0x70) { | |
574 | dev_info(&dev->dev, | |
575 | "ignoring Timedia subdevice %04x for parport_serial\n", | |
576 | dev->subsystem_device); | |
577 | return -ENODEV; | |
578 | } | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
61a116ef | 583 | static int pci_timedia_init(struct pci_dev *dev) |
1da177e4 | 584 | { |
e9422e09 | 585 | const unsigned short *ids; |
1da177e4 LT |
586 | int i, j; |
587 | ||
e9422e09 | 588 | for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { |
1da177e4 LT |
589 | ids = timedia_data[i].ids; |
590 | for (j = 0; ids[j]; j++) | |
591 | if (dev->subsystem_device == ids[j]) | |
592 | return timedia_data[i].num; | |
593 | } | |
594 | return 0; | |
595 | } | |
596 | ||
597 | /* | |
598 | * Timedia/SUNIX uses a mixture of BARs and offsets | |
599 | * Ugh, this is ugly as all hell --- TYT | |
600 | */ | |
601 | static int | |
975a1a7d RK |
602 | pci_timedia_setup(struct serial_private *priv, |
603 | const struct pciserial_board *board, | |
2655a2c7 | 604 | struct uart_8250_port *port, int idx) |
1da177e4 LT |
605 | { |
606 | unsigned int bar = 0, offset = board->first_offset; | |
607 | ||
608 | switch (idx) { | |
609 | case 0: | |
610 | bar = 0; | |
611 | break; | |
612 | case 1: | |
613 | offset = board->uart_offset; | |
614 | bar = 0; | |
615 | break; | |
616 | case 2: | |
617 | bar = 1; | |
618 | break; | |
619 | case 3: | |
620 | offset = board->uart_offset; | |
c2cd6d3c | 621 | /* FALLTHROUGH */ |
1da177e4 LT |
622 | case 4: /* BAR 2 */ |
623 | case 5: /* BAR 3 */ | |
624 | case 6: /* BAR 4 */ | |
625 | case 7: /* BAR 5 */ | |
626 | bar = idx - 2; | |
627 | } | |
628 | ||
70db3d91 | 629 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
630 | } |
631 | ||
632 | /* | |
633 | * Some Titan cards are also a little weird | |
634 | */ | |
635 | static int | |
70db3d91 | 636 | titan_400l_800l_setup(struct serial_private *priv, |
975a1a7d | 637 | const struct pciserial_board *board, |
2655a2c7 | 638 | struct uart_8250_port *port, int idx) |
1da177e4 LT |
639 | { |
640 | unsigned int bar, offset = board->first_offset; | |
641 | ||
642 | switch (idx) { | |
643 | case 0: | |
644 | bar = 1; | |
645 | break; | |
646 | case 1: | |
647 | bar = 2; | |
648 | break; | |
649 | default: | |
650 | bar = 4; | |
651 | offset = (idx - 2) * board->uart_offset; | |
652 | } | |
653 | ||
70db3d91 | 654 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
655 | } |
656 | ||
61a116ef | 657 | static int pci_xircom_init(struct pci_dev *dev) |
1da177e4 LT |
658 | { |
659 | msleep(100); | |
660 | return 0; | |
661 | } | |
662 | ||
04bf7e74 WP |
663 | static int pci_ni8420_init(struct pci_dev *dev) |
664 | { | |
665 | void __iomem *p; | |
04bf7e74 WP |
666 | unsigned int bar = 0; |
667 | ||
668 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | |
669 | moan_device("no memory in bar", dev); | |
670 | return 0; | |
671 | } | |
672 | ||
398a9db6 | 673 | p = pci_ioremap_bar(dev, bar); |
04bf7e74 WP |
674 | if (p == NULL) |
675 | return -ENOMEM; | |
676 | ||
677 | /* Enable CPU Interrupt */ | |
678 | writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, | |
679 | p + NI8420_INT_ENABLE_REG); | |
680 | ||
681 | iounmap(p); | |
682 | return 0; | |
683 | } | |
684 | ||
46a0fac9 SB |
685 | #define MITE_IOWBSR1_WSIZE 0xa |
686 | #define MITE_IOWBSR1_WIN_OFFSET 0x800 | |
687 | #define MITE_IOWBSR1_WENAB (1 << 7) | |
688 | #define MITE_LCIMR1_IO_IE_0 (1 << 24) | |
689 | #define MITE_LCIMR2_SET_CPU_IE (1 << 31) | |
690 | #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe | |
691 | ||
692 | static int pci_ni8430_init(struct pci_dev *dev) | |
693 | { | |
694 | void __iomem *p; | |
398a9db6 | 695 | struct pci_bus_region region; |
46a0fac9 SB |
696 | u32 device_window; |
697 | unsigned int bar = 0; | |
698 | ||
699 | if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { | |
700 | moan_device("no memory in bar", dev); | |
701 | return 0; | |
702 | } | |
703 | ||
398a9db6 | 704 | p = pci_ioremap_bar(dev, bar); |
46a0fac9 SB |
705 | if (p == NULL) |
706 | return -ENOMEM; | |
707 | ||
398a9db6 AS |
708 | /* |
709 | * Set device window address and size in BAR0, while acknowledging that | |
710 | * the resource structure may contain a translated address that differs | |
711 | * from the address the device responds to. | |
712 | */ | |
713 | pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); | |
714 | device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) | |
6d7c157f | 715 | | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; |
46a0fac9 SB |
716 | writel(device_window, p + MITE_IOWBSR1); |
717 | ||
718 | /* Set window access to go to RAMSEL IO address space */ | |
719 | writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), | |
720 | p + MITE_IOWCR1); | |
721 | ||
722 | /* Enable IO Bus Interrupt 0 */ | |
723 | writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); | |
724 | ||
725 | /* Enable CPU Interrupt */ | |
726 | writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); | |
727 | ||
728 | iounmap(p); | |
729 | return 0; | |
730 | } | |
731 | ||
732 | /* UART Port Control Register */ | |
733 | #define NI8430_PORTCON 0x0f | |
734 | #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) | |
735 | ||
736 | static int | |
bf538fe4 AC |
737 | pci_ni8430_setup(struct serial_private *priv, |
738 | const struct pciserial_board *board, | |
2655a2c7 | 739 | struct uart_8250_port *port, int idx) |
46a0fac9 | 740 | { |
398a9db6 | 741 | struct pci_dev *dev = priv->dev; |
46a0fac9 | 742 | void __iomem *p; |
46a0fac9 SB |
743 | unsigned int bar, offset = board->first_offset; |
744 | ||
745 | if (idx >= board->num_ports) | |
746 | return 1; | |
747 | ||
748 | bar = FL_GET_BASE(board->flags); | |
749 | offset += idx * board->uart_offset; | |
750 | ||
398a9db6 | 751 | p = pci_ioremap_bar(dev, bar); |
5d14bba9 AS |
752 | if (!p) |
753 | return -ENOMEM; | |
46a0fac9 | 754 | |
7c9d440e | 755 | /* enable the transceiver */ |
46a0fac9 SB |
756 | writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, |
757 | p + offset + NI8430_PORTCON); | |
758 | ||
759 | iounmap(p); | |
760 | ||
761 | return setup_port(priv, port, bar, offset, board->reg_shift); | |
762 | } | |
763 | ||
7808edcd NG |
764 | static int pci_netmos_9900_setup(struct serial_private *priv, |
765 | const struct pciserial_board *board, | |
2655a2c7 | 766 | struct uart_8250_port *port, int idx) |
7808edcd NG |
767 | { |
768 | unsigned int bar; | |
769 | ||
333c085e DES |
770 | if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && |
771 | (priv->dev->subsystem_device & 0xff00) == 0x3000) { | |
7808edcd NG |
772 | /* netmos apparently orders BARs by datasheet layout, so serial |
773 | * ports get BARs 0 and 3 (or 1 and 4 for memmapped) | |
774 | */ | |
775 | bar = 3 * idx; | |
776 | ||
777 | return setup_port(priv, port, bar, 0, board->reg_shift); | |
778 | } else { | |
779 | return pci_default_setup(priv, board, port, idx); | |
780 | } | |
781 | } | |
782 | ||
783 | /* the 99xx series comes with a range of device IDs and a variety | |
784 | * of capabilities: | |
785 | * | |
786 | * 9900 has varying capabilities and can cascade to sub-controllers | |
787 | * (cascading should be purely internal) | |
788 | * 9904 is hardwired with 4 serial ports | |
789 | * 9912 and 9922 are hardwired with 2 serial ports | |
790 | */ | |
791 | static int pci_netmos_9900_numports(struct pci_dev *dev) | |
792 | { | |
793 | unsigned int c = dev->class; | |
794 | unsigned int pi; | |
795 | unsigned short sub_serports; | |
796 | ||
149a44cc | 797 | pi = c & 0xff; |
7808edcd | 798 | |
c2f5fde1 | 799 | if (pi == 2) |
7808edcd | 800 | return 1; |
c2f5fde1 AW |
801 | |
802 | if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { | |
7808edcd NG |
803 | /* two possibilities: 0x30ps encodes number of parallel and |
804 | * serial ports, or 0x1000 indicates *something*. This is not | |
805 | * immediately obvious, since the 2s1p+4s configuration seems | |
806 | * to offer all functionality on functions 0..2, while still | |
807 | * advertising the same function 3 as the 4s+2s1p config. | |
808 | */ | |
809 | sub_serports = dev->subsystem_device & 0xf; | |
c2f5fde1 | 810 | if (sub_serports > 0) |
7808edcd | 811 | return sub_serports; |
c2f5fde1 AW |
812 | |
813 | dev_err(&dev->dev, | |
814 | "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); | |
815 | return 0; | |
7808edcd NG |
816 | } |
817 | ||
818 | moan_device("unknown NetMos/Mostech program interface", dev); | |
819 | return 0; | |
820 | } | |
46a0fac9 | 821 | |
61a116ef | 822 | static int pci_netmos_init(struct pci_dev *dev) |
1da177e4 LT |
823 | { |
824 | /* subdevice 0x00PS means <P> parallel, <S> serial */ | |
825 | unsigned int num_serial = dev->subsystem_device & 0xf; | |
826 | ||
ac6ec5b1 IS |
827 | if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || |
828 | (dev->device == PCI_DEVICE_ID_NETMOS_9865)) | |
c4285b47 | 829 | return 0; |
7808edcd | 830 | |
25cf9bc1 JS |
831 | if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && |
832 | dev->subsystem_device == 0x0299) | |
833 | return 0; | |
834 | ||
7808edcd | 835 | switch (dev->device) { /* FALLTHROUGH on all */ |
b3d67936 AW |
836 | case PCI_DEVICE_ID_NETMOS_9904: |
837 | case PCI_DEVICE_ID_NETMOS_9912: | |
838 | case PCI_DEVICE_ID_NETMOS_9922: | |
839 | case PCI_DEVICE_ID_NETMOS_9900: | |
840 | num_serial = pci_netmos_9900_numports(dev); | |
841 | break; | |
842 | ||
843 | default: | |
844 | break; | |
7808edcd NG |
845 | } |
846 | ||
829b0000 AW |
847 | if (num_serial == 0) { |
848 | moan_device("unknown NetMos/Mostech device", dev); | |
1da177e4 | 849 | return -ENODEV; |
829b0000 | 850 | } |
7808edcd | 851 | |
1da177e4 LT |
852 | return num_serial; |
853 | } | |
854 | ||
84f8c6fc | 855 | /* |
84f8c6fc NV |
856 | * These chips are available with optionally one parallel port and up to |
857 | * two serial ports. Unfortunately they all have the same product id. | |
858 | * | |
859 | * Basic configuration is done over a region of 32 I/O ports. The base | |
860 | * ioport is called INTA or INTC, depending on docs/other drivers. | |
861 | * | |
862 | * The region of the 32 I/O ports is configured in POSIO0R... | |
863 | */ | |
864 | ||
865 | /* registers */ | |
866 | #define ITE_887x_MISCR 0x9c | |
867 | #define ITE_887x_INTCBAR 0x78 | |
868 | #define ITE_887x_UARTBAR 0x7c | |
869 | #define ITE_887x_PS0BAR 0x10 | |
870 | #define ITE_887x_POSIO0 0x60 | |
871 | ||
872 | /* I/O space size */ | |
873 | #define ITE_887x_IOSIZE 32 | |
874 | /* I/O space size (bits 26-24; 8 bytes = 011b) */ | |
875 | #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) | |
876 | /* I/O space size (bits 26-24; 32 bytes = 101b) */ | |
877 | #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) | |
878 | /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ | |
879 | #define ITE_887x_POSIO_SPEED (3 << 29) | |
880 | /* enable IO_Space bit */ | |
881 | #define ITE_887x_POSIO_ENABLE (1 << 31) | |
882 | ||
f79abb82 | 883 | static int pci_ite887x_init(struct pci_dev *dev) |
84f8c6fc NV |
884 | { |
885 | /* inta_addr are the configuration addresses of the ITE */ | |
886 | static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, | |
887 | 0x200, 0x280, 0 }; | |
888 | int ret, i, type; | |
889 | struct resource *iobase = NULL; | |
890 | u32 miscr, uartbar, ioport; | |
891 | ||
892 | /* search for the base-ioport */ | |
893 | i = 0; | |
894 | while (inta_addr[i] && iobase == NULL) { | |
895 | iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, | |
896 | "ite887x"); | |
897 | if (iobase != NULL) { | |
898 | /* write POSIO0R - speed | size | ioport */ | |
899 | pci_write_config_dword(dev, ITE_887x_POSIO0, | |
900 | ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | | |
901 | ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); | |
902 | /* write INTCBAR - ioport */ | |
5756ee99 AC |
903 | pci_write_config_dword(dev, ITE_887x_INTCBAR, |
904 | inta_addr[i]); | |
84f8c6fc NV |
905 | ret = inb(inta_addr[i]); |
906 | if (ret != 0xff) { | |
907 | /* ioport connected */ | |
908 | break; | |
909 | } | |
910 | release_region(iobase->start, ITE_887x_IOSIZE); | |
911 | iobase = NULL; | |
912 | } | |
913 | i++; | |
914 | } | |
915 | ||
916 | if (!inta_addr[i]) { | |
af8c5b8d | 917 | dev_err(&dev->dev, "ite887x: could not find iobase\n"); |
84f8c6fc NV |
918 | return -ENODEV; |
919 | } | |
920 | ||
921 | /* start of undocumented type checking (see parport_pc.c) */ | |
922 | type = inb(iobase->start + 0x18) & 0x0f; | |
923 | ||
924 | switch (type) { | |
925 | case 0x2: /* ITE8871 (1P) */ | |
926 | case 0xa: /* ITE8875 (1P) */ | |
927 | ret = 0; | |
928 | break; | |
929 | case 0xe: /* ITE8872 (2S1P) */ | |
930 | ret = 2; | |
931 | break; | |
932 | case 0x6: /* ITE8873 (1S) */ | |
933 | ret = 1; | |
934 | break; | |
935 | case 0x8: /* ITE8874 (2S) */ | |
936 | ret = 2; | |
937 | break; | |
938 | default: | |
939 | moan_device("Unknown ITE887x", dev); | |
940 | ret = -ENODEV; | |
941 | } | |
942 | ||
943 | /* configure all serial ports */ | |
944 | for (i = 0; i < ret; i++) { | |
945 | /* read the I/O port from the device */ | |
946 | pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), | |
947 | &ioport); | |
948 | ioport &= 0x0000FF00; /* the actual base address */ | |
949 | pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), | |
950 | ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | | |
951 | ITE_887x_POSIO_IOSIZE_8 | ioport); | |
952 | ||
953 | /* write the ioport to the UARTBAR */ | |
954 | pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); | |
955 | uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ | |
956 | uartbar |= (ioport << (16 * i)); /* set the ioport */ | |
957 | pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); | |
958 | ||
959 | /* get current config */ | |
960 | pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); | |
961 | /* disable interrupts (UARTx_Routing[3:0]) */ | |
962 | miscr &= ~(0xf << (12 - 4 * i)); | |
963 | /* activate the UART (UARTx_En) */ | |
964 | miscr |= 1 << (23 - i); | |
965 | /* write new config with activated UART */ | |
966 | pci_write_config_dword(dev, ITE_887x_MISCR, miscr); | |
967 | } | |
968 | ||
969 | if (ret <= 0) { | |
970 | /* the device has no UARTs if we get here */ | |
971 | release_region(iobase->start, ITE_887x_IOSIZE); | |
972 | } | |
973 | ||
974 | return ret; | |
975 | } | |
976 | ||
ae8d8a14 | 977 | static void pci_ite887x_exit(struct pci_dev *dev) |
84f8c6fc NV |
978 | { |
979 | u32 ioport; | |
980 | /* the ioport is bit 0-15 in POSIO0R */ | |
981 | pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); | |
982 | ioport &= 0xffff; | |
983 | release_region(ioport, ITE_887x_IOSIZE); | |
984 | } | |
985 | ||
1bc8cde4 MS |
986 | /* |
987 | * EndRun Technologies. | |
988 | * Determine the number of ports available on the device. | |
989 | */ | |
990 | #define PCI_VENDOR_ID_ENDRUN 0x7401 | |
991 | #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 | |
992 | ||
993 | static int pci_endrun_init(struct pci_dev *dev) | |
994 | { | |
995 | u8 __iomem *p; | |
996 | unsigned long deviceID; | |
997 | unsigned int number_uarts = 0; | |
998 | ||
999 | /* EndRun device is all 0xexxx */ | |
1000 | if (dev->vendor == PCI_VENDOR_ID_ENDRUN && | |
1001 | (dev->device & 0xf000) != 0xe000) | |
1002 | return 0; | |
1003 | ||
1004 | p = pci_iomap(dev, 0, 5); | |
1005 | if (p == NULL) | |
1006 | return -ENOMEM; | |
1007 | ||
1008 | deviceID = ioread32(p); | |
1009 | /* EndRun device */ | |
1010 | if (deviceID == 0x07000200) { | |
1011 | number_uarts = ioread8(p + 4); | |
1012 | dev_dbg(&dev->dev, | |
1013 | "%d ports detected on EndRun PCI Express device\n", | |
1014 | number_uarts); | |
1015 | } | |
1016 | pci_iounmap(dev, p); | |
1017 | return number_uarts; | |
1018 | } | |
1019 | ||
9f2a036a RK |
1020 | /* |
1021 | * Oxford Semiconductor Inc. | |
1022 | * Check that device is part of the Tornado range of devices, then determine | |
1023 | * the number of ports available on the device. | |
1024 | */ | |
1025 | static int pci_oxsemi_tornado_init(struct pci_dev *dev) | |
1026 | { | |
1027 | u8 __iomem *p; | |
1028 | unsigned long deviceID; | |
1029 | unsigned int number_uarts = 0; | |
1030 | ||
1031 | /* OxSemi Tornado devices are all 0xCxxx */ | |
1032 | if (dev->vendor == PCI_VENDOR_ID_OXSEMI && | |
1033 | (dev->device & 0xF000) != 0xC000) | |
1034 | return 0; | |
1035 | ||
1036 | p = pci_iomap(dev, 0, 5); | |
1037 | if (p == NULL) | |
1038 | return -ENOMEM; | |
1039 | ||
1040 | deviceID = ioread32(p); | |
1041 | /* Tornado device */ | |
1042 | if (deviceID == 0x07000200) { | |
1043 | number_uarts = ioread8(p + 4); | |
af8c5b8d | 1044 | dev_dbg(&dev->dev, |
9f2a036a | 1045 | "%d ports detected on Oxford PCI Express device\n", |
af8c5b8d | 1046 | number_uarts); |
9f2a036a RK |
1047 | } |
1048 | pci_iounmap(dev, p); | |
1049 | return number_uarts; | |
1050 | } | |
1051 | ||
eb26dfe8 AC |
1052 | static int pci_asix_setup(struct serial_private *priv, |
1053 | const struct pciserial_board *board, | |
1054 | struct uart_8250_port *port, int idx) | |
1055 | { | |
1056 | port->bugs |= UART_BUG_PARITY; | |
1057 | return pci_default_setup(priv, board, port, idx); | |
1058 | } | |
1059 | ||
55c7c0fd AC |
1060 | /* Quatech devices have their own extra interface features */ |
1061 | ||
1062 | struct quatech_feature { | |
1063 | u16 devid; | |
1064 | bool amcc; | |
1065 | }; | |
1066 | ||
1067 | #define QPCR_TEST_FOR1 0x3F | |
1068 | #define QPCR_TEST_GET1 0x00 | |
1069 | #define QPCR_TEST_FOR2 0x40 | |
1070 | #define QPCR_TEST_GET2 0x40 | |
1071 | #define QPCR_TEST_FOR3 0x80 | |
1072 | #define QPCR_TEST_GET3 0x40 | |
1073 | #define QPCR_TEST_FOR4 0xC0 | |
1074 | #define QPCR_TEST_GET4 0x80 | |
1075 | ||
1076 | #define QOPR_CLOCK_X1 0x0000 | |
1077 | #define QOPR_CLOCK_X2 0x0001 | |
1078 | #define QOPR_CLOCK_X4 0x0002 | |
1079 | #define QOPR_CLOCK_X8 0x0003 | |
1080 | #define QOPR_CLOCK_RATE_MASK 0x0003 | |
1081 | ||
1082 | ||
1083 | static struct quatech_feature quatech_cards[] = { | |
1084 | { PCI_DEVICE_ID_QUATECH_QSC100, 1 }, | |
1085 | { PCI_DEVICE_ID_QUATECH_DSC100, 1 }, | |
1086 | { PCI_DEVICE_ID_QUATECH_DSC100E, 0 }, | |
1087 | { PCI_DEVICE_ID_QUATECH_DSC200, 1 }, | |
1088 | { PCI_DEVICE_ID_QUATECH_DSC200E, 0 }, | |
1089 | { PCI_DEVICE_ID_QUATECH_ESC100D, 1 }, | |
1090 | { PCI_DEVICE_ID_QUATECH_ESC100M, 1 }, | |
1091 | { PCI_DEVICE_ID_QUATECH_QSCP100, 1 }, | |
1092 | { PCI_DEVICE_ID_QUATECH_DSCP100, 1 }, | |
1093 | { PCI_DEVICE_ID_QUATECH_QSCP200, 1 }, | |
1094 | { PCI_DEVICE_ID_QUATECH_DSCP200, 1 }, | |
1095 | { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 }, | |
1096 | { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 }, | |
1097 | { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 }, | |
1098 | { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 }, | |
1099 | { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 }, | |
1100 | { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 }, | |
1101 | { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 }, | |
1102 | { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 }, | |
1103 | { 0, } | |
1104 | }; | |
1105 | ||
1106 | static int pci_quatech_amcc(u16 devid) | |
1107 | { | |
1108 | struct quatech_feature *qf = &quatech_cards[0]; | |
1109 | while (qf->devid) { | |
1110 | if (qf->devid == devid) | |
1111 | return qf->amcc; | |
1112 | qf++; | |
1113 | } | |
1114 | pr_err("quatech: unknown port type '0x%04X'.\n", devid); | |
1115 | return 0; | |
1116 | }; | |
1117 | ||
1118 | static int pci_quatech_rqopr(struct uart_8250_port *port) | |
1119 | { | |
1120 | unsigned long base = port->port.iobase; | |
1121 | u8 LCR, val; | |
1122 | ||
1123 | LCR = inb(base + UART_LCR); | |
1124 | outb(0xBF, base + UART_LCR); | |
1125 | val = inb(base + UART_SCR); | |
1126 | outb(LCR, base + UART_LCR); | |
1127 | return val; | |
1128 | } | |
1129 | ||
1130 | static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) | |
1131 | { | |
1132 | unsigned long base = port->port.iobase; | |
17b2720b | 1133 | u8 LCR; |
55c7c0fd AC |
1134 | |
1135 | LCR = inb(base + UART_LCR); | |
1136 | outb(0xBF, base + UART_LCR); | |
17b2720b | 1137 | inb(base + UART_SCR); |
55c7c0fd AC |
1138 | outb(qopr, base + UART_SCR); |
1139 | outb(LCR, base + UART_LCR); | |
1140 | } | |
1141 | ||
1142 | static int pci_quatech_rqmcr(struct uart_8250_port *port) | |
1143 | { | |
1144 | unsigned long base = port->port.iobase; | |
1145 | u8 LCR, val, qmcr; | |
1146 | ||
1147 | LCR = inb(base + UART_LCR); | |
1148 | outb(0xBF, base + UART_LCR); | |
1149 | val = inb(base + UART_SCR); | |
1150 | outb(val | 0x10, base + UART_SCR); | |
1151 | qmcr = inb(base + UART_MCR); | |
1152 | outb(val, base + UART_SCR); | |
1153 | outb(LCR, base + UART_LCR); | |
1154 | ||
1155 | return qmcr; | |
1156 | } | |
1157 | ||
1158 | static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) | |
1159 | { | |
1160 | unsigned long base = port->port.iobase; | |
1161 | u8 LCR, val; | |
1162 | ||
1163 | LCR = inb(base + UART_LCR); | |
1164 | outb(0xBF, base + UART_LCR); | |
1165 | val = inb(base + UART_SCR); | |
1166 | outb(val | 0x10, base + UART_SCR); | |
1167 | outb(qmcr, base + UART_MCR); | |
1168 | outb(val, base + UART_SCR); | |
1169 | outb(LCR, base + UART_LCR); | |
1170 | } | |
1171 | ||
1172 | static int pci_quatech_has_qmcr(struct uart_8250_port *port) | |
1173 | { | |
1174 | unsigned long base = port->port.iobase; | |
1175 | u8 LCR, val; | |
1176 | ||
1177 | LCR = inb(base + UART_LCR); | |
1178 | outb(0xBF, base + UART_LCR); | |
1179 | val = inb(base + UART_SCR); | |
1180 | if (val & 0x20) { | |
1181 | outb(0x80, UART_LCR); | |
1182 | if (!(inb(UART_SCR) & 0x20)) { | |
1183 | outb(LCR, base + UART_LCR); | |
1184 | return 1; | |
1185 | } | |
1186 | } | |
1187 | return 0; | |
1188 | } | |
1189 | ||
1190 | static int pci_quatech_test(struct uart_8250_port *port) | |
1191 | { | |
1a33e342 AW |
1192 | u8 reg, qopr; |
1193 | ||
1194 | qopr = pci_quatech_rqopr(port); | |
55c7c0fd AC |
1195 | pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); |
1196 | reg = pci_quatech_rqopr(port) & 0xC0; | |
1197 | if (reg != QPCR_TEST_GET1) | |
1198 | return -EINVAL; | |
1199 | pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); | |
1200 | reg = pci_quatech_rqopr(port) & 0xC0; | |
1201 | if (reg != QPCR_TEST_GET2) | |
1202 | return -EINVAL; | |
1203 | pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); | |
1204 | reg = pci_quatech_rqopr(port) & 0xC0; | |
1205 | if (reg != QPCR_TEST_GET3) | |
1206 | return -EINVAL; | |
1207 | pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); | |
1208 | reg = pci_quatech_rqopr(port) & 0xC0; | |
1209 | if (reg != QPCR_TEST_GET4) | |
1210 | return -EINVAL; | |
1211 | ||
1212 | pci_quatech_wqopr(port, qopr); | |
1213 | return 0; | |
1214 | } | |
1215 | ||
1216 | static int pci_quatech_clock(struct uart_8250_port *port) | |
1217 | { | |
1218 | u8 qopr, reg, set; | |
1219 | unsigned long clock; | |
1220 | ||
1221 | if (pci_quatech_test(port) < 0) | |
1222 | return 1843200; | |
1223 | ||
1224 | qopr = pci_quatech_rqopr(port); | |
1225 | ||
1226 | pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); | |
1227 | reg = pci_quatech_rqopr(port); | |
1228 | if (reg & QOPR_CLOCK_X8) { | |
1229 | clock = 1843200; | |
1230 | goto out; | |
1231 | } | |
1232 | pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); | |
1233 | reg = pci_quatech_rqopr(port); | |
1234 | if (!(reg & QOPR_CLOCK_X8)) { | |
1235 | clock = 1843200; | |
1236 | goto out; | |
1237 | } | |
1238 | reg &= QOPR_CLOCK_X8; | |
1239 | if (reg == QOPR_CLOCK_X2) { | |
1240 | clock = 3685400; | |
1241 | set = QOPR_CLOCK_X2; | |
1242 | } else if (reg == QOPR_CLOCK_X4) { | |
1243 | clock = 7372800; | |
1244 | set = QOPR_CLOCK_X4; | |
1245 | } else if (reg == QOPR_CLOCK_X8) { | |
1246 | clock = 14745600; | |
1247 | set = QOPR_CLOCK_X8; | |
1248 | } else { | |
1249 | clock = 1843200; | |
1250 | set = QOPR_CLOCK_X1; | |
1251 | } | |
1252 | qopr &= ~QOPR_CLOCK_RATE_MASK; | |
1253 | qopr |= set; | |
1254 | ||
1255 | out: | |
1256 | pci_quatech_wqopr(port, qopr); | |
1257 | return clock; | |
1258 | } | |
1259 | ||
1260 | static int pci_quatech_rs422(struct uart_8250_port *port) | |
1261 | { | |
1262 | u8 qmcr; | |
1263 | int rs422 = 0; | |
1264 | ||
1265 | if (!pci_quatech_has_qmcr(port)) | |
1266 | return 0; | |
1267 | qmcr = pci_quatech_rqmcr(port); | |
1268 | pci_quatech_wqmcr(port, 0xFF); | |
1269 | if (pci_quatech_rqmcr(port)) | |
1270 | rs422 = 1; | |
1271 | pci_quatech_wqmcr(port, qmcr); | |
1272 | return rs422; | |
1273 | } | |
1274 | ||
1275 | static int pci_quatech_init(struct pci_dev *dev) | |
1276 | { | |
1277 | if (pci_quatech_amcc(dev->device)) { | |
1278 | unsigned long base = pci_resource_start(dev, 0); | |
1279 | if (base) { | |
1280 | u32 tmp; | |
1a33e342 | 1281 | |
9c5320f8 | 1282 | outl(inl(base + 0x38) | 0x00002000, base + 0x38); |
55c7c0fd AC |
1283 | tmp = inl(base + 0x3c); |
1284 | outl(tmp | 0x01000000, base + 0x3c); | |
9c5320f8 | 1285 | outl(tmp &= ~0x01000000, base + 0x3c); |
55c7c0fd AC |
1286 | } |
1287 | } | |
1288 | return 0; | |
1289 | } | |
1290 | ||
1291 | static int pci_quatech_setup(struct serial_private *priv, | |
1292 | const struct pciserial_board *board, | |
1293 | struct uart_8250_port *port, int idx) | |
1294 | { | |
1295 | /* Needed by pci_quatech calls below */ | |
1296 | port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); | |
1297 | /* Set up the clocking */ | |
1298 | port->port.uartclk = pci_quatech_clock(port); | |
1299 | /* For now just warn about RS422 */ | |
1300 | if (pci_quatech_rs422(port)) | |
1301 | pr_warn("quatech: software control of RS422 features not currently supported.\n"); | |
1302 | return pci_default_setup(priv, board, port, idx); | |
1303 | } | |
1304 | ||
d73dfc6a | 1305 | static void pci_quatech_exit(struct pci_dev *dev) |
55c7c0fd AC |
1306 | { |
1307 | } | |
1308 | ||
eb26dfe8 | 1309 | static int pci_default_setup(struct serial_private *priv, |
975a1a7d | 1310 | const struct pciserial_board *board, |
2655a2c7 | 1311 | struct uart_8250_port *port, int idx) |
1da177e4 LT |
1312 | { |
1313 | unsigned int bar, offset = board->first_offset, maxnr; | |
1314 | ||
1315 | bar = FL_GET_BASE(board->flags); | |
1316 | if (board->flags & FL_BASE_BARS) | |
1317 | bar += idx; | |
1318 | else | |
1319 | offset += idx * board->uart_offset; | |
1320 | ||
2427ddd8 GKH |
1321 | maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> |
1322 | (board->reg_shift + 3); | |
1da177e4 LT |
1323 | |
1324 | if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) | |
1325 | return 1; | |
5756ee99 | 1326 | |
70db3d91 | 1327 | return setup_port(priv, port, bar, offset, board->reg_shift); |
1da177e4 LT |
1328 | } |
1329 | ||
5c31ef91 AB |
1330 | static int pci_pericom_setup(struct serial_private *priv, |
1331 | const struct pciserial_board *board, | |
1332 | struct uart_8250_port *port, int idx) | |
1333 | { | |
1334 | unsigned int bar, offset = board->first_offset, maxnr; | |
1335 | ||
1336 | bar = FL_GET_BASE(board->flags); | |
1337 | if (board->flags & FL_BASE_BARS) | |
1338 | bar += idx; | |
1339 | else | |
1340 | offset += idx * board->uart_offset; | |
1341 | ||
1342 | if (idx==3) | |
1343 | offset = 0x38; | |
1344 | ||
1345 | maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> | |
1346 | (board->reg_shift + 3); | |
1347 | ||
1348 | if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) | |
1349 | return 1; | |
1350 | ||
1351 | return setup_port(priv, port, bar, offset, board->reg_shift); | |
1352 | } | |
1353 | ||
095e24b0 DB |
1354 | static int |
1355 | ce4100_serial_setup(struct serial_private *priv, | |
1356 | const struct pciserial_board *board, | |
2655a2c7 | 1357 | struct uart_8250_port *port, int idx) |
095e24b0 DB |
1358 | { |
1359 | int ret; | |
1360 | ||
08ec212c | 1361 | ret = setup_port(priv, port, idx, 0, board->reg_shift); |
2655a2c7 AC |
1362 | port->port.iotype = UPIO_MEM32; |
1363 | port->port.type = PORT_XSCALE; | |
1364 | port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); | |
1365 | port->port.regshift = 2; | |
095e24b0 DB |
1366 | |
1367 | return ret; | |
1368 | } | |
1369 | ||
d9a0fbfd AP |
1370 | static int |
1371 | pci_omegapci_setup(struct serial_private *priv, | |
1798ca13 | 1372 | const struct pciserial_board *board, |
2655a2c7 | 1373 | struct uart_8250_port *port, int idx) |
d9a0fbfd AP |
1374 | { |
1375 | return setup_port(priv, port, 2, idx * 8, 0); | |
1376 | } | |
1377 | ||
ebebd49a SH |
1378 | static int |
1379 | pci_brcm_trumanage_setup(struct serial_private *priv, | |
1380 | const struct pciserial_board *board, | |
1381 | struct uart_8250_port *port, int idx) | |
1382 | { | |
1383 | int ret = pci_default_setup(priv, board, port, idx); | |
1384 | ||
1385 | port->port.type = PORT_BRCM_TRUMANAGE; | |
1386 | port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); | |
1387 | return ret; | |
1388 | } | |
1389 | ||
fecf27a3 PH |
1390 | /* RTS will control by MCR if this bit is 0 */ |
1391 | #define FINTEK_RTS_CONTROL_BY_HW BIT(4) | |
1392 | /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ | |
1393 | #define FINTEK_RTS_INVERT BIT(5) | |
1394 | ||
1395 | /* We should do proper H/W transceiver setting before change to RS485 mode */ | |
1396 | static int pci_fintek_rs485_config(struct uart_port *port, | |
1397 | struct serial_rs485 *rs485) | |
1398 | { | |
30c6c352 | 1399 | struct pci_dev *pci_dev = to_pci_dev(port->dev); |
fecf27a3 PH |
1400 | u8 setting; |
1401 | u8 *index = (u8 *) port->private_data; | |
fecf27a3 PH |
1402 | |
1403 | pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); | |
1404 | ||
d3159455 PH |
1405 | if (!rs485) |
1406 | rs485 = &port->rs485; | |
1407 | else if (rs485->flags & SER_RS485_ENABLED) | |
fecf27a3 PH |
1408 | memset(rs485->padding, 0, sizeof(rs485->padding)); |
1409 | else | |
1410 | memset(rs485, 0, sizeof(*rs485)); | |
1411 | ||
1412 | /* F81504/508/512 not support RTS delay before or after send */ | |
1413 | rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND; | |
1414 | ||
1415 | if (rs485->flags & SER_RS485_ENABLED) { | |
1416 | /* Enable RTS H/W control mode */ | |
1417 | setting |= FINTEK_RTS_CONTROL_BY_HW; | |
1418 | ||
1419 | if (rs485->flags & SER_RS485_RTS_ON_SEND) { | |
1420 | /* RTS driving high on TX */ | |
1421 | setting &= ~FINTEK_RTS_INVERT; | |
1422 | } else { | |
1423 | /* RTS driving low on TX */ | |
1424 | setting |= FINTEK_RTS_INVERT; | |
1425 | } | |
1426 | ||
1427 | rs485->delay_rts_after_send = 0; | |
1428 | rs485->delay_rts_before_send = 0; | |
1429 | } else { | |
1430 | /* Disable RTS H/W control mode */ | |
1431 | setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); | |
1432 | } | |
1433 | ||
1434 | pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); | |
d3159455 PH |
1435 | |
1436 | if (rs485 != &port->rs485) | |
1437 | port->rs485 = *rs485; | |
1438 | ||
fecf27a3 PH |
1439 | return 0; |
1440 | } | |
1441 | ||
2c62a3c8 GKH |
1442 | static int pci_fintek_setup(struct serial_private *priv, |
1443 | const struct pciserial_board *board, | |
1444 | struct uart_8250_port *port, int idx) | |
1445 | { | |
1446 | struct pci_dev *pdev = priv->dev; | |
fecf27a3 | 1447 | u8 *data; |
2c62a3c8 | 1448 | u8 config_base; |
6a8bc239 PH |
1449 | u16 iobase; |
1450 | ||
1451 | config_base = 0x40 + 0x08 * idx; | |
1452 | ||
1453 | /* Get the io address from configuration space */ | |
1454 | pci_read_config_word(pdev, config_base + 4, &iobase); | |
1455 | ||
1456 | dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase); | |
1457 | ||
1458 | port->port.iotype = UPIO_PORT; | |
1459 | port->port.iobase = iobase; | |
fecf27a3 PH |
1460 | port->port.rs485_config = pci_fintek_rs485_config; |
1461 | ||
1462 | data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); | |
1463 | if (!data) | |
1464 | return -ENOMEM; | |
1465 | ||
1466 | /* preserve index in PCI configuration space */ | |
1467 | *data = idx; | |
1468 | port->port.private_data = data; | |
6a8bc239 PH |
1469 | |
1470 | return 0; | |
1471 | } | |
1472 | ||
1473 | static int pci_fintek_init(struct pci_dev *dev) | |
1474 | { | |
1475 | unsigned long iobase; | |
1476 | u32 max_port, i; | |
6def047c | 1477 | resource_size_t bar_data[3]; |
6a8bc239 | 1478 | u8 config_base; |
d3159455 PH |
1479 | struct serial_private *priv = pci_get_drvdata(dev); |
1480 | struct uart_8250_port *port; | |
2c62a3c8 | 1481 | |
6def047c JZHPH |
1482 | if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || |
1483 | !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || | |
1484 | !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) | |
1485 | return -ENODEV; | |
1486 | ||
6a8bc239 PH |
1487 | switch (dev->device) { |
1488 | case 0x1104: /* 4 ports */ | |
1489 | case 0x1108: /* 8 ports */ | |
1490 | max_port = dev->device & 0xff; | |
cb8ee9f0 | 1491 | break; |
6a8bc239 PH |
1492 | case 0x1112: /* 12 ports */ |
1493 | max_port = 12; | |
cb8ee9f0 | 1494 | break; |
2c62a3c8 | 1495 | default: |
2c62a3c8 GKH |
1496 | return -EINVAL; |
1497 | } | |
1498 | ||
cb8ee9f0 | 1499 | /* Get the io address dispatch from the BIOS */ |
6def047c JZHPH |
1500 | bar_data[0] = pci_resource_start(dev, 5); |
1501 | bar_data[1] = pci_resource_start(dev, 4); | |
1502 | bar_data[2] = pci_resource_start(dev, 3); | |
cb8ee9f0 | 1503 | |
6a8bc239 PH |
1504 | for (i = 0; i < max_port; ++i) { |
1505 | /* UART0 configuration offset start from 0x40 */ | |
1506 | config_base = 0x40 + 0x08 * i; | |
2c62a3c8 | 1507 | |
6a8bc239 PH |
1508 | /* Calculate Real IO Port */ |
1509 | iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; | |
2c62a3c8 | 1510 | |
6a8bc239 PH |
1511 | /* Enable UART I/O port */ |
1512 | pci_write_config_byte(dev, config_base + 0x00, 0x01); | |
2c62a3c8 | 1513 | |
6a8bc239 PH |
1514 | /* Select 128-byte FIFO and 8x FIFO threshold */ |
1515 | pci_write_config_byte(dev, config_base + 0x01, 0x33); | |
2c62a3c8 | 1516 | |
6a8bc239 PH |
1517 | /* LSB UART */ |
1518 | pci_write_config_byte(dev, config_base + 0x04, | |
1519 | (u8)(iobase & 0xff)); | |
2c62a3c8 | 1520 | |
6a8bc239 PH |
1521 | /* MSB UART */ |
1522 | pci_write_config_byte(dev, config_base + 0x05, | |
1523 | (u8)((iobase & 0xff00) >> 8)); | |
2c62a3c8 | 1524 | |
6a8bc239 | 1525 | pci_write_config_byte(dev, config_base + 0x06, dev->irq); |
fecf27a3 | 1526 | |
d3159455 PH |
1527 | if (priv) { |
1528 | /* re-apply RS232/485 mode when | |
1529 | * pciserial_resume_ports() | |
1530 | */ | |
1531 | port = serial8250_get_port(priv->line[i]); | |
1532 | pci_fintek_rs485_config(&port->port, NULL); | |
1533 | } else { | |
1534 | /* First init without port data | |
1535 | * force init to RS232 Mode | |
1536 | */ | |
1537 | pci_write_config_byte(dev, config_base + 0x07, 0x01); | |
1538 | } | |
6a8bc239 | 1539 | } |
2c62a3c8 | 1540 | |
6a8bc239 | 1541 | return max_port; |
2c62a3c8 GKH |
1542 | } |
1543 | ||
b6adea33 MCC |
1544 | static int skip_tx_en_setup(struct serial_private *priv, |
1545 | const struct pciserial_board *board, | |
2655a2c7 | 1546 | struct uart_8250_port *port, int idx) |
b6adea33 | 1547 | { |
c7ac15ce | 1548 | port->port.quirks |= UPQ_NO_TXEN_TEST; |
af8c5b8d GKH |
1549 | dev_dbg(&priv->dev->dev, |
1550 | "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", | |
1551 | priv->dev->vendor, priv->dev->device, | |
1552 | priv->dev->subsystem_vendor, priv->dev->subsystem_device); | |
b6adea33 MCC |
1553 | |
1554 | return pci_default_setup(priv, board, port, idx); | |
1555 | } | |
1556 | ||
0ad372b9 SM |
1557 | static void kt_handle_break(struct uart_port *p) |
1558 | { | |
b1261c86 | 1559 | struct uart_8250_port *up = up_to_u8250p(p); |
0ad372b9 SM |
1560 | /* |
1561 | * On receipt of a BI, serial device in Intel ME (Intel | |
1562 | * management engine) needs to have its fifos cleared for sane | |
1563 | * SOL (Serial Over Lan) output. | |
1564 | */ | |
1565 | serial8250_clear_and_reinit_fifos(up); | |
1566 | } | |
1567 | ||
1568 | static unsigned int kt_serial_in(struct uart_port *p, int offset) | |
1569 | { | |
b1261c86 | 1570 | struct uart_8250_port *up = up_to_u8250p(p); |
0ad372b9 SM |
1571 | unsigned int val; |
1572 | ||
1573 | /* | |
1574 | * When the Intel ME (management engine) gets reset its serial | |
1575 | * port registers could return 0 momentarily. Functions like | |
1576 | * serial8250_console_write, read and save the IER, perform | |
1577 | * some operation and then restore it. In order to avoid | |
1578 | * setting IER register inadvertently to 0, if the value read | |
1579 | * is 0, double check with ier value in uart_8250_port and use | |
1580 | * that instead. up->ier should be the same value as what is | |
1581 | * currently configured. | |
1582 | */ | |
1583 | val = inb(p->iobase + offset); | |
1584 | if (offset == UART_IER) { | |
1585 | if (val == 0) | |
1586 | val = up->ier; | |
1587 | } | |
1588 | return val; | |
1589 | } | |
1590 | ||
bc02d15a DW |
1591 | static int kt_serial_setup(struct serial_private *priv, |
1592 | const struct pciserial_board *board, | |
2655a2c7 | 1593 | struct uart_8250_port *port, int idx) |
bc02d15a | 1594 | { |
2655a2c7 AC |
1595 | port->port.flags |= UPF_BUG_THRE; |
1596 | port->port.serial_in = kt_serial_in; | |
1597 | port->port.handle_break = kt_handle_break; | |
bc02d15a DW |
1598 | return skip_tx_en_setup(priv, board, port, idx); |
1599 | } | |
1600 | ||
eb7073db TM |
1601 | static int pci_eg20t_init(struct pci_dev *dev) |
1602 | { | |
1603 | #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) | |
1604 | return -ENODEV; | |
1605 | #else | |
1606 | return 0; | |
1607 | #endif | |
1608 | } | |
1609 | ||
6971c635 GA |
1610 | static int |
1611 | pci_wch_ch353_setup(struct serial_private *priv, | |
6d7c157f AW |
1612 | const struct pciserial_board *board, |
1613 | struct uart_8250_port *port, int idx) | |
6971c635 GA |
1614 | { |
1615 | port->port.flags |= UPF_FIXED_TYPE; | |
1616 | port->port.type = PORT_16550A; | |
06315348 SH |
1617 | return pci_default_setup(priv, board, port, idx); |
1618 | } | |
1619 | ||
55c368cb AP |
1620 | static int |
1621 | pci_wch_ch355_setup(struct serial_private *priv, | |
1622 | const struct pciserial_board *board, | |
1623 | struct uart_8250_port *port, int idx) | |
1624 | { | |
1625 | port->port.flags |= UPF_FIXED_TYPE; | |
1626 | port->port.type = PORT_16550A; | |
1627 | return pci_default_setup(priv, board, port, idx); | |
1628 | } | |
1629 | ||
2fdd8c8c | 1630 | static int |
72a3c0e4 | 1631 | pci_wch_ch38x_setup(struct serial_private *priv, |
6d7c157f AW |
1632 | const struct pciserial_board *board, |
1633 | struct uart_8250_port *port, int idx) | |
2fdd8c8c SP |
1634 | { |
1635 | port->port.flags |= UPF_FIXED_TYPE; | |
1636 | port->port.type = PORT_16850; | |
1637 | return pci_default_setup(priv, board, port, idx); | |
1638 | } | |
1639 | ||
1da177e4 LT |
1640 | #define PCI_VENDOR_ID_SBSMODULARIO 0x124B |
1641 | #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B | |
1642 | #define PCI_DEVICE_ID_OCTPRO 0x0001 | |
1643 | #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 | |
1644 | #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 | |
1645 | #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 | |
1646 | #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 | |
26e8220a FL |
1647 | #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 |
1648 | #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 | |
78d70d48 | 1649 | #define PCI_VENDOR_ID_ADVANTECH 0x13fe |
095e24b0 | 1650 | #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 |
78d70d48 | 1651 | #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 |
0c6d774c TW |
1652 | #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 |
1653 | #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 | |
66169ad1 YY |
1654 | #define PCI_DEVICE_ID_TITAN_200I 0x8028 |
1655 | #define PCI_DEVICE_ID_TITAN_400I 0x8048 | |
1656 | #define PCI_DEVICE_ID_TITAN_800I 0x8088 | |
1657 | #define PCI_DEVICE_ID_TITAN_800EH 0xA007 | |
1658 | #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 | |
1659 | #define PCI_DEVICE_ID_TITAN_400EH 0xA009 | |
1660 | #define PCI_DEVICE_ID_TITAN_100E 0xA010 | |
1661 | #define PCI_DEVICE_ID_TITAN_200E 0xA012 | |
1662 | #define PCI_DEVICE_ID_TITAN_400E 0xA013 | |
1663 | #define PCI_DEVICE_ID_TITAN_800E 0xA014 | |
1664 | #define PCI_DEVICE_ID_TITAN_200EI 0xA016 | |
1665 | #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 | |
48c0247d | 1666 | #define PCI_DEVICE_ID_TITAN_200V3 0xA306 |
1e9deb11 YY |
1667 | #define PCI_DEVICE_ID_TITAN_400V3 0xA310 |
1668 | #define PCI_DEVICE_ID_TITAN_410V3 0xA312 | |
1669 | #define PCI_DEVICE_ID_TITAN_800V3 0xA314 | |
1670 | #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 | |
e847003f | 1671 | #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 |
aa273ae5 | 1672 | #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 |
d9a0fbfd | 1673 | #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 |
bc02d15a | 1674 | #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d |
27788c5f | 1675 | #define PCI_VENDOR_ID_WCH 0x4348 |
8b5c913f | 1676 | #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 |
27788c5f AC |
1677 | #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 |
1678 | #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 | |
feb58142 | 1679 | #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 |
27788c5f | 1680 | #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 |
55c368cb | 1681 | #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 |
6683549e AC |
1682 | #define PCI_VENDOR_ID_AGESTAR 0x5372 |
1683 | #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 | |
eb26dfe8 | 1684 | #define PCI_VENDOR_ID_ASIX 0x9710 |
ebebd49a | 1685 | #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a |
57c1f0e9 | 1686 | #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e |
14faa8cc | 1687 | |
abd7baca SC |
1688 | #define PCI_VENDOR_ID_SUNIX 0x1fd4 |
1689 | #define PCI_DEVICE_ID_SUNIX_1999 0x1999 | |
1690 | ||
2fdd8c8c SP |
1691 | #define PCIE_VENDOR_ID_WCH 0x1c00 |
1692 | #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 | |
72a3c0e4 | 1693 | #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 |
7dde5578 | 1694 | #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 |
1da177e4 | 1695 | |
89c043a6 AL |
1696 | #define PCI_VENDOR_ID_PERICOM 0x12D8 |
1697 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951 | |
1698 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952 | |
1699 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954 | |
1700 | #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958 | |
1701 | ||
c8d19242 JD |
1702 | #define PCI_VENDOR_ID_ACCESIO 0x494f |
1703 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051 | |
1704 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053 | |
1705 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C | |
1706 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E | |
1707 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091 | |
1708 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093 | |
1709 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099 | |
1710 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B | |
1711 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1 | |
1712 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3 | |
1713 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA | |
1714 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC | |
1715 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108 | |
1716 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110 | |
1717 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111 | |
1718 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118 | |
1719 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119 | |
1720 | #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152 | |
1721 | #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A | |
1722 | #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190 | |
1723 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191 | |
1724 | #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198 | |
1725 | #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199 | |
1726 | #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0 | |
1727 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A | |
1728 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B | |
1729 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A | |
1730 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B | |
1731 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098 | |
1732 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9 | |
1733 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9 | |
1734 | #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9 | |
1735 | #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8 | |
1736 | ||
1737 | ||
1738 | ||
b76c5a07 CB |
1739 | /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ |
1740 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 | |
d13402a4 | 1741 | #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 |
b76c5a07 | 1742 | |
1da177e4 LT |
1743 | /* |
1744 | * Master list of serial port init/setup/exit quirks. | |
1745 | * This does not describe the general nature of the port. | |
1746 | * (ie, baud base, number and location of ports, etc) | |
1747 | * | |
1748 | * This list is ordered alphabetically by vendor then device. | |
1749 | * Specific entries must come before more generic entries. | |
1750 | */ | |
7a63ce5a | 1751 | static struct pci_serial_quirk pci_serial_quirks[] __refdata = { |
02c9b5cf KJ |
1752 | /* |
1753 | * ADDI-DATA GmbH communication cards <info@addi-data.com> | |
1754 | */ | |
1755 | { | |
086231f7 | 1756 | .vendor = PCI_VENDOR_ID_AMCC, |
57c1f0e9 | 1757 | .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, |
02c9b5cf KJ |
1758 | .subvendor = PCI_ANY_ID, |
1759 | .subdevice = PCI_ANY_ID, | |
1760 | .setup = addidata_apci7800_setup, | |
1761 | }, | |
1da177e4 | 1762 | /* |
61a116ef | 1763 | * AFAVLAB cards - these may be called via parport_serial |
1da177e4 LT |
1764 | * It is not clear whether this applies to all products. |
1765 | */ | |
1766 | { | |
1767 | .vendor = PCI_VENDOR_ID_AFAVLAB, | |
1768 | .device = PCI_ANY_ID, | |
1769 | .subvendor = PCI_ANY_ID, | |
1770 | .subdevice = PCI_ANY_ID, | |
1771 | .setup = afavlab_setup, | |
1772 | }, | |
1773 | /* | |
1774 | * HP Diva | |
1775 | */ | |
1776 | { | |
1777 | .vendor = PCI_VENDOR_ID_HP, | |
1778 | .device = PCI_DEVICE_ID_HP_DIVA, | |
1779 | .subvendor = PCI_ANY_ID, | |
1780 | .subdevice = PCI_ANY_ID, | |
1781 | .init = pci_hp_diva_init, | |
1782 | .setup = pci_hp_diva_setup, | |
1783 | }, | |
1784 | /* | |
1785 | * Intel | |
1786 | */ | |
1787 | { | |
1788 | .vendor = PCI_VENDOR_ID_INTEL, | |
1789 | .device = PCI_DEVICE_ID_INTEL_80960_RP, | |
1790 | .subvendor = 0xe4bf, | |
1791 | .subdevice = PCI_ANY_ID, | |
1792 | .init = pci_inteli960ni_init, | |
1793 | .setup = pci_default_setup, | |
1794 | }, | |
b6adea33 MCC |
1795 | { |
1796 | .vendor = PCI_VENDOR_ID_INTEL, | |
1797 | .device = PCI_DEVICE_ID_INTEL_8257X_SOL, | |
1798 | .subvendor = PCI_ANY_ID, | |
1799 | .subdevice = PCI_ANY_ID, | |
1800 | .setup = skip_tx_en_setup, | |
1801 | }, | |
1802 | { | |
1803 | .vendor = PCI_VENDOR_ID_INTEL, | |
1804 | .device = PCI_DEVICE_ID_INTEL_82573L_SOL, | |
1805 | .subvendor = PCI_ANY_ID, | |
1806 | .subdevice = PCI_ANY_ID, | |
1807 | .setup = skip_tx_en_setup, | |
1808 | }, | |
1809 | { | |
1810 | .vendor = PCI_VENDOR_ID_INTEL, | |
1811 | .device = PCI_DEVICE_ID_INTEL_82573E_SOL, | |
1812 | .subvendor = PCI_ANY_ID, | |
1813 | .subdevice = PCI_ANY_ID, | |
1814 | .setup = skip_tx_en_setup, | |
1815 | }, | |
095e24b0 DB |
1816 | { |
1817 | .vendor = PCI_VENDOR_ID_INTEL, | |
1818 | .device = PCI_DEVICE_ID_INTEL_CE4100_UART, | |
1819 | .subvendor = PCI_ANY_ID, | |
1820 | .subdevice = PCI_ANY_ID, | |
1821 | .setup = ce4100_serial_setup, | |
1822 | }, | |
bc02d15a DW |
1823 | { |
1824 | .vendor = PCI_VENDOR_ID_INTEL, | |
1825 | .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, | |
1826 | .subvendor = PCI_ANY_ID, | |
1827 | .subdevice = PCI_ANY_ID, | |
1828 | .setup = kt_serial_setup, | |
1829 | }, | |
84f8c6fc NV |
1830 | /* |
1831 | * ITE | |
1832 | */ | |
1833 | { | |
1834 | .vendor = PCI_VENDOR_ID_ITE, | |
1835 | .device = PCI_DEVICE_ID_ITE_8872, | |
1836 | .subvendor = PCI_ANY_ID, | |
1837 | .subdevice = PCI_ANY_ID, | |
1838 | .init = pci_ite887x_init, | |
1839 | .setup = pci_default_setup, | |
2d47b716 | 1840 | .exit = pci_ite887x_exit, |
84f8c6fc | 1841 | }, |
46a0fac9 SB |
1842 | /* |
1843 | * National Instruments | |
1844 | */ | |
04bf7e74 WP |
1845 | { |
1846 | .vendor = PCI_VENDOR_ID_NI, | |
1847 | .device = PCI_DEVICE_ID_NI_PCI23216, | |
1848 | .subvendor = PCI_ANY_ID, | |
1849 | .subdevice = PCI_ANY_ID, | |
1850 | .init = pci_ni8420_init, | |
1851 | .setup = pci_default_setup, | |
2d47b716 | 1852 | .exit = pci_ni8420_exit, |
04bf7e74 WP |
1853 | }, |
1854 | { | |
1855 | .vendor = PCI_VENDOR_ID_NI, | |
1856 | .device = PCI_DEVICE_ID_NI_PCI2328, | |
1857 | .subvendor = PCI_ANY_ID, | |
1858 | .subdevice = PCI_ANY_ID, | |
1859 | .init = pci_ni8420_init, | |
1860 | .setup = pci_default_setup, | |
2d47b716 | 1861 | .exit = pci_ni8420_exit, |
04bf7e74 WP |
1862 | }, |
1863 | { | |
1864 | .vendor = PCI_VENDOR_ID_NI, | |
1865 | .device = PCI_DEVICE_ID_NI_PCI2324, | |
1866 | .subvendor = PCI_ANY_ID, | |
1867 | .subdevice = PCI_ANY_ID, | |
1868 | .init = pci_ni8420_init, | |
1869 | .setup = pci_default_setup, | |
2d47b716 | 1870 | .exit = pci_ni8420_exit, |
04bf7e74 WP |
1871 | }, |
1872 | { | |
1873 | .vendor = PCI_VENDOR_ID_NI, | |
1874 | .device = PCI_DEVICE_ID_NI_PCI2322, | |
1875 | .subvendor = PCI_ANY_ID, | |
1876 | .subdevice = PCI_ANY_ID, | |
1877 | .init = pci_ni8420_init, | |
1878 | .setup = pci_default_setup, | |
2d47b716 | 1879 | .exit = pci_ni8420_exit, |
04bf7e74 WP |
1880 | }, |
1881 | { | |
1882 | .vendor = PCI_VENDOR_ID_NI, | |
1883 | .device = PCI_DEVICE_ID_NI_PCI2324I, | |
1884 | .subvendor = PCI_ANY_ID, | |
1885 | .subdevice = PCI_ANY_ID, | |
1886 | .init = pci_ni8420_init, | |
1887 | .setup = pci_default_setup, | |
2d47b716 | 1888 | .exit = pci_ni8420_exit, |
04bf7e74 WP |
1889 | }, |
1890 | { | |
1891 | .vendor = PCI_VENDOR_ID_NI, | |
1892 | .device = PCI_DEVICE_ID_NI_PCI2322I, | |
1893 | .subvendor = PCI_ANY_ID, | |
1894 | .subdevice = PCI_ANY_ID, | |
1895 | .init = pci_ni8420_init, | |
1896 | .setup = pci_default_setup, | |
2d47b716 | 1897 | .exit = pci_ni8420_exit, |
04bf7e74 WP |
1898 | }, |
1899 | { | |
1900 | .vendor = PCI_VENDOR_ID_NI, | |
1901 | .device = PCI_DEVICE_ID_NI_PXI8420_23216, | |
1902 | .subvendor = PCI_ANY_ID, | |
1903 | .subdevice = PCI_ANY_ID, | |
1904 | .init = pci_ni8420_init, | |
1905 | .setup = pci_default_setup, | |
2d47b716 | 1906 | .exit = pci_ni8420_exit, |
04bf7e74 WP |
1907 | }, |
1908 | { | |
1909 | .vendor = PCI_VENDOR_ID_NI, | |
1910 | .device = PCI_DEVICE_ID_NI_PXI8420_2328, | |
1911 | .subvendor = PCI_ANY_ID, | |
1912 | .subdevice = PCI_ANY_ID, | |
1913 | .init = pci_ni8420_init, | |
1914 | .setup = pci_default_setup, | |
2d47b716 | 1915 | .exit = pci_ni8420_exit, |
04bf7e74 WP |
1916 | }, |
1917 | { | |
1918 | .vendor = PCI_VENDOR_ID_NI, | |
1919 | .device = PCI_DEVICE_ID_NI_PXI8420_2324, | |
1920 | .subvendor = PCI_ANY_ID, | |
1921 | .subdevice = PCI_ANY_ID, | |
1922 | .init = pci_ni8420_init, | |
1923 | .setup = pci_default_setup, | |
2d47b716 | 1924 | .exit = pci_ni8420_exit, |
04bf7e74 WP |
1925 | }, |
1926 | { | |
1927 | .vendor = PCI_VENDOR_ID_NI, | |
1928 | .device = PCI_DEVICE_ID_NI_PXI8420_2322, | |
1929 | .subvendor = PCI_ANY_ID, | |
1930 | .subdevice = PCI_ANY_ID, | |
1931 | .init = pci_ni8420_init, | |
1932 | .setup = pci_default_setup, | |
2d47b716 | 1933 | .exit = pci_ni8420_exit, |
04bf7e74 WP |
1934 | }, |
1935 | { | |
1936 | .vendor = PCI_VENDOR_ID_NI, | |
1937 | .device = PCI_DEVICE_ID_NI_PXI8422_2324, | |
1938 | .subvendor = PCI_ANY_ID, | |
1939 | .subdevice = PCI_ANY_ID, | |
1940 | .init = pci_ni8420_init, | |
1941 | .setup = pci_default_setup, | |
2d47b716 | 1942 | .exit = pci_ni8420_exit, |
04bf7e74 WP |
1943 | }, |
1944 | { | |
1945 | .vendor = PCI_VENDOR_ID_NI, | |
1946 | .device = PCI_DEVICE_ID_NI_PXI8422_2322, | |
1947 | .subvendor = PCI_ANY_ID, | |
1948 | .subdevice = PCI_ANY_ID, | |
1949 | .init = pci_ni8420_init, | |
1950 | .setup = pci_default_setup, | |
2d47b716 | 1951 | .exit = pci_ni8420_exit, |
04bf7e74 | 1952 | }, |
46a0fac9 SB |
1953 | { |
1954 | .vendor = PCI_VENDOR_ID_NI, | |
1955 | .device = PCI_ANY_ID, | |
1956 | .subvendor = PCI_ANY_ID, | |
1957 | .subdevice = PCI_ANY_ID, | |
1958 | .init = pci_ni8430_init, | |
1959 | .setup = pci_ni8430_setup, | |
2d47b716 | 1960 | .exit = pci_ni8430_exit, |
46a0fac9 | 1961 | }, |
55c7c0fd AC |
1962 | /* Quatech */ |
1963 | { | |
1964 | .vendor = PCI_VENDOR_ID_QUATECH, | |
1965 | .device = PCI_ANY_ID, | |
1966 | .subvendor = PCI_ANY_ID, | |
1967 | .subdevice = PCI_ANY_ID, | |
1968 | .init = pci_quatech_init, | |
1969 | .setup = pci_quatech_setup, | |
d73dfc6a | 1970 | .exit = pci_quatech_exit, |
55c7c0fd | 1971 | }, |
1da177e4 LT |
1972 | /* |
1973 | * Panacom | |
1974 | */ | |
1975 | { | |
1976 | .vendor = PCI_VENDOR_ID_PANACOM, | |
1977 | .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, | |
1978 | .subvendor = PCI_ANY_ID, | |
1979 | .subdevice = PCI_ANY_ID, | |
1980 | .init = pci_plx9050_init, | |
1981 | .setup = pci_default_setup, | |
2d47b716 | 1982 | .exit = pci_plx9050_exit, |
5756ee99 | 1983 | }, |
1da177e4 LT |
1984 | { |
1985 | .vendor = PCI_VENDOR_ID_PANACOM, | |
1986 | .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, | |
1987 | .subvendor = PCI_ANY_ID, | |
1988 | .subdevice = PCI_ANY_ID, | |
1989 | .init = pci_plx9050_init, | |
1990 | .setup = pci_default_setup, | |
2d47b716 | 1991 | .exit = pci_plx9050_exit, |
1da177e4 | 1992 | }, |
5c31ef91 AB |
1993 | /* |
1994 | * Pericom (Only 7954 - It have a offset jump for port 4) | |
1995 | */ | |
1996 | { | |
1997 | .vendor = PCI_VENDOR_ID_PERICOM, | |
1998 | .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954, | |
1999 | .subvendor = PCI_ANY_ID, | |
2000 | .subdevice = PCI_ANY_ID, | |
2001 | .setup = pci_pericom_setup, | |
2002 | }, | |
1da177e4 LT |
2003 | /* |
2004 | * PLX | |
2005 | */ | |
add7b58e BH |
2006 | { |
2007 | .vendor = PCI_VENDOR_ID_PLX, | |
2008 | .device = PCI_DEVICE_ID_PLX_9050, | |
2009 | .subvendor = PCI_SUBVENDOR_ID_EXSYS, | |
2010 | .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, | |
2011 | .init = pci_plx9050_init, | |
2012 | .setup = pci_default_setup, | |
2d47b716 | 2013 | .exit = pci_plx9050_exit, |
add7b58e | 2014 | }, |
1da177e4 LT |
2015 | { |
2016 | .vendor = PCI_VENDOR_ID_PLX, | |
2017 | .device = PCI_DEVICE_ID_PLX_9050, | |
2018 | .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, | |
2019 | .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, | |
2020 | .init = pci_plx9050_init, | |
2021 | .setup = pci_default_setup, | |
2d47b716 | 2022 | .exit = pci_plx9050_exit, |
1da177e4 LT |
2023 | }, |
2024 | { | |
2025 | .vendor = PCI_VENDOR_ID_PLX, | |
2026 | .device = PCI_DEVICE_ID_PLX_ROMULUS, | |
2027 | .subvendor = PCI_VENDOR_ID_PLX, | |
2028 | .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, | |
2029 | .init = pci_plx9050_init, | |
2030 | .setup = pci_default_setup, | |
2d47b716 | 2031 | .exit = pci_plx9050_exit, |
1da177e4 LT |
2032 | }, |
2033 | /* | |
2034 | * SBS Technologies, Inc., PMC-OCTALPRO 232 | |
2035 | */ | |
2036 | { | |
2037 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
2038 | .device = PCI_DEVICE_ID_OCTPRO, | |
2039 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
2040 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, | |
2041 | .init = sbs_init, | |
2042 | .setup = sbs_setup, | |
2d47b716 | 2043 | .exit = sbs_exit, |
1da177e4 LT |
2044 | }, |
2045 | /* | |
2046 | * SBS Technologies, Inc., PMC-OCTALPRO 422 | |
2047 | */ | |
2048 | { | |
2049 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
2050 | .device = PCI_DEVICE_ID_OCTPRO, | |
2051 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
2052 | .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, | |
2053 | .init = sbs_init, | |
2054 | .setup = sbs_setup, | |
2d47b716 | 2055 | .exit = sbs_exit, |
1da177e4 LT |
2056 | }, |
2057 | /* | |
2058 | * SBS Technologies, Inc., P-Octal 232 | |
2059 | */ | |
2060 | { | |
2061 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
2062 | .device = PCI_DEVICE_ID_OCTPRO, | |
2063 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
2064 | .subdevice = PCI_SUBDEVICE_ID_POCTAL232, | |
2065 | .init = sbs_init, | |
2066 | .setup = sbs_setup, | |
2d47b716 | 2067 | .exit = sbs_exit, |
1da177e4 LT |
2068 | }, |
2069 | /* | |
2070 | * SBS Technologies, Inc., P-Octal 422 | |
2071 | */ | |
2072 | { | |
2073 | .vendor = PCI_VENDOR_ID_SBSMODULARIO, | |
2074 | .device = PCI_DEVICE_ID_OCTPRO, | |
2075 | .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, | |
2076 | .subdevice = PCI_SUBDEVICE_ID_POCTAL422, | |
2077 | .init = sbs_init, | |
2078 | .setup = sbs_setup, | |
2d47b716 | 2079 | .exit = sbs_exit, |
1da177e4 | 2080 | }, |
1da177e4 | 2081 | /* |
61a116ef | 2082 | * SIIG cards - these may be called via parport_serial |
1da177e4 LT |
2083 | */ |
2084 | { | |
2085 | .vendor = PCI_VENDOR_ID_SIIG, | |
67d74b87 | 2086 | .device = PCI_ANY_ID, |
1da177e4 LT |
2087 | .subvendor = PCI_ANY_ID, |
2088 | .subdevice = PCI_ANY_ID, | |
67d74b87 | 2089 | .init = pci_siig_init, |
3ec9c594 | 2090 | .setup = pci_siig_setup, |
1da177e4 LT |
2091 | }, |
2092 | /* | |
2093 | * Titan cards | |
2094 | */ | |
2095 | { | |
2096 | .vendor = PCI_VENDOR_ID_TITAN, | |
2097 | .device = PCI_DEVICE_ID_TITAN_400L, | |
2098 | .subvendor = PCI_ANY_ID, | |
2099 | .subdevice = PCI_ANY_ID, | |
2100 | .setup = titan_400l_800l_setup, | |
2101 | }, | |
2102 | { | |
2103 | .vendor = PCI_VENDOR_ID_TITAN, | |
2104 | .device = PCI_DEVICE_ID_TITAN_800L, | |
2105 | .subvendor = PCI_ANY_ID, | |
2106 | .subdevice = PCI_ANY_ID, | |
2107 | .setup = titan_400l_800l_setup, | |
2108 | }, | |
2109 | /* | |
2110 | * Timedia cards | |
2111 | */ | |
2112 | { | |
2113 | .vendor = PCI_VENDOR_ID_TIMEDIA, | |
2114 | .device = PCI_DEVICE_ID_TIMEDIA_1889, | |
2115 | .subvendor = PCI_VENDOR_ID_TIMEDIA, | |
2116 | .subdevice = PCI_ANY_ID, | |
b9b24558 | 2117 | .probe = pci_timedia_probe, |
1da177e4 LT |
2118 | .init = pci_timedia_init, |
2119 | .setup = pci_timedia_setup, | |
2120 | }, | |
2121 | { | |
2122 | .vendor = PCI_VENDOR_ID_TIMEDIA, | |
2123 | .device = PCI_ANY_ID, | |
2124 | .subvendor = PCI_ANY_ID, | |
2125 | .subdevice = PCI_ANY_ID, | |
2126 | .setup = pci_timedia_setup, | |
2127 | }, | |
abd7baca SC |
2128 | /* |
2129 | * SUNIX (Timedia) cards | |
2130 | * Do not "probe" for these cards as there is at least one combination | |
2131 | * card that should be handled by parport_pc that doesn't match the | |
2132 | * rule in pci_timedia_probe. | |
2133 | * It is part number is MIO5079A but its subdevice ID is 0x0102. | |
2134 | * There are some boards with part number SER5037AL that report | |
2135 | * subdevice ID 0x0002. | |
2136 | */ | |
2137 | { | |
2138 | .vendor = PCI_VENDOR_ID_SUNIX, | |
2139 | .device = PCI_DEVICE_ID_SUNIX_1999, | |
2140 | .subvendor = PCI_VENDOR_ID_SUNIX, | |
2141 | .subdevice = PCI_ANY_ID, | |
2142 | .init = pci_timedia_init, | |
2143 | .setup = pci_timedia_setup, | |
2144 | }, | |
1da177e4 LT |
2145 | /* |
2146 | * Xircom cards | |
2147 | */ | |
2148 | { | |
2149 | .vendor = PCI_VENDOR_ID_XIRCOM, | |
2150 | .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, | |
2151 | .subvendor = PCI_ANY_ID, | |
2152 | .subdevice = PCI_ANY_ID, | |
2153 | .init = pci_xircom_init, | |
2154 | .setup = pci_default_setup, | |
2155 | }, | |
2156 | /* | |
61a116ef | 2157 | * Netmos cards - these may be called via parport_serial |
1da177e4 LT |
2158 | */ |
2159 | { | |
2160 | .vendor = PCI_VENDOR_ID_NETMOS, | |
2161 | .device = PCI_ANY_ID, | |
2162 | .subvendor = PCI_ANY_ID, | |
2163 | .subdevice = PCI_ANY_ID, | |
2164 | .init = pci_netmos_init, | |
7808edcd | 2165 | .setup = pci_netmos_9900_setup, |
1da177e4 | 2166 | }, |
1bc8cde4 MS |
2167 | /* |
2168 | * EndRun Technologies | |
2169 | */ | |
2170 | { | |
2171 | .vendor = PCI_VENDOR_ID_ENDRUN, | |
2172 | .device = PCI_ANY_ID, | |
2173 | .subvendor = PCI_ANY_ID, | |
2174 | .subdevice = PCI_ANY_ID, | |
2175 | .init = pci_endrun_init, | |
2176 | .setup = pci_default_setup, | |
2177 | }, | |
9f2a036a | 2178 | /* |
aa273ae5 | 2179 | * For Oxford Semiconductor Tornado based devices |
9f2a036a RK |
2180 | */ |
2181 | { | |
2182 | .vendor = PCI_VENDOR_ID_OXSEMI, | |
2183 | .device = PCI_ANY_ID, | |
2184 | .subvendor = PCI_ANY_ID, | |
2185 | .subdevice = PCI_ANY_ID, | |
2186 | .init = pci_oxsemi_tornado_init, | |
2187 | .setup = pci_default_setup, | |
2188 | }, | |
2189 | { | |
2190 | .vendor = PCI_VENDOR_ID_MAINPINE, | |
2191 | .device = PCI_ANY_ID, | |
2192 | .subvendor = PCI_ANY_ID, | |
2193 | .subdevice = PCI_ANY_ID, | |
2194 | .init = pci_oxsemi_tornado_init, | |
2195 | .setup = pci_default_setup, | |
2196 | }, | |
aa273ae5 SK |
2197 | { |
2198 | .vendor = PCI_VENDOR_ID_DIGI, | |
2199 | .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, | |
2200 | .subvendor = PCI_SUBVENDOR_ID_IBM, | |
2201 | .subdevice = PCI_ANY_ID, | |
2202 | .init = pci_oxsemi_tornado_init, | |
2203 | .setup = pci_default_setup, | |
2204 | }, | |
eb7073db TM |
2205 | { |
2206 | .vendor = PCI_VENDOR_ID_INTEL, | |
2207 | .device = 0x8811, | |
aaa10eb1 AP |
2208 | .subvendor = PCI_ANY_ID, |
2209 | .subdevice = PCI_ANY_ID, | |
eb7073db | 2210 | .init = pci_eg20t_init, |
64d91cfa | 2211 | .setup = pci_default_setup, |
eb7073db TM |
2212 | }, |
2213 | { | |
2214 | .vendor = PCI_VENDOR_ID_INTEL, | |
2215 | .device = 0x8812, | |
aaa10eb1 AP |
2216 | .subvendor = PCI_ANY_ID, |
2217 | .subdevice = PCI_ANY_ID, | |
eb7073db | 2218 | .init = pci_eg20t_init, |
64d91cfa | 2219 | .setup = pci_default_setup, |
eb7073db TM |
2220 | }, |
2221 | { | |
2222 | .vendor = PCI_VENDOR_ID_INTEL, | |
2223 | .device = 0x8813, | |
aaa10eb1 AP |
2224 | .subvendor = PCI_ANY_ID, |
2225 | .subdevice = PCI_ANY_ID, | |
eb7073db | 2226 | .init = pci_eg20t_init, |
64d91cfa | 2227 | .setup = pci_default_setup, |
eb7073db TM |
2228 | }, |
2229 | { | |
2230 | .vendor = PCI_VENDOR_ID_INTEL, | |
2231 | .device = 0x8814, | |
aaa10eb1 AP |
2232 | .subvendor = PCI_ANY_ID, |
2233 | .subdevice = PCI_ANY_ID, | |
eb7073db | 2234 | .init = pci_eg20t_init, |
64d91cfa | 2235 | .setup = pci_default_setup, |
eb7073db TM |
2236 | }, |
2237 | { | |
2238 | .vendor = 0x10DB, | |
2239 | .device = 0x8027, | |
aaa10eb1 AP |
2240 | .subvendor = PCI_ANY_ID, |
2241 | .subdevice = PCI_ANY_ID, | |
eb7073db | 2242 | .init = pci_eg20t_init, |
64d91cfa | 2243 | .setup = pci_default_setup, |
eb7073db TM |
2244 | }, |
2245 | { | |
2246 | .vendor = 0x10DB, | |
2247 | .device = 0x8028, | |
aaa10eb1 AP |
2248 | .subvendor = PCI_ANY_ID, |
2249 | .subdevice = PCI_ANY_ID, | |
eb7073db | 2250 | .init = pci_eg20t_init, |
64d91cfa | 2251 | .setup = pci_default_setup, |
eb7073db TM |
2252 | }, |
2253 | { | |
2254 | .vendor = 0x10DB, | |
2255 | .device = 0x8029, | |
aaa10eb1 AP |
2256 | .subvendor = PCI_ANY_ID, |
2257 | .subdevice = PCI_ANY_ID, | |
eb7073db | 2258 | .init = pci_eg20t_init, |
64d91cfa | 2259 | .setup = pci_default_setup, |
eb7073db TM |
2260 | }, |
2261 | { | |
2262 | .vendor = 0x10DB, | |
2263 | .device = 0x800C, | |
aaa10eb1 AP |
2264 | .subvendor = PCI_ANY_ID, |
2265 | .subdevice = PCI_ANY_ID, | |
eb7073db | 2266 | .init = pci_eg20t_init, |
64d91cfa | 2267 | .setup = pci_default_setup, |
eb7073db TM |
2268 | }, |
2269 | { | |
2270 | .vendor = 0x10DB, | |
2271 | .device = 0x800D, | |
aaa10eb1 AP |
2272 | .subvendor = PCI_ANY_ID, |
2273 | .subdevice = PCI_ANY_ID, | |
eb7073db | 2274 | .init = pci_eg20t_init, |
64d91cfa | 2275 | .setup = pci_default_setup, |
eb7073db | 2276 | }, |
d9a0fbfd AP |
2277 | /* |
2278 | * Cronyx Omega PCI (PLX-chip based) | |
2279 | */ | |
2280 | { | |
2281 | .vendor = PCI_VENDOR_ID_PLX, | |
2282 | .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, | |
2283 | .subvendor = PCI_ANY_ID, | |
2284 | .subdevice = PCI_ANY_ID, | |
2285 | .setup = pci_omegapci_setup, | |
eb26dfe8 | 2286 | }, |
feb58142 EG |
2287 | /* WCH CH353 1S1P card (16550 clone) */ |
2288 | { | |
2289 | .vendor = PCI_VENDOR_ID_WCH, | |
2290 | .device = PCI_DEVICE_ID_WCH_CH353_1S1P, | |
2291 | .subvendor = PCI_ANY_ID, | |
2292 | .subdevice = PCI_ANY_ID, | |
2293 | .setup = pci_wch_ch353_setup, | |
2294 | }, | |
6971c635 GA |
2295 | /* WCH CH353 2S1P card (16550 clone) */ |
2296 | { | |
27788c5f AC |
2297 | .vendor = PCI_VENDOR_ID_WCH, |
2298 | .device = PCI_DEVICE_ID_WCH_CH353_2S1P, | |
2299 | .subvendor = PCI_ANY_ID, | |
2300 | .subdevice = PCI_ANY_ID, | |
2301 | .setup = pci_wch_ch353_setup, | |
2302 | }, | |
2303 | /* WCH CH353 4S card (16550 clone) */ | |
2304 | { | |
2305 | .vendor = PCI_VENDOR_ID_WCH, | |
2306 | .device = PCI_DEVICE_ID_WCH_CH353_4S, | |
2307 | .subvendor = PCI_ANY_ID, | |
2308 | .subdevice = PCI_ANY_ID, | |
2309 | .setup = pci_wch_ch353_setup, | |
2310 | }, | |
2311 | /* WCH CH353 2S1PF card (16550 clone) */ | |
2312 | { | |
2313 | .vendor = PCI_VENDOR_ID_WCH, | |
2314 | .device = PCI_DEVICE_ID_WCH_CH353_2S1PF, | |
2315 | .subvendor = PCI_ANY_ID, | |
2316 | .subdevice = PCI_ANY_ID, | |
6971c635 GA |
2317 | .setup = pci_wch_ch353_setup, |
2318 | }, | |
8b5c913f WY |
2319 | /* WCH CH352 2S card (16550 clone) */ |
2320 | { | |
2321 | .vendor = PCI_VENDOR_ID_WCH, | |
2322 | .device = PCI_DEVICE_ID_WCH_CH352_2S, | |
2323 | .subvendor = PCI_ANY_ID, | |
2324 | .subdevice = PCI_ANY_ID, | |
2325 | .setup = pci_wch_ch353_setup, | |
2326 | }, | |
55c368cb AP |
2327 | /* WCH CH355 4S card (16550 clone) */ |
2328 | { | |
2329 | .vendor = PCI_VENDOR_ID_WCH, | |
2330 | .device = PCI_DEVICE_ID_WCH_CH355_4S, | |
2331 | .subvendor = PCI_ANY_ID, | |
2332 | .subdevice = PCI_ANY_ID, | |
2333 | .setup = pci_wch_ch355_setup, | |
2334 | }, | |
7dde5578 JM |
2335 | /* WCH CH382 2S card (16850 clone) */ |
2336 | { | |
2337 | .vendor = PCIE_VENDOR_ID_WCH, | |
2338 | .device = PCIE_DEVICE_ID_WCH_CH382_2S, | |
2339 | .subvendor = PCI_ANY_ID, | |
2340 | .subdevice = PCI_ANY_ID, | |
2341 | .setup = pci_wch_ch38x_setup, | |
2342 | }, | |
72a3c0e4 | 2343 | /* WCH CH382 2S1P card (16850 clone) */ |
2fdd8c8c SP |
2344 | { |
2345 | .vendor = PCIE_VENDOR_ID_WCH, | |
2346 | .device = PCIE_DEVICE_ID_WCH_CH382_2S1P, | |
2347 | .subvendor = PCI_ANY_ID, | |
2348 | .subdevice = PCI_ANY_ID, | |
72a3c0e4 SP |
2349 | .setup = pci_wch_ch38x_setup, |
2350 | }, | |
2351 | /* WCH CH384 4S card (16850 clone) */ | |
2352 | { | |
2353 | .vendor = PCIE_VENDOR_ID_WCH, | |
2354 | .device = PCIE_DEVICE_ID_WCH_CH384_4S, | |
2355 | .subvendor = PCI_ANY_ID, | |
2356 | .subdevice = PCI_ANY_ID, | |
2357 | .setup = pci_wch_ch38x_setup, | |
2fdd8c8c | 2358 | }, |
eb26dfe8 AC |
2359 | /* |
2360 | * ASIX devices with FIFO bug | |
2361 | */ | |
2362 | { | |
2363 | .vendor = PCI_VENDOR_ID_ASIX, | |
2364 | .device = PCI_ANY_ID, | |
2365 | .subvendor = PCI_ANY_ID, | |
2366 | .subdevice = PCI_ANY_ID, | |
2367 | .setup = pci_asix_setup, | |
2368 | }, | |
ebebd49a SH |
2369 | /* |
2370 | * Broadcom TruManage (NetXtreme) | |
2371 | */ | |
2372 | { | |
2373 | .vendor = PCI_VENDOR_ID_BROADCOM, | |
2374 | .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, | |
2375 | .subvendor = PCI_ANY_ID, | |
2376 | .subdevice = PCI_ANY_ID, | |
2377 | .setup = pci_brcm_trumanage_setup, | |
2378 | }, | |
2c62a3c8 GKH |
2379 | { |
2380 | .vendor = 0x1c29, | |
2381 | .device = 0x1104, | |
2382 | .subvendor = PCI_ANY_ID, | |
2383 | .subdevice = PCI_ANY_ID, | |
2384 | .setup = pci_fintek_setup, | |
6a8bc239 | 2385 | .init = pci_fintek_init, |
2c62a3c8 GKH |
2386 | }, |
2387 | { | |
2388 | .vendor = 0x1c29, | |
2389 | .device = 0x1108, | |
2390 | .subvendor = PCI_ANY_ID, | |
2391 | .subdevice = PCI_ANY_ID, | |
2392 | .setup = pci_fintek_setup, | |
6a8bc239 | 2393 | .init = pci_fintek_init, |
2c62a3c8 GKH |
2394 | }, |
2395 | { | |
2396 | .vendor = 0x1c29, | |
2397 | .device = 0x1112, | |
2398 | .subvendor = PCI_ANY_ID, | |
2399 | .subdevice = PCI_ANY_ID, | |
2400 | .setup = pci_fintek_setup, | |
6a8bc239 | 2401 | .init = pci_fintek_init, |
2c62a3c8 | 2402 | }, |
ebebd49a | 2403 | |
1da177e4 LT |
2404 | /* |
2405 | * Default "match everything" terminator entry | |
2406 | */ | |
2407 | { | |
2408 | .vendor = PCI_ANY_ID, | |
2409 | .device = PCI_ANY_ID, | |
2410 | .subvendor = PCI_ANY_ID, | |
2411 | .subdevice = PCI_ANY_ID, | |
2412 | .setup = pci_default_setup, | |
2413 | } | |
2414 | }; | |
2415 | ||
2416 | static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) | |
2417 | { | |
2418 | return quirk_id == PCI_ANY_ID || quirk_id == dev_id; | |
2419 | } | |
2420 | ||
2421 | static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) | |
2422 | { | |
2423 | struct pci_serial_quirk *quirk; | |
2424 | ||
2425 | for (quirk = pci_serial_quirks; ; quirk++) | |
2426 | if (quirk_id_matches(quirk->vendor, dev->vendor) && | |
2427 | quirk_id_matches(quirk->device, dev->device) && | |
2428 | quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && | |
2429 | quirk_id_matches(quirk->subdevice, dev->subsystem_device)) | |
5756ee99 | 2430 | break; |
1da177e4 LT |
2431 | return quirk; |
2432 | } | |
2433 | ||
dd68e88c | 2434 | static inline int get_pci_irq(struct pci_dev *dev, |
975a1a7d | 2435 | const struct pciserial_board *board) |
1da177e4 LT |
2436 | { |
2437 | if (board->flags & FL_NOIRQ) | |
2438 | return 0; | |
2439 | else | |
2440 | return dev->irq; | |
2441 | } | |
2442 | ||
2443 | /* | |
2444 | * This is the configuration table for all of the PCI serial boards | |
2445 | * which we support. It is directly indexed by the pci_board_num_t enum | |
2446 | * value, which is encoded in the pci_device_id PCI probe table's | |
2447 | * driver_data member. | |
2448 | * | |
2449 | * The makeup of these names are: | |
26e92861 | 2450 | * pbn_bn{_bt}_n_baud{_offsetinhex} |
1da177e4 | 2451 | * |
26e92861 GH |
2452 | * bn = PCI BAR number |
2453 | * bt = Index using PCI BARs | |
2454 | * n = number of serial ports | |
2455 | * baud = baud rate | |
2456 | * offsetinhex = offset for each sequential port (in hex) | |
1da177e4 | 2457 | * |
26e92861 | 2458 | * This table is sorted by (in order): bn, bt, baud, offsetindex, n. |
f1690f37 | 2459 | * |
1da177e4 LT |
2460 | * Please note: in theory if n = 1, _bt infix should make no difference. |
2461 | * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 | |
2462 | */ | |
2463 | enum pci_board_num_t { | |
2464 | pbn_default = 0, | |
2465 | ||
2466 | pbn_b0_1_115200, | |
2467 | pbn_b0_2_115200, | |
2468 | pbn_b0_4_115200, | |
2469 | pbn_b0_5_115200, | |
bf0df636 | 2470 | pbn_b0_8_115200, |
1da177e4 LT |
2471 | |
2472 | pbn_b0_1_921600, | |
2473 | pbn_b0_2_921600, | |
2474 | pbn_b0_4_921600, | |
2475 | ||
db1de159 DR |
2476 | pbn_b0_2_1130000, |
2477 | ||
fbc0dc0d AP |
2478 | pbn_b0_4_1152000, |
2479 | ||
1c9c858e IA |
2480 | pbn_b0_4_1250000, |
2481 | ||
26e92861 GH |
2482 | pbn_b0_2_1843200, |
2483 | pbn_b0_4_1843200, | |
2484 | ||
7106b4e3 LH |
2485 | pbn_b0_1_4000000, |
2486 | ||
1da177e4 LT |
2487 | pbn_b0_bt_1_115200, |
2488 | pbn_b0_bt_2_115200, | |
ac6ec5b1 | 2489 | pbn_b0_bt_4_115200, |
1da177e4 LT |
2490 | pbn_b0_bt_8_115200, |
2491 | ||
2492 | pbn_b0_bt_1_460800, | |
2493 | pbn_b0_bt_2_460800, | |
2494 | pbn_b0_bt_4_460800, | |
2495 | ||
2496 | pbn_b0_bt_1_921600, | |
2497 | pbn_b0_bt_2_921600, | |
2498 | pbn_b0_bt_4_921600, | |
2499 | pbn_b0_bt_8_921600, | |
2500 | ||
2501 | pbn_b1_1_115200, | |
2502 | pbn_b1_2_115200, | |
2503 | pbn_b1_4_115200, | |
2504 | pbn_b1_8_115200, | |
04bf7e74 | 2505 | pbn_b1_16_115200, |
1da177e4 LT |
2506 | |
2507 | pbn_b1_1_921600, | |
2508 | pbn_b1_2_921600, | |
2509 | pbn_b1_4_921600, | |
2510 | pbn_b1_8_921600, | |
2511 | ||
26e92861 GH |
2512 | pbn_b1_2_1250000, |
2513 | ||
84f8c6fc | 2514 | pbn_b1_bt_1_115200, |
04bf7e74 WP |
2515 | pbn_b1_bt_2_115200, |
2516 | pbn_b1_bt_4_115200, | |
2517 | ||
1da177e4 LT |
2518 | pbn_b1_bt_2_921600, |
2519 | ||
2520 | pbn_b1_1_1382400, | |
2521 | pbn_b1_2_1382400, | |
2522 | pbn_b1_4_1382400, | |
2523 | pbn_b1_8_1382400, | |
2524 | ||
2525 | pbn_b2_1_115200, | |
737c1756 | 2526 | pbn_b2_2_115200, |
a9cccd34 | 2527 | pbn_b2_4_115200, |
1da177e4 LT |
2528 | pbn_b2_8_115200, |
2529 | ||
2530 | pbn_b2_1_460800, | |
2531 | pbn_b2_4_460800, | |
2532 | pbn_b2_8_460800, | |
2533 | pbn_b2_16_460800, | |
2534 | ||
2535 | pbn_b2_1_921600, | |
2536 | pbn_b2_4_921600, | |
2537 | pbn_b2_8_921600, | |
2538 | ||
e847003f LB |
2539 | pbn_b2_8_1152000, |
2540 | ||
1da177e4 LT |
2541 | pbn_b2_bt_1_115200, |
2542 | pbn_b2_bt_2_115200, | |
2543 | pbn_b2_bt_4_115200, | |
2544 | ||
2545 | pbn_b2_bt_2_921600, | |
2546 | pbn_b2_bt_4_921600, | |
2547 | ||
d9004eb4 | 2548 | pbn_b3_2_115200, |
1da177e4 LT |
2549 | pbn_b3_4_115200, |
2550 | pbn_b3_8_115200, | |
2551 | ||
66169ad1 YY |
2552 | pbn_b4_bt_2_921600, |
2553 | pbn_b4_bt_4_921600, | |
2554 | pbn_b4_bt_8_921600, | |
2555 | ||
1da177e4 LT |
2556 | /* |
2557 | * Board-specific versions. | |
2558 | */ | |
2559 | pbn_panacom, | |
2560 | pbn_panacom2, | |
2561 | pbn_panacom4, | |
2562 | pbn_plx_romulus, | |
1bc8cde4 | 2563 | pbn_endrun_2_4000000, |
1da177e4 | 2564 | pbn_oxsemi, |
7106b4e3 LH |
2565 | pbn_oxsemi_1_4000000, |
2566 | pbn_oxsemi_2_4000000, | |
2567 | pbn_oxsemi_4_4000000, | |
2568 | pbn_oxsemi_8_4000000, | |
1da177e4 LT |
2569 | pbn_intel_i960, |
2570 | pbn_sgi_ioc3, | |
1da177e4 LT |
2571 | pbn_computone_4, |
2572 | pbn_computone_6, | |
2573 | pbn_computone_8, | |
2574 | pbn_sbsxrsio, | |
aa798505 | 2575 | pbn_pasemi_1682M, |
46a0fac9 SB |
2576 | pbn_ni8430_2, |
2577 | pbn_ni8430_4, | |
2578 | pbn_ni8430_8, | |
2579 | pbn_ni8430_16, | |
1b62cbf2 KJ |
2580 | pbn_ADDIDATA_PCIe_1_3906250, |
2581 | pbn_ADDIDATA_PCIe_2_3906250, | |
2582 | pbn_ADDIDATA_PCIe_4_3906250, | |
2583 | pbn_ADDIDATA_PCIe_8_3906250, | |
095e24b0 | 2584 | pbn_ce4100_1_115200, |
d9a0fbfd | 2585 | pbn_omegapci, |
7808edcd | 2586 | pbn_NETMOS9900_2s_115200, |
ebebd49a | 2587 | pbn_brcm_trumanage, |
2c62a3c8 GKH |
2588 | pbn_fintek_4, |
2589 | pbn_fintek_8, | |
2590 | pbn_fintek_12, | |
7dde5578 | 2591 | pbn_wch382_2, |
72a3c0e4 | 2592 | pbn_wch384_4, |
89c043a6 AL |
2593 | pbn_pericom_PI7C9X7951, |
2594 | pbn_pericom_PI7C9X7952, | |
2595 | pbn_pericom_PI7C9X7954, | |
2596 | pbn_pericom_PI7C9X7958, | |
1da177e4 LT |
2597 | }; |
2598 | ||
2599 | /* | |
2600 | * uart_offset - the space between channels | |
2601 | * reg_shift - describes how the UART registers are mapped | |
2602 | * to PCI memory by the card. | |
2603 | * For example IER register on SBS, Inc. PMC-OctPro is located at | |
2604 | * offset 0x10 from the UART base, while UART_IER is defined as 1 | |
2605 | * in include/linux/serial_reg.h, | |
2606 | * see first lines of serial_in() and serial_out() in 8250.c | |
2607 | */ | |
2608 | ||
de88b340 | 2609 | static struct pciserial_board pci_boards[] = { |
1da177e4 LT |
2610 | [pbn_default] = { |
2611 | .flags = FL_BASE0, | |
2612 | .num_ports = 1, | |
2613 | .base_baud = 115200, | |
2614 | .uart_offset = 8, | |
2615 | }, | |
2616 | [pbn_b0_1_115200] = { | |
2617 | .flags = FL_BASE0, | |
2618 | .num_ports = 1, | |
2619 | .base_baud = 115200, | |
2620 | .uart_offset = 8, | |
2621 | }, | |
2622 | [pbn_b0_2_115200] = { | |
2623 | .flags = FL_BASE0, | |
2624 | .num_ports = 2, | |
2625 | .base_baud = 115200, | |
2626 | .uart_offset = 8, | |
2627 | }, | |
2628 | [pbn_b0_4_115200] = { | |
2629 | .flags = FL_BASE0, | |
2630 | .num_ports = 4, | |
2631 | .base_baud = 115200, | |
2632 | .uart_offset = 8, | |
2633 | }, | |
2634 | [pbn_b0_5_115200] = { | |
2635 | .flags = FL_BASE0, | |
2636 | .num_ports = 5, | |
2637 | .base_baud = 115200, | |
2638 | .uart_offset = 8, | |
2639 | }, | |
bf0df636 AC |
2640 | [pbn_b0_8_115200] = { |
2641 | .flags = FL_BASE0, | |
2642 | .num_ports = 8, | |
2643 | .base_baud = 115200, | |
2644 | .uart_offset = 8, | |
2645 | }, | |
1da177e4 LT |
2646 | [pbn_b0_1_921600] = { |
2647 | .flags = FL_BASE0, | |
2648 | .num_ports = 1, | |
2649 | .base_baud = 921600, | |
2650 | .uart_offset = 8, | |
2651 | }, | |
2652 | [pbn_b0_2_921600] = { | |
2653 | .flags = FL_BASE0, | |
2654 | .num_ports = 2, | |
2655 | .base_baud = 921600, | |
2656 | .uart_offset = 8, | |
2657 | }, | |
2658 | [pbn_b0_4_921600] = { | |
2659 | .flags = FL_BASE0, | |
2660 | .num_ports = 4, | |
2661 | .base_baud = 921600, | |
2662 | .uart_offset = 8, | |
2663 | }, | |
db1de159 DR |
2664 | |
2665 | [pbn_b0_2_1130000] = { | |
2666 | .flags = FL_BASE0, | |
2667 | .num_ports = 2, | |
2668 | .base_baud = 1130000, | |
2669 | .uart_offset = 8, | |
2670 | }, | |
2671 | ||
fbc0dc0d AP |
2672 | [pbn_b0_4_1152000] = { |
2673 | .flags = FL_BASE0, | |
2674 | .num_ports = 4, | |
2675 | .base_baud = 1152000, | |
2676 | .uart_offset = 8, | |
2677 | }, | |
1da177e4 | 2678 | |
1c9c858e IA |
2679 | [pbn_b0_4_1250000] = { |
2680 | .flags = FL_BASE0, | |
2681 | .num_ports = 4, | |
2682 | .base_baud = 1250000, | |
2683 | .uart_offset = 8, | |
2684 | }, | |
2685 | ||
26e92861 GH |
2686 | [pbn_b0_2_1843200] = { |
2687 | .flags = FL_BASE0, | |
2688 | .num_ports = 2, | |
2689 | .base_baud = 1843200, | |
2690 | .uart_offset = 8, | |
2691 | }, | |
2692 | [pbn_b0_4_1843200] = { | |
2693 | .flags = FL_BASE0, | |
2694 | .num_ports = 4, | |
2695 | .base_baud = 1843200, | |
2696 | .uart_offset = 8, | |
2697 | }, | |
2698 | ||
7106b4e3 LH |
2699 | [pbn_b0_1_4000000] = { |
2700 | .flags = FL_BASE0, | |
2701 | .num_ports = 1, | |
2702 | .base_baud = 4000000, | |
2703 | .uart_offset = 8, | |
2704 | }, | |
26e92861 | 2705 | |
1da177e4 LT |
2706 | [pbn_b0_bt_1_115200] = { |
2707 | .flags = FL_BASE0|FL_BASE_BARS, | |
2708 | .num_ports = 1, | |
2709 | .base_baud = 115200, | |
2710 | .uart_offset = 8, | |
2711 | }, | |
2712 | [pbn_b0_bt_2_115200] = { | |
2713 | .flags = FL_BASE0|FL_BASE_BARS, | |
2714 | .num_ports = 2, | |
2715 | .base_baud = 115200, | |
2716 | .uart_offset = 8, | |
2717 | }, | |
ac6ec5b1 IS |
2718 | [pbn_b0_bt_4_115200] = { |
2719 | .flags = FL_BASE0|FL_BASE_BARS, | |
2720 | .num_ports = 4, | |
2721 | .base_baud = 115200, | |
2722 | .uart_offset = 8, | |
2723 | }, | |
1da177e4 LT |
2724 | [pbn_b0_bt_8_115200] = { |
2725 | .flags = FL_BASE0|FL_BASE_BARS, | |
2726 | .num_ports = 8, | |
2727 | .base_baud = 115200, | |
2728 | .uart_offset = 8, | |
2729 | }, | |
2730 | ||
2731 | [pbn_b0_bt_1_460800] = { | |
2732 | .flags = FL_BASE0|FL_BASE_BARS, | |
2733 | .num_ports = 1, | |
2734 | .base_baud = 460800, | |
2735 | .uart_offset = 8, | |
2736 | }, | |
2737 | [pbn_b0_bt_2_460800] = { | |
2738 | .flags = FL_BASE0|FL_BASE_BARS, | |
2739 | .num_ports = 2, | |
2740 | .base_baud = 460800, | |
2741 | .uart_offset = 8, | |
2742 | }, | |
2743 | [pbn_b0_bt_4_460800] = { | |
2744 | .flags = FL_BASE0|FL_BASE_BARS, | |
2745 | .num_ports = 4, | |
2746 | .base_baud = 460800, | |
2747 | .uart_offset = 8, | |
2748 | }, | |
2749 | ||
2750 | [pbn_b0_bt_1_921600] = { | |
2751 | .flags = FL_BASE0|FL_BASE_BARS, | |
2752 | .num_ports = 1, | |
2753 | .base_baud = 921600, | |
2754 | .uart_offset = 8, | |
2755 | }, | |
2756 | [pbn_b0_bt_2_921600] = { | |
2757 | .flags = FL_BASE0|FL_BASE_BARS, | |
2758 | .num_ports = 2, | |
2759 | .base_baud = 921600, | |
2760 | .uart_offset = 8, | |
2761 | }, | |
2762 | [pbn_b0_bt_4_921600] = { | |
2763 | .flags = FL_BASE0|FL_BASE_BARS, | |
2764 | .num_ports = 4, | |
2765 | .base_baud = 921600, | |
2766 | .uart_offset = 8, | |
2767 | }, | |
2768 | [pbn_b0_bt_8_921600] = { | |
2769 | .flags = FL_BASE0|FL_BASE_BARS, | |
2770 | .num_ports = 8, | |
2771 | .base_baud = 921600, | |
2772 | .uart_offset = 8, | |
2773 | }, | |
2774 | ||
2775 | [pbn_b1_1_115200] = { | |
2776 | .flags = FL_BASE1, | |
2777 | .num_ports = 1, | |
2778 | .base_baud = 115200, | |
2779 | .uart_offset = 8, | |
2780 | }, | |
2781 | [pbn_b1_2_115200] = { | |
2782 | .flags = FL_BASE1, | |
2783 | .num_ports = 2, | |
2784 | .base_baud = 115200, | |
2785 | .uart_offset = 8, | |
2786 | }, | |
2787 | [pbn_b1_4_115200] = { | |
2788 | .flags = FL_BASE1, | |
2789 | .num_ports = 4, | |
2790 | .base_baud = 115200, | |
2791 | .uart_offset = 8, | |
2792 | }, | |
2793 | [pbn_b1_8_115200] = { | |
2794 | .flags = FL_BASE1, | |
2795 | .num_ports = 8, | |
2796 | .base_baud = 115200, | |
2797 | .uart_offset = 8, | |
2798 | }, | |
04bf7e74 WP |
2799 | [pbn_b1_16_115200] = { |
2800 | .flags = FL_BASE1, | |
2801 | .num_ports = 16, | |
2802 | .base_baud = 115200, | |
2803 | .uart_offset = 8, | |
2804 | }, | |
1da177e4 LT |
2805 | |
2806 | [pbn_b1_1_921600] = { | |
2807 | .flags = FL_BASE1, | |
2808 | .num_ports = 1, | |
2809 | .base_baud = 921600, | |
2810 | .uart_offset = 8, | |
2811 | }, | |
2812 | [pbn_b1_2_921600] = { | |
2813 | .flags = FL_BASE1, | |
2814 | .num_ports = 2, | |
2815 | .base_baud = 921600, | |
2816 | .uart_offset = 8, | |
2817 | }, | |
2818 | [pbn_b1_4_921600] = { | |
2819 | .flags = FL_BASE1, | |
2820 | .num_ports = 4, | |
2821 | .base_baud = 921600, | |
2822 | .uart_offset = 8, | |
2823 | }, | |
2824 | [pbn_b1_8_921600] = { | |
2825 | .flags = FL_BASE1, | |
2826 | .num_ports = 8, | |
2827 | .base_baud = 921600, | |
2828 | .uart_offset = 8, | |
2829 | }, | |
26e92861 GH |
2830 | [pbn_b1_2_1250000] = { |
2831 | .flags = FL_BASE1, | |
2832 | .num_ports = 2, | |
2833 | .base_baud = 1250000, | |
2834 | .uart_offset = 8, | |
2835 | }, | |
1da177e4 | 2836 | |
84f8c6fc NV |
2837 | [pbn_b1_bt_1_115200] = { |
2838 | .flags = FL_BASE1|FL_BASE_BARS, | |
2839 | .num_ports = 1, | |
2840 | .base_baud = 115200, | |
2841 | .uart_offset = 8, | |
2842 | }, | |
04bf7e74 WP |
2843 | [pbn_b1_bt_2_115200] = { |
2844 | .flags = FL_BASE1|FL_BASE_BARS, | |
2845 | .num_ports = 2, | |
2846 | .base_baud = 115200, | |
2847 | .uart_offset = 8, | |
2848 | }, | |
2849 | [pbn_b1_bt_4_115200] = { | |
2850 | .flags = FL_BASE1|FL_BASE_BARS, | |
2851 | .num_ports = 4, | |
2852 | .base_baud = 115200, | |
2853 | .uart_offset = 8, | |
2854 | }, | |
84f8c6fc | 2855 | |
1da177e4 LT |
2856 | [pbn_b1_bt_2_921600] = { |
2857 | .flags = FL_BASE1|FL_BASE_BARS, | |
2858 | .num_ports = 2, | |
2859 | .base_baud = 921600, | |
2860 | .uart_offset = 8, | |
2861 | }, | |
2862 | ||
2863 | [pbn_b1_1_1382400] = { | |
2864 | .flags = FL_BASE1, | |
2865 | .num_ports = 1, | |
2866 | .base_baud = 1382400, | |
2867 | .uart_offset = 8, | |
2868 | }, | |
2869 | [pbn_b1_2_1382400] = { | |
2870 | .flags = FL_BASE1, | |
2871 | .num_ports = 2, | |
2872 | .base_baud = 1382400, | |
2873 | .uart_offset = 8, | |
2874 | }, | |
2875 | [pbn_b1_4_1382400] = { | |
2876 | .flags = FL_BASE1, | |
2877 | .num_ports = 4, | |
2878 | .base_baud = 1382400, | |
2879 | .uart_offset = 8, | |
2880 | }, | |
2881 | [pbn_b1_8_1382400] = { | |
2882 | .flags = FL_BASE1, | |
2883 | .num_ports = 8, | |
2884 | .base_baud = 1382400, | |
2885 | .uart_offset = 8, | |
2886 | }, | |
2887 | ||
2888 | [pbn_b2_1_115200] = { | |
2889 | .flags = FL_BASE2, | |
2890 | .num_ports = 1, | |
2891 | .base_baud = 115200, | |
2892 | .uart_offset = 8, | |
2893 | }, | |
737c1756 PH |
2894 | [pbn_b2_2_115200] = { |
2895 | .flags = FL_BASE2, | |
2896 | .num_ports = 2, | |
2897 | .base_baud = 115200, | |
2898 | .uart_offset = 8, | |
2899 | }, | |
a9cccd34 MF |
2900 | [pbn_b2_4_115200] = { |
2901 | .flags = FL_BASE2, | |
2902 | .num_ports = 4, | |
2903 | .base_baud = 115200, | |
2904 | .uart_offset = 8, | |
2905 | }, | |
1da177e4 LT |
2906 | [pbn_b2_8_115200] = { |
2907 | .flags = FL_BASE2, | |
2908 | .num_ports = 8, | |
2909 | .base_baud = 115200, | |
2910 | .uart_offset = 8, | |
2911 | }, | |
2912 | ||
2913 | [pbn_b2_1_460800] = { | |
2914 | .flags = FL_BASE2, | |
2915 | .num_ports = 1, | |
2916 | .base_baud = 460800, | |
2917 | .uart_offset = 8, | |
2918 | }, | |
2919 | [pbn_b2_4_460800] = { | |
2920 | .flags = FL_BASE2, | |
2921 | .num_ports = 4, | |
2922 | .base_baud = 460800, | |
2923 | .uart_offset = 8, | |
2924 | }, | |
2925 | [pbn_b2_8_460800] = { | |
2926 | .flags = FL_BASE2, | |
2927 | .num_ports = 8, | |
2928 | .base_baud = 460800, | |
2929 | .uart_offset = 8, | |
2930 | }, | |
2931 | [pbn_b2_16_460800] = { | |
2932 | .flags = FL_BASE2, | |
2933 | .num_ports = 16, | |
2934 | .base_baud = 460800, | |
2935 | .uart_offset = 8, | |
2936 | }, | |
2937 | ||
2938 | [pbn_b2_1_921600] = { | |
2939 | .flags = FL_BASE2, | |
2940 | .num_ports = 1, | |
2941 | .base_baud = 921600, | |
2942 | .uart_offset = 8, | |
2943 | }, | |
2944 | [pbn_b2_4_921600] = { | |
2945 | .flags = FL_BASE2, | |
2946 | .num_ports = 4, | |
2947 | .base_baud = 921600, | |
2948 | .uart_offset = 8, | |
2949 | }, | |
2950 | [pbn_b2_8_921600] = { | |
2951 | .flags = FL_BASE2, | |
2952 | .num_ports = 8, | |
2953 | .base_baud = 921600, | |
2954 | .uart_offset = 8, | |
2955 | }, | |
2956 | ||
e847003f LB |
2957 | [pbn_b2_8_1152000] = { |
2958 | .flags = FL_BASE2, | |
2959 | .num_ports = 8, | |
2960 | .base_baud = 1152000, | |
2961 | .uart_offset = 8, | |
2962 | }, | |
2963 | ||
1da177e4 LT |
2964 | [pbn_b2_bt_1_115200] = { |
2965 | .flags = FL_BASE2|FL_BASE_BARS, | |
2966 | .num_ports = 1, | |
2967 | .base_baud = 115200, | |
2968 | .uart_offset = 8, | |
2969 | }, | |
2970 | [pbn_b2_bt_2_115200] = { | |
2971 | .flags = FL_BASE2|FL_BASE_BARS, | |
2972 | .num_ports = 2, | |
2973 | .base_baud = 115200, | |
2974 | .uart_offset = 8, | |
2975 | }, | |
2976 | [pbn_b2_bt_4_115200] = { | |
2977 | .flags = FL_BASE2|FL_BASE_BARS, | |
2978 | .num_ports = 4, | |
2979 | .base_baud = 115200, | |
2980 | .uart_offset = 8, | |
2981 | }, | |
2982 | ||
2983 | [pbn_b2_bt_2_921600] = { | |
2984 | .flags = FL_BASE2|FL_BASE_BARS, | |
2985 | .num_ports = 2, | |
2986 | .base_baud = 921600, | |
2987 | .uart_offset = 8, | |
2988 | }, | |
2989 | [pbn_b2_bt_4_921600] = { | |
2990 | .flags = FL_BASE2|FL_BASE_BARS, | |
2991 | .num_ports = 4, | |
2992 | .base_baud = 921600, | |
2993 | .uart_offset = 8, | |
2994 | }, | |
2995 | ||
d9004eb4 ABL |
2996 | [pbn_b3_2_115200] = { |
2997 | .flags = FL_BASE3, | |
2998 | .num_ports = 2, | |
2999 | .base_baud = 115200, | |
3000 | .uart_offset = 8, | |
3001 | }, | |
1da177e4 LT |
3002 | [pbn_b3_4_115200] = { |
3003 | .flags = FL_BASE3, | |
3004 | .num_ports = 4, | |
3005 | .base_baud = 115200, | |
3006 | .uart_offset = 8, | |
3007 | }, | |
3008 | [pbn_b3_8_115200] = { | |
3009 | .flags = FL_BASE3, | |
3010 | .num_ports = 8, | |
3011 | .base_baud = 115200, | |
3012 | .uart_offset = 8, | |
3013 | }, | |
3014 | ||
66169ad1 YY |
3015 | [pbn_b4_bt_2_921600] = { |
3016 | .flags = FL_BASE4, | |
3017 | .num_ports = 2, | |
3018 | .base_baud = 921600, | |
3019 | .uart_offset = 8, | |
3020 | }, | |
3021 | [pbn_b4_bt_4_921600] = { | |
3022 | .flags = FL_BASE4, | |
3023 | .num_ports = 4, | |
3024 | .base_baud = 921600, | |
3025 | .uart_offset = 8, | |
3026 | }, | |
3027 | [pbn_b4_bt_8_921600] = { | |
3028 | .flags = FL_BASE4, | |
3029 | .num_ports = 8, | |
3030 | .base_baud = 921600, | |
3031 | .uart_offset = 8, | |
3032 | }, | |
3033 | ||
1da177e4 LT |
3034 | /* |
3035 | * Entries following this are board-specific. | |
3036 | */ | |
3037 | ||
3038 | /* | |
3039 | * Panacom - IOMEM | |
3040 | */ | |
3041 | [pbn_panacom] = { | |
3042 | .flags = FL_BASE2, | |
3043 | .num_ports = 2, | |
3044 | .base_baud = 921600, | |
3045 | .uart_offset = 0x400, | |
3046 | .reg_shift = 7, | |
3047 | }, | |
3048 | [pbn_panacom2] = { | |
3049 | .flags = FL_BASE2|FL_BASE_BARS, | |
3050 | .num_ports = 2, | |
3051 | .base_baud = 921600, | |
3052 | .uart_offset = 0x400, | |
3053 | .reg_shift = 7, | |
3054 | }, | |
3055 | [pbn_panacom4] = { | |
3056 | .flags = FL_BASE2|FL_BASE_BARS, | |
3057 | .num_ports = 4, | |
3058 | .base_baud = 921600, | |
3059 | .uart_offset = 0x400, | |
3060 | .reg_shift = 7, | |
3061 | }, | |
3062 | ||
3063 | /* I think this entry is broken - the first_offset looks wrong --rmk */ | |
3064 | [pbn_plx_romulus] = { | |
3065 | .flags = FL_BASE2, | |
3066 | .num_ports = 4, | |
3067 | .base_baud = 921600, | |
3068 | .uart_offset = 8 << 2, | |
3069 | .reg_shift = 2, | |
3070 | .first_offset = 0x03, | |
3071 | }, | |
3072 | ||
1bc8cde4 MS |
3073 | /* |
3074 | * EndRun Technologies | |
3075 | * Uses the size of PCI Base region 0 to | |
3076 | * signal now many ports are available | |
3077 | * 2 port 952 Uart support | |
3078 | */ | |
3079 | [pbn_endrun_2_4000000] = { | |
3080 | .flags = FL_BASE0, | |
3081 | .num_ports = 2, | |
3082 | .base_baud = 4000000, | |
3083 | .uart_offset = 0x200, | |
3084 | .first_offset = 0x1000, | |
3085 | }, | |
3086 | ||
1da177e4 LT |
3087 | /* |
3088 | * This board uses the size of PCI Base region 0 to | |
3089 | * signal now many ports are available | |
3090 | */ | |
3091 | [pbn_oxsemi] = { | |
3092 | .flags = FL_BASE0|FL_REGION_SZ_CAP, | |
3093 | .num_ports = 32, | |
3094 | .base_baud = 115200, | |
3095 | .uart_offset = 8, | |
3096 | }, | |
7106b4e3 LH |
3097 | [pbn_oxsemi_1_4000000] = { |
3098 | .flags = FL_BASE0, | |
3099 | .num_ports = 1, | |
3100 | .base_baud = 4000000, | |
3101 | .uart_offset = 0x200, | |
3102 | .first_offset = 0x1000, | |
3103 | }, | |
3104 | [pbn_oxsemi_2_4000000] = { | |
3105 | .flags = FL_BASE0, | |
3106 | .num_ports = 2, | |
3107 | .base_baud = 4000000, | |
3108 | .uart_offset = 0x200, | |
3109 | .first_offset = 0x1000, | |
3110 | }, | |
3111 | [pbn_oxsemi_4_4000000] = { | |
3112 | .flags = FL_BASE0, | |
3113 | .num_ports = 4, | |
3114 | .base_baud = 4000000, | |
3115 | .uart_offset = 0x200, | |
3116 | .first_offset = 0x1000, | |
3117 | }, | |
3118 | [pbn_oxsemi_8_4000000] = { | |
3119 | .flags = FL_BASE0, | |
3120 | .num_ports = 8, | |
3121 | .base_baud = 4000000, | |
3122 | .uart_offset = 0x200, | |
3123 | .first_offset = 0x1000, | |
3124 | }, | |
3125 | ||
1da177e4 LT |
3126 | |
3127 | /* | |
3128 | * EKF addition for i960 Boards form EKF with serial port. | |
3129 | * Max 256 ports. | |
3130 | */ | |
3131 | [pbn_intel_i960] = { | |
3132 | .flags = FL_BASE0, | |
3133 | .num_ports = 32, | |
3134 | .base_baud = 921600, | |
3135 | .uart_offset = 8 << 2, | |
3136 | .reg_shift = 2, | |
3137 | .first_offset = 0x10000, | |
3138 | }, | |
3139 | [pbn_sgi_ioc3] = { | |
3140 | .flags = FL_BASE0|FL_NOIRQ, | |
3141 | .num_ports = 1, | |
3142 | .base_baud = 458333, | |
3143 | .uart_offset = 8, | |
3144 | .reg_shift = 0, | |
3145 | .first_offset = 0x20178, | |
3146 | }, | |
3147 | ||
1da177e4 LT |
3148 | /* |
3149 | * Computone - uses IOMEM. | |
3150 | */ | |
3151 | [pbn_computone_4] = { | |
3152 | .flags = FL_BASE0, | |
3153 | .num_ports = 4, | |
3154 | .base_baud = 921600, | |
3155 | .uart_offset = 0x40, | |
3156 | .reg_shift = 2, | |
3157 | .first_offset = 0x200, | |
3158 | }, | |
3159 | [pbn_computone_6] = { | |
3160 | .flags = FL_BASE0, | |
3161 | .num_ports = 6, | |
3162 | .base_baud = 921600, | |
3163 | .uart_offset = 0x40, | |
3164 | .reg_shift = 2, | |
3165 | .first_offset = 0x200, | |
3166 | }, | |
3167 | [pbn_computone_8] = { | |
3168 | .flags = FL_BASE0, | |
3169 | .num_ports = 8, | |
3170 | .base_baud = 921600, | |
3171 | .uart_offset = 0x40, | |
3172 | .reg_shift = 2, | |
3173 | .first_offset = 0x200, | |
3174 | }, | |
3175 | [pbn_sbsxrsio] = { | |
3176 | .flags = FL_BASE0, | |
3177 | .num_ports = 8, | |
3178 | .base_baud = 460800, | |
3179 | .uart_offset = 256, | |
3180 | .reg_shift = 4, | |
3181 | }, | |
aa798505 OJ |
3182 | /* |
3183 | * PA Semi PWRficient PA6T-1682M on-chip UART | |
3184 | */ | |
3185 | [pbn_pasemi_1682M] = { | |
3186 | .flags = FL_BASE0, | |
3187 | .num_ports = 1, | |
3188 | .base_baud = 8333333, | |
3189 | }, | |
46a0fac9 SB |
3190 | /* |
3191 | * National Instruments 843x | |
3192 | */ | |
3193 | [pbn_ni8430_16] = { | |
3194 | .flags = FL_BASE0, | |
3195 | .num_ports = 16, | |
3196 | .base_baud = 3686400, | |
3197 | .uart_offset = 0x10, | |
3198 | .first_offset = 0x800, | |
3199 | }, | |
3200 | [pbn_ni8430_8] = { | |
3201 | .flags = FL_BASE0, | |
3202 | .num_ports = 8, | |
3203 | .base_baud = 3686400, | |
3204 | .uart_offset = 0x10, | |
3205 | .first_offset = 0x800, | |
3206 | }, | |
3207 | [pbn_ni8430_4] = { | |
3208 | .flags = FL_BASE0, | |
3209 | .num_ports = 4, | |
3210 | .base_baud = 3686400, | |
3211 | .uart_offset = 0x10, | |
3212 | .first_offset = 0x800, | |
3213 | }, | |
3214 | [pbn_ni8430_2] = { | |
3215 | .flags = FL_BASE0, | |
3216 | .num_ports = 2, | |
3217 | .base_baud = 3686400, | |
3218 | .uart_offset = 0x10, | |
3219 | .first_offset = 0x800, | |
3220 | }, | |
1b62cbf2 KJ |
3221 | /* |
3222 | * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> | |
3223 | */ | |
3224 | [pbn_ADDIDATA_PCIe_1_3906250] = { | |
3225 | .flags = FL_BASE0, | |
3226 | .num_ports = 1, | |
3227 | .base_baud = 3906250, | |
3228 | .uart_offset = 0x200, | |
3229 | .first_offset = 0x1000, | |
3230 | }, | |
3231 | [pbn_ADDIDATA_PCIe_2_3906250] = { | |
3232 | .flags = FL_BASE0, | |
3233 | .num_ports = 2, | |
3234 | .base_baud = 3906250, | |
3235 | .uart_offset = 0x200, | |
3236 | .first_offset = 0x1000, | |
3237 | }, | |
3238 | [pbn_ADDIDATA_PCIe_4_3906250] = { | |
3239 | .flags = FL_BASE0, | |
3240 | .num_ports = 4, | |
3241 | .base_baud = 3906250, | |
3242 | .uart_offset = 0x200, | |
3243 | .first_offset = 0x1000, | |
3244 | }, | |
3245 | [pbn_ADDIDATA_PCIe_8_3906250] = { | |
3246 | .flags = FL_BASE0, | |
3247 | .num_ports = 8, | |
3248 | .base_baud = 3906250, | |
3249 | .uart_offset = 0x200, | |
3250 | .first_offset = 0x1000, | |
3251 | }, | |
095e24b0 | 3252 | [pbn_ce4100_1_115200] = { |
08ec212c MB |
3253 | .flags = FL_BASE_BARS, |
3254 | .num_ports = 2, | |
095e24b0 DB |
3255 | .base_baud = 921600, |
3256 | .reg_shift = 2, | |
3257 | }, | |
d9a0fbfd AP |
3258 | [pbn_omegapci] = { |
3259 | .flags = FL_BASE0, | |
3260 | .num_ports = 8, | |
3261 | .base_baud = 115200, | |
3262 | .uart_offset = 0x200, | |
3263 | }, | |
7808edcd NG |
3264 | [pbn_NETMOS9900_2s_115200] = { |
3265 | .flags = FL_BASE0, | |
3266 | .num_ports = 2, | |
3267 | .base_baud = 115200, | |
3268 | }, | |
ebebd49a SH |
3269 | [pbn_brcm_trumanage] = { |
3270 | .flags = FL_BASE0, | |
3271 | .num_ports = 1, | |
3272 | .reg_shift = 2, | |
3273 | .base_baud = 115200, | |
3274 | }, | |
2c62a3c8 GKH |
3275 | [pbn_fintek_4] = { |
3276 | .num_ports = 4, | |
3277 | .uart_offset = 8, | |
3278 | .base_baud = 115200, | |
3279 | .first_offset = 0x40, | |
3280 | }, | |
3281 | [pbn_fintek_8] = { | |
3282 | .num_ports = 8, | |
3283 | .uart_offset = 8, | |
3284 | .base_baud = 115200, | |
3285 | .first_offset = 0x40, | |
3286 | }, | |
3287 | [pbn_fintek_12] = { | |
3288 | .num_ports = 12, | |
3289 | .uart_offset = 8, | |
3290 | .base_baud = 115200, | |
3291 | .first_offset = 0x40, | |
3292 | }, | |
7dde5578 JM |
3293 | [pbn_wch382_2] = { |
3294 | .flags = FL_BASE0, | |
3295 | .num_ports = 2, | |
3296 | .base_baud = 115200, | |
3297 | .uart_offset = 8, | |
3298 | .first_offset = 0xC0, | |
3299 | }, | |
72a3c0e4 SP |
3300 | [pbn_wch384_4] = { |
3301 | .flags = FL_BASE0, | |
3302 | .num_ports = 4, | |
3303 | .base_baud = 115200, | |
3304 | .uart_offset = 8, | |
3305 | .first_offset = 0xC0, | |
3306 | }, | |
89c043a6 AL |
3307 | /* |
3308 | * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART | |
3309 | */ | |
3310 | [pbn_pericom_PI7C9X7951] = { | |
3311 | .flags = FL_BASE0, | |
3312 | .num_ports = 1, | |
3313 | .base_baud = 921600, | |
3314 | .uart_offset = 0x8, | |
3315 | }, | |
3316 | [pbn_pericom_PI7C9X7952] = { | |
3317 | .flags = FL_BASE0, | |
3318 | .num_ports = 2, | |
3319 | .base_baud = 921600, | |
3320 | .uart_offset = 0x8, | |
3321 | }, | |
3322 | [pbn_pericom_PI7C9X7954] = { | |
3323 | .flags = FL_BASE0, | |
3324 | .num_ports = 4, | |
3325 | .base_baud = 921600, | |
3326 | .uart_offset = 0x8, | |
3327 | }, | |
3328 | [pbn_pericom_PI7C9X7958] = { | |
3329 | .flags = FL_BASE0, | |
3330 | .num_ports = 8, | |
3331 | .base_baud = 921600, | |
3332 | .uart_offset = 0x8, | |
3333 | }, | |
1da177e4 LT |
3334 | }; |
3335 | ||
6971c635 GA |
3336 | static const struct pci_device_id blacklist[] = { |
3337 | /* softmodems */ | |
5756ee99 | 3338 | { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ |
ebf7c066 MS |
3339 | { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ |
3340 | { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ | |
6971c635 GA |
3341 | |
3342 | /* multi-io cards handled by parport_serial */ | |
3343 | { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */ | |
feb58142 | 3344 | { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */ |
55c368cb | 3345 | { PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */ |
2fdd8c8c | 3346 | { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */ |
72a3c0e4 | 3347 | { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */ |
d9eda9ba | 3348 | |
c216c4ad MO |
3349 | /* Moxa Smartio MUE boards handled by 8250_moxa */ |
3350 | { PCI_VDEVICE(MOXA, 0x1024), }, | |
3351 | { PCI_VDEVICE(MOXA, 0x1025), }, | |
3352 | { PCI_VDEVICE(MOXA, 0x1045), }, | |
3353 | { PCI_VDEVICE(MOXA, 0x1144), }, | |
3354 | { PCI_VDEVICE(MOXA, 0x1160), }, | |
3355 | { PCI_VDEVICE(MOXA, 0x1161), }, | |
3356 | { PCI_VDEVICE(MOXA, 0x1182), }, | |
3357 | { PCI_VDEVICE(MOXA, 0x1183), }, | |
3358 | { PCI_VDEVICE(MOXA, 0x1322), }, | |
3359 | { PCI_VDEVICE(MOXA, 0x1342), }, | |
3360 | { PCI_VDEVICE(MOXA, 0x1381), }, | |
3361 | { PCI_VDEVICE(MOXA, 0x1683), }, | |
3362 | ||
d9eda9ba HK |
3363 | /* Intel platforms with MID UART */ |
3364 | { PCI_VDEVICE(INTEL, 0x081b), }, | |
3365 | { PCI_VDEVICE(INTEL, 0x081c), }, | |
3366 | { PCI_VDEVICE(INTEL, 0x081d), }, | |
3367 | { PCI_VDEVICE(INTEL, 0x1191), }, | |
daf3930c | 3368 | { PCI_VDEVICE(INTEL, 0x18d8), }, |
6ede6dcd | 3369 | { PCI_VDEVICE(INTEL, 0x19d8), }, |
a13e19cf AS |
3370 | |
3371 | /* Intel platforms with DesignWare UART */ | |
6bb5d75e | 3372 | { PCI_VDEVICE(INTEL, 0x0936), }, |
a13e19cf AS |
3373 | { PCI_VDEVICE(INTEL, 0x0f0a), }, |
3374 | { PCI_VDEVICE(INTEL, 0x0f0c), }, | |
3375 | { PCI_VDEVICE(INTEL, 0x228a), }, | |
3376 | { PCI_VDEVICE(INTEL, 0x228c), }, | |
3377 | { PCI_VDEVICE(INTEL, 0x9ce3), }, | |
3378 | { PCI_VDEVICE(INTEL, 0x9ce4), }, | |
5d1a2388 SM |
3379 | |
3380 | /* Exar devices */ | |
3381 | { PCI_VDEVICE(EXAR, PCI_ANY_ID), }, | |
fc6cc961 | 3382 | { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), }, |
436bbd43 CS |
3383 | }; |
3384 | ||
7d8905d0 | 3385 | static int serial_pci_is_class_communication(struct pci_dev *dev) |
1da177e4 | 3386 | { |
1da177e4 LT |
3387 | /* |
3388 | * If it is not a communications device or the programming | |
3389 | * interface is greater than 6, give up. | |
3390 | * | |
3391 | * (Should we try to make guesses for multiport serial devices | |
5756ee99 | 3392 | * later?) |
1da177e4 LT |
3393 | */ |
3394 | if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && | |
3395 | ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || | |
3396 | (dev->class & 0xff) > 6) | |
3397 | return -ENODEV; | |
3398 | ||
7d8905d0 AS |
3399 | return 0; |
3400 | } | |
3401 | ||
3402 | static int serial_pci_is_blacklisted(struct pci_dev *dev) | |
3403 | { | |
3404 | const struct pci_device_id *bldev; | |
3405 | ||
436bbd43 CS |
3406 | /* |
3407 | * Do not access blacklisted devices that are known not to | |
6971c635 | 3408 | * feature serial ports or are handled by other modules. |
436bbd43 | 3409 | */ |
6971c635 GA |
3410 | for (bldev = blacklist; |
3411 | bldev < blacklist + ARRAY_SIZE(blacklist); | |
3412 | bldev++) { | |
3413 | if (dev->vendor == bldev->vendor && | |
3414 | dev->device == bldev->device) | |
436bbd43 CS |
3415 | return -ENODEV; |
3416 | } | |
3417 | ||
7d8905d0 AS |
3418 | return 0; |
3419 | } | |
3420 | ||
3421 | /* | |
3422 | * Given a complete unknown PCI device, try to use some heuristics to | |
3423 | * guess what the configuration might be, based on the pitiful PCI | |
3424 | * serial specs. Returns 0 on success, -ENODEV on failure. | |
3425 | */ | |
3426 | static int | |
3427 | serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) | |
3428 | { | |
3429 | int num_iomem, num_port, first_port = -1, i; | |
3430 | ||
1da177e4 LT |
3431 | num_iomem = num_port = 0; |
3432 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | |
3433 | if (pci_resource_flags(dev, i) & IORESOURCE_IO) { | |
3434 | num_port++; | |
3435 | if (first_port == -1) | |
3436 | first_port = i; | |
3437 | } | |
3438 | if (pci_resource_flags(dev, i) & IORESOURCE_MEM) | |
3439 | num_iomem++; | |
3440 | } | |
3441 | ||
3442 | /* | |
3443 | * If there is 1 or 0 iomem regions, and exactly one port, | |
3444 | * use it. We guess the number of ports based on the IO | |
3445 | * region size. | |
3446 | */ | |
3447 | if (num_iomem <= 1 && num_port == 1) { | |
3448 | board->flags = first_port; | |
3449 | board->num_ports = pci_resource_len(dev, first_port) / 8; | |
3450 | return 0; | |
3451 | } | |
3452 | ||
3453 | /* | |
3454 | * Now guess if we've got a board which indexes by BARs. | |
3455 | * Each IO BAR should be 8 bytes, and they should follow | |
3456 | * consecutively. | |
3457 | */ | |
3458 | first_port = -1; | |
3459 | num_port = 0; | |
3460 | for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) { | |
3461 | if (pci_resource_flags(dev, i) & IORESOURCE_IO && | |
3462 | pci_resource_len(dev, i) == 8 && | |
3463 | (first_port == -1 || (first_port + num_port) == i)) { | |
3464 | num_port++; | |
3465 | if (first_port == -1) | |
3466 | first_port = i; | |
3467 | } | |
3468 | } | |
3469 | ||
3470 | if (num_port > 1) { | |
3471 | board->flags = first_port | FL_BASE_BARS; | |
3472 | board->num_ports = num_port; | |
3473 | return 0; | |
3474 | } | |
3475 | ||
3476 | return -ENODEV; | |
3477 | } | |
3478 | ||
3479 | static inline int | |
975a1a7d RK |
3480 | serial_pci_matches(const struct pciserial_board *board, |
3481 | const struct pciserial_board *guessed) | |
1da177e4 LT |
3482 | { |
3483 | return | |
3484 | board->num_ports == guessed->num_ports && | |
3485 | board->base_baud == guessed->base_baud && | |
3486 | board->uart_offset == guessed->uart_offset && | |
3487 | board->reg_shift == guessed->reg_shift && | |
3488 | board->first_offset == guessed->first_offset; | |
3489 | } | |
3490 | ||
241fc436 | 3491 | struct serial_private * |
975a1a7d | 3492 | pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) |
1da177e4 | 3493 | { |
2655a2c7 | 3494 | struct uart_8250_port uart; |
1da177e4 | 3495 | struct serial_private *priv; |
1da177e4 LT |
3496 | struct pci_serial_quirk *quirk; |
3497 | int rc, nr_ports, i; | |
3498 | ||
1da177e4 LT |
3499 | nr_ports = board->num_ports; |
3500 | ||
3501 | /* | |
3502 | * Find an init and setup quirks. | |
3503 | */ | |
3504 | quirk = find_quirk(dev); | |
3505 | ||
3506 | /* | |
3507 | * Run the new-style initialization function. | |
3508 | * The initialization function returns: | |
3509 | * <0 - error | |
3510 | * 0 - use board->num_ports | |
3511 | * >0 - number of ports | |
3512 | */ | |
3513 | if (quirk->init) { | |
3514 | rc = quirk->init(dev); | |
241fc436 RK |
3515 | if (rc < 0) { |
3516 | priv = ERR_PTR(rc); | |
3517 | goto err_out; | |
3518 | } | |
1da177e4 LT |
3519 | if (rc) |
3520 | nr_ports = rc; | |
3521 | } | |
3522 | ||
8f31bb39 | 3523 | priv = kzalloc(sizeof(struct serial_private) + |
1da177e4 LT |
3524 | sizeof(unsigned int) * nr_ports, |
3525 | GFP_KERNEL); | |
3526 | if (!priv) { | |
241fc436 RK |
3527 | priv = ERR_PTR(-ENOMEM); |
3528 | goto err_deinit; | |
1da177e4 LT |
3529 | } |
3530 | ||
70db3d91 | 3531 | priv->dev = dev; |
1da177e4 | 3532 | priv->quirk = quirk; |
1da177e4 | 3533 | |
2655a2c7 AC |
3534 | memset(&uart, 0, sizeof(uart)); |
3535 | uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; | |
3536 | uart.port.uartclk = board->base_baud * 16; | |
3537 | uart.port.irq = get_pci_irq(dev, board); | |
3538 | uart.port.dev = &dev->dev; | |
72ce9a83 | 3539 | |
1da177e4 | 3540 | for (i = 0; i < nr_ports; i++) { |
2655a2c7 | 3541 | if (quirk->setup(priv, board, &uart, i)) |
1da177e4 | 3542 | break; |
72ce9a83 | 3543 | |
af8c5b8d GKH |
3544 | dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n", |
3545 | uart.port.iobase, uart.port.irq, uart.port.iotype); | |
5756ee99 | 3546 | |
2655a2c7 | 3547 | priv->line[i] = serial8250_register_8250_port(&uart); |
1da177e4 | 3548 | if (priv->line[i] < 0) { |
af8c5b8d GKH |
3549 | dev_err(&dev->dev, |
3550 | "Couldn't register serial port %lx, irq %d, type %d, error %d\n", | |
3551 | uart.port.iobase, uart.port.irq, | |
3552 | uart.port.iotype, priv->line[i]); | |
1da177e4 LT |
3553 | break; |
3554 | } | |
3555 | } | |
1da177e4 | 3556 | priv->nr = i; |
f209fa03 | 3557 | priv->board = board; |
241fc436 | 3558 | return priv; |
1da177e4 | 3559 | |
5756ee99 | 3560 | err_deinit: |
1da177e4 LT |
3561 | if (quirk->exit) |
3562 | quirk->exit(dev); | |
5756ee99 | 3563 | err_out: |
241fc436 | 3564 | return priv; |
1da177e4 | 3565 | } |
241fc436 | 3566 | EXPORT_SYMBOL_GPL(pciserial_init_ports); |
1da177e4 | 3567 | |
80cd94e7 | 3568 | static void pciserial_detach_ports(struct serial_private *priv) |
1da177e4 | 3569 | { |
056a8763 RK |
3570 | struct pci_serial_quirk *quirk; |
3571 | int i; | |
1da177e4 | 3572 | |
056a8763 RK |
3573 | for (i = 0; i < priv->nr; i++) |
3574 | serial8250_unregister_port(priv->line[i]); | |
1da177e4 | 3575 | |
056a8763 RK |
3576 | /* |
3577 | * Find the exit quirks. | |
3578 | */ | |
241fc436 | 3579 | quirk = find_quirk(priv->dev); |
056a8763 | 3580 | if (quirk->exit) |
241fc436 | 3581 | quirk->exit(priv->dev); |
f209fa03 | 3582 | } |
241fc436 | 3583 | |
f209fa03 GKB |
3584 | void pciserial_remove_ports(struct serial_private *priv) |
3585 | { | |
3586 | pciserial_detach_ports(priv); | |
241fc436 RK |
3587 | kfree(priv); |
3588 | } | |
3589 | EXPORT_SYMBOL_GPL(pciserial_remove_ports); | |
3590 | ||
3591 | void pciserial_suspend_ports(struct serial_private *priv) | |
3592 | { | |
3593 | int i; | |
3594 | ||
3595 | for (i = 0; i < priv->nr; i++) | |
3596 | if (priv->line[i] >= 0) | |
3597 | serial8250_suspend_port(priv->line[i]); | |
5f1a3895 DW |
3598 | |
3599 | /* | |
3600 | * Ensure that every init quirk is properly torn down | |
3601 | */ | |
3602 | if (priv->quirk->exit) | |
3603 | priv->quirk->exit(priv->dev); | |
241fc436 RK |
3604 | } |
3605 | EXPORT_SYMBOL_GPL(pciserial_suspend_ports); | |
3606 | ||
3607 | void pciserial_resume_ports(struct serial_private *priv) | |
3608 | { | |
3609 | int i; | |
3610 | ||
3611 | /* | |
3612 | * Ensure that the board is correctly configured. | |
3613 | */ | |
3614 | if (priv->quirk->init) | |
3615 | priv->quirk->init(priv->dev); | |
3616 | ||
3617 | for (i = 0; i < priv->nr; i++) | |
3618 | if (priv->line[i] >= 0) | |
3619 | serial8250_resume_port(priv->line[i]); | |
3620 | } | |
3621 | EXPORT_SYMBOL_GPL(pciserial_resume_ports); | |
3622 | ||
3623 | /* | |
3624 | * Probe one serial board. Unfortunately, there is no rhyme nor reason | |
3625 | * to the arrangement of serial ports on a PCI card. | |
3626 | */ | |
9671f099 | 3627 | static int |
241fc436 RK |
3628 | pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) |
3629 | { | |
5bf8f501 | 3630 | struct pci_serial_quirk *quirk; |
241fc436 | 3631 | struct serial_private *priv; |
975a1a7d RK |
3632 | const struct pciserial_board *board; |
3633 | struct pciserial_board tmp; | |
241fc436 RK |
3634 | int rc; |
3635 | ||
5bf8f501 FB |
3636 | quirk = find_quirk(dev); |
3637 | if (quirk->probe) { | |
3638 | rc = quirk->probe(dev); | |
3639 | if (rc) | |
3640 | return rc; | |
3641 | } | |
3642 | ||
241fc436 | 3643 | if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { |
af8c5b8d | 3644 | dev_err(&dev->dev, "invalid driver_data: %ld\n", |
241fc436 RK |
3645 | ent->driver_data); |
3646 | return -EINVAL; | |
3647 | } | |
3648 | ||
3649 | board = &pci_boards[ent->driver_data]; | |
3650 | ||
7d8905d0 AS |
3651 | rc = serial_pci_is_class_communication(dev); |
3652 | if (rc) | |
3653 | return rc; | |
3654 | ||
3655 | rc = serial_pci_is_blacklisted(dev); | |
3656 | if (rc) | |
3657 | return rc; | |
3658 | ||
3f64b1d3 | 3659 | rc = pcim_enable_device(dev); |
2807190b | 3660 | pci_save_state(dev); |
241fc436 RK |
3661 | if (rc) |
3662 | return rc; | |
3663 | ||
3664 | if (ent->driver_data == pbn_default) { | |
3665 | /* | |
3666 | * Use a copy of the pci_board entry for this; | |
3667 | * avoid changing entries in the table. | |
3668 | */ | |
3669 | memcpy(&tmp, board, sizeof(struct pciserial_board)); | |
3670 | board = &tmp; | |
3671 | ||
3672 | /* | |
3673 | * We matched one of our class entries. Try to | |
3674 | * determine the parameters of this board. | |
3675 | */ | |
975a1a7d | 3676 | rc = serial_pci_guess_board(dev, &tmp); |
241fc436 | 3677 | if (rc) |
3f64b1d3 | 3678 | return rc; |
241fc436 RK |
3679 | } else { |
3680 | /* | |
3681 | * We matched an explicit entry. If we are able to | |
3682 | * detect this boards settings with our heuristic, | |
3683 | * then we no longer need this entry. | |
3684 | */ | |
3685 | memcpy(&tmp, &pci_boards[pbn_default], | |
3686 | sizeof(struct pciserial_board)); | |
3687 | rc = serial_pci_guess_board(dev, &tmp); | |
3688 | if (rc == 0 && serial_pci_matches(board, &tmp)) | |
3689 | moan_device("Redundant entry in serial pci_table.", | |
3690 | dev); | |
3691 | } | |
3692 | ||
3693 | priv = pciserial_init_ports(dev, board); | |
3f64b1d3 AS |
3694 | if (IS_ERR(priv)) |
3695 | return PTR_ERR(priv); | |
1da177e4 | 3696 | |
3f64b1d3 AS |
3697 | pci_set_drvdata(dev, priv); |
3698 | return 0; | |
241fc436 | 3699 | } |
1da177e4 | 3700 | |
ae8d8a14 | 3701 | static void pciserial_remove_one(struct pci_dev *dev) |
241fc436 RK |
3702 | { |
3703 | struct serial_private *priv = pci_get_drvdata(dev); | |
3704 | ||
241fc436 | 3705 | pciserial_remove_ports(priv); |
1da177e4 LT |
3706 | } |
3707 | ||
61702c3e AS |
3708 | #ifdef CONFIG_PM_SLEEP |
3709 | static int pciserial_suspend_one(struct device *dev) | |
1da177e4 | 3710 | { |
61702c3e AS |
3711 | struct pci_dev *pdev = to_pci_dev(dev); |
3712 | struct serial_private *priv = pci_get_drvdata(pdev); | |
1da177e4 | 3713 | |
241fc436 RK |
3714 | if (priv) |
3715 | pciserial_suspend_ports(priv); | |
1da177e4 | 3716 | |
1da177e4 LT |
3717 | return 0; |
3718 | } | |
3719 | ||
61702c3e | 3720 | static int pciserial_resume_one(struct device *dev) |
1da177e4 | 3721 | { |
61702c3e AS |
3722 | struct pci_dev *pdev = to_pci_dev(dev); |
3723 | struct serial_private *priv = pci_get_drvdata(pdev); | |
ccb9d59e | 3724 | int err; |
1da177e4 LT |
3725 | |
3726 | if (priv) { | |
1da177e4 LT |
3727 | /* |
3728 | * The device may have been disabled. Re-enable it. | |
3729 | */ | |
61702c3e | 3730 | err = pci_enable_device(pdev); |
40836c48 | 3731 | /* FIXME: We cannot simply error out here */ |
ccb9d59e | 3732 | if (err) |
61702c3e | 3733 | dev_err(dev, "Unable to re-enable ports, trying to continue.\n"); |
241fc436 | 3734 | pciserial_resume_ports(priv); |
1da177e4 LT |
3735 | } |
3736 | return 0; | |
3737 | } | |
1d5e7996 | 3738 | #endif |
1da177e4 | 3739 | |
61702c3e AS |
3740 | static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, |
3741 | pciserial_resume_one); | |
3742 | ||
c40f716a | 3743 | static const struct pci_device_id serial_pci_tbl[] = { |
78d70d48 MB |
3744 | /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ |
3745 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, | |
3746 | PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0, | |
3747 | pbn_b2_8_921600 }, | |
0c6d774c TW |
3748 | /* Advantech also use 0x3618 and 0xf618 */ |
3749 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, | |
3750 | PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, | |
3751 | pbn_b0_4_921600 }, | |
3752 | { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, | |
3753 | PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0, | |
3754 | pbn_b0_4_921600 }, | |
1da177e4 LT |
3755 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, |
3756 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3757 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, | |
3758 | pbn_b1_8_1382400 }, | |
3759 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | |
3760 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3761 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, | |
3762 | pbn_b1_4_1382400 }, | |
3763 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960, | |
3764 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3765 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, | |
3766 | pbn_b1_2_1382400 }, | |
3767 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
3768 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3769 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0, | |
3770 | pbn_b1_8_1382400 }, | |
3771 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
3772 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3773 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0, | |
3774 | pbn_b1_4_1382400 }, | |
3775 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
3776 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3777 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0, | |
3778 | pbn_b1_2_1382400 }, | |
3779 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
3780 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3781 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0, | |
3782 | pbn_b1_8_921600 }, | |
3783 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
3784 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3785 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0, | |
3786 | pbn_b1_8_921600 }, | |
3787 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
3788 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3789 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0, | |
3790 | pbn_b1_4_921600 }, | |
3791 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
3792 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3793 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0, | |
3794 | pbn_b1_4_921600 }, | |
3795 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
3796 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3797 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0, | |
3798 | pbn_b1_2_921600 }, | |
3799 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
3800 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3801 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0, | |
3802 | pbn_b1_8_921600 }, | |
3803 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
3804 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3805 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0, | |
3806 | pbn_b1_8_921600 }, | |
3807 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, | |
3808 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3809 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0, | |
3810 | pbn_b1_4_921600 }, | |
26e92861 GH |
3811 | { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351, |
3812 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3813 | PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0, | |
3814 | pbn_b1_2_1250000 }, | |
3815 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | |
3816 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3817 | PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0, | |
3818 | pbn_b0_2_1843200 }, | |
3819 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, | |
3820 | PCI_SUBVENDOR_ID_CONNECT_TECH, | |
3821 | PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0, | |
3822 | pbn_b0_4_1843200 }, | |
85d1494e YY |
3823 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
3824 | PCI_VENDOR_ID_AFAVLAB, | |
3825 | PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0, | |
3826 | pbn_b0_4_1152000 }, | |
1da177e4 | 3827 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530, |
5756ee99 | 3828 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 LT |
3829 | pbn_b2_bt_1_115200 }, |
3830 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2, | |
5756ee99 | 3831 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 LT |
3832 | pbn_b2_bt_2_115200 }, |
3833 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422, | |
5756ee99 | 3834 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 LT |
3835 | pbn_b2_bt_4_115200 }, |
3836 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232, | |
5756ee99 | 3837 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 LT |
3838 | pbn_b2_bt_2_115200 }, |
3839 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4, | |
5756ee99 | 3840 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 LT |
3841 | pbn_b2_bt_4_115200 }, |
3842 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8, | |
5756ee99 | 3843 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 | 3844 | pbn_b2_8_115200 }, |
e65f0f82 FL |
3845 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803, |
3846 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3847 | pbn_b2_8_460800 }, | |
1da177e4 LT |
3848 | { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8, |
3849 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3850 | pbn_b2_8_115200 }, | |
3851 | ||
3852 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2, | |
3853 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3854 | pbn_b2_bt_2_115200 }, | |
3855 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200, | |
3856 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3857 | pbn_b2_bt_2_921600 }, | |
3858 | /* | |
3859 | * VScom SPCOM800, from sl@s.pl | |
3860 | */ | |
5756ee99 AC |
3861 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800, |
3862 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
1da177e4 LT |
3863 | pbn_b2_8_921600 }, |
3864 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077, | |
5756ee99 | 3865 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 | 3866 | pbn_b2_4_921600 }, |
b76c5a07 CB |
3867 | /* Unknown card - subdevice 0x1584 */ |
3868 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
3869 | PCI_VENDOR_ID_PLX, | |
3870 | PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0, | |
d13402a4 SA |
3871 | pbn_b2_4_115200 }, |
3872 | /* Unknown card - subdevice 0x1588 */ | |
3873 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
3874 | PCI_VENDOR_ID_PLX, | |
3875 | PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0, | |
3876 | pbn_b2_8_115200 }, | |
1da177e4 LT |
3877 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
3878 | PCI_SUBVENDOR_ID_KEYSPAN, | |
3879 | PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0, | |
3880 | pbn_panacom }, | |
3881 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM, | |
3882 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3883 | pbn_panacom4 }, | |
3884 | { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM, | |
3885 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3886 | pbn_panacom2 }, | |
a9cccd34 MF |
3887 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, |
3888 | PCI_VENDOR_ID_ESDGMBH, | |
3889 | PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0, | |
3890 | pbn_b2_4_115200 }, | |
1da177e4 LT |
3891 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
3892 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
5756ee99 | 3893 | PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0, |
1da177e4 LT |
3894 | pbn_b2_4_460800 }, |
3895 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
3896 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
5756ee99 | 3897 | PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0, |
1da177e4 LT |
3898 | pbn_b2_8_460800 }, |
3899 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
3900 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
5756ee99 | 3901 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0, |
1da177e4 LT |
3902 | pbn_b2_16_460800 }, |
3903 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
3904 | PCI_SUBVENDOR_ID_CHASE_PCIFAST, | |
5756ee99 | 3905 | PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0, |
1da177e4 LT |
3906 | pbn_b2_16_460800 }, |
3907 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
3908 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, | |
5756ee99 | 3909 | PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0, |
1da177e4 LT |
3910 | pbn_b2_4_460800 }, |
3911 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, | |
3912 | PCI_SUBVENDOR_ID_CHASE_PCIRAS, | |
5756ee99 | 3913 | PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0, |
1da177e4 | 3914 | pbn_b2_8_460800 }, |
add7b58e BH |
3915 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, |
3916 | PCI_SUBVENDOR_ID_EXSYS, | |
3917 | PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0, | |
ee4cd1b2 | 3918 | pbn_b2_4_115200 }, |
1da177e4 LT |
3919 | /* |
3920 | * Megawolf Romulus PCI Serial Card, from Mike Hudson | |
3921 | * (Exoray@isys.ca) | |
3922 | */ | |
3923 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS, | |
3924 | 0x10b5, 0x106a, 0, 0, | |
3925 | pbn_plx_romulus }, | |
1bc8cde4 MS |
3926 | /* |
3927 | * EndRun Technologies. PCI express device range. | |
3928 | * EndRun PTP/1588 has 2 Native UARTs. | |
3929 | */ | |
3930 | { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588, | |
3931 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3932 | pbn_endrun_2_4000000 }, | |
55c7c0fd AC |
3933 | /* |
3934 | * Quatech cards. These actually have configurable clocks but for | |
3935 | * now we just use the default. | |
3936 | * | |
3937 | * 100 series are RS232, 200 series RS422, | |
3938 | */ | |
1da177e4 LT |
3939 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100, |
3940 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3941 | pbn_b1_4_115200 }, | |
3942 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100, | |
3943 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3944 | pbn_b1_2_115200 }, | |
55c7c0fd AC |
3945 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E, |
3946 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3947 | pbn_b2_2_115200 }, | |
3948 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200, | |
3949 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3950 | pbn_b1_2_115200 }, | |
3951 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E, | |
3952 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3953 | pbn_b2_2_115200 }, | |
3954 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200, | |
3955 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3956 | pbn_b1_4_115200 }, | |
1da177e4 LT |
3957 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D, |
3958 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3959 | pbn_b1_8_115200 }, | |
3960 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M, | |
3961 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3962 | pbn_b1_8_115200 }, | |
55c7c0fd AC |
3963 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100, |
3964 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3965 | pbn_b1_4_115200 }, | |
3966 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100, | |
3967 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3968 | pbn_b1_2_115200 }, | |
3969 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200, | |
3970 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3971 | pbn_b1_4_115200 }, | |
3972 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200, | |
3973 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3974 | pbn_b1_2_115200 }, | |
3975 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100, | |
3976 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3977 | pbn_b2_4_115200 }, | |
3978 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100, | |
3979 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3980 | pbn_b2_2_115200 }, | |
3981 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100, | |
3982 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3983 | pbn_b2_1_115200 }, | |
3984 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200, | |
3985 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3986 | pbn_b2_4_115200 }, | |
3987 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200, | |
3988 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3989 | pbn_b2_2_115200 }, | |
3990 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200, | |
3991 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3992 | pbn_b2_1_115200 }, | |
3993 | { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100, | |
3994 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
3995 | pbn_b0_8_115200 }, | |
3996 | ||
1da177e4 | 3997 | { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, |
5756ee99 AC |
3998 | PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, |
3999 | 0, 0, | |
1da177e4 | 4000 | pbn_b0_4_921600 }, |
fbc0dc0d | 4001 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
5756ee99 AC |
4002 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, |
4003 | 0, 0, | |
fbc0dc0d | 4004 | pbn_b0_4_1152000 }, |
c9bd9d01 MP |
4005 | { PCI_VENDOR_ID_OXSEMI, 0x9505, |
4006 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4007 | pbn_b0_bt_2_921600 }, | |
db1de159 DR |
4008 | |
4009 | /* | |
4010 | * The below card is a little controversial since it is the | |
4011 | * subject of a PCI vendor/device ID clash. (See | |
4012 | * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). | |
4013 | * For now just used the hex ID 0x950a. | |
4014 | */ | |
39aced68 | 4015 | { PCI_VENDOR_ID_OXSEMI, 0x950a, |
26e8220a FL |
4016 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00, |
4017 | 0, 0, pbn_b0_2_115200 }, | |
4018 | { PCI_VENDOR_ID_OXSEMI, 0x950a, | |
4019 | PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30, | |
4020 | 0, 0, pbn_b0_2_115200 }, | |
db1de159 DR |
4021 | { PCI_VENDOR_ID_OXSEMI, 0x950a, |
4022 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4023 | pbn_b0_2_1130000 }, | |
70fd8fde AP |
4024 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, |
4025 | PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0, | |
4026 | pbn_b0_1_921600 }, | |
1da177e4 LT |
4027 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, |
4028 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4029 | pbn_b0_4_115200 }, | |
4030 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952, | |
4031 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4032 | pbn_b0_bt_2_921600 }, | |
e847003f | 4033 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958, |
1a33e342 | 4034 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
e847003f | 4035 | pbn_b2_8_1152000 }, |
1da177e4 | 4036 | |
7106b4e3 LH |
4037 | /* |
4038 | * Oxford Semiconductor Inc. Tornado PCI express device range. | |
4039 | */ | |
4040 | { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */ | |
4041 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4042 | pbn_b0_1_4000000 }, | |
4043 | { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */ | |
4044 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4045 | pbn_b0_1_4000000 }, | |
4046 | { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */ | |
4047 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4048 | pbn_oxsemi_1_4000000 }, | |
4049 | { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */ | |
4050 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4051 | pbn_oxsemi_1_4000000 }, | |
4052 | { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */ | |
4053 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4054 | pbn_b0_1_4000000 }, | |
4055 | { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */ | |
4056 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4057 | pbn_b0_1_4000000 }, | |
4058 | { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */ | |
4059 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4060 | pbn_oxsemi_1_4000000 }, | |
4061 | { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */ | |
4062 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4063 | pbn_oxsemi_1_4000000 }, | |
4064 | { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */ | |
4065 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4066 | pbn_b0_1_4000000 }, | |
4067 | { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */ | |
4068 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4069 | pbn_b0_1_4000000 }, | |
4070 | { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */ | |
4071 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4072 | pbn_b0_1_4000000 }, | |
4073 | { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */ | |
4074 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4075 | pbn_b0_1_4000000 }, | |
4076 | { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */ | |
4077 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4078 | pbn_oxsemi_2_4000000 }, | |
4079 | { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */ | |
4080 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4081 | pbn_oxsemi_2_4000000 }, | |
4082 | { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */ | |
4083 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4084 | pbn_oxsemi_4_4000000 }, | |
4085 | { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */ | |
4086 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4087 | pbn_oxsemi_4_4000000 }, | |
4088 | { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */ | |
4089 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4090 | pbn_oxsemi_8_4000000 }, | |
4091 | { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */ | |
4092 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4093 | pbn_oxsemi_8_4000000 }, | |
4094 | { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */ | |
4095 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4096 | pbn_oxsemi_1_4000000 }, | |
4097 | { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */ | |
4098 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4099 | pbn_oxsemi_1_4000000 }, | |
4100 | { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */ | |
4101 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4102 | pbn_oxsemi_1_4000000 }, | |
4103 | { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */ | |
4104 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4105 | pbn_oxsemi_1_4000000 }, | |
4106 | { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */ | |
4107 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4108 | pbn_oxsemi_1_4000000 }, | |
4109 | { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */ | |
4110 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4111 | pbn_oxsemi_1_4000000 }, | |
4112 | { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */ | |
4113 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4114 | pbn_oxsemi_1_4000000 }, | |
4115 | { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */ | |
4116 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4117 | pbn_oxsemi_1_4000000 }, | |
4118 | { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */ | |
4119 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4120 | pbn_oxsemi_1_4000000 }, | |
4121 | { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */ | |
4122 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4123 | pbn_oxsemi_1_4000000 }, | |
4124 | { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */ | |
4125 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4126 | pbn_oxsemi_1_4000000 }, | |
4127 | { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */ | |
4128 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4129 | pbn_oxsemi_1_4000000 }, | |
4130 | { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */ | |
4131 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4132 | pbn_oxsemi_1_4000000 }, | |
4133 | { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */ | |
4134 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4135 | pbn_oxsemi_1_4000000 }, | |
4136 | { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */ | |
4137 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4138 | pbn_oxsemi_1_4000000 }, | |
4139 | { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */ | |
4140 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4141 | pbn_oxsemi_1_4000000 }, | |
4142 | { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */ | |
4143 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4144 | pbn_oxsemi_1_4000000 }, | |
4145 | { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */ | |
4146 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4147 | pbn_oxsemi_1_4000000 }, | |
4148 | { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */ | |
4149 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4150 | pbn_oxsemi_1_4000000 }, | |
4151 | { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */ | |
4152 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4153 | pbn_oxsemi_1_4000000 }, | |
4154 | { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */ | |
4155 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4156 | pbn_oxsemi_1_4000000 }, | |
4157 | { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */ | |
4158 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4159 | pbn_oxsemi_1_4000000 }, | |
4160 | { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */ | |
4161 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4162 | pbn_oxsemi_1_4000000 }, | |
4163 | { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */ | |
4164 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4165 | pbn_oxsemi_1_4000000 }, | |
4166 | { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */ | |
4167 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4168 | pbn_oxsemi_1_4000000 }, | |
4169 | { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */ | |
4170 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4171 | pbn_oxsemi_1_4000000 }, | |
b80de369 LH |
4172 | /* |
4173 | * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado | |
4174 | */ | |
4175 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */ | |
4176 | PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0, | |
4177 | pbn_oxsemi_1_4000000 }, | |
4178 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */ | |
4179 | PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0, | |
4180 | pbn_oxsemi_2_4000000 }, | |
4181 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */ | |
4182 | PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0, | |
4183 | pbn_oxsemi_4_4000000 }, | |
4184 | { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */ | |
4185 | PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0, | |
4186 | pbn_oxsemi_8_4000000 }, | |
aa273ae5 SK |
4187 | |
4188 | /* | |
4189 | * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado | |
4190 | */ | |
4191 | { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, | |
4192 | PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0, | |
4193 | pbn_oxsemi_2_4000000 }, | |
4194 | ||
1da177e4 LT |
4195 | /* |
4196 | * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, | |
4197 | * from skokodyn@yahoo.com | |
4198 | */ | |
4199 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
4200 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0, | |
4201 | pbn_sbsxrsio }, | |
4202 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
4203 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0, | |
4204 | pbn_sbsxrsio }, | |
4205 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
4206 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0, | |
4207 | pbn_sbsxrsio }, | |
4208 | { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, | |
4209 | PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0, | |
4210 | pbn_sbsxrsio }, | |
4211 | ||
4212 | /* | |
4213 | * Digitan DS560-558, from jimd@esoft.com | |
4214 | */ | |
4215 | { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM, | |
5756ee99 | 4216 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 LT |
4217 | pbn_b1_1_115200 }, |
4218 | ||
4219 | /* | |
4220 | * Titan Electronic cards | |
4221 | * The 400L and 800L have a custom setup quirk. | |
4222 | */ | |
4223 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100, | |
5756ee99 | 4224 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 LT |
4225 | pbn_b0_1_921600 }, |
4226 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200, | |
5756ee99 | 4227 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 LT |
4228 | pbn_b0_2_921600 }, |
4229 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400, | |
5756ee99 | 4230 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 LT |
4231 | pbn_b0_4_921600 }, |
4232 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B, | |
5756ee99 | 4233 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
1da177e4 LT |
4234 | pbn_b0_4_921600 }, |
4235 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L, | |
4236 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4237 | pbn_b1_1_921600 }, | |
4238 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L, | |
4239 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4240 | pbn_b1_bt_2_921600 }, | |
4241 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L, | |
4242 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4243 | pbn_b0_bt_4_921600 }, | |
4244 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L, | |
4245 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4246 | pbn_b0_bt_8_921600 }, | |
66169ad1 YY |
4247 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I, |
4248 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4249 | pbn_b4_bt_2_921600 }, | |
4250 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I, | |
4251 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4252 | pbn_b4_bt_4_921600 }, | |
4253 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I, | |
4254 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4255 | pbn_b4_bt_8_921600 }, | |
4256 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH, | |
4257 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4258 | pbn_b0_4_921600 }, | |
4259 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH, | |
4260 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4261 | pbn_b0_4_921600 }, | |
4262 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB, | |
4263 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4264 | pbn_b0_4_921600 }, | |
4265 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E, | |
4266 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4267 | pbn_oxsemi_1_4000000 }, | |
4268 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E, | |
4269 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4270 | pbn_oxsemi_2_4000000 }, | |
4271 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E, | |
4272 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4273 | pbn_oxsemi_4_4000000 }, | |
4274 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E, | |
4275 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4276 | pbn_oxsemi_8_4000000 }, | |
4277 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI, | |
4278 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4279 | pbn_oxsemi_2_4000000 }, | |
4280 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI, | |
4281 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4282 | pbn_oxsemi_2_4000000 }, | |
48c0247d YY |
4283 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3, |
4284 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4285 | pbn_b0_bt_2_921600 }, | |
1e9deb11 YY |
4286 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3, |
4287 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4288 | pbn_b0_4_921600 }, | |
4289 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3, | |
4290 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4291 | pbn_b0_4_921600 }, | |
4292 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3, | |
4293 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4294 | pbn_b0_4_921600 }, | |
4295 | { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B, | |
4296 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4297 | pbn_b0_4_921600 }, | |
1da177e4 LT |
4298 | |
4299 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550, | |
4300 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4301 | pbn_b2_1_460800 }, | |
4302 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650, | |
4303 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4304 | pbn_b2_1_460800 }, | |
4305 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850, | |
4306 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4307 | pbn_b2_1_460800 }, | |
4308 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550, | |
4309 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4310 | pbn_b2_bt_2_921600 }, | |
4311 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650, | |
4312 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4313 | pbn_b2_bt_2_921600 }, | |
4314 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850, | |
4315 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4316 | pbn_b2_bt_2_921600 }, | |
4317 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550, | |
4318 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4319 | pbn_b2_bt_4_921600 }, | |
4320 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650, | |
4321 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4322 | pbn_b2_bt_4_921600 }, | |
4323 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850, | |
4324 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4325 | pbn_b2_bt_4_921600 }, | |
4326 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550, | |
4327 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4328 | pbn_b0_1_921600 }, | |
4329 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650, | |
4330 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4331 | pbn_b0_1_921600 }, | |
4332 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850, | |
4333 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4334 | pbn_b0_1_921600 }, | |
4335 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550, | |
4336 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4337 | pbn_b0_bt_2_921600 }, | |
4338 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650, | |
4339 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4340 | pbn_b0_bt_2_921600 }, | |
4341 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850, | |
4342 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4343 | pbn_b0_bt_2_921600 }, | |
4344 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550, | |
4345 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4346 | pbn_b0_bt_4_921600 }, | |
4347 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650, | |
4348 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4349 | pbn_b0_bt_4_921600 }, | |
4350 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850, | |
4351 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4352 | pbn_b0_bt_4_921600 }, | |
3ec9c594 AP |
4353 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550, |
4354 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4355 | pbn_b0_bt_8_921600 }, | |
4356 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650, | |
4357 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4358 | pbn_b0_bt_8_921600 }, | |
4359 | { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850, | |
4360 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4361 | pbn_b0_bt_8_921600 }, | |
1da177e4 LT |
4362 | |
4363 | /* | |
4364 | * Computone devices submitted by Doug McNash dmcnash@computone.com | |
4365 | */ | |
4366 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | |
4367 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4, | |
4368 | 0, 0, pbn_computone_4 }, | |
4369 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | |
4370 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8, | |
4371 | 0, 0, pbn_computone_8 }, | |
4372 | { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, | |
4373 | PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6, | |
4374 | 0, 0, pbn_computone_6 }, | |
4375 | ||
4376 | { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N, | |
4377 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4378 | pbn_oxsemi }, | |
4379 | { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, | |
4380 | PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0, | |
4381 | pbn_b0_bt_1_921600 }, | |
4382 | ||
abd7baca SC |
4383 | /* |
4384 | * SUNIX (TIMEDIA) | |
4385 | */ | |
4386 | { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, | |
4387 | PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, | |
4388 | PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00, | |
4389 | pbn_b0_bt_1_921600 }, | |
4390 | ||
4391 | { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, | |
4392 | PCI_VENDOR_ID_SUNIX, PCI_ANY_ID, | |
4393 | PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00, | |
4394 | pbn_b0_bt_1_921600 }, | |
4395 | ||
1da177e4 LT |
4396 | /* |
4397 | * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> | |
4398 | */ | |
4399 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028, | |
4400 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4401 | pbn_b0_bt_8_115200 }, | |
4402 | { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030, | |
4403 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4404 | pbn_b0_bt_8_115200 }, | |
4405 | ||
4406 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL, | |
4407 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4408 | pbn_b0_bt_2_115200 }, | |
4409 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A, | |
4410 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4411 | pbn_b0_bt_2_115200 }, | |
4412 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B, | |
4413 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4414 | pbn_b0_bt_2_115200 }, | |
b87e5e2b LB |
4415 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A, |
4416 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4417 | pbn_b0_bt_2_115200 }, | |
4418 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B, | |
4419 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4420 | pbn_b0_bt_2_115200 }, | |
1da177e4 LT |
4421 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A, |
4422 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4423 | pbn_b0_bt_4_460800 }, | |
4424 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B, | |
4425 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4426 | pbn_b0_bt_4_460800 }, | |
4427 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS, | |
4428 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4429 | pbn_b0_bt_2_460800 }, | |
4430 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A, | |
4431 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4432 | pbn_b0_bt_2_460800 }, | |
4433 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B, | |
4434 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4435 | pbn_b0_bt_2_460800 }, | |
4436 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL, | |
4437 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4438 | pbn_b0_bt_1_115200 }, | |
4439 | { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650, | |
4440 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4441 | pbn_b0_bt_1_460800 }, | |
4442 | ||
1fb8cacc RK |
4443 | /* |
4444 | * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). | |
4445 | * Cards are identified by their subsystem vendor IDs, which | |
4446 | * (in hex) match the model number. | |
4447 | * | |
4448 | * Note that JC140x are RS422/485 cards which require ox950 | |
4449 | * ACR = 0x10, and as such are not currently fully supported. | |
4450 | */ | |
4451 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | |
4452 | 0x1204, 0x0004, 0, 0, | |
4453 | pbn_b0_4_921600 }, | |
4454 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | |
4455 | 0x1208, 0x0004, 0, 0, | |
4456 | pbn_b0_4_921600 }, | |
4457 | /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | |
4458 | 0x1402, 0x0002, 0, 0, | |
4459 | pbn_b0_2_921600 }, */ | |
4460 | /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, | |
4461 | 0x1404, 0x0004, 0, 0, | |
4462 | pbn_b0_4_921600 }, */ | |
4463 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, | |
4464 | 0x1208, 0x0004, 0, 0, | |
4465 | pbn_b0_4_921600 }, | |
4466 | ||
2a52fcb5 KY |
4467 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, |
4468 | 0x1204, 0x0004, 0, 0, | |
4469 | pbn_b0_4_921600 }, | |
4470 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, | |
4471 | 0x1208, 0x0004, 0, 0, | |
4472 | pbn_b0_4_921600 }, | |
4473 | { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, | |
4474 | 0x1208, 0x0004, 0, 0, | |
4475 | pbn_b0_4_921600 }, | |
1da177e4 LT |
4476 | /* |
4477 | * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com | |
4478 | */ | |
4479 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4, | |
4480 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4481 | pbn_b1_1_1382400 }, | |
4482 | ||
4483 | /* | |
4484 | * Dell Remote Access Card III - Tim_T_Murphy@Dell.com | |
4485 | */ | |
4486 | { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII, | |
4487 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4488 | pbn_b1_1_1382400 }, | |
4489 | ||
4490 | /* | |
4491 | * RAStel 2 port modem, gerg@moreton.com.au | |
4492 | */ | |
4493 | { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT, | |
4494 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4495 | pbn_b2_bt_2_115200 }, | |
4496 | ||
4497 | /* | |
4498 | * EKF addition for i960 Boards form EKF with serial port | |
4499 | */ | |
4500 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP, | |
4501 | 0xE4BF, PCI_ANY_ID, 0, 0, | |
4502 | pbn_intel_i960 }, | |
4503 | ||
4504 | /* | |
4505 | * Xircom Cardbus/Ethernet combos | |
4506 | */ | |
4507 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM, | |
4508 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4509 | pbn_b0_1_115200 }, | |
4510 | /* | |
4511 | * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) | |
4512 | */ | |
4513 | { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G, | |
4514 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4515 | pbn_b0_1_115200 }, | |
4516 | ||
4517 | /* | |
4518 | * Untested PCI modems, sent in from various folks... | |
4519 | */ | |
4520 | ||
4521 | /* | |
4522 | * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> | |
4523 | */ | |
4524 | { PCI_VENDOR_ID_ROCKWELL, 0x1004, | |
4525 | 0x1048, 0x1500, 0, 0, | |
4526 | pbn_b1_1_115200 }, | |
4527 | ||
4528 | { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, | |
4529 | 0xFF00, 0, 0, 0, | |
4530 | pbn_sgi_ioc3 }, | |
4531 | ||
4532 | /* | |
4533 | * HP Diva card | |
4534 | */ | |
4535 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, | |
4536 | PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0, | |
4537 | pbn_b1_1_115200 }, | |
4538 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA, | |
4539 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4540 | pbn_b0_5_115200 }, | |
4541 | { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX, | |
4542 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4543 | pbn_b2_1_115200 }, | |
4544 | ||
d9004eb4 ABL |
4545 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2, |
4546 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4547 | pbn_b3_2_115200 }, | |
1da177e4 LT |
4548 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4, |
4549 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4550 | pbn_b3_4_115200 }, | |
4551 | { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8, | |
4552 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4553 | pbn_b3_8_115200 }, | |
89c043a6 AL |
4554 | /* |
4555 | * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART | |
4556 | */ | |
4557 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951, | |
4558 | PCI_ANY_ID, PCI_ANY_ID, | |
4559 | 0, | |
4560 | 0, pbn_pericom_PI7C9X7951 }, | |
4561 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952, | |
4562 | PCI_ANY_ID, PCI_ANY_ID, | |
4563 | 0, | |
4564 | 0, pbn_pericom_PI7C9X7952 }, | |
4565 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954, | |
4566 | PCI_ANY_ID, PCI_ANY_ID, | |
4567 | 0, | |
4568 | 0, pbn_pericom_PI7C9X7954 }, | |
4569 | { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958, | |
4570 | PCI_ANY_ID, PCI_ANY_ID, | |
4571 | 0, | |
4572 | 0, pbn_pericom_PI7C9X7958 }, | |
c8d19242 JD |
4573 | /* |
4574 | * ACCES I/O Products quad | |
4575 | */ | |
4576 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB, | |
4577 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4578 | pbn_pericom_PI7C9X7954 }, | |
4579 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S, | |
4580 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4581 | pbn_pericom_PI7C9X7954 }, | |
4582 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB, | |
4583 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4584 | pbn_pericom_PI7C9X7954 }, | |
4585 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S, | |
4586 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4587 | pbn_pericom_PI7C9X7954 }, | |
4588 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB, | |
4589 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4590 | pbn_pericom_PI7C9X7954 }, | |
4591 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2, | |
4592 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4593 | pbn_pericom_PI7C9X7954 }, | |
4594 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB, | |
4595 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4596 | pbn_pericom_PI7C9X7954 }, | |
4597 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4, | |
4598 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4599 | pbn_pericom_PI7C9X7954 }, | |
4600 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB, | |
4601 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4602 | pbn_pericom_PI7C9X7954 }, | |
4603 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM, | |
4604 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4605 | pbn_pericom_PI7C9X7954 }, | |
4606 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB, | |
4607 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4608 | pbn_pericom_PI7C9X7954 }, | |
4609 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM, | |
4610 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4611 | pbn_pericom_PI7C9X7954 }, | |
4612 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1, | |
4613 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4614 | pbn_pericom_PI7C9X7954 }, | |
4615 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2, | |
4616 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4617 | pbn_pericom_PI7C9X7954 }, | |
4618 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2, | |
4619 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4620 | pbn_pericom_PI7C9X7954 }, | |
4621 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4, | |
4622 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4623 | pbn_pericom_PI7C9X7954 }, | |
4624 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4, | |
4625 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4626 | pbn_pericom_PI7C9X7954 }, | |
4627 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S, | |
4628 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4629 | pbn_pericom_PI7C9X7954 }, | |
4630 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S, | |
4631 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4632 | pbn_pericom_PI7C9X7954 }, | |
4633 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2, | |
4634 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4635 | pbn_pericom_PI7C9X7954 }, | |
4636 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2, | |
4637 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4638 | pbn_pericom_PI7C9X7954 }, | |
4639 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4, | |
4640 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4641 | pbn_pericom_PI7C9X7954 }, | |
4642 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4, | |
4643 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4644 | pbn_pericom_PI7C9X7954 }, | |
4645 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM, | |
4646 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4647 | pbn_pericom_PI7C9X7954 }, | |
4648 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4, | |
4649 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4650 | pbn_pericom_PI7C9X7958 }, | |
4651 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4, | |
4652 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4653 | pbn_pericom_PI7C9X7958 }, | |
4654 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8, | |
4655 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4656 | pbn_pericom_PI7C9X7958 }, | |
4657 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8, | |
4658 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4659 | pbn_pericom_PI7C9X7958 }, | |
4660 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4, | |
4661 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4662 | pbn_pericom_PI7C9X7958 }, | |
4663 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8, | |
4664 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4665 | pbn_pericom_PI7C9X7958 }, | |
4666 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM, | |
4667 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4668 | pbn_pericom_PI7C9X7958 }, | |
4669 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM, | |
4670 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4671 | pbn_pericom_PI7C9X7958 }, | |
4672 | { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM, | |
4673 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4674 | pbn_pericom_PI7C9X7958 }, | |
1da177e4 LT |
4675 | /* |
4676 | * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) | |
4677 | */ | |
4678 | { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560, | |
4679 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4680 | pbn_b0_1_115200 }, | |
84f8c6fc NV |
4681 | /* |
4682 | * ITE | |
4683 | */ | |
4684 | { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872, | |
4685 | PCI_ANY_ID, PCI_ANY_ID, | |
4686 | 0, 0, | |
4687 | pbn_b1_bt_1_115200 }, | |
1da177e4 | 4688 | |
737c1756 PH |
4689 | /* |
4690 | * IntaShield IS-200 | |
4691 | */ | |
4692 | { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, | |
4693 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ | |
4694 | pbn_b2_2_115200 }, | |
4b6f6ce9 IGP |
4695 | /* |
4696 | * IntaShield IS-400 | |
4697 | */ | |
4698 | { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, | |
4699 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ | |
4700 | pbn_b2_4_115200 }, | |
48212008 TH |
4701 | /* |
4702 | * Perle PCI-RAS cards | |
4703 | */ | |
4704 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, | |
4705 | PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4, | |
4706 | 0, 0, pbn_b2_4_921600 }, | |
4707 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, | |
4708 | PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8, | |
4709 | 0, 0, pbn_b2_8_921600 }, | |
bf0df636 AC |
4710 | |
4711 | /* | |
4712 | * Mainpine series cards: Fairly standard layout but fools | |
4713 | * parts of the autodetect in some cases and uses otherwise | |
4714 | * unmatched communications subclasses in the PCI Express case | |
4715 | */ | |
4716 | ||
4717 | { /* RockForceDUO */ | |
4718 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4719 | PCI_VENDOR_ID_MAINPINE, 0x0200, | |
4720 | 0, 0, pbn_b0_2_115200 }, | |
4721 | { /* RockForceQUATRO */ | |
4722 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4723 | PCI_VENDOR_ID_MAINPINE, 0x0300, | |
4724 | 0, 0, pbn_b0_4_115200 }, | |
4725 | { /* RockForceDUO+ */ | |
4726 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4727 | PCI_VENDOR_ID_MAINPINE, 0x0400, | |
4728 | 0, 0, pbn_b0_2_115200 }, | |
4729 | { /* RockForceQUATRO+ */ | |
4730 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4731 | PCI_VENDOR_ID_MAINPINE, 0x0500, | |
4732 | 0, 0, pbn_b0_4_115200 }, | |
4733 | { /* RockForce+ */ | |
4734 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4735 | PCI_VENDOR_ID_MAINPINE, 0x0600, | |
4736 | 0, 0, pbn_b0_2_115200 }, | |
4737 | { /* RockForce+ */ | |
4738 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4739 | PCI_VENDOR_ID_MAINPINE, 0x0700, | |
4740 | 0, 0, pbn_b0_4_115200 }, | |
4741 | { /* RockForceOCTO+ */ | |
4742 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4743 | PCI_VENDOR_ID_MAINPINE, 0x0800, | |
4744 | 0, 0, pbn_b0_8_115200 }, | |
4745 | { /* RockForceDUO+ */ | |
4746 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4747 | PCI_VENDOR_ID_MAINPINE, 0x0C00, | |
4748 | 0, 0, pbn_b0_2_115200 }, | |
4749 | { /* RockForceQUARTRO+ */ | |
4750 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4751 | PCI_VENDOR_ID_MAINPINE, 0x0D00, | |
4752 | 0, 0, pbn_b0_4_115200 }, | |
4753 | { /* RockForceOCTO+ */ | |
4754 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4755 | PCI_VENDOR_ID_MAINPINE, 0x1D00, | |
4756 | 0, 0, pbn_b0_8_115200 }, | |
4757 | { /* RockForceD1 */ | |
4758 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4759 | PCI_VENDOR_ID_MAINPINE, 0x2000, | |
4760 | 0, 0, pbn_b0_1_115200 }, | |
4761 | { /* RockForceF1 */ | |
4762 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4763 | PCI_VENDOR_ID_MAINPINE, 0x2100, | |
4764 | 0, 0, pbn_b0_1_115200 }, | |
4765 | { /* RockForceD2 */ | |
4766 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4767 | PCI_VENDOR_ID_MAINPINE, 0x2200, | |
4768 | 0, 0, pbn_b0_2_115200 }, | |
4769 | { /* RockForceF2 */ | |
4770 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4771 | PCI_VENDOR_ID_MAINPINE, 0x2300, | |
4772 | 0, 0, pbn_b0_2_115200 }, | |
4773 | { /* RockForceD4 */ | |
4774 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4775 | PCI_VENDOR_ID_MAINPINE, 0x2400, | |
4776 | 0, 0, pbn_b0_4_115200 }, | |
4777 | { /* RockForceF4 */ | |
4778 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4779 | PCI_VENDOR_ID_MAINPINE, 0x2500, | |
4780 | 0, 0, pbn_b0_4_115200 }, | |
4781 | { /* RockForceD8 */ | |
4782 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4783 | PCI_VENDOR_ID_MAINPINE, 0x2600, | |
4784 | 0, 0, pbn_b0_8_115200 }, | |
4785 | { /* RockForceF8 */ | |
4786 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4787 | PCI_VENDOR_ID_MAINPINE, 0x2700, | |
4788 | 0, 0, pbn_b0_8_115200 }, | |
4789 | { /* IQ Express D1 */ | |
4790 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4791 | PCI_VENDOR_ID_MAINPINE, 0x3000, | |
4792 | 0, 0, pbn_b0_1_115200 }, | |
4793 | { /* IQ Express F1 */ | |
4794 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4795 | PCI_VENDOR_ID_MAINPINE, 0x3100, | |
4796 | 0, 0, pbn_b0_1_115200 }, | |
4797 | { /* IQ Express D2 */ | |
4798 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4799 | PCI_VENDOR_ID_MAINPINE, 0x3200, | |
4800 | 0, 0, pbn_b0_2_115200 }, | |
4801 | { /* IQ Express F2 */ | |
4802 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4803 | PCI_VENDOR_ID_MAINPINE, 0x3300, | |
4804 | 0, 0, pbn_b0_2_115200 }, | |
4805 | { /* IQ Express D4 */ | |
4806 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4807 | PCI_VENDOR_ID_MAINPINE, 0x3400, | |
4808 | 0, 0, pbn_b0_4_115200 }, | |
4809 | { /* IQ Express F4 */ | |
4810 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4811 | PCI_VENDOR_ID_MAINPINE, 0x3500, | |
4812 | 0, 0, pbn_b0_4_115200 }, | |
4813 | { /* IQ Express D8 */ | |
4814 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4815 | PCI_VENDOR_ID_MAINPINE, 0x3C00, | |
4816 | 0, 0, pbn_b0_8_115200 }, | |
4817 | { /* IQ Express F8 */ | |
4818 | PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, | |
4819 | PCI_VENDOR_ID_MAINPINE, 0x3D00, | |
4820 | 0, 0, pbn_b0_8_115200 }, | |
4821 | ||
4822 | ||
aa798505 OJ |
4823 | /* |
4824 | * PA Semi PA6T-1682M on-chip UART | |
4825 | */ | |
4826 | { PCI_VENDOR_ID_PASEMI, 0xa004, | |
4827 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4828 | pbn_pasemi_1682M }, | |
4829 | ||
46a0fac9 SB |
4830 | /* |
4831 | * National Instruments | |
4832 | */ | |
04bf7e74 WP |
4833 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216, |
4834 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4835 | pbn_b1_16_115200 }, | |
4836 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328, | |
4837 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4838 | pbn_b1_8_115200 }, | |
4839 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324, | |
4840 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4841 | pbn_b1_bt_4_115200 }, | |
4842 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322, | |
4843 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4844 | pbn_b1_bt_2_115200 }, | |
4845 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I, | |
4846 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4847 | pbn_b1_bt_4_115200 }, | |
4848 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I, | |
4849 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4850 | pbn_b1_bt_2_115200 }, | |
4851 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216, | |
4852 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4853 | pbn_b1_16_115200 }, | |
4854 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328, | |
4855 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4856 | pbn_b1_8_115200 }, | |
4857 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324, | |
4858 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4859 | pbn_b1_bt_4_115200 }, | |
4860 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322, | |
4861 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4862 | pbn_b1_bt_2_115200 }, | |
4863 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324, | |
4864 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4865 | pbn_b1_bt_4_115200 }, | |
4866 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322, | |
4867 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4868 | pbn_b1_bt_2_115200 }, | |
46a0fac9 SB |
4869 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322, |
4870 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4871 | pbn_ni8430_2 }, | |
4872 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322, | |
4873 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4874 | pbn_ni8430_2 }, | |
4875 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324, | |
4876 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4877 | pbn_ni8430_4 }, | |
4878 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324, | |
4879 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4880 | pbn_ni8430_4 }, | |
4881 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328, | |
4882 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4883 | pbn_ni8430_8 }, | |
4884 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328, | |
4885 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4886 | pbn_ni8430_8 }, | |
4887 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216, | |
4888 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4889 | pbn_ni8430_16 }, | |
4890 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216, | |
4891 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4892 | pbn_ni8430_16 }, | |
4893 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322, | |
4894 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4895 | pbn_ni8430_2 }, | |
4896 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322, | |
4897 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4898 | pbn_ni8430_2 }, | |
4899 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324, | |
4900 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4901 | pbn_ni8430_4 }, | |
4902 | { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324, | |
4903 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
4904 | pbn_ni8430_4 }, | |
4905 | ||
02c9b5cf KJ |
4906 | /* |
4907 | * ADDI-DATA GmbH communication cards <info@addi-data.com> | |
4908 | */ | |
4909 | { PCI_VENDOR_ID_ADDIDATA, | |
4910 | PCI_DEVICE_ID_ADDIDATA_APCI7500, | |
4911 | PCI_ANY_ID, | |
4912 | PCI_ANY_ID, | |
4913 | 0, | |
4914 | 0, | |
4915 | pbn_b0_4_115200 }, | |
4916 | ||
4917 | { PCI_VENDOR_ID_ADDIDATA, | |
4918 | PCI_DEVICE_ID_ADDIDATA_APCI7420, | |
4919 | PCI_ANY_ID, | |
4920 | PCI_ANY_ID, | |
4921 | 0, | |
4922 | 0, | |
4923 | pbn_b0_2_115200 }, | |
4924 | ||
4925 | { PCI_VENDOR_ID_ADDIDATA, | |
4926 | PCI_DEVICE_ID_ADDIDATA_APCI7300, | |
4927 | PCI_ANY_ID, | |
4928 | PCI_ANY_ID, | |
4929 | 0, | |
4930 | 0, | |
4931 | pbn_b0_1_115200 }, | |
4932 | ||
086231f7 | 4933 | { PCI_VENDOR_ID_AMCC, |
57c1f0e9 | 4934 | PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, |
02c9b5cf KJ |
4935 | PCI_ANY_ID, |
4936 | PCI_ANY_ID, | |
4937 | 0, | |
4938 | 0, | |
4939 | pbn_b1_8_115200 }, | |
4940 | ||
4941 | { PCI_VENDOR_ID_ADDIDATA, | |
4942 | PCI_DEVICE_ID_ADDIDATA_APCI7500_2, | |
4943 | PCI_ANY_ID, | |
4944 | PCI_ANY_ID, | |
4945 | 0, | |
4946 | 0, | |
4947 | pbn_b0_4_115200 }, | |
4948 | ||
4949 | { PCI_VENDOR_ID_ADDIDATA, | |
4950 | PCI_DEVICE_ID_ADDIDATA_APCI7420_2, | |
4951 | PCI_ANY_ID, | |
4952 | PCI_ANY_ID, | |
4953 | 0, | |
4954 | 0, | |
4955 | pbn_b0_2_115200 }, | |
4956 | ||
4957 | { PCI_VENDOR_ID_ADDIDATA, | |
4958 | PCI_DEVICE_ID_ADDIDATA_APCI7300_2, | |
4959 | PCI_ANY_ID, | |
4960 | PCI_ANY_ID, | |
4961 | 0, | |
4962 | 0, | |
4963 | pbn_b0_1_115200 }, | |
4964 | ||
4965 | { PCI_VENDOR_ID_ADDIDATA, | |
4966 | PCI_DEVICE_ID_ADDIDATA_APCI7500_3, | |
4967 | PCI_ANY_ID, | |
4968 | PCI_ANY_ID, | |
4969 | 0, | |
4970 | 0, | |
4971 | pbn_b0_4_115200 }, | |
4972 | ||
4973 | { PCI_VENDOR_ID_ADDIDATA, | |
4974 | PCI_DEVICE_ID_ADDIDATA_APCI7420_3, | |
4975 | PCI_ANY_ID, | |
4976 | PCI_ANY_ID, | |
4977 | 0, | |
4978 | 0, | |
4979 | pbn_b0_2_115200 }, | |
4980 | ||
4981 | { PCI_VENDOR_ID_ADDIDATA, | |
4982 | PCI_DEVICE_ID_ADDIDATA_APCI7300_3, | |
4983 | PCI_ANY_ID, | |
4984 | PCI_ANY_ID, | |
4985 | 0, | |
4986 | 0, | |
4987 | pbn_b0_1_115200 }, | |
4988 | ||
4989 | { PCI_VENDOR_ID_ADDIDATA, | |
4990 | PCI_DEVICE_ID_ADDIDATA_APCI7800_3, | |
4991 | PCI_ANY_ID, | |
4992 | PCI_ANY_ID, | |
4993 | 0, | |
4994 | 0, | |
4995 | pbn_b0_8_115200 }, | |
4996 | ||
1b62cbf2 KJ |
4997 | { PCI_VENDOR_ID_ADDIDATA, |
4998 | PCI_DEVICE_ID_ADDIDATA_APCIe7500, | |
4999 | PCI_ANY_ID, | |
5000 | PCI_ANY_ID, | |
5001 | 0, | |
5002 | 0, | |
5003 | pbn_ADDIDATA_PCIe_4_3906250 }, | |
5004 | ||
5005 | { PCI_VENDOR_ID_ADDIDATA, | |
5006 | PCI_DEVICE_ID_ADDIDATA_APCIe7420, | |
5007 | PCI_ANY_ID, | |
5008 | PCI_ANY_ID, | |
5009 | 0, | |
5010 | 0, | |
5011 | pbn_ADDIDATA_PCIe_2_3906250 }, | |
5012 | ||
5013 | { PCI_VENDOR_ID_ADDIDATA, | |
5014 | PCI_DEVICE_ID_ADDIDATA_APCIe7300, | |
5015 | PCI_ANY_ID, | |
5016 | PCI_ANY_ID, | |
5017 | 0, | |
5018 | 0, | |
5019 | pbn_ADDIDATA_PCIe_1_3906250 }, | |
5020 | ||
5021 | { PCI_VENDOR_ID_ADDIDATA, | |
5022 | PCI_DEVICE_ID_ADDIDATA_APCIe7800, | |
5023 | PCI_ANY_ID, | |
5024 | PCI_ANY_ID, | |
5025 | 0, | |
5026 | 0, | |
5027 | pbn_ADDIDATA_PCIe_8_3906250 }, | |
5028 | ||
25cf9bc1 JS |
5029 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835, |
5030 | PCI_VENDOR_ID_IBM, 0x0299, | |
5031 | 0, 0, pbn_b0_bt_2_115200 }, | |
5032 | ||
972ce085 SS |
5033 | /* |
5034 | * other NetMos 9835 devices are most likely handled by the | |
5035 | * parport_serial driver, check drivers/parport/parport_serial.c | |
5036 | * before adding them here. | |
5037 | */ | |
5038 | ||
c4285b47 MB |
5039 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901, |
5040 | 0xA000, 0x1000, | |
5041 | 0, 0, pbn_b0_1_115200 }, | |
5042 | ||
7808edcd NG |
5043 | /* the 9901 is a rebranded 9912 */ |
5044 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912, | |
5045 | 0xA000, 0x1000, | |
5046 | 0, 0, pbn_b0_1_115200 }, | |
5047 | ||
5048 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922, | |
5049 | 0xA000, 0x1000, | |
5050 | 0, 0, pbn_b0_1_115200 }, | |
5051 | ||
5052 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904, | |
5053 | 0xA000, 0x1000, | |
5054 | 0, 0, pbn_b0_1_115200 }, | |
5055 | ||
5056 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, | |
5057 | 0xA000, 0x1000, | |
5058 | 0, 0, pbn_b0_1_115200 }, | |
5059 | ||
5060 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900, | |
5061 | 0xA000, 0x3002, | |
5062 | 0, 0, pbn_NETMOS9900_2s_115200 }, | |
5063 | ||
ac6ec5b1 | 5064 | /* |
44178176 | 5065 | * Best Connectivity and Rosewill PCI Multi I/O cards |
ac6ec5b1 IS |
5066 | */ |
5067 | ||
5068 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, | |
5069 | 0xA000, 0x1000, | |
5070 | 0, 0, pbn_b0_1_115200 }, | |
5071 | ||
44178176 ES |
5072 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, |
5073 | 0xA000, 0x3002, | |
5074 | 0, 0, pbn_b0_bt_2_115200 }, | |
5075 | ||
ac6ec5b1 IS |
5076 | { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865, |
5077 | 0xA000, 0x3004, | |
5078 | 0, 0, pbn_b0_bt_4_115200 }, | |
095e24b0 DB |
5079 | /* Intel CE4100 */ |
5080 | { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART, | |
5081 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
5082 | pbn_ce4100_1_115200 }, | |
6c55d9b9 | 5083 | |
d9a0fbfd AP |
5084 | /* |
5085 | * Cronyx Omega PCI | |
5086 | */ | |
5087 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA, | |
5088 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
5089 | pbn_omegapci }, | |
ac6ec5b1 | 5090 | |
ebebd49a SH |
5091 | /* |
5092 | * Broadcom TruManage | |
5093 | */ | |
5094 | { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE, | |
5095 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, | |
5096 | pbn_brcm_trumanage }, | |
5097 | ||
6683549e AC |
5098 | /* |
5099 | * AgeStar as-prs2-009 | |
5100 | */ | |
5101 | { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375, | |
5102 | PCI_ANY_ID, PCI_ANY_ID, | |
5103 | 0, 0, pbn_b0_bt_2_115200 }, | |
27788c5f AC |
5104 | |
5105 | /* | |
5106 | * WCH CH353 series devices: The 2S1P is handled by parport_serial | |
5107 | * so not listed here. | |
5108 | */ | |
5109 | { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S, | |
5110 | PCI_ANY_ID, PCI_ANY_ID, | |
5111 | 0, 0, pbn_b0_bt_4_115200 }, | |
5112 | ||
5113 | { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF, | |
5114 | PCI_ANY_ID, PCI_ANY_ID, | |
5115 | 0, 0, pbn_b0_bt_2_115200 }, | |
5116 | ||
55c368cb AP |
5117 | { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S, |
5118 | PCI_ANY_ID, PCI_ANY_ID, | |
5119 | 0, 0, pbn_b0_bt_4_115200 }, | |
5120 | ||
7dde5578 JM |
5121 | { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S, |
5122 | PCI_ANY_ID, PCI_ANY_ID, | |
5123 | 0, 0, pbn_wch382_2 }, | |
5124 | ||
72a3c0e4 SP |
5125 | { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S, |
5126 | PCI_ANY_ID, PCI_ANY_ID, | |
5127 | 0, 0, pbn_wch384_4 }, | |
5128 | ||
2c62a3c8 GKH |
5129 | /* Fintek PCI serial cards */ |
5130 | { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 }, | |
5131 | { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 }, | |
5132 | { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 }, | |
5133 | ||
1c9c858e IA |
5134 | /* MKS Tenta SCOM-080x serial cards */ |
5135 | { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 }, | |
5136 | { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 }, | |
5137 | ||
1da177e4 LT |
5138 | /* |
5139 | * These entries match devices with class COMMUNICATION_SERIAL, | |
5140 | * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL | |
5141 | */ | |
5142 | { PCI_ANY_ID, PCI_ANY_ID, | |
5143 | PCI_ANY_ID, PCI_ANY_ID, | |
5144 | PCI_CLASS_COMMUNICATION_SERIAL << 8, | |
5145 | 0xffff00, pbn_default }, | |
5146 | { PCI_ANY_ID, PCI_ANY_ID, | |
5147 | PCI_ANY_ID, PCI_ANY_ID, | |
5148 | PCI_CLASS_COMMUNICATION_MODEM << 8, | |
5149 | 0xffff00, pbn_default }, | |
5150 | { PCI_ANY_ID, PCI_ANY_ID, | |
5151 | PCI_ANY_ID, PCI_ANY_ID, | |
5152 | PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, | |
5153 | 0xffff00, pbn_default }, | |
5154 | { 0, } | |
5155 | }; | |
5156 | ||
2807190b MR |
5157 | static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, |
5158 | pci_channel_state_t state) | |
5159 | { | |
5160 | struct serial_private *priv = pci_get_drvdata(dev); | |
5161 | ||
5162 | if (state == pci_channel_io_perm_failure) | |
5163 | return PCI_ERS_RESULT_DISCONNECT; | |
5164 | ||
5165 | if (priv) | |
f209fa03 | 5166 | pciserial_detach_ports(priv); |
2807190b MR |
5167 | |
5168 | pci_disable_device(dev); | |
5169 | ||
5170 | return PCI_ERS_RESULT_NEED_RESET; | |
5171 | } | |
5172 | ||
5173 | static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) | |
5174 | { | |
5175 | int rc; | |
5176 | ||
5177 | rc = pci_enable_device(dev); | |
5178 | ||
5179 | if (rc) | |
5180 | return PCI_ERS_RESULT_DISCONNECT; | |
5181 | ||
5182 | pci_restore_state(dev); | |
5183 | pci_save_state(dev); | |
5184 | ||
5185 | return PCI_ERS_RESULT_RECOVERED; | |
5186 | } | |
5187 | ||
5188 | static void serial8250_io_resume(struct pci_dev *dev) | |
5189 | { | |
5190 | struct serial_private *priv = pci_get_drvdata(dev); | |
c130b666 | 5191 | struct serial_private *new; |
2807190b | 5192 | |
f209fa03 GKB |
5193 | if (!priv) |
5194 | return; | |
5195 | ||
c130b666 GKB |
5196 | new = pciserial_init_ports(dev, priv->board); |
5197 | if (!IS_ERR(new)) { | |
5198 | pci_set_drvdata(dev, new); | |
5199 | kfree(priv); | |
f209fa03 | 5200 | } |
2807190b MR |
5201 | } |
5202 | ||
1d352035 | 5203 | static const struct pci_error_handlers serial8250_err_handler = { |
2807190b MR |
5204 | .error_detected = serial8250_io_error_detected, |
5205 | .slot_reset = serial8250_io_slot_reset, | |
5206 | .resume = serial8250_io_resume, | |
5207 | }; | |
5208 | ||
1da177e4 LT |
5209 | static struct pci_driver serial_pci_driver = { |
5210 | .name = "serial", | |
5211 | .probe = pciserial_init_one, | |
2d47b716 | 5212 | .remove = pciserial_remove_one, |
61702c3e AS |
5213 | .driver = { |
5214 | .pm = &pciserial_pm_ops, | |
5215 | }, | |
1da177e4 | 5216 | .id_table = serial_pci_tbl, |
2807190b | 5217 | .err_handler = &serial8250_err_handler, |
1da177e4 LT |
5218 | }; |
5219 | ||
15a12e83 | 5220 | module_pci_driver(serial_pci_driver); |
1da177e4 LT |
5221 | |
5222 | MODULE_LICENSE("GPL"); | |
5223 | MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); | |
5224 | MODULE_DEVICE_TABLE(pci, serial_pci_tbl); |