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serial: 8250_pci: more BayTrail error-free bauds
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4 11 */
af8c5b8d 12#undef DEBUG
1da177e4 13#include <linux/module.h>
1da177e4 14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
24
25#include <asm/byteorder.h>
26#include <asm/io.h>
27
28#include "8250.h"
29
1da177e4
LT		 30/*
31 * init function returns:
32 * > 0 - number of ports
33 * = 0 - use board->num_ports
34 * < 0 - error
35 */
36struct pci_serial_quirk {
37 u32 vendor;
38 u32 device;
39 u32 subvendor;
40 u32 subdevice;
5bf8f501 41 int (*probe)(struct pci_dev *dev);
1da177e4 42 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
2655a2c7 45 struct uart_8250_port *, int);
1da177e4
LT		 46 void (*exit)(struct pci_dev *dev);
47};
48
49#define PCI_NUM_BAR_RESOURCES 6
50
51struct serial_private {
70db3d91 52 struct pci_dev *dev;
1da177e4
LT		 53 unsigned int nr;
54 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
55 struct pci_serial_quirk *quirk;
56 int line[0];
57};
58
7808edcd 59static int pci_default_setup(struct serial_private*,
2655a2c7 60 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 61
1da177e4
LT		 62static void moan_device(const char *str, struct pci_dev *dev)
63{
af8c5b8d 64 dev_err(&dev->dev,
ad361c98
JP		 65 "%s: %s\n"
66 "Please send the output of lspci -vv, this\n"
67 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 "manufacturer and name of serial board or\n"
69 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
72}
73
74static int
2655a2c7 75setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 76 int bar, int offset, int regshift)
77{
70db3d91 78 struct pci_dev *dev = priv->dev;
1da177e4
LT		 79 unsigned long base, len;
80
81 if (bar >= PCI_NUM_BAR_RESOURCES)
82 return -EINVAL;
83
72ce9a83
RK		 84 base = pci_resource_start(dev, bar);
85
1da177e4 86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 87 len = pci_resource_len(dev, bar);
88
89 if (!priv->remapped_bar[bar])
6f441fe9 90 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
2655a2c7
AC		 94 port->port.iotype = UPIO_MEM;
95 port->port.iobase = 0;
96 port->port.mapbase = base + offset;
97 port->port.membase = priv->remapped_bar[bar] + offset;
98 port->port.regshift = regshift;
1da177e4 99 } else {
2655a2c7
AC		 100 port->port.iotype = UPIO_PORT;
101 port->port.iobase = base + offset;
102 port->port.mapbase = 0;
103 port->port.membase = NULL;
104 port->port.regshift = 0;
1da177e4
LT		 105 }
106 return 0;
107}
108
02c9b5cf
KJ		 109/*
110 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 */
112static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 113 const struct pciserial_board *board,
2655a2c7 114 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 115{
116 unsigned int bar = 0, offset = board->first_offset;
117 bar = FL_GET_BASE(board->flags);
118
119 if (idx < 2) {
120 offset += idx * board->uart_offset;
121 } else if ((idx >= 2) && (idx < 4)) {
122 bar += 1;
123 offset += ((idx - 2) * board->uart_offset);
124 } else if ((idx >= 4) && (idx < 6)) {
125 bar += 2;
126 offset += ((idx - 4) * board->uart_offset);
127 } else if (idx >= 6) {
128 bar += 3;
129 offset += ((idx - 6) * board->uart_offset);
130 }
131
132 return setup_port(priv, port, bar, offset, board->reg_shift);
133}
134
1da177e4
LT		 135/*
136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
138 */
139static int
975a1a7d 140afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 141 struct uart_8250_port *port, int idx)
1da177e4
LT		 142{
143 unsigned int bar, offset = board->first_offset;
5756ee99 144
1da177e4
LT		 145 bar = FL_GET_BASE(board->flags);
146 if (idx < 4)
147 bar += idx;
148 else {
149 bar = 4;
150 offset += (idx - 4) * board->uart_offset;
151 }
152
70db3d91 153 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 154}
155
156/*
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
162 */
61a116ef 163static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 164{
165 int rc = 0;
166
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 rc = 3;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 rc = 2;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 rc = 4;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 182 rc = 1;
183 break;
184 }
185
186 return rc;
187}
188
189/*
190 * HP's Diva chip puts the 4th/5th serial port further out, and
191 * some serial ports are supposed to be hidden on certain models.
192 */
193static int
975a1a7d
RK		 194pci_hp_diva_setup(struct serial_private *priv,
195 const struct pciserial_board *board,
2655a2c7 196 struct uart_8250_port *port, int idx)
1da177e4
LT		 197{
198 unsigned int offset = board->first_offset;
199 unsigned int bar = FL_GET_BASE(board->flags);
200
70db3d91 201 switch (priv->dev->subsystem_device) {
1da177e4
LT		 202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
203 if (idx == 3)
204 idx++;
205 break;
206 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
207 if (idx > 0)
208 idx++;
209 if (idx > 2)
210 idx++;
211 break;
212 }
213 if (idx > 2)
214 offset = 0x18;
215
216 offset += idx * board->uart_offset;
217
70db3d91 218 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 219}
220
221/*
222 * Added for EKF Intel i960 serial boards
223 */
61a116ef 224static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 225{
226 unsigned long oldval;
227
228 if (!(dev->subsystem_device & 0x1000))
229 return -ENODEV;
230
231 /* is firmware started? */
5756ee99
AC		 232 pci_read_config_dword(dev, 0x44, (void *)&oldval);
233 if (oldval == 0x00001000L) { /* RESET value */
af8c5b8d 234 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
1da177e4
LT		 235 return -ENODEV;
236 }
237 return 0;
238}
239
240/*
241 * Some PCI serial cards using the PLX 9050 PCI interface chip require
242 * that the card interrupt be explicitly enabled or disabled. This
243 * seems to be mainly needed on card using the PLX which also use I/O
244 * mapped memory.
245 */
61a116ef 246static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 247{
248 u8 irq_config;
249 void __iomem *p;
250
251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
252 moan_device("no memory in bar 0", dev);
253 return 0;
254 }
255
256 irq_config = 0x41;
add7b58e 257 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 259 irq_config = 0x43;
5756ee99 260
1da177e4 261 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 263 /*
264 * As the megawolf cards have the int pins active
265 * high, and have 2 UART chips, both ints must be
266 * enabled on the 9050. Also, the UARTS are set in
267 * 16450 mode by default, so we have to enable the
268 * 16C950 'enhanced' mode so that we can use the
269 * deep FIFOs
270 */
271 irq_config = 0x5b;
1da177e4
LT		 272 /*
273 * enable/disable interrupts
274 */
6f441fe9 275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 276 if (p == NULL)
277 return -ENOMEM;
278 writel(irq_config, p + 0x4c);
279
280 /*
281 * Read the register back to ensure that it took effect.
282 */
283 readl(p + 0x4c);
284 iounmap(p);
285
286 return 0;
287}
288
ae8d8a14 289static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 290{
291 u8 __iomem *p;
292
293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
294 return;
295
296 /*
297 * disable interrupts
298 */
6f441fe9 299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 300 if (p != NULL) {
301 writel(0, p + 0x4c);
302
303 /*
304 * Read the register back to ensure that it took effect.
305 */
306 readl(p + 0x4c);
307 iounmap(p);
308 }
309}
310
04bf7e74
WP		 311#define NI8420_INT_ENABLE_REG 0x38
312#define NI8420_INT_ENABLE_BIT 0x2000
313
ae8d8a14 314static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 315{
316 void __iomem *p;
317 unsigned long base, len;
318 unsigned int bar = 0;
319
320 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
321 moan_device("no memory in bar", dev);
322 return;
323 }
324
325 base = pci_resource_start(dev, bar);
326 len = pci_resource_len(dev, bar);
327 p = ioremap_nocache(base, len);
328 if (p == NULL)
329 return;
330
331 /* Disable the CPU Interrupt */
332 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
333 p + NI8420_INT_ENABLE_REG);
334 iounmap(p);
335}
336
337
46a0fac9
SB		 338/* MITE registers */
339#define MITE_IOWBSR1 0xc4
340#define MITE_IOWCR1 0xf4
341#define MITE_LCIMR1 0x08
342#define MITE_LCIMR2 0x10
343
344#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
345
ae8d8a14 346static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 347{
348 void __iomem *p;
349 unsigned long base, len;
350 unsigned int bar = 0;
351
352 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
353 moan_device("no memory in bar", dev);
354 return;
355 }
356
357 base = pci_resource_start(dev, bar);
358 len = pci_resource_len(dev, bar);
359 p = ioremap_nocache(base, len);
360 if (p == NULL)
361 return;
362
363 /* Disable the CPU Interrupt */
364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
365 iounmap(p);
366}
367
1da177e4
LT		 368/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
369static int
975a1a7d 370sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 371 struct uart_8250_port *port, int idx)
1da177e4
LT		 372{
373 unsigned int bar, offset = board->first_offset;
374
375 bar = 0;
376
377 if (idx < 4) {
378 /* first four channels map to 0, 0x100, 0x200, 0x300 */
379 offset += idx * board->uart_offset;
380 } else if (idx < 8) {
381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
382 offset += idx * board->uart_offset + 0xC00;
383 } else /* we have only 8 ports on PMC-OCTALPRO */
384 return 1;
385
70db3d91 386 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 387}
388
389/*
390* This does initialization for PMC OCTALPRO cards:
391* maps the device memory, resets the UARTs (needed, bc
392* if the module is removed and inserted again, the card
393* is in the sleep mode) and enables global interrupt.
394*/
395
396/* global control register offset for SBS PMC-OctalPro */
397#define OCT_REG_CR_OFF 0x500
398
61a116ef 399static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 400{
401 u8 __iomem *p;
402
24ed3aba 403 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 404
405 if (p == NULL)
406 return -ENOMEM;
407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 408 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 409 udelay(50);
5756ee99 410 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 411
412 /* Set bit-2 (INTENABLE) of Control Register */
413 writeb(0x4, p + OCT_REG_CR_OFF);
414 iounmap(p);
415
416 return 0;
417}
418
419/*
420 * Disables the global interrupt of PMC-OctalPro
421 */
422
ae8d8a14 423static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 424{
425 u8 __iomem *p;
426
24ed3aba 427 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
429 if (p != NULL)
1da177e4 430 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 431 iounmap(p);
432}
433
434/*
435 * SIIG serial cards have an PCI interface chip which also controls
436 * the UART clocking frequency. Each UART can be clocked independently
25985edc 437 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 438 * are stored in the EEPROM chip. It can cause problems because this
439 * version of serial driver doesn't support differently clocked UART's
440 * on single PCI card. To prevent this, initialization functions set
441 * high frequency clocking for all UART's on given card. It is safe (I
442 * hope) because it doesn't touch EEPROM settings to prevent conflicts
443 * with other OSes (like M$ DOS).
444 *
445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 446 *
1da177e4
LT		 447 * There is two family of SIIG serial cards with different PCI
448 * interface chip and different configuration methods:
449 * - 10x cards have control registers in IO and/or memory space;
450 * - 20x cards have control registers in standard PCI configuration space.
451 *
67d74b87
RK		 452 * Note: all 10x cards have PCI device ids 0x10..
453 * all 20x cards have PCI device ids 0x20..
454 *
fbc0dc0d
AP		 455 * There are also Quartet Serial cards which use Oxford Semiconductor
456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
457 *
1da177e4
LT		 458 * Note: some SIIG cards are probed by the parport_serial object.
459 */
460
461#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
462#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
463
464static int pci_siig10x_init(struct pci_dev *dev)
465{
466 u16 data;
467 void __iomem *p;
468
469 switch (dev->device & 0xfff8) {
470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
471 data = 0xffdf;
472 break;
473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
474 data = 0xf7ff;
475 break;
476 default: /* 1S1P, 4S */
477 data = 0xfffb;
478 break;
479 }
480
6f441fe9 481 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 482 if (p == NULL)
483 return -ENOMEM;
484
485 writew(readw(p + 0x28) & data, p + 0x28);
486 readw(p + 0x28);
487 iounmap(p);
488 return 0;
489}
490
491#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
492#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
493
494static int pci_siig20x_init(struct pci_dev *dev)
495{
496 u8 data;
497
498 /* Change clock frequency for the first UART. */
499 pci_read_config_byte(dev, 0x6f, &data);
500 pci_write_config_byte(dev, 0x6f, data & 0xef);
501
502 /* If this card has 2 UART, we have to do the same with second UART. */
503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
505 pci_read_config_byte(dev, 0x73, &data);
506 pci_write_config_byte(dev, 0x73, data & 0xef);
507 }
508 return 0;
509}
510
67d74b87
RK		 511static int pci_siig_init(struct pci_dev *dev)
512{
513 unsigned int type = dev->device & 0xff00;
514
515 if (type == 0x1000)
516 return pci_siig10x_init(dev);
517 else if (type == 0x2000)
518 return pci_siig20x_init(dev);
519
520 moan_device("Unknown SIIG card", dev);
521 return -ENODEV;
522}
523
3ec9c594 524static int pci_siig_setup(struct serial_private *priv,
975a1a7d 525 const struct pciserial_board *board,
2655a2c7 526 struct uart_8250_port *port, int idx)
3ec9c594
AP		 527{
528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
529
530 if (idx > 3) {
531 bar = 4;
532 offset = (idx - 4) * 8;
533 }
534
535 return setup_port(priv, port, bar, offset, 0);
536}
537
1da177e4
LT		 538/*
539 * Timedia has an explosion of boards, and to avoid the PCI table from
540 * growing *huge*, we use this function to collapse some 70 entries
541 * in the PCI table into one, for sanity's and compactness's sake.
542 */
e9422e09 543static const unsigned short timedia_single_port[] = {
1da177e4
LT		 544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
545};
546
e9422e09 547static const unsigned short timedia_dual_port[] = {
1da177e4 548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
552 0xD079, 0
553};
554
e9422e09 555static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
559 0xB157, 0
560};
561
e9422e09 562static const unsigned short timedia_eight_port[] = {
5756ee99 563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
565};
566
cb3592be 567static const struct timedia_struct {
1da177e4 568 int num;
e9422e09 569 const unsigned short *ids;
1da177e4
LT		 570} timedia_data[] = {
571 { 1, timedia_single_port },
572 { 2, timedia_dual_port },
573 { 4, timedia_quad_port },
e9422e09 574 { 8, timedia_eight_port }
1da177e4
LT		 575};
576
b9b24558
FB		 577/*
578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
579 * listing them individually, this driver merely grabs them all with
580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
581 * and should be left free to be claimed by parport_serial instead.
582 */
583static int pci_timedia_probe(struct pci_dev *dev)
584{
585 /*
586 * Check the third digit of the subdevice ID
587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
588 */
589 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
590 dev_info(&dev->dev,
591 "ignoring Timedia subdevice %04x for parport_serial\n",
592 dev->subsystem_device);
593 return -ENODEV;
594 }
595
596 return 0;
597}
598
61a116ef 599static int pci_timedia_init(struct pci_dev *dev)
1da177e4 600{
e9422e09 601 const unsigned short *ids;
1da177e4
LT		 602 int i, j;
603
e9422e09 604 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 605 ids = timedia_data[i].ids;
606 for (j = 0; ids[j]; j++)
607 if (dev->subsystem_device == ids[j])
608 return timedia_data[i].num;
609 }
610 return 0;
611}
612
613/*
614 * Timedia/SUNIX uses a mixture of BARs and offsets
615 * Ugh, this is ugly as all hell --- TYT
616 */
617static int
975a1a7d
RK		 618pci_timedia_setup(struct serial_private *priv,
619 const struct pciserial_board *board,
2655a2c7 620 struct uart_8250_port *port, int idx)
1da177e4
LT		 621{
622 unsigned int bar = 0, offset = board->first_offset;
623
624 switch (idx) {
625 case 0:
626 bar = 0;
627 break;
628 case 1:
629 offset = board->uart_offset;
630 bar = 0;
631 break;
632 case 2:
633 bar = 1;
634 break;
635 case 3:
636 offset = board->uart_offset;
c2cd6d3c 637 /* FALLTHROUGH */
1da177e4
LT		 638 case 4: /* BAR 2 */
639 case 5: /* BAR 3 */
640 case 6: /* BAR 4 */
641 case 7: /* BAR 5 */
642 bar = idx - 2;
643 }
644
70db3d91 645 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 646}
647
648/*
649 * Some Titan cards are also a little weird
650 */
651static int
70db3d91 652titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 653 const struct pciserial_board *board,
2655a2c7 654 struct uart_8250_port *port, int idx)
1da177e4
LT		 655{
656 unsigned int bar, offset = board->first_offset;
657
658 switch (idx) {
659 case 0:
660 bar = 1;
661 break;
662 case 1:
663 bar = 2;
664 break;
665 default:
666 bar = 4;
667 offset = (idx - 2) * board->uart_offset;
668 }
669
70db3d91 670 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 671}
672
61a116ef 673static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 674{
675 msleep(100);
676 return 0;
677}
678
04bf7e74
WP		 679static int pci_ni8420_init(struct pci_dev *dev)
680{
681 void __iomem *p;
682 unsigned long base, len;
683 unsigned int bar = 0;
684
685 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
686 moan_device("no memory in bar", dev);
687 return 0;
688 }
689
690 base = pci_resource_start(dev, bar);
691 len = pci_resource_len(dev, bar);
692 p = ioremap_nocache(base, len);
693 if (p == NULL)
694 return -ENOMEM;
695
696 /* Enable CPU Interrupt */
697 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
698 p + NI8420_INT_ENABLE_REG);
699
700 iounmap(p);
701 return 0;
702}
703
46a0fac9
SB		 704#define MITE_IOWBSR1_WSIZE 0xa
705#define MITE_IOWBSR1_WIN_OFFSET 0x800
706#define MITE_IOWBSR1_WENAB (1 << 7)
707#define MITE_LCIMR1_IO_IE_0 (1 << 24)
708#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
709#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
710
711static int pci_ni8430_init(struct pci_dev *dev)
712{
713 void __iomem *p;
714 unsigned long base, len;
715 u32 device_window;
716 unsigned int bar = 0;
717
718 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
719 moan_device("no memory in bar", dev);
720 return 0;
721 }
722
723 base = pci_resource_start(dev, bar);
724 len = pci_resource_len(dev, bar);
725 p = ioremap_nocache(base, len);
726 if (p == NULL)
727 return -ENOMEM;
728
729 /* Set device window address and size in BAR0 */
730 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
731 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
732 writel(device_window, p + MITE_IOWBSR1);
733
734 /* Set window access to go to RAMSEL IO address space */
735 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
736 p + MITE_IOWCR1);
737
738 /* Enable IO Bus Interrupt 0 */
739 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
740
741 /* Enable CPU Interrupt */
742 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
743
744 iounmap(p);
745 return 0;
746}
747
748/* UART Port Control Register */
749#define NI8430_PORTCON 0x0f
750#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
751
752static int
bf538fe4
AC		 753pci_ni8430_setup(struct serial_private *priv,
754 const struct pciserial_board *board,
2655a2c7 755 struct uart_8250_port *port, int idx)
46a0fac9
SB		 756{
757 void __iomem *p;
758 unsigned long base, len;
759 unsigned int bar, offset = board->first_offset;
760
761 if (idx >= board->num_ports)
762 return 1;
763
764 bar = FL_GET_BASE(board->flags);
765 offset += idx * board->uart_offset;
766
767 base = pci_resource_start(priv->dev, bar);
768 len = pci_resource_len(priv->dev, bar);
769 p = ioremap_nocache(base, len);
770
7c9d440e 771 /* enable the transceiver */
46a0fac9
SB		 772 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
773 p + offset + NI8430_PORTCON);
774
775 iounmap(p);
776
777 return setup_port(priv, port, bar, offset, board->reg_shift);
778}
779
7808edcd
NG		 780static int pci_netmos_9900_setup(struct serial_private *priv,
781 const struct pciserial_board *board,
2655a2c7 782 struct uart_8250_port *port, int idx)
7808edcd
NG		 783{
784 unsigned int bar;
785
333c085e
DES		 786 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
787 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
7808edcd
NG		 788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797}
798
799/* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807static int pci_netmos_9900_numports(struct pci_dev *dev)
808{
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
af8c5b8d 829 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
7808edcd
NG		 830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836}
46a0fac9 837
61a116ef 838static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 839{
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
ac6ec5b1
IS		 843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 845 return 0;
7808edcd 846
25cf9bc1
JS		 847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
7808edcd
NG		 851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
1da177e4
LT		 865 if (num_serial == 0)
866 return -ENODEV;
7808edcd 867
1da177e4
LT		 868 return num_serial;
869}
870
84f8c6fc 871/*
84f8c6fc
NV		 872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881/* registers */
882#define ITE_887x_MISCR 0x9c
883#define ITE_887x_INTCBAR 0x78
884#define ITE_887x_UARTBAR 0x7c
885#define ITE_887x_PS0BAR 0x10
886#define ITE_887x_POSIO0 0x60
887
888/* I/O space size */
889#define ITE_887x_IOSIZE 32
890/* I/O space size (bits 26-24; 8 bytes = 011b) */
891#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892/* I/O space size (bits 26-24; 32 bytes = 101b) */
893#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895#define ITE_887x_POSIO_SPEED (3 << 29)
896/* enable IO_Space bit */
897#define ITE_887x_POSIO_ENABLE (1 << 31)
898
f79abb82 899static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 900{
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
5756ee99
AC		 919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
84f8c6fc
NV		 921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
af8c5b8d 933 dev_err(&dev->dev, "ite887x: could not find iobase\n");
84f8c6fc
NV		 934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991}
992
ae8d8a14 993static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 994{
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000}
1001
9f2a036a
RK		 1002/*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008{
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
af8c5b8d 1026 dev_dbg(&dev->dev,
9f2a036a 1027 "%d ports detected on Oxford PCI Express device\n",
af8c5b8d 1028 number_uarts);
9f2a036a
RK		 1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032}
1033
eb26dfe8
AC		 1034static int pci_asix_setup(struct serial_private *priv,
1035 const struct pciserial_board *board,
1036 struct uart_8250_port *port, int idx)
1037{
1038 port->bugs |= UART_BUG_PARITY;
1039 return pci_default_setup(priv, board, port, idx);
1040}
1041
55c7c0fd
AC		 1042/* Quatech devices have their own extra interface features */
1043
1044struct quatech_feature {
1045 u16 devid;
1046 bool amcc;
1047};
1048
1049#define QPCR_TEST_FOR1 0x3F
1050#define QPCR_TEST_GET1 0x00
1051#define QPCR_TEST_FOR2 0x40
1052#define QPCR_TEST_GET2 0x40
1053#define QPCR_TEST_FOR3 0x80
1054#define QPCR_TEST_GET3 0x40
1055#define QPCR_TEST_FOR4 0xC0
1056#define QPCR_TEST_GET4 0x80
1057
1058#define QOPR_CLOCK_X1 0x0000
1059#define QOPR_CLOCK_X2 0x0001
1060#define QOPR_CLOCK_X4 0x0002
1061#define QOPR_CLOCK_X8 0x0003
1062#define QOPR_CLOCK_RATE_MASK 0x0003
1063
1064
1065static struct quatech_feature quatech_cards[] = {
1066 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1067 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1068 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1069 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1070 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1071 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1072 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1073 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1074 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1075 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1076 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1077 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1078 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1079 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1082 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1083 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1084 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1085 { 0, }
1086};
1087
1088static int pci_quatech_amcc(u16 devid)
1089{
1090 struct quatech_feature *qf = &quatech_cards[0];
1091 while (qf->devid) {
1092 if (qf->devid == devid)
1093 return qf->amcc;
1094 qf++;
1095 }
1096 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1097 return 0;
1098};
1099
1100static int pci_quatech_rqopr(struct uart_8250_port *port)
1101{
1102 unsigned long base = port->port.iobase;
1103 u8 LCR, val;
1104
1105 LCR = inb(base + UART_LCR);
1106 outb(0xBF, base + UART_LCR);
1107 val = inb(base + UART_SCR);
1108 outb(LCR, base + UART_LCR);
1109 return val;
1110}
1111
1112static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1113{
1114 unsigned long base = port->port.iobase;
1115 u8 LCR, val;
1116
1117 LCR = inb(base + UART_LCR);
1118 outb(0xBF, base + UART_LCR);
1119 val = inb(base + UART_SCR);
1120 outb(qopr, base + UART_SCR);
1121 outb(LCR, base + UART_LCR);
1122}
1123
1124static int pci_quatech_rqmcr(struct uart_8250_port *port)
1125{
1126 unsigned long base = port->port.iobase;
1127 u8 LCR, val, qmcr;
1128
1129 LCR = inb(base + UART_LCR);
1130 outb(0xBF, base + UART_LCR);
1131 val = inb(base + UART_SCR);
1132 outb(val | 0x10, base + UART_SCR);
1133 qmcr = inb(base + UART_MCR);
1134 outb(val, base + UART_SCR);
1135 outb(LCR, base + UART_LCR);
1136
1137 return qmcr;
1138}
1139
1140static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1141{
1142 unsigned long base = port->port.iobase;
1143 u8 LCR, val;
1144
1145 LCR = inb(base + UART_LCR);
1146 outb(0xBF, base + UART_LCR);
1147 val = inb(base + UART_SCR);
1148 outb(val | 0x10, base + UART_SCR);
1149 outb(qmcr, base + UART_MCR);
1150 outb(val, base + UART_SCR);
1151 outb(LCR, base + UART_LCR);
1152}
1153
1154static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1155{
1156 unsigned long base = port->port.iobase;
1157 u8 LCR, val;
1158
1159 LCR = inb(base + UART_LCR);
1160 outb(0xBF, base + UART_LCR);
1161 val = inb(base + UART_SCR);
1162 if (val & 0x20) {
1163 outb(0x80, UART_LCR);
1164 if (!(inb(UART_SCR) & 0x20)) {
1165 outb(LCR, base + UART_LCR);
1166 return 1;
1167 }
1168 }
1169 return 0;
1170}
1171
1172static int pci_quatech_test(struct uart_8250_port *port)
1173{
1174 u8 reg;
1175 u8 qopr = pci_quatech_rqopr(port);
1176 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1177 reg = pci_quatech_rqopr(port) & 0xC0;
1178 if (reg != QPCR_TEST_GET1)
1179 return -EINVAL;
1180 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1181 reg = pci_quatech_rqopr(port) & 0xC0;
1182 if (reg != QPCR_TEST_GET2)
1183 return -EINVAL;
1184 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1185 reg = pci_quatech_rqopr(port) & 0xC0;
1186 if (reg != QPCR_TEST_GET3)
1187 return -EINVAL;
1188 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1189 reg = pci_quatech_rqopr(port) & 0xC0;
1190 if (reg != QPCR_TEST_GET4)
1191 return -EINVAL;
1192
1193 pci_quatech_wqopr(port, qopr);
1194 return 0;
1195}
1196
1197static int pci_quatech_clock(struct uart_8250_port *port)
1198{
1199 u8 qopr, reg, set;
1200 unsigned long clock;
1201
1202 if (pci_quatech_test(port) < 0)
1203 return 1843200;
1204
1205 qopr = pci_quatech_rqopr(port);
1206
1207 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1208 reg = pci_quatech_rqopr(port);
1209 if (reg & QOPR_CLOCK_X8) {
1210 clock = 1843200;
1211 goto out;
1212 }
1213 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1214 reg = pci_quatech_rqopr(port);
1215 if (!(reg & QOPR_CLOCK_X8)) {
1216 clock = 1843200;
1217 goto out;
1218 }
1219 reg &= QOPR_CLOCK_X8;
1220 if (reg == QOPR_CLOCK_X2) {
1221 clock = 3685400;
1222 set = QOPR_CLOCK_X2;
1223 } else if (reg == QOPR_CLOCK_X4) {
1224 clock = 7372800;
1225 set = QOPR_CLOCK_X4;
1226 } else if (reg == QOPR_CLOCK_X8) {
1227 clock = 14745600;
1228 set = QOPR_CLOCK_X8;
1229 } else {
1230 clock = 1843200;
1231 set = QOPR_CLOCK_X1;
1232 }
1233 qopr &= ~QOPR_CLOCK_RATE_MASK;
1234 qopr |= set;
1235
1236out:
1237 pci_quatech_wqopr(port, qopr);
1238 return clock;
1239}
1240
1241static int pci_quatech_rs422(struct uart_8250_port *port)
1242{
1243 u8 qmcr;
1244 int rs422 = 0;
1245
1246 if (!pci_quatech_has_qmcr(port))
1247 return 0;
1248 qmcr = pci_quatech_rqmcr(port);
1249 pci_quatech_wqmcr(port, 0xFF);
1250 if (pci_quatech_rqmcr(port))
1251 rs422 = 1;
1252 pci_quatech_wqmcr(port, qmcr);
1253 return rs422;
1254}
1255
1256static int pci_quatech_init(struct pci_dev *dev)
1257{
1258 if (pci_quatech_amcc(dev->device)) {
1259 unsigned long base = pci_resource_start(dev, 0);
1260 if (base) {
1261 u32 tmp;
9c5320f8 1262 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
55c7c0fd
AC		 1263 tmp = inl(base + 0x3c);
1264 outl(tmp | 0x01000000, base + 0x3c);
9c5320f8 1265 outl(tmp &= ~0x01000000, base + 0x3c);
55c7c0fd
AC		 1266 }
1267 }
1268 return 0;
1269}
1270
1271static int pci_quatech_setup(struct serial_private *priv,
1272 const struct pciserial_board *board,
1273 struct uart_8250_port *port, int idx)
1274{
1275 /* Needed by pci_quatech calls below */
1276 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1277 /* Set up the clocking */
1278 port->port.uartclk = pci_quatech_clock(port);
1279 /* For now just warn about RS422 */
1280 if (pci_quatech_rs422(port))
1281 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1282 return pci_default_setup(priv, board, port, idx);
1283}
1284
d73dfc6a 1285static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1286{
1287}
1288
eb26dfe8 1289static int pci_default_setup(struct serial_private *priv,
975a1a7d 1290 const struct pciserial_board *board,
2655a2c7 1291 struct uart_8250_port *port, int idx)
1da177e4
LT		 1292{
1293 unsigned int bar, offset = board->first_offset, maxnr;
1294
1295 bar = FL_GET_BASE(board->flags);
1296 if (board->flags & FL_BASE_BARS)
1297 bar += idx;
1298 else
1299 offset += idx * board->uart_offset;
1300
2427ddd8
GKH		 1301 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1302 (board->reg_shift + 3);
1da177e4
LT		 1303
1304 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1305 return 1;
5756ee99 1306
70db3d91 1307 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1308}
1309
94341475
AB		 1310static int pci_pericom_setup(struct serial_private *priv,
1311 const struct pciserial_board *board,
1312 struct uart_8250_port *port, int idx)
1313{
1314 unsigned int bar, offset = board->first_offset, maxnr;
1315
1316 bar = FL_GET_BASE(board->flags);
1317 if (board->flags & FL_BASE_BARS)
1318 bar += idx;
1319 else
1320 offset += idx * board->uart_offset;
1321
1322 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1323 (board->reg_shift + 3);
1324
1325 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1326 return 1;
1327
1328 port->port.uartclk = 14745600;
1329
1330 return setup_port(priv, port, bar, offset, board->reg_shift);
1331}
1332
095e24b0
DB		 1333static int
1334ce4100_serial_setup(struct serial_private *priv,
1335 const struct pciserial_board *board,
2655a2c7 1336 struct uart_8250_port *port, int idx)
095e24b0
DB		 1337{
1338 int ret;
1339
08ec212c 1340 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1341 port->port.iotype = UPIO_MEM32;
1342 port->port.type = PORT_XSCALE;
1343 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344 port->port.regshift = 2;
095e24b0
DB		 1345
1346 return ret;
1347}
1348
b15e5691
HK		 1349#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1350#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1351
1352#define BYT_PRV_CLK 0x800
1353#define BYT_PRV_CLK_EN (1 << 0)
1354#define BYT_PRV_CLK_M_VAL_SHIFT 1
1355#define BYT_PRV_CLK_N_VAL_SHIFT 16
1356#define BYT_PRV_CLK_UPDATE (1 << 31)
1357
1358#define BYT_GENERAL_REG 0x808
1359#define BYT_GENERAL_DIS_RTS_N_OVERRIDE (1 << 3)
1360
1361#define BYT_TX_OVF_INT 0x820
1362#define BYT_TX_OVF_INT_MASK (1 << 1)
1363
1364static void
1365byt_set_termios(struct uart_port *p, struct ktermios *termios,
1366 struct ktermios *old)
1367{
1368 unsigned int baud = tty_termios_baud_rate(termios);
50825c57 1369 unsigned int m, n;
b15e5691
HK		 1370 u32 reg;
1371
50825c57
AS		 1372 /*
1373 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1374 * dividers must be adjusted.
1375 *
1376 * uartclk = (m / n) * 100 MHz, where m <= n
1377 */
1378 switch (baud) {
1379 case 500000:
1380 case 1000000:
1381 case 2000000:
1382 case 4000000:
b15e5691
HK		 1383 m = 64;
1384 n = 100;
b15e5691 1385 p->uartclk = 64000000;
50825c57
AS		 1386 break;
1387 case 3500000:
1388 m = 56;
1389 n = 100;
1390 p->uartclk = 56000000;
1391 break;
1392 case 1500000:
1393 case 3000000:
b15e5691
HK		 1394 m = 48;
1395 n = 100;
b15e5691 1396 p->uartclk = 48000000;
50825c57
AS		 1397 break;
1398 case 2500000:
1399 m = 40;
1400 n = 100;
1401 p->uartclk = 40000000;
1402 break;
1403 default:
1404 m = 6912;
1405 n = 15625;
b15e5691
HK		 1406 p->uartclk = 44236800;
1407 }
1408
1409 /* Reset the clock */
1410 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1411 writel(reg, p->membase + BYT_PRV_CLK);
1412 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1413 writel(reg, p->membase + BYT_PRV_CLK);
1414
1415 /*
1416 * If auto-handshake mechanism is not enabled,
1417 * disable rts_n override
1418 */
1419 reg = readl(p->membase + BYT_GENERAL_REG);
1420 reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1421 if (termios->c_cflag & CRTSCTS)
1422 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1423 writel(reg, p->membase + BYT_GENERAL_REG);
1424
1425 serial8250_do_set_termios(p, termios, old);
1426}
1427
1428static bool byt_dma_filter(struct dma_chan *chan, void *param)
1429{
1430 return chan->chan_id == *(int *)param;
1431}
1432
1433static int
1434byt_serial_setup(struct serial_private *priv,
1435 const struct pciserial_board *board,
1436 struct uart_8250_port *port, int idx)
1437{
1438 struct uart_8250_dma *dma;
1439 int ret;
1440
1441 dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL);
1442 if (!dma)
1443 return -ENOMEM;
1444
1445 switch (priv->dev->device) {
1446 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1447 dma->rx_chan_id = 3;
1448 dma->tx_chan_id = 2;
1449 break;
1450 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1451 dma->rx_chan_id = 5;
1452 dma->tx_chan_id = 4;
1453 break;
1454 default:
1455 return -EINVAL;
1456 }
1457
1458 dma->rxconf.slave_id = dma->rx_chan_id;
1459 dma->rxconf.src_maxburst = 16;
1460
1461 dma->txconf.slave_id = dma->tx_chan_id;
1462 dma->txconf.dst_maxburst = 16;
1463
1464 dma->fn = byt_dma_filter;
1465 dma->rx_param = &dma->rx_chan_id;
1466 dma->tx_param = &dma->tx_chan_id;
1467
1468 ret = pci_default_setup(priv, board, port, idx);
1469 port->port.iotype = UPIO_MEM;
1470 port->port.type = PORT_16550A;
1471 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1472 port->port.set_termios = byt_set_termios;
1473 port->port.fifosize = 64;
1474 port->tx_loadsz = 64;
1475 port->dma = dma;
1476 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1477
1478 /* Disable Tx counter interrupts */
1479 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1480
1481 return ret;
1482}
1483
d9a0fbfd
AP		 1484static int
1485pci_omegapci_setup(struct serial_private *priv,
1798ca13 1486 const struct pciserial_board *board,
2655a2c7 1487 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1488{
1489 return setup_port(priv, port, 2, idx * 8, 0);
1490}
1491
ebebd49a
SH		 1492static int
1493pci_brcm_trumanage_setup(struct serial_private *priv,
1494 const struct pciserial_board *board,
1495 struct uart_8250_port *port, int idx)
1496{
1497 int ret = pci_default_setup(priv, board, port, idx);
1498
1499 port->port.type = PORT_BRCM_TRUMANAGE;
1500 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1501 return ret;
1502}
1503
2c62a3c8
GKH		 1504static int pci_fintek_setup(struct serial_private *priv,
1505 const struct pciserial_board *board,
1506 struct uart_8250_port *port, int idx)
1507{
1508 struct pci_dev *pdev = priv->dev;
1509 unsigned long base;
1510 unsigned long iobase;
1511 unsigned long ciobase = 0;
1512 u8 config_base;
1513
1514 /*
1515 * We are supposed to be able to read these from the PCI config space,
1516 * but the values there don't seem to match what we need to use, so
1517 * just use these hard-coded values for now, as they are correct.
1518 */
1519 switch (idx) {
1520 case 0: iobase = 0xe000; config_base = 0x40; break;
1521 case 1: iobase = 0xe008; config_base = 0x48; break;
1522 case 2: iobase = 0xe010; config_base = 0x50; break;
1523 case 3: iobase = 0xe018; config_base = 0x58; break;
1524 case 4: iobase = 0xe020; config_base = 0x60; break;
1525 case 5: iobase = 0xe028; config_base = 0x68; break;
1526 case 6: iobase = 0xe030; config_base = 0x70; break;
1527 case 7: iobase = 0xe038; config_base = 0x78; break;
1528 case 8: iobase = 0xe040; config_base = 0x80; break;
1529 case 9: iobase = 0xe048; config_base = 0x88; break;
1530 case 10: iobase = 0xe050; config_base = 0x90; break;
1531 case 11: iobase = 0xe058; config_base = 0x98; break;
1532 default:
1533 /* Unknown number of ports, get out of here */
1534 return -EINVAL;
1535 }
1536
1537 if (idx < 4) {
1538 base = pci_resource_start(priv->dev, 3);
1539 ciobase = (int)(base + (0x8 * idx));
1540 }
1541
1542 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1543 __func__, idx, iobase, ciobase, config_base);
1544
1545 /* Enable UART I/O port */
1546 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1547
1548 /* Select 128-byte FIFO and 8x FIFO threshold */
1549 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1550
1551 /* LSB UART */
1552 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1553
1554 /* MSB UART */
1555 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1556
1557 /* irq number, this usually fails, but the spec says to do it anyway. */
1558 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1559
1560 port->port.iotype = UPIO_PORT;
1561 port->port.iobase = iobase;
1562 port->port.mapbase = 0;
1563 port->port.membase = NULL;
1564 port->port.regshift = 0;
1565
1566 return 0;
1567}
1568
b6adea33
MCC		 1569static int skip_tx_en_setup(struct serial_private *priv,
1570 const struct pciserial_board *board,
2655a2c7 1571 struct uart_8250_port *port, int idx)
b6adea33 1572{
2655a2c7 1573 port->port.flags |= UPF_NO_TXEN_TEST;
af8c5b8d
GKH		 1574 dev_dbg(&priv->dev->dev,
1575 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1576 priv->dev->vendor, priv->dev->device,
1577 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
b6adea33
MCC		 1578
1579 return pci_default_setup(priv, board, port, idx);
1580}
1581
0ad372b9
SM		 1582static void kt_handle_break(struct uart_port *p)
1583{
1584 struct uart_8250_port *up =
1585 container_of(p, struct uart_8250_port, port);
1586 /*
1587 * On receipt of a BI, serial device in Intel ME (Intel
1588 * management engine) needs to have its fifos cleared for sane
1589 * SOL (Serial Over Lan) output.
1590 */
1591 serial8250_clear_and_reinit_fifos(up);
1592}
1593
1594static unsigned int kt_serial_in(struct uart_port *p, int offset)
1595{
1596 struct uart_8250_port *up =
1597 container_of(p, struct uart_8250_port, port);
1598 unsigned int val;
1599
1600 /*
1601 * When the Intel ME (management engine) gets reset its serial
1602 * port registers could return 0 momentarily. Functions like
1603 * serial8250_console_write, read and save the IER, perform
1604 * some operation and then restore it. In order to avoid
1605 * setting IER register inadvertently to 0, if the value read
1606 * is 0, double check with ier value in uart_8250_port and use
1607 * that instead. up->ier should be the same value as what is
1608 * currently configured.
1609 */
1610 val = inb(p->iobase + offset);
1611 if (offset == UART_IER) {
1612 if (val == 0)
1613 val = up->ier;
1614 }
1615 return val;
1616}
1617
bc02d15a
DW		 1618static int kt_serial_setup(struct serial_private *priv,
1619 const struct pciserial_board *board,
2655a2c7 1620 struct uart_8250_port *port, int idx)
bc02d15a 1621{
2655a2c7
AC		 1622 port->port.flags |= UPF_BUG_THRE;
1623 port->port.serial_in = kt_serial_in;
1624 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1625 return skip_tx_en_setup(priv, board, port, idx);
1626}
1627
eb7073db
TM		 1628static int pci_eg20t_init(struct pci_dev *dev)
1629{
1630#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1631 return -ENODEV;
1632#else
1633 return 0;
1634#endif
1635}
1636
06315348
SH		 1637static int
1638pci_xr17c154_setup(struct serial_private *priv,
1639 const struct pciserial_board *board,
2655a2c7 1640 struct uart_8250_port *port, int idx)
06315348 1641{
2655a2c7 1642 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1643 return pci_default_setup(priv, board, port, idx);
1644}
1645
dc96efb7
MS		 1646static int
1647pci_xr17v35x_setup(struct serial_private *priv,
1648 const struct pciserial_board *board,
1649 struct uart_8250_port *port, int idx)
1650{
1651 u8 __iomem *p;
1652
1653 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1654 if (p == NULL)
1655 return -ENOMEM;
dc96efb7
MS		 1656
1657 port->port.flags |= UPF_EXAR_EFR;
1658
1659 /*
1660 * Setup Multipurpose Input/Output pins.
1661 */
1662 if (idx == 0) {
1663 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1664 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1665 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1666 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1667 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1668 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1669 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1670 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1671 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1672 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1673 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1674 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1675 }
f965b9c4
MS		 1676 writeb(0x00, p + UART_EXAR_8XMODE);
1677 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1678 writeb(128, p + UART_EXAR_TXTRG);
1679 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1680 iounmap(p);
1681
1682 return pci_default_setup(priv, board, port, idx);
1683}
1684
14faa8cc
MS		 1685#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1686#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1687#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1688#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1689
1690static int
1691pci_fastcom335_setup(struct serial_private *priv,
1692 const struct pciserial_board *board,
1693 struct uart_8250_port *port, int idx)
1694{
1695 u8 __iomem *p;
1696
1697 p = pci_ioremap_bar(priv->dev, 0);
1698 if (p == NULL)
1699 return -ENOMEM;
1700
1701 port->port.flags |= UPF_EXAR_EFR;
1702
1703 /*
1704 * Setup Multipurpose Input/Output pins.
1705 */
1706 if (idx == 0) {
1707 switch (priv->dev->device) {
1708 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1709 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1710 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1711 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1712 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1713 break;
1714 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1715 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1716 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1717 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1718 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1719 break;
1720 }
1721 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1722 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1723 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1724 }
1725 writeb(0x00, p + UART_EXAR_8XMODE);
1726 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1727 writeb(32, p + UART_EXAR_TXTRG);
1728 writeb(32, p + UART_EXAR_RXTRG);
1729 iounmap(p);
1730
1731 return pci_default_setup(priv, board, port, idx);
1732}
1733
6971c635
GA		 1734static int
1735pci_wch_ch353_setup(struct serial_private *priv,
1736 const struct pciserial_board *board,
1737 struct uart_8250_port *port, int idx)
1738{
1739 port->port.flags |= UPF_FIXED_TYPE;
1740 port->port.type = PORT_16550A;
06315348
SH		 1741 return pci_default_setup(priv, board, port, idx);
1742}
1743
1da177e4
LT		 1744#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1745#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1746#define PCI_DEVICE_ID_OCTPRO 0x0001
1747#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1748#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1749#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1750#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 1751#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1752#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 1753#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1754#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1755#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1756#define PCI_DEVICE_ID_TITAN_200I 0x8028
1757#define PCI_DEVICE_ID_TITAN_400I 0x8048
1758#define PCI_DEVICE_ID_TITAN_800I 0x8088
1759#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1760#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1761#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1762#define PCI_DEVICE_ID_TITAN_100E 0xA010
1763#define PCI_DEVICE_ID_TITAN_200E 0xA012
1764#define PCI_DEVICE_ID_TITAN_400E 0xA013
1765#define PCI_DEVICE_ID_TITAN_800E 0xA014
1766#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1767#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
48c0247d 1768#define PCI_DEVICE_ID_TITAN_200V3 0xA306
1e9deb11
YY		 1769#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1770#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1771#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1772#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1773#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1774#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1775#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1776#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 1777#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 1778#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 1779#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1780#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1781#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 1782#define PCI_VENDOR_ID_AGESTAR 0x5372
1783#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 1784#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 1785#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1786#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 1787#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 1788#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
57c1f0e9 1789#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
14faa8cc 1790
abd7baca
SC		 1791#define PCI_VENDOR_ID_SUNIX 0x1fd4
1792#define PCI_DEVICE_ID_SUNIX_1999 0x1999
1793
1da177e4 1794
b76c5a07
CB		 1795/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1796#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 1797#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 1798
1da177e4
LT		 1799/*
1800 * Master list of serial port init/setup/exit quirks.
1801 * This does not describe the general nature of the port.
1802 * (ie, baud base, number and location of ports, etc)
1803 *
1804 * This list is ordered alphabetically by vendor then device.
1805 * Specific entries must come before more generic entries.
1806 */
7a63ce5a 1807static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1808 /*
1809 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1810 */
1811 {
086231f7 1812 .vendor = PCI_VENDOR_ID_AMCC,
57c1f0e9 1813 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 1814 .subvendor = PCI_ANY_ID,
1815 .subdevice = PCI_ANY_ID,
1816 .setup = addidata_apci7800_setup,
1817 },
1da177e4 1818 /*
61a116ef 1819 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1820 * It is not clear whether this applies to all products.
1821 */
1822 {
1823 .vendor = PCI_VENDOR_ID_AFAVLAB,
1824 .device = PCI_ANY_ID,
1825 .subvendor = PCI_ANY_ID,
1826 .subdevice = PCI_ANY_ID,
1827 .setup = afavlab_setup,
1828 },
1829 /*
1830 * HP Diva
1831 */
1832 {
1833 .vendor = PCI_VENDOR_ID_HP,
1834 .device = PCI_DEVICE_ID_HP_DIVA,
1835 .subvendor = PCI_ANY_ID,
1836 .subdevice = PCI_ANY_ID,
1837 .init = pci_hp_diva_init,
1838 .setup = pci_hp_diva_setup,
1839 },
1840 /*
1841 * Intel
1842 */
1843 {
1844 .vendor = PCI_VENDOR_ID_INTEL,
1845 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1846 .subvendor = 0xe4bf,
1847 .subdevice = PCI_ANY_ID,
1848 .init = pci_inteli960ni_init,
1849 .setup = pci_default_setup,
1850 },
b6adea33
MCC		 1851 {
1852 .vendor = PCI_VENDOR_ID_INTEL,
1853 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1854 .subvendor = PCI_ANY_ID,
1855 .subdevice = PCI_ANY_ID,
1856 .setup = skip_tx_en_setup,
1857 },
1858 {
1859 .vendor = PCI_VENDOR_ID_INTEL,
1860 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1861 .subvendor = PCI_ANY_ID,
1862 .subdevice = PCI_ANY_ID,
1863 .setup = skip_tx_en_setup,
1864 },
1865 {
1866 .vendor = PCI_VENDOR_ID_INTEL,
1867 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1868 .subvendor = PCI_ANY_ID,
1869 .subdevice = PCI_ANY_ID,
1870 .setup = skip_tx_en_setup,
1871 },
095e24b0
DB		 1872 {
1873 .vendor = PCI_VENDOR_ID_INTEL,
1874 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1875 .subvendor = PCI_ANY_ID,
1876 .subdevice = PCI_ANY_ID,
1877 .setup = ce4100_serial_setup,
1878 },
bc02d15a
DW		 1879 {
1880 .vendor = PCI_VENDOR_ID_INTEL,
1881 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1882 .subvendor = PCI_ANY_ID,
1883 .subdevice = PCI_ANY_ID,
1884 .setup = kt_serial_setup,
1885 },
b15e5691
HK		 1886 {
1887 .vendor = PCI_VENDOR_ID_INTEL,
1888 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1889 .subvendor = PCI_ANY_ID,
1890 .subdevice = PCI_ANY_ID,
1891 .setup = byt_serial_setup,
1892 },
1893 {
1894 .vendor = PCI_VENDOR_ID_INTEL,
1895 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1896 .subvendor = PCI_ANY_ID,
1897 .subdevice = PCI_ANY_ID,
1898 .setup = byt_serial_setup,
1899 },
84f8c6fc
NV		 1900 /*
1901 * ITE
1902 */
1903 {
1904 .vendor = PCI_VENDOR_ID_ITE,
1905 .device = PCI_DEVICE_ID_ITE_8872,
1906 .subvendor = PCI_ANY_ID,
1907 .subdevice = PCI_ANY_ID,
1908 .init = pci_ite887x_init,
1909 .setup = pci_default_setup,
2d47b716 1910 .exit = pci_ite887x_exit,
84f8c6fc 1911 },
46a0fac9
SB		 1912 /*
1913 * National Instruments
1914 */
04bf7e74
WP		 1915 {
1916 .vendor = PCI_VENDOR_ID_NI,
1917 .device = PCI_DEVICE_ID_NI_PCI23216,
1918 .subvendor = PCI_ANY_ID,
1919 .subdevice = PCI_ANY_ID,
1920 .init = pci_ni8420_init,
1921 .setup = pci_default_setup,
2d47b716 1922 .exit = pci_ni8420_exit,
04bf7e74
WP		 1923 },
1924 {
1925 .vendor = PCI_VENDOR_ID_NI,
1926 .device = PCI_DEVICE_ID_NI_PCI2328,
1927 .subvendor = PCI_ANY_ID,
1928 .subdevice = PCI_ANY_ID,
1929 .init = pci_ni8420_init,
1930 .setup = pci_default_setup,
2d47b716 1931 .exit = pci_ni8420_exit,
04bf7e74
WP		 1932 },
1933 {
1934 .vendor = PCI_VENDOR_ID_NI,
1935 .device = PCI_DEVICE_ID_NI_PCI2324,
1936 .subvendor = PCI_ANY_ID,
1937 .subdevice = PCI_ANY_ID,
1938 .init = pci_ni8420_init,
1939 .setup = pci_default_setup,
2d47b716 1940 .exit = pci_ni8420_exit,
04bf7e74
WP		 1941 },
1942 {
1943 .vendor = PCI_VENDOR_ID_NI,
1944 .device = PCI_DEVICE_ID_NI_PCI2322,
1945 .subvendor = PCI_ANY_ID,
1946 .subdevice = PCI_ANY_ID,
1947 .init = pci_ni8420_init,
1948 .setup = pci_default_setup,
2d47b716 1949 .exit = pci_ni8420_exit,
04bf7e74
WP		 1950 },
1951 {
1952 .vendor = PCI_VENDOR_ID_NI,
1953 .device = PCI_DEVICE_ID_NI_PCI2324I,
1954 .subvendor = PCI_ANY_ID,
1955 .subdevice = PCI_ANY_ID,
1956 .init = pci_ni8420_init,
1957 .setup = pci_default_setup,
2d47b716 1958 .exit = pci_ni8420_exit,
04bf7e74
WP		 1959 },
1960 {
1961 .vendor = PCI_VENDOR_ID_NI,
1962 .device = PCI_DEVICE_ID_NI_PCI2322I,
1963 .subvendor = PCI_ANY_ID,
1964 .subdevice = PCI_ANY_ID,
1965 .init = pci_ni8420_init,
1966 .setup = pci_default_setup,
2d47b716 1967 .exit = pci_ni8420_exit,
04bf7e74
WP		 1968 },
1969 {
1970 .vendor = PCI_VENDOR_ID_NI,
1971 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1972 .subvendor = PCI_ANY_ID,
1973 .subdevice = PCI_ANY_ID,
1974 .init = pci_ni8420_init,
1975 .setup = pci_default_setup,
2d47b716 1976 .exit = pci_ni8420_exit,
04bf7e74
WP		 1977 },
1978 {
1979 .vendor = PCI_VENDOR_ID_NI,
1980 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1981 .subvendor = PCI_ANY_ID,
1982 .subdevice = PCI_ANY_ID,
1983 .init = pci_ni8420_init,
1984 .setup = pci_default_setup,
2d47b716 1985 .exit = pci_ni8420_exit,
04bf7e74
WP		 1986 },
1987 {
1988 .vendor = PCI_VENDOR_ID_NI,
1989 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1990 .subvendor = PCI_ANY_ID,
1991 .subdevice = PCI_ANY_ID,
1992 .init = pci_ni8420_init,
1993 .setup = pci_default_setup,
2d47b716 1994 .exit = pci_ni8420_exit,
04bf7e74
WP		 1995 },
1996 {
1997 .vendor = PCI_VENDOR_ID_NI,
1998 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1999 .subvendor = PCI_ANY_ID,
2000 .subdevice = PCI_ANY_ID,
2001 .init = pci_ni8420_init,
2002 .setup = pci_default_setup,
2d47b716 2003 .exit = pci_ni8420_exit,
04bf7e74
WP		 2004 },
2005 {
2006 .vendor = PCI_VENDOR_ID_NI,
2007 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2008 .subvendor = PCI_ANY_ID,
2009 .subdevice = PCI_ANY_ID,
2010 .init = pci_ni8420_init,
2011 .setup = pci_default_setup,
2d47b716 2012 .exit = pci_ni8420_exit,
04bf7e74
WP		 2013 },
2014 {
2015 .vendor = PCI_VENDOR_ID_NI,
2016 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2017 .subvendor = PCI_ANY_ID,
2018 .subdevice = PCI_ANY_ID,
2019 .init = pci_ni8420_init,
2020 .setup = pci_default_setup,
2d47b716 2021 .exit = pci_ni8420_exit,
04bf7e74 2022 },
46a0fac9
SB		 2023 {
2024 .vendor = PCI_VENDOR_ID_NI,
2025 .device = PCI_ANY_ID,
2026 .subvendor = PCI_ANY_ID,
2027 .subdevice = PCI_ANY_ID,
2028 .init = pci_ni8430_init,
2029 .setup = pci_ni8430_setup,
2d47b716 2030 .exit = pci_ni8430_exit,
46a0fac9 2031 },
55c7c0fd
AC		 2032 /* Quatech */
2033 {
2034 .vendor = PCI_VENDOR_ID_QUATECH,
2035 .device = PCI_ANY_ID,
2036 .subvendor = PCI_ANY_ID,
2037 .subdevice = PCI_ANY_ID,
2038 .init = pci_quatech_init,
2039 .setup = pci_quatech_setup,
d73dfc6a 2040 .exit = pci_quatech_exit,
55c7c0fd 2041 },
1da177e4
LT		 2042 /*
2043 * Panacom
2044 */
2045 {
2046 .vendor = PCI_VENDOR_ID_PANACOM,
2047 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2048 .subvendor = PCI_ANY_ID,
2049 .subdevice = PCI_ANY_ID,
2050 .init = pci_plx9050_init,
2051 .setup = pci_default_setup,
2d47b716 2052 .exit = pci_plx9050_exit,
5756ee99 2053 },
1da177e4
LT		 2054 {
2055 .vendor = PCI_VENDOR_ID_PANACOM,
2056 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2057 .subvendor = PCI_ANY_ID,
2058 .subdevice = PCI_ANY_ID,
2059 .init = pci_plx9050_init,
2060 .setup = pci_default_setup,
2d47b716 2061 .exit = pci_plx9050_exit,
1da177e4 2062 },
94341475
AB		 2063 /*
2064 * Pericom
2065 */
2066 {
2067 .vendor = 0x12d8,
2068 .device = 0x7952,
2069 .subvendor = PCI_ANY_ID,
2070 .subdevice = PCI_ANY_ID,
2071 .setup = pci_pericom_setup,
2072 },
2073 {
2074 .vendor = 0x12d8,
2075 .device = 0x7954,
2076 .subvendor = PCI_ANY_ID,
2077 .subdevice = PCI_ANY_ID,
2078 .setup = pci_pericom_setup,
2079 },
2080 {
2081 .vendor = 0x12d8,
2082 .device = 0x7958,
2083 .subvendor = PCI_ANY_ID,
2084 .subdevice = PCI_ANY_ID,
2085 .setup = pci_pericom_setup,
2086 },
2087
1da177e4
LT		 2088 /*
2089 * PLX
2090 */
48212008
TH		 2091 {
2092 .vendor = PCI_VENDOR_ID_PLX,
2093 .device = PCI_DEVICE_ID_PLX_9030,
2094 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2095 .subdevice = PCI_ANY_ID,
2096 .setup = pci_default_setup,
2097 },
add7b58e
BH		 2098 {
2099 .vendor = PCI_VENDOR_ID_PLX,
2100 .device = PCI_DEVICE_ID_PLX_9050,
2101 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2102 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2103 .init = pci_plx9050_init,
2104 .setup = pci_default_setup,
2d47b716 2105 .exit = pci_plx9050_exit,
add7b58e 2106 },
1da177e4
LT		 2107 {
2108 .vendor = PCI_VENDOR_ID_PLX,
2109 .device = PCI_DEVICE_ID_PLX_9050,
2110 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2111 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2112 .init = pci_plx9050_init,
2113 .setup = pci_default_setup,
2d47b716 2114 .exit = pci_plx9050_exit,
1da177e4
LT		 2115 },
2116 {
2117 .vendor = PCI_VENDOR_ID_PLX,
2118 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2119 .subvendor = PCI_VENDOR_ID_PLX,
2120 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2121 .init = pci_plx9050_init,
2122 .setup = pci_default_setup,
2d47b716 2123 .exit = pci_plx9050_exit,
1da177e4
LT		 2124 },
2125 /*
2126 * SBS Technologies, Inc., PMC-OCTALPRO 232
2127 */
2128 {
2129 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2130 .device = PCI_DEVICE_ID_OCTPRO,
2131 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2132 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2133 .init = sbs_init,
2134 .setup = sbs_setup,
2d47b716 2135 .exit = sbs_exit,
1da177e4
LT		 2136 },
2137 /*
2138 * SBS Technologies, Inc., PMC-OCTALPRO 422
2139 */
2140 {
2141 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2142 .device = PCI_DEVICE_ID_OCTPRO,
2143 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2144 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2145 .init = sbs_init,
2146 .setup = sbs_setup,
2d47b716 2147 .exit = sbs_exit,
1da177e4
LT		 2148 },
2149 /*
2150 * SBS Technologies, Inc., P-Octal 232
2151 */
2152 {
2153 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2154 .device = PCI_DEVICE_ID_OCTPRO,
2155 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2156 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2157 .init = sbs_init,
2158 .setup = sbs_setup,
2d47b716 2159 .exit = sbs_exit,
1da177e4
LT		 2160 },
2161 /*
2162 * SBS Technologies, Inc., P-Octal 422
2163 */
2164 {
2165 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2166 .device = PCI_DEVICE_ID_OCTPRO,
2167 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2168 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2169 .init = sbs_init,
2170 .setup = sbs_setup,
2d47b716 2171 .exit = sbs_exit,
1da177e4 2172 },
1da177e4 2173 /*
61a116ef 2174 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 2175 */
2176 {
2177 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 2178 .device = PCI_ANY_ID,
1da177e4
LT		 2179 .subvendor = PCI_ANY_ID,
2180 .subdevice = PCI_ANY_ID,
67d74b87 2181 .init = pci_siig_init,
3ec9c594 2182 .setup = pci_siig_setup,
1da177e4
LT		 2183 },
2184 /*
2185 * Titan cards
2186 */
2187 {
2188 .vendor = PCI_VENDOR_ID_TITAN,
2189 .device = PCI_DEVICE_ID_TITAN_400L,
2190 .subvendor = PCI_ANY_ID,
2191 .subdevice = PCI_ANY_ID,
2192 .setup = titan_400l_800l_setup,
2193 },
2194 {
2195 .vendor = PCI_VENDOR_ID_TITAN,
2196 .device = PCI_DEVICE_ID_TITAN_800L,
2197 .subvendor = PCI_ANY_ID,
2198 .subdevice = PCI_ANY_ID,
2199 .setup = titan_400l_800l_setup,
2200 },
2201 /*
2202 * Timedia cards
2203 */
2204 {
2205 .vendor = PCI_VENDOR_ID_TIMEDIA,
2206 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2207 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2208 .subdevice = PCI_ANY_ID,
b9b24558 2209 .probe = pci_timedia_probe,
1da177e4
LT		 2210 .init = pci_timedia_init,
2211 .setup = pci_timedia_setup,
2212 },
2213 {
2214 .vendor = PCI_VENDOR_ID_TIMEDIA,
2215 .device = PCI_ANY_ID,
2216 .subvendor = PCI_ANY_ID,
2217 .subdevice = PCI_ANY_ID,
2218 .setup = pci_timedia_setup,
2219 },
abd7baca
SC		 2220 /*
2221 * SUNIX (Timedia) cards
2222 * Do not "probe" for these cards as there is at least one combination
2223 * card that should be handled by parport_pc that doesn't match the
2224 * rule in pci_timedia_probe.
2225 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2226 * There are some boards with part number SER5037AL that report
2227 * subdevice ID 0x0002.
2228 */
2229 {
2230 .vendor = PCI_VENDOR_ID_SUNIX,
2231 .device = PCI_DEVICE_ID_SUNIX_1999,
2232 .subvendor = PCI_VENDOR_ID_SUNIX,
2233 .subdevice = PCI_ANY_ID,
2234 .init = pci_timedia_init,
2235 .setup = pci_timedia_setup,
2236 },
06315348
SH		 2237 /*
2238 * Exar cards
2239 */
2240 {
2241 .vendor = PCI_VENDOR_ID_EXAR,
2242 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2243 .subvendor = PCI_ANY_ID,
2244 .subdevice = PCI_ANY_ID,
2245 .setup = pci_xr17c154_setup,
2246 },
2247 {
2248 .vendor = PCI_VENDOR_ID_EXAR,
2249 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2250 .subvendor = PCI_ANY_ID,
2251 .subdevice = PCI_ANY_ID,
2252 .setup = pci_xr17c154_setup,
2253 },
2254 {
2255 .vendor = PCI_VENDOR_ID_EXAR,
2256 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2257 .subvendor = PCI_ANY_ID,
2258 .subdevice = PCI_ANY_ID,
2259 .setup = pci_xr17c154_setup,
2260 },
dc96efb7
MS		 2261 {
2262 .vendor = PCI_VENDOR_ID_EXAR,
2263 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2264 .subvendor = PCI_ANY_ID,
2265 .subdevice = PCI_ANY_ID,
2266 .setup = pci_xr17v35x_setup,
2267 },
2268 {
2269 .vendor = PCI_VENDOR_ID_EXAR,
2270 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2271 .subvendor = PCI_ANY_ID,
2272 .subdevice = PCI_ANY_ID,
2273 .setup = pci_xr17v35x_setup,
2274 },
2275 {
2276 .vendor = PCI_VENDOR_ID_EXAR,
2277 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2278 .subvendor = PCI_ANY_ID,
2279 .subdevice = PCI_ANY_ID,
2280 .setup = pci_xr17v35x_setup,
2281 },
1da177e4
LT		 2282 /*
2283 * Xircom cards
2284 */
2285 {
2286 .vendor = PCI_VENDOR_ID_XIRCOM,
2287 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2288 .subvendor = PCI_ANY_ID,
2289 .subdevice = PCI_ANY_ID,
2290 .init = pci_xircom_init,
2291 .setup = pci_default_setup,
2292 },
2293 /*
61a116ef 2294 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2295 */
2296 {
2297 .vendor = PCI_VENDOR_ID_NETMOS,
2298 .device = PCI_ANY_ID,
2299 .subvendor = PCI_ANY_ID,
2300 .subdevice = PCI_ANY_ID,
2301 .init = pci_netmos_init,
7808edcd 2302 .setup = pci_netmos_9900_setup,
1da177e4 2303 },
9f2a036a 2304 /*
aa273ae5 2305 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2306 */
2307 {
2308 .vendor = PCI_VENDOR_ID_OXSEMI,
2309 .device = PCI_ANY_ID,
2310 .subvendor = PCI_ANY_ID,
2311 .subdevice = PCI_ANY_ID,
2312 .init = pci_oxsemi_tornado_init,
2313 .setup = pci_default_setup,
2314 },
2315 {
2316 .vendor = PCI_VENDOR_ID_MAINPINE,
2317 .device = PCI_ANY_ID,
2318 .subvendor = PCI_ANY_ID,
2319 .subdevice = PCI_ANY_ID,
2320 .init = pci_oxsemi_tornado_init,
2321 .setup = pci_default_setup,
2322 },
aa273ae5
SK		 2323 {
2324 .vendor = PCI_VENDOR_ID_DIGI,
2325 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2326 .subvendor = PCI_SUBVENDOR_ID_IBM,
2327 .subdevice = PCI_ANY_ID,
2328 .init = pci_oxsemi_tornado_init,
2329 .setup = pci_default_setup,
2330 },
eb7073db
TM		 2331 {
2332 .vendor = PCI_VENDOR_ID_INTEL,
2333 .device = 0x8811,
aaa10eb1
AP		 2334 .subvendor = PCI_ANY_ID,
2335 .subdevice = PCI_ANY_ID,
eb7073db 2336 .init = pci_eg20t_init,
64d91cfa 2337 .setup = pci_default_setup,
eb7073db
TM		 2338 },
2339 {
2340 .vendor = PCI_VENDOR_ID_INTEL,
2341 .device = 0x8812,
aaa10eb1
AP		 2342 .subvendor = PCI_ANY_ID,
2343 .subdevice = PCI_ANY_ID,
eb7073db 2344 .init = pci_eg20t_init,
64d91cfa 2345 .setup = pci_default_setup,
eb7073db
TM		 2346 },
2347 {
2348 .vendor = PCI_VENDOR_ID_INTEL,
2349 .device = 0x8813,
aaa10eb1
AP		 2350 .subvendor = PCI_ANY_ID,
2351 .subdevice = PCI_ANY_ID,
eb7073db 2352 .init = pci_eg20t_init,
64d91cfa 2353 .setup = pci_default_setup,
eb7073db
TM		 2354 },
2355 {
2356 .vendor = PCI_VENDOR_ID_INTEL,
2357 .device = 0x8814,
aaa10eb1
AP		 2358 .subvendor = PCI_ANY_ID,
2359 .subdevice = PCI_ANY_ID,
eb7073db 2360 .init = pci_eg20t_init,
64d91cfa 2361 .setup = pci_default_setup,
eb7073db
TM		 2362 },
2363 {
2364 .vendor = 0x10DB,
2365 .device = 0x8027,
aaa10eb1
AP		 2366 .subvendor = PCI_ANY_ID,
2367 .subdevice = PCI_ANY_ID,
eb7073db 2368 .init = pci_eg20t_init,
64d91cfa 2369 .setup = pci_default_setup,
eb7073db
TM		 2370 },
2371 {
2372 .vendor = 0x10DB,
2373 .device = 0x8028,
aaa10eb1
AP		 2374 .subvendor = PCI_ANY_ID,
2375 .subdevice = PCI_ANY_ID,
eb7073db 2376 .init = pci_eg20t_init,
64d91cfa 2377 .setup = pci_default_setup,
eb7073db
TM		 2378 },
2379 {
2380 .vendor = 0x10DB,
2381 .device = 0x8029,
aaa10eb1
AP		 2382 .subvendor = PCI_ANY_ID,
2383 .subdevice = PCI_ANY_ID,
eb7073db 2384 .init = pci_eg20t_init,
64d91cfa 2385 .setup = pci_default_setup,
eb7073db
TM		 2386 },
2387 {
2388 .vendor = 0x10DB,
2389 .device = 0x800C,
aaa10eb1
AP		 2390 .subvendor = PCI_ANY_ID,
2391 .subdevice = PCI_ANY_ID,
eb7073db 2392 .init = pci_eg20t_init,
64d91cfa 2393 .setup = pci_default_setup,
eb7073db
TM		 2394 },
2395 {
2396 .vendor = 0x10DB,
2397 .device = 0x800D,
aaa10eb1
AP		 2398 .subvendor = PCI_ANY_ID,
2399 .subdevice = PCI_ANY_ID,
eb7073db 2400 .init = pci_eg20t_init,
64d91cfa 2401 .setup = pci_default_setup,
eb7073db 2402 },
d9a0fbfd
AP		 2403 /*
2404 * Cronyx Omega PCI (PLX-chip based)
2405 */
2406 {
2407 .vendor = PCI_VENDOR_ID_PLX,
2408 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2409 .subvendor = PCI_ANY_ID,
2410 .subdevice = PCI_ANY_ID,
2411 .setup = pci_omegapci_setup,
eb26dfe8 2412 },
6971c635
GA		 2413 /* WCH CH353 2S1P card (16550 clone) */
2414 {
27788c5f
AC		 2415 .vendor = PCI_VENDOR_ID_WCH,
2416 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2417 .subvendor = PCI_ANY_ID,
2418 .subdevice = PCI_ANY_ID,
2419 .setup = pci_wch_ch353_setup,
2420 },
2421 /* WCH CH353 4S card (16550 clone) */
2422 {
2423 .vendor = PCI_VENDOR_ID_WCH,
2424 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2425 .subvendor = PCI_ANY_ID,
2426 .subdevice = PCI_ANY_ID,
2427 .setup = pci_wch_ch353_setup,
2428 },
2429 /* WCH CH353 2S1PF card (16550 clone) */
2430 {
2431 .vendor = PCI_VENDOR_ID_WCH,
2432 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2433 .subvendor = PCI_ANY_ID,
2434 .subdevice = PCI_ANY_ID,
6971c635
GA		 2435 .setup = pci_wch_ch353_setup,
2436 },
8b5c913f
WY		 2437 /* WCH CH352 2S card (16550 clone) */
2438 {
2439 .vendor = PCI_VENDOR_ID_WCH,
2440 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2441 .subvendor = PCI_ANY_ID,
2442 .subdevice = PCI_ANY_ID,
2443 .setup = pci_wch_ch353_setup,
2444 },
eb26dfe8
AC		 2445 /*
2446 * ASIX devices with FIFO bug
2447 */
2448 {
2449 .vendor = PCI_VENDOR_ID_ASIX,
2450 .device = PCI_ANY_ID,
2451 .subvendor = PCI_ANY_ID,
2452 .subdevice = PCI_ANY_ID,
2453 .setup = pci_asix_setup,
2454 },
14faa8cc
MS		 2455 /*
2456 * Commtech, Inc. Fastcom adapters
2457 *
2458 */
2459 {
2460 .vendor = PCI_VENDOR_ID_COMMTECH,
2461 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2462 .subvendor = PCI_ANY_ID,
2463 .subdevice = PCI_ANY_ID,
2464 .setup = pci_fastcom335_setup,
2465 },
2466 {
2467 .vendor = PCI_VENDOR_ID_COMMTECH,
2468 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2469 .subvendor = PCI_ANY_ID,
2470 .subdevice = PCI_ANY_ID,
2471 .setup = pci_fastcom335_setup,
2472 },
2473 {
2474 .vendor = PCI_VENDOR_ID_COMMTECH,
2475 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2476 .subvendor = PCI_ANY_ID,
2477 .subdevice = PCI_ANY_ID,
2478 .setup = pci_fastcom335_setup,
2479 },
2480 {
2481 .vendor = PCI_VENDOR_ID_COMMTECH,
2482 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2483 .subvendor = PCI_ANY_ID,
2484 .subdevice = PCI_ANY_ID,
2485 .setup = pci_fastcom335_setup,
2486 },
2487 {
2488 .vendor = PCI_VENDOR_ID_COMMTECH,
2489 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2490 .subvendor = PCI_ANY_ID,
2491 .subdevice = PCI_ANY_ID,
2492 .setup = pci_xr17v35x_setup,
2493 },
2494 {
2495 .vendor = PCI_VENDOR_ID_COMMTECH,
2496 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2497 .subvendor = PCI_ANY_ID,
2498 .subdevice = PCI_ANY_ID,
2499 .setup = pci_xr17v35x_setup,
2500 },
2501 {
2502 .vendor = PCI_VENDOR_ID_COMMTECH,
2503 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2504 .subvendor = PCI_ANY_ID,
2505 .subdevice = PCI_ANY_ID,
2506 .setup = pci_xr17v35x_setup,
2507 },
ebebd49a
SH		 2508 /*
2509 * Broadcom TruManage (NetXtreme)
2510 */
2511 {
2512 .vendor = PCI_VENDOR_ID_BROADCOM,
2513 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2514 .subvendor = PCI_ANY_ID,
2515 .subdevice = PCI_ANY_ID,
2516 .setup = pci_brcm_trumanage_setup,
2517 },
2c62a3c8
GKH		 2518 {
2519 .vendor = 0x1c29,
2520 .device = 0x1104,
2521 .subvendor = PCI_ANY_ID,
2522 .subdevice = PCI_ANY_ID,
2523 .setup = pci_fintek_setup,
2524 },
2525 {
2526 .vendor = 0x1c29,
2527 .device = 0x1108,
2528 .subvendor = PCI_ANY_ID,
2529 .subdevice = PCI_ANY_ID,
2530 .setup = pci_fintek_setup,
2531 },
2532 {
2533 .vendor = 0x1c29,
2534 .device = 0x1112,
2535 .subvendor = PCI_ANY_ID,
2536 .subdevice = PCI_ANY_ID,
2537 .setup = pci_fintek_setup,
2538 },
ebebd49a 2539
1da177e4
LT		 2540 /*
2541 * Default "match everything" terminator entry
2542 */
2543 {
2544 .vendor = PCI_ANY_ID,
2545 .device = PCI_ANY_ID,
2546 .subvendor = PCI_ANY_ID,
2547 .subdevice = PCI_ANY_ID,
2548 .setup = pci_default_setup,
2549 }
2550};
2551
2552static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2553{
2554 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2555}
2556
2557static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2558{
2559 struct pci_serial_quirk *quirk;
2560
2561 for (quirk = pci_serial_quirks; ; quirk++)
2562 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2563 quirk_id_matches(quirk->device, dev->device) &&
2564 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2565 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2566 break;
1da177e4
LT		 2567 return quirk;
2568}
2569
dd68e88c 2570static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2571 const struct pciserial_board *board)
1da177e4
LT		 2572{
2573 if (board->flags & FL_NOIRQ)
2574 return 0;
2575 else
2576 return dev->irq;
2577}
2578
2579/*
2580 * This is the configuration table for all of the PCI serial boards
2581 * which we support. It is directly indexed by the pci_board_num_t enum
2582 * value, which is encoded in the pci_device_id PCI probe table's
2583 * driver_data member.
2584 *
2585 * The makeup of these names are:
26e92861 2586 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2587 *
26e92861
GH		 2588 * bn = PCI BAR number
2589 * bt = Index using PCI BARs
2590 * n = number of serial ports
2591 * baud = baud rate
2592 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2593 *
26e92861 2594 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2595 *
1da177e4
LT		 2596 * Please note: in theory if n = 1, _bt infix should make no difference.
2597 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2598 */
2599enum pci_board_num_t {
2600 pbn_default = 0,
2601
2602 pbn_b0_1_115200,
2603 pbn_b0_2_115200,
2604 pbn_b0_4_115200,
2605 pbn_b0_5_115200,
bf0df636 2606 pbn_b0_8_115200,
1da177e4
LT		 2607
2608 pbn_b0_1_921600,
2609 pbn_b0_2_921600,
2610 pbn_b0_4_921600,
2611
db1de159
DR		 2612 pbn_b0_2_1130000,
2613
fbc0dc0d
AP		 2614 pbn_b0_4_1152000,
2615
14faa8cc
MS		 2616 pbn_b0_2_1152000_200,
2617 pbn_b0_4_1152000_200,
2618 pbn_b0_8_1152000_200,
2619
26e92861
GH		 2620 pbn_b0_2_1843200,
2621 pbn_b0_4_1843200,
2622
2623 pbn_b0_2_1843200_200,
2624 pbn_b0_4_1843200_200,
2625 pbn_b0_8_1843200_200,
2626
7106b4e3
LH		 2627 pbn_b0_1_4000000,
2628
1da177e4
LT		 2629 pbn_b0_bt_1_115200,
2630 pbn_b0_bt_2_115200,
ac6ec5b1 2631 pbn_b0_bt_4_115200,
1da177e4
LT		 2632 pbn_b0_bt_8_115200,
2633
2634 pbn_b0_bt_1_460800,
2635 pbn_b0_bt_2_460800,
2636 pbn_b0_bt_4_460800,
2637
2638 pbn_b0_bt_1_921600,
2639 pbn_b0_bt_2_921600,
2640 pbn_b0_bt_4_921600,
2641 pbn_b0_bt_8_921600,
2642
2643 pbn_b1_1_115200,
2644 pbn_b1_2_115200,
2645 pbn_b1_4_115200,
2646 pbn_b1_8_115200,
04bf7e74 2647 pbn_b1_16_115200,
1da177e4
LT		 2648
2649 pbn_b1_1_921600,
2650 pbn_b1_2_921600,
2651 pbn_b1_4_921600,
2652 pbn_b1_8_921600,
2653
26e92861
GH		 2654 pbn_b1_2_1250000,
2655
84f8c6fc 2656 pbn_b1_bt_1_115200,
04bf7e74
WP		 2657 pbn_b1_bt_2_115200,
2658 pbn_b1_bt_4_115200,
2659
1da177e4
LT		 2660 pbn_b1_bt_2_921600,
2661
2662 pbn_b1_1_1382400,
2663 pbn_b1_2_1382400,
2664 pbn_b1_4_1382400,
2665 pbn_b1_8_1382400,
2666
2667 pbn_b2_1_115200,
737c1756 2668 pbn_b2_2_115200,
a9cccd34 2669 pbn_b2_4_115200,
1da177e4
LT		 2670 pbn_b2_8_115200,
2671
2672 pbn_b2_1_460800,
2673 pbn_b2_4_460800,
2674 pbn_b2_8_460800,
2675 pbn_b2_16_460800,
2676
2677 pbn_b2_1_921600,
2678 pbn_b2_4_921600,
2679 pbn_b2_8_921600,
2680
e847003f
LB		 2681 pbn_b2_8_1152000,
2682
1da177e4
LT		 2683 pbn_b2_bt_1_115200,
2684 pbn_b2_bt_2_115200,
2685 pbn_b2_bt_4_115200,
2686
2687 pbn_b2_bt_2_921600,
2688 pbn_b2_bt_4_921600,
2689
d9004eb4 2690 pbn_b3_2_115200,
1da177e4
LT		 2691 pbn_b3_4_115200,
2692 pbn_b3_8_115200,
2693
66169ad1
YY		 2694 pbn_b4_bt_2_921600,
2695 pbn_b4_bt_4_921600,
2696 pbn_b4_bt_8_921600,
2697
1da177e4
LT		 2698 /*
2699 * Board-specific versions.
2700 */
2701 pbn_panacom,
2702 pbn_panacom2,
2703 pbn_panacom4,
2704 pbn_plx_romulus,
2705 pbn_oxsemi,
7106b4e3
LH		 2706 pbn_oxsemi_1_4000000,
2707 pbn_oxsemi_2_4000000,
2708 pbn_oxsemi_4_4000000,
2709 pbn_oxsemi_8_4000000,
1da177e4
LT		 2710 pbn_intel_i960,
2711 pbn_sgi_ioc3,
1da177e4
LT		 2712 pbn_computone_4,
2713 pbn_computone_6,
2714 pbn_computone_8,
2715 pbn_sbsxrsio,
2716 pbn_exar_XR17C152,
2717 pbn_exar_XR17C154,
2718 pbn_exar_XR17C158,
dc96efb7
MS		 2719 pbn_exar_XR17V352,
2720 pbn_exar_XR17V354,
2721 pbn_exar_XR17V358,
c68d2b15 2722 pbn_exar_ibm_saturn,
aa798505 2723 pbn_pasemi_1682M,
46a0fac9
SB		 2724 pbn_ni8430_2,
2725 pbn_ni8430_4,
2726 pbn_ni8430_8,
2727 pbn_ni8430_16,
1b62cbf2
KJ		 2728 pbn_ADDIDATA_PCIe_1_3906250,
2729 pbn_ADDIDATA_PCIe_2_3906250,
2730 pbn_ADDIDATA_PCIe_4_3906250,
2731 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 2732 pbn_ce4100_1_115200,
b15e5691 2733 pbn_byt,
d9a0fbfd 2734 pbn_omegapci,
7808edcd 2735 pbn_NETMOS9900_2s_115200,
ebebd49a 2736 pbn_brcm_trumanage,
2c62a3c8
GKH		 2737 pbn_fintek_4,
2738 pbn_fintek_8,
2739 pbn_fintek_12,
1da177e4
LT		 2740};
2741
2742/*
2743 * uart_offset - the space between channels
2744 * reg_shift - describes how the UART registers are mapped
2745 * to PCI memory by the card.
2746 * For example IER register on SBS, Inc. PMC-OctPro is located at
2747 * offset 0x10 from the UART base, while UART_IER is defined as 1
2748 * in include/linux/serial_reg.h,
2749 * see first lines of serial_in() and serial_out() in 8250.c
2750*/
2751
de88b340 2752static struct pciserial_board pci_boards[] = {
1da177e4
LT		 2753 [pbn_default] = {
2754 .flags = FL_BASE0,
2755 .num_ports = 1,
2756 .base_baud = 115200,
2757 .uart_offset = 8,
2758 },
2759 [pbn_b0_1_115200] = {
2760 .flags = FL_BASE0,
2761 .num_ports = 1,
2762 .base_baud = 115200,
2763 .uart_offset = 8,
2764 },
2765 [pbn_b0_2_115200] = {
2766 .flags = FL_BASE0,
2767 .num_ports = 2,
2768 .base_baud = 115200,
2769 .uart_offset = 8,
2770 },
2771 [pbn_b0_4_115200] = {
2772 .flags = FL_BASE0,
2773 .num_ports = 4,
2774 .base_baud = 115200,
2775 .uart_offset = 8,
2776 },
2777 [pbn_b0_5_115200] = {
2778 .flags = FL_BASE0,
2779 .num_ports = 5,
2780 .base_baud = 115200,
2781 .uart_offset = 8,
2782 },
bf0df636
AC		 2783 [pbn_b0_8_115200] = {
2784 .flags = FL_BASE0,
2785 .num_ports = 8,
2786 .base_baud = 115200,
2787 .uart_offset = 8,
2788 },
1da177e4
LT		 2789 [pbn_b0_1_921600] = {
2790 .flags = FL_BASE0,
2791 .num_ports = 1,
2792 .base_baud = 921600,
2793 .uart_offset = 8,
2794 },
2795 [pbn_b0_2_921600] = {
2796 .flags = FL_BASE0,
2797 .num_ports = 2,
2798 .base_baud = 921600,
2799 .uart_offset = 8,
2800 },
2801 [pbn_b0_4_921600] = {
2802 .flags = FL_BASE0,
2803 .num_ports = 4,
2804 .base_baud = 921600,
2805 .uart_offset = 8,
2806 },
db1de159
DR		 2807
2808 [pbn_b0_2_1130000] = {
2809 .flags = FL_BASE0,
2810 .num_ports = 2,
2811 .base_baud = 1130000,
2812 .uart_offset = 8,
2813 },
2814
fbc0dc0d
AP		 2815 [pbn_b0_4_1152000] = {
2816 .flags = FL_BASE0,
2817 .num_ports = 4,
2818 .base_baud = 1152000,
2819 .uart_offset = 8,
2820 },
1da177e4 2821
14faa8cc
MS		 2822 [pbn_b0_2_1152000_200] = {
2823 .flags = FL_BASE0,
2824 .num_ports = 2,
2825 .base_baud = 1152000,
2826 .uart_offset = 0x200,
2827 },
2828
2829 [pbn_b0_4_1152000_200] = {
2830 .flags = FL_BASE0,
2831 .num_ports = 4,
2832 .base_baud = 1152000,
2833 .uart_offset = 0x200,
2834 },
2835
2836 [pbn_b0_8_1152000_200] = {
2837 .flags = FL_BASE0,
4f7d67d0 2838 .num_ports = 8,
14faa8cc
MS		 2839 .base_baud = 1152000,
2840 .uart_offset = 0x200,
2841 },
2842
26e92861
GH		 2843 [pbn_b0_2_1843200] = {
2844 .flags = FL_BASE0,
2845 .num_ports = 2,
2846 .base_baud = 1843200,
2847 .uart_offset = 8,
2848 },
2849 [pbn_b0_4_1843200] = {
2850 .flags = FL_BASE0,
2851 .num_ports = 4,
2852 .base_baud = 1843200,
2853 .uart_offset = 8,
2854 },
2855
2856 [pbn_b0_2_1843200_200] = {
2857 .flags = FL_BASE0,
2858 .num_ports = 2,
2859 .base_baud = 1843200,
2860 .uart_offset = 0x200,
2861 },
2862 [pbn_b0_4_1843200_200] = {
2863 .flags = FL_BASE0,
2864 .num_ports = 4,
2865 .base_baud = 1843200,
2866 .uart_offset = 0x200,
2867 },
2868 [pbn_b0_8_1843200_200] = {
2869 .flags = FL_BASE0,
2870 .num_ports = 8,
2871 .base_baud = 1843200,
2872 .uart_offset = 0x200,
2873 },
7106b4e3
LH		 2874 [pbn_b0_1_4000000] = {
2875 .flags = FL_BASE0,
2876 .num_ports = 1,
2877 .base_baud = 4000000,
2878 .uart_offset = 8,
2879 },
26e92861 2880
1da177e4
LT		 2881 [pbn_b0_bt_1_115200] = {
2882 .flags = FL_BASE0|FL_BASE_BARS,
2883 .num_ports = 1,
2884 .base_baud = 115200,
2885 .uart_offset = 8,
2886 },
2887 [pbn_b0_bt_2_115200] = {
2888 .flags = FL_BASE0|FL_BASE_BARS,
2889 .num_ports = 2,
2890 .base_baud = 115200,
2891 .uart_offset = 8,
2892 },
ac6ec5b1
IS		 2893 [pbn_b0_bt_4_115200] = {
2894 .flags = FL_BASE0|FL_BASE_BARS,
2895 .num_ports = 4,
2896 .base_baud = 115200,
2897 .uart_offset = 8,
2898 },
1da177e4
LT		 2899 [pbn_b0_bt_8_115200] = {
2900 .flags = FL_BASE0|FL_BASE_BARS,
2901 .num_ports = 8,
2902 .base_baud = 115200,
2903 .uart_offset = 8,
2904 },
2905
2906 [pbn_b0_bt_1_460800] = {
2907 .flags = FL_BASE0|FL_BASE_BARS,
2908 .num_ports = 1,
2909 .base_baud = 460800,
2910 .uart_offset = 8,
2911 },
2912 [pbn_b0_bt_2_460800] = {
2913 .flags = FL_BASE0|FL_BASE_BARS,
2914 .num_ports = 2,
2915 .base_baud = 460800,
2916 .uart_offset = 8,
2917 },
2918 [pbn_b0_bt_4_460800] = {
2919 .flags = FL_BASE0|FL_BASE_BARS,
2920 .num_ports = 4,
2921 .base_baud = 460800,
2922 .uart_offset = 8,
2923 },
2924
2925 [pbn_b0_bt_1_921600] = {
2926 .flags = FL_BASE0|FL_BASE_BARS,
2927 .num_ports = 1,
2928 .base_baud = 921600,
2929 .uart_offset = 8,
2930 },
2931 [pbn_b0_bt_2_921600] = {
2932 .flags = FL_BASE0|FL_BASE_BARS,
2933 .num_ports = 2,
2934 .base_baud = 921600,
2935 .uart_offset = 8,
2936 },
2937 [pbn_b0_bt_4_921600] = {
2938 .flags = FL_BASE0|FL_BASE_BARS,
2939 .num_ports = 4,
2940 .base_baud = 921600,
2941 .uart_offset = 8,
2942 },
2943 [pbn_b0_bt_8_921600] = {
2944 .flags = FL_BASE0|FL_BASE_BARS,
2945 .num_ports = 8,
2946 .base_baud = 921600,
2947 .uart_offset = 8,
2948 },
2949
2950 [pbn_b1_1_115200] = {
2951 .flags = FL_BASE1,
2952 .num_ports = 1,
2953 .base_baud = 115200,
2954 .uart_offset = 8,
2955 },
2956 [pbn_b1_2_115200] = {
2957 .flags = FL_BASE1,
2958 .num_ports = 2,
2959 .base_baud = 115200,
2960 .uart_offset = 8,
2961 },
2962 [pbn_b1_4_115200] = {
2963 .flags = FL_BASE1,
2964 .num_ports = 4,
2965 .base_baud = 115200,
2966 .uart_offset = 8,
2967 },
2968 [pbn_b1_8_115200] = {
2969 .flags = FL_BASE1,
2970 .num_ports = 8,
2971 .base_baud = 115200,
2972 .uart_offset = 8,
2973 },
04bf7e74
WP		 2974 [pbn_b1_16_115200] = {
2975 .flags = FL_BASE1,
2976 .num_ports = 16,
2977 .base_baud = 115200,
2978 .uart_offset = 8,
2979 },
1da177e4
LT		 2980
2981 [pbn_b1_1_921600] = {
2982 .flags = FL_BASE1,
2983 .num_ports = 1,
2984 .base_baud = 921600,
2985 .uart_offset = 8,
2986 },
2987 [pbn_b1_2_921600] = {
2988 .flags = FL_BASE1,
2989 .num_ports = 2,
2990 .base_baud = 921600,
2991 .uart_offset = 8,
2992 },
2993 [pbn_b1_4_921600] = {
2994 .flags = FL_BASE1,
2995 .num_ports = 4,
2996 .base_baud = 921600,
2997 .uart_offset = 8,
2998 },
2999 [pbn_b1_8_921600] = {
3000 .flags = FL_BASE1,
3001 .num_ports = 8,
3002 .base_baud = 921600,
3003 .uart_offset = 8,
3004 },
26e92861
GH		 3005 [pbn_b1_2_1250000] = {
3006 .flags = FL_BASE1,
3007 .num_ports = 2,
3008 .base_baud = 1250000,
3009 .uart_offset = 8,
3010 },
1da177e4 3011
84f8c6fc
NV		 3012 [pbn_b1_bt_1_115200] = {
3013 .flags = FL_BASE1|FL_BASE_BARS,
3014 .num_ports = 1,
3015 .base_baud = 115200,
3016 .uart_offset = 8,
3017 },
04bf7e74
WP		 3018 [pbn_b1_bt_2_115200] = {
3019 .flags = FL_BASE1|FL_BASE_BARS,
3020 .num_ports = 2,
3021 .base_baud = 115200,
3022 .uart_offset = 8,
3023 },
3024 [pbn_b1_bt_4_115200] = {
3025 .flags = FL_BASE1|FL_BASE_BARS,
3026 .num_ports = 4,
3027 .base_baud = 115200,
3028 .uart_offset = 8,
3029 },
84f8c6fc 3030
1da177e4
LT		 3031 [pbn_b1_bt_2_921600] = {
3032 .flags = FL_BASE1|FL_BASE_BARS,
3033 .num_ports = 2,
3034 .base_baud = 921600,
3035 .uart_offset = 8,
3036 },
3037
3038 [pbn_b1_1_1382400] = {
3039 .flags = FL_BASE1,
3040 .num_ports = 1,
3041 .base_baud = 1382400,
3042 .uart_offset = 8,
3043 },
3044 [pbn_b1_2_1382400] = {
3045 .flags = FL_BASE1,
3046 .num_ports = 2,
3047 .base_baud = 1382400,
3048 .uart_offset = 8,
3049 },
3050 [pbn_b1_4_1382400] = {
3051 .flags = FL_BASE1,
3052 .num_ports = 4,
3053 .base_baud = 1382400,
3054 .uart_offset = 8,
3055 },
3056 [pbn_b1_8_1382400] = {
3057 .flags = FL_BASE1,
3058 .num_ports = 8,
3059 .base_baud = 1382400,
3060 .uart_offset = 8,
3061 },
3062
3063 [pbn_b2_1_115200] = {
3064 .flags = FL_BASE2,
3065 .num_ports = 1,
3066 .base_baud = 115200,
3067 .uart_offset = 8,
3068 },
737c1756
PH		 3069 [pbn_b2_2_115200] = {
3070 .flags = FL_BASE2,
3071 .num_ports = 2,
3072 .base_baud = 115200,
3073 .uart_offset = 8,
3074 },
a9cccd34
MF		 3075 [pbn_b2_4_115200] = {
3076 .flags = FL_BASE2,
3077 .num_ports = 4,
3078 .base_baud = 115200,
3079 .uart_offset = 8,
3080 },
1da177e4
LT		 3081 [pbn_b2_8_115200] = {
3082 .flags = FL_BASE2,
3083 .num_ports = 8,
3084 .base_baud = 115200,
3085 .uart_offset = 8,
3086 },
3087
3088 [pbn_b2_1_460800] = {
3089 .flags = FL_BASE2,
3090 .num_ports = 1,
3091 .base_baud = 460800,
3092 .uart_offset = 8,
3093 },
3094 [pbn_b2_4_460800] = {
3095 .flags = FL_BASE2,
3096 .num_ports = 4,
3097 .base_baud = 460800,
3098 .uart_offset = 8,
3099 },
3100 [pbn_b2_8_460800] = {
3101 .flags = FL_BASE2,
3102 .num_ports = 8,
3103 .base_baud = 460800,
3104 .uart_offset = 8,
3105 },
3106 [pbn_b2_16_460800] = {
3107 .flags = FL_BASE2,
3108 .num_ports = 16,
3109 .base_baud = 460800,
3110 .uart_offset = 8,
3111 },
3112
3113 [pbn_b2_1_921600] = {
3114 .flags = FL_BASE2,
3115 .num_ports = 1,
3116 .base_baud = 921600,
3117 .uart_offset = 8,
3118 },
3119 [pbn_b2_4_921600] = {
3120 .flags = FL_BASE2,
3121 .num_ports = 4,
3122 .base_baud = 921600,
3123 .uart_offset = 8,
3124 },
3125 [pbn_b2_8_921600] = {
3126 .flags = FL_BASE2,
3127 .num_ports = 8,
3128 .base_baud = 921600,
3129 .uart_offset = 8,
3130 },
3131
e847003f
LB		 3132 [pbn_b2_8_1152000] = {
3133 .flags = FL_BASE2,
3134 .num_ports = 8,
3135 .base_baud = 1152000,
3136 .uart_offset = 8,
3137 },
3138
1da177e4
LT		 3139 [pbn_b2_bt_1_115200] = {
3140 .flags = FL_BASE2|FL_BASE_BARS,
3141 .num_ports = 1,
3142 .base_baud = 115200,
3143 .uart_offset = 8,
3144 },
3145 [pbn_b2_bt_2_115200] = {
3146 .flags = FL_BASE2|FL_BASE_BARS,
3147 .num_ports = 2,
3148 .base_baud = 115200,
3149 .uart_offset = 8,
3150 },
3151 [pbn_b2_bt_4_115200] = {
3152 .flags = FL_BASE2|FL_BASE_BARS,
3153 .num_ports = 4,
3154 .base_baud = 115200,
3155 .uart_offset = 8,
3156 },
3157
3158 [pbn_b2_bt_2_921600] = {
3159 .flags = FL_BASE2|FL_BASE_BARS,
3160 .num_ports = 2,
3161 .base_baud = 921600,
3162 .uart_offset = 8,
3163 },
3164 [pbn_b2_bt_4_921600] = {
3165 .flags = FL_BASE2|FL_BASE_BARS,
3166 .num_ports = 4,
3167 .base_baud = 921600,
3168 .uart_offset = 8,
3169 },
3170
d9004eb4
ABL		 3171 [pbn_b3_2_115200] = {
3172 .flags = FL_BASE3,
3173 .num_ports = 2,
3174 .base_baud = 115200,
3175 .uart_offset = 8,
3176 },
1da177e4
LT		 3177 [pbn_b3_4_115200] = {
3178 .flags = FL_BASE3,
3179 .num_ports = 4,
3180 .base_baud = 115200,
3181 .uart_offset = 8,
3182 },
3183 [pbn_b3_8_115200] = {
3184 .flags = FL_BASE3,
3185 .num_ports = 8,
3186 .base_baud = 115200,
3187 .uart_offset = 8,
3188 },
3189
66169ad1
YY		 3190 [pbn_b4_bt_2_921600] = {
3191 .flags = FL_BASE4,
3192 .num_ports = 2,
3193 .base_baud = 921600,
3194 .uart_offset = 8,
3195 },
3196 [pbn_b4_bt_4_921600] = {
3197 .flags = FL_BASE4,
3198 .num_ports = 4,
3199 .base_baud = 921600,
3200 .uart_offset = 8,
3201 },
3202 [pbn_b4_bt_8_921600] = {
3203 .flags = FL_BASE4,
3204 .num_ports = 8,
3205 .base_baud = 921600,
3206 .uart_offset = 8,
3207 },
3208
1da177e4
LT		 3209 /*
3210 * Entries following this are board-specific.
3211 */
3212
3213 /*
3214 * Panacom - IOMEM
3215 */
3216 [pbn_panacom] = {
3217 .flags = FL_BASE2,
3218 .num_ports = 2,
3219 .base_baud = 921600,
3220 .uart_offset = 0x400,
3221 .reg_shift = 7,
3222 },
3223 [pbn_panacom2] = {
3224 .flags = FL_BASE2|FL_BASE_BARS,
3225 .num_ports = 2,
3226 .base_baud = 921600,
3227 .uart_offset = 0x400,
3228 .reg_shift = 7,
3229 },
3230 [pbn_panacom4] = {
3231 .flags = FL_BASE2|FL_BASE_BARS,
3232 .num_ports = 4,
3233 .base_baud = 921600,
3234 .uart_offset = 0x400,
3235 .reg_shift = 7,
3236 },
3237
3238 /* I think this entry is broken - the first_offset looks wrong --rmk */
3239 [pbn_plx_romulus] = {
3240 .flags = FL_BASE2,
3241 .num_ports = 4,
3242 .base_baud = 921600,
3243 .uart_offset = 8 << 2,
3244 .reg_shift = 2,
3245 .first_offset = 0x03,
3246 },
3247
3248 /*
3249 * This board uses the size of PCI Base region 0 to
3250 * signal now many ports are available
3251 */
3252 [pbn_oxsemi] = {
3253 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3254 .num_ports = 32,
3255 .base_baud = 115200,
3256 .uart_offset = 8,
3257 },
7106b4e3
LH		 3258 [pbn_oxsemi_1_4000000] = {
3259 .flags = FL_BASE0,
3260 .num_ports = 1,
3261 .base_baud = 4000000,
3262 .uart_offset = 0x200,
3263 .first_offset = 0x1000,
3264 },
3265 [pbn_oxsemi_2_4000000] = {
3266 .flags = FL_BASE0,
3267 .num_ports = 2,
3268 .base_baud = 4000000,
3269 .uart_offset = 0x200,
3270 .first_offset = 0x1000,
3271 },
3272 [pbn_oxsemi_4_4000000] = {
3273 .flags = FL_BASE0,
3274 .num_ports = 4,
3275 .base_baud = 4000000,
3276 .uart_offset = 0x200,
3277 .first_offset = 0x1000,
3278 },
3279 [pbn_oxsemi_8_4000000] = {
3280 .flags = FL_BASE0,
3281 .num_ports = 8,
3282 .base_baud = 4000000,
3283 .uart_offset = 0x200,
3284 .first_offset = 0x1000,
3285 },
3286
1da177e4
LT		 3287
3288 /*
3289 * EKF addition for i960 Boards form EKF with serial port.
3290 * Max 256 ports.
3291 */
3292 [pbn_intel_i960] = {
3293 .flags = FL_BASE0,
3294 .num_ports = 32,
3295 .base_baud = 921600,
3296 .uart_offset = 8 << 2,
3297 .reg_shift = 2,
3298 .first_offset = 0x10000,
3299 },
3300 [pbn_sgi_ioc3] = {
3301 .flags = FL_BASE0|FL_NOIRQ,
3302 .num_ports = 1,
3303 .base_baud = 458333,
3304 .uart_offset = 8,
3305 .reg_shift = 0,
3306 .first_offset = 0x20178,
3307 },
3308
1da177e4
LT		 3309 /*
3310 * Computone - uses IOMEM.
3311 */
3312 [pbn_computone_4] = {
3313 .flags = FL_BASE0,
3314 .num_ports = 4,
3315 .base_baud = 921600,
3316 .uart_offset = 0x40,
3317 .reg_shift = 2,
3318 .first_offset = 0x200,
3319 },
3320 [pbn_computone_6] = {
3321 .flags = FL_BASE0,
3322 .num_ports = 6,
3323 .base_baud = 921600,
3324 .uart_offset = 0x40,
3325 .reg_shift = 2,
3326 .first_offset = 0x200,
3327 },
3328 [pbn_computone_8] = {
3329 .flags = FL_BASE0,
3330 .num_ports = 8,
3331 .base_baud = 921600,
3332 .uart_offset = 0x40,
3333 .reg_shift = 2,
3334 .first_offset = 0x200,
3335 },
3336 [pbn_sbsxrsio] = {
3337 .flags = FL_BASE0,
3338 .num_ports = 8,
3339 .base_baud = 460800,
3340 .uart_offset = 256,
3341 .reg_shift = 4,
3342 },
3343 /*
3344 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3345 * Only basic 16550A support.
3346 * XR17C15[24] are not tested, but they should work.
3347 */
3348 [pbn_exar_XR17C152] = {
3349 .flags = FL_BASE0,
3350 .num_ports = 2,
3351 .base_baud = 921600,
3352 .uart_offset = 0x200,
3353 },
3354 [pbn_exar_XR17C154] = {
3355 .flags = FL_BASE0,
3356 .num_ports = 4,
3357 .base_baud = 921600,
3358 .uart_offset = 0x200,
3359 },
3360 [pbn_exar_XR17C158] = {
3361 .flags = FL_BASE0,
3362 .num_ports = 8,
3363 .base_baud = 921600,
3364 .uart_offset = 0x200,
3365 },
dc96efb7
MS		 3366 [pbn_exar_XR17V352] = {
3367 .flags = FL_BASE0,
3368 .num_ports = 2,
3369 .base_baud = 7812500,
3370 .uart_offset = 0x400,
3371 .reg_shift = 0,
3372 .first_offset = 0,
3373 },
3374 [pbn_exar_XR17V354] = {
3375 .flags = FL_BASE0,
3376 .num_ports = 4,
3377 .base_baud = 7812500,
3378 .uart_offset = 0x400,
3379 .reg_shift = 0,
3380 .first_offset = 0,
3381 },
3382 [pbn_exar_XR17V358] = {
3383 .flags = FL_BASE0,
3384 .num_ports = 8,
3385 .base_baud = 7812500,
3386 .uart_offset = 0x400,
3387 .reg_shift = 0,
3388 .first_offset = 0,
3389 },
c68d2b15
BH		 3390 [pbn_exar_ibm_saturn] = {
3391 .flags = FL_BASE0,
3392 .num_ports = 1,
3393 .base_baud = 921600,
3394 .uart_offset = 0x200,
3395 },
3396
aa798505
OJ		 3397 /*
3398 * PA Semi PWRficient PA6T-1682M on-chip UART
3399 */
3400 [pbn_pasemi_1682M] = {
3401 .flags = FL_BASE0,
3402 .num_ports = 1,
3403 .base_baud = 8333333,
3404 },
46a0fac9
SB		 3405 /*
3406 * National Instruments 843x
3407 */
3408 [pbn_ni8430_16] = {
3409 .flags = FL_BASE0,
3410 .num_ports = 16,
3411 .base_baud = 3686400,
3412 .uart_offset = 0x10,
3413 .first_offset = 0x800,
3414 },
3415 [pbn_ni8430_8] = {
3416 .flags = FL_BASE0,
3417 .num_ports = 8,
3418 .base_baud = 3686400,
3419 .uart_offset = 0x10,
3420 .first_offset = 0x800,
3421 },
3422 [pbn_ni8430_4] = {
3423 .flags = FL_BASE0,
3424 .num_ports = 4,
3425 .base_baud = 3686400,
3426 .uart_offset = 0x10,
3427 .first_offset = 0x800,
3428 },
3429 [pbn_ni8430_2] = {
3430 .flags = FL_BASE0,
3431 .num_ports = 2,
3432 .base_baud = 3686400,
3433 .uart_offset = 0x10,
3434 .first_offset = 0x800,
3435 },
1b62cbf2
KJ		 3436 /*
3437 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3438 */
3439 [pbn_ADDIDATA_PCIe_1_3906250] = {
3440 .flags = FL_BASE0,
3441 .num_ports = 1,
3442 .base_baud = 3906250,
3443 .uart_offset = 0x200,
3444 .first_offset = 0x1000,
3445 },
3446 [pbn_ADDIDATA_PCIe_2_3906250] = {
3447 .flags = FL_BASE0,
3448 .num_ports = 2,
3449 .base_baud = 3906250,
3450 .uart_offset = 0x200,
3451 .first_offset = 0x1000,
3452 },
3453 [pbn_ADDIDATA_PCIe_4_3906250] = {
3454 .flags = FL_BASE0,
3455 .num_ports = 4,
3456 .base_baud = 3906250,
3457 .uart_offset = 0x200,
3458 .first_offset = 0x1000,
3459 },
3460 [pbn_ADDIDATA_PCIe_8_3906250] = {
3461 .flags = FL_BASE0,
3462 .num_ports = 8,
3463 .base_baud = 3906250,
3464 .uart_offset = 0x200,
3465 .first_offset = 0x1000,
3466 },
095e24b0 3467 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3468 .flags = FL_BASE_BARS,
3469 .num_ports = 2,
095e24b0
DB		 3470 .base_baud = 921600,
3471 .reg_shift = 2,
3472 },
b15e5691
HK		 3473 [pbn_byt] = {
3474 .flags = FL_BASE0,
3475 .num_ports = 1,
3476 .base_baud = 2764800,
3477 .uart_offset = 0x80,
3478 .reg_shift = 2,
3479 },
d9a0fbfd
AP		 3480 [pbn_omegapci] = {
3481 .flags = FL_BASE0,
3482 .num_ports = 8,
3483 .base_baud = 115200,
3484 .uart_offset = 0x200,
3485 },
7808edcd
NG		 3486 [pbn_NETMOS9900_2s_115200] = {
3487 .flags = FL_BASE0,
3488 .num_ports = 2,
3489 .base_baud = 115200,
3490 },
ebebd49a
SH		 3491 [pbn_brcm_trumanage] = {
3492 .flags = FL_BASE0,
3493 .num_ports = 1,
3494 .reg_shift = 2,
3495 .base_baud = 115200,
3496 },
2c62a3c8
GKH		 3497 [pbn_fintek_4] = {
3498 .num_ports = 4,
3499 .uart_offset = 8,
3500 .base_baud = 115200,
3501 .first_offset = 0x40,
3502 },
3503 [pbn_fintek_8] = {
3504 .num_ports = 8,
3505 .uart_offset = 8,
3506 .base_baud = 115200,
3507 .first_offset = 0x40,
3508 },
3509 [pbn_fintek_12] = {
3510 .num_ports = 12,
3511 .uart_offset = 8,
3512 .base_baud = 115200,
3513 .first_offset = 0x40,
3514 },
1da177e4
LT		 3515};
3516
6971c635
GA		 3517static const struct pci_device_id blacklist[] = {
3518 /* softmodems */
5756ee99 3519 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3520 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3521 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3522
3523 /* multi-io cards handled by parport_serial */
3524 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
436bbd43
CS		 3525};
3526
1da177e4
LT		 3527/*
3528 * Given a complete unknown PCI device, try to use some heuristics to
3529 * guess what the configuration might be, based on the pitiful PCI
3530 * serial specs. Returns 0 on success, 1 on failure.
3531 */
9671f099 3532static int
1c7c1fe5 3533serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 3534{
6971c635 3535 const struct pci_device_id *bldev;
1da177e4 3536 int num_iomem, num_port, first_port = -1, i;
5756ee99 3537
1da177e4
LT		 3538 /*
3539 * If it is not a communications device or the programming
3540 * interface is greater than 6, give up.
3541 *
3542 * (Should we try to make guesses for multiport serial devices
5756ee99 3543 * later?)
1da177e4
LT		 3544 */
3545 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3546 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3547 (dev->class & 0xff) > 6)
3548 return -ENODEV;
3549
436bbd43
CS		 3550 /*
3551 * Do not access blacklisted devices that are known not to
6971c635 3552 * feature serial ports or are handled by other modules.
436bbd43 3553 */
6971c635
GA		 3554 for (bldev = blacklist;
3555 bldev < blacklist + ARRAY_SIZE(blacklist);
3556 bldev++) {
3557 if (dev->vendor == bldev->vendor &&
3558 dev->device == bldev->device)
436bbd43
CS		 3559 return -ENODEV;
3560 }
3561
1da177e4
LT		 3562 num_iomem = num_port = 0;
3563 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3564 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3565 num_port++;
3566 if (first_port == -1)
3567 first_port = i;
3568 }
3569 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3570 num_iomem++;
3571 }
3572
3573 /*
3574 * If there is 1 or 0 iomem regions, and exactly one port,
3575 * use it. We guess the number of ports based on the IO
3576 * region size.
3577 */
3578 if (num_iomem <= 1 && num_port == 1) {
3579 board->flags = first_port;
3580 board->num_ports = pci_resource_len(dev, first_port) / 8;
3581 return 0;
3582 }
3583
3584 /*
3585 * Now guess if we've got a board which indexes by BARs.
3586 * Each IO BAR should be 8 bytes, and they should follow
3587 * consecutively.
3588 */
3589 first_port = -1;
3590 num_port = 0;
3591 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3592 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3593 pci_resource_len(dev, i) == 8 &&
3594 (first_port == -1 || (first_port + num_port) == i)) {
3595 num_port++;
3596 if (first_port == -1)
3597 first_port = i;
3598 }
3599 }
3600
3601 if (num_port > 1) {
3602 board->flags = first_port | FL_BASE_BARS;
3603 board->num_ports = num_port;
3604 return 0;
3605 }
3606
3607 return -ENODEV;
3608}
3609
3610static inline int
975a1a7d
RK		 3611serial_pci_matches(const struct pciserial_board *board,
3612 const struct pciserial_board *guessed)
1da177e4
LT		 3613{
3614 return
3615 board->num_ports == guessed->num_ports &&
3616 board->base_baud == guessed->base_baud &&
3617 board->uart_offset == guessed->uart_offset &&
3618 board->reg_shift == guessed->reg_shift &&
3619 board->first_offset == guessed->first_offset;
3620}
3621
241fc436 3622struct serial_private *
975a1a7d 3623pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 3624{
2655a2c7 3625 struct uart_8250_port uart;
1da177e4 3626 struct serial_private *priv;
1da177e4
LT		 3627 struct pci_serial_quirk *quirk;
3628 int rc, nr_ports, i;
3629
1da177e4
LT		 3630 nr_ports = board->num_ports;
3631
3632 /*
3633 * Find an init and setup quirks.
3634 */
3635 quirk = find_quirk(dev);
3636
3637 /*
3638 * Run the new-style initialization function.
3639 * The initialization function returns:
3640 * <0 - error
3641 * 0 - use board->num_ports
3642 * >0 - number of ports
3643 */
3644 if (quirk->init) {
3645 rc = quirk->init(dev);
241fc436
RK		 3646 if (rc < 0) {
3647 priv = ERR_PTR(rc);
3648 goto err_out;
3649 }
1da177e4
LT		 3650 if (rc)
3651 nr_ports = rc;
3652 }
3653
8f31bb39 3654 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 3655 sizeof(unsigned int) * nr_ports,
3656 GFP_KERNEL);
3657 if (!priv) {
241fc436
RK		 3658 priv = ERR_PTR(-ENOMEM);
3659 goto err_deinit;
1da177e4
LT		 3660 }
3661
70db3d91 3662 priv->dev = dev;
1da177e4 3663 priv->quirk = quirk;
1da177e4 3664
2655a2c7
AC		 3665 memset(&uart, 0, sizeof(uart));
3666 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3667 uart.port.uartclk = board->base_baud * 16;
3668 uart.port.irq = get_pci_irq(dev, board);
3669 uart.port.dev = &dev->dev;
72ce9a83 3670
1da177e4 3671 for (i = 0; i < nr_ports; i++) {
2655a2c7 3672 if (quirk->setup(priv, board, &uart, i))
1da177e4 3673 break;
72ce9a83 3674
af8c5b8d
GKH		 3675 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3676 uart.port.iobase, uart.port.irq, uart.port.iotype);
5756ee99 3677
2655a2c7 3678 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4 3679 if (priv->line[i] < 0) {
af8c5b8d
GKH		 3680 dev_err(&dev->dev,
3681 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3682 uart.port.iobase, uart.port.irq,
3683 uart.port.iotype, priv->line[i]);
1da177e4
LT		 3684 break;
3685 }
3686 }
1da177e4 3687 priv->nr = i;
241fc436 3688 return priv;
1da177e4 3689
5756ee99 3690err_deinit:
1da177e4
LT		 3691 if (quirk->exit)
3692 quirk->exit(dev);
5756ee99 3693err_out:
241fc436 3694 return priv;
1da177e4 3695}
241fc436 3696EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 3697
241fc436 3698void pciserial_remove_ports(struct serial_private *priv)
1da177e4 3699{
056a8763
RK		 3700 struct pci_serial_quirk *quirk;
3701 int i;
1da177e4 3702
056a8763
RK		 3703 for (i = 0; i < priv->nr; i++)
3704 serial8250_unregister_port(priv->line[i]);
1da177e4 3705
056a8763
RK		 3706 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3707 if (priv->remapped_bar[i])
3708 iounmap(priv->remapped_bar[i]);
3709 priv->remapped_bar[i] = NULL;
3710 }
1da177e4 3711
056a8763
RK		 3712 /*
3713 * Find the exit quirks.
3714 */
241fc436 3715 quirk = find_quirk(priv->dev);
056a8763 3716 if (quirk->exit)
241fc436
RK		 3717 quirk->exit(priv->dev);
3718
3719 kfree(priv);
3720}
3721EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3722
3723void pciserial_suspend_ports(struct serial_private *priv)
3724{
3725 int i;
3726
3727 for (i = 0; i < priv->nr; i++)
3728 if (priv->line[i] >= 0)
3729 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 3730
3731 /*
3732 * Ensure that every init quirk is properly torn down
3733 */
3734 if (priv->quirk->exit)
3735 priv->quirk->exit(priv->dev);
241fc436
RK		 3736}
3737EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3738
3739void pciserial_resume_ports(struct serial_private *priv)
3740{
3741 int i;
3742
3743 /*
3744 * Ensure that the board is correctly configured.
3745 */
3746 if (priv->quirk->init)
3747 priv->quirk->init(priv->dev);
3748
3749 for (i = 0; i < priv->nr; i++)
3750 if (priv->line[i] >= 0)
3751 serial8250_resume_port(priv->line[i]);
3752}
3753EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3754
3755/*
3756 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3757 * to the arrangement of serial ports on a PCI card.
3758 */
9671f099 3759static int
241fc436
RK		 3760pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3761{
5bf8f501 3762 struct pci_serial_quirk *quirk;
241fc436 3763 struct serial_private *priv;
975a1a7d
RK		 3764 const struct pciserial_board *board;
3765 struct pciserial_board tmp;
241fc436
RK		 3766 int rc;
3767
5bf8f501
FB		 3768 quirk = find_quirk(dev);
3769 if (quirk->probe) {
3770 rc = quirk->probe(dev);
3771 if (rc)
3772 return rc;
3773 }
3774
241fc436 3775 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
af8c5b8d 3776 dev_err(&dev->dev, "invalid driver_data: %ld\n",
241fc436
RK		 3777 ent->driver_data);
3778 return -EINVAL;
3779 }
3780
3781 board = &pci_boards[ent->driver_data];
3782
3783 rc = pci_enable_device(dev);
2807190b 3784 pci_save_state(dev);
241fc436
RK		 3785 if (rc)
3786 return rc;
3787
3788 if (ent->driver_data == pbn_default) {
3789 /*
3790 * Use a copy of the pci_board entry for this;
3791 * avoid changing entries in the table.
3792 */
3793 memcpy(&tmp, board, sizeof(struct pciserial_board));
3794 board = &tmp;
3795
3796 /*
3797 * We matched one of our class entries. Try to
3798 * determine the parameters of this board.
3799 */
975a1a7d 3800 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 3801 if (rc)
3802 goto disable;
3803 } else {
3804 /*
3805 * We matched an explicit entry. If we are able to
3806 * detect this boards settings with our heuristic,
3807 * then we no longer need this entry.
3808 */
3809 memcpy(&tmp, &pci_boards[pbn_default],
3810 sizeof(struct pciserial_board));
3811 rc = serial_pci_guess_board(dev, &tmp);
3812 if (rc == 0 && serial_pci_matches(board, &tmp))
3813 moan_device("Redundant entry in serial pci_table.",
3814 dev);
3815 }
3816
3817 priv = pciserial_init_ports(dev, board);
3818 if (!IS_ERR(priv)) {
3819 pci_set_drvdata(dev, priv);
3820 return 0;
3821 }
3822
3823 rc = PTR_ERR(priv);
1da177e4 3824
241fc436 3825 disable:
056a8763 3826 pci_disable_device(dev);
241fc436
RK		 3827 return rc;
3828}
1da177e4 3829
ae8d8a14 3830static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 3831{
3832 struct serial_private *priv = pci_get_drvdata(dev);
3833
241fc436
RK		 3834 pciserial_remove_ports(priv);
3835
3836 pci_disable_device(dev);
1da177e4
LT		 3837}
3838
1d5e7996 3839#ifdef CONFIG_PM
1da177e4
LT		 3840static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3841{
3842 struct serial_private *priv = pci_get_drvdata(dev);
3843
241fc436
RK		 3844 if (priv)
3845 pciserial_suspend_ports(priv);
1da177e4 3846
1da177e4
LT		 3847 pci_save_state(dev);
3848 pci_set_power_state(dev, pci_choose_state(dev, state));
3849 return 0;
3850}
3851
3852static int pciserial_resume_one(struct pci_dev *dev)
3853{
ccb9d59e 3854 int err;
1da177e4
LT		 3855 struct serial_private *priv = pci_get_drvdata(dev);
3856
3857 pci_set_power_state(dev, PCI_D0);
3858 pci_restore_state(dev);
3859
3860 if (priv) {
1da177e4
LT		 3861 /*
3862 * The device may have been disabled. Re-enable it.
3863 */
ccb9d59e 3864 err = pci_enable_device(dev);
40836c48 3865 /* FIXME: We cannot simply error out here */
ccb9d59e 3866 if (err)
af8c5b8d 3867 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
241fc436 3868 pciserial_resume_ports(priv);
1da177e4
LT		 3869 }
3870 return 0;
3871}
1d5e7996 3872#endif
1da177e4
LT		 3873
3874static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 3875 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3876 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3877 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3878 pbn_b2_8_921600 },
1da177e4
LT		 3879 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3880 PCI_SUBVENDOR_ID_CONNECT_TECH,
3881 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3882 pbn_b1_8_1382400 },
3883 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3884 PCI_SUBVENDOR_ID_CONNECT_TECH,
3885 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3886 pbn_b1_4_1382400 },
3887 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3888 PCI_SUBVENDOR_ID_CONNECT_TECH,
3889 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3890 pbn_b1_2_1382400 },
3891 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3892 PCI_SUBVENDOR_ID_CONNECT_TECH,
3893 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3894 pbn_b1_8_1382400 },
3895 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3896 PCI_SUBVENDOR_ID_CONNECT_TECH,
3897 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3898 pbn_b1_4_1382400 },
3899 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3900 PCI_SUBVENDOR_ID_CONNECT_TECH,
3901 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3902 pbn_b1_2_1382400 },
3903 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3904 PCI_SUBVENDOR_ID_CONNECT_TECH,
3905 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3906 pbn_b1_8_921600 },
3907 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3908 PCI_SUBVENDOR_ID_CONNECT_TECH,
3909 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3910 pbn_b1_8_921600 },
3911 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3912 PCI_SUBVENDOR_ID_CONNECT_TECH,
3913 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3914 pbn_b1_4_921600 },
3915 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3916 PCI_SUBVENDOR_ID_CONNECT_TECH,
3917 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3918 pbn_b1_4_921600 },
3919 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3920 PCI_SUBVENDOR_ID_CONNECT_TECH,
3921 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3922 pbn_b1_2_921600 },
3923 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3924 PCI_SUBVENDOR_ID_CONNECT_TECH,
3925 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3926 pbn_b1_8_921600 },
3927 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3928 PCI_SUBVENDOR_ID_CONNECT_TECH,
3929 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3930 pbn_b1_8_921600 },
3931 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3932 PCI_SUBVENDOR_ID_CONNECT_TECH,
3933 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3934 pbn_b1_4_921600 },
26e92861
GH		 3935 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3936 PCI_SUBVENDOR_ID_CONNECT_TECH,
3937 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3938 pbn_b1_2_1250000 },
3939 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3940 PCI_SUBVENDOR_ID_CONNECT_TECH,
3941 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3942 pbn_b0_2_1843200 },
3943 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3944 PCI_SUBVENDOR_ID_CONNECT_TECH,
3945 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3946 pbn_b0_4_1843200 },
85d1494e
YY		 3947 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3948 PCI_VENDOR_ID_AFAVLAB,
3949 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3950 pbn_b0_4_1152000 },
26e92861
GH		 3951 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3952 PCI_SUBVENDOR_ID_CONNECT_TECH,
3953 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3954 pbn_b0_2_1843200_200 },
3955 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3956 PCI_SUBVENDOR_ID_CONNECT_TECH,
3957 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3958 pbn_b0_4_1843200_200 },
3959 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3960 PCI_SUBVENDOR_ID_CONNECT_TECH,
3961 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3962 pbn_b0_8_1843200_200 },
3963 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3964 PCI_SUBVENDOR_ID_CONNECT_TECH,
3965 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3966 pbn_b0_2_1843200_200 },
3967 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3968 PCI_SUBVENDOR_ID_CONNECT_TECH,
3969 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3970 pbn_b0_4_1843200_200 },
3971 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3972 PCI_SUBVENDOR_ID_CONNECT_TECH,
3973 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3974 pbn_b0_8_1843200_200 },
3975 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3976 PCI_SUBVENDOR_ID_CONNECT_TECH,
3977 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3978 pbn_b0_2_1843200_200 },
3979 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3980 PCI_SUBVENDOR_ID_CONNECT_TECH,
3981 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3982 pbn_b0_4_1843200_200 },
3983 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3984 PCI_SUBVENDOR_ID_CONNECT_TECH,
3985 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3986 pbn_b0_8_1843200_200 },
3987 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3988 PCI_SUBVENDOR_ID_CONNECT_TECH,
3989 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3990 pbn_b0_2_1843200_200 },
3991 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3992 PCI_SUBVENDOR_ID_CONNECT_TECH,
3993 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3994 pbn_b0_4_1843200_200 },
3995 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3996 PCI_SUBVENDOR_ID_CONNECT_TECH,
3997 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3998 pbn_b0_8_1843200_200 },
c68d2b15
BH		 3999 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4000 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4001 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 4002
4003 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 4004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4005 pbn_b2_bt_1_115200 },
4006 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 4007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4008 pbn_b2_bt_2_115200 },
4009 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 4010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4011 pbn_b2_bt_4_115200 },
4012 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 4013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4014 pbn_b2_bt_2_115200 },
4015 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 4016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4017 pbn_b2_bt_4_115200 },
4018 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 4019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4020 pbn_b2_8_115200 },
e65f0f82
FL		 4021 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4022 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4023 pbn_b2_8_460800 },
1da177e4
LT		 4024 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4026 pbn_b2_8_115200 },
4027
4028 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4030 pbn_b2_bt_2_115200 },
4031 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4033 pbn_b2_bt_2_921600 },
4034 /*
4035 * VScom SPCOM800, from sl@s.pl
4036 */
5756ee99
AC		 4037 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4038 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4039 pbn_b2_8_921600 },
4040 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 4041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4042 pbn_b2_4_921600 },
b76c5a07
CB		 4043 /* Unknown card - subdevice 0x1584 */
4044 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4045 PCI_VENDOR_ID_PLX,
4046 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 4047 pbn_b2_4_115200 },
4048 /* Unknown card - subdevice 0x1588 */
4049 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4050 PCI_VENDOR_ID_PLX,
4051 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4052 pbn_b2_8_115200 },
1da177e4
LT		 4053 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4054 PCI_SUBVENDOR_ID_KEYSPAN,
4055 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4056 pbn_panacom },
4057 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4059 pbn_panacom4 },
4060 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4062 pbn_panacom2 },
a9cccd34
MF		 4063 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4064 PCI_VENDOR_ID_ESDGMBH,
4065 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4066 pbn_b2_4_115200 },
1da177e4
LT		 4067 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4068 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4069 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 4070 pbn_b2_4_460800 },
4071 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4072 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4073 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 4074 pbn_b2_8_460800 },
4075 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4076 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4077 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 4078 pbn_b2_16_460800 },
4079 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4080 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4081 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 4082 pbn_b2_16_460800 },
4083 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4084 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4085 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 4086 pbn_b2_4_460800 },
4087 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4088 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4089 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 4090 pbn_b2_8_460800 },
add7b58e
BH		 4091 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4092 PCI_SUBVENDOR_ID_EXSYS,
4093 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 4094 pbn_b2_4_115200 },
1da177e4
LT		 4095 /*
4096 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4097 * (Exoray@isys.ca)
4098 */
4099 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4100 0x10b5, 0x106a, 0, 0,
4101 pbn_plx_romulus },
55c7c0fd
AC		 4102 /*
4103 * Quatech cards. These actually have configurable clocks but for
4104 * now we just use the default.
4105 *
4106 * 100 series are RS232, 200 series RS422,
4107 */
1da177e4
LT		 4108 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4110 pbn_b1_4_115200 },
4111 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4113 pbn_b1_2_115200 },
55c7c0fd
AC		 4114 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4116 pbn_b2_2_115200 },
4117 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4119 pbn_b1_2_115200 },
4120 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4122 pbn_b2_2_115200 },
4123 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4125 pbn_b1_4_115200 },
1da177e4
LT		 4126 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4128 pbn_b1_8_115200 },
4129 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131 pbn_b1_8_115200 },
55c7c0fd
AC		 4132 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134 pbn_b1_4_115200 },
4135 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4137 pbn_b1_2_115200 },
4138 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4140 pbn_b1_4_115200 },
4141 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143 pbn_b1_2_115200 },
4144 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4146 pbn_b2_4_115200 },
4147 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4149 pbn_b2_2_115200 },
4150 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4152 pbn_b2_1_115200 },
4153 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4155 pbn_b2_4_115200 },
4156 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4158 pbn_b2_2_115200 },
4159 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4161 pbn_b2_1_115200 },
4162 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4164 pbn_b0_8_115200 },
4165
1da177e4 4166 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4167 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4168 0, 0,
1da177e4 4169 pbn_b0_4_921600 },
fbc0dc0d 4170 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4171 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4172 0, 0,
fbc0dc0d 4173 pbn_b0_4_1152000 },
c9bd9d01
MP		 4174 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4176 pbn_b0_bt_2_921600 },
db1de159
DR		 4177
4178 /*
4179 * The below card is a little controversial since it is the
4180 * subject of a PCI vendor/device ID clash. (See
4181 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4182 * For now just used the hex ID 0x950a.
4183 */
39aced68 4184 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 4185 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4186 0, 0, pbn_b0_2_115200 },
4187 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4188 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4189 0, 0, pbn_b0_2_115200 },
db1de159
DR		 4190 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4192 pbn_b0_2_1130000 },
70fd8fde
AP		 4193 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4194 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4195 pbn_b0_1_921600 },
1da177e4
LT		 4196 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4198 pbn_b0_4_115200 },
4199 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4201 pbn_b0_bt_2_921600 },
e847003f
LB		 4202 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4203 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4204 pbn_b2_8_1152000 },
1da177e4 4205
7106b4e3
LH		 4206 /*
4207 * Oxford Semiconductor Inc. Tornado PCI express device range.
4208 */
4209 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4211 pbn_b0_1_4000000 },
4212 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4214 pbn_b0_1_4000000 },
4215 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4217 pbn_oxsemi_1_4000000 },
4218 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4220 pbn_oxsemi_1_4000000 },
4221 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4223 pbn_b0_1_4000000 },
4224 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4226 pbn_b0_1_4000000 },
4227 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4229 pbn_oxsemi_1_4000000 },
4230 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4232 pbn_oxsemi_1_4000000 },
4233 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4235 pbn_b0_1_4000000 },
4236 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4238 pbn_b0_1_4000000 },
4239 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4240 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4241 pbn_b0_1_4000000 },
4242 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4244 pbn_b0_1_4000000 },
4245 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4246 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4247 pbn_oxsemi_2_4000000 },
4248 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4250 pbn_oxsemi_2_4000000 },
4251 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4253 pbn_oxsemi_4_4000000 },
4254 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4256 pbn_oxsemi_4_4000000 },
4257 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4259 pbn_oxsemi_8_4000000 },
4260 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4262 pbn_oxsemi_8_4000000 },
4263 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4265 pbn_oxsemi_1_4000000 },
4266 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4268 pbn_oxsemi_1_4000000 },
4269 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4271 pbn_oxsemi_1_4000000 },
4272 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4274 pbn_oxsemi_1_4000000 },
4275 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4277 pbn_oxsemi_1_4000000 },
4278 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4280 pbn_oxsemi_1_4000000 },
4281 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4283 pbn_oxsemi_1_4000000 },
4284 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4286 pbn_oxsemi_1_4000000 },
4287 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4289 pbn_oxsemi_1_4000000 },
4290 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4292 pbn_oxsemi_1_4000000 },
4293 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4295 pbn_oxsemi_1_4000000 },
4296 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298 pbn_oxsemi_1_4000000 },
4299 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4301 pbn_oxsemi_1_4000000 },
4302 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4304 pbn_oxsemi_1_4000000 },
4305 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4307 pbn_oxsemi_1_4000000 },
4308 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4310 pbn_oxsemi_1_4000000 },
4311 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4313 pbn_oxsemi_1_4000000 },
4314 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4316 pbn_oxsemi_1_4000000 },
4317 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4319 pbn_oxsemi_1_4000000 },
4320 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4322 pbn_oxsemi_1_4000000 },
4323 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325 pbn_oxsemi_1_4000000 },
4326 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328 pbn_oxsemi_1_4000000 },
4329 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331 pbn_oxsemi_1_4000000 },
4332 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4334 pbn_oxsemi_1_4000000 },
4335 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4337 pbn_oxsemi_1_4000000 },
4338 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4340 pbn_oxsemi_1_4000000 },
b80de369
LH		 4341 /*
4342 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4343 */
4344 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4345 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4346 pbn_oxsemi_1_4000000 },
4347 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4348 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4349 pbn_oxsemi_2_4000000 },
4350 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4351 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4352 pbn_oxsemi_4_4000000 },
4353 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4354 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4355 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4356
4357 /*
4358 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4359 */
4360 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4361 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4362 pbn_oxsemi_2_4000000 },
4363
1da177e4
LT		 4364 /*
4365 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4366 * from skokodyn@yahoo.com
4367 */
4368 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4369 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4370 pbn_sbsxrsio },
4371 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4372 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4373 pbn_sbsxrsio },
4374 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4375 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4376 pbn_sbsxrsio },
4377 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4378 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4379 pbn_sbsxrsio },
4380
4381 /*
4382 * Digitan DS560-558, from jimd@esoft.com
4383 */
4384 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4386 pbn_b1_1_115200 },
4387
4388 /*
4389 * Titan Electronic cards
4390 * The 400L and 800L have a custom setup quirk.
4391 */
4392 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4394 pbn_b0_1_921600 },
4395 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4397 pbn_b0_2_921600 },
4398 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4400 pbn_b0_4_921600 },
4401 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4403 pbn_b0_4_921600 },
4404 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 pbn_b1_1_921600 },
4407 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_b1_bt_2_921600 },
4410 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 pbn_b0_bt_4_921600 },
4413 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 pbn_b0_bt_8_921600 },
66169ad1
YY		 4416 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 pbn_b4_bt_2_921600 },
4419 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 pbn_b4_bt_4_921600 },
4422 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 pbn_b4_bt_8_921600 },
4425 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 pbn_b0_4_921600 },
4428 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 pbn_b0_4_921600 },
4431 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433 pbn_b0_4_921600 },
4434 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436 pbn_oxsemi_1_4000000 },
4437 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 pbn_oxsemi_2_4000000 },
4440 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 pbn_oxsemi_4_4000000 },
4443 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 pbn_oxsemi_8_4000000 },
4446 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 pbn_oxsemi_2_4000000 },
4449 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_oxsemi_2_4000000 },
48c0247d
YY		 4452 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_b0_bt_2_921600 },
1e9deb11
YY		 4455 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_b0_4_921600 },
4458 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 pbn_b0_4_921600 },
4461 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463 pbn_b0_4_921600 },
4464 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466 pbn_b0_4_921600 },
1da177e4
LT		 4467
4468 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4470 pbn_b2_1_460800 },
4471 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4473 pbn_b2_1_460800 },
4474 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4476 pbn_b2_1_460800 },
4477 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4479 pbn_b2_bt_2_921600 },
4480 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482 pbn_b2_bt_2_921600 },
4483 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4485 pbn_b2_bt_2_921600 },
4486 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4488 pbn_b2_bt_4_921600 },
4489 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 pbn_b2_bt_4_921600 },
4492 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 pbn_b2_bt_4_921600 },
4495 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_b0_1_921600 },
4498 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_b0_1_921600 },
4501 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_b0_1_921600 },
4504 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506 pbn_b0_bt_2_921600 },
4507 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509 pbn_b0_bt_2_921600 },
4510 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512 pbn_b0_bt_2_921600 },
4513 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4515 pbn_b0_bt_4_921600 },
4516 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518 pbn_b0_bt_4_921600 },
4519 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 pbn_b0_bt_4_921600 },
3ec9c594
AP		 4522 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524 pbn_b0_bt_8_921600 },
4525 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4527 pbn_b0_bt_8_921600 },
4528 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4530 pbn_b0_bt_8_921600 },
1da177e4
LT		 4531
4532 /*
4533 * Computone devices submitted by Doug McNash dmcnash@computone.com
4534 */
4535 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4536 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4537 0, 0, pbn_computone_4 },
4538 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4539 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4540 0, 0, pbn_computone_8 },
4541 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4542 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4543 0, 0, pbn_computone_6 },
4544
4545 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 pbn_oxsemi },
4548 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4549 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4550 pbn_b0_bt_1_921600 },
4551
abd7baca
SC		 4552 /*
4553 * SUNIX (TIMEDIA)
4554 */
4555 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4556 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4557 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4558 pbn_b0_bt_1_921600 },
4559
4560 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4561 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4562 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4563 pbn_b0_bt_1_921600 },
4564
1da177e4
LT		 4565 /*
4566 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4567 */
4568 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570 pbn_b0_bt_8_115200 },
4571 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4573 pbn_b0_bt_8_115200 },
4574
4575 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_b0_bt_2_115200 },
4578 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_b0_bt_2_115200 },
4581 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 4584 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_b0_bt_2_115200 },
4587 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_b0_bt_2_115200 },
1da177e4
LT		 4590 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_b0_bt_4_460800 },
4593 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_b0_bt_4_460800 },
4596 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_b0_bt_2_460800 },
4599 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_b0_bt_2_460800 },
4602 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_b0_bt_2_460800 },
4605 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_b0_bt_1_115200 },
4608 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_b0_bt_1_460800 },
4611
1fb8cacc
RK		 4612 /*
4613 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4614 * Cards are identified by their subsystem vendor IDs, which
4615 * (in hex) match the model number.
4616 *
4617 * Note that JC140x are RS422/485 cards which require ox950
4618 * ACR = 0x10, and as such are not currently fully supported.
4619 */
4620 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4621 0x1204, 0x0004, 0, 0,
4622 pbn_b0_4_921600 },
4623 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4624 0x1208, 0x0004, 0, 0,
4625 pbn_b0_4_921600 },
4626/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4627 0x1402, 0x0002, 0, 0,
4628 pbn_b0_2_921600 }, */
4629/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4630 0x1404, 0x0004, 0, 0,
4631 pbn_b0_4_921600 }, */
4632 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4633 0x1208, 0x0004, 0, 0,
4634 pbn_b0_4_921600 },
4635
2a52fcb5
KY		 4636 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4637 0x1204, 0x0004, 0, 0,
4638 pbn_b0_4_921600 },
4639 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4640 0x1208, 0x0004, 0, 0,
4641 pbn_b0_4_921600 },
4642 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4643 0x1208, 0x0004, 0, 0,
4644 pbn_b0_4_921600 },
1da177e4
LT		 4645 /*
4646 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4647 */
4648 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_b1_1_1382400 },
4651
4652 /*
4653 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4654 */
4655 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 pbn_b1_1_1382400 },
4658
4659 /*
4660 * RAStel 2 port modem, gerg@moreton.com.au
4661 */
4662 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4664 pbn_b2_bt_2_115200 },
4665
4666 /*
4667 * EKF addition for i960 Boards form EKF with serial port
4668 */
4669 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4670 0xE4BF, PCI_ANY_ID, 0, 0,
4671 pbn_intel_i960 },
4672
4673 /*
4674 * Xircom Cardbus/Ethernet combos
4675 */
4676 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_b0_1_115200 },
4679 /*
4680 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4681 */
4682 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_b0_1_115200 },
4685
4686 /*
4687 * Untested PCI modems, sent in from various folks...
4688 */
4689
4690 /*
4691 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4692 */
4693 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4694 0x1048, 0x1500, 0, 0,
4695 pbn_b1_1_115200 },
4696
4697 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4698 0xFF00, 0, 0, 0,
4699 pbn_sgi_ioc3 },
4700
4701 /*
4702 * HP Diva card
4703 */
4704 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4705 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4706 pbn_b1_1_115200 },
4707 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709 pbn_b0_5_115200 },
4710 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4712 pbn_b2_1_115200 },
4713
d9004eb4
ABL		 4714 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_b3_2_115200 },
1da177e4
LT		 4717 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_b3_4_115200 },
4720 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_b3_8_115200 },
4723
4724 /*
4725 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4726 */
4727 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4728 PCI_ANY_ID, PCI_ANY_ID,
4729 0,
4730 0, pbn_exar_XR17C152 },
4731 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4732 PCI_ANY_ID, PCI_ANY_ID,
4733 0,
4734 0, pbn_exar_XR17C154 },
4735 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4736 PCI_ANY_ID, PCI_ANY_ID,
4737 0,
4738 0, pbn_exar_XR17C158 },
dc96efb7
MS		 4739 /*
4740 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4741 */
4742 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4743 PCI_ANY_ID, PCI_ANY_ID,
4744 0,
4745 0, pbn_exar_XR17V352 },
4746 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4747 PCI_ANY_ID, PCI_ANY_ID,
4748 0,
4749 0, pbn_exar_XR17V354 },
4750 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4751 PCI_ANY_ID, PCI_ANY_ID,
4752 0,
4753 0, pbn_exar_XR17V358 },
1da177e4
LT		 4754
4755 /*
4756 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4757 */
4758 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 pbn_b0_1_115200 },
84f8c6fc
NV		 4761 /*
4762 * ITE
4763 */
4764 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4765 PCI_ANY_ID, PCI_ANY_ID,
4766 0, 0,
4767 pbn_b1_bt_1_115200 },
1da177e4 4768
737c1756
PH		 4769 /*
4770 * IntaShield IS-200
4771 */
4772 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4774 pbn_b2_2_115200 },
4b6f6ce9
IGP		 4775 /*
4776 * IntaShield IS-400
4777 */
4778 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4780 pbn_b2_4_115200 },
48212008
TH		 4781 /*
4782 * Perle PCI-RAS cards
4783 */
4784 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4785 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4786 0, 0, pbn_b2_4_921600 },
4787 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4788 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4789 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 4790
4791 /*
4792 * Mainpine series cards: Fairly standard layout but fools
4793 * parts of the autodetect in some cases and uses otherwise
4794 * unmatched communications subclasses in the PCI Express case
4795 */
4796
4797 { /* RockForceDUO */
4798 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4799 PCI_VENDOR_ID_MAINPINE, 0x0200,
4800 0, 0, pbn_b0_2_115200 },
4801 { /* RockForceQUATRO */
4802 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4803 PCI_VENDOR_ID_MAINPINE, 0x0300,
4804 0, 0, pbn_b0_4_115200 },
4805 { /* RockForceDUO+ */
4806 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4807 PCI_VENDOR_ID_MAINPINE, 0x0400,
4808 0, 0, pbn_b0_2_115200 },
4809 { /* RockForceQUATRO+ */
4810 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4811 PCI_VENDOR_ID_MAINPINE, 0x0500,
4812 0, 0, pbn_b0_4_115200 },
4813 { /* RockForce+ */
4814 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4815 PCI_VENDOR_ID_MAINPINE, 0x0600,
4816 0, 0, pbn_b0_2_115200 },
4817 { /* RockForce+ */
4818 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4819 PCI_VENDOR_ID_MAINPINE, 0x0700,
4820 0, 0, pbn_b0_4_115200 },
4821 { /* RockForceOCTO+ */
4822 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4823 PCI_VENDOR_ID_MAINPINE, 0x0800,
4824 0, 0, pbn_b0_8_115200 },
4825 { /* RockForceDUO+ */
4826 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4827 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4828 0, 0, pbn_b0_2_115200 },
4829 { /* RockForceQUARTRO+ */
4830 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4831 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4832 0, 0, pbn_b0_4_115200 },
4833 { /* RockForceOCTO+ */
4834 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4835 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4836 0, 0, pbn_b0_8_115200 },
4837 { /* RockForceD1 */
4838 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4839 PCI_VENDOR_ID_MAINPINE, 0x2000,
4840 0, 0, pbn_b0_1_115200 },
4841 { /* RockForceF1 */
4842 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4843 PCI_VENDOR_ID_MAINPINE, 0x2100,
4844 0, 0, pbn_b0_1_115200 },
4845 { /* RockForceD2 */
4846 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4847 PCI_VENDOR_ID_MAINPINE, 0x2200,
4848 0, 0, pbn_b0_2_115200 },
4849 { /* RockForceF2 */
4850 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4851 PCI_VENDOR_ID_MAINPINE, 0x2300,
4852 0, 0, pbn_b0_2_115200 },
4853 { /* RockForceD4 */
4854 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4855 PCI_VENDOR_ID_MAINPINE, 0x2400,
4856 0, 0, pbn_b0_4_115200 },
4857 { /* RockForceF4 */
4858 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4859 PCI_VENDOR_ID_MAINPINE, 0x2500,
4860 0, 0, pbn_b0_4_115200 },
4861 { /* RockForceD8 */
4862 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4863 PCI_VENDOR_ID_MAINPINE, 0x2600,
4864 0, 0, pbn_b0_8_115200 },
4865 { /* RockForceF8 */
4866 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4867 PCI_VENDOR_ID_MAINPINE, 0x2700,
4868 0, 0, pbn_b0_8_115200 },
4869 { /* IQ Express D1 */
4870 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4871 PCI_VENDOR_ID_MAINPINE, 0x3000,
4872 0, 0, pbn_b0_1_115200 },
4873 { /* IQ Express F1 */
4874 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4875 PCI_VENDOR_ID_MAINPINE, 0x3100,
4876 0, 0, pbn_b0_1_115200 },
4877 { /* IQ Express D2 */
4878 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4879 PCI_VENDOR_ID_MAINPINE, 0x3200,
4880 0, 0, pbn_b0_2_115200 },
4881 { /* IQ Express F2 */
4882 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4883 PCI_VENDOR_ID_MAINPINE, 0x3300,
4884 0, 0, pbn_b0_2_115200 },
4885 { /* IQ Express D4 */
4886 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4887 PCI_VENDOR_ID_MAINPINE, 0x3400,
4888 0, 0, pbn_b0_4_115200 },
4889 { /* IQ Express F4 */
4890 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4891 PCI_VENDOR_ID_MAINPINE, 0x3500,
4892 0, 0, pbn_b0_4_115200 },
4893 { /* IQ Express D8 */
4894 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4895 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4896 0, 0, pbn_b0_8_115200 },
4897 { /* IQ Express F8 */
4898 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4899 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4900 0, 0, pbn_b0_8_115200 },
4901
4902
aa798505
OJ		 4903 /*
4904 * PA Semi PA6T-1682M on-chip UART
4905 */
4906 { PCI_VENDOR_ID_PASEMI, 0xa004,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_pasemi_1682M },
4909
46a0fac9
SB		 4910 /*
4911 * National Instruments
4912 */
04bf7e74
WP		 4913 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915 pbn_b1_16_115200 },
4916 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918 pbn_b1_8_115200 },
4919 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921 pbn_b1_bt_4_115200 },
4922 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4924 pbn_b1_bt_2_115200 },
4925 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4927 pbn_b1_bt_4_115200 },
4928 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4930 pbn_b1_bt_2_115200 },
4931 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4933 pbn_b1_16_115200 },
4934 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4936 pbn_b1_8_115200 },
4937 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939 pbn_b1_bt_4_115200 },
4940 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4941 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4942 pbn_b1_bt_2_115200 },
4943 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4945 pbn_b1_bt_4_115200 },
4946 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4948 pbn_b1_bt_2_115200 },
46a0fac9
SB		 4949 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4951 pbn_ni8430_2 },
4952 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4954 pbn_ni8430_2 },
4955 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957 pbn_ni8430_4 },
4958 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4960 pbn_ni8430_4 },
4961 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963 pbn_ni8430_8 },
4964 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4966 pbn_ni8430_8 },
4967 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4969 pbn_ni8430_16 },
4970 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4972 pbn_ni8430_16 },
4973 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 pbn_ni8430_2 },
4976 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 pbn_ni8430_2 },
4979 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981 pbn_ni8430_4 },
4982 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 pbn_ni8430_4 },
4985
02c9b5cf
KJ		 4986 /*
4987 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4988 */
4989 { PCI_VENDOR_ID_ADDIDATA,
4990 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4991 PCI_ANY_ID,
4992 PCI_ANY_ID,
4993 0,
4994 0,
4995 pbn_b0_4_115200 },
4996
4997 { PCI_VENDOR_ID_ADDIDATA,
4998 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4999 PCI_ANY_ID,
5000 PCI_ANY_ID,
5001 0,
5002 0,
5003 pbn_b0_2_115200 },
5004
5005 { PCI_VENDOR_ID_ADDIDATA,
5006 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5007 PCI_ANY_ID,
5008 PCI_ANY_ID,
5009 0,
5010 0,
5011 pbn_b0_1_115200 },
5012
086231f7 5013 { PCI_VENDOR_ID_AMCC,
57c1f0e9 5014 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 5015 PCI_ANY_ID,
5016 PCI_ANY_ID,
5017 0,
5018 0,
5019 pbn_b1_8_115200 },
5020
5021 { PCI_VENDOR_ID_ADDIDATA,
5022 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5023 PCI_ANY_ID,
5024 PCI_ANY_ID,
5025 0,
5026 0,
5027 pbn_b0_4_115200 },
5028
5029 { PCI_VENDOR_ID_ADDIDATA,
5030 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5031 PCI_ANY_ID,
5032 PCI_ANY_ID,
5033 0,
5034 0,
5035 pbn_b0_2_115200 },
5036
5037 { PCI_VENDOR_ID_ADDIDATA,
5038 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5039 PCI_ANY_ID,
5040 PCI_ANY_ID,
5041 0,
5042 0,
5043 pbn_b0_1_115200 },
5044
5045 { PCI_VENDOR_ID_ADDIDATA,
5046 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5047 PCI_ANY_ID,
5048 PCI_ANY_ID,
5049 0,
5050 0,
5051 pbn_b0_4_115200 },
5052
5053 { PCI_VENDOR_ID_ADDIDATA,
5054 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5055 PCI_ANY_ID,
5056 PCI_ANY_ID,
5057 0,
5058 0,
5059 pbn_b0_2_115200 },
5060
5061 { PCI_VENDOR_ID_ADDIDATA,
5062 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5063 PCI_ANY_ID,
5064 PCI_ANY_ID,
5065 0,
5066 0,
5067 pbn_b0_1_115200 },
5068
5069 { PCI_VENDOR_ID_ADDIDATA,
5070 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5071 PCI_ANY_ID,
5072 PCI_ANY_ID,
5073 0,
5074 0,
5075 pbn_b0_8_115200 },
5076
1b62cbf2
KJ		 5077 { PCI_VENDOR_ID_ADDIDATA,
5078 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5079 PCI_ANY_ID,
5080 PCI_ANY_ID,
5081 0,
5082 0,
5083 pbn_ADDIDATA_PCIe_4_3906250 },
5084
5085 { PCI_VENDOR_ID_ADDIDATA,
5086 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5087 PCI_ANY_ID,
5088 PCI_ANY_ID,
5089 0,
5090 0,
5091 pbn_ADDIDATA_PCIe_2_3906250 },
5092
5093 { PCI_VENDOR_ID_ADDIDATA,
5094 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5095 PCI_ANY_ID,
5096 PCI_ANY_ID,
5097 0,
5098 0,
5099 pbn_ADDIDATA_PCIe_1_3906250 },
5100
5101 { PCI_VENDOR_ID_ADDIDATA,
5102 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5103 PCI_ANY_ID,
5104 PCI_ANY_ID,
5105 0,
5106 0,
5107 pbn_ADDIDATA_PCIe_8_3906250 },
5108
25cf9bc1
JS		 5109 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5110 PCI_VENDOR_ID_IBM, 0x0299,
5111 0, 0, pbn_b0_bt_2_115200 },
5112
972ce085
SS		 5113 /*
5114 * other NetMos 9835 devices are most likely handled by the
5115 * parport_serial driver, check drivers/parport/parport_serial.c
5116 * before adding them here.
5117 */
5118
c4285b47
MB		 5119 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5120 0xA000, 0x1000,
5121 0, 0, pbn_b0_1_115200 },
5122
7808edcd
NG		 5123 /* the 9901 is a rebranded 9912 */
5124 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5125 0xA000, 0x1000,
5126 0, 0, pbn_b0_1_115200 },
5127
5128 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5129 0xA000, 0x1000,
5130 0, 0, pbn_b0_1_115200 },
5131
5132 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5133 0xA000, 0x1000,
5134 0, 0, pbn_b0_1_115200 },
5135
5136 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5137 0xA000, 0x1000,
5138 0, 0, pbn_b0_1_115200 },
5139
5140 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5141 0xA000, 0x3002,
5142 0, 0, pbn_NETMOS9900_2s_115200 },
5143
ac6ec5b1 5144 /*
44178176 5145 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 5146 */
5147
5148 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5149 0xA000, 0x1000,
5150 0, 0, pbn_b0_1_115200 },
5151
44178176
ES		 5152 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5153 0xA000, 0x3002,
5154 0, 0, pbn_b0_bt_2_115200 },
5155
ac6ec5b1
IS		 5156 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5157 0xA000, 0x3004,
5158 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 5159 /* Intel CE4100 */
5160 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5162 pbn_ce4100_1_115200 },
b15e5691
HK		 5163 /* Intel BayTrail */
5164 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5165 PCI_ANY_ID, PCI_ANY_ID,
5166 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5167 pbn_byt },
5168 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5169 PCI_ANY_ID, PCI_ANY_ID,
5170 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5171 pbn_byt },
095e24b0 5172
d9a0fbfd
AP		 5173 /*
5174 * Cronyx Omega PCI
5175 */
5176 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5178 pbn_omegapci },
ac6ec5b1 5179
ebebd49a
SH		 5180 /*
5181 * Broadcom TruManage
5182 */
5183 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5185 pbn_brcm_trumanage },
5186
6683549e
AC		 5187 /*
5188 * AgeStar as-prs2-009
5189 */
5190 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5191 PCI_ANY_ID, PCI_ANY_ID,
5192 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 5193
5194 /*
5195 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5196 * so not listed here.
5197 */
5198 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5199 PCI_ANY_ID, PCI_ANY_ID,
5200 0, 0, pbn_b0_bt_4_115200 },
5201
5202 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5203 PCI_ANY_ID, PCI_ANY_ID,
5204 0, 0, pbn_b0_bt_2_115200 },
5205
8b5c913f
WY		 5206 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5207 PCI_ANY_ID, PCI_ANY_ID,
5208 0, 0, pbn_b0_bt_2_115200 },
5209
14faa8cc
MS		 5210 /*
5211 * Commtech, Inc. Fastcom adapters
5212 */
5213 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5214 PCI_ANY_ID, PCI_ANY_ID,
5215 0,
5216 0, pbn_b0_2_1152000_200 },
5217 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5218 PCI_ANY_ID, PCI_ANY_ID,
5219 0,
5220 0, pbn_b0_4_1152000_200 },
5221 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5222 PCI_ANY_ID, PCI_ANY_ID,
5223 0,
5224 0, pbn_b0_4_1152000_200 },
5225 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5226 PCI_ANY_ID, PCI_ANY_ID,
5227 0,
5228 0, pbn_b0_8_1152000_200 },
5229 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5230 PCI_ANY_ID, PCI_ANY_ID,
5231 0,
5232 0, pbn_exar_XR17V352 },
5233 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5234 PCI_ANY_ID, PCI_ANY_ID,
5235 0,
5236 0, pbn_exar_XR17V354 },
5237 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5238 PCI_ANY_ID, PCI_ANY_ID,
5239 0,
5240 0, pbn_exar_XR17V358 },
5241
2c62a3c8
GKH		 5242 /* Fintek PCI serial cards */
5243 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5244 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5245 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5246
1da177e4
LT		 5247 /*
5248 * These entries match devices with class COMMUNICATION_SERIAL,
5249 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5250 */
5251 { PCI_ANY_ID, PCI_ANY_ID,
5252 PCI_ANY_ID, PCI_ANY_ID,
5253 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5254 0xffff00, pbn_default },
5255 { PCI_ANY_ID, PCI_ANY_ID,
5256 PCI_ANY_ID, PCI_ANY_ID,
5257 PCI_CLASS_COMMUNICATION_MODEM << 8,
5258 0xffff00, pbn_default },
5259 { PCI_ANY_ID, PCI_ANY_ID,
5260 PCI_ANY_ID, PCI_ANY_ID,
5261 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5262 0xffff00, pbn_default },
5263 { 0, }
5264};
5265
2807190b
MR		 5266static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5267 pci_channel_state_t state)
5268{
5269 struct serial_private *priv = pci_get_drvdata(dev);
5270
5271 if (state == pci_channel_io_perm_failure)
5272 return PCI_ERS_RESULT_DISCONNECT;
5273
5274 if (priv)
5275 pciserial_suspend_ports(priv);
5276
5277 pci_disable_device(dev);
5278
5279 return PCI_ERS_RESULT_NEED_RESET;
5280}
5281
5282static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5283{
5284 int rc;
5285
5286 rc = pci_enable_device(dev);
5287
5288 if (rc)
5289 return PCI_ERS_RESULT_DISCONNECT;
5290
5291 pci_restore_state(dev);
5292 pci_save_state(dev);
5293
5294 return PCI_ERS_RESULT_RECOVERED;
5295}
5296
5297static void serial8250_io_resume(struct pci_dev *dev)
5298{
5299 struct serial_private *priv = pci_get_drvdata(dev);
5300
5301 if (priv)
5302 pciserial_resume_ports(priv);
5303}
5304
1d352035 5305static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 5306 .error_detected = serial8250_io_error_detected,
5307 .slot_reset = serial8250_io_slot_reset,
5308 .resume = serial8250_io_resume,
5309};
5310
1da177e4
LT		 5311static struct pci_driver serial_pci_driver = {
5312 .name = "serial",
5313 .probe = pciserial_init_one,
2d47b716 5314 .remove = pciserial_remove_one,
1d5e7996 5315#ifdef CONFIG_PM
1da177e4
LT		 5316 .suspend = pciserial_suspend_one,
5317 .resume = pciserial_resume_one,
1d5e7996 5318#endif
1da177e4 5319 .id_table = serial_pci_tbl,
2807190b 5320 .err_handler = &serial8250_err_handler,
1da177e4
LT		 5321};
5322
15a12e83 5323module_pci_driver(serial_pci_driver);
1da177e4
LT		 5324
5325MODULE_LICENSE("GPL");
5326MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5327MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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