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sc16is7xx: constify devtype
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4 11 */
af8c5b8d 12#undef DEBUG
1da177e4 13#include <linux/module.h>
1da177e4 14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
21947ba6 24#include <linux/rational.h>
1da177e4
LT		 25
26#include <asm/byteorder.h>
27#include <asm/io.h>
28
9a1870ce
AS		 29#include <linux/dmaengine.h>
30#include <linux/platform_data/dma-dw.h>
f549e94e 31#include <linux/platform_data/dma-hsu.h>
9a1870ce 32
1da177e4
LT		 33#include "8250.h"
34
1da177e4
LT		 35/*
36 * init function returns:
37 * > 0 - number of ports
38 * = 0 - use board->num_ports
39 * < 0 - error
40 */
41struct pci_serial_quirk {
42 u32 vendor;
43 u32 device;
44 u32 subvendor;
45 u32 subdevice;
5bf8f501 46 int (*probe)(struct pci_dev *dev);
1da177e4 47 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 48 int (*setup)(struct serial_private *,
49 const struct pciserial_board *,
2655a2c7 50 struct uart_8250_port *, int);
1da177e4
LT		 51 void (*exit)(struct pci_dev *dev);
52};
53
54#define PCI_NUM_BAR_RESOURCES 6
55
56struct serial_private {
70db3d91 57 struct pci_dev *dev;
1da177e4
LT		 58 unsigned int nr;
59 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
60 struct pci_serial_quirk *quirk;
61 int line[0];
62};
63
7808edcd 64static int pci_default_setup(struct serial_private*,
2655a2c7 65 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 66
1da177e4
LT		 67static void moan_device(const char *str, struct pci_dev *dev)
68{
af8c5b8d 69 dev_err(&dev->dev,
ad361c98
JP		 70 "%s: %s\n"
71 "Please send the output of lspci -vv, this\n"
72 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
73 "manufacturer and name of serial board or\n"
f2e0ea86 74 "modem board to <linux-serial@vger.kernel.org>.\n",
1da177e4
LT		 75 pci_name(dev), str, dev->vendor, dev->device,
76 dev->subsystem_vendor, dev->subsystem_device);
77}
78
79static int
2655a2c7 80setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 81 int bar, int offset, int regshift)
82{
70db3d91 83 struct pci_dev *dev = priv->dev;
1da177e4
LT		 84
85 if (bar >= PCI_NUM_BAR_RESOURCES)
86 return -EINVAL;
87
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4 89 if (!priv->remapped_bar[bar])
398a9db6 90 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
1da177e4
LT		 91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
2655a2c7
AC		 94 port->port.iotype = UPIO_MEM;
95 port->port.iobase = 0;
398a9db6 96 port->port.mapbase = pci_resource_start(dev, bar) + offset;
2655a2c7
AC		 97 port->port.membase = priv->remapped_bar[bar] + offset;
98 port->port.regshift = regshift;
1da177e4 99 } else {
2655a2c7 100 port->port.iotype = UPIO_PORT;
398a9db6 101 port->port.iobase = pci_resource_start(dev, bar) + offset;
2655a2c7
AC		 102 port->port.mapbase = 0;
103 port->port.membase = NULL;
104 port->port.regshift = 0;
1da177e4
LT		 105 }
106 return 0;
107}
108
02c9b5cf
KJ		 109/*
110 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 */
112static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 113 const struct pciserial_board *board,
2655a2c7 114 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 115{
116 unsigned int bar = 0, offset = board->first_offset;
117 bar = FL_GET_BASE(board->flags);
118
119 if (idx < 2) {
120 offset += idx * board->uart_offset;
121 } else if ((idx >= 2) && (idx < 4)) {
122 bar += 1;
123 offset += ((idx - 2) * board->uart_offset);
124 } else if ((idx >= 4) && (idx < 6)) {
125 bar += 2;
126 offset += ((idx - 4) * board->uart_offset);
127 } else if (idx >= 6) {
128 bar += 3;
129 offset += ((idx - 6) * board->uart_offset);
130 }
131
132 return setup_port(priv, port, bar, offset, board->reg_shift);
133}
134
1da177e4
LT		 135/*
136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
138 */
139static int
975a1a7d 140afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 141 struct uart_8250_port *port, int idx)
1da177e4
LT		 142{
143 unsigned int bar, offset = board->first_offset;
5756ee99 144
1da177e4
LT		 145 bar = FL_GET_BASE(board->flags);
146 if (idx < 4)
147 bar += idx;
148 else {
149 bar = 4;
150 offset += (idx - 4) * board->uart_offset;
151 }
152
70db3d91 153 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 154}
155
156/*
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
162 */
61a116ef 163static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 164{
165 int rc = 0;
166
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 rc = 3;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 rc = 2;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 rc = 4;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 182 rc = 1;
183 break;
184 }
185
186 return rc;
187}
188
189/*
190 * HP's Diva chip puts the 4th/5th serial port further out, and
191 * some serial ports are supposed to be hidden on certain models.
192 */
193static int
975a1a7d
RK		 194pci_hp_diva_setup(struct serial_private *priv,
195 const struct pciserial_board *board,
2655a2c7 196 struct uart_8250_port *port, int idx)
1da177e4
LT		 197{
198 unsigned int offset = board->first_offset;
199 unsigned int bar = FL_GET_BASE(board->flags);
200
70db3d91 201 switch (priv->dev->subsystem_device) {
1da177e4
LT		 202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
203 if (idx == 3)
204 idx++;
205 break;
206 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
207 if (idx > 0)
208 idx++;
209 if (idx > 2)
210 idx++;
211 break;
212 }
213 if (idx > 2)
214 offset = 0x18;
215
216 offset += idx * board->uart_offset;
217
70db3d91 218 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 219}
220
221/*
222 * Added for EKF Intel i960 serial boards
223 */
61a116ef 224static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4 225{
0a0d412a 226 u32 oldval;
1da177e4
LT		 227
228 if (!(dev->subsystem_device & 0x1000))
229 return -ENODEV;
230
231 /* is firmware started? */
0a0d412a 232 pci_read_config_dword(dev, 0x44, &oldval);
5756ee99 233 if (oldval == 0x00001000L) { /* RESET value */
af8c5b8d 234 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
1da177e4
LT		 235 return -ENODEV;
236 }
237 return 0;
238}
239
240/*
241 * Some PCI serial cards using the PLX 9050 PCI interface chip require
242 * that the card interrupt be explicitly enabled or disabled. This
243 * seems to be mainly needed on card using the PLX which also use I/O
244 * mapped memory.
245 */
61a116ef 246static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 247{
248 u8 irq_config;
249 void __iomem *p;
250
251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
252 moan_device("no memory in bar 0", dev);
253 return 0;
254 }
255
256 irq_config = 0x41;
add7b58e 257 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 259 irq_config = 0x43;
5756ee99 260
1da177e4 261 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 263 /*
264 * As the megawolf cards have the int pins active
265 * high, and have 2 UART chips, both ints must be
266 * enabled on the 9050. Also, the UARTS are set in
267 * 16450 mode by default, so we have to enable the
268 * 16C950 'enhanced' mode so that we can use the
269 * deep FIFOs
270 */
271 irq_config = 0x5b;
1da177e4
LT		 272 /*
273 * enable/disable interrupts
274 */
6f441fe9 275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 276 if (p == NULL)
277 return -ENOMEM;
278 writel(irq_config, p + 0x4c);
279
280 /*
281 * Read the register back to ensure that it took effect.
282 */
283 readl(p + 0x4c);
284 iounmap(p);
285
286 return 0;
287}
288
ae8d8a14 289static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 290{
291 u8 __iomem *p;
292
293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
294 return;
295
296 /*
297 * disable interrupts
298 */
6f441fe9 299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 300 if (p != NULL) {
301 writel(0, p + 0x4c);
302
303 /*
304 * Read the register back to ensure that it took effect.
305 */
306 readl(p + 0x4c);
307 iounmap(p);
308 }
309}
310
04bf7e74
WP		 311#define NI8420_INT_ENABLE_REG 0x38
312#define NI8420_INT_ENABLE_BIT 0x2000
313
ae8d8a14 314static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 315{
316 void __iomem *p;
04bf7e74
WP		 317 unsigned int bar = 0;
318
319 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
320 moan_device("no memory in bar", dev);
321 return;
322 }
323
398a9db6 324 p = pci_ioremap_bar(dev, bar);
04bf7e74
WP		 325 if (p == NULL)
326 return;
327
328 /* Disable the CPU Interrupt */
329 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
330 p + NI8420_INT_ENABLE_REG);
331 iounmap(p);
332}
333
334
46a0fac9
SB		 335/* MITE registers */
336#define MITE_IOWBSR1 0xc4
337#define MITE_IOWCR1 0xf4
338#define MITE_LCIMR1 0x08
339#define MITE_LCIMR2 0x10
340
341#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342
ae8d8a14 343static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 344{
345 void __iomem *p;
46a0fac9
SB		 346 unsigned int bar = 0;
347
348 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
349 moan_device("no memory in bar", dev);
350 return;
351 }
352
398a9db6 353 p = pci_ioremap_bar(dev, bar);
46a0fac9
SB		 354 if (p == NULL)
355 return;
356
357 /* Disable the CPU Interrupt */
358 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
359 iounmap(p);
360}
361
1da177e4
LT		 362/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
363static int
975a1a7d 364sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 365 struct uart_8250_port *port, int idx)
1da177e4
LT		 366{
367 unsigned int bar, offset = board->first_offset;
368
369 bar = 0;
370
371 if (idx < 4) {
372 /* first four channels map to 0, 0x100, 0x200, 0x300 */
373 offset += idx * board->uart_offset;
374 } else if (idx < 8) {
375 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
376 offset += idx * board->uart_offset + 0xC00;
377 } else /* we have only 8 ports on PMC-OCTALPRO */
378 return 1;
379
70db3d91 380 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 381}
382
383/*
384* This does initialization for PMC OCTALPRO cards:
385* maps the device memory, resets the UARTs (needed, bc
386* if the module is removed and inserted again, the card
387* is in the sleep mode) and enables global interrupt.
388*/
389
390/* global control register offset for SBS PMC-OctalPro */
391#define OCT_REG_CR_OFF 0x500
392
61a116ef 393static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 394{
395 u8 __iomem *p;
396
24ed3aba 397 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 398
399 if (p == NULL)
400 return -ENOMEM;
401 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 402 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 403 udelay(50);
5756ee99 404 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 405
406 /* Set bit-2 (INTENABLE) of Control Register */
407 writeb(0x4, p + OCT_REG_CR_OFF);
408 iounmap(p);
409
410 return 0;
411}
412
413/*
414 * Disables the global interrupt of PMC-OctalPro
415 */
416
ae8d8a14 417static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 418{
419 u8 __iomem *p;
420
24ed3aba 421 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 422 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
423 if (p != NULL)
1da177e4 424 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 425 iounmap(p);
426}
427
428/*
429 * SIIG serial cards have an PCI interface chip which also controls
430 * the UART clocking frequency. Each UART can be clocked independently
25985edc 431 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 432 * are stored in the EEPROM chip. It can cause problems because this
433 * version of serial driver doesn't support differently clocked UART's
434 * on single PCI card. To prevent this, initialization functions set
435 * high frequency clocking for all UART's on given card. It is safe (I
436 * hope) because it doesn't touch EEPROM settings to prevent conflicts
437 * with other OSes (like M$ DOS).
438 *
439 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 440 *
1da177e4
LT		 441 * There is two family of SIIG serial cards with different PCI
442 * interface chip and different configuration methods:
443 * - 10x cards have control registers in IO and/or memory space;
444 * - 20x cards have control registers in standard PCI configuration space.
445 *
67d74b87
RK		 446 * Note: all 10x cards have PCI device ids 0x10..
447 * all 20x cards have PCI device ids 0x20..
448 *
fbc0dc0d
AP		 449 * There are also Quartet Serial cards which use Oxford Semiconductor
450 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
451 *
1da177e4
LT		 452 * Note: some SIIG cards are probed by the parport_serial object.
453 */
454
455#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
456#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
457
458static int pci_siig10x_init(struct pci_dev *dev)
459{
460 u16 data;
461 void __iomem *p;
462
463 switch (dev->device & 0xfff8) {
464 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
465 data = 0xffdf;
466 break;
467 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
468 data = 0xf7ff;
469 break;
470 default: /* 1S1P, 4S */
471 data = 0xfffb;
472 break;
473 }
474
6f441fe9 475 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 476 if (p == NULL)
477 return -ENOMEM;
478
479 writew(readw(p + 0x28) & data, p + 0x28);
480 readw(p + 0x28);
481 iounmap(p);
482 return 0;
483}
484
485#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
486#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
487
488static int pci_siig20x_init(struct pci_dev *dev)
489{
490 u8 data;
491
492 /* Change clock frequency for the first UART. */
493 pci_read_config_byte(dev, 0x6f, &data);
494 pci_write_config_byte(dev, 0x6f, data & 0xef);
495
496 /* If this card has 2 UART, we have to do the same with second UART. */
497 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
498 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
499 pci_read_config_byte(dev, 0x73, &data);
500 pci_write_config_byte(dev, 0x73, data & 0xef);
501 }
502 return 0;
503}
504
67d74b87
RK		 505static int pci_siig_init(struct pci_dev *dev)
506{
507 unsigned int type = dev->device & 0xff00;
508
509 if (type == 0x1000)
510 return pci_siig10x_init(dev);
511 else if (type == 0x2000)
512 return pci_siig20x_init(dev);
513
514 moan_device("Unknown SIIG card", dev);
515 return -ENODEV;
516}
517
3ec9c594 518static int pci_siig_setup(struct serial_private *priv,
975a1a7d 519 const struct pciserial_board *board,
2655a2c7 520 struct uart_8250_port *port, int idx)
3ec9c594
AP		 521{
522 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
523
524 if (idx > 3) {
525 bar = 4;
526 offset = (idx - 4) * 8;
527 }
528
529 return setup_port(priv, port, bar, offset, 0);
530}
531
1da177e4
LT		 532/*
533 * Timedia has an explosion of boards, and to avoid the PCI table from
534 * growing *huge*, we use this function to collapse some 70 entries
535 * in the PCI table into one, for sanity's and compactness's sake.
536 */
e9422e09 537static const unsigned short timedia_single_port[] = {
1da177e4
LT		 538 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
539};
540
e9422e09 541static const unsigned short timedia_dual_port[] = {
1da177e4 542 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 543 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
544 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 545 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
546 0xD079, 0
547};
548
e9422e09 549static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 550 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
551 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 552 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
553 0xB157, 0
554};
555
e9422e09 556static const unsigned short timedia_eight_port[] = {
5756ee99 557 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 558 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
559};
560
cb3592be 561static const struct timedia_struct {
1da177e4 562 int num;
e9422e09 563 const unsigned short *ids;
1da177e4
LT		 564} timedia_data[] = {
565 { 1, timedia_single_port },
566 { 2, timedia_dual_port },
567 { 4, timedia_quad_port },
e9422e09 568 { 8, timedia_eight_port }
1da177e4
LT		 569};
570
b9b24558
FB		 571/*
572 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
573 * listing them individually, this driver merely grabs them all with
574 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
575 * and should be left free to be claimed by parport_serial instead.
576 */
577static int pci_timedia_probe(struct pci_dev *dev)
578{
579 /*
580 * Check the third digit of the subdevice ID
581 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
582 */
583 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
584 dev_info(&dev->dev,
585 "ignoring Timedia subdevice %04x for parport_serial\n",
586 dev->subsystem_device);
587 return -ENODEV;
588 }
589
590 return 0;
591}
592
61a116ef 593static int pci_timedia_init(struct pci_dev *dev)
1da177e4 594{
e9422e09 595 const unsigned short *ids;
1da177e4
LT		 596 int i, j;
597
e9422e09 598 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 599 ids = timedia_data[i].ids;
600 for (j = 0; ids[j]; j++)
601 if (dev->subsystem_device == ids[j])
602 return timedia_data[i].num;
603 }
604 return 0;
605}
606
607/*
608 * Timedia/SUNIX uses a mixture of BARs and offsets
609 * Ugh, this is ugly as all hell --- TYT
610 */
611static int
975a1a7d
RK		 612pci_timedia_setup(struct serial_private *priv,
613 const struct pciserial_board *board,
2655a2c7 614 struct uart_8250_port *port, int idx)
1da177e4
LT		 615{
616 unsigned int bar = 0, offset = board->first_offset;
617
618 switch (idx) {
619 case 0:
620 bar = 0;
621 break;
622 case 1:
623 offset = board->uart_offset;
624 bar = 0;
625 break;
626 case 2:
627 bar = 1;
628 break;
629 case 3:
630 offset = board->uart_offset;
c2cd6d3c 631 /* FALLTHROUGH */
1da177e4
LT		 632 case 4: /* BAR 2 */
633 case 5: /* BAR 3 */
634 case 6: /* BAR 4 */
635 case 7: /* BAR 5 */
636 bar = idx - 2;
637 }
638
70db3d91 639 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 640}
641
642/*
643 * Some Titan cards are also a little weird
644 */
645static int
70db3d91 646titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 647 const struct pciserial_board *board,
2655a2c7 648 struct uart_8250_port *port, int idx)
1da177e4
LT		 649{
650 unsigned int bar, offset = board->first_offset;
651
652 switch (idx) {
653 case 0:
654 bar = 1;
655 break;
656 case 1:
657 bar = 2;
658 break;
659 default:
660 bar = 4;
661 offset = (idx - 2) * board->uart_offset;
662 }
663
70db3d91 664 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 665}
666
61a116ef 667static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 668{
669 msleep(100);
670 return 0;
671}
672
04bf7e74
WP		 673static int pci_ni8420_init(struct pci_dev *dev)
674{
675 void __iomem *p;
04bf7e74
WP		 676 unsigned int bar = 0;
677
678 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
679 moan_device("no memory in bar", dev);
680 return 0;
681 }
682
398a9db6 683 p = pci_ioremap_bar(dev, bar);
04bf7e74
WP		 684 if (p == NULL)
685 return -ENOMEM;
686
687 /* Enable CPU Interrupt */
688 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
689 p + NI8420_INT_ENABLE_REG);
690
691 iounmap(p);
692 return 0;
693}
694
46a0fac9
SB		 695#define MITE_IOWBSR1_WSIZE 0xa
696#define MITE_IOWBSR1_WIN_OFFSET 0x800
697#define MITE_IOWBSR1_WENAB (1 << 7)
698#define MITE_LCIMR1_IO_IE_0 (1 << 24)
699#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
700#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
701
702static int pci_ni8430_init(struct pci_dev *dev)
703{
704 void __iomem *p;
398a9db6 705 struct pci_bus_region region;
46a0fac9
SB		 706 u32 device_window;
707 unsigned int bar = 0;
708
709 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
710 moan_device("no memory in bar", dev);
711 return 0;
712 }
713
398a9db6 714 p = pci_ioremap_bar(dev, bar);
46a0fac9
SB		 715 if (p == NULL)
716 return -ENOMEM;
717
398a9db6
AS		 718 /*
719 * Set device window address and size in BAR0, while acknowledging that
720 * the resource structure may contain a translated address that differs
721 * from the address the device responds to.
722 */
723 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
724 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
46a0fac9
SB		 725 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
726 writel(device_window, p + MITE_IOWBSR1);
727
728 /* Set window access to go to RAMSEL IO address space */
729 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
730 p + MITE_IOWCR1);
731
732 /* Enable IO Bus Interrupt 0 */
733 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
734
735 /* Enable CPU Interrupt */
736 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
737
738 iounmap(p);
739 return 0;
740}
741
742/* UART Port Control Register */
743#define NI8430_PORTCON 0x0f
744#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
745
746static int
bf538fe4
AC		 747pci_ni8430_setup(struct serial_private *priv,
748 const struct pciserial_board *board,
2655a2c7 749 struct uart_8250_port *port, int idx)
46a0fac9 750{
398a9db6 751 struct pci_dev *dev = priv->dev;
46a0fac9 752 void __iomem *p;
46a0fac9
SB		 753 unsigned int bar, offset = board->first_offset;
754
755 if (idx >= board->num_ports)
756 return 1;
757
758 bar = FL_GET_BASE(board->flags);
759 offset += idx * board->uart_offset;
760
398a9db6 761 p = pci_ioremap_bar(dev, bar);
5d14bba9
AS		 762 if (!p)
763 return -ENOMEM;
46a0fac9 764
7c9d440e 765 /* enable the transceiver */
46a0fac9
SB		 766 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
767 p + offset + NI8430_PORTCON);
768
769 iounmap(p);
770
771 return setup_port(priv, port, bar, offset, board->reg_shift);
772}
773
7808edcd
NG		 774static int pci_netmos_9900_setup(struct serial_private *priv,
775 const struct pciserial_board *board,
2655a2c7 776 struct uart_8250_port *port, int idx)
7808edcd
NG		 777{
778 unsigned int bar;
779
333c085e
DES		 780 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
781 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
7808edcd
NG		 782 /* netmos apparently orders BARs by datasheet layout, so serial
783 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
784 */
785 bar = 3 * idx;
786
787 return setup_port(priv, port, bar, 0, board->reg_shift);
788 } else {
789 return pci_default_setup(priv, board, port, idx);
790 }
791}
792
793/* the 99xx series comes with a range of device IDs and a variety
794 * of capabilities:
795 *
796 * 9900 has varying capabilities and can cascade to sub-controllers
797 * (cascading should be purely internal)
798 * 9904 is hardwired with 4 serial ports
799 * 9912 and 9922 are hardwired with 2 serial ports
800 */
801static int pci_netmos_9900_numports(struct pci_dev *dev)
802{
803 unsigned int c = dev->class;
804 unsigned int pi;
805 unsigned short sub_serports;
806
807 pi = (c & 0xff);
808
809 if (pi == 2) {
810 return 1;
811 } else if ((pi == 0) &&
812 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
813 /* two possibilities: 0x30ps encodes number of parallel and
814 * serial ports, or 0x1000 indicates *something*. This is not
815 * immediately obvious, since the 2s1p+4s configuration seems
816 * to offer all functionality on functions 0..2, while still
817 * advertising the same function 3 as the 4s+2s1p config.
818 */
819 sub_serports = dev->subsystem_device & 0xf;
820 if (sub_serports > 0) {
821 return sub_serports;
822 } else {
af8c5b8d 823 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
7808edcd
NG		 824 return 0;
825 }
826 }
827
828 moan_device("unknown NetMos/Mostech program interface", dev);
829 return 0;
830}
46a0fac9 831
61a116ef 832static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 833{
834 /* subdevice 0x00PS means <P> parallel, <S> serial */
835 unsigned int num_serial = dev->subsystem_device & 0xf;
836
ac6ec5b1
IS		 837 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
838 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 839 return 0;
7808edcd 840
25cf9bc1
JS		 841 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
842 dev->subsystem_device == 0x0299)
843 return 0;
844
7808edcd
NG		 845 switch (dev->device) { /* FALLTHROUGH on all */
846 case PCI_DEVICE_ID_NETMOS_9904:
847 case PCI_DEVICE_ID_NETMOS_9912:
848 case PCI_DEVICE_ID_NETMOS_9922:
849 case PCI_DEVICE_ID_NETMOS_9900:
850 num_serial = pci_netmos_9900_numports(dev);
851 break;
852
853 default:
854 if (num_serial == 0 ) {
855 moan_device("unknown NetMos/Mostech device", dev);
856 }
857 }
858
1da177e4
LT		 859 if (num_serial == 0)
860 return -ENODEV;
7808edcd 861
1da177e4
LT		 862 return num_serial;
863}
864
84f8c6fc 865/*
84f8c6fc
NV		 866 * These chips are available with optionally one parallel port and up to
867 * two serial ports. Unfortunately they all have the same product id.
868 *
869 * Basic configuration is done over a region of 32 I/O ports. The base
870 * ioport is called INTA or INTC, depending on docs/other drivers.
871 *
872 * The region of the 32 I/O ports is configured in POSIO0R...
873 */
874
875/* registers */
876#define ITE_887x_MISCR 0x9c
877#define ITE_887x_INTCBAR 0x78
878#define ITE_887x_UARTBAR 0x7c
879#define ITE_887x_PS0BAR 0x10
880#define ITE_887x_POSIO0 0x60
881
882/* I/O space size */
883#define ITE_887x_IOSIZE 32
884/* I/O space size (bits 26-24; 8 bytes = 011b) */
885#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
886/* I/O space size (bits 26-24; 32 bytes = 101b) */
887#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
888/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
889#define ITE_887x_POSIO_SPEED (3 << 29)
890/* enable IO_Space bit */
891#define ITE_887x_POSIO_ENABLE (1 << 31)
892
f79abb82 893static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 894{
895 /* inta_addr are the configuration addresses of the ITE */
896 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
897 0x200, 0x280, 0 };
898 int ret, i, type;
899 struct resource *iobase = NULL;
900 u32 miscr, uartbar, ioport;
901
902 /* search for the base-ioport */
903 i = 0;
904 while (inta_addr[i] && iobase == NULL) {
905 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
906 "ite887x");
907 if (iobase != NULL) {
908 /* write POSIO0R - speed | size | ioport */
909 pci_write_config_dword(dev, ITE_887x_POSIO0,
910 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
911 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
912 /* write INTCBAR - ioport */
5756ee99
AC		 913 pci_write_config_dword(dev, ITE_887x_INTCBAR,
914 inta_addr[i]);
84f8c6fc
NV		 915 ret = inb(inta_addr[i]);
916 if (ret != 0xff) {
917 /* ioport connected */
918 break;
919 }
920 release_region(iobase->start, ITE_887x_IOSIZE);
921 iobase = NULL;
922 }
923 i++;
924 }
925
926 if (!inta_addr[i]) {
af8c5b8d 927 dev_err(&dev->dev, "ite887x: could not find iobase\n");
84f8c6fc
NV		 928 return -ENODEV;
929 }
930
931 /* start of undocumented type checking (see parport_pc.c) */
932 type = inb(iobase->start + 0x18) & 0x0f;
933
934 switch (type) {
935 case 0x2: /* ITE8871 (1P) */
936 case 0xa: /* ITE8875 (1P) */
937 ret = 0;
938 break;
939 case 0xe: /* ITE8872 (2S1P) */
940 ret = 2;
941 break;
942 case 0x6: /* ITE8873 (1S) */
943 ret = 1;
944 break;
945 case 0x8: /* ITE8874 (2S) */
946 ret = 2;
947 break;
948 default:
949 moan_device("Unknown ITE887x", dev);
950 ret = -ENODEV;
951 }
952
953 /* configure all serial ports */
954 for (i = 0; i < ret; i++) {
955 /* read the I/O port from the device */
956 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
957 &ioport);
958 ioport &= 0x0000FF00; /* the actual base address */
959 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
960 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
961 ITE_887x_POSIO_IOSIZE_8 | ioport);
962
963 /* write the ioport to the UARTBAR */
964 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
965 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
966 uartbar |= (ioport << (16 * i)); /* set the ioport */
967 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
968
969 /* get current config */
970 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
971 /* disable interrupts (UARTx_Routing[3:0]) */
972 miscr &= ~(0xf << (12 - 4 * i));
973 /* activate the UART (UARTx_En) */
974 miscr |= 1 << (23 - i);
975 /* write new config with activated UART */
976 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
977 }
978
979 if (ret <= 0) {
980 /* the device has no UARTs if we get here */
981 release_region(iobase->start, ITE_887x_IOSIZE);
982 }
983
984 return ret;
985}
986
ae8d8a14 987static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 988{
989 u32 ioport;
990 /* the ioport is bit 0-15 in POSIO0R */
991 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
992 ioport &= 0xffff;
993 release_region(ioport, ITE_887x_IOSIZE);
994}
995
1bc8cde4
MS		 996/*
997 * EndRun Technologies.
998 * Determine the number of ports available on the device.
999 */
1000#define PCI_VENDOR_ID_ENDRUN 0x7401
1001#define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1002
1003static int pci_endrun_init(struct pci_dev *dev)
1004{
1005 u8 __iomem *p;
1006 unsigned long deviceID;
1007 unsigned int number_uarts = 0;
1008
1009 /* EndRun device is all 0xexxx */
1010 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1011 (dev->device & 0xf000) != 0xe000)
1012 return 0;
1013
1014 p = pci_iomap(dev, 0, 5);
1015 if (p == NULL)
1016 return -ENOMEM;
1017
1018 deviceID = ioread32(p);
1019 /* EndRun device */
1020 if (deviceID == 0x07000200) {
1021 number_uarts = ioread8(p + 4);
1022 dev_dbg(&dev->dev,
1023 "%d ports detected on EndRun PCI Express device\n",
1024 number_uarts);
1025 }
1026 pci_iounmap(dev, p);
1027 return number_uarts;
1028}
1029
9f2a036a
RK		 1030/*
1031 * Oxford Semiconductor Inc.
1032 * Check that device is part of the Tornado range of devices, then determine
1033 * the number of ports available on the device.
1034 */
1035static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1036{
1037 u8 __iomem *p;
1038 unsigned long deviceID;
1039 unsigned int number_uarts = 0;
1040
1041 /* OxSemi Tornado devices are all 0xCxxx */
1042 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1043 (dev->device & 0xF000) != 0xC000)
1044 return 0;
1045
1046 p = pci_iomap(dev, 0, 5);
1047 if (p == NULL)
1048 return -ENOMEM;
1049
1050 deviceID = ioread32(p);
1051 /* Tornado device */
1052 if (deviceID == 0x07000200) {
1053 number_uarts = ioread8(p + 4);
af8c5b8d 1054 dev_dbg(&dev->dev,
9f2a036a 1055 "%d ports detected on Oxford PCI Express device\n",
af8c5b8d 1056 number_uarts);
9f2a036a
RK		 1057 }
1058 pci_iounmap(dev, p);
1059 return number_uarts;
1060}
1061
eb26dfe8
AC		 1062static int pci_asix_setup(struct serial_private *priv,
1063 const struct pciserial_board *board,
1064 struct uart_8250_port *port, int idx)
1065{
1066 port->bugs |= UART_BUG_PARITY;
1067 return pci_default_setup(priv, board, port, idx);
1068}
1069
55c7c0fd
AC		 1070/* Quatech devices have their own extra interface features */
1071
1072struct quatech_feature {
1073 u16 devid;
1074 bool amcc;
1075};
1076
1077#define QPCR_TEST_FOR1 0x3F
1078#define QPCR_TEST_GET1 0x00
1079#define QPCR_TEST_FOR2 0x40
1080#define QPCR_TEST_GET2 0x40
1081#define QPCR_TEST_FOR3 0x80
1082#define QPCR_TEST_GET3 0x40
1083#define QPCR_TEST_FOR4 0xC0
1084#define QPCR_TEST_GET4 0x80
1085
1086#define QOPR_CLOCK_X1 0x0000
1087#define QOPR_CLOCK_X2 0x0001
1088#define QOPR_CLOCK_X4 0x0002
1089#define QOPR_CLOCK_X8 0x0003
1090#define QOPR_CLOCK_RATE_MASK 0x0003
1091
1092
1093static struct quatech_feature quatech_cards[] = {
1094 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1096 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1097 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1098 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1099 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1100 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1101 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1102 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1103 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1104 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1105 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1108 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1109 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1111 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1112 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1113 { 0, }
1114};
1115
1116static int pci_quatech_amcc(u16 devid)
1117{
1118 struct quatech_feature *qf = &quatech_cards[0];
1119 while (qf->devid) {
1120 if (qf->devid == devid)
1121 return qf->amcc;
1122 qf++;
1123 }
1124 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1125 return 0;
1126};
1127
1128static int pci_quatech_rqopr(struct uart_8250_port *port)
1129{
1130 unsigned long base = port->port.iobase;
1131 u8 LCR, val;
1132
1133 LCR = inb(base + UART_LCR);
1134 outb(0xBF, base + UART_LCR);
1135 val = inb(base + UART_SCR);
1136 outb(LCR, base + UART_LCR);
1137 return val;
1138}
1139
1140static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1141{
1142 unsigned long base = port->port.iobase;
1143 u8 LCR, val;
1144
1145 LCR = inb(base + UART_LCR);
1146 outb(0xBF, base + UART_LCR);
1147 val = inb(base + UART_SCR);
1148 outb(qopr, base + UART_SCR);
1149 outb(LCR, base + UART_LCR);
1150}
1151
1152static int pci_quatech_rqmcr(struct uart_8250_port *port)
1153{
1154 unsigned long base = port->port.iobase;
1155 u8 LCR, val, qmcr;
1156
1157 LCR = inb(base + UART_LCR);
1158 outb(0xBF, base + UART_LCR);
1159 val = inb(base + UART_SCR);
1160 outb(val | 0x10, base + UART_SCR);
1161 qmcr = inb(base + UART_MCR);
1162 outb(val, base + UART_SCR);
1163 outb(LCR, base + UART_LCR);
1164
1165 return qmcr;
1166}
1167
1168static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1169{
1170 unsigned long base = port->port.iobase;
1171 u8 LCR, val;
1172
1173 LCR = inb(base + UART_LCR);
1174 outb(0xBF, base + UART_LCR);
1175 val = inb(base + UART_SCR);
1176 outb(val | 0x10, base + UART_SCR);
1177 outb(qmcr, base + UART_MCR);
1178 outb(val, base + UART_SCR);
1179 outb(LCR, base + UART_LCR);
1180}
1181
1182static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1183{
1184 unsigned long base = port->port.iobase;
1185 u8 LCR, val;
1186
1187 LCR = inb(base + UART_LCR);
1188 outb(0xBF, base + UART_LCR);
1189 val = inb(base + UART_SCR);
1190 if (val & 0x20) {
1191 outb(0x80, UART_LCR);
1192 if (!(inb(UART_SCR) & 0x20)) {
1193 outb(LCR, base + UART_LCR);
1194 return 1;
1195 }
1196 }
1197 return 0;
1198}
1199
1200static int pci_quatech_test(struct uart_8250_port *port)
1201{
1202 u8 reg;
1203 u8 qopr = pci_quatech_rqopr(port);
1204 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1205 reg = pci_quatech_rqopr(port) & 0xC0;
1206 if (reg != QPCR_TEST_GET1)
1207 return -EINVAL;
1208 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1209 reg = pci_quatech_rqopr(port) & 0xC0;
1210 if (reg != QPCR_TEST_GET2)
1211 return -EINVAL;
1212 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1213 reg = pci_quatech_rqopr(port) & 0xC0;
1214 if (reg != QPCR_TEST_GET3)
1215 return -EINVAL;
1216 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1217 reg = pci_quatech_rqopr(port) & 0xC0;
1218 if (reg != QPCR_TEST_GET4)
1219 return -EINVAL;
1220
1221 pci_quatech_wqopr(port, qopr);
1222 return 0;
1223}
1224
1225static int pci_quatech_clock(struct uart_8250_port *port)
1226{
1227 u8 qopr, reg, set;
1228 unsigned long clock;
1229
1230 if (pci_quatech_test(port) < 0)
1231 return 1843200;
1232
1233 qopr = pci_quatech_rqopr(port);
1234
1235 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1236 reg = pci_quatech_rqopr(port);
1237 if (reg & QOPR_CLOCK_X8) {
1238 clock = 1843200;
1239 goto out;
1240 }
1241 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1242 reg = pci_quatech_rqopr(port);
1243 if (!(reg & QOPR_CLOCK_X8)) {
1244 clock = 1843200;
1245 goto out;
1246 }
1247 reg &= QOPR_CLOCK_X8;
1248 if (reg == QOPR_CLOCK_X2) {
1249 clock = 3685400;
1250 set = QOPR_CLOCK_X2;
1251 } else if (reg == QOPR_CLOCK_X4) {
1252 clock = 7372800;
1253 set = QOPR_CLOCK_X4;
1254 } else if (reg == QOPR_CLOCK_X8) {
1255 clock = 14745600;
1256 set = QOPR_CLOCK_X8;
1257 } else {
1258 clock = 1843200;
1259 set = QOPR_CLOCK_X1;
1260 }
1261 qopr &= ~QOPR_CLOCK_RATE_MASK;
1262 qopr |= set;
1263
1264out:
1265 pci_quatech_wqopr(port, qopr);
1266 return clock;
1267}
1268
1269static int pci_quatech_rs422(struct uart_8250_port *port)
1270{
1271 u8 qmcr;
1272 int rs422 = 0;
1273
1274 if (!pci_quatech_has_qmcr(port))
1275 return 0;
1276 qmcr = pci_quatech_rqmcr(port);
1277 pci_quatech_wqmcr(port, 0xFF);
1278 if (pci_quatech_rqmcr(port))
1279 rs422 = 1;
1280 pci_quatech_wqmcr(port, qmcr);
1281 return rs422;
1282}
1283
1284static int pci_quatech_init(struct pci_dev *dev)
1285{
1286 if (pci_quatech_amcc(dev->device)) {
1287 unsigned long base = pci_resource_start(dev, 0);
1288 if (base) {
1289 u32 tmp;
9c5320f8 1290 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
55c7c0fd
AC		 1291 tmp = inl(base + 0x3c);
1292 outl(tmp | 0x01000000, base + 0x3c);
9c5320f8 1293 outl(tmp &= ~0x01000000, base + 0x3c);
55c7c0fd
AC		 1294 }
1295 }
1296 return 0;
1297}
1298
1299static int pci_quatech_setup(struct serial_private *priv,
1300 const struct pciserial_board *board,
1301 struct uart_8250_port *port, int idx)
1302{
1303 /* Needed by pci_quatech calls below */
1304 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1305 /* Set up the clocking */
1306 port->port.uartclk = pci_quatech_clock(port);
1307 /* For now just warn about RS422 */
1308 if (pci_quatech_rs422(port))
1309 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1310 return pci_default_setup(priv, board, port, idx);
1311}
1312
d73dfc6a 1313static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1314{
1315}
1316
eb26dfe8 1317static int pci_default_setup(struct serial_private *priv,
975a1a7d 1318 const struct pciserial_board *board,
2655a2c7 1319 struct uart_8250_port *port, int idx)
1da177e4
LT		 1320{
1321 unsigned int bar, offset = board->first_offset, maxnr;
1322
1323 bar = FL_GET_BASE(board->flags);
1324 if (board->flags & FL_BASE_BARS)
1325 bar += idx;
1326 else
1327 offset += idx * board->uart_offset;
1328
2427ddd8
GKH		 1329 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1330 (board->reg_shift + 3);
1da177e4
LT		 1331
1332 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1333 return 1;
5756ee99 1334
70db3d91 1335 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1336}
1337
94341475
AB		 1338static int pci_pericom_setup(struct serial_private *priv,
1339 const struct pciserial_board *board,
1340 struct uart_8250_port *port, int idx)
1341{
1342 unsigned int bar, offset = board->first_offset, maxnr;
1343
1344 bar = FL_GET_BASE(board->flags);
1345 if (board->flags & FL_BASE_BARS)
1346 bar += idx;
1347 else
1348 offset += idx * board->uart_offset;
1349
1350 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1351 (board->reg_shift + 3);
1352
1353 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1354 return 1;
1355
1356 port->port.uartclk = 14745600;
1357
1358 return setup_port(priv, port, bar, offset, board->reg_shift);
1359}
1360
095e24b0
DB		 1361static int
1362ce4100_serial_setup(struct serial_private *priv,
1363 const struct pciserial_board *board,
2655a2c7 1364 struct uart_8250_port *port, int idx)
095e24b0
DB		 1365{
1366 int ret;
1367
08ec212c 1368 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1369 port->port.iotype = UPIO_MEM32;
1370 port->port.type = PORT_XSCALE;
1371 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1372 port->port.regshift = 2;
095e24b0
DB		 1373
1374 return ret;
1375}
1376
b15e5691
HK		 1377#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1378#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1379
29897087
AC		 1380#define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1381#define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1382
b15e5691
HK		 1383#define BYT_PRV_CLK 0x800
1384#define BYT_PRV_CLK_EN (1 << 0)
1385#define BYT_PRV_CLK_M_VAL_SHIFT 1
1386#define BYT_PRV_CLK_N_VAL_SHIFT 16
1387#define BYT_PRV_CLK_UPDATE (1 << 31)
1388
b15e5691
HK		 1389#define BYT_TX_OVF_INT 0x820
1390#define BYT_TX_OVF_INT_MASK (1 << 1)
1391
1392static void
1393byt_set_termios(struct uart_port *p, struct ktermios *termios,
1394 struct ktermios *old)
1395{
1396 unsigned int baud = tty_termios_baud_rate(termios);
21947ba6
AS		 1397 unsigned long fref = 100000000, fuart = baud * 16;
1398 unsigned long w = BIT(15) - 1;
1399 unsigned long m, n;
b15e5691
HK		 1400 u32 reg;
1401
21947ba6
AS		 1402 /* Get Fuart closer to Fref */
1403 fuart *= rounddown_pow_of_two(fref / fuart);
1404
50825c57
AS		 1405 /*
1406 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1407 * dividers must be adjusted.
1408 *
1409 * uartclk = (m / n) * 100 MHz, where m <= n
1410 */
21947ba6
AS		 1411 rational_best_approximation(fuart, fref, w, w, &m, &n);
1412 p->uartclk = fuart;
b15e5691
HK		 1413
1414 /* Reset the clock */
1415 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1416 writel(reg, p->membase + BYT_PRV_CLK);
1417 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1418 writel(reg, p->membase + BYT_PRV_CLK);
1419
0a6c301a
QZ		 1420 p->status &= ~UPSTAT_AUTOCTS;
1421 if (termios->c_cflag & CRTSCTS)
1422 p->status |= UPSTAT_AUTOCTS;
1423
b15e5691
HK		 1424 serial8250_do_set_termios(p, termios, old);
1425}
1426
1427static bool byt_dma_filter(struct dma_chan *chan, void *param)
1428{
9a1870ce
AS		 1429 struct dw_dma_slave *dws = param;
1430
1431 if (dws->dma_dev != chan->device->dev)
1432 return false;
1433
1434 chan->private = dws;
1435 return true;
b15e5691
HK		 1436}
1437
1438static int
1439byt_serial_setup(struct serial_private *priv,
1440 const struct pciserial_board *board,
1441 struct uart_8250_port *port, int idx)
1442{
9a1870ce
AS		 1443 struct pci_dev *pdev = priv->dev;
1444 struct device *dev = port->port.dev;
b15e5691 1445 struct uart_8250_dma *dma;
9a1870ce
AS		 1446 struct dw_dma_slave *tx_param, *rx_param;
1447 struct pci_dev *dma_dev;
b15e5691
HK		 1448 int ret;
1449
9a1870ce 1450 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
b15e5691
HK		 1451 if (!dma)
1452 return -ENOMEM;
1453
9a1870ce
AS		 1454 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1455 if (!tx_param)
1456 return -ENOMEM;
1457
1458 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1459 if (!rx_param)
1460 return -ENOMEM;
1461
1462 switch (pdev->device) {
b15e5691 1463 case PCI_DEVICE_ID_INTEL_BYT_UART1:
29897087 1464 case PCI_DEVICE_ID_INTEL_BSW_UART1:
9a1870ce
AS		 1465 rx_param->src_id = 3;
1466 tx_param->dst_id = 2;
b15e5691
HK		 1467 break;
1468 case PCI_DEVICE_ID_INTEL_BYT_UART2:
29897087 1469 case PCI_DEVICE_ID_INTEL_BSW_UART2:
9a1870ce
AS		 1470 rx_param->src_id = 5;
1471 tx_param->dst_id = 4;
b15e5691
HK		 1472 break;
1473 default:
1474 return -EINVAL;
1475 }
1476
9a1870ce
AS		 1477 rx_param->src_master = 1;
1478 rx_param->dst_master = 0;
1479
b15e5691
HK		 1480 dma->rxconf.src_maxburst = 16;
1481
9a1870ce
AS		 1482 tx_param->src_master = 1;
1483 tx_param->dst_master = 0;
1484
b15e5691
HK		 1485 dma->txconf.dst_maxburst = 16;
1486
9a1870ce
AS		 1487 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1488 rx_param->dma_dev = &dma_dev->dev;
1489 tx_param->dma_dev = &dma_dev->dev;
1490
b15e5691 1491 dma->fn = byt_dma_filter;
9a1870ce
AS		 1492 dma->rx_param = rx_param;
1493 dma->tx_param = tx_param;
b15e5691
HK		 1494
1495 ret = pci_default_setup(priv, board, port, idx);
1496 port->port.iotype = UPIO_MEM;
1497 port->port.type = PORT_16550A;
1498 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1499 port->port.set_termios = byt_set_termios;
1500 port->port.fifosize = 64;
1501 port->tx_loadsz = 64;
1502 port->dma = dma;
1503 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1504
1505 /* Disable Tx counter interrupts */
1506 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1507
1508 return ret;
1509}
1510
f549e94e
AS		 1511#define INTEL_MID_UART_PS 0x30
1512#define INTEL_MID_UART_MUL 0x34
c1a67b48 1513#define INTEL_MID_UART_DIV 0x38
f549e94e 1514
c1a67b48
AS		 1515static void intel_mid_set_termios(struct uart_port *p,
1516 struct ktermios *termios,
1517 struct ktermios *old,
1518 unsigned long fref)
f549e94e
AS		 1519{
1520 unsigned int baud = tty_termios_baud_rate(termios);
c1a67b48
AS		 1521 unsigned short ps = 16;
1522 unsigned long fuart = baud * ps;
1523 unsigned long w = BIT(24) - 1;
1524 unsigned long mul, div;
1525
1526 if (fref < fuart) {
1527 /* Find prescaler value that satisfies Fuart < Fref */
1528 if (fref > baud)
1529 ps = fref / baud; /* baud rate too high */
1530 else
1531 ps = 1; /* PLL case */
1532 fuart = baud * ps;
1533 } else {
1534 /* Get Fuart closer to Fref */
1535 fuart *= rounddown_pow_of_two(fref / fuart);
f549e94e
AS		 1536 }
1537
c1a67b48
AS		 1538 rational_best_approximation(fuart, fref, w, w, &mul, &div);
1539 p->uartclk = fuart * 16 / ps; /* core uses ps = 16 always */
1540
f549e94e
AS		 1541 writel(ps, p->membase + INTEL_MID_UART_PS); /* set PS */
1542 writel(mul, p->membase + INTEL_MID_UART_MUL); /* set MUL */
c1a67b48 1543 writel(div, p->membase + INTEL_MID_UART_DIV);
f549e94e
AS		 1544
1545 serial8250_do_set_termios(p, termios, old);
1546}
90b9aacf
AS		 1547
1548static void intel_mid_set_termios_38_4M(struct uart_port *p,
1549 struct ktermios *termios,
1550 struct ktermios *old)
1551{
1552 intel_mid_set_termios(p, termios, old, 38400000);
1553}
1554
c1a67b48
AS		 1555static void intel_mid_set_termios_50M(struct uart_port *p,
1556 struct ktermios *termios,
1557 struct ktermios *old)
1558{
1559 /*
1560 * The uart clk is 50Mhz, and the baud rate come from:
1561 * baud = 50M * MUL / (DIV * PS * DLAB)
1562 */
1563 intel_mid_set_termios(p, termios, old, 50000000);
1564}
f549e94e
AS		 1565
1566static bool intel_mid_dma_filter(struct dma_chan *chan, void *param)
1567{
1568 struct hsu_dma_slave *s = param;
1569
1570 if (s->dma_dev != chan->device->dev || s->chan_id != chan->chan_id)
1571 return false;
1572
1573 chan->private = s;
1574 return true;
1575}
1576
1577static int intel_mid_serial_setup(struct serial_private *priv,
1578 const struct pciserial_board *board,
1579 struct uart_8250_port *port, int idx,
1580 int index, struct pci_dev *dma_dev)
1581{
1582 struct device *dev = port->port.dev;
1583 struct uart_8250_dma *dma;
1584 struct hsu_dma_slave *tx_param, *rx_param;
1585
1586 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1587 if (!dma)
1588 return -ENOMEM;
1589
1590 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1591 if (!tx_param)
1592 return -ENOMEM;
1593
1594 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1595 if (!rx_param)
1596 return -ENOMEM;
1597
1598 rx_param->chan_id = index * 2 + 1;
1599 tx_param->chan_id = index * 2;
1600
1601 dma->rxconf.src_maxburst = 64;
1602 dma->txconf.dst_maxburst = 64;
1603
1604 rx_param->dma_dev = &dma_dev->dev;
1605 tx_param->dma_dev = &dma_dev->dev;
1606
1607 dma->fn = intel_mid_dma_filter;
1608 dma->rx_param = rx_param;
1609 dma->tx_param = tx_param;
1610
1611 port->port.type = PORT_16750;
1612 port->port.flags |= UPF_FIXED_PORT | UPF_FIXED_TYPE;
1613 port->dma = dma;
1614
1615 return pci_default_setup(priv, board, port, idx);
1616}
1617
1618#define PCI_DEVICE_ID_INTEL_PNW_UART1 0x081b
1619#define PCI_DEVICE_ID_INTEL_PNW_UART2 0x081c
1620#define PCI_DEVICE_ID_INTEL_PNW_UART3 0x081d
1621
1622static int pnw_serial_setup(struct serial_private *priv,
1623 const struct pciserial_board *board,
1624 struct uart_8250_port *port, int idx)
1625{
1626 struct pci_dev *pdev = priv->dev;
1627 struct pci_dev *dma_dev;
1628 int index;
1629
1630 switch (pdev->device) {
1631 case PCI_DEVICE_ID_INTEL_PNW_UART1:
1632 index = 0;
1633 break;
1634 case PCI_DEVICE_ID_INTEL_PNW_UART2:
1635 index = 1;
1636 break;
1637 case PCI_DEVICE_ID_INTEL_PNW_UART3:
1638 index = 2;
1639 break;
1640 default:
1641 return -EINVAL;
1642 }
1643
1644 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 3));
1645
1646 port->port.set_termios = intel_mid_set_termios_50M;
1647
1648 return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1649}
1650
90b9aacf
AS		 1651#define PCI_DEVICE_ID_INTEL_TNG_UART 0x1191
1652
1653static int tng_serial_setup(struct serial_private *priv,
1654 const struct pciserial_board *board,
1655 struct uart_8250_port *port, int idx)
1656{
1657 struct pci_dev *pdev = priv->dev;
1658 struct pci_dev *dma_dev;
1659 int index = PCI_FUNC(pdev->devfn);
1660
1661 /* Currently no support for HSU port0 */
1662 if (index-- == 0)
1663 return -ENODEV;
1664
1665 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
1666
1667 port->port.set_termios = intel_mid_set_termios_38_4M;
1668
1669 return intel_mid_serial_setup(priv, board, port, idx, index, dma_dev);
1670}
1671
d9a0fbfd
AP		 1672static int
1673pci_omegapci_setup(struct serial_private *priv,
1798ca13 1674 const struct pciserial_board *board,
2655a2c7 1675 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1676{
1677 return setup_port(priv, port, 2, idx * 8, 0);
1678}
1679
ebebd49a
SH		 1680static int
1681pci_brcm_trumanage_setup(struct serial_private *priv,
1682 const struct pciserial_board *board,
1683 struct uart_8250_port *port, int idx)
1684{
1685 int ret = pci_default_setup(priv, board, port, idx);
1686
1687 port->port.type = PORT_BRCM_TRUMANAGE;
1688 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1689 return ret;
1690}
1691
fecf27a3
PH		 1692/* RTS will control by MCR if this bit is 0 */
1693#define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1694/* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1695#define FINTEK_RTS_INVERT BIT(5)
1696
1697/* We should do proper H/W transceiver setting before change to RS485 mode */
1698static int pci_fintek_rs485_config(struct uart_port *port,
1699 struct serial_rs485 *rs485)
1700{
1701 u8 setting;
1702 u8 *index = (u8 *) port->private_data;
1703 struct pci_dev *pci_dev = container_of(port->dev, struct pci_dev,
1704 dev);
1705
1706 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1707
1708 if (rs485->flags & SER_RS485_ENABLED)
1709 memset(rs485->padding, 0, sizeof(rs485->padding));
1710 else
1711 memset(rs485, 0, sizeof(*rs485));
1712
1713 /* F81504/508/512 not support RTS delay before or after send */
1714 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1715
1716 if (rs485->flags & SER_RS485_ENABLED) {
1717 /* Enable RTS H/W control mode */
1718 setting |= FINTEK_RTS_CONTROL_BY_HW;
1719
1720 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1721 /* RTS driving high on TX */
1722 setting &= ~FINTEK_RTS_INVERT;
1723 } else {
1724 /* RTS driving low on TX */
1725 setting |= FINTEK_RTS_INVERT;
1726 }
1727
1728 rs485->delay_rts_after_send = 0;
1729 rs485->delay_rts_before_send = 0;
1730 } else {
1731 /* Disable RTS H/W control mode */
1732 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1733 }
1734
1735 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1736 port->rs485 = *rs485;
1737 return 0;
1738}
1739
2c62a3c8
GKH		 1740static int pci_fintek_setup(struct serial_private *priv,
1741 const struct pciserial_board *board,
1742 struct uart_8250_port *port, int idx)
1743{
1744 struct pci_dev *pdev = priv->dev;
fecf27a3 1745 u8 *data;
2c62a3c8 1746 u8 config_base;
6a8bc239
PH		 1747 u16 iobase;
1748
1749 config_base = 0x40 + 0x08 * idx;
1750
1751 /* Get the io address from configuration space */
1752 pci_read_config_word(pdev, config_base + 4, &iobase);
1753
1754 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1755
1756 port->port.iotype = UPIO_PORT;
1757 port->port.iobase = iobase;
fecf27a3
PH		 1758 port->port.rs485_config = pci_fintek_rs485_config;
1759
1760 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1761 if (!data)
1762 return -ENOMEM;
1763
1764 /* preserve index in PCI configuration space */
1765 *data = idx;
1766 port->port.private_data = data;
6a8bc239
PH		 1767
1768 return 0;
1769}
1770
1771static int pci_fintek_init(struct pci_dev *dev)
1772{
1773 unsigned long iobase;
1774 u32 max_port, i;
cb8ee9f0 1775 u32 bar_data[3];
6a8bc239 1776 u8 config_base;
2c62a3c8 1777
6a8bc239
PH		 1778 switch (dev->device) {
1779 case 0x1104: /* 4 ports */
1780 case 0x1108: /* 8 ports */
1781 max_port = dev->device & 0xff;
cb8ee9f0 1782 break;
6a8bc239
PH		 1783 case 0x1112: /* 12 ports */
1784 max_port = 12;
cb8ee9f0 1785 break;
2c62a3c8 1786 default:
2c62a3c8
GKH		 1787 return -EINVAL;
1788 }
1789
cb8ee9f0 1790 /* Get the io address dispatch from the BIOS */
6a8bc239
PH		 1791 pci_read_config_dword(dev, 0x24, &bar_data[0]);
1792 pci_read_config_dword(dev, 0x20, &bar_data[1]);
1793 pci_read_config_dword(dev, 0x1c, &bar_data[2]);
cb8ee9f0 1794
6a8bc239
PH		 1795 for (i = 0; i < max_port; ++i) {
1796 /* UART0 configuration offset start from 0x40 */
1797 config_base = 0x40 + 0x08 * i;
2c62a3c8 1798
6a8bc239
PH		 1799 /* Calculate Real IO Port */
1800 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
2c62a3c8 1801
6a8bc239
PH		 1802 /* Enable UART I/O port */
1803 pci_write_config_byte(dev, config_base + 0x00, 0x01);
2c62a3c8 1804
6a8bc239
PH		 1805 /* Select 128-byte FIFO and 8x FIFO threshold */
1806 pci_write_config_byte(dev, config_base + 0x01, 0x33);
2c62a3c8 1807
6a8bc239
PH		 1808 /* LSB UART */
1809 pci_write_config_byte(dev, config_base + 0x04,
1810 (u8)(iobase & 0xff));
2c62a3c8 1811
6a8bc239
PH		 1812 /* MSB UART */
1813 pci_write_config_byte(dev, config_base + 0x05,
1814 (u8)((iobase & 0xff00) >> 8));
2c62a3c8 1815
6a8bc239 1816 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
fecf27a3
PH		 1817
1818 /* force init to RS232 Mode */
1819 pci_write_config_byte(dev, config_base + 0x07, 0x01);
6a8bc239 1820 }
2c62a3c8 1821
6a8bc239 1822 return max_port;
2c62a3c8
GKH		 1823}
1824
b6adea33
MCC		 1825static int skip_tx_en_setup(struct serial_private *priv,
1826 const struct pciserial_board *board,
2655a2c7 1827 struct uart_8250_port *port, int idx)
b6adea33 1828{
2655a2c7 1829 port->port.flags |= UPF_NO_TXEN_TEST;
af8c5b8d
GKH		 1830 dev_dbg(&priv->dev->dev,
1831 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1832 priv->dev->vendor, priv->dev->device,
1833 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
b6adea33
MCC		 1834
1835 return pci_default_setup(priv, board, port, idx);
1836}
1837
0ad372b9
SM		 1838static void kt_handle_break(struct uart_port *p)
1839{
b1261c86 1840 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1841 /*
1842 * On receipt of a BI, serial device in Intel ME (Intel
1843 * management engine) needs to have its fifos cleared for sane
1844 * SOL (Serial Over Lan) output.
1845 */
1846 serial8250_clear_and_reinit_fifos(up);
1847}
1848
1849static unsigned int kt_serial_in(struct uart_port *p, int offset)
1850{
b1261c86 1851 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1852 unsigned int val;
1853
1854 /*
1855 * When the Intel ME (management engine) gets reset its serial
1856 * port registers could return 0 momentarily. Functions like
1857 * serial8250_console_write, read and save the IER, perform
1858 * some operation and then restore it. In order to avoid
1859 * setting IER register inadvertently to 0, if the value read
1860 * is 0, double check with ier value in uart_8250_port and use
1861 * that instead. up->ier should be the same value as what is
1862 * currently configured.
1863 */
1864 val = inb(p->iobase + offset);
1865 if (offset == UART_IER) {
1866 if (val == 0)
1867 val = up->ier;
1868 }
1869 return val;
1870}
1871
bc02d15a
DW		 1872static int kt_serial_setup(struct serial_private *priv,
1873 const struct pciserial_board *board,
2655a2c7 1874 struct uart_8250_port *port, int idx)
bc02d15a 1875{
2655a2c7
AC		 1876 port->port.flags |= UPF_BUG_THRE;
1877 port->port.serial_in = kt_serial_in;
1878 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1879 return skip_tx_en_setup(priv, board, port, idx);
1880}
1881
eb7073db
TM		 1882static int pci_eg20t_init(struct pci_dev *dev)
1883{
1884#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1885 return -ENODEV;
1886#else
1887 return 0;
1888#endif
1889}
1890
899f0c1c
SG		 1891#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1892#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1893
06315348
SH		 1894static int
1895pci_xr17c154_setup(struct serial_private *priv,
1896 const struct pciserial_board *board,
2655a2c7 1897 struct uart_8250_port *port, int idx)
06315348 1898{
2655a2c7 1899 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1900 return pci_default_setup(priv, board, port, idx);
1901}
1902
899f0c1c
SG		 1903static inline int
1904xr17v35x_has_slave(struct serial_private *priv)
1905{
1906 const int dev_id = priv->dev->device;
1907
1908 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
1909 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
1910}
1911
dc96efb7
MS		 1912static int
1913pci_xr17v35x_setup(struct serial_private *priv,
1914 const struct pciserial_board *board,
1915 struct uart_8250_port *port, int idx)
1916{
1917 u8 __iomem *p;
1918
1919 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1920 if (p == NULL)
1921 return -ENOMEM;
dc96efb7
MS		 1922
1923 port->port.flags |= UPF_EXAR_EFR;
1924
899f0c1c
SG		 1925 /*
1926 * Setup the uart clock for the devices on expansion slot to
1927 * half the clock speed of the main chip (which is 125MHz)
1928 */
1929 if (xr17v35x_has_slave(priv) && idx >= 8)
1930 port->port.uartclk = (7812500 * 16 / 2);
1931
dc96efb7
MS		 1932 /*
1933 * Setup Multipurpose Input/Output pins.
1934 */
1935 if (idx == 0) {
1936 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1937 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1938 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1939 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1940 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1941 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1942 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1943 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1944 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1945 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1946 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1947 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1948 }
f965b9c4
MS		 1949 writeb(0x00, p + UART_EXAR_8XMODE);
1950 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1951 writeb(128, p + UART_EXAR_TXTRG);
1952 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1953 iounmap(p);
1954
1955 return pci_default_setup(priv, board, port, idx);
1956}
1957
14faa8cc
MS		 1958#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1959#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1960#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1961#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1962
1963static int
1964pci_fastcom335_setup(struct serial_private *priv,
1965 const struct pciserial_board *board,
1966 struct uart_8250_port *port, int idx)
1967{
1968 u8 __iomem *p;
1969
1970 p = pci_ioremap_bar(priv->dev, 0);
1971 if (p == NULL)
1972 return -ENOMEM;
1973
1974 port->port.flags |= UPF_EXAR_EFR;
1975
1976 /*
1977 * Setup Multipurpose Input/Output pins.
1978 */
1979 if (idx == 0) {
1980 switch (priv->dev->device) {
1981 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1982 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1983 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1984 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1985 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1986 break;
1987 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1988 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1989 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1990 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1991 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1992 break;
1993 }
1994 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1995 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1996 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1997 }
1998 writeb(0x00, p + UART_EXAR_8XMODE);
1999 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
2000 writeb(32, p + UART_EXAR_TXTRG);
2001 writeb(32, p + UART_EXAR_RXTRG);
2002 iounmap(p);
2003
2004 return pci_default_setup(priv, board, port, idx);
2005}
2006
6971c635
GA		 2007static int
2008pci_wch_ch353_setup(struct serial_private *priv,
2009 const struct pciserial_board *board,
2010 struct uart_8250_port *port, int idx)
2011{
2012 port->port.flags |= UPF_FIXED_TYPE;
2013 port->port.type = PORT_16550A;
06315348
SH		 2014 return pci_default_setup(priv, board, port, idx);
2015}
2016
2fdd8c8c 2017static int
72a3c0e4 2018pci_wch_ch38x_setup(struct serial_private *priv,
2fdd8c8c
SP		 2019 const struct pciserial_board *board,
2020 struct uart_8250_port *port, int idx)
2021{
2022 port->port.flags |= UPF_FIXED_TYPE;
2023 port->port.type = PORT_16850;
2024 return pci_default_setup(priv, board, port, idx);
2025}
2026
1da177e4
LT		 2027#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
2028#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
2029#define PCI_DEVICE_ID_OCTPRO 0x0001
2030#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
2031#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
2032#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
2033#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 2034#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
2035#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 2036#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 2037#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 2038#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
0c6d774c
TW		 2039#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
2040#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
66169ad1
YY		 2041#define PCI_DEVICE_ID_TITAN_200I 0x8028
2042#define PCI_DEVICE_ID_TITAN_400I 0x8048
2043#define PCI_DEVICE_ID_TITAN_800I 0x8088
2044#define PCI_DEVICE_ID_TITAN_800EH 0xA007
2045#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
2046#define PCI_DEVICE_ID_TITAN_400EH 0xA009
2047#define PCI_DEVICE_ID_TITAN_100E 0xA010
2048#define PCI_DEVICE_ID_TITAN_200E 0xA012
2049#define PCI_DEVICE_ID_TITAN_400E 0xA013
2050#define PCI_DEVICE_ID_TITAN_800E 0xA014
2051#define PCI_DEVICE_ID_TITAN_200EI 0xA016
2052#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
48c0247d 2053#define PCI_DEVICE_ID_TITAN_200V3 0xA306
1e9deb11
YY		 2054#define PCI_DEVICE_ID_TITAN_400V3 0xA310
2055#define PCI_DEVICE_ID_TITAN_410V3 0xA312
2056#define PCI_DEVICE_ID_TITAN_800V3 0xA314
2057#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 2058#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 2059#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 2060#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 2061#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 2062#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 2063#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 2064#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
2065#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
feb58142 2066#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
27788c5f 2067#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 2068#define PCI_VENDOR_ID_AGESTAR 0x5372
2069#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 2070#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 2071#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
2072#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 2073#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 2074#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
57c1f0e9 2075#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1ede7dcc 2076#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
14faa8cc 2077
abd7baca
SC		 2078#define PCI_VENDOR_ID_SUNIX 0x1fd4
2079#define PCI_DEVICE_ID_SUNIX_1999 0x1999
2080
2fdd8c8c
SP		 2081#define PCIE_VENDOR_ID_WCH 0x1c00
2082#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
72a3c0e4 2083#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1da177e4 2084
89c043a6
AL		 2085#define PCI_VENDOR_ID_PERICOM 0x12D8
2086#define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
2087#define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
2088#define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
2089#define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
2090
b76c5a07
CB		 2091/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
2092#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 2093#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 2094
1da177e4
LT		 2095/*
2096 * Master list of serial port init/setup/exit quirks.
2097 * This does not describe the general nature of the port.
2098 * (ie, baud base, number and location of ports, etc)
2099 *
2100 * This list is ordered alphabetically by vendor then device.
2101 * Specific entries must come before more generic entries.
2102 */
7a63ce5a 2103static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 2104 /*
2105 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2106 */
2107 {
086231f7 2108 .vendor = PCI_VENDOR_ID_AMCC,
57c1f0e9 2109 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 2110 .subvendor = PCI_ANY_ID,
2111 .subdevice = PCI_ANY_ID,
2112 .setup = addidata_apci7800_setup,
2113 },
1da177e4 2114 /*
61a116ef 2115 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 2116 * It is not clear whether this applies to all products.
2117 */
2118 {
2119 .vendor = PCI_VENDOR_ID_AFAVLAB,
2120 .device = PCI_ANY_ID,
2121 .subvendor = PCI_ANY_ID,
2122 .subdevice = PCI_ANY_ID,
2123 .setup = afavlab_setup,
2124 },
2125 /*
2126 * HP Diva
2127 */
2128 {
2129 .vendor = PCI_VENDOR_ID_HP,
2130 .device = PCI_DEVICE_ID_HP_DIVA,
2131 .subvendor = PCI_ANY_ID,
2132 .subdevice = PCI_ANY_ID,
2133 .init = pci_hp_diva_init,
2134 .setup = pci_hp_diva_setup,
2135 },
2136 /*
2137 * Intel
2138 */
2139 {
2140 .vendor = PCI_VENDOR_ID_INTEL,
2141 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2142 .subvendor = 0xe4bf,
2143 .subdevice = PCI_ANY_ID,
2144 .init = pci_inteli960ni_init,
2145 .setup = pci_default_setup,
2146 },
b6adea33
MCC		 2147 {
2148 .vendor = PCI_VENDOR_ID_INTEL,
2149 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2150 .subvendor = PCI_ANY_ID,
2151 .subdevice = PCI_ANY_ID,
2152 .setup = skip_tx_en_setup,
2153 },
2154 {
2155 .vendor = PCI_VENDOR_ID_INTEL,
2156 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2157 .subvendor = PCI_ANY_ID,
2158 .subdevice = PCI_ANY_ID,
2159 .setup = skip_tx_en_setup,
2160 },
2161 {
2162 .vendor = PCI_VENDOR_ID_INTEL,
2163 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2164 .subvendor = PCI_ANY_ID,
2165 .subdevice = PCI_ANY_ID,
2166 .setup = skip_tx_en_setup,
2167 },
095e24b0
DB		 2168 {
2169 .vendor = PCI_VENDOR_ID_INTEL,
2170 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2171 .subvendor = PCI_ANY_ID,
2172 .subdevice = PCI_ANY_ID,
2173 .setup = ce4100_serial_setup,
2174 },
bc02d15a
DW		 2175 {
2176 .vendor = PCI_VENDOR_ID_INTEL,
2177 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2178 .subvendor = PCI_ANY_ID,
2179 .subdevice = PCI_ANY_ID,
2180 .setup = kt_serial_setup,
2181 },
b15e5691
HK		 2182 {
2183 .vendor = PCI_VENDOR_ID_INTEL,
2184 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
2185 .subvendor = PCI_ANY_ID,
2186 .subdevice = PCI_ANY_ID,
2187 .setup = byt_serial_setup,
2188 },
2189 {
2190 .vendor = PCI_VENDOR_ID_INTEL,
2191 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
2192 .subvendor = PCI_ANY_ID,
2193 .subdevice = PCI_ANY_ID,
2194 .setup = byt_serial_setup,
2195 },
f549e94e
AS		 2196 {
2197 .vendor = PCI_VENDOR_ID_INTEL,
2198 .device = PCI_DEVICE_ID_INTEL_PNW_UART1,
2199 .subvendor = PCI_ANY_ID,
2200 .subdevice = PCI_ANY_ID,
2201 .setup = pnw_serial_setup,
2202 },
2203 {
2204 .vendor = PCI_VENDOR_ID_INTEL,
2205 .device = PCI_DEVICE_ID_INTEL_PNW_UART2,
2206 .subvendor = PCI_ANY_ID,
2207 .subdevice = PCI_ANY_ID,
2208 .setup = pnw_serial_setup,
2209 },
2210 {
2211 .vendor = PCI_VENDOR_ID_INTEL,
2212 .device = PCI_DEVICE_ID_INTEL_PNW_UART3,
2213 .subvendor = PCI_ANY_ID,
2214 .subdevice = PCI_ANY_ID,
2215 .setup = pnw_serial_setup,
2216 },
90b9aacf
AS		 2217 {
2218 .vendor = PCI_VENDOR_ID_INTEL,
2219 .device = PCI_DEVICE_ID_INTEL_TNG_UART,
2220 .subvendor = PCI_ANY_ID,
2221 .subdevice = PCI_ANY_ID,
2222 .setup = tng_serial_setup,
2223 },
29897087
AC		 2224 {
2225 .vendor = PCI_VENDOR_ID_INTEL,
2226 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
2227 .subvendor = PCI_ANY_ID,
2228 .subdevice = PCI_ANY_ID,
2229 .setup = byt_serial_setup,
2230 },
2231 {
2232 .vendor = PCI_VENDOR_ID_INTEL,
2233 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2234 .subvendor = PCI_ANY_ID,
2235 .subdevice = PCI_ANY_ID,
2236 .setup = byt_serial_setup,
2237 },
84f8c6fc
NV		 2238 /*
2239 * ITE
2240 */
2241 {
2242 .vendor = PCI_VENDOR_ID_ITE,
2243 .device = PCI_DEVICE_ID_ITE_8872,
2244 .subvendor = PCI_ANY_ID,
2245 .subdevice = PCI_ANY_ID,
2246 .init = pci_ite887x_init,
2247 .setup = pci_default_setup,
2d47b716 2248 .exit = pci_ite887x_exit,
84f8c6fc 2249 },
46a0fac9
SB		 2250 /*
2251 * National Instruments
2252 */
04bf7e74
WP		 2253 {
2254 .vendor = PCI_VENDOR_ID_NI,
2255 .device = PCI_DEVICE_ID_NI_PCI23216,
2256 .subvendor = PCI_ANY_ID,
2257 .subdevice = PCI_ANY_ID,
2258 .init = pci_ni8420_init,
2259 .setup = pci_default_setup,
2d47b716 2260 .exit = pci_ni8420_exit,
04bf7e74
WP		 2261 },
2262 {
2263 .vendor = PCI_VENDOR_ID_NI,
2264 .device = PCI_DEVICE_ID_NI_PCI2328,
2265 .subvendor = PCI_ANY_ID,
2266 .subdevice = PCI_ANY_ID,
2267 .init = pci_ni8420_init,
2268 .setup = pci_default_setup,
2d47b716 2269 .exit = pci_ni8420_exit,
04bf7e74
WP		 2270 },
2271 {
2272 .vendor = PCI_VENDOR_ID_NI,
2273 .device = PCI_DEVICE_ID_NI_PCI2324,
2274 .subvendor = PCI_ANY_ID,
2275 .subdevice = PCI_ANY_ID,
2276 .init = pci_ni8420_init,
2277 .setup = pci_default_setup,
2d47b716 2278 .exit = pci_ni8420_exit,
04bf7e74
WP		 2279 },
2280 {
2281 .vendor = PCI_VENDOR_ID_NI,
2282 .device = PCI_DEVICE_ID_NI_PCI2322,
2283 .subvendor = PCI_ANY_ID,
2284 .subdevice = PCI_ANY_ID,
2285 .init = pci_ni8420_init,
2286 .setup = pci_default_setup,
2d47b716 2287 .exit = pci_ni8420_exit,
04bf7e74
WP		 2288 },
2289 {
2290 .vendor = PCI_VENDOR_ID_NI,
2291 .device = PCI_DEVICE_ID_NI_PCI2324I,
2292 .subvendor = PCI_ANY_ID,
2293 .subdevice = PCI_ANY_ID,
2294 .init = pci_ni8420_init,
2295 .setup = pci_default_setup,
2d47b716 2296 .exit = pci_ni8420_exit,
04bf7e74
WP		 2297 },
2298 {
2299 .vendor = PCI_VENDOR_ID_NI,
2300 .device = PCI_DEVICE_ID_NI_PCI2322I,
2301 .subvendor = PCI_ANY_ID,
2302 .subdevice = PCI_ANY_ID,
2303 .init = pci_ni8420_init,
2304 .setup = pci_default_setup,
2d47b716 2305 .exit = pci_ni8420_exit,
04bf7e74
WP		 2306 },
2307 {
2308 .vendor = PCI_VENDOR_ID_NI,
2309 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2310 .subvendor = PCI_ANY_ID,
2311 .subdevice = PCI_ANY_ID,
2312 .init = pci_ni8420_init,
2313 .setup = pci_default_setup,
2d47b716 2314 .exit = pci_ni8420_exit,
04bf7e74
WP		 2315 },
2316 {
2317 .vendor = PCI_VENDOR_ID_NI,
2318 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2319 .subvendor = PCI_ANY_ID,
2320 .subdevice = PCI_ANY_ID,
2321 .init = pci_ni8420_init,
2322 .setup = pci_default_setup,
2d47b716 2323 .exit = pci_ni8420_exit,
04bf7e74
WP		 2324 },
2325 {
2326 .vendor = PCI_VENDOR_ID_NI,
2327 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2328 .subvendor = PCI_ANY_ID,
2329 .subdevice = PCI_ANY_ID,
2330 .init = pci_ni8420_init,
2331 .setup = pci_default_setup,
2d47b716 2332 .exit = pci_ni8420_exit,
04bf7e74
WP		 2333 },
2334 {
2335 .vendor = PCI_VENDOR_ID_NI,
2336 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2337 .subvendor = PCI_ANY_ID,
2338 .subdevice = PCI_ANY_ID,
2339 .init = pci_ni8420_init,
2340 .setup = pci_default_setup,
2d47b716 2341 .exit = pci_ni8420_exit,
04bf7e74
WP		 2342 },
2343 {
2344 .vendor = PCI_VENDOR_ID_NI,
2345 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2346 .subvendor = PCI_ANY_ID,
2347 .subdevice = PCI_ANY_ID,
2348 .init = pci_ni8420_init,
2349 .setup = pci_default_setup,
2d47b716 2350 .exit = pci_ni8420_exit,
04bf7e74
WP		 2351 },
2352 {
2353 .vendor = PCI_VENDOR_ID_NI,
2354 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2355 .subvendor = PCI_ANY_ID,
2356 .subdevice = PCI_ANY_ID,
2357 .init = pci_ni8420_init,
2358 .setup = pci_default_setup,
2d47b716 2359 .exit = pci_ni8420_exit,
04bf7e74 2360 },
46a0fac9
SB		 2361 {
2362 .vendor = PCI_VENDOR_ID_NI,
2363 .device = PCI_ANY_ID,
2364 .subvendor = PCI_ANY_ID,
2365 .subdevice = PCI_ANY_ID,
2366 .init = pci_ni8430_init,
2367 .setup = pci_ni8430_setup,
2d47b716 2368 .exit = pci_ni8430_exit,
46a0fac9 2369 },
55c7c0fd
AC		 2370 /* Quatech */
2371 {
2372 .vendor = PCI_VENDOR_ID_QUATECH,
2373 .device = PCI_ANY_ID,
2374 .subvendor = PCI_ANY_ID,
2375 .subdevice = PCI_ANY_ID,
2376 .init = pci_quatech_init,
2377 .setup = pci_quatech_setup,
d73dfc6a 2378 .exit = pci_quatech_exit,
55c7c0fd 2379 },
1da177e4
LT		 2380 /*
2381 * Panacom
2382 */
2383 {
2384 .vendor = PCI_VENDOR_ID_PANACOM,
2385 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2386 .subvendor = PCI_ANY_ID,
2387 .subdevice = PCI_ANY_ID,
2388 .init = pci_plx9050_init,
2389 .setup = pci_default_setup,
2d47b716 2390 .exit = pci_plx9050_exit,
5756ee99 2391 },
1da177e4
LT		 2392 {
2393 .vendor = PCI_VENDOR_ID_PANACOM,
2394 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2395 .subvendor = PCI_ANY_ID,
2396 .subdevice = PCI_ANY_ID,
2397 .init = pci_plx9050_init,
2398 .setup = pci_default_setup,
2d47b716 2399 .exit = pci_plx9050_exit,
1da177e4 2400 },
94341475
AB		 2401 /*
2402 * Pericom
2403 */
2404 {
89c043a6
AL		 2405 .vendor = PCI_VENDOR_ID_PERICOM,
2406 .device = PCI_ANY_ID,
2407 .subvendor = PCI_ANY_ID,
2408 .subdevice = PCI_ANY_ID,
2409 .setup = pci_pericom_setup,
94341475 2410 },
1da177e4
LT		 2411 /*
2412 * PLX
2413 */
add7b58e
BH		 2414 {
2415 .vendor = PCI_VENDOR_ID_PLX,
2416 .device = PCI_DEVICE_ID_PLX_9050,
2417 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2418 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2419 .init = pci_plx9050_init,
2420 .setup = pci_default_setup,
2d47b716 2421 .exit = pci_plx9050_exit,
add7b58e 2422 },
1da177e4
LT		 2423 {
2424 .vendor = PCI_VENDOR_ID_PLX,
2425 .device = PCI_DEVICE_ID_PLX_9050,
2426 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2427 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2428 .init = pci_plx9050_init,
2429 .setup = pci_default_setup,
2d47b716 2430 .exit = pci_plx9050_exit,
1da177e4
LT		 2431 },
2432 {
2433 .vendor = PCI_VENDOR_ID_PLX,
2434 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2435 .subvendor = PCI_VENDOR_ID_PLX,
2436 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2437 .init = pci_plx9050_init,
2438 .setup = pci_default_setup,
2d47b716 2439 .exit = pci_plx9050_exit,
1da177e4
LT		 2440 },
2441 /*
2442 * SBS Technologies, Inc., PMC-OCTALPRO 232
2443 */
2444 {
2445 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2446 .device = PCI_DEVICE_ID_OCTPRO,
2447 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2448 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2449 .init = sbs_init,
2450 .setup = sbs_setup,
2d47b716 2451 .exit = sbs_exit,
1da177e4
LT		 2452 },
2453 /*
2454 * SBS Technologies, Inc., PMC-OCTALPRO 422
2455 */
2456 {
2457 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2458 .device = PCI_DEVICE_ID_OCTPRO,
2459 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2460 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2461 .init = sbs_init,
2462 .setup = sbs_setup,
2d47b716 2463 .exit = sbs_exit,
1da177e4
LT		 2464 },
2465 /*
2466 * SBS Technologies, Inc., P-Octal 232
2467 */
2468 {
2469 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2470 .device = PCI_DEVICE_ID_OCTPRO,
2471 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2472 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2473 .init = sbs_init,
2474 .setup = sbs_setup,
2d47b716 2475 .exit = sbs_exit,
1da177e4
LT		 2476 },
2477 /*
2478 * SBS Technologies, Inc., P-Octal 422
2479 */
2480 {
2481 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2482 .device = PCI_DEVICE_ID_OCTPRO,
2483 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2484 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2485 .init = sbs_init,
2486 .setup = sbs_setup,
2d47b716 2487 .exit = sbs_exit,
1da177e4 2488 },
1da177e4 2489 /*
61a116ef 2490 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 2491 */
2492 {
2493 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 2494 .device = PCI_ANY_ID,
1da177e4
LT		 2495 .subvendor = PCI_ANY_ID,
2496 .subdevice = PCI_ANY_ID,
67d74b87 2497 .init = pci_siig_init,
3ec9c594 2498 .setup = pci_siig_setup,
1da177e4
LT		 2499 },
2500 /*
2501 * Titan cards
2502 */
2503 {
2504 .vendor = PCI_VENDOR_ID_TITAN,
2505 .device = PCI_DEVICE_ID_TITAN_400L,
2506 .subvendor = PCI_ANY_ID,
2507 .subdevice = PCI_ANY_ID,
2508 .setup = titan_400l_800l_setup,
2509 },
2510 {
2511 .vendor = PCI_VENDOR_ID_TITAN,
2512 .device = PCI_DEVICE_ID_TITAN_800L,
2513 .subvendor = PCI_ANY_ID,
2514 .subdevice = PCI_ANY_ID,
2515 .setup = titan_400l_800l_setup,
2516 },
2517 /*
2518 * Timedia cards
2519 */
2520 {
2521 .vendor = PCI_VENDOR_ID_TIMEDIA,
2522 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2523 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2524 .subdevice = PCI_ANY_ID,
b9b24558 2525 .probe = pci_timedia_probe,
1da177e4
LT		 2526 .init = pci_timedia_init,
2527 .setup = pci_timedia_setup,
2528 },
2529 {
2530 .vendor = PCI_VENDOR_ID_TIMEDIA,
2531 .device = PCI_ANY_ID,
2532 .subvendor = PCI_ANY_ID,
2533 .subdevice = PCI_ANY_ID,
2534 .setup = pci_timedia_setup,
2535 },
abd7baca
SC		 2536 /*
2537 * SUNIX (Timedia) cards
2538 * Do not "probe" for these cards as there is at least one combination
2539 * card that should be handled by parport_pc that doesn't match the
2540 * rule in pci_timedia_probe.
2541 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2542 * There are some boards with part number SER5037AL that report
2543 * subdevice ID 0x0002.
2544 */
2545 {
2546 .vendor = PCI_VENDOR_ID_SUNIX,
2547 .device = PCI_DEVICE_ID_SUNIX_1999,
2548 .subvendor = PCI_VENDOR_ID_SUNIX,
2549 .subdevice = PCI_ANY_ID,
2550 .init = pci_timedia_init,
2551 .setup = pci_timedia_setup,
2552 },
06315348
SH		 2553 /*
2554 * Exar cards
2555 */
2556 {
2557 .vendor = PCI_VENDOR_ID_EXAR,
2558 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2559 .subvendor = PCI_ANY_ID,
2560 .subdevice = PCI_ANY_ID,
2561 .setup = pci_xr17c154_setup,
2562 },
2563 {
2564 .vendor = PCI_VENDOR_ID_EXAR,
2565 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2566 .subvendor = PCI_ANY_ID,
2567 .subdevice = PCI_ANY_ID,
2568 .setup = pci_xr17c154_setup,
2569 },
2570 {
2571 .vendor = PCI_VENDOR_ID_EXAR,
2572 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2573 .subvendor = PCI_ANY_ID,
2574 .subdevice = PCI_ANY_ID,
2575 .setup = pci_xr17c154_setup,
2576 },
dc96efb7
MS		 2577 {
2578 .vendor = PCI_VENDOR_ID_EXAR,
2579 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2580 .subvendor = PCI_ANY_ID,
2581 .subdevice = PCI_ANY_ID,
2582 .setup = pci_xr17v35x_setup,
2583 },
2584 {
2585 .vendor = PCI_VENDOR_ID_EXAR,
2586 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2587 .subvendor = PCI_ANY_ID,
2588 .subdevice = PCI_ANY_ID,
2589 .setup = pci_xr17v35x_setup,
2590 },
2591 {
2592 .vendor = PCI_VENDOR_ID_EXAR,
2593 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2594 .subvendor = PCI_ANY_ID,
2595 .subdevice = PCI_ANY_ID,
2596 .setup = pci_xr17v35x_setup,
2597 },
be32c0cf
SG		 2598 {
2599 .vendor = PCI_VENDOR_ID_EXAR,
2600 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2601 .subvendor = PCI_ANY_ID,
2602 .subdevice = PCI_ANY_ID,
2603 .setup = pci_xr17v35x_setup,
2604 },
96a5d18b
SG		 2605 {
2606 .vendor = PCI_VENDOR_ID_EXAR,
2607 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2608 .subvendor = PCI_ANY_ID,
2609 .subdevice = PCI_ANY_ID,
2610 .setup = pci_xr17v35x_setup,
2611 },
1da177e4
LT		 2612 /*
2613 * Xircom cards
2614 */
2615 {
2616 .vendor = PCI_VENDOR_ID_XIRCOM,
2617 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2618 .subvendor = PCI_ANY_ID,
2619 .subdevice = PCI_ANY_ID,
2620 .init = pci_xircom_init,
2621 .setup = pci_default_setup,
2622 },
2623 /*
61a116ef 2624 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2625 */
2626 {
2627 .vendor = PCI_VENDOR_ID_NETMOS,
2628 .device = PCI_ANY_ID,
2629 .subvendor = PCI_ANY_ID,
2630 .subdevice = PCI_ANY_ID,
2631 .init = pci_netmos_init,
7808edcd 2632 .setup = pci_netmos_9900_setup,
1da177e4 2633 },
1bc8cde4
MS		 2634 /*
2635 * EndRun Technologies
2636 */
2637 {
2638 .vendor = PCI_VENDOR_ID_ENDRUN,
2639 .device = PCI_ANY_ID,
2640 .subvendor = PCI_ANY_ID,
2641 .subdevice = PCI_ANY_ID,
2642 .init = pci_endrun_init,
2643 .setup = pci_default_setup,
2644 },
9f2a036a 2645 /*
aa273ae5 2646 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2647 */
2648 {
2649 .vendor = PCI_VENDOR_ID_OXSEMI,
2650 .device = PCI_ANY_ID,
2651 .subvendor = PCI_ANY_ID,
2652 .subdevice = PCI_ANY_ID,
2653 .init = pci_oxsemi_tornado_init,
2654 .setup = pci_default_setup,
2655 },
2656 {
2657 .vendor = PCI_VENDOR_ID_MAINPINE,
2658 .device = PCI_ANY_ID,
2659 .subvendor = PCI_ANY_ID,
2660 .subdevice = PCI_ANY_ID,
2661 .init = pci_oxsemi_tornado_init,
2662 .setup = pci_default_setup,
2663 },
aa273ae5
SK		 2664 {
2665 .vendor = PCI_VENDOR_ID_DIGI,
2666 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2667 .subvendor = PCI_SUBVENDOR_ID_IBM,
2668 .subdevice = PCI_ANY_ID,
2669 .init = pci_oxsemi_tornado_init,
2670 .setup = pci_default_setup,
2671 },
eb7073db
TM		 2672 {
2673 .vendor = PCI_VENDOR_ID_INTEL,
2674 .device = 0x8811,
aaa10eb1
AP		 2675 .subvendor = PCI_ANY_ID,
2676 .subdevice = PCI_ANY_ID,
eb7073db 2677 .init = pci_eg20t_init,
64d91cfa 2678 .setup = pci_default_setup,
eb7073db
TM		 2679 },
2680 {
2681 .vendor = PCI_VENDOR_ID_INTEL,
2682 .device = 0x8812,
aaa10eb1
AP		 2683 .subvendor = PCI_ANY_ID,
2684 .subdevice = PCI_ANY_ID,
eb7073db 2685 .init = pci_eg20t_init,
64d91cfa 2686 .setup = pci_default_setup,
eb7073db
TM		 2687 },
2688 {
2689 .vendor = PCI_VENDOR_ID_INTEL,
2690 .device = 0x8813,
aaa10eb1
AP		 2691 .subvendor = PCI_ANY_ID,
2692 .subdevice = PCI_ANY_ID,
eb7073db 2693 .init = pci_eg20t_init,
64d91cfa 2694 .setup = pci_default_setup,
eb7073db
TM		 2695 },
2696 {
2697 .vendor = PCI_VENDOR_ID_INTEL,
2698 .device = 0x8814,
aaa10eb1
AP		 2699 .subvendor = PCI_ANY_ID,
2700 .subdevice = PCI_ANY_ID,
eb7073db 2701 .init = pci_eg20t_init,
64d91cfa 2702 .setup = pci_default_setup,
eb7073db
TM		 2703 },
2704 {
2705 .vendor = 0x10DB,
2706 .device = 0x8027,
aaa10eb1
AP		 2707 .subvendor = PCI_ANY_ID,
2708 .subdevice = PCI_ANY_ID,
eb7073db 2709 .init = pci_eg20t_init,
64d91cfa 2710 .setup = pci_default_setup,
eb7073db
TM		 2711 },
2712 {
2713 .vendor = 0x10DB,
2714 .device = 0x8028,
aaa10eb1
AP		 2715 .subvendor = PCI_ANY_ID,
2716 .subdevice = PCI_ANY_ID,
eb7073db 2717 .init = pci_eg20t_init,
64d91cfa 2718 .setup = pci_default_setup,
eb7073db
TM		 2719 },
2720 {
2721 .vendor = 0x10DB,
2722 .device = 0x8029,
aaa10eb1
AP		 2723 .subvendor = PCI_ANY_ID,
2724 .subdevice = PCI_ANY_ID,
eb7073db 2725 .init = pci_eg20t_init,
64d91cfa 2726 .setup = pci_default_setup,
eb7073db
TM		 2727 },
2728 {
2729 .vendor = 0x10DB,
2730 .device = 0x800C,
aaa10eb1
AP		 2731 .subvendor = PCI_ANY_ID,
2732 .subdevice = PCI_ANY_ID,
eb7073db 2733 .init = pci_eg20t_init,
64d91cfa 2734 .setup = pci_default_setup,
eb7073db
TM		 2735 },
2736 {
2737 .vendor = 0x10DB,
2738 .device = 0x800D,
aaa10eb1
AP		 2739 .subvendor = PCI_ANY_ID,
2740 .subdevice = PCI_ANY_ID,
eb7073db 2741 .init = pci_eg20t_init,
64d91cfa 2742 .setup = pci_default_setup,
eb7073db 2743 },
d9a0fbfd
AP		 2744 /*
2745 * Cronyx Omega PCI (PLX-chip based)
2746 */
2747 {
2748 .vendor = PCI_VENDOR_ID_PLX,
2749 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2750 .subvendor = PCI_ANY_ID,
2751 .subdevice = PCI_ANY_ID,
2752 .setup = pci_omegapci_setup,
eb26dfe8 2753 },
feb58142
EG		 2754 /* WCH CH353 1S1P card (16550 clone) */
2755 {
2756 .vendor = PCI_VENDOR_ID_WCH,
2757 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2758 .subvendor = PCI_ANY_ID,
2759 .subdevice = PCI_ANY_ID,
2760 .setup = pci_wch_ch353_setup,
2761 },
6971c635
GA		 2762 /* WCH CH353 2S1P card (16550 clone) */
2763 {
27788c5f
AC		 2764 .vendor = PCI_VENDOR_ID_WCH,
2765 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2766 .subvendor = PCI_ANY_ID,
2767 .subdevice = PCI_ANY_ID,
2768 .setup = pci_wch_ch353_setup,
2769 },
2770 /* WCH CH353 4S card (16550 clone) */
2771 {
2772 .vendor = PCI_VENDOR_ID_WCH,
2773 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2774 .subvendor = PCI_ANY_ID,
2775 .subdevice = PCI_ANY_ID,
2776 .setup = pci_wch_ch353_setup,
2777 },
2778 /* WCH CH353 2S1PF card (16550 clone) */
2779 {
2780 .vendor = PCI_VENDOR_ID_WCH,
2781 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2782 .subvendor = PCI_ANY_ID,
2783 .subdevice = PCI_ANY_ID,
6971c635
GA		 2784 .setup = pci_wch_ch353_setup,
2785 },
8b5c913f
WY		 2786 /* WCH CH352 2S card (16550 clone) */
2787 {
2788 .vendor = PCI_VENDOR_ID_WCH,
2789 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2790 .subvendor = PCI_ANY_ID,
2791 .subdevice = PCI_ANY_ID,
2792 .setup = pci_wch_ch353_setup,
2793 },
72a3c0e4 2794 /* WCH CH382 2S1P card (16850 clone) */
2fdd8c8c
SP		 2795 {
2796 .vendor = PCIE_VENDOR_ID_WCH,
2797 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2798 .subvendor = PCI_ANY_ID,
2799 .subdevice = PCI_ANY_ID,
72a3c0e4
SP		 2800 .setup = pci_wch_ch38x_setup,
2801 },
2802 /* WCH CH384 4S card (16850 clone) */
2803 {
2804 .vendor = PCIE_VENDOR_ID_WCH,
2805 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2806 .subvendor = PCI_ANY_ID,
2807 .subdevice = PCI_ANY_ID,
2808 .setup = pci_wch_ch38x_setup,
2fdd8c8c 2809 },
eb26dfe8
AC		 2810 /*
2811 * ASIX devices with FIFO bug
2812 */
2813 {
2814 .vendor = PCI_VENDOR_ID_ASIX,
2815 .device = PCI_ANY_ID,
2816 .subvendor = PCI_ANY_ID,
2817 .subdevice = PCI_ANY_ID,
2818 .setup = pci_asix_setup,
2819 },
14faa8cc
MS		 2820 /*
2821 * Commtech, Inc. Fastcom adapters
2822 *
2823 */
2824 {
2825 .vendor = PCI_VENDOR_ID_COMMTECH,
2826 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2827 .subvendor = PCI_ANY_ID,
2828 .subdevice = PCI_ANY_ID,
2829 .setup = pci_fastcom335_setup,
2830 },
2831 {
2832 .vendor = PCI_VENDOR_ID_COMMTECH,
2833 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2834 .subvendor = PCI_ANY_ID,
2835 .subdevice = PCI_ANY_ID,
2836 .setup = pci_fastcom335_setup,
2837 },
2838 {
2839 .vendor = PCI_VENDOR_ID_COMMTECH,
2840 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2841 .subvendor = PCI_ANY_ID,
2842 .subdevice = PCI_ANY_ID,
2843 .setup = pci_fastcom335_setup,
2844 },
2845 {
2846 .vendor = PCI_VENDOR_ID_COMMTECH,
2847 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2848 .subvendor = PCI_ANY_ID,
2849 .subdevice = PCI_ANY_ID,
2850 .setup = pci_fastcom335_setup,
2851 },
2852 {
2853 .vendor = PCI_VENDOR_ID_COMMTECH,
2854 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2855 .subvendor = PCI_ANY_ID,
2856 .subdevice = PCI_ANY_ID,
2857 .setup = pci_xr17v35x_setup,
2858 },
2859 {
2860 .vendor = PCI_VENDOR_ID_COMMTECH,
2861 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2862 .subvendor = PCI_ANY_ID,
2863 .subdevice = PCI_ANY_ID,
2864 .setup = pci_xr17v35x_setup,
2865 },
2866 {
2867 .vendor = PCI_VENDOR_ID_COMMTECH,
2868 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2869 .subvendor = PCI_ANY_ID,
2870 .subdevice = PCI_ANY_ID,
2871 .setup = pci_xr17v35x_setup,
2872 },
ebebd49a
SH		 2873 /*
2874 * Broadcom TruManage (NetXtreme)
2875 */
2876 {
2877 .vendor = PCI_VENDOR_ID_BROADCOM,
2878 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2879 .subvendor = PCI_ANY_ID,
2880 .subdevice = PCI_ANY_ID,
2881 .setup = pci_brcm_trumanage_setup,
2882 },
2c62a3c8
GKH		 2883 {
2884 .vendor = 0x1c29,
2885 .device = 0x1104,
2886 .subvendor = PCI_ANY_ID,
2887 .subdevice = PCI_ANY_ID,
2888 .setup = pci_fintek_setup,
6a8bc239 2889 .init = pci_fintek_init,
2c62a3c8
GKH		 2890 },
2891 {
2892 .vendor = 0x1c29,
2893 .device = 0x1108,
2894 .subvendor = PCI_ANY_ID,
2895 .subdevice = PCI_ANY_ID,
2896 .setup = pci_fintek_setup,
6a8bc239 2897 .init = pci_fintek_init,
2c62a3c8
GKH		 2898 },
2899 {
2900 .vendor = 0x1c29,
2901 .device = 0x1112,
2902 .subvendor = PCI_ANY_ID,
2903 .subdevice = PCI_ANY_ID,
2904 .setup = pci_fintek_setup,
6a8bc239 2905 .init = pci_fintek_init,
2c62a3c8 2906 },
ebebd49a 2907
1da177e4
LT		 2908 /*
2909 * Default "match everything" terminator entry
2910 */
2911 {
2912 .vendor = PCI_ANY_ID,
2913 .device = PCI_ANY_ID,
2914 .subvendor = PCI_ANY_ID,
2915 .subdevice = PCI_ANY_ID,
2916 .setup = pci_default_setup,
2917 }
2918};
2919
2920static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2921{
2922 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2923}
2924
2925static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2926{
2927 struct pci_serial_quirk *quirk;
2928
2929 for (quirk = pci_serial_quirks; ; quirk++)
2930 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2931 quirk_id_matches(quirk->device, dev->device) &&
2932 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2933 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2934 break;
1da177e4
LT		 2935 return quirk;
2936}
2937
dd68e88c 2938static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2939 const struct pciserial_board *board)
1da177e4
LT		 2940{
2941 if (board->flags & FL_NOIRQ)
2942 return 0;
2943 else
2944 return dev->irq;
2945}
2946
2947/*
2948 * This is the configuration table for all of the PCI serial boards
2949 * which we support. It is directly indexed by the pci_board_num_t enum
2950 * value, which is encoded in the pci_device_id PCI probe table's
2951 * driver_data member.
2952 *
2953 * The makeup of these names are:
26e92861 2954 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2955 *
26e92861
GH		 2956 * bn = PCI BAR number
2957 * bt = Index using PCI BARs
2958 * n = number of serial ports
2959 * baud = baud rate
2960 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2961 *
26e92861 2962 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2963 *
1da177e4
LT		 2964 * Please note: in theory if n = 1, _bt infix should make no difference.
2965 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2966 */
2967enum pci_board_num_t {
2968 pbn_default = 0,
2969
2970 pbn_b0_1_115200,
2971 pbn_b0_2_115200,
2972 pbn_b0_4_115200,
2973 pbn_b0_5_115200,
bf0df636 2974 pbn_b0_8_115200,
1da177e4
LT		 2975
2976 pbn_b0_1_921600,
2977 pbn_b0_2_921600,
2978 pbn_b0_4_921600,
2979
db1de159
DR		 2980 pbn_b0_2_1130000,
2981
fbc0dc0d
AP		 2982 pbn_b0_4_1152000,
2983
14faa8cc
MS		 2984 pbn_b0_2_1152000_200,
2985 pbn_b0_4_1152000_200,
2986 pbn_b0_8_1152000_200,
2987
26e92861
GH		 2988 pbn_b0_2_1843200,
2989 pbn_b0_4_1843200,
2990
2991 pbn_b0_2_1843200_200,
2992 pbn_b0_4_1843200_200,
2993 pbn_b0_8_1843200_200,
2994
7106b4e3
LH		 2995 pbn_b0_1_4000000,
2996
1da177e4
LT		 2997 pbn_b0_bt_1_115200,
2998 pbn_b0_bt_2_115200,
ac6ec5b1 2999 pbn_b0_bt_4_115200,
1da177e4
LT		 3000 pbn_b0_bt_8_115200,
3001
3002 pbn_b0_bt_1_460800,
3003 pbn_b0_bt_2_460800,
3004 pbn_b0_bt_4_460800,
3005
3006 pbn_b0_bt_1_921600,
3007 pbn_b0_bt_2_921600,
3008 pbn_b0_bt_4_921600,
3009 pbn_b0_bt_8_921600,
3010
3011 pbn_b1_1_115200,
3012 pbn_b1_2_115200,
3013 pbn_b1_4_115200,
3014 pbn_b1_8_115200,
04bf7e74 3015 pbn_b1_16_115200,
1da177e4
LT		 3016
3017 pbn_b1_1_921600,
3018 pbn_b1_2_921600,
3019 pbn_b1_4_921600,
3020 pbn_b1_8_921600,
3021
26e92861
GH		 3022 pbn_b1_2_1250000,
3023
84f8c6fc 3024 pbn_b1_bt_1_115200,
04bf7e74
WP		 3025 pbn_b1_bt_2_115200,
3026 pbn_b1_bt_4_115200,
3027
1da177e4
LT		 3028 pbn_b1_bt_2_921600,
3029
3030 pbn_b1_1_1382400,
3031 pbn_b1_2_1382400,
3032 pbn_b1_4_1382400,
3033 pbn_b1_8_1382400,
3034
3035 pbn_b2_1_115200,
737c1756 3036 pbn_b2_2_115200,
a9cccd34 3037 pbn_b2_4_115200,
1da177e4
LT		 3038 pbn_b2_8_115200,
3039
3040 pbn_b2_1_460800,
3041 pbn_b2_4_460800,
3042 pbn_b2_8_460800,
3043 pbn_b2_16_460800,
3044
3045 pbn_b2_1_921600,
3046 pbn_b2_4_921600,
3047 pbn_b2_8_921600,
3048
e847003f
LB		 3049 pbn_b2_8_1152000,
3050
1da177e4
LT		 3051 pbn_b2_bt_1_115200,
3052 pbn_b2_bt_2_115200,
3053 pbn_b2_bt_4_115200,
3054
3055 pbn_b2_bt_2_921600,
3056 pbn_b2_bt_4_921600,
3057
d9004eb4 3058 pbn_b3_2_115200,
1da177e4
LT		 3059 pbn_b3_4_115200,
3060 pbn_b3_8_115200,
3061
66169ad1
YY		 3062 pbn_b4_bt_2_921600,
3063 pbn_b4_bt_4_921600,
3064 pbn_b4_bt_8_921600,
3065
1da177e4
LT		 3066 /*
3067 * Board-specific versions.
3068 */
3069 pbn_panacom,
3070 pbn_panacom2,
3071 pbn_panacom4,
3072 pbn_plx_romulus,
1bc8cde4 3073 pbn_endrun_2_4000000,
1da177e4 3074 pbn_oxsemi,
7106b4e3
LH		 3075 pbn_oxsemi_1_4000000,
3076 pbn_oxsemi_2_4000000,
3077 pbn_oxsemi_4_4000000,
3078 pbn_oxsemi_8_4000000,
1da177e4
LT		 3079 pbn_intel_i960,
3080 pbn_sgi_ioc3,
1da177e4
LT		 3081 pbn_computone_4,
3082 pbn_computone_6,
3083 pbn_computone_8,
3084 pbn_sbsxrsio,
3085 pbn_exar_XR17C152,
3086 pbn_exar_XR17C154,
3087 pbn_exar_XR17C158,
dc96efb7
MS		 3088 pbn_exar_XR17V352,
3089 pbn_exar_XR17V354,
3090 pbn_exar_XR17V358,
be32c0cf 3091 pbn_exar_XR17V4358,
96a5d18b 3092 pbn_exar_XR17V8358,
c68d2b15 3093 pbn_exar_ibm_saturn,
aa798505 3094 pbn_pasemi_1682M,
46a0fac9
SB		 3095 pbn_ni8430_2,
3096 pbn_ni8430_4,
3097 pbn_ni8430_8,
3098 pbn_ni8430_16,
1b62cbf2
KJ		 3099 pbn_ADDIDATA_PCIe_1_3906250,
3100 pbn_ADDIDATA_PCIe_2_3906250,
3101 pbn_ADDIDATA_PCIe_4_3906250,
3102 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 3103 pbn_ce4100_1_115200,
b15e5691 3104 pbn_byt,
f549e94e 3105 pbn_pnw,
90b9aacf 3106 pbn_tng,
1ede7dcc 3107 pbn_qrk,
d9a0fbfd 3108 pbn_omegapci,
7808edcd 3109 pbn_NETMOS9900_2s_115200,
ebebd49a 3110 pbn_brcm_trumanage,
2c62a3c8
GKH		 3111 pbn_fintek_4,
3112 pbn_fintek_8,
3113 pbn_fintek_12,
72a3c0e4 3114 pbn_wch384_4,
89c043a6
AL		 3115 pbn_pericom_PI7C9X7951,
3116 pbn_pericom_PI7C9X7952,
3117 pbn_pericom_PI7C9X7954,
3118 pbn_pericom_PI7C9X7958,
1da177e4
LT		 3119};
3120
3121/*
3122 * uart_offset - the space between channels
3123 * reg_shift - describes how the UART registers are mapped
3124 * to PCI memory by the card.
3125 * For example IER register on SBS, Inc. PMC-OctPro is located at
3126 * offset 0x10 from the UART base, while UART_IER is defined as 1
3127 * in include/linux/serial_reg.h,
3128 * see first lines of serial_in() and serial_out() in 8250.c
3129*/
3130
de88b340 3131static struct pciserial_board pci_boards[] = {
1da177e4
LT		 3132 [pbn_default] = {
3133 .flags = FL_BASE0,
3134 .num_ports = 1,
3135 .base_baud = 115200,
3136 .uart_offset = 8,
3137 },
3138 [pbn_b0_1_115200] = {
3139 .flags = FL_BASE0,
3140 .num_ports = 1,
3141 .base_baud = 115200,
3142 .uart_offset = 8,
3143 },
3144 [pbn_b0_2_115200] = {
3145 .flags = FL_BASE0,
3146 .num_ports = 2,
3147 .base_baud = 115200,
3148 .uart_offset = 8,
3149 },
3150 [pbn_b0_4_115200] = {
3151 .flags = FL_BASE0,
3152 .num_ports = 4,
3153 .base_baud = 115200,
3154 .uart_offset = 8,
3155 },
3156 [pbn_b0_5_115200] = {
3157 .flags = FL_BASE0,
3158 .num_ports = 5,
3159 .base_baud = 115200,
3160 .uart_offset = 8,
3161 },
bf0df636
AC		 3162 [pbn_b0_8_115200] = {
3163 .flags = FL_BASE0,
3164 .num_ports = 8,
3165 .base_baud = 115200,
3166 .uart_offset = 8,
3167 },
1da177e4
LT		 3168 [pbn_b0_1_921600] = {
3169 .flags = FL_BASE0,
3170 .num_ports = 1,
3171 .base_baud = 921600,
3172 .uart_offset = 8,
3173 },
3174 [pbn_b0_2_921600] = {
3175 .flags = FL_BASE0,
3176 .num_ports = 2,
3177 .base_baud = 921600,
3178 .uart_offset = 8,
3179 },
3180 [pbn_b0_4_921600] = {
3181 .flags = FL_BASE0,
3182 .num_ports = 4,
3183 .base_baud = 921600,
3184 .uart_offset = 8,
3185 },
db1de159
DR		 3186
3187 [pbn_b0_2_1130000] = {
3188 .flags = FL_BASE0,
3189 .num_ports = 2,
3190 .base_baud = 1130000,
3191 .uart_offset = 8,
3192 },
3193
fbc0dc0d
AP		 3194 [pbn_b0_4_1152000] = {
3195 .flags = FL_BASE0,
3196 .num_ports = 4,
3197 .base_baud = 1152000,
3198 .uart_offset = 8,
3199 },
1da177e4 3200
14faa8cc
MS		 3201 [pbn_b0_2_1152000_200] = {
3202 .flags = FL_BASE0,
3203 .num_ports = 2,
3204 .base_baud = 1152000,
3205 .uart_offset = 0x200,
3206 },
3207
3208 [pbn_b0_4_1152000_200] = {
3209 .flags = FL_BASE0,
3210 .num_ports = 4,
3211 .base_baud = 1152000,
3212 .uart_offset = 0x200,
3213 },
3214
3215 [pbn_b0_8_1152000_200] = {
3216 .flags = FL_BASE0,
4f7d67d0 3217 .num_ports = 8,
14faa8cc
MS		 3218 .base_baud = 1152000,
3219 .uart_offset = 0x200,
3220 },
3221
26e92861
GH		 3222 [pbn_b0_2_1843200] = {
3223 .flags = FL_BASE0,
3224 .num_ports = 2,
3225 .base_baud = 1843200,
3226 .uart_offset = 8,
3227 },
3228 [pbn_b0_4_1843200] = {
3229 .flags = FL_BASE0,
3230 .num_ports = 4,
3231 .base_baud = 1843200,
3232 .uart_offset = 8,
3233 },
3234
3235 [pbn_b0_2_1843200_200] = {
3236 .flags = FL_BASE0,
3237 .num_ports = 2,
3238 .base_baud = 1843200,
3239 .uart_offset = 0x200,
3240 },
3241 [pbn_b0_4_1843200_200] = {
3242 .flags = FL_BASE0,
3243 .num_ports = 4,
3244 .base_baud = 1843200,
3245 .uart_offset = 0x200,
3246 },
3247 [pbn_b0_8_1843200_200] = {
3248 .flags = FL_BASE0,
3249 .num_ports = 8,
3250 .base_baud = 1843200,
3251 .uart_offset = 0x200,
3252 },
7106b4e3
LH		 3253 [pbn_b0_1_4000000] = {
3254 .flags = FL_BASE0,
3255 .num_ports = 1,
3256 .base_baud = 4000000,
3257 .uart_offset = 8,
3258 },
26e92861 3259
1da177e4
LT		 3260 [pbn_b0_bt_1_115200] = {
3261 .flags = FL_BASE0|FL_BASE_BARS,
3262 .num_ports = 1,
3263 .base_baud = 115200,
3264 .uart_offset = 8,
3265 },
3266 [pbn_b0_bt_2_115200] = {
3267 .flags = FL_BASE0|FL_BASE_BARS,
3268 .num_ports = 2,
3269 .base_baud = 115200,
3270 .uart_offset = 8,
3271 },
ac6ec5b1
IS		 3272 [pbn_b0_bt_4_115200] = {
3273 .flags = FL_BASE0|FL_BASE_BARS,
3274 .num_ports = 4,
3275 .base_baud = 115200,
3276 .uart_offset = 8,
3277 },
1da177e4
LT		 3278 [pbn_b0_bt_8_115200] = {
3279 .flags = FL_BASE0|FL_BASE_BARS,
3280 .num_ports = 8,
3281 .base_baud = 115200,
3282 .uart_offset = 8,
3283 },
3284
3285 [pbn_b0_bt_1_460800] = {
3286 .flags = FL_BASE0|FL_BASE_BARS,
3287 .num_ports = 1,
3288 .base_baud = 460800,
3289 .uart_offset = 8,
3290 },
3291 [pbn_b0_bt_2_460800] = {
3292 .flags = FL_BASE0|FL_BASE_BARS,
3293 .num_ports = 2,
3294 .base_baud = 460800,
3295 .uart_offset = 8,
3296 },
3297 [pbn_b0_bt_4_460800] = {
3298 .flags = FL_BASE0|FL_BASE_BARS,
3299 .num_ports = 4,
3300 .base_baud = 460800,
3301 .uart_offset = 8,
3302 },
3303
3304 [pbn_b0_bt_1_921600] = {
3305 .flags = FL_BASE0|FL_BASE_BARS,
3306 .num_ports = 1,
3307 .base_baud = 921600,
3308 .uart_offset = 8,
3309 },
3310 [pbn_b0_bt_2_921600] = {
3311 .flags = FL_BASE0|FL_BASE_BARS,
3312 .num_ports = 2,
3313 .base_baud = 921600,
3314 .uart_offset = 8,
3315 },
3316 [pbn_b0_bt_4_921600] = {
3317 .flags = FL_BASE0|FL_BASE_BARS,
3318 .num_ports = 4,
3319 .base_baud = 921600,
3320 .uart_offset = 8,
3321 },
3322 [pbn_b0_bt_8_921600] = {
3323 .flags = FL_BASE0|FL_BASE_BARS,
3324 .num_ports = 8,
3325 .base_baud = 921600,
3326 .uart_offset = 8,
3327 },
3328
3329 [pbn_b1_1_115200] = {
3330 .flags = FL_BASE1,
3331 .num_ports = 1,
3332 .base_baud = 115200,
3333 .uart_offset = 8,
3334 },
3335 [pbn_b1_2_115200] = {
3336 .flags = FL_BASE1,
3337 .num_ports = 2,
3338 .base_baud = 115200,
3339 .uart_offset = 8,
3340 },
3341 [pbn_b1_4_115200] = {
3342 .flags = FL_BASE1,
3343 .num_ports = 4,
3344 .base_baud = 115200,
3345 .uart_offset = 8,
3346 },
3347 [pbn_b1_8_115200] = {
3348 .flags = FL_BASE1,
3349 .num_ports = 8,
3350 .base_baud = 115200,
3351 .uart_offset = 8,
3352 },
04bf7e74
WP		 3353 [pbn_b1_16_115200] = {
3354 .flags = FL_BASE1,
3355 .num_ports = 16,
3356 .base_baud = 115200,
3357 .uart_offset = 8,
3358 },
1da177e4
LT		 3359
3360 [pbn_b1_1_921600] = {
3361 .flags = FL_BASE1,
3362 .num_ports = 1,
3363 .base_baud = 921600,
3364 .uart_offset = 8,
3365 },
3366 [pbn_b1_2_921600] = {
3367 .flags = FL_BASE1,
3368 .num_ports = 2,
3369 .base_baud = 921600,
3370 .uart_offset = 8,
3371 },
3372 [pbn_b1_4_921600] = {
3373 .flags = FL_BASE1,
3374 .num_ports = 4,
3375 .base_baud = 921600,
3376 .uart_offset = 8,
3377 },
3378 [pbn_b1_8_921600] = {
3379 .flags = FL_BASE1,
3380 .num_ports = 8,
3381 .base_baud = 921600,
3382 .uart_offset = 8,
3383 },
26e92861
GH		 3384 [pbn_b1_2_1250000] = {
3385 .flags = FL_BASE1,
3386 .num_ports = 2,
3387 .base_baud = 1250000,
3388 .uart_offset = 8,
3389 },
1da177e4 3390
84f8c6fc
NV		 3391 [pbn_b1_bt_1_115200] = {
3392 .flags = FL_BASE1|FL_BASE_BARS,
3393 .num_ports = 1,
3394 .base_baud = 115200,
3395 .uart_offset = 8,
3396 },
04bf7e74
WP		 3397 [pbn_b1_bt_2_115200] = {
3398 .flags = FL_BASE1|FL_BASE_BARS,
3399 .num_ports = 2,
3400 .base_baud = 115200,
3401 .uart_offset = 8,
3402 },
3403 [pbn_b1_bt_4_115200] = {
3404 .flags = FL_BASE1|FL_BASE_BARS,
3405 .num_ports = 4,
3406 .base_baud = 115200,
3407 .uart_offset = 8,
3408 },
84f8c6fc 3409
1da177e4
LT		 3410 [pbn_b1_bt_2_921600] = {
3411 .flags = FL_BASE1|FL_BASE_BARS,
3412 .num_ports = 2,
3413 .base_baud = 921600,
3414 .uart_offset = 8,
3415 },
3416
3417 [pbn_b1_1_1382400] = {
3418 .flags = FL_BASE1,
3419 .num_ports = 1,
3420 .base_baud = 1382400,
3421 .uart_offset = 8,
3422 },
3423 [pbn_b1_2_1382400] = {
3424 .flags = FL_BASE1,
3425 .num_ports = 2,
3426 .base_baud = 1382400,
3427 .uart_offset = 8,
3428 },
3429 [pbn_b1_4_1382400] = {
3430 .flags = FL_BASE1,
3431 .num_ports = 4,
3432 .base_baud = 1382400,
3433 .uart_offset = 8,
3434 },
3435 [pbn_b1_8_1382400] = {
3436 .flags = FL_BASE1,
3437 .num_ports = 8,
3438 .base_baud = 1382400,
3439 .uart_offset = 8,
3440 },
3441
3442 [pbn_b2_1_115200] = {
3443 .flags = FL_BASE2,
3444 .num_ports = 1,
3445 .base_baud = 115200,
3446 .uart_offset = 8,
3447 },
737c1756
PH		 3448 [pbn_b2_2_115200] = {
3449 .flags = FL_BASE2,
3450 .num_ports = 2,
3451 .base_baud = 115200,
3452 .uart_offset = 8,
3453 },
a9cccd34
MF		 3454 [pbn_b2_4_115200] = {
3455 .flags = FL_BASE2,
3456 .num_ports = 4,
3457 .base_baud = 115200,
3458 .uart_offset = 8,
3459 },
1da177e4
LT		 3460 [pbn_b2_8_115200] = {
3461 .flags = FL_BASE2,
3462 .num_ports = 8,
3463 .base_baud = 115200,
3464 .uart_offset = 8,
3465 },
3466
3467 [pbn_b2_1_460800] = {
3468 .flags = FL_BASE2,
3469 .num_ports = 1,
3470 .base_baud = 460800,
3471 .uart_offset = 8,
3472 },
3473 [pbn_b2_4_460800] = {
3474 .flags = FL_BASE2,
3475 .num_ports = 4,
3476 .base_baud = 460800,
3477 .uart_offset = 8,
3478 },
3479 [pbn_b2_8_460800] = {
3480 .flags = FL_BASE2,
3481 .num_ports = 8,
3482 .base_baud = 460800,
3483 .uart_offset = 8,
3484 },
3485 [pbn_b2_16_460800] = {
3486 .flags = FL_BASE2,
3487 .num_ports = 16,
3488 .base_baud = 460800,
3489 .uart_offset = 8,
3490 },
3491
3492 [pbn_b2_1_921600] = {
3493 .flags = FL_BASE2,
3494 .num_ports = 1,
3495 .base_baud = 921600,
3496 .uart_offset = 8,
3497 },
3498 [pbn_b2_4_921600] = {
3499 .flags = FL_BASE2,
3500 .num_ports = 4,
3501 .base_baud = 921600,
3502 .uart_offset = 8,
3503 },
3504 [pbn_b2_8_921600] = {
3505 .flags = FL_BASE2,
3506 .num_ports = 8,
3507 .base_baud = 921600,
3508 .uart_offset = 8,
3509 },
3510
e847003f
LB		 3511 [pbn_b2_8_1152000] = {
3512 .flags = FL_BASE2,
3513 .num_ports = 8,
3514 .base_baud = 1152000,
3515 .uart_offset = 8,
3516 },
3517
1da177e4
LT		 3518 [pbn_b2_bt_1_115200] = {
3519 .flags = FL_BASE2|FL_BASE_BARS,
3520 .num_ports = 1,
3521 .base_baud = 115200,
3522 .uart_offset = 8,
3523 },
3524 [pbn_b2_bt_2_115200] = {
3525 .flags = FL_BASE2|FL_BASE_BARS,
3526 .num_ports = 2,
3527 .base_baud = 115200,
3528 .uart_offset = 8,
3529 },
3530 [pbn_b2_bt_4_115200] = {
3531 .flags = FL_BASE2|FL_BASE_BARS,
3532 .num_ports = 4,
3533 .base_baud = 115200,
3534 .uart_offset = 8,
3535 },
3536
3537 [pbn_b2_bt_2_921600] = {
3538 .flags = FL_BASE2|FL_BASE_BARS,
3539 .num_ports = 2,
3540 .base_baud = 921600,
3541 .uart_offset = 8,
3542 },
3543 [pbn_b2_bt_4_921600] = {
3544 .flags = FL_BASE2|FL_BASE_BARS,
3545 .num_ports = 4,
3546 .base_baud = 921600,
3547 .uart_offset = 8,
3548 },
3549
d9004eb4
ABL		 3550 [pbn_b3_2_115200] = {
3551 .flags = FL_BASE3,
3552 .num_ports = 2,
3553 .base_baud = 115200,
3554 .uart_offset = 8,
3555 },
1da177e4
LT		 3556 [pbn_b3_4_115200] = {
3557 .flags = FL_BASE3,
3558 .num_ports = 4,
3559 .base_baud = 115200,
3560 .uart_offset = 8,
3561 },
3562 [pbn_b3_8_115200] = {
3563 .flags = FL_BASE3,
3564 .num_ports = 8,
3565 .base_baud = 115200,
3566 .uart_offset = 8,
3567 },
3568
66169ad1
YY		 3569 [pbn_b4_bt_2_921600] = {
3570 .flags = FL_BASE4,
3571 .num_ports = 2,
3572 .base_baud = 921600,
3573 .uart_offset = 8,
3574 },
3575 [pbn_b4_bt_4_921600] = {
3576 .flags = FL_BASE4,
3577 .num_ports = 4,
3578 .base_baud = 921600,
3579 .uart_offset = 8,
3580 },
3581 [pbn_b4_bt_8_921600] = {
3582 .flags = FL_BASE4,
3583 .num_ports = 8,
3584 .base_baud = 921600,
3585 .uart_offset = 8,
3586 },
3587
1da177e4
LT		 3588 /*
3589 * Entries following this are board-specific.
3590 */
3591
3592 /*
3593 * Panacom - IOMEM
3594 */
3595 [pbn_panacom] = {
3596 .flags = FL_BASE2,
3597 .num_ports = 2,
3598 .base_baud = 921600,
3599 .uart_offset = 0x400,
3600 .reg_shift = 7,
3601 },
3602 [pbn_panacom2] = {
3603 .flags = FL_BASE2|FL_BASE_BARS,
3604 .num_ports = 2,
3605 .base_baud = 921600,
3606 .uart_offset = 0x400,
3607 .reg_shift = 7,
3608 },
3609 [pbn_panacom4] = {
3610 .flags = FL_BASE2|FL_BASE_BARS,
3611 .num_ports = 4,
3612 .base_baud = 921600,
3613 .uart_offset = 0x400,
3614 .reg_shift = 7,
3615 },
3616
3617 /* I think this entry is broken - the first_offset looks wrong --rmk */
3618 [pbn_plx_romulus] = {
3619 .flags = FL_BASE2,
3620 .num_ports = 4,
3621 .base_baud = 921600,
3622 .uart_offset = 8 << 2,
3623 .reg_shift = 2,
3624 .first_offset = 0x03,
3625 },
3626
1bc8cde4
MS		 3627 /*
3628 * EndRun Technologies
3629 * Uses the size of PCI Base region 0 to
3630 * signal now many ports are available
3631 * 2 port 952 Uart support
3632 */
3633 [pbn_endrun_2_4000000] = {
3634 .flags = FL_BASE0,
3635 .num_ports = 2,
3636 .base_baud = 4000000,
3637 .uart_offset = 0x200,
3638 .first_offset = 0x1000,
3639 },
3640
1da177e4
LT		 3641 /*
3642 * This board uses the size of PCI Base region 0 to
3643 * signal now many ports are available
3644 */
3645 [pbn_oxsemi] = {
3646 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3647 .num_ports = 32,
3648 .base_baud = 115200,
3649 .uart_offset = 8,
3650 },
7106b4e3
LH		 3651 [pbn_oxsemi_1_4000000] = {
3652 .flags = FL_BASE0,
3653 .num_ports = 1,
3654 .base_baud = 4000000,
3655 .uart_offset = 0x200,
3656 .first_offset = 0x1000,
3657 },
3658 [pbn_oxsemi_2_4000000] = {
3659 .flags = FL_BASE0,
3660 .num_ports = 2,
3661 .base_baud = 4000000,
3662 .uart_offset = 0x200,
3663 .first_offset = 0x1000,
3664 },
3665 [pbn_oxsemi_4_4000000] = {
3666 .flags = FL_BASE0,
3667 .num_ports = 4,
3668 .base_baud = 4000000,
3669 .uart_offset = 0x200,
3670 .first_offset = 0x1000,
3671 },
3672 [pbn_oxsemi_8_4000000] = {
3673 .flags = FL_BASE0,
3674 .num_ports = 8,
3675 .base_baud = 4000000,
3676 .uart_offset = 0x200,
3677 .first_offset = 0x1000,
3678 },
3679
1da177e4
LT		 3680
3681 /*
3682 * EKF addition for i960 Boards form EKF with serial port.
3683 * Max 256 ports.
3684 */
3685 [pbn_intel_i960] = {
3686 .flags = FL_BASE0,
3687 .num_ports = 32,
3688 .base_baud = 921600,
3689 .uart_offset = 8 << 2,
3690 .reg_shift = 2,
3691 .first_offset = 0x10000,
3692 },
3693 [pbn_sgi_ioc3] = {
3694 .flags = FL_BASE0|FL_NOIRQ,
3695 .num_ports = 1,
3696 .base_baud = 458333,
3697 .uart_offset = 8,
3698 .reg_shift = 0,
3699 .first_offset = 0x20178,
3700 },
3701
1da177e4
LT		 3702 /*
3703 * Computone - uses IOMEM.
3704 */
3705 [pbn_computone_4] = {
3706 .flags = FL_BASE0,
3707 .num_ports = 4,
3708 .base_baud = 921600,
3709 .uart_offset = 0x40,
3710 .reg_shift = 2,
3711 .first_offset = 0x200,
3712 },
3713 [pbn_computone_6] = {
3714 .flags = FL_BASE0,
3715 .num_ports = 6,
3716 .base_baud = 921600,
3717 .uart_offset = 0x40,
3718 .reg_shift = 2,
3719 .first_offset = 0x200,
3720 },
3721 [pbn_computone_8] = {
3722 .flags = FL_BASE0,
3723 .num_ports = 8,
3724 .base_baud = 921600,
3725 .uart_offset = 0x40,
3726 .reg_shift = 2,
3727 .first_offset = 0x200,
3728 },
3729 [pbn_sbsxrsio] = {
3730 .flags = FL_BASE0,
3731 .num_ports = 8,
3732 .base_baud = 460800,
3733 .uart_offset = 256,
3734 .reg_shift = 4,
3735 },
3736 /*
3737 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3738 * Only basic 16550A support.
3739 * XR17C15[24] are not tested, but they should work.
3740 */
3741 [pbn_exar_XR17C152] = {
3742 .flags = FL_BASE0,
3743 .num_ports = 2,
3744 .base_baud = 921600,
3745 .uart_offset = 0x200,
3746 },
3747 [pbn_exar_XR17C154] = {
3748 .flags = FL_BASE0,
3749 .num_ports = 4,
3750 .base_baud = 921600,
3751 .uart_offset = 0x200,
3752 },
3753 [pbn_exar_XR17C158] = {
3754 .flags = FL_BASE0,
3755 .num_ports = 8,
3756 .base_baud = 921600,
3757 .uart_offset = 0x200,
3758 },
dc96efb7
MS		 3759 [pbn_exar_XR17V352] = {
3760 .flags = FL_BASE0,
3761 .num_ports = 2,
3762 .base_baud = 7812500,
3763 .uart_offset = 0x400,
3764 .reg_shift = 0,
3765 .first_offset = 0,
3766 },
3767 [pbn_exar_XR17V354] = {
3768 .flags = FL_BASE0,
3769 .num_ports = 4,
3770 .base_baud = 7812500,
3771 .uart_offset = 0x400,
3772 .reg_shift = 0,
3773 .first_offset = 0,
3774 },
3775 [pbn_exar_XR17V358] = {
3776 .flags = FL_BASE0,
3777 .num_ports = 8,
3778 .base_baud = 7812500,
3779 .uart_offset = 0x400,
3780 .reg_shift = 0,
3781 .first_offset = 0,
3782 },
be32c0cf
SG		 3783 [pbn_exar_XR17V4358] = {
3784 .flags = FL_BASE0,
3785 .num_ports = 12,
3786 .base_baud = 7812500,
3787 .uart_offset = 0x400,
3788 .reg_shift = 0,
3789 .first_offset = 0,
3790 },
96a5d18b
SG		 3791 [pbn_exar_XR17V8358] = {
3792 .flags = FL_BASE0,
3793 .num_ports = 16,
3794 .base_baud = 7812500,
3795 .uart_offset = 0x400,
3796 .reg_shift = 0,
3797 .first_offset = 0,
3798 },
c68d2b15
BH		 3799 [pbn_exar_ibm_saturn] = {
3800 .flags = FL_BASE0,
3801 .num_ports = 1,
3802 .base_baud = 921600,
3803 .uart_offset = 0x200,
3804 },
3805
aa798505
OJ		 3806 /*
3807 * PA Semi PWRficient PA6T-1682M on-chip UART
3808 */
3809 [pbn_pasemi_1682M] = {
3810 .flags = FL_BASE0,
3811 .num_ports = 1,
3812 .base_baud = 8333333,
3813 },
46a0fac9
SB		 3814 /*
3815 * National Instruments 843x
3816 */
3817 [pbn_ni8430_16] = {
3818 .flags = FL_BASE0,
3819 .num_ports = 16,
3820 .base_baud = 3686400,
3821 .uart_offset = 0x10,
3822 .first_offset = 0x800,
3823 },
3824 [pbn_ni8430_8] = {
3825 .flags = FL_BASE0,
3826 .num_ports = 8,
3827 .base_baud = 3686400,
3828 .uart_offset = 0x10,
3829 .first_offset = 0x800,
3830 },
3831 [pbn_ni8430_4] = {
3832 .flags = FL_BASE0,
3833 .num_ports = 4,
3834 .base_baud = 3686400,
3835 .uart_offset = 0x10,
3836 .first_offset = 0x800,
3837 },
3838 [pbn_ni8430_2] = {
3839 .flags = FL_BASE0,
3840 .num_ports = 2,
3841 .base_baud = 3686400,
3842 .uart_offset = 0x10,
3843 .first_offset = 0x800,
3844 },
1b62cbf2
KJ		 3845 /*
3846 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3847 */
3848 [pbn_ADDIDATA_PCIe_1_3906250] = {
3849 .flags = FL_BASE0,
3850 .num_ports = 1,
3851 .base_baud = 3906250,
3852 .uart_offset = 0x200,
3853 .first_offset = 0x1000,
3854 },
3855 [pbn_ADDIDATA_PCIe_2_3906250] = {
3856 .flags = FL_BASE0,
3857 .num_ports = 2,
3858 .base_baud = 3906250,
3859 .uart_offset = 0x200,
3860 .first_offset = 0x1000,
3861 },
3862 [pbn_ADDIDATA_PCIe_4_3906250] = {
3863 .flags = FL_BASE0,
3864 .num_ports = 4,
3865 .base_baud = 3906250,
3866 .uart_offset = 0x200,
3867 .first_offset = 0x1000,
3868 },
3869 [pbn_ADDIDATA_PCIe_8_3906250] = {
3870 .flags = FL_BASE0,
3871 .num_ports = 8,
3872 .base_baud = 3906250,
3873 .uart_offset = 0x200,
3874 .first_offset = 0x1000,
3875 },
095e24b0 3876 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3877 .flags = FL_BASE_BARS,
3878 .num_ports = 2,
095e24b0
DB		 3879 .base_baud = 921600,
3880 .reg_shift = 2,
3881 },
41d3f099
AS		 3882 /*
3883 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3884 * but is overridden by byt_set_termios.
3885 */
b15e5691
HK		 3886 [pbn_byt] = {
3887 .flags = FL_BASE0,
3888 .num_ports = 1,
3889 .base_baud = 2764800,
3890 .uart_offset = 0x80,
3891 .reg_shift = 2,
3892 },
f549e94e
AS		 3893 [pbn_pnw] = {
3894 .flags = FL_BASE0,
3895 .num_ports = 1,
3896 .base_baud = 115200,
3897 },
90b9aacf
AS		 3898 [pbn_tng] = {
3899 .flags = FL_BASE0,
3900 .num_ports = 1,
3901 .base_baud = 1843200,
3902 },
1ede7dcc
BD		 3903 [pbn_qrk] = {
3904 .flags = FL_BASE0,
3905 .num_ports = 1,
3906 .base_baud = 2764800,
3907 .reg_shift = 2,
3908 },
d9a0fbfd
AP		 3909 [pbn_omegapci] = {
3910 .flags = FL_BASE0,
3911 .num_ports = 8,
3912 .base_baud = 115200,
3913 .uart_offset = 0x200,
3914 },
7808edcd
NG		 3915 [pbn_NETMOS9900_2s_115200] = {
3916 .flags = FL_BASE0,
3917 .num_ports = 2,
3918 .base_baud = 115200,
3919 },
ebebd49a
SH		 3920 [pbn_brcm_trumanage] = {
3921 .flags = FL_BASE0,
3922 .num_ports = 1,
3923 .reg_shift = 2,
3924 .base_baud = 115200,
3925 },
2c62a3c8
GKH		 3926 [pbn_fintek_4] = {
3927 .num_ports = 4,
3928 .uart_offset = 8,
3929 .base_baud = 115200,
3930 .first_offset = 0x40,
3931 },
3932 [pbn_fintek_8] = {
3933 .num_ports = 8,
3934 .uart_offset = 8,
3935 .base_baud = 115200,
3936 .first_offset = 0x40,
3937 },
3938 [pbn_fintek_12] = {
3939 .num_ports = 12,
3940 .uart_offset = 8,
3941 .base_baud = 115200,
3942 .first_offset = 0x40,
3943 },
72a3c0e4
SP		 3944 [pbn_wch384_4] = {
3945 .flags = FL_BASE0,
3946 .num_ports = 4,
3947 .base_baud = 115200,
3948 .uart_offset = 8,
3949 .first_offset = 0xC0,
3950 },
89c043a6
AL		 3951 /*
3952 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3953 */
3954 [pbn_pericom_PI7C9X7951] = {
3955 .flags = FL_BASE0,
3956 .num_ports = 1,
3957 .base_baud = 921600,
3958 .uart_offset = 0x8,
3959 },
3960 [pbn_pericom_PI7C9X7952] = {
3961 .flags = FL_BASE0,
3962 .num_ports = 2,
3963 .base_baud = 921600,
3964 .uart_offset = 0x8,
3965 },
3966 [pbn_pericom_PI7C9X7954] = {
3967 .flags = FL_BASE0,
3968 .num_ports = 4,
3969 .base_baud = 921600,
3970 .uart_offset = 0x8,
3971 },
3972 [pbn_pericom_PI7C9X7958] = {
3973 .flags = FL_BASE0,
3974 .num_ports = 8,
3975 .base_baud = 921600,
3976 .uart_offset = 0x8,
3977 },
1da177e4
LT		 3978};
3979
6971c635
GA		 3980static const struct pci_device_id blacklist[] = {
3981 /* softmodems */
5756ee99 3982 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3983 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3984 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3985
3986 /* multi-io cards handled by parport_serial */
3987 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
feb58142 3988 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
2fdd8c8c 3989 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
72a3c0e4 3990 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
436bbd43
CS		 3991};
3992
1da177e4
LT		 3993/*
3994 * Given a complete unknown PCI device, try to use some heuristics to
3995 * guess what the configuration might be, based on the pitiful PCI
3996 * serial specs. Returns 0 on success, 1 on failure.
3997 */
9671f099 3998static int
1c7c1fe5 3999serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 4000{
6971c635 4001 const struct pci_device_id *bldev;
1da177e4 4002 int num_iomem, num_port, first_port = -1, i;
5756ee99 4003
1da177e4
LT		 4004 /*
4005 * If it is not a communications device or the programming
4006 * interface is greater than 6, give up.
4007 *
4008 * (Should we try to make guesses for multiport serial devices
5756ee99 4009 * later?)
1da177e4
LT		 4010 */
4011 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
4012 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
4013 (dev->class & 0xff) > 6)
4014 return -ENODEV;
4015
436bbd43
CS		 4016 /*
4017 * Do not access blacklisted devices that are known not to
6971c635 4018 * feature serial ports or are handled by other modules.
436bbd43 4019 */
6971c635
GA		 4020 for (bldev = blacklist;
4021 bldev < blacklist + ARRAY_SIZE(blacklist);
4022 bldev++) {
4023 if (dev->vendor == bldev->vendor &&
4024 dev->device == bldev->device)
436bbd43
CS		 4025 return -ENODEV;
4026 }
4027
1da177e4
LT		 4028 num_iomem = num_port = 0;
4029 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4030 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4031 num_port++;
4032 if (first_port == -1)
4033 first_port = i;
4034 }
4035 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4036 num_iomem++;
4037 }
4038
4039 /*
4040 * If there is 1 or 0 iomem regions, and exactly one port,
4041 * use it. We guess the number of ports based on the IO
4042 * region size.
4043 */
4044 if (num_iomem <= 1 && num_port == 1) {
4045 board->flags = first_port;
4046 board->num_ports = pci_resource_len(dev, first_port) / 8;
4047 return 0;
4048 }
4049
4050 /*
4051 * Now guess if we've got a board which indexes by BARs.
4052 * Each IO BAR should be 8 bytes, and they should follow
4053 * consecutively.
4054 */
4055 first_port = -1;
4056 num_port = 0;
4057 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4058 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4059 pci_resource_len(dev, i) == 8 &&
4060 (first_port == -1 || (first_port + num_port) == i)) {
4061 num_port++;
4062 if (first_port == -1)
4063 first_port = i;
4064 }
4065 }
4066
4067 if (num_port > 1) {
4068 board->flags = first_port | FL_BASE_BARS;
4069 board->num_ports = num_port;
4070 return 0;
4071 }
4072
4073 return -ENODEV;
4074}
4075
4076static inline int
975a1a7d
RK		 4077serial_pci_matches(const struct pciserial_board *board,
4078 const struct pciserial_board *guessed)
1da177e4
LT		 4079{
4080 return
4081 board->num_ports == guessed->num_ports &&
4082 board->base_baud == guessed->base_baud &&
4083 board->uart_offset == guessed->uart_offset &&
4084 board->reg_shift == guessed->reg_shift &&
4085 board->first_offset == guessed->first_offset;
4086}
4087
241fc436 4088struct serial_private *
975a1a7d 4089pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 4090{
2655a2c7 4091 struct uart_8250_port uart;
1da177e4 4092 struct serial_private *priv;
1da177e4
LT		 4093 struct pci_serial_quirk *quirk;
4094 int rc, nr_ports, i;
4095
1da177e4
LT		 4096 nr_ports = board->num_ports;
4097
4098 /*
4099 * Find an init and setup quirks.
4100 */
4101 quirk = find_quirk(dev);
4102
4103 /*
4104 * Run the new-style initialization function.
4105 * The initialization function returns:
4106 * <0 - error
4107 * 0 - use board->num_ports
4108 * >0 - number of ports
4109 */
4110 if (quirk->init) {
4111 rc = quirk->init(dev);
241fc436
RK		 4112 if (rc < 0) {
4113 priv = ERR_PTR(rc);
4114 goto err_out;
4115 }
1da177e4
LT		 4116 if (rc)
4117 nr_ports = rc;
4118 }
4119
8f31bb39 4120 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 4121 sizeof(unsigned int) * nr_ports,
4122 GFP_KERNEL);
4123 if (!priv) {
241fc436
RK		 4124 priv = ERR_PTR(-ENOMEM);
4125 goto err_deinit;
1da177e4
LT		 4126 }
4127
70db3d91 4128 priv->dev = dev;
1da177e4 4129 priv->quirk = quirk;
1da177e4 4130
2655a2c7
AC		 4131 memset(&uart, 0, sizeof(uart));
4132 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4133 uart.port.uartclk = board->base_baud * 16;
4134 uart.port.irq = get_pci_irq(dev, board);
4135 uart.port.dev = &dev->dev;
72ce9a83 4136
1da177e4 4137 for (i = 0; i < nr_ports; i++) {
2655a2c7 4138 if (quirk->setup(priv, board, &uart, i))
1da177e4 4139 break;
72ce9a83 4140
af8c5b8d
GKH		 4141 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4142 uart.port.iobase, uart.port.irq, uart.port.iotype);
5756ee99 4143
2655a2c7 4144 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4 4145 if (priv->line[i] < 0) {
af8c5b8d
GKH		 4146 dev_err(&dev->dev,
4147 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4148 uart.port.iobase, uart.port.irq,
4149 uart.port.iotype, priv->line[i]);
1da177e4
LT		 4150 break;
4151 }
4152 }
1da177e4 4153 priv->nr = i;
241fc436 4154 return priv;
1da177e4 4155
5756ee99 4156err_deinit:
1da177e4
LT		 4157 if (quirk->exit)
4158 quirk->exit(dev);
5756ee99 4159err_out:
241fc436 4160 return priv;
1da177e4 4161}
241fc436 4162EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 4163
241fc436 4164void pciserial_remove_ports(struct serial_private *priv)
1da177e4 4165{
056a8763
RK		 4166 struct pci_serial_quirk *quirk;
4167 int i;
1da177e4 4168
056a8763
RK		 4169 for (i = 0; i < priv->nr; i++)
4170 serial8250_unregister_port(priv->line[i]);
1da177e4 4171
056a8763
RK		 4172 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4173 if (priv->remapped_bar[i])
4174 iounmap(priv->remapped_bar[i]);
4175 priv->remapped_bar[i] = NULL;
4176 }
1da177e4 4177
056a8763
RK		 4178 /*
4179 * Find the exit quirks.
4180 */
241fc436 4181 quirk = find_quirk(priv->dev);
056a8763 4182 if (quirk->exit)
241fc436
RK		 4183 quirk->exit(priv->dev);
4184
4185 kfree(priv);
4186}
4187EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4188
4189void pciserial_suspend_ports(struct serial_private *priv)
4190{
4191 int i;
4192
4193 for (i = 0; i < priv->nr; i++)
4194 if (priv->line[i] >= 0)
4195 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 4196
4197 /*
4198 * Ensure that every init quirk is properly torn down
4199 */
4200 if (priv->quirk->exit)
4201 priv->quirk->exit(priv->dev);
241fc436
RK		 4202}
4203EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4204
4205void pciserial_resume_ports(struct serial_private *priv)
4206{
4207 int i;
4208
4209 /*
4210 * Ensure that the board is correctly configured.
4211 */
4212 if (priv->quirk->init)
4213 priv->quirk->init(priv->dev);
4214
4215 for (i = 0; i < priv->nr; i++)
4216 if (priv->line[i] >= 0)
4217 serial8250_resume_port(priv->line[i]);
4218}
4219EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4220
4221/*
4222 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4223 * to the arrangement of serial ports on a PCI card.
4224 */
9671f099 4225static int
241fc436
RK		 4226pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4227{
5bf8f501 4228 struct pci_serial_quirk *quirk;
241fc436 4229 struct serial_private *priv;
975a1a7d
RK		 4230 const struct pciserial_board *board;
4231 struct pciserial_board tmp;
241fc436
RK		 4232 int rc;
4233
5bf8f501
FB		 4234 quirk = find_quirk(dev);
4235 if (quirk->probe) {
4236 rc = quirk->probe(dev);
4237 if (rc)
4238 return rc;
4239 }
4240
241fc436 4241 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
af8c5b8d 4242 dev_err(&dev->dev, "invalid driver_data: %ld\n",
241fc436
RK		 4243 ent->driver_data);
4244 return -EINVAL;
4245 }
4246
4247 board = &pci_boards[ent->driver_data];
4248
4249 rc = pci_enable_device(dev);
2807190b 4250 pci_save_state(dev);
241fc436
RK		 4251 if (rc)
4252 return rc;
4253
4254 if (ent->driver_data == pbn_default) {
4255 /*
4256 * Use a copy of the pci_board entry for this;
4257 * avoid changing entries in the table.
4258 */
4259 memcpy(&tmp, board, sizeof(struct pciserial_board));
4260 board = &tmp;
4261
4262 /*
4263 * We matched one of our class entries. Try to
4264 * determine the parameters of this board.
4265 */
975a1a7d 4266 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 4267 if (rc)
4268 goto disable;
4269 } else {
4270 /*
4271 * We matched an explicit entry. If we are able to
4272 * detect this boards settings with our heuristic,
4273 * then we no longer need this entry.
4274 */
4275 memcpy(&tmp, &pci_boards[pbn_default],
4276 sizeof(struct pciserial_board));
4277 rc = serial_pci_guess_board(dev, &tmp);
4278 if (rc == 0 && serial_pci_matches(board, &tmp))
4279 moan_device("Redundant entry in serial pci_table.",
4280 dev);
4281 }
4282
4283 priv = pciserial_init_ports(dev, board);
4284 if (!IS_ERR(priv)) {
4285 pci_set_drvdata(dev, priv);
4286 return 0;
4287 }
4288
4289 rc = PTR_ERR(priv);
1da177e4 4290
241fc436 4291 disable:
056a8763 4292 pci_disable_device(dev);
241fc436
RK		 4293 return rc;
4294}
1da177e4 4295
ae8d8a14 4296static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 4297{
4298 struct serial_private *priv = pci_get_drvdata(dev);
4299
241fc436
RK		 4300 pciserial_remove_ports(priv);
4301
4302 pci_disable_device(dev);
1da177e4
LT		 4303}
4304
61702c3e
AS		 4305#ifdef CONFIG_PM_SLEEP
4306static int pciserial_suspend_one(struct device *dev)
1da177e4 4307{
61702c3e
AS		 4308 struct pci_dev *pdev = to_pci_dev(dev);
4309 struct serial_private *priv = pci_get_drvdata(pdev);
1da177e4 4310
241fc436
RK		 4311 if (priv)
4312 pciserial_suspend_ports(priv);
1da177e4 4313
1da177e4
LT		 4314 return 0;
4315}
4316
61702c3e 4317static int pciserial_resume_one(struct device *dev)
1da177e4 4318{
61702c3e
AS		 4319 struct pci_dev *pdev = to_pci_dev(dev);
4320 struct serial_private *priv = pci_get_drvdata(pdev);
ccb9d59e 4321 int err;
1da177e4
LT		 4322
4323 if (priv) {
1da177e4
LT		 4324 /*
4325 * The device may have been disabled. Re-enable it.
4326 */
61702c3e 4327 err = pci_enable_device(pdev);
40836c48 4328 /* FIXME: We cannot simply error out here */
ccb9d59e 4329 if (err)
61702c3e 4330 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
241fc436 4331 pciserial_resume_ports(priv);
1da177e4
LT		 4332 }
4333 return 0;
4334}
1d5e7996 4335#endif
1da177e4 4336
61702c3e
AS		 4337static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4338 pciserial_resume_one);
4339
1da177e4 4340static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 4341 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4342 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4343 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4344 pbn_b2_8_921600 },
0c6d774c
TW		 4345 /* Advantech also use 0x3618 and 0xf618 */
4346 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4347 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4348 pbn_b0_4_921600 },
4349 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4350 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4351 pbn_b0_4_921600 },
1da177e4
LT		 4352 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4353 PCI_SUBVENDOR_ID_CONNECT_TECH,
4354 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4355 pbn_b1_8_1382400 },
4356 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4357 PCI_SUBVENDOR_ID_CONNECT_TECH,
4358 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4359 pbn_b1_4_1382400 },
4360 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4361 PCI_SUBVENDOR_ID_CONNECT_TECH,
4362 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4363 pbn_b1_2_1382400 },
4364 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4365 PCI_SUBVENDOR_ID_CONNECT_TECH,
4366 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4367 pbn_b1_8_1382400 },
4368 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4369 PCI_SUBVENDOR_ID_CONNECT_TECH,
4370 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4371 pbn_b1_4_1382400 },
4372 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4373 PCI_SUBVENDOR_ID_CONNECT_TECH,
4374 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4375 pbn_b1_2_1382400 },
4376 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4377 PCI_SUBVENDOR_ID_CONNECT_TECH,
4378 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4379 pbn_b1_8_921600 },
4380 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4381 PCI_SUBVENDOR_ID_CONNECT_TECH,
4382 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4383 pbn_b1_8_921600 },
4384 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4385 PCI_SUBVENDOR_ID_CONNECT_TECH,
4386 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4387 pbn_b1_4_921600 },
4388 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4389 PCI_SUBVENDOR_ID_CONNECT_TECH,
4390 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4391 pbn_b1_4_921600 },
4392 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4393 PCI_SUBVENDOR_ID_CONNECT_TECH,
4394 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4395 pbn_b1_2_921600 },
4396 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4397 PCI_SUBVENDOR_ID_CONNECT_TECH,
4398 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4399 pbn_b1_8_921600 },
4400 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4401 PCI_SUBVENDOR_ID_CONNECT_TECH,
4402 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4403 pbn_b1_8_921600 },
4404 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4405 PCI_SUBVENDOR_ID_CONNECT_TECH,
4406 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4407 pbn_b1_4_921600 },
26e92861
GH		 4408 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4409 PCI_SUBVENDOR_ID_CONNECT_TECH,
4410 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4411 pbn_b1_2_1250000 },
4412 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4413 PCI_SUBVENDOR_ID_CONNECT_TECH,
4414 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4415 pbn_b0_2_1843200 },
4416 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4417 PCI_SUBVENDOR_ID_CONNECT_TECH,
4418 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4419 pbn_b0_4_1843200 },
85d1494e
YY		 4420 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4421 PCI_VENDOR_ID_AFAVLAB,
4422 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4423 pbn_b0_4_1152000 },
26e92861
GH		 4424 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4425 PCI_SUBVENDOR_ID_CONNECT_TECH,
4426 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4427 pbn_b0_2_1843200_200 },
4428 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4429 PCI_SUBVENDOR_ID_CONNECT_TECH,
4430 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4431 pbn_b0_4_1843200_200 },
4432 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4433 PCI_SUBVENDOR_ID_CONNECT_TECH,
4434 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4435 pbn_b0_8_1843200_200 },
4436 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4437 PCI_SUBVENDOR_ID_CONNECT_TECH,
4438 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4439 pbn_b0_2_1843200_200 },
4440 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4441 PCI_SUBVENDOR_ID_CONNECT_TECH,
4442 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4443 pbn_b0_4_1843200_200 },
4444 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4445 PCI_SUBVENDOR_ID_CONNECT_TECH,
4446 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4447 pbn_b0_8_1843200_200 },
4448 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4449 PCI_SUBVENDOR_ID_CONNECT_TECH,
4450 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4451 pbn_b0_2_1843200_200 },
4452 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4453 PCI_SUBVENDOR_ID_CONNECT_TECH,
4454 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4455 pbn_b0_4_1843200_200 },
4456 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4457 PCI_SUBVENDOR_ID_CONNECT_TECH,
4458 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4459 pbn_b0_8_1843200_200 },
4460 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4461 PCI_SUBVENDOR_ID_CONNECT_TECH,
4462 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4463 pbn_b0_2_1843200_200 },
4464 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4465 PCI_SUBVENDOR_ID_CONNECT_TECH,
4466 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4467 pbn_b0_4_1843200_200 },
4468 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4469 PCI_SUBVENDOR_ID_CONNECT_TECH,
4470 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4471 pbn_b0_8_1843200_200 },
c68d2b15
BH		 4472 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4473 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4474 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 4475
4476 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4478 pbn_b2_bt_1_115200 },
4479 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4481 pbn_b2_bt_2_115200 },
4482 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4484 pbn_b2_bt_4_115200 },
4485 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4487 pbn_b2_bt_2_115200 },
4488 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4490 pbn_b2_bt_4_115200 },
4491 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4493 pbn_b2_8_115200 },
e65f0f82
FL		 4494 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496 pbn_b2_8_460800 },
1da177e4
LT		 4497 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499 pbn_b2_8_115200 },
4500
4501 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_b2_bt_2_115200 },
4504 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506 pbn_b2_bt_2_921600 },
4507 /*
4508 * VScom SPCOM800, from sl@s.pl
4509 */
5756ee99
AC		 4510 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4512 pbn_b2_8_921600 },
4513 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4515 pbn_b2_4_921600 },
b76c5a07
CB		 4516 /* Unknown card - subdevice 0x1584 */
4517 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4518 PCI_VENDOR_ID_PLX,
4519 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 4520 pbn_b2_4_115200 },
4521 /* Unknown card - subdevice 0x1588 */
4522 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4523 PCI_VENDOR_ID_PLX,
4524 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4525 pbn_b2_8_115200 },
1da177e4
LT		 4526 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4527 PCI_SUBVENDOR_ID_KEYSPAN,
4528 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4529 pbn_panacom },
4530 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4532 pbn_panacom4 },
4533 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4535 pbn_panacom2 },
a9cccd34
MF		 4536 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4537 PCI_VENDOR_ID_ESDGMBH,
4538 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4539 pbn_b2_4_115200 },
1da177e4
LT		 4540 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4541 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4542 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 4543 pbn_b2_4_460800 },
4544 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4545 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4546 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 4547 pbn_b2_8_460800 },
4548 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4549 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4550 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 4551 pbn_b2_16_460800 },
4552 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4553 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4554 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 4555 pbn_b2_16_460800 },
4556 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4557 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4558 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 4559 pbn_b2_4_460800 },
4560 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4561 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4562 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 4563 pbn_b2_8_460800 },
add7b58e
BH		 4564 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4565 PCI_SUBVENDOR_ID_EXSYS,
4566 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 4567 pbn_b2_4_115200 },
1da177e4
LT		 4568 /*
4569 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4570 * (Exoray@isys.ca)
4571 */
4572 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4573 0x10b5, 0x106a, 0, 0,
4574 pbn_plx_romulus },
1bc8cde4
MS		 4575 /*
4576 * EndRun Technologies. PCI express device range.
4577 * EndRun PTP/1588 has 2 Native UARTs.
4578 */
4579 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_endrun_2_4000000 },
55c7c0fd
AC		 4582 /*
4583 * Quatech cards. These actually have configurable clocks but for
4584 * now we just use the default.
4585 *
4586 * 100 series are RS232, 200 series RS422,
4587 */
1da177e4
LT		 4588 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_b1_4_115200 },
4591 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_b1_2_115200 },
55c7c0fd
AC		 4594 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b2_2_115200 },
4597 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_b1_2_115200 },
4600 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_b2_2_115200 },
4603 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b1_4_115200 },
1da177e4
LT		 4606 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_b1_8_115200 },
4609 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_b1_8_115200 },
55c7c0fd
AC		 4612 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_b1_4_115200 },
4615 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_b1_2_115200 },
4618 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_b1_4_115200 },
4621 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_b1_2_115200 },
4624 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_b2_4_115200 },
4627 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_b2_2_115200 },
4630 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_b2_1_115200 },
4633 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_b2_4_115200 },
4636 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_b2_2_115200 },
4639 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_b2_1_115200 },
4642 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_b0_8_115200 },
4645
1da177e4 4646 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4647 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4648 0, 0,
1da177e4 4649 pbn_b0_4_921600 },
fbc0dc0d 4650 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4651 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4652 0, 0,
fbc0dc0d 4653 pbn_b0_4_1152000 },
c9bd9d01
MP		 4654 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_b0_bt_2_921600 },
db1de159
DR		 4657
4658 /*
4659 * The below card is a little controversial since it is the
4660 * subject of a PCI vendor/device ID clash. (See
4661 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4662 * For now just used the hex ID 0x950a.
4663 */
39aced68 4664 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 4665 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4666 0, 0, pbn_b0_2_115200 },
4667 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4668 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4669 0, 0, pbn_b0_2_115200 },
db1de159
DR		 4670 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_b0_2_1130000 },
70fd8fde
AP		 4673 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4674 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4675 pbn_b0_1_921600 },
1da177e4
LT		 4676 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_b0_4_115200 },
4679 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 pbn_b0_bt_2_921600 },
e847003f
LB		 4682 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4683 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4684 pbn_b2_8_1152000 },
1da177e4 4685
7106b4e3
LH		 4686 /*
4687 * Oxford Semiconductor Inc. Tornado PCI express device range.
4688 */
4689 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4691 pbn_b0_1_4000000 },
4692 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4694 pbn_b0_1_4000000 },
4695 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 pbn_oxsemi_1_4000000 },
4698 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 pbn_oxsemi_1_4000000 },
4701 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4703 pbn_b0_1_4000000 },
4704 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4706 pbn_b0_1_4000000 },
4707 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4709 pbn_oxsemi_1_4000000 },
4710 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4712 pbn_oxsemi_1_4000000 },
4713 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715 pbn_b0_1_4000000 },
4716 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718 pbn_b0_1_4000000 },
4719 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721 pbn_b0_1_4000000 },
4722 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724 pbn_b0_1_4000000 },
4725 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727 pbn_oxsemi_2_4000000 },
4728 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730 pbn_oxsemi_2_4000000 },
4731 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 pbn_oxsemi_4_4000000 },
4734 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736 pbn_oxsemi_4_4000000 },
4737 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739 pbn_oxsemi_8_4000000 },
4740 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742 pbn_oxsemi_8_4000000 },
4743 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_oxsemi_1_4000000 },
4746 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4748 pbn_oxsemi_1_4000000 },
4749 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4750 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4751 pbn_oxsemi_1_4000000 },
4752 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754 pbn_oxsemi_1_4000000 },
4755 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757 pbn_oxsemi_1_4000000 },
4758 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4759 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4760 pbn_oxsemi_1_4000000 },
4761 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4762 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4763 pbn_oxsemi_1_4000000 },
4764 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4765 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4766 pbn_oxsemi_1_4000000 },
4767 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4768 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4769 pbn_oxsemi_1_4000000 },
4770 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4771 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4772 pbn_oxsemi_1_4000000 },
4773 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4774 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4775 pbn_oxsemi_1_4000000 },
4776 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4777 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4778 pbn_oxsemi_1_4000000 },
4779 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4780 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4781 pbn_oxsemi_1_4000000 },
4782 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_oxsemi_1_4000000 },
4785 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4787 pbn_oxsemi_1_4000000 },
4788 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4790 pbn_oxsemi_1_4000000 },
4791 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4793 pbn_oxsemi_1_4000000 },
4794 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4796 pbn_oxsemi_1_4000000 },
4797 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_oxsemi_1_4000000 },
4800 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4802 pbn_oxsemi_1_4000000 },
4803 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 pbn_oxsemi_1_4000000 },
4806 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4807 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4808 pbn_oxsemi_1_4000000 },
4809 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 pbn_oxsemi_1_4000000 },
4812 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4814 pbn_oxsemi_1_4000000 },
4815 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4816 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4817 pbn_oxsemi_1_4000000 },
4818 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4819 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4820 pbn_oxsemi_1_4000000 },
b80de369
LH		 4821 /*
4822 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4823 */
4824 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4825 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4826 pbn_oxsemi_1_4000000 },
4827 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4828 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4829 pbn_oxsemi_2_4000000 },
4830 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4831 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4832 pbn_oxsemi_4_4000000 },
4833 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4834 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4835 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4836
4837 /*
4838 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4839 */
4840 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4841 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4842 pbn_oxsemi_2_4000000 },
4843
1da177e4
LT		 4844 /*
4845 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4846 * from skokodyn@yahoo.com
4847 */
4848 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4849 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4850 pbn_sbsxrsio },
4851 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4852 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4853 pbn_sbsxrsio },
4854 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4855 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4856 pbn_sbsxrsio },
4857 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4858 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4859 pbn_sbsxrsio },
4860
4861 /*
4862 * Digitan DS560-558, from jimd@esoft.com
4863 */
4864 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4865 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4866 pbn_b1_1_115200 },
4867
4868 /*
4869 * Titan Electronic cards
4870 * The 400L and 800L have a custom setup quirk.
4871 */
4872 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4874 pbn_b0_1_921600 },
4875 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4877 pbn_b0_2_921600 },
4878 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4880 pbn_b0_4_921600 },
4881 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4883 pbn_b0_4_921600 },
4884 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4886 pbn_b1_1_921600 },
4887 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4889 pbn_b1_bt_2_921600 },
4890 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4892 pbn_b0_bt_4_921600 },
4893 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4895 pbn_b0_bt_8_921600 },
66169ad1
YY		 4896 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4898 pbn_b4_bt_2_921600 },
4899 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4901 pbn_b4_bt_4_921600 },
4902 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4904 pbn_b4_bt_8_921600 },
4905 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4907 pbn_b0_4_921600 },
4908 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4910 pbn_b0_4_921600 },
4911 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4913 pbn_b0_4_921600 },
4914 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4916 pbn_oxsemi_1_4000000 },
4917 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4919 pbn_oxsemi_2_4000000 },
4920 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4922 pbn_oxsemi_4_4000000 },
4923 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4924 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4925 pbn_oxsemi_8_4000000 },
4926 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4928 pbn_oxsemi_2_4000000 },
4929 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4931 pbn_oxsemi_2_4000000 },
48c0247d
YY		 4932 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4934 pbn_b0_bt_2_921600 },
1e9deb11
YY		 4935 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4937 pbn_b0_4_921600 },
4938 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4940 pbn_b0_4_921600 },
4941 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4943 pbn_b0_4_921600 },
4944 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4946 pbn_b0_4_921600 },
1da177e4
LT		 4947
4948 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 pbn_b2_1_460800 },
4951 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953 pbn_b2_1_460800 },
4954 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956 pbn_b2_1_460800 },
4957 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959 pbn_b2_bt_2_921600 },
4960 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 pbn_b2_bt_2_921600 },
4963 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4965 pbn_b2_bt_2_921600 },
4966 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4968 pbn_b2_bt_4_921600 },
4969 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4971 pbn_b2_bt_4_921600 },
4972 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4974 pbn_b2_bt_4_921600 },
4975 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4977 pbn_b0_1_921600 },
4978 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4980 pbn_b0_1_921600 },
4981 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4983 pbn_b0_1_921600 },
4984 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4986 pbn_b0_bt_2_921600 },
4987 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4989 pbn_b0_bt_2_921600 },
4990 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4992 pbn_b0_bt_2_921600 },
4993 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4995 pbn_b0_bt_4_921600 },
4996 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4998 pbn_b0_bt_4_921600 },
4999 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
5000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5001 pbn_b0_bt_4_921600 },
3ec9c594
AP		 5002 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
5003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5004 pbn_b0_bt_8_921600 },
5005 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
5006 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5007 pbn_b0_bt_8_921600 },
5008 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
5009 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5010 pbn_b0_bt_8_921600 },
1da177e4
LT		 5011
5012 /*
5013 * Computone devices submitted by Doug McNash dmcnash@computone.com
5014 */
5015 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5016 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
5017 0, 0, pbn_computone_4 },
5018 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5019 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
5020 0, 0, pbn_computone_8 },
5021 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5022 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
5023 0, 0, pbn_computone_6 },
5024
5025 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
5026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5027 pbn_oxsemi },
5028 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
5029 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5030 pbn_b0_bt_1_921600 },
5031
abd7baca
SC		 5032 /*
5033 * SUNIX (TIMEDIA)
5034 */
5035 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5036 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
5037 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
5038 pbn_b0_bt_1_921600 },
5039
5040 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5041 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
5042 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5043 pbn_b0_bt_1_921600 },
5044
1da177e4
LT		 5045 /*
5046 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5047 */
5048 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5050 pbn_b0_bt_8_115200 },
5051 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5053 pbn_b0_bt_8_115200 },
5054
5055 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5057 pbn_b0_bt_2_115200 },
5058 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5060 pbn_b0_bt_2_115200 },
5061 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5063 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 5064 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5066 pbn_b0_bt_2_115200 },
5067 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5069 pbn_b0_bt_2_115200 },
1da177e4
LT		 5070 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5072 pbn_b0_bt_4_460800 },
5073 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5075 pbn_b0_bt_4_460800 },
5076 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5078 pbn_b0_bt_2_460800 },
5079 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5081 pbn_b0_bt_2_460800 },
5082 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5084 pbn_b0_bt_2_460800 },
5085 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5087 pbn_b0_bt_1_115200 },
5088 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5090 pbn_b0_bt_1_460800 },
5091
1fb8cacc
RK		 5092 /*
5093 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5094 * Cards are identified by their subsystem vendor IDs, which
5095 * (in hex) match the model number.
5096 *
5097 * Note that JC140x are RS422/485 cards which require ox950
5098 * ACR = 0x10, and as such are not currently fully supported.
5099 */
5100 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5101 0x1204, 0x0004, 0, 0,
5102 pbn_b0_4_921600 },
5103 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5104 0x1208, 0x0004, 0, 0,
5105 pbn_b0_4_921600 },
5106/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5107 0x1402, 0x0002, 0, 0,
5108 pbn_b0_2_921600 }, */
5109/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5110 0x1404, 0x0004, 0, 0,
5111 pbn_b0_4_921600 }, */
5112 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5113 0x1208, 0x0004, 0, 0,
5114 pbn_b0_4_921600 },
5115
2a52fcb5
KY		 5116 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5117 0x1204, 0x0004, 0, 0,
5118 pbn_b0_4_921600 },
5119 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5120 0x1208, 0x0004, 0, 0,
5121 pbn_b0_4_921600 },
5122 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5123 0x1208, 0x0004, 0, 0,
5124 pbn_b0_4_921600 },
1da177e4
LT		 5125 /*
5126 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5127 */
5128 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5130 pbn_b1_1_1382400 },
5131
5132 /*
5133 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5134 */
5135 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5137 pbn_b1_1_1382400 },
5138
5139 /*
5140 * RAStel 2 port modem, gerg@moreton.com.au
5141 */
5142 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5144 pbn_b2_bt_2_115200 },
5145
5146 /*
5147 * EKF addition for i960 Boards form EKF with serial port
5148 */
5149 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5150 0xE4BF, PCI_ANY_ID, 0, 0,
5151 pbn_intel_i960 },
5152
5153 /*
5154 * Xircom Cardbus/Ethernet combos
5155 */
5156 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5158 pbn_b0_1_115200 },
5159 /*
5160 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5161 */
5162 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5164 pbn_b0_1_115200 },
5165
5166 /*
5167 * Untested PCI modems, sent in from various folks...
5168 */
5169
5170 /*
5171 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5172 */
5173 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5174 0x1048, 0x1500, 0, 0,
5175 pbn_b1_1_115200 },
5176
5177 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5178 0xFF00, 0, 0, 0,
5179 pbn_sgi_ioc3 },
5180
5181 /*
5182 * HP Diva card
5183 */
5184 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5185 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5186 pbn_b1_1_115200 },
5187 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5189 pbn_b0_5_115200 },
5190 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5192 pbn_b2_1_115200 },
5193
d9004eb4
ABL		 5194 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5196 pbn_b3_2_115200 },
1da177e4
LT		 5197 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5199 pbn_b3_4_115200 },
5200 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5202 pbn_b3_8_115200 },
5203
5204 /*
5205 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
5206 */
5207 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
5208 PCI_ANY_ID, PCI_ANY_ID,
5209 0,
5210 0, pbn_exar_XR17C152 },
5211 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
5212 PCI_ANY_ID, PCI_ANY_ID,
5213 0,
5214 0, pbn_exar_XR17C154 },
5215 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
5216 PCI_ANY_ID, PCI_ANY_ID,
5217 0,
5218 0, pbn_exar_XR17C158 },
dc96efb7 5219 /*
96a5d18b 5220 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
dc96efb7
MS		 5221 */
5222 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
5223 PCI_ANY_ID, PCI_ANY_ID,
5224 0,
5225 0, pbn_exar_XR17V352 },
5226 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
5227 PCI_ANY_ID, PCI_ANY_ID,
5228 0,
5229 0, pbn_exar_XR17V354 },
5230 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
5231 PCI_ANY_ID, PCI_ANY_ID,
5232 0,
5233 0, pbn_exar_XR17V358 },
be32c0cf
SG		 5234 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
5235 PCI_ANY_ID, PCI_ANY_ID,
5236 0,
5237 0, pbn_exar_XR17V4358 },
96a5d18b
SG		 5238 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
5239 PCI_ANY_ID, PCI_ANY_ID,
5240 0,
5241 0, pbn_exar_XR17V8358 },
89c043a6
AL		 5242 /*
5243 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5244 */
5245 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5246 PCI_ANY_ID, PCI_ANY_ID,
5247 0,
5248 0, pbn_pericom_PI7C9X7951 },
5249 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5250 PCI_ANY_ID, PCI_ANY_ID,
5251 0,
5252 0, pbn_pericom_PI7C9X7952 },
5253 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5254 PCI_ANY_ID, PCI_ANY_ID,
5255 0,
5256 0, pbn_pericom_PI7C9X7954 },
5257 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5258 PCI_ANY_ID, PCI_ANY_ID,
5259 0,
5260 0, pbn_pericom_PI7C9X7958 },
1da177e4
LT		 5261 /*
5262 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5263 */
5264 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5266 pbn_b0_1_115200 },
84f8c6fc
NV		 5267 /*
5268 * ITE
5269 */
5270 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5271 PCI_ANY_ID, PCI_ANY_ID,
5272 0, 0,
5273 pbn_b1_bt_1_115200 },
1da177e4 5274
737c1756
PH		 5275 /*
5276 * IntaShield IS-200
5277 */
5278 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5279 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5280 pbn_b2_2_115200 },
4b6f6ce9
IGP		 5281 /*
5282 * IntaShield IS-400
5283 */
5284 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5285 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5286 pbn_b2_4_115200 },
48212008
TH		 5287 /*
5288 * Perle PCI-RAS cards
5289 */
5290 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5291 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5292 0, 0, pbn_b2_4_921600 },
5293 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5294 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5295 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 5296
5297 /*
5298 * Mainpine series cards: Fairly standard layout but fools
5299 * parts of the autodetect in some cases and uses otherwise
5300 * unmatched communications subclasses in the PCI Express case
5301 */
5302
5303 { /* RockForceDUO */
5304 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5305 PCI_VENDOR_ID_MAINPINE, 0x0200,
5306 0, 0, pbn_b0_2_115200 },
5307 { /* RockForceQUATRO */
5308 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5309 PCI_VENDOR_ID_MAINPINE, 0x0300,
5310 0, 0, pbn_b0_4_115200 },
5311 { /* RockForceDUO+ */
5312 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5313 PCI_VENDOR_ID_MAINPINE, 0x0400,
5314 0, 0, pbn_b0_2_115200 },
5315 { /* RockForceQUATRO+ */
5316 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5317 PCI_VENDOR_ID_MAINPINE, 0x0500,
5318 0, 0, pbn_b0_4_115200 },
5319 { /* RockForce+ */
5320 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5321 PCI_VENDOR_ID_MAINPINE, 0x0600,
5322 0, 0, pbn_b0_2_115200 },
5323 { /* RockForce+ */
5324 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5325 PCI_VENDOR_ID_MAINPINE, 0x0700,
5326 0, 0, pbn_b0_4_115200 },
5327 { /* RockForceOCTO+ */
5328 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5329 PCI_VENDOR_ID_MAINPINE, 0x0800,
5330 0, 0, pbn_b0_8_115200 },
5331 { /* RockForceDUO+ */
5332 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5333 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5334 0, 0, pbn_b0_2_115200 },
5335 { /* RockForceQUARTRO+ */
5336 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5337 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5338 0, 0, pbn_b0_4_115200 },
5339 { /* RockForceOCTO+ */
5340 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5341 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5342 0, 0, pbn_b0_8_115200 },
5343 { /* RockForceD1 */
5344 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5345 PCI_VENDOR_ID_MAINPINE, 0x2000,
5346 0, 0, pbn_b0_1_115200 },
5347 { /* RockForceF1 */
5348 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5349 PCI_VENDOR_ID_MAINPINE, 0x2100,
5350 0, 0, pbn_b0_1_115200 },
5351 { /* RockForceD2 */
5352 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5353 PCI_VENDOR_ID_MAINPINE, 0x2200,
5354 0, 0, pbn_b0_2_115200 },
5355 { /* RockForceF2 */
5356 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5357 PCI_VENDOR_ID_MAINPINE, 0x2300,
5358 0, 0, pbn_b0_2_115200 },
5359 { /* RockForceD4 */
5360 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5361 PCI_VENDOR_ID_MAINPINE, 0x2400,
5362 0, 0, pbn_b0_4_115200 },
5363 { /* RockForceF4 */
5364 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5365 PCI_VENDOR_ID_MAINPINE, 0x2500,
5366 0, 0, pbn_b0_4_115200 },
5367 { /* RockForceD8 */
5368 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5369 PCI_VENDOR_ID_MAINPINE, 0x2600,
5370 0, 0, pbn_b0_8_115200 },
5371 { /* RockForceF8 */
5372 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5373 PCI_VENDOR_ID_MAINPINE, 0x2700,
5374 0, 0, pbn_b0_8_115200 },
5375 { /* IQ Express D1 */
5376 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5377 PCI_VENDOR_ID_MAINPINE, 0x3000,
5378 0, 0, pbn_b0_1_115200 },
5379 { /* IQ Express F1 */
5380 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5381 PCI_VENDOR_ID_MAINPINE, 0x3100,
5382 0, 0, pbn_b0_1_115200 },
5383 { /* IQ Express D2 */
5384 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5385 PCI_VENDOR_ID_MAINPINE, 0x3200,
5386 0, 0, pbn_b0_2_115200 },
5387 { /* IQ Express F2 */
5388 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5389 PCI_VENDOR_ID_MAINPINE, 0x3300,
5390 0, 0, pbn_b0_2_115200 },
5391 { /* IQ Express D4 */
5392 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5393 PCI_VENDOR_ID_MAINPINE, 0x3400,
5394 0, 0, pbn_b0_4_115200 },
5395 { /* IQ Express F4 */
5396 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5397 PCI_VENDOR_ID_MAINPINE, 0x3500,
5398 0, 0, pbn_b0_4_115200 },
5399 { /* IQ Express D8 */
5400 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5401 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5402 0, 0, pbn_b0_8_115200 },
5403 { /* IQ Express F8 */
5404 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5405 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5406 0, 0, pbn_b0_8_115200 },
5407
5408
aa798505
OJ		 5409 /*
5410 * PA Semi PA6T-1682M on-chip UART
5411 */
5412 { PCI_VENDOR_ID_PASEMI, 0xa004,
5413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5414 pbn_pasemi_1682M },
5415
46a0fac9
SB		 5416 /*
5417 * National Instruments
5418 */
04bf7e74
WP		 5419 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5421 pbn_b1_16_115200 },
5422 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5424 pbn_b1_8_115200 },
5425 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5427 pbn_b1_bt_4_115200 },
5428 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5430 pbn_b1_bt_2_115200 },
5431 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5433 pbn_b1_bt_4_115200 },
5434 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5436 pbn_b1_bt_2_115200 },
5437 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5439 pbn_b1_16_115200 },
5440 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5442 pbn_b1_8_115200 },
5443 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5445 pbn_b1_bt_4_115200 },
5446 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5448 pbn_b1_bt_2_115200 },
5449 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5451 pbn_b1_bt_4_115200 },
5452 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5454 pbn_b1_bt_2_115200 },
46a0fac9
SB		 5455 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5457 pbn_ni8430_2 },
5458 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5460 pbn_ni8430_2 },
5461 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5463 pbn_ni8430_4 },
5464 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5466 pbn_ni8430_4 },
5467 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5469 pbn_ni8430_8 },
5470 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5472 pbn_ni8430_8 },
5473 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5475 pbn_ni8430_16 },
5476 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5478 pbn_ni8430_16 },
5479 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5481 pbn_ni8430_2 },
5482 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5484 pbn_ni8430_2 },
5485 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5487 pbn_ni8430_4 },
5488 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5490 pbn_ni8430_4 },
5491
02c9b5cf
KJ		 5492 /*
5493 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5494 */
5495 { PCI_VENDOR_ID_ADDIDATA,
5496 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5497 PCI_ANY_ID,
5498 PCI_ANY_ID,
5499 0,
5500 0,
5501 pbn_b0_4_115200 },
5502
5503 { PCI_VENDOR_ID_ADDIDATA,
5504 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5505 PCI_ANY_ID,
5506 PCI_ANY_ID,
5507 0,
5508 0,
5509 pbn_b0_2_115200 },
5510
5511 { PCI_VENDOR_ID_ADDIDATA,
5512 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5513 PCI_ANY_ID,
5514 PCI_ANY_ID,
5515 0,
5516 0,
5517 pbn_b0_1_115200 },
5518
086231f7 5519 { PCI_VENDOR_ID_AMCC,
57c1f0e9 5520 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 5521 PCI_ANY_ID,
5522 PCI_ANY_ID,
5523 0,
5524 0,
5525 pbn_b1_8_115200 },
5526
5527 { PCI_VENDOR_ID_ADDIDATA,
5528 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5529 PCI_ANY_ID,
5530 PCI_ANY_ID,
5531 0,
5532 0,
5533 pbn_b0_4_115200 },
5534
5535 { PCI_VENDOR_ID_ADDIDATA,
5536 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5537 PCI_ANY_ID,
5538 PCI_ANY_ID,
5539 0,
5540 0,
5541 pbn_b0_2_115200 },
5542
5543 { PCI_VENDOR_ID_ADDIDATA,
5544 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5545 PCI_ANY_ID,
5546 PCI_ANY_ID,
5547 0,
5548 0,
5549 pbn_b0_1_115200 },
5550
5551 { PCI_VENDOR_ID_ADDIDATA,
5552 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5553 PCI_ANY_ID,
5554 PCI_ANY_ID,
5555 0,
5556 0,
5557 pbn_b0_4_115200 },
5558
5559 { PCI_VENDOR_ID_ADDIDATA,
5560 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5561 PCI_ANY_ID,
5562 PCI_ANY_ID,
5563 0,
5564 0,
5565 pbn_b0_2_115200 },
5566
5567 { PCI_VENDOR_ID_ADDIDATA,
5568 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5569 PCI_ANY_ID,
5570 PCI_ANY_ID,
5571 0,
5572 0,
5573 pbn_b0_1_115200 },
5574
5575 { PCI_VENDOR_ID_ADDIDATA,
5576 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5577 PCI_ANY_ID,
5578 PCI_ANY_ID,
5579 0,
5580 0,
5581 pbn_b0_8_115200 },
5582
1b62cbf2
KJ		 5583 { PCI_VENDOR_ID_ADDIDATA,
5584 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5585 PCI_ANY_ID,
5586 PCI_ANY_ID,
5587 0,
5588 0,
5589 pbn_ADDIDATA_PCIe_4_3906250 },
5590
5591 { PCI_VENDOR_ID_ADDIDATA,
5592 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5593 PCI_ANY_ID,
5594 PCI_ANY_ID,
5595 0,
5596 0,
5597 pbn_ADDIDATA_PCIe_2_3906250 },
5598
5599 { PCI_VENDOR_ID_ADDIDATA,
5600 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5601 PCI_ANY_ID,
5602 PCI_ANY_ID,
5603 0,
5604 0,
5605 pbn_ADDIDATA_PCIe_1_3906250 },
5606
5607 { PCI_VENDOR_ID_ADDIDATA,
5608 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5609 PCI_ANY_ID,
5610 PCI_ANY_ID,
5611 0,
5612 0,
5613 pbn_ADDIDATA_PCIe_8_3906250 },
5614
25cf9bc1
JS		 5615 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5616 PCI_VENDOR_ID_IBM, 0x0299,
5617 0, 0, pbn_b0_bt_2_115200 },
5618
972ce085
SS		 5619 /*
5620 * other NetMos 9835 devices are most likely handled by the
5621 * parport_serial driver, check drivers/parport/parport_serial.c
5622 * before adding them here.
5623 */
5624
c4285b47
MB		 5625 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5626 0xA000, 0x1000,
5627 0, 0, pbn_b0_1_115200 },
5628
7808edcd
NG		 5629 /* the 9901 is a rebranded 9912 */
5630 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5631 0xA000, 0x1000,
5632 0, 0, pbn_b0_1_115200 },
5633
5634 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5635 0xA000, 0x1000,
5636 0, 0, pbn_b0_1_115200 },
5637
5638 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5639 0xA000, 0x1000,
5640 0, 0, pbn_b0_1_115200 },
5641
5642 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5643 0xA000, 0x1000,
5644 0, 0, pbn_b0_1_115200 },
5645
5646 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5647 0xA000, 0x3002,
5648 0, 0, pbn_NETMOS9900_2s_115200 },
5649
ac6ec5b1 5650 /*
44178176 5651 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 5652 */
5653
5654 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5655 0xA000, 0x1000,
5656 0, 0, pbn_b0_1_115200 },
5657
44178176
ES		 5658 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5659 0xA000, 0x3002,
5660 0, 0, pbn_b0_bt_2_115200 },
5661
ac6ec5b1
IS		 5662 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5663 0xA000, 0x3004,
5664 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 5665 /* Intel CE4100 */
5666 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5667 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5668 pbn_ce4100_1_115200 },
b15e5691
HK		 5669 /* Intel BayTrail */
5670 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5671 PCI_ANY_ID, PCI_ANY_ID,
5672 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5673 pbn_byt },
5674 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5675 PCI_ANY_ID, PCI_ANY_ID,
5676 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5677 pbn_byt },
29897087
AC		 5678 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5679 PCI_ANY_ID, PCI_ANY_ID,
5680 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5681 pbn_byt },
5682 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
b15e5691
HK		 5683 PCI_ANY_ID, PCI_ANY_ID,
5684 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5685 pbn_byt },
095e24b0 5686
f549e94e
AS		 5687 /*
5688 * Intel Penwell
5689 */
5690 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART1,
5691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5692 pbn_pnw},
5693 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART2,
5694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5695 pbn_pnw},
5696 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PNW_UART3,
5697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5698 pbn_pnw},
5699
90b9aacf
AS		 5700 /*
5701 * Intel Tangier
5702 */
5703 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TNG_UART,
5704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5705 pbn_tng},
5706
1ede7dcc
BD		 5707 /*
5708 * Intel Quark x1000
5709 */
5710 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5712 pbn_qrk },
d9a0fbfd
AP		 5713 /*
5714 * Cronyx Omega PCI
5715 */
5716 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5718 pbn_omegapci },
ac6ec5b1 5719
ebebd49a
SH		 5720 /*
5721 * Broadcom TruManage
5722 */
5723 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5725 pbn_brcm_trumanage },
5726
6683549e
AC		 5727 /*
5728 * AgeStar as-prs2-009
5729 */
5730 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5731 PCI_ANY_ID, PCI_ANY_ID,
5732 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 5733
5734 /*
5735 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5736 * so not listed here.
5737 */
5738 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5739 PCI_ANY_ID, PCI_ANY_ID,
5740 0, 0, pbn_b0_bt_4_115200 },
5741
5742 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5743 PCI_ANY_ID, PCI_ANY_ID,
5744 0, 0, pbn_b0_bt_2_115200 },
5745
72a3c0e4
SP		 5746 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5747 PCI_ANY_ID, PCI_ANY_ID,
5748 0, 0, pbn_wch384_4 },
5749
14faa8cc
MS		 5750 /*
5751 * Commtech, Inc. Fastcom adapters
5752 */
5753 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5754 PCI_ANY_ID, PCI_ANY_ID,
5755 0,
5756 0, pbn_b0_2_1152000_200 },
5757 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5758 PCI_ANY_ID, PCI_ANY_ID,
5759 0,
5760 0, pbn_b0_4_1152000_200 },
5761 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5762 PCI_ANY_ID, PCI_ANY_ID,
5763 0,
5764 0, pbn_b0_4_1152000_200 },
5765 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5766 PCI_ANY_ID, PCI_ANY_ID,
5767 0,
5768 0, pbn_b0_8_1152000_200 },
5769 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5770 PCI_ANY_ID, PCI_ANY_ID,
5771 0,
5772 0, pbn_exar_XR17V352 },
5773 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5774 PCI_ANY_ID, PCI_ANY_ID,
5775 0,
5776 0, pbn_exar_XR17V354 },
5777 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5778 PCI_ANY_ID, PCI_ANY_ID,
5779 0,
5780 0, pbn_exar_XR17V358 },
5781
2c62a3c8
GKH		 5782 /* Fintek PCI serial cards */
5783 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5784 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5785 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5786
1da177e4
LT		 5787 /*
5788 * These entries match devices with class COMMUNICATION_SERIAL,
5789 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5790 */
5791 { PCI_ANY_ID, PCI_ANY_ID,
5792 PCI_ANY_ID, PCI_ANY_ID,
5793 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5794 0xffff00, pbn_default },
5795 { PCI_ANY_ID, PCI_ANY_ID,
5796 PCI_ANY_ID, PCI_ANY_ID,
5797 PCI_CLASS_COMMUNICATION_MODEM << 8,
5798 0xffff00, pbn_default },
5799 { PCI_ANY_ID, PCI_ANY_ID,
5800 PCI_ANY_ID, PCI_ANY_ID,
5801 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5802 0xffff00, pbn_default },
5803 { 0, }
5804};
5805
2807190b
MR		 5806static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5807 pci_channel_state_t state)
5808{
5809 struct serial_private *priv = pci_get_drvdata(dev);
5810
5811 if (state == pci_channel_io_perm_failure)
5812 return PCI_ERS_RESULT_DISCONNECT;
5813
5814 if (priv)
5815 pciserial_suspend_ports(priv);
5816
5817 pci_disable_device(dev);
5818
5819 return PCI_ERS_RESULT_NEED_RESET;
5820}
5821
5822static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5823{
5824 int rc;
5825
5826 rc = pci_enable_device(dev);
5827
5828 if (rc)
5829 return PCI_ERS_RESULT_DISCONNECT;
5830
5831 pci_restore_state(dev);
5832 pci_save_state(dev);
5833
5834 return PCI_ERS_RESULT_RECOVERED;
5835}
5836
5837static void serial8250_io_resume(struct pci_dev *dev)
5838{
5839 struct serial_private *priv = pci_get_drvdata(dev);
5840
5841 if (priv)
5842 pciserial_resume_ports(priv);
5843}
5844
1d352035 5845static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 5846 .error_detected = serial8250_io_error_detected,
5847 .slot_reset = serial8250_io_slot_reset,
5848 .resume = serial8250_io_resume,
5849};
5850
1da177e4
LT		 5851static struct pci_driver serial_pci_driver = {
5852 .name = "serial",
5853 .probe = pciserial_init_one,
2d47b716 5854 .remove = pciserial_remove_one,
61702c3e
AS		 5855 .driver = {
5856 .pm = &pciserial_pm_ops,
5857 },
1da177e4 5858 .id_table = serial_pci_tbl,
2807190b 5859 .err_handler = &serial8250_err_handler,
1da177e4
LT		 5860};
5861
15a12e83 5862module_pci_driver(serial_pci_driver);
1da177e4
LT		 5863
5864MODULE_LICENSE("GPL");
5865MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5866MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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