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serial: 8250_lpss: split LPSS driver to separate module
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4 11 */
af8c5b8d 12#undef DEBUG
1da177e4 13#include <linux/module.h>
1da177e4 14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
24
25#include <asm/byteorder.h>
26#include <asm/io.h>
27
28#include "8250.h"
29
1da177e4
LT		 30/*
31 * init function returns:
32 * > 0 - number of ports
33 * = 0 - use board->num_ports
34 * < 0 - error
35 */
36struct pci_serial_quirk {
37 u32 vendor;
38 u32 device;
39 u32 subvendor;
40 u32 subdevice;
5bf8f501 41 int (*probe)(struct pci_dev *dev);
1da177e4 42 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
2655a2c7 45 struct uart_8250_port *, int);
1da177e4
LT		 46 void (*exit)(struct pci_dev *dev);
47};
48
49#define PCI_NUM_BAR_RESOURCES 6
50
51struct serial_private {
70db3d91 52 struct pci_dev *dev;
1da177e4 53 unsigned int nr;
1da177e4
LT		 54 struct pci_serial_quirk *quirk;
55 int line[0];
56};
57
7808edcd 58static int pci_default_setup(struct serial_private*,
2655a2c7 59 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 60
1da177e4
LT		 61static void moan_device(const char *str, struct pci_dev *dev)
62{
af8c5b8d 63 dev_err(&dev->dev,
ad361c98
JP		 64 "%s: %s\n"
65 "Please send the output of lspci -vv, this\n"
66 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
67 "manufacturer and name of serial board or\n"
f2e0ea86 68 "modem board to <linux-serial@vger.kernel.org>.\n",
1da177e4
LT		 69 pci_name(dev), str, dev->vendor, dev->device,
70 dev->subsystem_vendor, dev->subsystem_device);
71}
72
73static int
2655a2c7 74setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 75 int bar, int offset, int regshift)
76{
70db3d91 77 struct pci_dev *dev = priv->dev;
1da177e4
LT		 78
79 if (bar >= PCI_NUM_BAR_RESOURCES)
80 return -EINVAL;
81
82 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
3f64b1d3 83 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
1da177e4
LT		 84 return -ENOMEM;
85
2655a2c7
AC		 86 port->port.iotype = UPIO_MEM;
87 port->port.iobase = 0;
398a9db6 88 port->port.mapbase = pci_resource_start(dev, bar) + offset;
3f64b1d3 89 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
2655a2c7 90 port->port.regshift = regshift;
1da177e4 91 } else {
2655a2c7 92 port->port.iotype = UPIO_PORT;
398a9db6 93 port->port.iobase = pci_resource_start(dev, bar) + offset;
2655a2c7
AC		 94 port->port.mapbase = 0;
95 port->port.membase = NULL;
96 port->port.regshift = 0;
1da177e4
LT		 97 }
98 return 0;
99}
100
02c9b5cf
KJ		 101/*
102 * ADDI-DATA GmbH communication cards <info@addi-data.com>
103 */
104static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 105 const struct pciserial_board *board,
2655a2c7 106 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 107{
108 unsigned int bar = 0, offset = board->first_offset;
109 bar = FL_GET_BASE(board->flags);
110
111 if (idx < 2) {
112 offset += idx * board->uart_offset;
113 } else if ((idx >= 2) && (idx < 4)) {
114 bar += 1;
115 offset += ((idx - 2) * board->uart_offset);
116 } else if ((idx >= 4) && (idx < 6)) {
117 bar += 2;
118 offset += ((idx - 4) * board->uart_offset);
119 } else if (idx >= 6) {
120 bar += 3;
121 offset += ((idx - 6) * board->uart_offset);
122 }
123
124 return setup_port(priv, port, bar, offset, board->reg_shift);
125}
126
1da177e4
LT		 127/*
128 * AFAVLAB uses a different mixture of BARs and offsets
129 * Not that ugly ;) -- HW
130 */
131static int
975a1a7d 132afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 133 struct uart_8250_port *port, int idx)
1da177e4
LT		 134{
135 unsigned int bar, offset = board->first_offset;
5756ee99 136
1da177e4
LT		 137 bar = FL_GET_BASE(board->flags);
138 if (idx < 4)
139 bar += idx;
140 else {
141 bar = 4;
142 offset += (idx - 4) * board->uart_offset;
143 }
144
70db3d91 145 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 146}
147
148/*
149 * HP's Remote Management Console. The Diva chip came in several
150 * different versions. N-class, L2000 and A500 have two Diva chips, each
151 * with 3 UARTs (the third UART on the second chip is unused). Superdome
152 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
153 * one Diva chip, but it has been expanded to 5 UARTs.
154 */
61a116ef 155static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 156{
157 int rc = 0;
158
159 switch (dev->subsystem_device) {
160 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
161 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
162 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
163 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
164 rc = 3;
165 break;
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
167 rc = 2;
168 break;
169 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
170 rc = 4;
171 break;
172 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 173 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 174 rc = 1;
175 break;
176 }
177
178 return rc;
179}
180
181/*
182 * HP's Diva chip puts the 4th/5th serial port further out, and
183 * some serial ports are supposed to be hidden on certain models.
184 */
185static int
975a1a7d
RK		 186pci_hp_diva_setup(struct serial_private *priv,
187 const struct pciserial_board *board,
2655a2c7 188 struct uart_8250_port *port, int idx)
1da177e4
LT		 189{
190 unsigned int offset = board->first_offset;
191 unsigned int bar = FL_GET_BASE(board->flags);
192
70db3d91 193 switch (priv->dev->subsystem_device) {
1da177e4
LT		 194 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
195 if (idx == 3)
196 idx++;
197 break;
198 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
199 if (idx > 0)
200 idx++;
201 if (idx > 2)
202 idx++;
203 break;
204 }
205 if (idx > 2)
206 offset = 0x18;
207
208 offset += idx * board->uart_offset;
209
70db3d91 210 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 211}
212
213/*
214 * Added for EKF Intel i960 serial boards
215 */
61a116ef 216static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4 217{
0a0d412a 218 u32 oldval;
1da177e4
LT		 219
220 if (!(dev->subsystem_device & 0x1000))
221 return -ENODEV;
222
223 /* is firmware started? */
0a0d412a 224 pci_read_config_dword(dev, 0x44, &oldval);
5756ee99 225 if (oldval == 0x00001000L) { /* RESET value */
af8c5b8d 226 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
1da177e4
LT		 227 return -ENODEV;
228 }
229 return 0;
230}
231
232/*
233 * Some PCI serial cards using the PLX 9050 PCI interface chip require
234 * that the card interrupt be explicitly enabled or disabled. This
235 * seems to be mainly needed on card using the PLX which also use I/O
236 * mapped memory.
237 */
61a116ef 238static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 239{
240 u8 irq_config;
241 void __iomem *p;
242
243 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
244 moan_device("no memory in bar 0", dev);
245 return 0;
246 }
247
248 irq_config = 0x41;
add7b58e 249 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 250 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 251 irq_config = 0x43;
5756ee99 252
1da177e4 253 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 254 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 255 /*
256 * As the megawolf cards have the int pins active
257 * high, and have 2 UART chips, both ints must be
258 * enabled on the 9050. Also, the UARTS are set in
259 * 16450 mode by default, so we have to enable the
260 * 16C950 'enhanced' mode so that we can use the
261 * deep FIFOs
262 */
263 irq_config = 0x5b;
1da177e4
LT		 264 /*
265 * enable/disable interrupts
266 */
6f441fe9 267 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 268 if (p == NULL)
269 return -ENOMEM;
270 writel(irq_config, p + 0x4c);
271
272 /*
273 * Read the register back to ensure that it took effect.
274 */
275 readl(p + 0x4c);
276 iounmap(p);
277
278 return 0;
279}
280
ae8d8a14 281static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 282{
283 u8 __iomem *p;
284
285 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
286 return;
287
288 /*
289 * disable interrupts
290 */
6f441fe9 291 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 292 if (p != NULL) {
293 writel(0, p + 0x4c);
294
295 /*
296 * Read the register back to ensure that it took effect.
297 */
298 readl(p + 0x4c);
299 iounmap(p);
300 }
301}
302
04bf7e74
WP		 303#define NI8420_INT_ENABLE_REG 0x38
304#define NI8420_INT_ENABLE_BIT 0x2000
305
ae8d8a14 306static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 307{
308 void __iomem *p;
04bf7e74
WP		 309 unsigned int bar = 0;
310
311 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
312 moan_device("no memory in bar", dev);
313 return;
314 }
315
398a9db6 316 p = pci_ioremap_bar(dev, bar);
04bf7e74
WP		 317 if (p == NULL)
318 return;
319
320 /* Disable the CPU Interrupt */
321 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
322 p + NI8420_INT_ENABLE_REG);
323 iounmap(p);
324}
325
326
46a0fac9
SB		 327/* MITE registers */
328#define MITE_IOWBSR1 0xc4
329#define MITE_IOWCR1 0xf4
330#define MITE_LCIMR1 0x08
331#define MITE_LCIMR2 0x10
332
333#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
334
ae8d8a14 335static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 336{
337 void __iomem *p;
46a0fac9
SB		 338 unsigned int bar = 0;
339
340 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
341 moan_device("no memory in bar", dev);
342 return;
343 }
344
398a9db6 345 p = pci_ioremap_bar(dev, bar);
46a0fac9
SB		 346 if (p == NULL)
347 return;
348
349 /* Disable the CPU Interrupt */
350 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
351 iounmap(p);
352}
353
1da177e4
LT		 354/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
355static int
975a1a7d 356sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 357 struct uart_8250_port *port, int idx)
1da177e4
LT		 358{
359 unsigned int bar, offset = board->first_offset;
360
361 bar = 0;
362
363 if (idx < 4) {
364 /* first four channels map to 0, 0x100, 0x200, 0x300 */
365 offset += idx * board->uart_offset;
366 } else if (idx < 8) {
367 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
368 offset += idx * board->uart_offset + 0xC00;
369 } else /* we have only 8 ports on PMC-OCTALPRO */
370 return 1;
371
70db3d91 372 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 373}
374
375/*
376* This does initialization for PMC OCTALPRO cards:
377* maps the device memory, resets the UARTs (needed, bc
378* if the module is removed and inserted again, the card
379* is in the sleep mode) and enables global interrupt.
380*/
381
382/* global control register offset for SBS PMC-OctalPro */
383#define OCT_REG_CR_OFF 0x500
384
61a116ef 385static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 386{
387 u8 __iomem *p;
388
24ed3aba 389 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 390
391 if (p == NULL)
392 return -ENOMEM;
393 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 394 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 395 udelay(50);
5756ee99 396 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 397
398 /* Set bit-2 (INTENABLE) of Control Register */
399 writeb(0x4, p + OCT_REG_CR_OFF);
400 iounmap(p);
401
402 return 0;
403}
404
405/*
406 * Disables the global interrupt of PMC-OctalPro
407 */
408
ae8d8a14 409static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 410{
411 u8 __iomem *p;
412
24ed3aba 413 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 414 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
415 if (p != NULL)
1da177e4 416 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 417 iounmap(p);
418}
419
420/*
421 * SIIG serial cards have an PCI interface chip which also controls
422 * the UART clocking frequency. Each UART can be clocked independently
25985edc 423 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 424 * are stored in the EEPROM chip. It can cause problems because this
425 * version of serial driver doesn't support differently clocked UART's
426 * on single PCI card. To prevent this, initialization functions set
427 * high frequency clocking for all UART's on given card. It is safe (I
428 * hope) because it doesn't touch EEPROM settings to prevent conflicts
429 * with other OSes (like M$ DOS).
430 *
431 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 432 *
1da177e4
LT		 433 * There is two family of SIIG serial cards with different PCI
434 * interface chip and different configuration methods:
435 * - 10x cards have control registers in IO and/or memory space;
436 * - 20x cards have control registers in standard PCI configuration space.
437 *
67d74b87
RK		 438 * Note: all 10x cards have PCI device ids 0x10..
439 * all 20x cards have PCI device ids 0x20..
440 *
fbc0dc0d
AP		 441 * There are also Quartet Serial cards which use Oxford Semiconductor
442 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
443 *
1da177e4
LT		 444 * Note: some SIIG cards are probed by the parport_serial object.
445 */
446
447#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
448#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
449
450static int pci_siig10x_init(struct pci_dev *dev)
451{
452 u16 data;
453 void __iomem *p;
454
455 switch (dev->device & 0xfff8) {
456 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
457 data = 0xffdf;
458 break;
459 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
460 data = 0xf7ff;
461 break;
462 default: /* 1S1P, 4S */
463 data = 0xfffb;
464 break;
465 }
466
6f441fe9 467 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 468 if (p == NULL)
469 return -ENOMEM;
470
471 writew(readw(p + 0x28) & data, p + 0x28);
472 readw(p + 0x28);
473 iounmap(p);
474 return 0;
475}
476
477#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
478#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
479
480static int pci_siig20x_init(struct pci_dev *dev)
481{
482 u8 data;
483
484 /* Change clock frequency for the first UART. */
485 pci_read_config_byte(dev, 0x6f, &data);
486 pci_write_config_byte(dev, 0x6f, data & 0xef);
487
488 /* If this card has 2 UART, we have to do the same with second UART. */
489 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
490 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
491 pci_read_config_byte(dev, 0x73, &data);
492 pci_write_config_byte(dev, 0x73, data & 0xef);
493 }
494 return 0;
495}
496
67d74b87
RK		 497static int pci_siig_init(struct pci_dev *dev)
498{
499 unsigned int type = dev->device & 0xff00;
500
501 if (type == 0x1000)
502 return pci_siig10x_init(dev);
503 else if (type == 0x2000)
504 return pci_siig20x_init(dev);
505
506 moan_device("Unknown SIIG card", dev);
507 return -ENODEV;
508}
509
3ec9c594 510static int pci_siig_setup(struct serial_private *priv,
975a1a7d 511 const struct pciserial_board *board,
2655a2c7 512 struct uart_8250_port *port, int idx)
3ec9c594
AP		 513{
514 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
515
516 if (idx > 3) {
517 bar = 4;
518 offset = (idx - 4) * 8;
519 }
520
521 return setup_port(priv, port, bar, offset, 0);
522}
523
1da177e4
LT		 524/*
525 * Timedia has an explosion of boards, and to avoid the PCI table from
526 * growing *huge*, we use this function to collapse some 70 entries
527 * in the PCI table into one, for sanity's and compactness's sake.
528 */
e9422e09 529static const unsigned short timedia_single_port[] = {
1da177e4
LT		 530 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
531};
532
e9422e09 533static const unsigned short timedia_dual_port[] = {
1da177e4 534 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 535 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
536 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 537 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
538 0xD079, 0
539};
540
e9422e09 541static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 542 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
543 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 544 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
545 0xB157, 0
546};
547
e9422e09 548static const unsigned short timedia_eight_port[] = {
5756ee99 549 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 550 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
551};
552
cb3592be 553static const struct timedia_struct {
1da177e4 554 int num;
e9422e09 555 const unsigned short *ids;
1da177e4
LT		 556} timedia_data[] = {
557 { 1, timedia_single_port },
558 { 2, timedia_dual_port },
559 { 4, timedia_quad_port },
e9422e09 560 { 8, timedia_eight_port }
1da177e4
LT		 561};
562
b9b24558
FB		 563/*
564 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
565 * listing them individually, this driver merely grabs them all with
566 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
567 * and should be left free to be claimed by parport_serial instead.
568 */
569static int pci_timedia_probe(struct pci_dev *dev)
570{
571 /*
572 * Check the third digit of the subdevice ID
573 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
574 */
575 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
576 dev_info(&dev->dev,
577 "ignoring Timedia subdevice %04x for parport_serial\n",
578 dev->subsystem_device);
579 return -ENODEV;
580 }
581
582 return 0;
583}
584
61a116ef 585static int pci_timedia_init(struct pci_dev *dev)
1da177e4 586{
e9422e09 587 const unsigned short *ids;
1da177e4
LT		 588 int i, j;
589
e9422e09 590 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 591 ids = timedia_data[i].ids;
592 for (j = 0; ids[j]; j++)
593 if (dev->subsystem_device == ids[j])
594 return timedia_data[i].num;
595 }
596 return 0;
597}
598
599/*
600 * Timedia/SUNIX uses a mixture of BARs and offsets
601 * Ugh, this is ugly as all hell --- TYT
602 */
603static int
975a1a7d
RK		 604pci_timedia_setup(struct serial_private *priv,
605 const struct pciserial_board *board,
2655a2c7 606 struct uart_8250_port *port, int idx)
1da177e4
LT		 607{
608 unsigned int bar = 0, offset = board->first_offset;
609
610 switch (idx) {
611 case 0:
612 bar = 0;
613 break;
614 case 1:
615 offset = board->uart_offset;
616 bar = 0;
617 break;
618 case 2:
619 bar = 1;
620 break;
621 case 3:
622 offset = board->uart_offset;
c2cd6d3c 623 /* FALLTHROUGH */
1da177e4
LT		 624 case 4: /* BAR 2 */
625 case 5: /* BAR 3 */
626 case 6: /* BAR 4 */
627 case 7: /* BAR 5 */
628 bar = idx - 2;
629 }
630
70db3d91 631 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 632}
633
634/*
635 * Some Titan cards are also a little weird
636 */
637static int
70db3d91 638titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 639 const struct pciserial_board *board,
2655a2c7 640 struct uart_8250_port *port, int idx)
1da177e4
LT		 641{
642 unsigned int bar, offset = board->first_offset;
643
644 switch (idx) {
645 case 0:
646 bar = 1;
647 break;
648 case 1:
649 bar = 2;
650 break;
651 default:
652 bar = 4;
653 offset = (idx - 2) * board->uart_offset;
654 }
655
70db3d91 656 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 657}
658
61a116ef 659static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 660{
661 msleep(100);
662 return 0;
663}
664
04bf7e74
WP		 665static int pci_ni8420_init(struct pci_dev *dev)
666{
667 void __iomem *p;
04bf7e74
WP		 668 unsigned int bar = 0;
669
670 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
671 moan_device("no memory in bar", dev);
672 return 0;
673 }
674
398a9db6 675 p = pci_ioremap_bar(dev, bar);
04bf7e74
WP		 676 if (p == NULL)
677 return -ENOMEM;
678
679 /* Enable CPU Interrupt */
680 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
681 p + NI8420_INT_ENABLE_REG);
682
683 iounmap(p);
684 return 0;
685}
686
46a0fac9
SB		 687#define MITE_IOWBSR1_WSIZE 0xa
688#define MITE_IOWBSR1_WIN_OFFSET 0x800
689#define MITE_IOWBSR1_WENAB (1 << 7)
690#define MITE_LCIMR1_IO_IE_0 (1 << 24)
691#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
692#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
693
694static int pci_ni8430_init(struct pci_dev *dev)
695{
696 void __iomem *p;
398a9db6 697 struct pci_bus_region region;
46a0fac9
SB		 698 u32 device_window;
699 unsigned int bar = 0;
700
701 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
702 moan_device("no memory in bar", dev);
703 return 0;
704 }
705
398a9db6 706 p = pci_ioremap_bar(dev, bar);
46a0fac9
SB		 707 if (p == NULL)
708 return -ENOMEM;
709
398a9db6
AS		 710 /*
711 * Set device window address and size in BAR0, while acknowledging that
712 * the resource structure may contain a translated address that differs
713 * from the address the device responds to.
714 */
715 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
716 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
6d7c157f 717 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
46a0fac9
SB		 718 writel(device_window, p + MITE_IOWBSR1);
719
720 /* Set window access to go to RAMSEL IO address space */
721 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
722 p + MITE_IOWCR1);
723
724 /* Enable IO Bus Interrupt 0 */
725 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
726
727 /* Enable CPU Interrupt */
728 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
729
730 iounmap(p);
731 return 0;
732}
733
734/* UART Port Control Register */
735#define NI8430_PORTCON 0x0f
736#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
737
738static int
bf538fe4
AC		 739pci_ni8430_setup(struct serial_private *priv,
740 const struct pciserial_board *board,
2655a2c7 741 struct uart_8250_port *port, int idx)
46a0fac9 742{
398a9db6 743 struct pci_dev *dev = priv->dev;
46a0fac9 744 void __iomem *p;
46a0fac9
SB		 745 unsigned int bar, offset = board->first_offset;
746
747 if (idx >= board->num_ports)
748 return 1;
749
750 bar = FL_GET_BASE(board->flags);
751 offset += idx * board->uart_offset;
752
398a9db6 753 p = pci_ioremap_bar(dev, bar);
5d14bba9
AS		 754 if (!p)
755 return -ENOMEM;
46a0fac9 756
7c9d440e 757 /* enable the transceiver */
46a0fac9
SB		 758 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
759 p + offset + NI8430_PORTCON);
760
761 iounmap(p);
762
763 return setup_port(priv, port, bar, offset, board->reg_shift);
764}
765
7808edcd
NG		 766static int pci_netmos_9900_setup(struct serial_private *priv,
767 const struct pciserial_board *board,
2655a2c7 768 struct uart_8250_port *port, int idx)
7808edcd
NG		 769{
770 unsigned int bar;
771
333c085e
DES		 772 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
773 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
7808edcd
NG		 774 /* netmos apparently orders BARs by datasheet layout, so serial
775 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
776 */
777 bar = 3 * idx;
778
779 return setup_port(priv, port, bar, 0, board->reg_shift);
780 } else {
781 return pci_default_setup(priv, board, port, idx);
782 }
783}
784
785/* the 99xx series comes with a range of device IDs and a variety
786 * of capabilities:
787 *
788 * 9900 has varying capabilities and can cascade to sub-controllers
789 * (cascading should be purely internal)
790 * 9904 is hardwired with 4 serial ports
791 * 9912 and 9922 are hardwired with 2 serial ports
792 */
793static int pci_netmos_9900_numports(struct pci_dev *dev)
794{
795 unsigned int c = dev->class;
796 unsigned int pi;
797 unsigned short sub_serports;
798
149a44cc 799 pi = c & 0xff;
7808edcd 800
c2f5fde1 801 if (pi == 2)
7808edcd 802 return 1;
c2f5fde1
AW		 803
804 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
7808edcd
NG		 805 /* two possibilities: 0x30ps encodes number of parallel and
806 * serial ports, or 0x1000 indicates *something*. This is not
807 * immediately obvious, since the 2s1p+4s configuration seems
808 * to offer all functionality on functions 0..2, while still
809 * advertising the same function 3 as the 4s+2s1p config.
810 */
811 sub_serports = dev->subsystem_device & 0xf;
c2f5fde1 812 if (sub_serports > 0)
7808edcd 813 return sub_serports;
c2f5fde1
AW		 814
815 dev_err(&dev->dev,
816 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
817 return 0;
7808edcd
NG		 818 }
819
820 moan_device("unknown NetMos/Mostech program interface", dev);
821 return 0;
822}
46a0fac9 823
61a116ef 824static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 825{
826 /* subdevice 0x00PS means <P> parallel, <S> serial */
827 unsigned int num_serial = dev->subsystem_device & 0xf;
828
ac6ec5b1
IS		 829 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
830 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 831 return 0;
7808edcd 832
25cf9bc1
JS		 833 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
834 dev->subsystem_device == 0x0299)
835 return 0;
836
7808edcd 837 switch (dev->device) { /* FALLTHROUGH on all */
b3d67936
AW		 838 case PCI_DEVICE_ID_NETMOS_9904:
839 case PCI_DEVICE_ID_NETMOS_9912:
840 case PCI_DEVICE_ID_NETMOS_9922:
841 case PCI_DEVICE_ID_NETMOS_9900:
842 num_serial = pci_netmos_9900_numports(dev);
843 break;
844
845 default:
846 break;
7808edcd
NG		 847 }
848
829b0000
AW		 849 if (num_serial == 0) {
850 moan_device("unknown NetMos/Mostech device", dev);
1da177e4 851 return -ENODEV;
829b0000 852 }
7808edcd 853
1da177e4
LT		 854 return num_serial;
855}
856
84f8c6fc 857/*
84f8c6fc
NV		 858 * These chips are available with optionally one parallel port and up to
859 * two serial ports. Unfortunately they all have the same product id.
860 *
861 * Basic configuration is done over a region of 32 I/O ports. The base
862 * ioport is called INTA or INTC, depending on docs/other drivers.
863 *
864 * The region of the 32 I/O ports is configured in POSIO0R...
865 */
866
867/* registers */
868#define ITE_887x_MISCR 0x9c
869#define ITE_887x_INTCBAR 0x78
870#define ITE_887x_UARTBAR 0x7c
871#define ITE_887x_PS0BAR 0x10
872#define ITE_887x_POSIO0 0x60
873
874/* I/O space size */
875#define ITE_887x_IOSIZE 32
876/* I/O space size (bits 26-24; 8 bytes = 011b) */
877#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
878/* I/O space size (bits 26-24; 32 bytes = 101b) */
879#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
880/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
881#define ITE_887x_POSIO_SPEED (3 << 29)
882/* enable IO_Space bit */
883#define ITE_887x_POSIO_ENABLE (1 << 31)
884
f79abb82 885static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 886{
887 /* inta_addr are the configuration addresses of the ITE */
888 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
889 0x200, 0x280, 0 };
890 int ret, i, type;
891 struct resource *iobase = NULL;
892 u32 miscr, uartbar, ioport;
893
894 /* search for the base-ioport */
895 i = 0;
896 while (inta_addr[i] && iobase == NULL) {
897 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
898 "ite887x");
899 if (iobase != NULL) {
900 /* write POSIO0R - speed | size | ioport */
901 pci_write_config_dword(dev, ITE_887x_POSIO0,
902 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
903 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
904 /* write INTCBAR - ioport */
5756ee99
AC		 905 pci_write_config_dword(dev, ITE_887x_INTCBAR,
906 inta_addr[i]);
84f8c6fc
NV		 907 ret = inb(inta_addr[i]);
908 if (ret != 0xff) {
909 /* ioport connected */
910 break;
911 }
912 release_region(iobase->start, ITE_887x_IOSIZE);
913 iobase = NULL;
914 }
915 i++;
916 }
917
918 if (!inta_addr[i]) {
af8c5b8d 919 dev_err(&dev->dev, "ite887x: could not find iobase\n");
84f8c6fc
NV		 920 return -ENODEV;
921 }
922
923 /* start of undocumented type checking (see parport_pc.c) */
924 type = inb(iobase->start + 0x18) & 0x0f;
925
926 switch (type) {
927 case 0x2: /* ITE8871 (1P) */
928 case 0xa: /* ITE8875 (1P) */
929 ret = 0;
930 break;
931 case 0xe: /* ITE8872 (2S1P) */
932 ret = 2;
933 break;
934 case 0x6: /* ITE8873 (1S) */
935 ret = 1;
936 break;
937 case 0x8: /* ITE8874 (2S) */
938 ret = 2;
939 break;
940 default:
941 moan_device("Unknown ITE887x", dev);
942 ret = -ENODEV;
943 }
944
945 /* configure all serial ports */
946 for (i = 0; i < ret; i++) {
947 /* read the I/O port from the device */
948 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
949 &ioport);
950 ioport &= 0x0000FF00; /* the actual base address */
951 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
952 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
953 ITE_887x_POSIO_IOSIZE_8 | ioport);
954
955 /* write the ioport to the UARTBAR */
956 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
957 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
958 uartbar |= (ioport << (16 * i)); /* set the ioport */
959 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
960
961 /* get current config */
962 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
963 /* disable interrupts (UARTx_Routing[3:0]) */
964 miscr &= ~(0xf << (12 - 4 * i));
965 /* activate the UART (UARTx_En) */
966 miscr |= 1 << (23 - i);
967 /* write new config with activated UART */
968 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
969 }
970
971 if (ret <= 0) {
972 /* the device has no UARTs if we get here */
973 release_region(iobase->start, ITE_887x_IOSIZE);
974 }
975
976 return ret;
977}
978
ae8d8a14 979static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 980{
981 u32 ioport;
982 /* the ioport is bit 0-15 in POSIO0R */
983 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
984 ioport &= 0xffff;
985 release_region(ioport, ITE_887x_IOSIZE);
986}
987
1bc8cde4
MS		 988/*
989 * EndRun Technologies.
990 * Determine the number of ports available on the device.
991 */
992#define PCI_VENDOR_ID_ENDRUN 0x7401
993#define PCI_DEVICE_ID_ENDRUN_1588 0xe100
994
995static int pci_endrun_init(struct pci_dev *dev)
996{
997 u8 __iomem *p;
998 unsigned long deviceID;
999 unsigned int number_uarts = 0;
1000
1001 /* EndRun device is all 0xexxx */
1002 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1003 (dev->device & 0xf000) != 0xe000)
1004 return 0;
1005
1006 p = pci_iomap(dev, 0, 5);
1007 if (p == NULL)
1008 return -ENOMEM;
1009
1010 deviceID = ioread32(p);
1011 /* EndRun device */
1012 if (deviceID == 0x07000200) {
1013 number_uarts = ioread8(p + 4);
1014 dev_dbg(&dev->dev,
1015 "%d ports detected on EndRun PCI Express device\n",
1016 number_uarts);
1017 }
1018 pci_iounmap(dev, p);
1019 return number_uarts;
1020}
1021
9f2a036a
RK		 1022/*
1023 * Oxford Semiconductor Inc.
1024 * Check that device is part of the Tornado range of devices, then determine
1025 * the number of ports available on the device.
1026 */
1027static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1028{
1029 u8 __iomem *p;
1030 unsigned long deviceID;
1031 unsigned int number_uarts = 0;
1032
1033 /* OxSemi Tornado devices are all 0xCxxx */
1034 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1035 (dev->device & 0xF000) != 0xC000)
1036 return 0;
1037
1038 p = pci_iomap(dev, 0, 5);
1039 if (p == NULL)
1040 return -ENOMEM;
1041
1042 deviceID = ioread32(p);
1043 /* Tornado device */
1044 if (deviceID == 0x07000200) {
1045 number_uarts = ioread8(p + 4);
af8c5b8d 1046 dev_dbg(&dev->dev,
9f2a036a 1047 "%d ports detected on Oxford PCI Express device\n",
af8c5b8d 1048 number_uarts);
9f2a036a
RK		 1049 }
1050 pci_iounmap(dev, p);
1051 return number_uarts;
1052}
1053
eb26dfe8
AC		 1054static int pci_asix_setup(struct serial_private *priv,
1055 const struct pciserial_board *board,
1056 struct uart_8250_port *port, int idx)
1057{
1058 port->bugs |= UART_BUG_PARITY;
1059 return pci_default_setup(priv, board, port, idx);
1060}
1061
55c7c0fd
AC		 1062/* Quatech devices have their own extra interface features */
1063
1064struct quatech_feature {
1065 u16 devid;
1066 bool amcc;
1067};
1068
1069#define QPCR_TEST_FOR1 0x3F
1070#define QPCR_TEST_GET1 0x00
1071#define QPCR_TEST_FOR2 0x40
1072#define QPCR_TEST_GET2 0x40
1073#define QPCR_TEST_FOR3 0x80
1074#define QPCR_TEST_GET3 0x40
1075#define QPCR_TEST_FOR4 0xC0
1076#define QPCR_TEST_GET4 0x80
1077
1078#define QOPR_CLOCK_X1 0x0000
1079#define QOPR_CLOCK_X2 0x0001
1080#define QOPR_CLOCK_X4 0x0002
1081#define QOPR_CLOCK_X8 0x0003
1082#define QOPR_CLOCK_RATE_MASK 0x0003
1083
1084
1085static struct quatech_feature quatech_cards[] = {
1086 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1087 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1088 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1089 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1090 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1091 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1092 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1093 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1095 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1096 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1097 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1098 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1099 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1100 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1101 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1102 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1103 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1104 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1105 { 0, }
1106};
1107
1108static int pci_quatech_amcc(u16 devid)
1109{
1110 struct quatech_feature *qf = &quatech_cards[0];
1111 while (qf->devid) {
1112 if (qf->devid == devid)
1113 return qf->amcc;
1114 qf++;
1115 }
1116 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1117 return 0;
1118};
1119
1120static int pci_quatech_rqopr(struct uart_8250_port *port)
1121{
1122 unsigned long base = port->port.iobase;
1123 u8 LCR, val;
1124
1125 LCR = inb(base + UART_LCR);
1126 outb(0xBF, base + UART_LCR);
1127 val = inb(base + UART_SCR);
1128 outb(LCR, base + UART_LCR);
1129 return val;
1130}
1131
1132static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1133{
1134 unsigned long base = port->port.iobase;
17b2720b 1135 u8 LCR;
55c7c0fd
AC		 1136
1137 LCR = inb(base + UART_LCR);
1138 outb(0xBF, base + UART_LCR);
17b2720b 1139 inb(base + UART_SCR);
55c7c0fd
AC		 1140 outb(qopr, base + UART_SCR);
1141 outb(LCR, base + UART_LCR);
1142}
1143
1144static int pci_quatech_rqmcr(struct uart_8250_port *port)
1145{
1146 unsigned long base = port->port.iobase;
1147 u8 LCR, val, qmcr;
1148
1149 LCR = inb(base + UART_LCR);
1150 outb(0xBF, base + UART_LCR);
1151 val = inb(base + UART_SCR);
1152 outb(val | 0x10, base + UART_SCR);
1153 qmcr = inb(base + UART_MCR);
1154 outb(val, base + UART_SCR);
1155 outb(LCR, base + UART_LCR);
1156
1157 return qmcr;
1158}
1159
1160static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1161{
1162 unsigned long base = port->port.iobase;
1163 u8 LCR, val;
1164
1165 LCR = inb(base + UART_LCR);
1166 outb(0xBF, base + UART_LCR);
1167 val = inb(base + UART_SCR);
1168 outb(val | 0x10, base + UART_SCR);
1169 outb(qmcr, base + UART_MCR);
1170 outb(val, base + UART_SCR);
1171 outb(LCR, base + UART_LCR);
1172}
1173
1174static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1175{
1176 unsigned long base = port->port.iobase;
1177 u8 LCR, val;
1178
1179 LCR = inb(base + UART_LCR);
1180 outb(0xBF, base + UART_LCR);
1181 val = inb(base + UART_SCR);
1182 if (val & 0x20) {
1183 outb(0x80, UART_LCR);
1184 if (!(inb(UART_SCR) & 0x20)) {
1185 outb(LCR, base + UART_LCR);
1186 return 1;
1187 }
1188 }
1189 return 0;
1190}
1191
1192static int pci_quatech_test(struct uart_8250_port *port)
1193{
1a33e342
AW		 1194 u8 reg, qopr;
1195
1196 qopr = pci_quatech_rqopr(port);
55c7c0fd
AC		 1197 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1198 reg = pci_quatech_rqopr(port) & 0xC0;
1199 if (reg != QPCR_TEST_GET1)
1200 return -EINVAL;
1201 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1202 reg = pci_quatech_rqopr(port) & 0xC0;
1203 if (reg != QPCR_TEST_GET2)
1204 return -EINVAL;
1205 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1206 reg = pci_quatech_rqopr(port) & 0xC0;
1207 if (reg != QPCR_TEST_GET3)
1208 return -EINVAL;
1209 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1210 reg = pci_quatech_rqopr(port) & 0xC0;
1211 if (reg != QPCR_TEST_GET4)
1212 return -EINVAL;
1213
1214 pci_quatech_wqopr(port, qopr);
1215 return 0;
1216}
1217
1218static int pci_quatech_clock(struct uart_8250_port *port)
1219{
1220 u8 qopr, reg, set;
1221 unsigned long clock;
1222
1223 if (pci_quatech_test(port) < 0)
1224 return 1843200;
1225
1226 qopr = pci_quatech_rqopr(port);
1227
1228 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1229 reg = pci_quatech_rqopr(port);
1230 if (reg & QOPR_CLOCK_X8) {
1231 clock = 1843200;
1232 goto out;
1233 }
1234 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1235 reg = pci_quatech_rqopr(port);
1236 if (!(reg & QOPR_CLOCK_X8)) {
1237 clock = 1843200;
1238 goto out;
1239 }
1240 reg &= QOPR_CLOCK_X8;
1241 if (reg == QOPR_CLOCK_X2) {
1242 clock = 3685400;
1243 set = QOPR_CLOCK_X2;
1244 } else if (reg == QOPR_CLOCK_X4) {
1245 clock = 7372800;
1246 set = QOPR_CLOCK_X4;
1247 } else if (reg == QOPR_CLOCK_X8) {
1248 clock = 14745600;
1249 set = QOPR_CLOCK_X8;
1250 } else {
1251 clock = 1843200;
1252 set = QOPR_CLOCK_X1;
1253 }
1254 qopr &= ~QOPR_CLOCK_RATE_MASK;
1255 qopr |= set;
1256
1257out:
1258 pci_quatech_wqopr(port, qopr);
1259 return clock;
1260}
1261
1262static int pci_quatech_rs422(struct uart_8250_port *port)
1263{
1264 u8 qmcr;
1265 int rs422 = 0;
1266
1267 if (!pci_quatech_has_qmcr(port))
1268 return 0;
1269 qmcr = pci_quatech_rqmcr(port);
1270 pci_quatech_wqmcr(port, 0xFF);
1271 if (pci_quatech_rqmcr(port))
1272 rs422 = 1;
1273 pci_quatech_wqmcr(port, qmcr);
1274 return rs422;
1275}
1276
1277static int pci_quatech_init(struct pci_dev *dev)
1278{
1279 if (pci_quatech_amcc(dev->device)) {
1280 unsigned long base = pci_resource_start(dev, 0);
1281 if (base) {
1282 u32 tmp;
1a33e342 1283
9c5320f8 1284 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
55c7c0fd
AC		 1285 tmp = inl(base + 0x3c);
1286 outl(tmp | 0x01000000, base + 0x3c);
9c5320f8 1287 outl(tmp &= ~0x01000000, base + 0x3c);
55c7c0fd
AC		 1288 }
1289 }
1290 return 0;
1291}
1292
1293static int pci_quatech_setup(struct serial_private *priv,
1294 const struct pciserial_board *board,
1295 struct uart_8250_port *port, int idx)
1296{
1297 /* Needed by pci_quatech calls below */
1298 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1299 /* Set up the clocking */
1300 port->port.uartclk = pci_quatech_clock(port);
1301 /* For now just warn about RS422 */
1302 if (pci_quatech_rs422(port))
1303 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1304 return pci_default_setup(priv, board, port, idx);
1305}
1306
d73dfc6a 1307static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1308{
1309}
1310
eb26dfe8 1311static int pci_default_setup(struct serial_private *priv,
975a1a7d 1312 const struct pciserial_board *board,
2655a2c7 1313 struct uart_8250_port *port, int idx)
1da177e4
LT		 1314{
1315 unsigned int bar, offset = board->first_offset, maxnr;
1316
1317 bar = FL_GET_BASE(board->flags);
1318 if (board->flags & FL_BASE_BARS)
1319 bar += idx;
1320 else
1321 offset += idx * board->uart_offset;
1322
2427ddd8
GKH		 1323 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1324 (board->reg_shift + 3);
1da177e4
LT		 1325
1326 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1327 return 1;
5756ee99 1328
70db3d91 1329 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1330}
1331
095e24b0
DB		 1332static int
1333ce4100_serial_setup(struct serial_private *priv,
1334 const struct pciserial_board *board,
2655a2c7 1335 struct uart_8250_port *port, int idx)
095e24b0
DB		 1336{
1337 int ret;
1338
08ec212c 1339 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1340 port->port.iotype = UPIO_MEM32;
1341 port->port.type = PORT_XSCALE;
1342 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1343 port->port.regshift = 2;
095e24b0
DB		 1344
1345 return ret;
1346}
1347
d9a0fbfd
AP		 1348static int
1349pci_omegapci_setup(struct serial_private *priv,
1798ca13 1350 const struct pciserial_board *board,
2655a2c7 1351 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1352{
1353 return setup_port(priv, port, 2, idx * 8, 0);
1354}
1355
ebebd49a
SH		 1356static int
1357pci_brcm_trumanage_setup(struct serial_private *priv,
1358 const struct pciserial_board *board,
1359 struct uart_8250_port *port, int idx)
1360{
1361 int ret = pci_default_setup(priv, board, port, idx);
1362
1363 port->port.type = PORT_BRCM_TRUMANAGE;
1364 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1365 return ret;
1366}
1367
fecf27a3
PH		 1368/* RTS will control by MCR if this bit is 0 */
1369#define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1370/* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1371#define FINTEK_RTS_INVERT BIT(5)
1372
1373/* We should do proper H/W transceiver setting before change to RS485 mode */
1374static int pci_fintek_rs485_config(struct uart_port *port,
1375 struct serial_rs485 *rs485)
1376{
30c6c352 1377 struct pci_dev *pci_dev = to_pci_dev(port->dev);
fecf27a3
PH		 1378 u8 setting;
1379 u8 *index = (u8 *) port->private_data;
fecf27a3
PH		 1380
1381 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1382
d3159455
PH		 1383 if (!rs485)
1384 rs485 = &port->rs485;
1385 else if (rs485->flags & SER_RS485_ENABLED)
fecf27a3
PH		 1386 memset(rs485->padding, 0, sizeof(rs485->padding));
1387 else
1388 memset(rs485, 0, sizeof(*rs485));
1389
1390 /* F81504/508/512 not support RTS delay before or after send */
1391 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1392
1393 if (rs485->flags & SER_RS485_ENABLED) {
1394 /* Enable RTS H/W control mode */
1395 setting |= FINTEK_RTS_CONTROL_BY_HW;
1396
1397 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1398 /* RTS driving high on TX */
1399 setting &= ~FINTEK_RTS_INVERT;
1400 } else {
1401 /* RTS driving low on TX */
1402 setting |= FINTEK_RTS_INVERT;
1403 }
1404
1405 rs485->delay_rts_after_send = 0;
1406 rs485->delay_rts_before_send = 0;
1407 } else {
1408 /* Disable RTS H/W control mode */
1409 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1410 }
1411
1412 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
d3159455
PH		 1413
1414 if (rs485 != &port->rs485)
1415 port->rs485 = *rs485;
1416
fecf27a3
PH		 1417 return 0;
1418}
1419
2c62a3c8
GKH		 1420static int pci_fintek_setup(struct serial_private *priv,
1421 const struct pciserial_board *board,
1422 struct uart_8250_port *port, int idx)
1423{
1424 struct pci_dev *pdev = priv->dev;
fecf27a3 1425 u8 *data;
2c62a3c8 1426 u8 config_base;
6a8bc239
PH		 1427 u16 iobase;
1428
1429 config_base = 0x40 + 0x08 * idx;
1430
1431 /* Get the io address from configuration space */
1432 pci_read_config_word(pdev, config_base + 4, &iobase);
1433
1434 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1435
1436 port->port.iotype = UPIO_PORT;
1437 port->port.iobase = iobase;
fecf27a3
PH		 1438 port->port.rs485_config = pci_fintek_rs485_config;
1439
1440 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1441 if (!data)
1442 return -ENOMEM;
1443
1444 /* preserve index in PCI configuration space */
1445 *data = idx;
1446 port->port.private_data = data;
6a8bc239
PH		 1447
1448 return 0;
1449}
1450
1451static int pci_fintek_init(struct pci_dev *dev)
1452{
1453 unsigned long iobase;
1454 u32 max_port, i;
cb8ee9f0 1455 u32 bar_data[3];
6a8bc239 1456 u8 config_base;
d3159455
PH		 1457 struct serial_private *priv = pci_get_drvdata(dev);
1458 struct uart_8250_port *port;
2c62a3c8 1459
6a8bc239
PH		 1460 switch (dev->device) {
1461 case 0x1104: /* 4 ports */
1462 case 0x1108: /* 8 ports */
1463 max_port = dev->device & 0xff;
cb8ee9f0 1464 break;
6a8bc239
PH		 1465 case 0x1112: /* 12 ports */
1466 max_port = 12;
cb8ee9f0 1467 break;
2c62a3c8 1468 default:
2c62a3c8
GKH		 1469 return -EINVAL;
1470 }
1471
cb8ee9f0 1472 /* Get the io address dispatch from the BIOS */
6a8bc239
PH		 1473 pci_read_config_dword(dev, 0x24, &bar_data[0]);
1474 pci_read_config_dword(dev, 0x20, &bar_data[1]);
1475 pci_read_config_dword(dev, 0x1c, &bar_data[2]);
cb8ee9f0 1476
6a8bc239
PH		 1477 for (i = 0; i < max_port; ++i) {
1478 /* UART0 configuration offset start from 0x40 */
1479 config_base = 0x40 + 0x08 * i;
2c62a3c8 1480
6a8bc239
PH		 1481 /* Calculate Real IO Port */
1482 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
2c62a3c8 1483
6a8bc239
PH		 1484 /* Enable UART I/O port */
1485 pci_write_config_byte(dev, config_base + 0x00, 0x01);
2c62a3c8 1486
6a8bc239
PH		 1487 /* Select 128-byte FIFO and 8x FIFO threshold */
1488 pci_write_config_byte(dev, config_base + 0x01, 0x33);
2c62a3c8 1489
6a8bc239
PH		 1490 /* LSB UART */
1491 pci_write_config_byte(dev, config_base + 0x04,
1492 (u8)(iobase & 0xff));
2c62a3c8 1493
6a8bc239
PH		 1494 /* MSB UART */
1495 pci_write_config_byte(dev, config_base + 0x05,
1496 (u8)((iobase & 0xff00) >> 8));
2c62a3c8 1497
6a8bc239 1498 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
fecf27a3 1499
d3159455
PH		 1500 if (priv) {
1501 /* re-apply RS232/485 mode when
1502 * pciserial_resume_ports()
1503 */
1504 port = serial8250_get_port(priv->line[i]);
1505 pci_fintek_rs485_config(&port->port, NULL);
1506 } else {
1507 /* First init without port data
1508 * force init to RS232 Mode
1509 */
1510 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1511 }
6a8bc239 1512 }
2c62a3c8 1513
6a8bc239 1514 return max_port;
2c62a3c8
GKH		 1515}
1516
b6adea33
MCC		 1517static int skip_tx_en_setup(struct serial_private *priv,
1518 const struct pciserial_board *board,
2655a2c7 1519 struct uart_8250_port *port, int idx)
b6adea33 1520{
2655a2c7 1521 port->port.flags |= UPF_NO_TXEN_TEST;
af8c5b8d
GKH		 1522 dev_dbg(&priv->dev->dev,
1523 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1524 priv->dev->vendor, priv->dev->device,
1525 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
b6adea33
MCC		 1526
1527 return pci_default_setup(priv, board, port, idx);
1528}
1529
0ad372b9
SM		 1530static void kt_handle_break(struct uart_port *p)
1531{
b1261c86 1532 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1533 /*
1534 * On receipt of a BI, serial device in Intel ME (Intel
1535 * management engine) needs to have its fifos cleared for sane
1536 * SOL (Serial Over Lan) output.
1537 */
1538 serial8250_clear_and_reinit_fifos(up);
1539}
1540
1541static unsigned int kt_serial_in(struct uart_port *p, int offset)
1542{
b1261c86 1543 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1544 unsigned int val;
1545
1546 /*
1547 * When the Intel ME (management engine) gets reset its serial
1548 * port registers could return 0 momentarily. Functions like
1549 * serial8250_console_write, read and save the IER, perform
1550 * some operation and then restore it. In order to avoid
1551 * setting IER register inadvertently to 0, if the value read
1552 * is 0, double check with ier value in uart_8250_port and use
1553 * that instead. up->ier should be the same value as what is
1554 * currently configured.
1555 */
1556 val = inb(p->iobase + offset);
1557 if (offset == UART_IER) {
1558 if (val == 0)
1559 val = up->ier;
1560 }
1561 return val;
1562}
1563
bc02d15a
DW		 1564static int kt_serial_setup(struct serial_private *priv,
1565 const struct pciserial_board *board,
2655a2c7 1566 struct uart_8250_port *port, int idx)
bc02d15a 1567{
2655a2c7
AC		 1568 port->port.flags |= UPF_BUG_THRE;
1569 port->port.serial_in = kt_serial_in;
1570 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1571 return skip_tx_en_setup(priv, board, port, idx);
1572}
1573
eb7073db
TM		 1574static int pci_eg20t_init(struct pci_dev *dev)
1575{
1576#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1577 return -ENODEV;
1578#else
1579 return 0;
1580#endif
1581}
1582
899f0c1c
SG		 1583#define PCI_DEVICE_ID_EXAR_XR17V4358 0x4358
1584#define PCI_DEVICE_ID_EXAR_XR17V8358 0x8358
1585
06315348
SH		 1586static int
1587pci_xr17c154_setup(struct serial_private *priv,
1588 const struct pciserial_board *board,
2655a2c7 1589 struct uart_8250_port *port, int idx)
06315348 1590{
2655a2c7 1591 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1592 return pci_default_setup(priv, board, port, idx);
1593}
1594
899f0c1c
SG		 1595static inline int
1596xr17v35x_has_slave(struct serial_private *priv)
1597{
1598 const int dev_id = priv->dev->device;
1599
1600 return ((dev_id == PCI_DEVICE_ID_EXAR_XR17V4358) ||
6d7c157f 1601 (dev_id == PCI_DEVICE_ID_EXAR_XR17V8358));
899f0c1c
SG		 1602}
1603
dc96efb7
MS		 1604static int
1605pci_xr17v35x_setup(struct serial_private *priv,
1606 const struct pciserial_board *board,
1607 struct uart_8250_port *port, int idx)
1608{
1609 u8 __iomem *p;
1610
1611 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1612 if (p == NULL)
1613 return -ENOMEM;
dc96efb7
MS		 1614
1615 port->port.flags |= UPF_EXAR_EFR;
1616
899f0c1c
SG		 1617 /*
1618 * Setup the uart clock for the devices on expansion slot to
1619 * half the clock speed of the main chip (which is 125MHz)
1620 */
1621 if (xr17v35x_has_slave(priv) && idx >= 8)
1622 port->port.uartclk = (7812500 * 16 / 2);
1623
dc96efb7
MS		 1624 /*
1625 * Setup Multipurpose Input/Output pins.
1626 */
1627 if (idx == 0) {
1628 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1629 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1630 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1631 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1632 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1633 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1634 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1635 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1636 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1637 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1638 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1639 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1640 }
f965b9c4
MS		 1641 writeb(0x00, p + UART_EXAR_8XMODE);
1642 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1643 writeb(128, p + UART_EXAR_TXTRG);
1644 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1645 iounmap(p);
1646
1647 return pci_default_setup(priv, board, port, idx);
1648}
1649
14faa8cc
MS		 1650#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1651#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1652#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1653#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1654
1655static int
1656pci_fastcom335_setup(struct serial_private *priv,
1657 const struct pciserial_board *board,
1658 struct uart_8250_port *port, int idx)
1659{
1660 u8 __iomem *p;
1661
1662 p = pci_ioremap_bar(priv->dev, 0);
1663 if (p == NULL)
1664 return -ENOMEM;
1665
1666 port->port.flags |= UPF_EXAR_EFR;
1667
1668 /*
1669 * Setup Multipurpose Input/Output pins.
1670 */
1671 if (idx == 0) {
1672 switch (priv->dev->device) {
1673 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1674 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1675 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1676 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1677 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1678 break;
1679 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1680 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1681 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1682 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1683 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1684 break;
1685 }
1686 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1687 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1688 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1689 }
1690 writeb(0x00, p + UART_EXAR_8XMODE);
1691 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1692 writeb(32, p + UART_EXAR_TXTRG);
1693 writeb(32, p + UART_EXAR_RXTRG);
1694 iounmap(p);
1695
1696 return pci_default_setup(priv, board, port, idx);
1697}
1698
6971c635
GA		 1699static int
1700pci_wch_ch353_setup(struct serial_private *priv,
6d7c157f
AW		 1701 const struct pciserial_board *board,
1702 struct uart_8250_port *port, int idx)
6971c635
GA		 1703{
1704 port->port.flags |= UPF_FIXED_TYPE;
1705 port->port.type = PORT_16550A;
06315348
SH		 1706 return pci_default_setup(priv, board, port, idx);
1707}
1708
55c368cb
AP		 1709static int
1710pci_wch_ch355_setup(struct serial_private *priv,
1711 const struct pciserial_board *board,
1712 struct uart_8250_port *port, int idx)
1713{
1714 port->port.flags |= UPF_FIXED_TYPE;
1715 port->port.type = PORT_16550A;
1716 return pci_default_setup(priv, board, port, idx);
1717}
1718
2fdd8c8c 1719static int
72a3c0e4 1720pci_wch_ch38x_setup(struct serial_private *priv,
6d7c157f
AW		 1721 const struct pciserial_board *board,
1722 struct uart_8250_port *port, int idx)
2fdd8c8c
SP		 1723{
1724 port->port.flags |= UPF_FIXED_TYPE;
1725 port->port.type = PORT_16850;
1726 return pci_default_setup(priv, board, port, idx);
1727}
1728
1da177e4
LT		 1729#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1730#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1731#define PCI_DEVICE_ID_OCTPRO 0x0001
1732#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1733#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1734#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1735#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 1736#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1737#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 1738#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1739#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1740#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
0c6d774c
TW		 1741#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1742#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
66169ad1
YY		 1743#define PCI_DEVICE_ID_TITAN_200I 0x8028
1744#define PCI_DEVICE_ID_TITAN_400I 0x8048
1745#define PCI_DEVICE_ID_TITAN_800I 0x8088
1746#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1747#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1748#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1749#define PCI_DEVICE_ID_TITAN_100E 0xA010
1750#define PCI_DEVICE_ID_TITAN_200E 0xA012
1751#define PCI_DEVICE_ID_TITAN_400E 0xA013
1752#define PCI_DEVICE_ID_TITAN_800E 0xA014
1753#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1754#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
48c0247d 1755#define PCI_DEVICE_ID_TITAN_200V3 0xA306
1e9deb11
YY		 1756#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1757#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1758#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1759#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1760#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1761#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1762#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1763#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 1764#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 1765#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 1766#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1767#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
feb58142 1768#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
27788c5f 1769#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
55c368cb 1770#define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
6683549e
AC		 1771#define PCI_VENDOR_ID_AGESTAR 0x5372
1772#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 1773#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 1774#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1775#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 1776#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 1777#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
57c1f0e9 1778#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1ede7dcc 1779#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
14faa8cc 1780
abd7baca
SC		 1781#define PCI_VENDOR_ID_SUNIX 0x1fd4
1782#define PCI_DEVICE_ID_SUNIX_1999 0x1999
1783
2fdd8c8c
SP		 1784#define PCIE_VENDOR_ID_WCH 0x1c00
1785#define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
72a3c0e4 1786#define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
7dde5578 1787#define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1da177e4 1788
89c043a6
AL		 1789#define PCI_VENDOR_ID_PERICOM 0x12D8
1790#define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1791#define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1792#define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1793#define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1794
b76c5a07
CB		 1795/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1796#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 1797#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 1798
1da177e4
LT		 1799/*
1800 * Master list of serial port init/setup/exit quirks.
1801 * This does not describe the general nature of the port.
1802 * (ie, baud base, number and location of ports, etc)
1803 *
1804 * This list is ordered alphabetically by vendor then device.
1805 * Specific entries must come before more generic entries.
1806 */
7a63ce5a 1807static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1808 /*
1809 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1810 */
1811 {
086231f7 1812 .vendor = PCI_VENDOR_ID_AMCC,
57c1f0e9 1813 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 1814 .subvendor = PCI_ANY_ID,
1815 .subdevice = PCI_ANY_ID,
1816 .setup = addidata_apci7800_setup,
1817 },
1da177e4 1818 /*
61a116ef 1819 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1820 * It is not clear whether this applies to all products.
1821 */
1822 {
1823 .vendor = PCI_VENDOR_ID_AFAVLAB,
1824 .device = PCI_ANY_ID,
1825 .subvendor = PCI_ANY_ID,
1826 .subdevice = PCI_ANY_ID,
1827 .setup = afavlab_setup,
1828 },
1829 /*
1830 * HP Diva
1831 */
1832 {
1833 .vendor = PCI_VENDOR_ID_HP,
1834 .device = PCI_DEVICE_ID_HP_DIVA,
1835 .subvendor = PCI_ANY_ID,
1836 .subdevice = PCI_ANY_ID,
1837 .init = pci_hp_diva_init,
1838 .setup = pci_hp_diva_setup,
1839 },
1840 /*
1841 * Intel
1842 */
1843 {
1844 .vendor = PCI_VENDOR_ID_INTEL,
1845 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1846 .subvendor = 0xe4bf,
1847 .subdevice = PCI_ANY_ID,
1848 .init = pci_inteli960ni_init,
1849 .setup = pci_default_setup,
1850 },
b6adea33
MCC		 1851 {
1852 .vendor = PCI_VENDOR_ID_INTEL,
1853 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1854 .subvendor = PCI_ANY_ID,
1855 .subdevice = PCI_ANY_ID,
1856 .setup = skip_tx_en_setup,
1857 },
1858 {
1859 .vendor = PCI_VENDOR_ID_INTEL,
1860 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1861 .subvendor = PCI_ANY_ID,
1862 .subdevice = PCI_ANY_ID,
1863 .setup = skip_tx_en_setup,
1864 },
1865 {
1866 .vendor = PCI_VENDOR_ID_INTEL,
1867 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1868 .subvendor = PCI_ANY_ID,
1869 .subdevice = PCI_ANY_ID,
1870 .setup = skip_tx_en_setup,
1871 },
095e24b0
DB		 1872 {
1873 .vendor = PCI_VENDOR_ID_INTEL,
1874 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1875 .subvendor = PCI_ANY_ID,
1876 .subdevice = PCI_ANY_ID,
1877 .setup = ce4100_serial_setup,
1878 },
bc02d15a
DW		 1879 {
1880 .vendor = PCI_VENDOR_ID_INTEL,
1881 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1882 .subvendor = PCI_ANY_ID,
1883 .subdevice = PCI_ANY_ID,
1884 .setup = kt_serial_setup,
1885 },
84f8c6fc
NV		 1886 /*
1887 * ITE
1888 */
1889 {
1890 .vendor = PCI_VENDOR_ID_ITE,
1891 .device = PCI_DEVICE_ID_ITE_8872,
1892 .subvendor = PCI_ANY_ID,
1893 .subdevice = PCI_ANY_ID,
1894 .init = pci_ite887x_init,
1895 .setup = pci_default_setup,
2d47b716 1896 .exit = pci_ite887x_exit,
84f8c6fc 1897 },
46a0fac9
SB		 1898 /*
1899 * National Instruments
1900 */
04bf7e74
WP		 1901 {
1902 .vendor = PCI_VENDOR_ID_NI,
1903 .device = PCI_DEVICE_ID_NI_PCI23216,
1904 .subvendor = PCI_ANY_ID,
1905 .subdevice = PCI_ANY_ID,
1906 .init = pci_ni8420_init,
1907 .setup = pci_default_setup,
2d47b716 1908 .exit = pci_ni8420_exit,
04bf7e74
WP		 1909 },
1910 {
1911 .vendor = PCI_VENDOR_ID_NI,
1912 .device = PCI_DEVICE_ID_NI_PCI2328,
1913 .subvendor = PCI_ANY_ID,
1914 .subdevice = PCI_ANY_ID,
1915 .init = pci_ni8420_init,
1916 .setup = pci_default_setup,
2d47b716 1917 .exit = pci_ni8420_exit,
04bf7e74
WP		 1918 },
1919 {
1920 .vendor = PCI_VENDOR_ID_NI,
1921 .device = PCI_DEVICE_ID_NI_PCI2324,
1922 .subvendor = PCI_ANY_ID,
1923 .subdevice = PCI_ANY_ID,
1924 .init = pci_ni8420_init,
1925 .setup = pci_default_setup,
2d47b716 1926 .exit = pci_ni8420_exit,
04bf7e74
WP		 1927 },
1928 {
1929 .vendor = PCI_VENDOR_ID_NI,
1930 .device = PCI_DEVICE_ID_NI_PCI2322,
1931 .subvendor = PCI_ANY_ID,
1932 .subdevice = PCI_ANY_ID,
1933 .init = pci_ni8420_init,
1934 .setup = pci_default_setup,
2d47b716 1935 .exit = pci_ni8420_exit,
04bf7e74
WP		 1936 },
1937 {
1938 .vendor = PCI_VENDOR_ID_NI,
1939 .device = PCI_DEVICE_ID_NI_PCI2324I,
1940 .subvendor = PCI_ANY_ID,
1941 .subdevice = PCI_ANY_ID,
1942 .init = pci_ni8420_init,
1943 .setup = pci_default_setup,
2d47b716 1944 .exit = pci_ni8420_exit,
04bf7e74
WP		 1945 },
1946 {
1947 .vendor = PCI_VENDOR_ID_NI,
1948 .device = PCI_DEVICE_ID_NI_PCI2322I,
1949 .subvendor = PCI_ANY_ID,
1950 .subdevice = PCI_ANY_ID,
1951 .init = pci_ni8420_init,
1952 .setup = pci_default_setup,
2d47b716 1953 .exit = pci_ni8420_exit,
04bf7e74
WP		 1954 },
1955 {
1956 .vendor = PCI_VENDOR_ID_NI,
1957 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1958 .subvendor = PCI_ANY_ID,
1959 .subdevice = PCI_ANY_ID,
1960 .init = pci_ni8420_init,
1961 .setup = pci_default_setup,
2d47b716 1962 .exit = pci_ni8420_exit,
04bf7e74
WP		 1963 },
1964 {
1965 .vendor = PCI_VENDOR_ID_NI,
1966 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1967 .subvendor = PCI_ANY_ID,
1968 .subdevice = PCI_ANY_ID,
1969 .init = pci_ni8420_init,
1970 .setup = pci_default_setup,
2d47b716 1971 .exit = pci_ni8420_exit,
04bf7e74
WP		 1972 },
1973 {
1974 .vendor = PCI_VENDOR_ID_NI,
1975 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1976 .subvendor = PCI_ANY_ID,
1977 .subdevice = PCI_ANY_ID,
1978 .init = pci_ni8420_init,
1979 .setup = pci_default_setup,
2d47b716 1980 .exit = pci_ni8420_exit,
04bf7e74
WP		 1981 },
1982 {
1983 .vendor = PCI_VENDOR_ID_NI,
1984 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1985 .subvendor = PCI_ANY_ID,
1986 .subdevice = PCI_ANY_ID,
1987 .init = pci_ni8420_init,
1988 .setup = pci_default_setup,
2d47b716 1989 .exit = pci_ni8420_exit,
04bf7e74
WP		 1990 },
1991 {
1992 .vendor = PCI_VENDOR_ID_NI,
1993 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1994 .subvendor = PCI_ANY_ID,
1995 .subdevice = PCI_ANY_ID,
1996 .init = pci_ni8420_init,
1997 .setup = pci_default_setup,
2d47b716 1998 .exit = pci_ni8420_exit,
04bf7e74
WP		 1999 },
2000 {
2001 .vendor = PCI_VENDOR_ID_NI,
2002 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .init = pci_ni8420_init,
2006 .setup = pci_default_setup,
2d47b716 2007 .exit = pci_ni8420_exit,
04bf7e74 2008 },
46a0fac9
SB		 2009 {
2010 .vendor = PCI_VENDOR_ID_NI,
2011 .device = PCI_ANY_ID,
2012 .subvendor = PCI_ANY_ID,
2013 .subdevice = PCI_ANY_ID,
2014 .init = pci_ni8430_init,
2015 .setup = pci_ni8430_setup,
2d47b716 2016 .exit = pci_ni8430_exit,
46a0fac9 2017 },
55c7c0fd
AC		 2018 /* Quatech */
2019 {
2020 .vendor = PCI_VENDOR_ID_QUATECH,
2021 .device = PCI_ANY_ID,
2022 .subvendor = PCI_ANY_ID,
2023 .subdevice = PCI_ANY_ID,
2024 .init = pci_quatech_init,
2025 .setup = pci_quatech_setup,
d73dfc6a 2026 .exit = pci_quatech_exit,
55c7c0fd 2027 },
1da177e4
LT		 2028 /*
2029 * Panacom
2030 */
2031 {
2032 .vendor = PCI_VENDOR_ID_PANACOM,
2033 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2034 .subvendor = PCI_ANY_ID,
2035 .subdevice = PCI_ANY_ID,
2036 .init = pci_plx9050_init,
2037 .setup = pci_default_setup,
2d47b716 2038 .exit = pci_plx9050_exit,
5756ee99 2039 },
1da177e4
LT		 2040 {
2041 .vendor = PCI_VENDOR_ID_PANACOM,
2042 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2043 .subvendor = PCI_ANY_ID,
2044 .subdevice = PCI_ANY_ID,
2045 .init = pci_plx9050_init,
2046 .setup = pci_default_setup,
2d47b716 2047 .exit = pci_plx9050_exit,
1da177e4
LT		 2048 },
2049 /*
2050 * PLX
2051 */
add7b58e
BH		 2052 {
2053 .vendor = PCI_VENDOR_ID_PLX,
2054 .device = PCI_DEVICE_ID_PLX_9050,
2055 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2056 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2057 .init = pci_plx9050_init,
2058 .setup = pci_default_setup,
2d47b716 2059 .exit = pci_plx9050_exit,
add7b58e 2060 },
1da177e4
LT		 2061 {
2062 .vendor = PCI_VENDOR_ID_PLX,
2063 .device = PCI_DEVICE_ID_PLX_9050,
2064 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2065 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2066 .init = pci_plx9050_init,
2067 .setup = pci_default_setup,
2d47b716 2068 .exit = pci_plx9050_exit,
1da177e4
LT		 2069 },
2070 {
2071 .vendor = PCI_VENDOR_ID_PLX,
2072 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2073 .subvendor = PCI_VENDOR_ID_PLX,
2074 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2075 .init = pci_plx9050_init,
2076 .setup = pci_default_setup,
2d47b716 2077 .exit = pci_plx9050_exit,
1da177e4
LT		 2078 },
2079 /*
2080 * SBS Technologies, Inc., PMC-OCTALPRO 232
2081 */
2082 {
2083 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2084 .device = PCI_DEVICE_ID_OCTPRO,
2085 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2086 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2087 .init = sbs_init,
2088 .setup = sbs_setup,
2d47b716 2089 .exit = sbs_exit,
1da177e4
LT		 2090 },
2091 /*
2092 * SBS Technologies, Inc., PMC-OCTALPRO 422
2093 */
2094 {
2095 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2096 .device = PCI_DEVICE_ID_OCTPRO,
2097 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2098 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2099 .init = sbs_init,
2100 .setup = sbs_setup,
2d47b716 2101 .exit = sbs_exit,
1da177e4
LT		 2102 },
2103 /*
2104 * SBS Technologies, Inc., P-Octal 232
2105 */
2106 {
2107 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2108 .device = PCI_DEVICE_ID_OCTPRO,
2109 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2110 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2111 .init = sbs_init,
2112 .setup = sbs_setup,
2d47b716 2113 .exit = sbs_exit,
1da177e4
LT		 2114 },
2115 /*
2116 * SBS Technologies, Inc., P-Octal 422
2117 */
2118 {
2119 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2120 .device = PCI_DEVICE_ID_OCTPRO,
2121 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2122 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2123 .init = sbs_init,
2124 .setup = sbs_setup,
2d47b716 2125 .exit = sbs_exit,
1da177e4 2126 },
1da177e4 2127 /*
61a116ef 2128 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 2129 */
2130 {
2131 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 2132 .device = PCI_ANY_ID,
1da177e4
LT		 2133 .subvendor = PCI_ANY_ID,
2134 .subdevice = PCI_ANY_ID,
67d74b87 2135 .init = pci_siig_init,
3ec9c594 2136 .setup = pci_siig_setup,
1da177e4
LT		 2137 },
2138 /*
2139 * Titan cards
2140 */
2141 {
2142 .vendor = PCI_VENDOR_ID_TITAN,
2143 .device = PCI_DEVICE_ID_TITAN_400L,
2144 .subvendor = PCI_ANY_ID,
2145 .subdevice = PCI_ANY_ID,
2146 .setup = titan_400l_800l_setup,
2147 },
2148 {
2149 .vendor = PCI_VENDOR_ID_TITAN,
2150 .device = PCI_DEVICE_ID_TITAN_800L,
2151 .subvendor = PCI_ANY_ID,
2152 .subdevice = PCI_ANY_ID,
2153 .setup = titan_400l_800l_setup,
2154 },
2155 /*
2156 * Timedia cards
2157 */
2158 {
2159 .vendor = PCI_VENDOR_ID_TIMEDIA,
2160 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2161 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2162 .subdevice = PCI_ANY_ID,
b9b24558 2163 .probe = pci_timedia_probe,
1da177e4
LT		 2164 .init = pci_timedia_init,
2165 .setup = pci_timedia_setup,
2166 },
2167 {
2168 .vendor = PCI_VENDOR_ID_TIMEDIA,
2169 .device = PCI_ANY_ID,
2170 .subvendor = PCI_ANY_ID,
2171 .subdevice = PCI_ANY_ID,
2172 .setup = pci_timedia_setup,
2173 },
abd7baca
SC		 2174 /*
2175 * SUNIX (Timedia) cards
2176 * Do not "probe" for these cards as there is at least one combination
2177 * card that should be handled by parport_pc that doesn't match the
2178 * rule in pci_timedia_probe.
2179 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2180 * There are some boards with part number SER5037AL that report
2181 * subdevice ID 0x0002.
2182 */
2183 {
2184 .vendor = PCI_VENDOR_ID_SUNIX,
2185 .device = PCI_DEVICE_ID_SUNIX_1999,
2186 .subvendor = PCI_VENDOR_ID_SUNIX,
2187 .subdevice = PCI_ANY_ID,
2188 .init = pci_timedia_init,
2189 .setup = pci_timedia_setup,
2190 },
06315348
SH		 2191 /*
2192 * Exar cards
2193 */
2194 {
2195 .vendor = PCI_VENDOR_ID_EXAR,
2196 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2197 .subvendor = PCI_ANY_ID,
2198 .subdevice = PCI_ANY_ID,
2199 .setup = pci_xr17c154_setup,
2200 },
2201 {
2202 .vendor = PCI_VENDOR_ID_EXAR,
2203 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2204 .subvendor = PCI_ANY_ID,
2205 .subdevice = PCI_ANY_ID,
2206 .setup = pci_xr17c154_setup,
2207 },
2208 {
2209 .vendor = PCI_VENDOR_ID_EXAR,
2210 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2211 .subvendor = PCI_ANY_ID,
2212 .subdevice = PCI_ANY_ID,
2213 .setup = pci_xr17c154_setup,
2214 },
dc96efb7
MS		 2215 {
2216 .vendor = PCI_VENDOR_ID_EXAR,
2217 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2218 .subvendor = PCI_ANY_ID,
2219 .subdevice = PCI_ANY_ID,
2220 .setup = pci_xr17v35x_setup,
2221 },
2222 {
2223 .vendor = PCI_VENDOR_ID_EXAR,
2224 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2225 .subvendor = PCI_ANY_ID,
2226 .subdevice = PCI_ANY_ID,
2227 .setup = pci_xr17v35x_setup,
2228 },
2229 {
2230 .vendor = PCI_VENDOR_ID_EXAR,
2231 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2232 .subvendor = PCI_ANY_ID,
2233 .subdevice = PCI_ANY_ID,
2234 .setup = pci_xr17v35x_setup,
2235 },
be32c0cf
SG		 2236 {
2237 .vendor = PCI_VENDOR_ID_EXAR,
2238 .device = PCI_DEVICE_ID_EXAR_XR17V4358,
2239 .subvendor = PCI_ANY_ID,
2240 .subdevice = PCI_ANY_ID,
2241 .setup = pci_xr17v35x_setup,
2242 },
96a5d18b
SG		 2243 {
2244 .vendor = PCI_VENDOR_ID_EXAR,
2245 .device = PCI_DEVICE_ID_EXAR_XR17V8358,
2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
2248 .setup = pci_xr17v35x_setup,
2249 },
1da177e4
LT		 2250 /*
2251 * Xircom cards
2252 */
2253 {
2254 .vendor = PCI_VENDOR_ID_XIRCOM,
2255 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2256 .subvendor = PCI_ANY_ID,
2257 .subdevice = PCI_ANY_ID,
2258 .init = pci_xircom_init,
2259 .setup = pci_default_setup,
2260 },
2261 /*
61a116ef 2262 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2263 */
2264 {
2265 .vendor = PCI_VENDOR_ID_NETMOS,
2266 .device = PCI_ANY_ID,
2267 .subvendor = PCI_ANY_ID,
2268 .subdevice = PCI_ANY_ID,
2269 .init = pci_netmos_init,
7808edcd 2270 .setup = pci_netmos_9900_setup,
1da177e4 2271 },
1bc8cde4
MS		 2272 /*
2273 * EndRun Technologies
2274 */
2275 {
2276 .vendor = PCI_VENDOR_ID_ENDRUN,
2277 .device = PCI_ANY_ID,
2278 .subvendor = PCI_ANY_ID,
2279 .subdevice = PCI_ANY_ID,
2280 .init = pci_endrun_init,
2281 .setup = pci_default_setup,
2282 },
9f2a036a 2283 /*
aa273ae5 2284 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2285 */
2286 {
2287 .vendor = PCI_VENDOR_ID_OXSEMI,
2288 .device = PCI_ANY_ID,
2289 .subvendor = PCI_ANY_ID,
2290 .subdevice = PCI_ANY_ID,
2291 .init = pci_oxsemi_tornado_init,
2292 .setup = pci_default_setup,
2293 },
2294 {
2295 .vendor = PCI_VENDOR_ID_MAINPINE,
2296 .device = PCI_ANY_ID,
2297 .subvendor = PCI_ANY_ID,
2298 .subdevice = PCI_ANY_ID,
2299 .init = pci_oxsemi_tornado_init,
2300 .setup = pci_default_setup,
2301 },
aa273ae5
SK		 2302 {
2303 .vendor = PCI_VENDOR_ID_DIGI,
2304 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2305 .subvendor = PCI_SUBVENDOR_ID_IBM,
2306 .subdevice = PCI_ANY_ID,
2307 .init = pci_oxsemi_tornado_init,
2308 .setup = pci_default_setup,
2309 },
eb7073db
TM		 2310 {
2311 .vendor = PCI_VENDOR_ID_INTEL,
2312 .device = 0x8811,
aaa10eb1
AP		 2313 .subvendor = PCI_ANY_ID,
2314 .subdevice = PCI_ANY_ID,
eb7073db 2315 .init = pci_eg20t_init,
64d91cfa 2316 .setup = pci_default_setup,
eb7073db
TM		 2317 },
2318 {
2319 .vendor = PCI_VENDOR_ID_INTEL,
2320 .device = 0x8812,
aaa10eb1
AP		 2321 .subvendor = PCI_ANY_ID,
2322 .subdevice = PCI_ANY_ID,
eb7073db 2323 .init = pci_eg20t_init,
64d91cfa 2324 .setup = pci_default_setup,
eb7073db
TM		 2325 },
2326 {
2327 .vendor = PCI_VENDOR_ID_INTEL,
2328 .device = 0x8813,
aaa10eb1
AP		 2329 .subvendor = PCI_ANY_ID,
2330 .subdevice = PCI_ANY_ID,
eb7073db 2331 .init = pci_eg20t_init,
64d91cfa 2332 .setup = pci_default_setup,
eb7073db
TM		 2333 },
2334 {
2335 .vendor = PCI_VENDOR_ID_INTEL,
2336 .device = 0x8814,
aaa10eb1
AP		 2337 .subvendor = PCI_ANY_ID,
2338 .subdevice = PCI_ANY_ID,
eb7073db 2339 .init = pci_eg20t_init,
64d91cfa 2340 .setup = pci_default_setup,
eb7073db
TM		 2341 },
2342 {
2343 .vendor = 0x10DB,
2344 .device = 0x8027,
aaa10eb1
AP		 2345 .subvendor = PCI_ANY_ID,
2346 .subdevice = PCI_ANY_ID,
eb7073db 2347 .init = pci_eg20t_init,
64d91cfa 2348 .setup = pci_default_setup,
eb7073db
TM		 2349 },
2350 {
2351 .vendor = 0x10DB,
2352 .device = 0x8028,
aaa10eb1
AP		 2353 .subvendor = PCI_ANY_ID,
2354 .subdevice = PCI_ANY_ID,
eb7073db 2355 .init = pci_eg20t_init,
64d91cfa 2356 .setup = pci_default_setup,
eb7073db
TM		 2357 },
2358 {
2359 .vendor = 0x10DB,
2360 .device = 0x8029,
aaa10eb1
AP		 2361 .subvendor = PCI_ANY_ID,
2362 .subdevice = PCI_ANY_ID,
eb7073db 2363 .init = pci_eg20t_init,
64d91cfa 2364 .setup = pci_default_setup,
eb7073db
TM		 2365 },
2366 {
2367 .vendor = 0x10DB,
2368 .device = 0x800C,
aaa10eb1
AP		 2369 .subvendor = PCI_ANY_ID,
2370 .subdevice = PCI_ANY_ID,
eb7073db 2371 .init = pci_eg20t_init,
64d91cfa 2372 .setup = pci_default_setup,
eb7073db
TM		 2373 },
2374 {
2375 .vendor = 0x10DB,
2376 .device = 0x800D,
aaa10eb1
AP		 2377 .subvendor = PCI_ANY_ID,
2378 .subdevice = PCI_ANY_ID,
eb7073db 2379 .init = pci_eg20t_init,
64d91cfa 2380 .setup = pci_default_setup,
eb7073db 2381 },
d9a0fbfd
AP		 2382 /*
2383 * Cronyx Omega PCI (PLX-chip based)
2384 */
2385 {
2386 .vendor = PCI_VENDOR_ID_PLX,
2387 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2388 .subvendor = PCI_ANY_ID,
2389 .subdevice = PCI_ANY_ID,
2390 .setup = pci_omegapci_setup,
eb26dfe8 2391 },
feb58142
EG		 2392 /* WCH CH353 1S1P card (16550 clone) */
2393 {
2394 .vendor = PCI_VENDOR_ID_WCH,
2395 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2396 .subvendor = PCI_ANY_ID,
2397 .subdevice = PCI_ANY_ID,
2398 .setup = pci_wch_ch353_setup,
2399 },
6971c635
GA		 2400 /* WCH CH353 2S1P card (16550 clone) */
2401 {
27788c5f
AC		 2402 .vendor = PCI_VENDOR_ID_WCH,
2403 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2404 .subvendor = PCI_ANY_ID,
2405 .subdevice = PCI_ANY_ID,
2406 .setup = pci_wch_ch353_setup,
2407 },
2408 /* WCH CH353 4S card (16550 clone) */
2409 {
2410 .vendor = PCI_VENDOR_ID_WCH,
2411 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2412 .subvendor = PCI_ANY_ID,
2413 .subdevice = PCI_ANY_ID,
2414 .setup = pci_wch_ch353_setup,
2415 },
2416 /* WCH CH353 2S1PF card (16550 clone) */
2417 {
2418 .vendor = PCI_VENDOR_ID_WCH,
2419 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2420 .subvendor = PCI_ANY_ID,
2421 .subdevice = PCI_ANY_ID,
6971c635
GA		 2422 .setup = pci_wch_ch353_setup,
2423 },
8b5c913f
WY		 2424 /* WCH CH352 2S card (16550 clone) */
2425 {
2426 .vendor = PCI_VENDOR_ID_WCH,
2427 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2428 .subvendor = PCI_ANY_ID,
2429 .subdevice = PCI_ANY_ID,
2430 .setup = pci_wch_ch353_setup,
2431 },
55c368cb
AP		 2432 /* WCH CH355 4S card (16550 clone) */
2433 {
2434 .vendor = PCI_VENDOR_ID_WCH,
2435 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2436 .subvendor = PCI_ANY_ID,
2437 .subdevice = PCI_ANY_ID,
2438 .setup = pci_wch_ch355_setup,
2439 },
7dde5578
JM		 2440 /* WCH CH382 2S card (16850 clone) */
2441 {
2442 .vendor = PCIE_VENDOR_ID_WCH,
2443 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2444 .subvendor = PCI_ANY_ID,
2445 .subdevice = PCI_ANY_ID,
2446 .setup = pci_wch_ch38x_setup,
2447 },
72a3c0e4 2448 /* WCH CH382 2S1P card (16850 clone) */
2fdd8c8c
SP		 2449 {
2450 .vendor = PCIE_VENDOR_ID_WCH,
2451 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2452 .subvendor = PCI_ANY_ID,
2453 .subdevice = PCI_ANY_ID,
72a3c0e4
SP		 2454 .setup = pci_wch_ch38x_setup,
2455 },
2456 /* WCH CH384 4S card (16850 clone) */
2457 {
2458 .vendor = PCIE_VENDOR_ID_WCH,
2459 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2460 .subvendor = PCI_ANY_ID,
2461 .subdevice = PCI_ANY_ID,
2462 .setup = pci_wch_ch38x_setup,
2fdd8c8c 2463 },
eb26dfe8
AC		 2464 /*
2465 * ASIX devices with FIFO bug
2466 */
2467 {
2468 .vendor = PCI_VENDOR_ID_ASIX,
2469 .device = PCI_ANY_ID,
2470 .subvendor = PCI_ANY_ID,
2471 .subdevice = PCI_ANY_ID,
2472 .setup = pci_asix_setup,
2473 },
14faa8cc
MS		 2474 /*
2475 * Commtech, Inc. Fastcom adapters
2476 *
2477 */
2478 {
2479 .vendor = PCI_VENDOR_ID_COMMTECH,
2480 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2481 .subvendor = PCI_ANY_ID,
2482 .subdevice = PCI_ANY_ID,
2483 .setup = pci_fastcom335_setup,
2484 },
2485 {
2486 .vendor = PCI_VENDOR_ID_COMMTECH,
2487 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2488 .subvendor = PCI_ANY_ID,
2489 .subdevice = PCI_ANY_ID,
2490 .setup = pci_fastcom335_setup,
2491 },
2492 {
2493 .vendor = PCI_VENDOR_ID_COMMTECH,
2494 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2495 .subvendor = PCI_ANY_ID,
2496 .subdevice = PCI_ANY_ID,
2497 .setup = pci_fastcom335_setup,
2498 },
2499 {
2500 .vendor = PCI_VENDOR_ID_COMMTECH,
2501 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2502 .subvendor = PCI_ANY_ID,
2503 .subdevice = PCI_ANY_ID,
2504 .setup = pci_fastcom335_setup,
2505 },
2506 {
2507 .vendor = PCI_VENDOR_ID_COMMTECH,
2508 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2509 .subvendor = PCI_ANY_ID,
2510 .subdevice = PCI_ANY_ID,
2511 .setup = pci_xr17v35x_setup,
2512 },
2513 {
2514 .vendor = PCI_VENDOR_ID_COMMTECH,
2515 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2516 .subvendor = PCI_ANY_ID,
2517 .subdevice = PCI_ANY_ID,
2518 .setup = pci_xr17v35x_setup,
2519 },
2520 {
2521 .vendor = PCI_VENDOR_ID_COMMTECH,
2522 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2523 .subvendor = PCI_ANY_ID,
2524 .subdevice = PCI_ANY_ID,
2525 .setup = pci_xr17v35x_setup,
2526 },
ebebd49a
SH		 2527 /*
2528 * Broadcom TruManage (NetXtreme)
2529 */
2530 {
2531 .vendor = PCI_VENDOR_ID_BROADCOM,
2532 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2533 .subvendor = PCI_ANY_ID,
2534 .subdevice = PCI_ANY_ID,
2535 .setup = pci_brcm_trumanage_setup,
2536 },
2c62a3c8
GKH		 2537 {
2538 .vendor = 0x1c29,
2539 .device = 0x1104,
2540 .subvendor = PCI_ANY_ID,
2541 .subdevice = PCI_ANY_ID,
2542 .setup = pci_fintek_setup,
6a8bc239 2543 .init = pci_fintek_init,
2c62a3c8
GKH		 2544 },
2545 {
2546 .vendor = 0x1c29,
2547 .device = 0x1108,
2548 .subvendor = PCI_ANY_ID,
2549 .subdevice = PCI_ANY_ID,
2550 .setup = pci_fintek_setup,
6a8bc239 2551 .init = pci_fintek_init,
2c62a3c8
GKH		 2552 },
2553 {
2554 .vendor = 0x1c29,
2555 .device = 0x1112,
2556 .subvendor = PCI_ANY_ID,
2557 .subdevice = PCI_ANY_ID,
2558 .setup = pci_fintek_setup,
6a8bc239 2559 .init = pci_fintek_init,
2c62a3c8 2560 },
ebebd49a 2561
1da177e4
LT		 2562 /*
2563 * Default "match everything" terminator entry
2564 */
2565 {
2566 .vendor = PCI_ANY_ID,
2567 .device = PCI_ANY_ID,
2568 .subvendor = PCI_ANY_ID,
2569 .subdevice = PCI_ANY_ID,
2570 .setup = pci_default_setup,
2571 }
2572};
2573
2574static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2575{
2576 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2577}
2578
2579static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2580{
2581 struct pci_serial_quirk *quirk;
2582
2583 for (quirk = pci_serial_quirks; ; quirk++)
2584 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2585 quirk_id_matches(quirk->device, dev->device) &&
2586 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2587 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2588 break;
1da177e4
LT		 2589 return quirk;
2590}
2591
dd68e88c 2592static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2593 const struct pciserial_board *board)
1da177e4
LT		 2594{
2595 if (board->flags & FL_NOIRQ)
2596 return 0;
2597 else
2598 return dev->irq;
2599}
2600
2601/*
2602 * This is the configuration table for all of the PCI serial boards
2603 * which we support. It is directly indexed by the pci_board_num_t enum
2604 * value, which is encoded in the pci_device_id PCI probe table's
2605 * driver_data member.
2606 *
2607 * The makeup of these names are:
26e92861 2608 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2609 *
26e92861
GH		 2610 * bn = PCI BAR number
2611 * bt = Index using PCI BARs
2612 * n = number of serial ports
2613 * baud = baud rate
2614 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2615 *
26e92861 2616 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2617 *
1da177e4
LT		 2618 * Please note: in theory if n = 1, _bt infix should make no difference.
2619 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2620 */
2621enum pci_board_num_t {
2622 pbn_default = 0,
2623
2624 pbn_b0_1_115200,
2625 pbn_b0_2_115200,
2626 pbn_b0_4_115200,
2627 pbn_b0_5_115200,
bf0df636 2628 pbn_b0_8_115200,
1da177e4
LT		 2629
2630 pbn_b0_1_921600,
2631 pbn_b0_2_921600,
2632 pbn_b0_4_921600,
2633
db1de159
DR		 2634 pbn_b0_2_1130000,
2635
fbc0dc0d
AP		 2636 pbn_b0_4_1152000,
2637
14faa8cc
MS		 2638 pbn_b0_2_1152000_200,
2639 pbn_b0_4_1152000_200,
2640 pbn_b0_8_1152000_200,
2641
26e92861
GH		 2642 pbn_b0_2_1843200,
2643 pbn_b0_4_1843200,
2644
2645 pbn_b0_2_1843200_200,
2646 pbn_b0_4_1843200_200,
2647 pbn_b0_8_1843200_200,
2648
7106b4e3
LH		 2649 pbn_b0_1_4000000,
2650
1da177e4
LT		 2651 pbn_b0_bt_1_115200,
2652 pbn_b0_bt_2_115200,
ac6ec5b1 2653 pbn_b0_bt_4_115200,
1da177e4
LT		 2654 pbn_b0_bt_8_115200,
2655
2656 pbn_b0_bt_1_460800,
2657 pbn_b0_bt_2_460800,
2658 pbn_b0_bt_4_460800,
2659
2660 pbn_b0_bt_1_921600,
2661 pbn_b0_bt_2_921600,
2662 pbn_b0_bt_4_921600,
2663 pbn_b0_bt_8_921600,
2664
2665 pbn_b1_1_115200,
2666 pbn_b1_2_115200,
2667 pbn_b1_4_115200,
2668 pbn_b1_8_115200,
04bf7e74 2669 pbn_b1_16_115200,
1da177e4
LT		 2670
2671 pbn_b1_1_921600,
2672 pbn_b1_2_921600,
2673 pbn_b1_4_921600,
2674 pbn_b1_8_921600,
2675
26e92861
GH		 2676 pbn_b1_2_1250000,
2677
84f8c6fc 2678 pbn_b1_bt_1_115200,
04bf7e74
WP		 2679 pbn_b1_bt_2_115200,
2680 pbn_b1_bt_4_115200,
2681
1da177e4
LT		 2682 pbn_b1_bt_2_921600,
2683
2684 pbn_b1_1_1382400,
2685 pbn_b1_2_1382400,
2686 pbn_b1_4_1382400,
2687 pbn_b1_8_1382400,
2688
2689 pbn_b2_1_115200,
737c1756 2690 pbn_b2_2_115200,
a9cccd34 2691 pbn_b2_4_115200,
1da177e4
LT		 2692 pbn_b2_8_115200,
2693
2694 pbn_b2_1_460800,
2695 pbn_b2_4_460800,
2696 pbn_b2_8_460800,
2697 pbn_b2_16_460800,
2698
2699 pbn_b2_1_921600,
2700 pbn_b2_4_921600,
2701 pbn_b2_8_921600,
2702
e847003f
LB		 2703 pbn_b2_8_1152000,
2704
1da177e4
LT		 2705 pbn_b2_bt_1_115200,
2706 pbn_b2_bt_2_115200,
2707 pbn_b2_bt_4_115200,
2708
2709 pbn_b2_bt_2_921600,
2710 pbn_b2_bt_4_921600,
2711
d9004eb4 2712 pbn_b3_2_115200,
1da177e4
LT		 2713 pbn_b3_4_115200,
2714 pbn_b3_8_115200,
2715
66169ad1
YY		 2716 pbn_b4_bt_2_921600,
2717 pbn_b4_bt_4_921600,
2718 pbn_b4_bt_8_921600,
2719
1da177e4
LT		 2720 /*
2721 * Board-specific versions.
2722 */
2723 pbn_panacom,
2724 pbn_panacom2,
2725 pbn_panacom4,
2726 pbn_plx_romulus,
1bc8cde4 2727 pbn_endrun_2_4000000,
1da177e4 2728 pbn_oxsemi,
7106b4e3
LH		 2729 pbn_oxsemi_1_4000000,
2730 pbn_oxsemi_2_4000000,
2731 pbn_oxsemi_4_4000000,
2732 pbn_oxsemi_8_4000000,
1da177e4
LT		 2733 pbn_intel_i960,
2734 pbn_sgi_ioc3,
1da177e4
LT		 2735 pbn_computone_4,
2736 pbn_computone_6,
2737 pbn_computone_8,
2738 pbn_sbsxrsio,
2739 pbn_exar_XR17C152,
2740 pbn_exar_XR17C154,
2741 pbn_exar_XR17C158,
dc96efb7
MS		 2742 pbn_exar_XR17V352,
2743 pbn_exar_XR17V354,
2744 pbn_exar_XR17V358,
be32c0cf 2745 pbn_exar_XR17V4358,
96a5d18b 2746 pbn_exar_XR17V8358,
c68d2b15 2747 pbn_exar_ibm_saturn,
aa798505 2748 pbn_pasemi_1682M,
46a0fac9
SB		 2749 pbn_ni8430_2,
2750 pbn_ni8430_4,
2751 pbn_ni8430_8,
2752 pbn_ni8430_16,
1b62cbf2
KJ		 2753 pbn_ADDIDATA_PCIe_1_3906250,
2754 pbn_ADDIDATA_PCIe_2_3906250,
2755 pbn_ADDIDATA_PCIe_4_3906250,
2756 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 2757 pbn_ce4100_1_115200,
1ede7dcc 2758 pbn_qrk,
d9a0fbfd 2759 pbn_omegapci,
7808edcd 2760 pbn_NETMOS9900_2s_115200,
ebebd49a 2761 pbn_brcm_trumanage,
2c62a3c8
GKH		 2762 pbn_fintek_4,
2763 pbn_fintek_8,
2764 pbn_fintek_12,
7dde5578 2765 pbn_wch382_2,
72a3c0e4 2766 pbn_wch384_4,
89c043a6
AL		 2767 pbn_pericom_PI7C9X7951,
2768 pbn_pericom_PI7C9X7952,
2769 pbn_pericom_PI7C9X7954,
2770 pbn_pericom_PI7C9X7958,
1da177e4
LT		 2771};
2772
2773/*
2774 * uart_offset - the space between channels
2775 * reg_shift - describes how the UART registers are mapped
2776 * to PCI memory by the card.
2777 * For example IER register on SBS, Inc. PMC-OctPro is located at
2778 * offset 0x10 from the UART base, while UART_IER is defined as 1
2779 * in include/linux/serial_reg.h,
2780 * see first lines of serial_in() and serial_out() in 8250.c
2781*/
2782
de88b340 2783static struct pciserial_board pci_boards[] = {
1da177e4
LT		 2784 [pbn_default] = {
2785 .flags = FL_BASE0,
2786 .num_ports = 1,
2787 .base_baud = 115200,
2788 .uart_offset = 8,
2789 },
2790 [pbn_b0_1_115200] = {
2791 .flags = FL_BASE0,
2792 .num_ports = 1,
2793 .base_baud = 115200,
2794 .uart_offset = 8,
2795 },
2796 [pbn_b0_2_115200] = {
2797 .flags = FL_BASE0,
2798 .num_ports = 2,
2799 .base_baud = 115200,
2800 .uart_offset = 8,
2801 },
2802 [pbn_b0_4_115200] = {
2803 .flags = FL_BASE0,
2804 .num_ports = 4,
2805 .base_baud = 115200,
2806 .uart_offset = 8,
2807 },
2808 [pbn_b0_5_115200] = {
2809 .flags = FL_BASE0,
2810 .num_ports = 5,
2811 .base_baud = 115200,
2812 .uart_offset = 8,
2813 },
bf0df636
AC		 2814 [pbn_b0_8_115200] = {
2815 .flags = FL_BASE0,
2816 .num_ports = 8,
2817 .base_baud = 115200,
2818 .uart_offset = 8,
2819 },
1da177e4
LT		 2820 [pbn_b0_1_921600] = {
2821 .flags = FL_BASE0,
2822 .num_ports = 1,
2823 .base_baud = 921600,
2824 .uart_offset = 8,
2825 },
2826 [pbn_b0_2_921600] = {
2827 .flags = FL_BASE0,
2828 .num_ports = 2,
2829 .base_baud = 921600,
2830 .uart_offset = 8,
2831 },
2832 [pbn_b0_4_921600] = {
2833 .flags = FL_BASE0,
2834 .num_ports = 4,
2835 .base_baud = 921600,
2836 .uart_offset = 8,
2837 },
db1de159
DR		 2838
2839 [pbn_b0_2_1130000] = {
2840 .flags = FL_BASE0,
2841 .num_ports = 2,
2842 .base_baud = 1130000,
2843 .uart_offset = 8,
2844 },
2845
fbc0dc0d
AP		 2846 [pbn_b0_4_1152000] = {
2847 .flags = FL_BASE0,
2848 .num_ports = 4,
2849 .base_baud = 1152000,
2850 .uart_offset = 8,
2851 },
1da177e4 2852
14faa8cc
MS		 2853 [pbn_b0_2_1152000_200] = {
2854 .flags = FL_BASE0,
2855 .num_ports = 2,
2856 .base_baud = 1152000,
2857 .uart_offset = 0x200,
2858 },
2859
2860 [pbn_b0_4_1152000_200] = {
2861 .flags = FL_BASE0,
2862 .num_ports = 4,
2863 .base_baud = 1152000,
2864 .uart_offset = 0x200,
2865 },
2866
2867 [pbn_b0_8_1152000_200] = {
2868 .flags = FL_BASE0,
4f7d67d0 2869 .num_ports = 8,
14faa8cc
MS		 2870 .base_baud = 1152000,
2871 .uart_offset = 0x200,
2872 },
2873
26e92861
GH		 2874 [pbn_b0_2_1843200] = {
2875 .flags = FL_BASE0,
2876 .num_ports = 2,
2877 .base_baud = 1843200,
2878 .uart_offset = 8,
2879 },
2880 [pbn_b0_4_1843200] = {
2881 .flags = FL_BASE0,
2882 .num_ports = 4,
2883 .base_baud = 1843200,
2884 .uart_offset = 8,
2885 },
2886
2887 [pbn_b0_2_1843200_200] = {
2888 .flags = FL_BASE0,
2889 .num_ports = 2,
2890 .base_baud = 1843200,
2891 .uart_offset = 0x200,
2892 },
2893 [pbn_b0_4_1843200_200] = {
2894 .flags = FL_BASE0,
2895 .num_ports = 4,
2896 .base_baud = 1843200,
2897 .uart_offset = 0x200,
2898 },
2899 [pbn_b0_8_1843200_200] = {
2900 .flags = FL_BASE0,
2901 .num_ports = 8,
2902 .base_baud = 1843200,
2903 .uart_offset = 0x200,
2904 },
7106b4e3
LH		 2905 [pbn_b0_1_4000000] = {
2906 .flags = FL_BASE0,
2907 .num_ports = 1,
2908 .base_baud = 4000000,
2909 .uart_offset = 8,
2910 },
26e92861 2911
1da177e4
LT		 2912 [pbn_b0_bt_1_115200] = {
2913 .flags = FL_BASE0|FL_BASE_BARS,
2914 .num_ports = 1,
2915 .base_baud = 115200,
2916 .uart_offset = 8,
2917 },
2918 [pbn_b0_bt_2_115200] = {
2919 .flags = FL_BASE0|FL_BASE_BARS,
2920 .num_ports = 2,
2921 .base_baud = 115200,
2922 .uart_offset = 8,
2923 },
ac6ec5b1
IS		 2924 [pbn_b0_bt_4_115200] = {
2925 .flags = FL_BASE0|FL_BASE_BARS,
2926 .num_ports = 4,
2927 .base_baud = 115200,
2928 .uart_offset = 8,
2929 },
1da177e4
LT		 2930 [pbn_b0_bt_8_115200] = {
2931 .flags = FL_BASE0|FL_BASE_BARS,
2932 .num_ports = 8,
2933 .base_baud = 115200,
2934 .uart_offset = 8,
2935 },
2936
2937 [pbn_b0_bt_1_460800] = {
2938 .flags = FL_BASE0|FL_BASE_BARS,
2939 .num_ports = 1,
2940 .base_baud = 460800,
2941 .uart_offset = 8,
2942 },
2943 [pbn_b0_bt_2_460800] = {
2944 .flags = FL_BASE0|FL_BASE_BARS,
2945 .num_ports = 2,
2946 .base_baud = 460800,
2947 .uart_offset = 8,
2948 },
2949 [pbn_b0_bt_4_460800] = {
2950 .flags = FL_BASE0|FL_BASE_BARS,
2951 .num_ports = 4,
2952 .base_baud = 460800,
2953 .uart_offset = 8,
2954 },
2955
2956 [pbn_b0_bt_1_921600] = {
2957 .flags = FL_BASE0|FL_BASE_BARS,
2958 .num_ports = 1,
2959 .base_baud = 921600,
2960 .uart_offset = 8,
2961 },
2962 [pbn_b0_bt_2_921600] = {
2963 .flags = FL_BASE0|FL_BASE_BARS,
2964 .num_ports = 2,
2965 .base_baud = 921600,
2966 .uart_offset = 8,
2967 },
2968 [pbn_b0_bt_4_921600] = {
2969 .flags = FL_BASE0|FL_BASE_BARS,
2970 .num_ports = 4,
2971 .base_baud = 921600,
2972 .uart_offset = 8,
2973 },
2974 [pbn_b0_bt_8_921600] = {
2975 .flags = FL_BASE0|FL_BASE_BARS,
2976 .num_ports = 8,
2977 .base_baud = 921600,
2978 .uart_offset = 8,
2979 },
2980
2981 [pbn_b1_1_115200] = {
2982 .flags = FL_BASE1,
2983 .num_ports = 1,
2984 .base_baud = 115200,
2985 .uart_offset = 8,
2986 },
2987 [pbn_b1_2_115200] = {
2988 .flags = FL_BASE1,
2989 .num_ports = 2,
2990 .base_baud = 115200,
2991 .uart_offset = 8,
2992 },
2993 [pbn_b1_4_115200] = {
2994 .flags = FL_BASE1,
2995 .num_ports = 4,
2996 .base_baud = 115200,
2997 .uart_offset = 8,
2998 },
2999 [pbn_b1_8_115200] = {
3000 .flags = FL_BASE1,
3001 .num_ports = 8,
3002 .base_baud = 115200,
3003 .uart_offset = 8,
3004 },
04bf7e74
WP		 3005 [pbn_b1_16_115200] = {
3006 .flags = FL_BASE1,
3007 .num_ports = 16,
3008 .base_baud = 115200,
3009 .uart_offset = 8,
3010 },
1da177e4
LT		 3011
3012 [pbn_b1_1_921600] = {
3013 .flags = FL_BASE1,
3014 .num_ports = 1,
3015 .base_baud = 921600,
3016 .uart_offset = 8,
3017 },
3018 [pbn_b1_2_921600] = {
3019 .flags = FL_BASE1,
3020 .num_ports = 2,
3021 .base_baud = 921600,
3022 .uart_offset = 8,
3023 },
3024 [pbn_b1_4_921600] = {
3025 .flags = FL_BASE1,
3026 .num_ports = 4,
3027 .base_baud = 921600,
3028 .uart_offset = 8,
3029 },
3030 [pbn_b1_8_921600] = {
3031 .flags = FL_BASE1,
3032 .num_ports = 8,
3033 .base_baud = 921600,
3034 .uart_offset = 8,
3035 },
26e92861
GH		 3036 [pbn_b1_2_1250000] = {
3037 .flags = FL_BASE1,
3038 .num_ports = 2,
3039 .base_baud = 1250000,
3040 .uart_offset = 8,
3041 },
1da177e4 3042
84f8c6fc
NV		 3043 [pbn_b1_bt_1_115200] = {
3044 .flags = FL_BASE1|FL_BASE_BARS,
3045 .num_ports = 1,
3046 .base_baud = 115200,
3047 .uart_offset = 8,
3048 },
04bf7e74
WP		 3049 [pbn_b1_bt_2_115200] = {
3050 .flags = FL_BASE1|FL_BASE_BARS,
3051 .num_ports = 2,
3052 .base_baud = 115200,
3053 .uart_offset = 8,
3054 },
3055 [pbn_b1_bt_4_115200] = {
3056 .flags = FL_BASE1|FL_BASE_BARS,
3057 .num_ports = 4,
3058 .base_baud = 115200,
3059 .uart_offset = 8,
3060 },
84f8c6fc 3061
1da177e4
LT		 3062 [pbn_b1_bt_2_921600] = {
3063 .flags = FL_BASE1|FL_BASE_BARS,
3064 .num_ports = 2,
3065 .base_baud = 921600,
3066 .uart_offset = 8,
3067 },
3068
3069 [pbn_b1_1_1382400] = {
3070 .flags = FL_BASE1,
3071 .num_ports = 1,
3072 .base_baud = 1382400,
3073 .uart_offset = 8,
3074 },
3075 [pbn_b1_2_1382400] = {
3076 .flags = FL_BASE1,
3077 .num_ports = 2,
3078 .base_baud = 1382400,
3079 .uart_offset = 8,
3080 },
3081 [pbn_b1_4_1382400] = {
3082 .flags = FL_BASE1,
3083 .num_ports = 4,
3084 .base_baud = 1382400,
3085 .uart_offset = 8,
3086 },
3087 [pbn_b1_8_1382400] = {
3088 .flags = FL_BASE1,
3089 .num_ports = 8,
3090 .base_baud = 1382400,
3091 .uart_offset = 8,
3092 },
3093
3094 [pbn_b2_1_115200] = {
3095 .flags = FL_BASE2,
3096 .num_ports = 1,
3097 .base_baud = 115200,
3098 .uart_offset = 8,
3099 },
737c1756
PH		 3100 [pbn_b2_2_115200] = {
3101 .flags = FL_BASE2,
3102 .num_ports = 2,
3103 .base_baud = 115200,
3104 .uart_offset = 8,
3105 },
a9cccd34
MF		 3106 [pbn_b2_4_115200] = {
3107 .flags = FL_BASE2,
3108 .num_ports = 4,
3109 .base_baud = 115200,
3110 .uart_offset = 8,
3111 },
1da177e4
LT		 3112 [pbn_b2_8_115200] = {
3113 .flags = FL_BASE2,
3114 .num_ports = 8,
3115 .base_baud = 115200,
3116 .uart_offset = 8,
3117 },
3118
3119 [pbn_b2_1_460800] = {
3120 .flags = FL_BASE2,
3121 .num_ports = 1,
3122 .base_baud = 460800,
3123 .uart_offset = 8,
3124 },
3125 [pbn_b2_4_460800] = {
3126 .flags = FL_BASE2,
3127 .num_ports = 4,
3128 .base_baud = 460800,
3129 .uart_offset = 8,
3130 },
3131 [pbn_b2_8_460800] = {
3132 .flags = FL_BASE2,
3133 .num_ports = 8,
3134 .base_baud = 460800,
3135 .uart_offset = 8,
3136 },
3137 [pbn_b2_16_460800] = {
3138 .flags = FL_BASE2,
3139 .num_ports = 16,
3140 .base_baud = 460800,
3141 .uart_offset = 8,
3142 },
3143
3144 [pbn_b2_1_921600] = {
3145 .flags = FL_BASE2,
3146 .num_ports = 1,
3147 .base_baud = 921600,
3148 .uart_offset = 8,
3149 },
3150 [pbn_b2_4_921600] = {
3151 .flags = FL_BASE2,
3152 .num_ports = 4,
3153 .base_baud = 921600,
3154 .uart_offset = 8,
3155 },
3156 [pbn_b2_8_921600] = {
3157 .flags = FL_BASE2,
3158 .num_ports = 8,
3159 .base_baud = 921600,
3160 .uart_offset = 8,
3161 },
3162
e847003f
LB		 3163 [pbn_b2_8_1152000] = {
3164 .flags = FL_BASE2,
3165 .num_ports = 8,
3166 .base_baud = 1152000,
3167 .uart_offset = 8,
3168 },
3169
1da177e4
LT		 3170 [pbn_b2_bt_1_115200] = {
3171 .flags = FL_BASE2|FL_BASE_BARS,
3172 .num_ports = 1,
3173 .base_baud = 115200,
3174 .uart_offset = 8,
3175 },
3176 [pbn_b2_bt_2_115200] = {
3177 .flags = FL_BASE2|FL_BASE_BARS,
3178 .num_ports = 2,
3179 .base_baud = 115200,
3180 .uart_offset = 8,
3181 },
3182 [pbn_b2_bt_4_115200] = {
3183 .flags = FL_BASE2|FL_BASE_BARS,
3184 .num_ports = 4,
3185 .base_baud = 115200,
3186 .uart_offset = 8,
3187 },
3188
3189 [pbn_b2_bt_2_921600] = {
3190 .flags = FL_BASE2|FL_BASE_BARS,
3191 .num_ports = 2,
3192 .base_baud = 921600,
3193 .uart_offset = 8,
3194 },
3195 [pbn_b2_bt_4_921600] = {
3196 .flags = FL_BASE2|FL_BASE_BARS,
3197 .num_ports = 4,
3198 .base_baud = 921600,
3199 .uart_offset = 8,
3200 },
3201
d9004eb4
ABL		 3202 [pbn_b3_2_115200] = {
3203 .flags = FL_BASE3,
3204 .num_ports = 2,
3205 .base_baud = 115200,
3206 .uart_offset = 8,
3207 },
1da177e4
LT		 3208 [pbn_b3_4_115200] = {
3209 .flags = FL_BASE3,
3210 .num_ports = 4,
3211 .base_baud = 115200,
3212 .uart_offset = 8,
3213 },
3214 [pbn_b3_8_115200] = {
3215 .flags = FL_BASE3,
3216 .num_ports = 8,
3217 .base_baud = 115200,
3218 .uart_offset = 8,
3219 },
3220
66169ad1
YY		 3221 [pbn_b4_bt_2_921600] = {
3222 .flags = FL_BASE4,
3223 .num_ports = 2,
3224 .base_baud = 921600,
3225 .uart_offset = 8,
3226 },
3227 [pbn_b4_bt_4_921600] = {
3228 .flags = FL_BASE4,
3229 .num_ports = 4,
3230 .base_baud = 921600,
3231 .uart_offset = 8,
3232 },
3233 [pbn_b4_bt_8_921600] = {
3234 .flags = FL_BASE4,
3235 .num_ports = 8,
3236 .base_baud = 921600,
3237 .uart_offset = 8,
3238 },
3239
1da177e4
LT		 3240 /*
3241 * Entries following this are board-specific.
3242 */
3243
3244 /*
3245 * Panacom - IOMEM
3246 */
3247 [pbn_panacom] = {
3248 .flags = FL_BASE2,
3249 .num_ports = 2,
3250 .base_baud = 921600,
3251 .uart_offset = 0x400,
3252 .reg_shift = 7,
3253 },
3254 [pbn_panacom2] = {
3255 .flags = FL_BASE2|FL_BASE_BARS,
3256 .num_ports = 2,
3257 .base_baud = 921600,
3258 .uart_offset = 0x400,
3259 .reg_shift = 7,
3260 },
3261 [pbn_panacom4] = {
3262 .flags = FL_BASE2|FL_BASE_BARS,
3263 .num_ports = 4,
3264 .base_baud = 921600,
3265 .uart_offset = 0x400,
3266 .reg_shift = 7,
3267 },
3268
3269 /* I think this entry is broken - the first_offset looks wrong --rmk */
3270 [pbn_plx_romulus] = {
3271 .flags = FL_BASE2,
3272 .num_ports = 4,
3273 .base_baud = 921600,
3274 .uart_offset = 8 << 2,
3275 .reg_shift = 2,
3276 .first_offset = 0x03,
3277 },
3278
1bc8cde4
MS		 3279 /*
3280 * EndRun Technologies
3281 * Uses the size of PCI Base region 0 to
3282 * signal now many ports are available
3283 * 2 port 952 Uart support
3284 */
3285 [pbn_endrun_2_4000000] = {
3286 .flags = FL_BASE0,
3287 .num_ports = 2,
3288 .base_baud = 4000000,
3289 .uart_offset = 0x200,
3290 .first_offset = 0x1000,
3291 },
3292
1da177e4
LT		 3293 /*
3294 * This board uses the size of PCI Base region 0 to
3295 * signal now many ports are available
3296 */
3297 [pbn_oxsemi] = {
3298 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3299 .num_ports = 32,
3300 .base_baud = 115200,
3301 .uart_offset = 8,
3302 },
7106b4e3
LH		 3303 [pbn_oxsemi_1_4000000] = {
3304 .flags = FL_BASE0,
3305 .num_ports = 1,
3306 .base_baud = 4000000,
3307 .uart_offset = 0x200,
3308 .first_offset = 0x1000,
3309 },
3310 [pbn_oxsemi_2_4000000] = {
3311 .flags = FL_BASE0,
3312 .num_ports = 2,
3313 .base_baud = 4000000,
3314 .uart_offset = 0x200,
3315 .first_offset = 0x1000,
3316 },
3317 [pbn_oxsemi_4_4000000] = {
3318 .flags = FL_BASE0,
3319 .num_ports = 4,
3320 .base_baud = 4000000,
3321 .uart_offset = 0x200,
3322 .first_offset = 0x1000,
3323 },
3324 [pbn_oxsemi_8_4000000] = {
3325 .flags = FL_BASE0,
3326 .num_ports = 8,
3327 .base_baud = 4000000,
3328 .uart_offset = 0x200,
3329 .first_offset = 0x1000,
3330 },
3331
1da177e4
LT		 3332
3333 /*
3334 * EKF addition for i960 Boards form EKF with serial port.
3335 * Max 256 ports.
3336 */
3337 [pbn_intel_i960] = {
3338 .flags = FL_BASE0,
3339 .num_ports = 32,
3340 .base_baud = 921600,
3341 .uart_offset = 8 << 2,
3342 .reg_shift = 2,
3343 .first_offset = 0x10000,
3344 },
3345 [pbn_sgi_ioc3] = {
3346 .flags = FL_BASE0|FL_NOIRQ,
3347 .num_ports = 1,
3348 .base_baud = 458333,
3349 .uart_offset = 8,
3350 .reg_shift = 0,
3351 .first_offset = 0x20178,
3352 },
3353
1da177e4
LT		 3354 /*
3355 * Computone - uses IOMEM.
3356 */
3357 [pbn_computone_4] = {
3358 .flags = FL_BASE0,
3359 .num_ports = 4,
3360 .base_baud = 921600,
3361 .uart_offset = 0x40,
3362 .reg_shift = 2,
3363 .first_offset = 0x200,
3364 },
3365 [pbn_computone_6] = {
3366 .flags = FL_BASE0,
3367 .num_ports = 6,
3368 .base_baud = 921600,
3369 .uart_offset = 0x40,
3370 .reg_shift = 2,
3371 .first_offset = 0x200,
3372 },
3373 [pbn_computone_8] = {
3374 .flags = FL_BASE0,
3375 .num_ports = 8,
3376 .base_baud = 921600,
3377 .uart_offset = 0x40,
3378 .reg_shift = 2,
3379 .first_offset = 0x200,
3380 },
3381 [pbn_sbsxrsio] = {
3382 .flags = FL_BASE0,
3383 .num_ports = 8,
3384 .base_baud = 460800,
3385 .uart_offset = 256,
3386 .reg_shift = 4,
3387 },
3388 /*
3389 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3390 * Only basic 16550A support.
3391 * XR17C15[24] are not tested, but they should work.
3392 */
3393 [pbn_exar_XR17C152] = {
3394 .flags = FL_BASE0,
3395 .num_ports = 2,
3396 .base_baud = 921600,
3397 .uart_offset = 0x200,
3398 },
3399 [pbn_exar_XR17C154] = {
3400 .flags = FL_BASE0,
3401 .num_ports = 4,
3402 .base_baud = 921600,
3403 .uart_offset = 0x200,
3404 },
3405 [pbn_exar_XR17C158] = {
3406 .flags = FL_BASE0,
3407 .num_ports = 8,
3408 .base_baud = 921600,
3409 .uart_offset = 0x200,
3410 },
dc96efb7
MS		 3411 [pbn_exar_XR17V352] = {
3412 .flags = FL_BASE0,
3413 .num_ports = 2,
3414 .base_baud = 7812500,
3415 .uart_offset = 0x400,
3416 .reg_shift = 0,
3417 .first_offset = 0,
3418 },
3419 [pbn_exar_XR17V354] = {
3420 .flags = FL_BASE0,
3421 .num_ports = 4,
3422 .base_baud = 7812500,
3423 .uart_offset = 0x400,
3424 .reg_shift = 0,
3425 .first_offset = 0,
3426 },
3427 [pbn_exar_XR17V358] = {
3428 .flags = FL_BASE0,
3429 .num_ports = 8,
3430 .base_baud = 7812500,
3431 .uart_offset = 0x400,
3432 .reg_shift = 0,
3433 .first_offset = 0,
3434 },
be32c0cf
SG		 3435 [pbn_exar_XR17V4358] = {
3436 .flags = FL_BASE0,
3437 .num_ports = 12,
3438 .base_baud = 7812500,
3439 .uart_offset = 0x400,
3440 .reg_shift = 0,
3441 .first_offset = 0,
3442 },
96a5d18b
SG		 3443 [pbn_exar_XR17V8358] = {
3444 .flags = FL_BASE0,
3445 .num_ports = 16,
3446 .base_baud = 7812500,
3447 .uart_offset = 0x400,
3448 .reg_shift = 0,
3449 .first_offset = 0,
3450 },
c68d2b15
BH		 3451 [pbn_exar_ibm_saturn] = {
3452 .flags = FL_BASE0,
3453 .num_ports = 1,
3454 .base_baud = 921600,
3455 .uart_offset = 0x200,
3456 },
3457
aa798505
OJ		 3458 /*
3459 * PA Semi PWRficient PA6T-1682M on-chip UART
3460 */
3461 [pbn_pasemi_1682M] = {
3462 .flags = FL_BASE0,
3463 .num_ports = 1,
3464 .base_baud = 8333333,
3465 },
46a0fac9
SB		 3466 /*
3467 * National Instruments 843x
3468 */
3469 [pbn_ni8430_16] = {
3470 .flags = FL_BASE0,
3471 .num_ports = 16,
3472 .base_baud = 3686400,
3473 .uart_offset = 0x10,
3474 .first_offset = 0x800,
3475 },
3476 [pbn_ni8430_8] = {
3477 .flags = FL_BASE0,
3478 .num_ports = 8,
3479 .base_baud = 3686400,
3480 .uart_offset = 0x10,
3481 .first_offset = 0x800,
3482 },
3483 [pbn_ni8430_4] = {
3484 .flags = FL_BASE0,
3485 .num_ports = 4,
3486 .base_baud = 3686400,
3487 .uart_offset = 0x10,
3488 .first_offset = 0x800,
3489 },
3490 [pbn_ni8430_2] = {
3491 .flags = FL_BASE0,
3492 .num_ports = 2,
3493 .base_baud = 3686400,
3494 .uart_offset = 0x10,
3495 .first_offset = 0x800,
3496 },
1b62cbf2
KJ		 3497 /*
3498 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3499 */
3500 [pbn_ADDIDATA_PCIe_1_3906250] = {
3501 .flags = FL_BASE0,
3502 .num_ports = 1,
3503 .base_baud = 3906250,
3504 .uart_offset = 0x200,
3505 .first_offset = 0x1000,
3506 },
3507 [pbn_ADDIDATA_PCIe_2_3906250] = {
3508 .flags = FL_BASE0,
3509 .num_ports = 2,
3510 .base_baud = 3906250,
3511 .uart_offset = 0x200,
3512 .first_offset = 0x1000,
3513 },
3514 [pbn_ADDIDATA_PCIe_4_3906250] = {
3515 .flags = FL_BASE0,
3516 .num_ports = 4,
3517 .base_baud = 3906250,
3518 .uart_offset = 0x200,
3519 .first_offset = 0x1000,
3520 },
3521 [pbn_ADDIDATA_PCIe_8_3906250] = {
3522 .flags = FL_BASE0,
3523 .num_ports = 8,
3524 .base_baud = 3906250,
3525 .uart_offset = 0x200,
3526 .first_offset = 0x1000,
3527 },
095e24b0 3528 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3529 .flags = FL_BASE_BARS,
3530 .num_ports = 2,
095e24b0
DB		 3531 .base_baud = 921600,
3532 .reg_shift = 2,
3533 },
1ede7dcc
BD		 3534 [pbn_qrk] = {
3535 .flags = FL_BASE0,
3536 .num_ports = 1,
3537 .base_baud = 2764800,
3538 .reg_shift = 2,
3539 },
d9a0fbfd
AP		 3540 [pbn_omegapci] = {
3541 .flags = FL_BASE0,
3542 .num_ports = 8,
3543 .base_baud = 115200,
3544 .uart_offset = 0x200,
3545 },
7808edcd
NG		 3546 [pbn_NETMOS9900_2s_115200] = {
3547 .flags = FL_BASE0,
3548 .num_ports = 2,
3549 .base_baud = 115200,
3550 },
ebebd49a
SH		 3551 [pbn_brcm_trumanage] = {
3552 .flags = FL_BASE0,
3553 .num_ports = 1,
3554 .reg_shift = 2,
3555 .base_baud = 115200,
3556 },
2c62a3c8
GKH		 3557 [pbn_fintek_4] = {
3558 .num_ports = 4,
3559 .uart_offset = 8,
3560 .base_baud = 115200,
3561 .first_offset = 0x40,
3562 },
3563 [pbn_fintek_8] = {
3564 .num_ports = 8,
3565 .uart_offset = 8,
3566 .base_baud = 115200,
3567 .first_offset = 0x40,
3568 },
3569 [pbn_fintek_12] = {
3570 .num_ports = 12,
3571 .uart_offset = 8,
3572 .base_baud = 115200,
3573 .first_offset = 0x40,
3574 },
7dde5578
JM		 3575 [pbn_wch382_2] = {
3576 .flags = FL_BASE0,
3577 .num_ports = 2,
3578 .base_baud = 115200,
3579 .uart_offset = 8,
3580 .first_offset = 0xC0,
3581 },
72a3c0e4
SP		 3582 [pbn_wch384_4] = {
3583 .flags = FL_BASE0,
3584 .num_ports = 4,
3585 .base_baud = 115200,
3586 .uart_offset = 8,
3587 .first_offset = 0xC0,
3588 },
89c043a6
AL		 3589 /*
3590 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3591 */
3592 [pbn_pericom_PI7C9X7951] = {
3593 .flags = FL_BASE0,
3594 .num_ports = 1,
3595 .base_baud = 921600,
3596 .uart_offset = 0x8,
3597 },
3598 [pbn_pericom_PI7C9X7952] = {
3599 .flags = FL_BASE0,
3600 .num_ports = 2,
3601 .base_baud = 921600,
3602 .uart_offset = 0x8,
3603 },
3604 [pbn_pericom_PI7C9X7954] = {
3605 .flags = FL_BASE0,
3606 .num_ports = 4,
3607 .base_baud = 921600,
3608 .uart_offset = 0x8,
3609 },
3610 [pbn_pericom_PI7C9X7958] = {
3611 .flags = FL_BASE0,
3612 .num_ports = 8,
3613 .base_baud = 921600,
3614 .uart_offset = 0x8,
3615 },
1da177e4
LT		 3616};
3617
6971c635
GA		 3618static const struct pci_device_id blacklist[] = {
3619 /* softmodems */
5756ee99 3620 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3621 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3622 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3623
3624 /* multi-io cards handled by parport_serial */
3625 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
feb58142 3626 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
55c368cb 3627 { PCI_DEVICE(0x4348, 0x7173), }, /* WCH CH355 4S */
2fdd8c8c 3628 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
72a3c0e4 3629 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
d9eda9ba 3630
c216c4ad
MO		 3631 /* Moxa Smartio MUE boards handled by 8250_moxa */
3632 { PCI_VDEVICE(MOXA, 0x1024), },
3633 { PCI_VDEVICE(MOXA, 0x1025), },
3634 { PCI_VDEVICE(MOXA, 0x1045), },
3635 { PCI_VDEVICE(MOXA, 0x1144), },
3636 { PCI_VDEVICE(MOXA, 0x1160), },
3637 { PCI_VDEVICE(MOXA, 0x1161), },
3638 { PCI_VDEVICE(MOXA, 0x1182), },
3639 { PCI_VDEVICE(MOXA, 0x1183), },
3640 { PCI_VDEVICE(MOXA, 0x1322), },
3641 { PCI_VDEVICE(MOXA, 0x1342), },
3642 { PCI_VDEVICE(MOXA, 0x1381), },
3643 { PCI_VDEVICE(MOXA, 0x1683), },
3644
d9eda9ba
HK		 3645 /* Intel platforms with MID UART */
3646 { PCI_VDEVICE(INTEL, 0x081b), },
3647 { PCI_VDEVICE(INTEL, 0x081c), },
3648 { PCI_VDEVICE(INTEL, 0x081d), },
3649 { PCI_VDEVICE(INTEL, 0x1191), },
6ede6dcd 3650 { PCI_VDEVICE(INTEL, 0x19d8), },
a13e19cf
AS		 3651
3652 /* Intel platforms with DesignWare UART */
3653 { PCI_VDEVICE(INTEL, 0x0f0a), },
3654 { PCI_VDEVICE(INTEL, 0x0f0c), },
3655 { PCI_VDEVICE(INTEL, 0x228a), },
3656 { PCI_VDEVICE(INTEL, 0x228c), },
3657 { PCI_VDEVICE(INTEL, 0x9ce3), },
3658 { PCI_VDEVICE(INTEL, 0x9ce4), },
436bbd43
CS		 3659};
3660
1da177e4
LT		 3661/*
3662 * Given a complete unknown PCI device, try to use some heuristics to
3663 * guess what the configuration might be, based on the pitiful PCI
3664 * serial specs. Returns 0 on success, 1 on failure.
3665 */
9671f099 3666static int
1c7c1fe5 3667serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 3668{
6971c635 3669 const struct pci_device_id *bldev;
1da177e4 3670 int num_iomem, num_port, first_port = -1, i;
5756ee99 3671
1da177e4
LT		 3672 /*
3673 * If it is not a communications device or the programming
3674 * interface is greater than 6, give up.
3675 *
3676 * (Should we try to make guesses for multiport serial devices
5756ee99 3677 * later?)
1da177e4
LT		 3678 */
3679 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3680 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3681 (dev->class & 0xff) > 6)
3682 return -ENODEV;
3683
436bbd43
CS		 3684 /*
3685 * Do not access blacklisted devices that are known not to
6971c635 3686 * feature serial ports or are handled by other modules.
436bbd43 3687 */
6971c635
GA		 3688 for (bldev = blacklist;
3689 bldev < blacklist + ARRAY_SIZE(blacklist);
3690 bldev++) {
3691 if (dev->vendor == bldev->vendor &&
3692 dev->device == bldev->device)
436bbd43
CS		 3693 return -ENODEV;
3694 }
3695
1da177e4
LT		 3696 num_iomem = num_port = 0;
3697 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3698 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3699 num_port++;
3700 if (first_port == -1)
3701 first_port = i;
3702 }
3703 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3704 num_iomem++;
3705 }
3706
3707 /*
3708 * If there is 1 or 0 iomem regions, and exactly one port,
3709 * use it. We guess the number of ports based on the IO
3710 * region size.
3711 */
3712 if (num_iomem <= 1 && num_port == 1) {
3713 board->flags = first_port;
3714 board->num_ports = pci_resource_len(dev, first_port) / 8;
3715 return 0;
3716 }
3717
3718 /*
3719 * Now guess if we've got a board which indexes by BARs.
3720 * Each IO BAR should be 8 bytes, and they should follow
3721 * consecutively.
3722 */
3723 first_port = -1;
3724 num_port = 0;
3725 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3726 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3727 pci_resource_len(dev, i) == 8 &&
3728 (first_port == -1 || (first_port + num_port) == i)) {
3729 num_port++;
3730 if (first_port == -1)
3731 first_port = i;
3732 }
3733 }
3734
3735 if (num_port > 1) {
3736 board->flags = first_port | FL_BASE_BARS;
3737 board->num_ports = num_port;
3738 return 0;
3739 }
3740
3741 return -ENODEV;
3742}
3743
3744static inline int
975a1a7d
RK		 3745serial_pci_matches(const struct pciserial_board *board,
3746 const struct pciserial_board *guessed)
1da177e4
LT		 3747{
3748 return
3749 board->num_ports == guessed->num_ports &&
3750 board->base_baud == guessed->base_baud &&
3751 board->uart_offset == guessed->uart_offset &&
3752 board->reg_shift == guessed->reg_shift &&
3753 board->first_offset == guessed->first_offset;
3754}
3755
241fc436 3756struct serial_private *
975a1a7d 3757pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 3758{
2655a2c7 3759 struct uart_8250_port uart;
1da177e4 3760 struct serial_private *priv;
1da177e4
LT		 3761 struct pci_serial_quirk *quirk;
3762 int rc, nr_ports, i;
3763
1da177e4
LT		 3764 nr_ports = board->num_ports;
3765
3766 /*
3767 * Find an init and setup quirks.
3768 */
3769 quirk = find_quirk(dev);
3770
3771 /*
3772 * Run the new-style initialization function.
3773 * The initialization function returns:
3774 * <0 - error
3775 * 0 - use board->num_ports
3776 * >0 - number of ports
3777 */
3778 if (quirk->init) {
3779 rc = quirk->init(dev);
241fc436
RK		 3780 if (rc < 0) {
3781 priv = ERR_PTR(rc);
3782 goto err_out;
3783 }
1da177e4
LT		 3784 if (rc)
3785 nr_ports = rc;
3786 }
3787
8f31bb39 3788 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 3789 sizeof(unsigned int) * nr_ports,
3790 GFP_KERNEL);
3791 if (!priv) {
241fc436
RK		 3792 priv = ERR_PTR(-ENOMEM);
3793 goto err_deinit;
1da177e4
LT		 3794 }
3795
70db3d91 3796 priv->dev = dev;
1da177e4 3797 priv->quirk = quirk;
1da177e4 3798
2655a2c7
AC		 3799 memset(&uart, 0, sizeof(uart));
3800 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3801 uart.port.uartclk = board->base_baud * 16;
3802 uart.port.irq = get_pci_irq(dev, board);
3803 uart.port.dev = &dev->dev;
72ce9a83 3804
1da177e4 3805 for (i = 0; i < nr_ports; i++) {
2655a2c7 3806 if (quirk->setup(priv, board, &uart, i))
1da177e4 3807 break;
72ce9a83 3808
af8c5b8d
GKH		 3809 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3810 uart.port.iobase, uart.port.irq, uart.port.iotype);
5756ee99 3811
2655a2c7 3812 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4 3813 if (priv->line[i] < 0) {
af8c5b8d
GKH		 3814 dev_err(&dev->dev,
3815 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3816 uart.port.iobase, uart.port.irq,
3817 uart.port.iotype, priv->line[i]);
1da177e4
LT		 3818 break;
3819 }
3820 }
1da177e4 3821 priv->nr = i;
241fc436 3822 return priv;
1da177e4 3823
5756ee99 3824err_deinit:
1da177e4
LT		 3825 if (quirk->exit)
3826 quirk->exit(dev);
5756ee99 3827err_out:
241fc436 3828 return priv;
1da177e4 3829}
241fc436 3830EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 3831
241fc436 3832void pciserial_remove_ports(struct serial_private *priv)
1da177e4 3833{
056a8763
RK		 3834 struct pci_serial_quirk *quirk;
3835 int i;
1da177e4 3836
056a8763
RK		 3837 for (i = 0; i < priv->nr; i++)
3838 serial8250_unregister_port(priv->line[i]);
1da177e4 3839
056a8763
RK		 3840 /*
3841 * Find the exit quirks.
3842 */
241fc436 3843 quirk = find_quirk(priv->dev);
056a8763 3844 if (quirk->exit)
241fc436
RK		 3845 quirk->exit(priv->dev);
3846
3847 kfree(priv);
3848}
3849EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3850
3851void pciserial_suspend_ports(struct serial_private *priv)
3852{
3853 int i;
3854
3855 for (i = 0; i < priv->nr; i++)
3856 if (priv->line[i] >= 0)
3857 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 3858
3859 /*
3860 * Ensure that every init quirk is properly torn down
3861 */
3862 if (priv->quirk->exit)
3863 priv->quirk->exit(priv->dev);
241fc436
RK		 3864}
3865EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3866
3867void pciserial_resume_ports(struct serial_private *priv)
3868{
3869 int i;
3870
3871 /*
3872 * Ensure that the board is correctly configured.
3873 */
3874 if (priv->quirk->init)
3875 priv->quirk->init(priv->dev);
3876
3877 for (i = 0; i < priv->nr; i++)
3878 if (priv->line[i] >= 0)
3879 serial8250_resume_port(priv->line[i]);
3880}
3881EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3882
3883/*
3884 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3885 * to the arrangement of serial ports on a PCI card.
3886 */
9671f099 3887static int
241fc436
RK		 3888pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3889{
5bf8f501 3890 struct pci_serial_quirk *quirk;
241fc436 3891 struct serial_private *priv;
975a1a7d
RK		 3892 const struct pciserial_board *board;
3893 struct pciserial_board tmp;
241fc436
RK		 3894 int rc;
3895
5bf8f501
FB		 3896 quirk = find_quirk(dev);
3897 if (quirk->probe) {
3898 rc = quirk->probe(dev);
3899 if (rc)
3900 return rc;
3901 }
3902
241fc436 3903 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
af8c5b8d 3904 dev_err(&dev->dev, "invalid driver_data: %ld\n",
241fc436
RK		 3905 ent->driver_data);
3906 return -EINVAL;
3907 }
3908
3909 board = &pci_boards[ent->driver_data];
3910
3f64b1d3 3911 rc = pcim_enable_device(dev);
2807190b 3912 pci_save_state(dev);
241fc436
RK		 3913 if (rc)
3914 return rc;
3915
3916 if (ent->driver_data == pbn_default) {
3917 /*
3918 * Use a copy of the pci_board entry for this;
3919 * avoid changing entries in the table.
3920 */
3921 memcpy(&tmp, board, sizeof(struct pciserial_board));
3922 board = &tmp;
3923
3924 /*
3925 * We matched one of our class entries. Try to
3926 * determine the parameters of this board.
3927 */
975a1a7d 3928 rc = serial_pci_guess_board(dev, &tmp);
241fc436 3929 if (rc)
3f64b1d3 3930 return rc;
241fc436
RK		 3931 } else {
3932 /*
3933 * We matched an explicit entry. If we are able to
3934 * detect this boards settings with our heuristic,
3935 * then we no longer need this entry.
3936 */
3937 memcpy(&tmp, &pci_boards[pbn_default],
3938 sizeof(struct pciserial_board));
3939 rc = serial_pci_guess_board(dev, &tmp);
3940 if (rc == 0 && serial_pci_matches(board, &tmp))
3941 moan_device("Redundant entry in serial pci_table.",
3942 dev);
3943 }
3944
3945 priv = pciserial_init_ports(dev, board);
3f64b1d3
AS		 3946 if (IS_ERR(priv))
3947 return PTR_ERR(priv);
1da177e4 3948
3f64b1d3
AS		 3949 pci_set_drvdata(dev, priv);
3950 return 0;
241fc436 3951}
1da177e4 3952
ae8d8a14 3953static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 3954{
3955 struct serial_private *priv = pci_get_drvdata(dev);
3956
241fc436 3957 pciserial_remove_ports(priv);
1da177e4
LT		 3958}
3959
61702c3e
AS		 3960#ifdef CONFIG_PM_SLEEP
3961static int pciserial_suspend_one(struct device *dev)
1da177e4 3962{
61702c3e
AS		 3963 struct pci_dev *pdev = to_pci_dev(dev);
3964 struct serial_private *priv = pci_get_drvdata(pdev);
1da177e4 3965
241fc436
RK		 3966 if (priv)
3967 pciserial_suspend_ports(priv);
1da177e4 3968
1da177e4
LT		 3969 return 0;
3970}
3971
61702c3e 3972static int pciserial_resume_one(struct device *dev)
1da177e4 3973{
61702c3e
AS		 3974 struct pci_dev *pdev = to_pci_dev(dev);
3975 struct serial_private *priv = pci_get_drvdata(pdev);
ccb9d59e 3976 int err;
1da177e4
LT		 3977
3978 if (priv) {
1da177e4
LT		 3979 /*
3980 * The device may have been disabled. Re-enable it.
3981 */
61702c3e 3982 err = pci_enable_device(pdev);
40836c48 3983 /* FIXME: We cannot simply error out here */
ccb9d59e 3984 if (err)
61702c3e 3985 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
241fc436 3986 pciserial_resume_ports(priv);
1da177e4
LT		 3987 }
3988 return 0;
3989}
1d5e7996 3990#endif
1da177e4 3991
61702c3e
AS		 3992static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
3993 pciserial_resume_one);
3994
1da177e4 3995static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 3996 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3997 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3998 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3999 pbn_b2_8_921600 },
0c6d774c
TW		 4000 /* Advantech also use 0x3618 and 0xf618 */
4001 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4002 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4003 pbn_b0_4_921600 },
4004 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4005 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4006 pbn_b0_4_921600 },
1da177e4
LT		 4007 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4008 PCI_SUBVENDOR_ID_CONNECT_TECH,
4009 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4010 pbn_b1_8_1382400 },
4011 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4012 PCI_SUBVENDOR_ID_CONNECT_TECH,
4013 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4014 pbn_b1_4_1382400 },
4015 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4016 PCI_SUBVENDOR_ID_CONNECT_TECH,
4017 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4018 pbn_b1_2_1382400 },
4019 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4020 PCI_SUBVENDOR_ID_CONNECT_TECH,
4021 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4022 pbn_b1_8_1382400 },
4023 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4024 PCI_SUBVENDOR_ID_CONNECT_TECH,
4025 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4026 pbn_b1_4_1382400 },
4027 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4028 PCI_SUBVENDOR_ID_CONNECT_TECH,
4029 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4030 pbn_b1_2_1382400 },
4031 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4032 PCI_SUBVENDOR_ID_CONNECT_TECH,
4033 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4034 pbn_b1_8_921600 },
4035 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4036 PCI_SUBVENDOR_ID_CONNECT_TECH,
4037 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4038 pbn_b1_8_921600 },
4039 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4040 PCI_SUBVENDOR_ID_CONNECT_TECH,
4041 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4042 pbn_b1_4_921600 },
4043 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4044 PCI_SUBVENDOR_ID_CONNECT_TECH,
4045 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4046 pbn_b1_4_921600 },
4047 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4048 PCI_SUBVENDOR_ID_CONNECT_TECH,
4049 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4050 pbn_b1_2_921600 },
4051 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4052 PCI_SUBVENDOR_ID_CONNECT_TECH,
4053 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4054 pbn_b1_8_921600 },
4055 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4056 PCI_SUBVENDOR_ID_CONNECT_TECH,
4057 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4058 pbn_b1_8_921600 },
4059 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4060 PCI_SUBVENDOR_ID_CONNECT_TECH,
4061 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4062 pbn_b1_4_921600 },
26e92861
GH		 4063 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4064 PCI_SUBVENDOR_ID_CONNECT_TECH,
4065 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4066 pbn_b1_2_1250000 },
4067 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4068 PCI_SUBVENDOR_ID_CONNECT_TECH,
4069 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4070 pbn_b0_2_1843200 },
4071 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4072 PCI_SUBVENDOR_ID_CONNECT_TECH,
4073 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4074 pbn_b0_4_1843200 },
85d1494e
YY		 4075 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4076 PCI_VENDOR_ID_AFAVLAB,
4077 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4078 pbn_b0_4_1152000 },
26e92861
GH		 4079 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4080 PCI_SUBVENDOR_ID_CONNECT_TECH,
4081 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4082 pbn_b0_2_1843200_200 },
4083 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4084 PCI_SUBVENDOR_ID_CONNECT_TECH,
4085 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4086 pbn_b0_4_1843200_200 },
4087 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4088 PCI_SUBVENDOR_ID_CONNECT_TECH,
4089 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4090 pbn_b0_8_1843200_200 },
4091 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4092 PCI_SUBVENDOR_ID_CONNECT_TECH,
4093 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4094 pbn_b0_2_1843200_200 },
4095 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4096 PCI_SUBVENDOR_ID_CONNECT_TECH,
4097 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4098 pbn_b0_4_1843200_200 },
4099 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4100 PCI_SUBVENDOR_ID_CONNECT_TECH,
4101 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4102 pbn_b0_8_1843200_200 },
4103 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4104 PCI_SUBVENDOR_ID_CONNECT_TECH,
4105 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4106 pbn_b0_2_1843200_200 },
4107 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4108 PCI_SUBVENDOR_ID_CONNECT_TECH,
4109 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4110 pbn_b0_4_1843200_200 },
4111 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4112 PCI_SUBVENDOR_ID_CONNECT_TECH,
4113 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4114 pbn_b0_8_1843200_200 },
4115 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4116 PCI_SUBVENDOR_ID_CONNECT_TECH,
4117 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4118 pbn_b0_2_1843200_200 },
4119 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4120 PCI_SUBVENDOR_ID_CONNECT_TECH,
4121 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4122 pbn_b0_4_1843200_200 },
4123 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4124 PCI_SUBVENDOR_ID_CONNECT_TECH,
4125 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4126 pbn_b0_8_1843200_200 },
c68d2b15
BH		 4127 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4128 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4129 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 4130
4131 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 4132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4133 pbn_b2_bt_1_115200 },
4134 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 4135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4136 pbn_b2_bt_2_115200 },
4137 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 4138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4139 pbn_b2_bt_4_115200 },
4140 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 4141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4142 pbn_b2_bt_2_115200 },
4143 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 4144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4145 pbn_b2_bt_4_115200 },
4146 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 4147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4148 pbn_b2_8_115200 },
e65f0f82
FL		 4149 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4151 pbn_b2_8_460800 },
1da177e4
LT		 4152 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4154 pbn_b2_8_115200 },
4155
4156 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4158 pbn_b2_bt_2_115200 },
4159 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4161 pbn_b2_bt_2_921600 },
4162 /*
4163 * VScom SPCOM800, from sl@s.pl
4164 */
5756ee99
AC		 4165 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4167 pbn_b2_8_921600 },
4168 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 4169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4170 pbn_b2_4_921600 },
b76c5a07
CB		 4171 /* Unknown card - subdevice 0x1584 */
4172 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4173 PCI_VENDOR_ID_PLX,
4174 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 4175 pbn_b2_4_115200 },
4176 /* Unknown card - subdevice 0x1588 */
4177 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4178 PCI_VENDOR_ID_PLX,
4179 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4180 pbn_b2_8_115200 },
1da177e4
LT		 4181 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4182 PCI_SUBVENDOR_ID_KEYSPAN,
4183 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4184 pbn_panacom },
4185 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4187 pbn_panacom4 },
4188 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4190 pbn_panacom2 },
a9cccd34
MF		 4191 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4192 PCI_VENDOR_ID_ESDGMBH,
4193 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4194 pbn_b2_4_115200 },
1da177e4
LT		 4195 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4196 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4197 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 4198 pbn_b2_4_460800 },
4199 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4200 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4201 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 4202 pbn_b2_8_460800 },
4203 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4204 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4205 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 4206 pbn_b2_16_460800 },
4207 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4208 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4209 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 4210 pbn_b2_16_460800 },
4211 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4212 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4213 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 4214 pbn_b2_4_460800 },
4215 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4216 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4217 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 4218 pbn_b2_8_460800 },
add7b58e
BH		 4219 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4220 PCI_SUBVENDOR_ID_EXSYS,
4221 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 4222 pbn_b2_4_115200 },
1da177e4
LT		 4223 /*
4224 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4225 * (Exoray@isys.ca)
4226 */
4227 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4228 0x10b5, 0x106a, 0, 0,
4229 pbn_plx_romulus },
1bc8cde4
MS		 4230 /*
4231 * EndRun Technologies. PCI express device range.
4232 * EndRun PTP/1588 has 2 Native UARTs.
4233 */
4234 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4236 pbn_endrun_2_4000000 },
55c7c0fd
AC		 4237 /*
4238 * Quatech cards. These actually have configurable clocks but for
4239 * now we just use the default.
4240 *
4241 * 100 series are RS232, 200 series RS422,
4242 */
1da177e4
LT		 4243 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4244 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4245 pbn_b1_4_115200 },
4246 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4247 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4248 pbn_b1_2_115200 },
55c7c0fd
AC		 4249 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4250 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4251 pbn_b2_2_115200 },
4252 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4254 pbn_b1_2_115200 },
4255 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4257 pbn_b2_2_115200 },
4258 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4259 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4260 pbn_b1_4_115200 },
1da177e4
LT		 4261 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4262 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4263 pbn_b1_8_115200 },
4264 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4265 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4266 pbn_b1_8_115200 },
55c7c0fd
AC		 4267 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4268 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4269 pbn_b1_4_115200 },
4270 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4271 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4272 pbn_b1_2_115200 },
4273 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4274 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4275 pbn_b1_4_115200 },
4276 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4278 pbn_b1_2_115200 },
4279 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4281 pbn_b2_4_115200 },
4282 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4283 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4284 pbn_b2_2_115200 },
4285 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4287 pbn_b2_1_115200 },
4288 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4290 pbn_b2_4_115200 },
4291 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4292 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4293 pbn_b2_2_115200 },
4294 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4295 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4296 pbn_b2_1_115200 },
4297 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4298 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4299 pbn_b0_8_115200 },
4300
1da177e4 4301 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4302 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4303 0, 0,
1da177e4 4304 pbn_b0_4_921600 },
fbc0dc0d 4305 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4306 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4307 0, 0,
fbc0dc0d 4308 pbn_b0_4_1152000 },
c9bd9d01
MP		 4309 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4310 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4311 pbn_b0_bt_2_921600 },
db1de159
DR		 4312
4313 /*
4314 * The below card is a little controversial since it is the
4315 * subject of a PCI vendor/device ID clash. (See
4316 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4317 * For now just used the hex ID 0x950a.
4318 */
39aced68 4319 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 4320 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4321 0, 0, pbn_b0_2_115200 },
4322 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4323 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4324 0, 0, pbn_b0_2_115200 },
db1de159
DR		 4325 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 pbn_b0_2_1130000 },
70fd8fde
AP		 4328 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4329 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4330 pbn_b0_1_921600 },
1da177e4
LT		 4331 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 pbn_b0_4_115200 },
4334 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_b0_bt_2_921600 },
e847003f 4337 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
1a33e342 4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
e847003f 4339 pbn_b2_8_1152000 },
1da177e4 4340
7106b4e3
LH		 4341 /*
4342 * Oxford Semiconductor Inc. Tornado PCI express device range.
4343 */
4344 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4346 pbn_b0_1_4000000 },
4347 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4349 pbn_b0_1_4000000 },
4350 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4351 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4352 pbn_oxsemi_1_4000000 },
4353 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4355 pbn_oxsemi_1_4000000 },
4356 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4358 pbn_b0_1_4000000 },
4359 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4361 pbn_b0_1_4000000 },
4362 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4364 pbn_oxsemi_1_4000000 },
4365 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4367 pbn_oxsemi_1_4000000 },
4368 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4370 pbn_b0_1_4000000 },
4371 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4373 pbn_b0_1_4000000 },
4374 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376 pbn_b0_1_4000000 },
4377 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4378 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4379 pbn_b0_1_4000000 },
4380 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4381 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4382 pbn_oxsemi_2_4000000 },
4383 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4384 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4385 pbn_oxsemi_2_4000000 },
4386 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4387 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4388 pbn_oxsemi_4_4000000 },
4389 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4390 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4391 pbn_oxsemi_4_4000000 },
4392 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394 pbn_oxsemi_8_4000000 },
4395 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397 pbn_oxsemi_8_4000000 },
4398 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400 pbn_oxsemi_1_4000000 },
4401 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 pbn_oxsemi_1_4000000 },
4404 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 pbn_oxsemi_1_4000000 },
4407 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_oxsemi_1_4000000 },
4410 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 pbn_oxsemi_1_4000000 },
4413 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 pbn_oxsemi_1_4000000 },
4416 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 pbn_oxsemi_1_4000000 },
4419 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 pbn_oxsemi_1_4000000 },
4422 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 pbn_oxsemi_1_4000000 },
4425 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 pbn_oxsemi_1_4000000 },
4428 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 pbn_oxsemi_1_4000000 },
4431 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433 pbn_oxsemi_1_4000000 },
4434 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436 pbn_oxsemi_1_4000000 },
4437 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 pbn_oxsemi_1_4000000 },
4440 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 pbn_oxsemi_1_4000000 },
4443 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 pbn_oxsemi_1_4000000 },
4446 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 pbn_oxsemi_1_4000000 },
4449 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_oxsemi_1_4000000 },
4452 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_oxsemi_1_4000000 },
4455 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_oxsemi_1_4000000 },
4458 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 pbn_oxsemi_1_4000000 },
4461 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463 pbn_oxsemi_1_4000000 },
4464 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466 pbn_oxsemi_1_4000000 },
4467 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469 pbn_oxsemi_1_4000000 },
4470 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472 pbn_oxsemi_1_4000000 },
4473 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475 pbn_oxsemi_1_4000000 },
b80de369
LH		 4476 /*
4477 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4478 */
4479 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4480 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4481 pbn_oxsemi_1_4000000 },
4482 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4483 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4484 pbn_oxsemi_2_4000000 },
4485 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4486 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4487 pbn_oxsemi_4_4000000 },
4488 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4489 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4490 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4491
4492 /*
4493 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4494 */
4495 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4496 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4497 pbn_oxsemi_2_4000000 },
4498
1da177e4
LT		 4499 /*
4500 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4501 * from skokodyn@yahoo.com
4502 */
4503 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4504 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4505 pbn_sbsxrsio },
4506 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4507 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4508 pbn_sbsxrsio },
4509 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4510 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4511 pbn_sbsxrsio },
4512 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4513 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4514 pbn_sbsxrsio },
4515
4516 /*
4517 * Digitan DS560-558, from jimd@esoft.com
4518 */
4519 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4521 pbn_b1_1_115200 },
4522
4523 /*
4524 * Titan Electronic cards
4525 * The 400L and 800L have a custom setup quirk.
4526 */
4527 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4528 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4529 pbn_b0_1_921600 },
4530 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4531 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4532 pbn_b0_2_921600 },
4533 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4534 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4535 pbn_b0_4_921600 },
4536 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4537 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4538 pbn_b0_4_921600 },
4539 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4540 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4541 pbn_b1_1_921600 },
4542 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4543 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4544 pbn_b1_bt_2_921600 },
4545 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4546 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4547 pbn_b0_bt_4_921600 },
4548 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4549 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4550 pbn_b0_bt_8_921600 },
66169ad1
YY		 4551 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4552 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4553 pbn_b4_bt_2_921600 },
4554 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556 pbn_b4_bt_4_921600 },
4557 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4558 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4559 pbn_b4_bt_8_921600 },
4560 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4561 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4562 pbn_b0_4_921600 },
4563 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4564 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4565 pbn_b0_4_921600 },
4566 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4567 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4568 pbn_b0_4_921600 },
4569 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4570 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4571 pbn_oxsemi_1_4000000 },
4572 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 pbn_oxsemi_2_4000000 },
4575 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4577 pbn_oxsemi_4_4000000 },
4578 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_oxsemi_8_4000000 },
4581 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_oxsemi_2_4000000 },
4584 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_oxsemi_2_4000000 },
48c0247d
YY		 4587 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_b0_bt_2_921600 },
1e9deb11
YY		 4590 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_b0_4_921600 },
4593 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_b0_4_921600 },
4596 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_b0_4_921600 },
4599 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_b0_4_921600 },
1da177e4
LT		 4602
4603 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b2_1_460800 },
4606 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_b2_1_460800 },
4609 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_b2_1_460800 },
4612 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_b2_bt_2_921600 },
4615 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_b2_bt_2_921600 },
4618 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_b2_bt_2_921600 },
4621 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_b2_bt_4_921600 },
4624 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_b2_bt_4_921600 },
4627 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_b2_bt_4_921600 },
4630 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_b0_1_921600 },
4633 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_b0_1_921600 },
4636 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_b0_1_921600 },
4639 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_b0_bt_2_921600 },
4642 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_b0_bt_2_921600 },
4645 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_b0_bt_2_921600 },
4648 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_b0_bt_4_921600 },
4651 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653 pbn_b0_bt_4_921600 },
4654 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_b0_bt_4_921600 },
3ec9c594
AP		 4657 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4658 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659 pbn_b0_bt_8_921600 },
4660 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_b0_bt_8_921600 },
4663 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 pbn_b0_bt_8_921600 },
1da177e4
LT		 4666
4667 /*
4668 * Computone devices submitted by Doug McNash dmcnash@computone.com
4669 */
4670 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4671 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4672 0, 0, pbn_computone_4 },
4673 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4674 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4675 0, 0, pbn_computone_8 },
4676 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4677 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4678 0, 0, pbn_computone_6 },
4679
4680 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4682 pbn_oxsemi },
4683 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4684 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4685 pbn_b0_bt_1_921600 },
4686
abd7baca
SC		 4687 /*
4688 * SUNIX (TIMEDIA)
4689 */
4690 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4691 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4692 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4693 pbn_b0_bt_1_921600 },
4694
4695 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4696 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4697 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4698 pbn_b0_bt_1_921600 },
4699
1da177e4
LT		 4700 /*
4701 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4702 */
4703 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 pbn_b0_bt_8_115200 },
4706 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 pbn_b0_bt_8_115200 },
4709
4710 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4712 pbn_b0_bt_2_115200 },
4713 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4715 pbn_b0_bt_2_115200 },
4716 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4718 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 4719 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4720 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4721 pbn_b0_bt_2_115200 },
4722 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4723 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4724 pbn_b0_bt_2_115200 },
1da177e4
LT		 4725 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4726 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4727 pbn_b0_bt_4_460800 },
4728 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4729 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4730 pbn_b0_bt_4_460800 },
4731 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4732 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4733 pbn_b0_bt_2_460800 },
4734 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4735 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4736 pbn_b0_bt_2_460800 },
4737 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4739 pbn_b0_bt_2_460800 },
4740 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4742 pbn_b0_bt_1_115200 },
4743 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4745 pbn_b0_bt_1_460800 },
4746
1fb8cacc
RK		 4747 /*
4748 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4749 * Cards are identified by their subsystem vendor IDs, which
4750 * (in hex) match the model number.
4751 *
4752 * Note that JC140x are RS422/485 cards which require ox950
4753 * ACR = 0x10, and as such are not currently fully supported.
4754 */
4755 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4756 0x1204, 0x0004, 0, 0,
4757 pbn_b0_4_921600 },
4758 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4759 0x1208, 0x0004, 0, 0,
4760 pbn_b0_4_921600 },
4761/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4762 0x1402, 0x0002, 0, 0,
4763 pbn_b0_2_921600 }, */
4764/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4765 0x1404, 0x0004, 0, 0,
4766 pbn_b0_4_921600 }, */
4767 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4768 0x1208, 0x0004, 0, 0,
4769 pbn_b0_4_921600 },
4770
2a52fcb5
KY		 4771 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4772 0x1204, 0x0004, 0, 0,
4773 pbn_b0_4_921600 },
4774 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4775 0x1208, 0x0004, 0, 0,
4776 pbn_b0_4_921600 },
4777 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4778 0x1208, 0x0004, 0, 0,
4779 pbn_b0_4_921600 },
1da177e4
LT		 4780 /*
4781 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4782 */
4783 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 pbn_b1_1_1382400 },
4786
4787 /*
4788 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4789 */
4790 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792 pbn_b1_1_1382400 },
4793
4794 /*
4795 * RAStel 2 port modem, gerg@moreton.com.au
4796 */
4797 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4799 pbn_b2_bt_2_115200 },
4800
4801 /*
4802 * EKF addition for i960 Boards form EKF with serial port
4803 */
4804 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4805 0xE4BF, PCI_ANY_ID, 0, 0,
4806 pbn_intel_i960 },
4807
4808 /*
4809 * Xircom Cardbus/Ethernet combos
4810 */
4811 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813 pbn_b0_1_115200 },
4814 /*
4815 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4816 */
4817 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4819 pbn_b0_1_115200 },
4820
4821 /*
4822 * Untested PCI modems, sent in from various folks...
4823 */
4824
4825 /*
4826 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4827 */
4828 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4829 0x1048, 0x1500, 0, 0,
4830 pbn_b1_1_115200 },
4831
4832 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4833 0xFF00, 0, 0, 0,
4834 pbn_sgi_ioc3 },
4835
4836 /*
4837 * HP Diva card
4838 */
4839 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4840 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4841 pbn_b1_1_115200 },
4842 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4843 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4844 pbn_b0_5_115200 },
4845 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4846 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4847 pbn_b2_1_115200 },
4848
d9004eb4
ABL		 4849 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4851 pbn_b3_2_115200 },
1da177e4
LT		 4852 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4854 pbn_b3_4_115200 },
4855 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4857 pbn_b3_8_115200 },
4858
4859 /*
4860 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4861 */
4862 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4863 PCI_ANY_ID, PCI_ANY_ID,
4864 0,
4865 0, pbn_exar_XR17C152 },
4866 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4867 PCI_ANY_ID, PCI_ANY_ID,
4868 0,
4869 0, pbn_exar_XR17C154 },
4870 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4871 PCI_ANY_ID, PCI_ANY_ID,
4872 0,
4873 0, pbn_exar_XR17C158 },
dc96efb7 4874 /*
96a5d18b 4875 * Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs
dc96efb7
MS		 4876 */
4877 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4878 PCI_ANY_ID, PCI_ANY_ID,
4879 0,
4880 0, pbn_exar_XR17V352 },
4881 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4882 PCI_ANY_ID, PCI_ANY_ID,
4883 0,
4884 0, pbn_exar_XR17V354 },
4885 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4886 PCI_ANY_ID, PCI_ANY_ID,
4887 0,
4888 0, pbn_exar_XR17V358 },
be32c0cf
SG		 4889 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V4358,
4890 PCI_ANY_ID, PCI_ANY_ID,
4891 0,
4892 0, pbn_exar_XR17V4358 },
96a5d18b
SG		 4893 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V8358,
4894 PCI_ANY_ID, PCI_ANY_ID,
4895 0,
4896 0, pbn_exar_XR17V8358 },
89c043a6
AL		 4897 /*
4898 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4899 */
4900 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4901 PCI_ANY_ID, PCI_ANY_ID,
4902 0,
4903 0, pbn_pericom_PI7C9X7951 },
4904 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4905 PCI_ANY_ID, PCI_ANY_ID,
4906 0,
4907 0, pbn_pericom_PI7C9X7952 },
4908 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4909 PCI_ANY_ID, PCI_ANY_ID,
4910 0,
4911 0, pbn_pericom_PI7C9X7954 },
4912 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4913 PCI_ANY_ID, PCI_ANY_ID,
4914 0,
4915 0, pbn_pericom_PI7C9X7958 },
1da177e4
LT		 4916 /*
4917 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4918 */
4919 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921 pbn_b0_1_115200 },
84f8c6fc
NV		 4922 /*
4923 * ITE
4924 */
4925 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4926 PCI_ANY_ID, PCI_ANY_ID,
4927 0, 0,
4928 pbn_b1_bt_1_115200 },
1da177e4 4929
737c1756
PH		 4930 /*
4931 * IntaShield IS-200
4932 */
4933 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4935 pbn_b2_2_115200 },
4b6f6ce9
IGP		 4936 /*
4937 * IntaShield IS-400
4938 */
4939 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4941 pbn_b2_4_115200 },
48212008
TH		 4942 /*
4943 * Perle PCI-RAS cards
4944 */
4945 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4946 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4947 0, 0, pbn_b2_4_921600 },
4948 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4949 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4950 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 4951
4952 /*
4953 * Mainpine series cards: Fairly standard layout but fools
4954 * parts of the autodetect in some cases and uses otherwise
4955 * unmatched communications subclasses in the PCI Express case
4956 */
4957
4958 { /* RockForceDUO */
4959 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4960 PCI_VENDOR_ID_MAINPINE, 0x0200,
4961 0, 0, pbn_b0_2_115200 },
4962 { /* RockForceQUATRO */
4963 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4964 PCI_VENDOR_ID_MAINPINE, 0x0300,
4965 0, 0, pbn_b0_4_115200 },
4966 { /* RockForceDUO+ */
4967 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4968 PCI_VENDOR_ID_MAINPINE, 0x0400,
4969 0, 0, pbn_b0_2_115200 },
4970 { /* RockForceQUATRO+ */
4971 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4972 PCI_VENDOR_ID_MAINPINE, 0x0500,
4973 0, 0, pbn_b0_4_115200 },
4974 { /* RockForce+ */
4975 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4976 PCI_VENDOR_ID_MAINPINE, 0x0600,
4977 0, 0, pbn_b0_2_115200 },
4978 { /* RockForce+ */
4979 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4980 PCI_VENDOR_ID_MAINPINE, 0x0700,
4981 0, 0, pbn_b0_4_115200 },
4982 { /* RockForceOCTO+ */
4983 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4984 PCI_VENDOR_ID_MAINPINE, 0x0800,
4985 0, 0, pbn_b0_8_115200 },
4986 { /* RockForceDUO+ */
4987 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4988 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4989 0, 0, pbn_b0_2_115200 },
4990 { /* RockForceQUARTRO+ */
4991 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4992 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4993 0, 0, pbn_b0_4_115200 },
4994 { /* RockForceOCTO+ */
4995 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4996 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4997 0, 0, pbn_b0_8_115200 },
4998 { /* RockForceD1 */
4999 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5000 PCI_VENDOR_ID_MAINPINE, 0x2000,
5001 0, 0, pbn_b0_1_115200 },
5002 { /* RockForceF1 */
5003 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5004 PCI_VENDOR_ID_MAINPINE, 0x2100,
5005 0, 0, pbn_b0_1_115200 },
5006 { /* RockForceD2 */
5007 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5008 PCI_VENDOR_ID_MAINPINE, 0x2200,
5009 0, 0, pbn_b0_2_115200 },
5010 { /* RockForceF2 */
5011 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5012 PCI_VENDOR_ID_MAINPINE, 0x2300,
5013 0, 0, pbn_b0_2_115200 },
5014 { /* RockForceD4 */
5015 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5016 PCI_VENDOR_ID_MAINPINE, 0x2400,
5017 0, 0, pbn_b0_4_115200 },
5018 { /* RockForceF4 */
5019 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5020 PCI_VENDOR_ID_MAINPINE, 0x2500,
5021 0, 0, pbn_b0_4_115200 },
5022 { /* RockForceD8 */
5023 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5024 PCI_VENDOR_ID_MAINPINE, 0x2600,
5025 0, 0, pbn_b0_8_115200 },
5026 { /* RockForceF8 */
5027 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5028 PCI_VENDOR_ID_MAINPINE, 0x2700,
5029 0, 0, pbn_b0_8_115200 },
5030 { /* IQ Express D1 */
5031 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5032 PCI_VENDOR_ID_MAINPINE, 0x3000,
5033 0, 0, pbn_b0_1_115200 },
5034 { /* IQ Express F1 */
5035 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5036 PCI_VENDOR_ID_MAINPINE, 0x3100,
5037 0, 0, pbn_b0_1_115200 },
5038 { /* IQ Express D2 */
5039 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5040 PCI_VENDOR_ID_MAINPINE, 0x3200,
5041 0, 0, pbn_b0_2_115200 },
5042 { /* IQ Express F2 */
5043 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5044 PCI_VENDOR_ID_MAINPINE, 0x3300,
5045 0, 0, pbn_b0_2_115200 },
5046 { /* IQ Express D4 */
5047 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5048 PCI_VENDOR_ID_MAINPINE, 0x3400,
5049 0, 0, pbn_b0_4_115200 },
5050 { /* IQ Express F4 */
5051 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5052 PCI_VENDOR_ID_MAINPINE, 0x3500,
5053 0, 0, pbn_b0_4_115200 },
5054 { /* IQ Express D8 */
5055 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5056 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5057 0, 0, pbn_b0_8_115200 },
5058 { /* IQ Express F8 */
5059 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5060 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5061 0, 0, pbn_b0_8_115200 },
5062
5063
aa798505
OJ		 5064 /*
5065 * PA Semi PA6T-1682M on-chip UART
5066 */
5067 { PCI_VENDOR_ID_PASEMI, 0xa004,
5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5069 pbn_pasemi_1682M },
5070
46a0fac9
SB		 5071 /*
5072 * National Instruments
5073 */
04bf7e74
WP		 5074 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5076 pbn_b1_16_115200 },
5077 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5079 pbn_b1_8_115200 },
5080 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5082 pbn_b1_bt_4_115200 },
5083 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5085 pbn_b1_bt_2_115200 },
5086 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5088 pbn_b1_bt_4_115200 },
5089 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5091 pbn_b1_bt_2_115200 },
5092 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5094 pbn_b1_16_115200 },
5095 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5097 pbn_b1_8_115200 },
5098 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5100 pbn_b1_bt_4_115200 },
5101 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5103 pbn_b1_bt_2_115200 },
5104 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5106 pbn_b1_bt_4_115200 },
5107 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5109 pbn_b1_bt_2_115200 },
46a0fac9
SB		 5110 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5112 pbn_ni8430_2 },
5113 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5115 pbn_ni8430_2 },
5116 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5118 pbn_ni8430_4 },
5119 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5121 pbn_ni8430_4 },
5122 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5124 pbn_ni8430_8 },
5125 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5127 pbn_ni8430_8 },
5128 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5130 pbn_ni8430_16 },
5131 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5133 pbn_ni8430_16 },
5134 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5136 pbn_ni8430_2 },
5137 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5139 pbn_ni8430_2 },
5140 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5142 pbn_ni8430_4 },
5143 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5145 pbn_ni8430_4 },
5146
02c9b5cf
KJ		 5147 /*
5148 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5149 */
5150 { PCI_VENDOR_ID_ADDIDATA,
5151 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5152 PCI_ANY_ID,
5153 PCI_ANY_ID,
5154 0,
5155 0,
5156 pbn_b0_4_115200 },
5157
5158 { PCI_VENDOR_ID_ADDIDATA,
5159 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5160 PCI_ANY_ID,
5161 PCI_ANY_ID,
5162 0,
5163 0,
5164 pbn_b0_2_115200 },
5165
5166 { PCI_VENDOR_ID_ADDIDATA,
5167 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5168 PCI_ANY_ID,
5169 PCI_ANY_ID,
5170 0,
5171 0,
5172 pbn_b0_1_115200 },
5173
086231f7 5174 { PCI_VENDOR_ID_AMCC,
57c1f0e9 5175 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 5176 PCI_ANY_ID,
5177 PCI_ANY_ID,
5178 0,
5179 0,
5180 pbn_b1_8_115200 },
5181
5182 { PCI_VENDOR_ID_ADDIDATA,
5183 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5184 PCI_ANY_ID,
5185 PCI_ANY_ID,
5186 0,
5187 0,
5188 pbn_b0_4_115200 },
5189
5190 { PCI_VENDOR_ID_ADDIDATA,
5191 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5192 PCI_ANY_ID,
5193 PCI_ANY_ID,
5194 0,
5195 0,
5196 pbn_b0_2_115200 },
5197
5198 { PCI_VENDOR_ID_ADDIDATA,
5199 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5200 PCI_ANY_ID,
5201 PCI_ANY_ID,
5202 0,
5203 0,
5204 pbn_b0_1_115200 },
5205
5206 { PCI_VENDOR_ID_ADDIDATA,
5207 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5208 PCI_ANY_ID,
5209 PCI_ANY_ID,
5210 0,
5211 0,
5212 pbn_b0_4_115200 },
5213
5214 { PCI_VENDOR_ID_ADDIDATA,
5215 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5216 PCI_ANY_ID,
5217 PCI_ANY_ID,
5218 0,
5219 0,
5220 pbn_b0_2_115200 },
5221
5222 { PCI_VENDOR_ID_ADDIDATA,
5223 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5224 PCI_ANY_ID,
5225 PCI_ANY_ID,
5226 0,
5227 0,
5228 pbn_b0_1_115200 },
5229
5230 { PCI_VENDOR_ID_ADDIDATA,
5231 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5232 PCI_ANY_ID,
5233 PCI_ANY_ID,
5234 0,
5235 0,
5236 pbn_b0_8_115200 },
5237
1b62cbf2
KJ		 5238 { PCI_VENDOR_ID_ADDIDATA,
5239 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5240 PCI_ANY_ID,
5241 PCI_ANY_ID,
5242 0,
5243 0,
5244 pbn_ADDIDATA_PCIe_4_3906250 },
5245
5246 { PCI_VENDOR_ID_ADDIDATA,
5247 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5248 PCI_ANY_ID,
5249 PCI_ANY_ID,
5250 0,
5251 0,
5252 pbn_ADDIDATA_PCIe_2_3906250 },
5253
5254 { PCI_VENDOR_ID_ADDIDATA,
5255 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5256 PCI_ANY_ID,
5257 PCI_ANY_ID,
5258 0,
5259 0,
5260 pbn_ADDIDATA_PCIe_1_3906250 },
5261
5262 { PCI_VENDOR_ID_ADDIDATA,
5263 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5264 PCI_ANY_ID,
5265 PCI_ANY_ID,
5266 0,
5267 0,
5268 pbn_ADDIDATA_PCIe_8_3906250 },
5269
25cf9bc1
JS		 5270 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5271 PCI_VENDOR_ID_IBM, 0x0299,
5272 0, 0, pbn_b0_bt_2_115200 },
5273
972ce085
SS		 5274 /*
5275 * other NetMos 9835 devices are most likely handled by the
5276 * parport_serial driver, check drivers/parport/parport_serial.c
5277 * before adding them here.
5278 */
5279
c4285b47
MB		 5280 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5281 0xA000, 0x1000,
5282 0, 0, pbn_b0_1_115200 },
5283
7808edcd
NG		 5284 /* the 9901 is a rebranded 9912 */
5285 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5286 0xA000, 0x1000,
5287 0, 0, pbn_b0_1_115200 },
5288
5289 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5290 0xA000, 0x1000,
5291 0, 0, pbn_b0_1_115200 },
5292
5293 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5294 0xA000, 0x1000,
5295 0, 0, pbn_b0_1_115200 },
5296
5297 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5298 0xA000, 0x1000,
5299 0, 0, pbn_b0_1_115200 },
5300
5301 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5302 0xA000, 0x3002,
5303 0, 0, pbn_NETMOS9900_2s_115200 },
5304
ac6ec5b1 5305 /*
44178176 5306 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 5307 */
5308
5309 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5310 0xA000, 0x1000,
5311 0, 0, pbn_b0_1_115200 },
5312
44178176
ES		 5313 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5314 0xA000, 0x3002,
5315 0, 0, pbn_b0_bt_2_115200 },
5316
ac6ec5b1
IS		 5317 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5318 0xA000, 0x3004,
5319 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 5320 /* Intel CE4100 */
5321 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5322 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5323 pbn_ce4100_1_115200 },
6c55d9b9 5324
1ede7dcc
BD		 5325 /*
5326 * Intel Quark x1000
5327 */
5328 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5330 pbn_qrk },
d9a0fbfd
AP		 5331 /*
5332 * Cronyx Omega PCI
5333 */
5334 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5336 pbn_omegapci },
ac6ec5b1 5337
ebebd49a
SH		 5338 /*
5339 * Broadcom TruManage
5340 */
5341 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5343 pbn_brcm_trumanage },
5344
6683549e
AC		 5345 /*
5346 * AgeStar as-prs2-009
5347 */
5348 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5349 PCI_ANY_ID, PCI_ANY_ID,
5350 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 5351
5352 /*
5353 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5354 * so not listed here.
5355 */
5356 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5357 PCI_ANY_ID, PCI_ANY_ID,
5358 0, 0, pbn_b0_bt_4_115200 },
5359
5360 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5361 PCI_ANY_ID, PCI_ANY_ID,
5362 0, 0, pbn_b0_bt_2_115200 },
5363
55c368cb
AP		 5364 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5365 PCI_ANY_ID, PCI_ANY_ID,
5366 0, 0, pbn_b0_bt_4_115200 },
5367
7dde5578
JM		 5368 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5369 PCI_ANY_ID, PCI_ANY_ID,
5370 0, 0, pbn_wch382_2 },
5371
72a3c0e4
SP		 5372 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5373 PCI_ANY_ID, PCI_ANY_ID,
5374 0, 0, pbn_wch384_4 },
5375
14faa8cc
MS		 5376 /*
5377 * Commtech, Inc. Fastcom adapters
5378 */
5379 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5380 PCI_ANY_ID, PCI_ANY_ID,
5381 0,
5382 0, pbn_b0_2_1152000_200 },
5383 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5384 PCI_ANY_ID, PCI_ANY_ID,
5385 0,
5386 0, pbn_b0_4_1152000_200 },
5387 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5388 PCI_ANY_ID, PCI_ANY_ID,
5389 0,
5390 0, pbn_b0_4_1152000_200 },
5391 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5392 PCI_ANY_ID, PCI_ANY_ID,
5393 0,
5394 0, pbn_b0_8_1152000_200 },
5395 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5396 PCI_ANY_ID, PCI_ANY_ID,
5397 0,
5398 0, pbn_exar_XR17V352 },
5399 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5400 PCI_ANY_ID, PCI_ANY_ID,
5401 0,
5402 0, pbn_exar_XR17V354 },
5403 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5404 PCI_ANY_ID, PCI_ANY_ID,
5405 0,
5406 0, pbn_exar_XR17V358 },
5407
2c62a3c8
GKH		 5408 /* Fintek PCI serial cards */
5409 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5410 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5411 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5412
1da177e4
LT		 5413 /*
5414 * These entries match devices with class COMMUNICATION_SERIAL,
5415 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5416 */
5417 { PCI_ANY_ID, PCI_ANY_ID,
5418 PCI_ANY_ID, PCI_ANY_ID,
5419 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5420 0xffff00, pbn_default },
5421 { PCI_ANY_ID, PCI_ANY_ID,
5422 PCI_ANY_ID, PCI_ANY_ID,
5423 PCI_CLASS_COMMUNICATION_MODEM << 8,
5424 0xffff00, pbn_default },
5425 { PCI_ANY_ID, PCI_ANY_ID,
5426 PCI_ANY_ID, PCI_ANY_ID,
5427 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5428 0xffff00, pbn_default },
5429 { 0, }
5430};
5431
2807190b
MR		 5432static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5433 pci_channel_state_t state)
5434{
5435 struct serial_private *priv = pci_get_drvdata(dev);
5436
5437 if (state == pci_channel_io_perm_failure)
5438 return PCI_ERS_RESULT_DISCONNECT;
5439
5440 if (priv)
5441 pciserial_suspend_ports(priv);
5442
5443 pci_disable_device(dev);
5444
5445 return PCI_ERS_RESULT_NEED_RESET;
5446}
5447
5448static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5449{
5450 int rc;
5451
5452 rc = pci_enable_device(dev);
5453
5454 if (rc)
5455 return PCI_ERS_RESULT_DISCONNECT;
5456
5457 pci_restore_state(dev);
5458 pci_save_state(dev);
5459
5460 return PCI_ERS_RESULT_RECOVERED;
5461}
5462
5463static void serial8250_io_resume(struct pci_dev *dev)
5464{
5465 struct serial_private *priv = pci_get_drvdata(dev);
5466
5467 if (priv)
5468 pciserial_resume_ports(priv);
5469}
5470
1d352035 5471static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 5472 .error_detected = serial8250_io_error_detected,
5473 .slot_reset = serial8250_io_slot_reset,
5474 .resume = serial8250_io_resume,
5475};
5476
1da177e4
LT		 5477static struct pci_driver serial_pci_driver = {
5478 .name = "serial",
5479 .probe = pciserial_init_one,
2d47b716 5480 .remove = pciserial_remove_one,
61702c3e
AS		 5481 .driver = {
5482 .pm = &pciserial_pm_ops,
5483 },
1da177e4 5484 .id_table = serial_pci_tbl,
2807190b 5485 .err_handler = &serial8250_err_handler,
1da177e4
LT		 5486};
5487
15a12e83 5488module_pci_driver(serial_pci_driver);
1da177e4
LT		 5489
5490MODULE_LICENSE("GPL");
5491MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5492MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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