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8250: propogate the bugs field
[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
24
25#include <asm/byteorder.h>
26#include <asm/io.h>
27
28#include "8250.h"
29
30#undef SERIAL_DEBUG_PCI
31
1da177e4
LT		 32/*
33 * init function returns:
34 * > 0 - number of ports
35 * = 0 - use board->num_ports
36 * < 0 - error
37 */
38struct pci_serial_quirk {
39 u32 vendor;
40 u32 device;
41 u32 subvendor;
42 u32 subdevice;
5bf8f501 43 int (*probe)(struct pci_dev *dev);
1da177e4 44 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
2655a2c7 47 struct uart_8250_port *, int);
1da177e4
LT		 48 void (*exit)(struct pci_dev *dev);
49};
50
51#define PCI_NUM_BAR_RESOURCES 6
52
53struct serial_private {
70db3d91 54 struct pci_dev *dev;
1da177e4
LT		 55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59};
60
7808edcd 61static int pci_default_setup(struct serial_private*,
2655a2c7 62 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 63
1da177e4
LT		 64static void moan_device(const char *str, struct pci_dev *dev)
65{
ad361c98
JP		 66 printk(KERN_WARNING
67 "%s: %s\n"
68 "Please send the output of lspci -vv, this\n"
69 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
70 "manufacturer and name of serial board or\n"
71 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 72 pci_name(dev), str, dev->vendor, dev->device,
73 dev->subsystem_vendor, dev->subsystem_device);
74}
75
76static int
2655a2c7 77setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 78 int bar, int offset, int regshift)
79{
70db3d91 80 struct pci_dev *dev = priv->dev;
1da177e4
LT		 81 unsigned long base, len;
82
83 if (bar >= PCI_NUM_BAR_RESOURCES)
84 return -EINVAL;
85
72ce9a83
RK		 86 base = pci_resource_start(dev, bar);
87
1da177e4 88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 89 len = pci_resource_len(dev, bar);
90
91 if (!priv->remapped_bar[bar])
6f441fe9 92 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 93 if (!priv->remapped_bar[bar])
94 return -ENOMEM;
95
2655a2c7
AC		 96 port->port.iotype = UPIO_MEM;
97 port->port.iobase = 0;
98 port->port.mapbase = base + offset;
99 port->port.membase = priv->remapped_bar[bar] + offset;
100 port->port.regshift = regshift;
1da177e4 101 } else {
2655a2c7
AC		 102 port->port.iotype = UPIO_PORT;
103 port->port.iobase = base + offset;
104 port->port.mapbase = 0;
105 port->port.membase = NULL;
106 port->port.regshift = 0;
1da177e4
LT		 107 }
108 return 0;
109}
110
02c9b5cf
KJ		 111/*
112 * ADDI-DATA GmbH communication cards <info@addi-data.com>
113 */
114static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 115 const struct pciserial_board *board,
2655a2c7 116 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 117{
118 unsigned int bar = 0, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
120
121 if (idx < 2) {
122 offset += idx * board->uart_offset;
123 } else if ((idx >= 2) && (idx < 4)) {
124 bar += 1;
125 offset += ((idx - 2) * board->uart_offset);
126 } else if ((idx >= 4) && (idx < 6)) {
127 bar += 2;
128 offset += ((idx - 4) * board->uart_offset);
129 } else if (idx >= 6) {
130 bar += 3;
131 offset += ((idx - 6) * board->uart_offset);
132 }
133
134 return setup_port(priv, port, bar, offset, board->reg_shift);
135}
136
1da177e4
LT		 137/*
138 * AFAVLAB uses a different mixture of BARs and offsets
139 * Not that ugly ;) -- HW
140 */
141static int
975a1a7d 142afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 143 struct uart_8250_port *port, int idx)
1da177e4
LT		 144{
145 unsigned int bar, offset = board->first_offset;
5756ee99 146
1da177e4
LT		 147 bar = FL_GET_BASE(board->flags);
148 if (idx < 4)
149 bar += idx;
150 else {
151 bar = 4;
152 offset += (idx - 4) * board->uart_offset;
153 }
154
70db3d91 155 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 156}
157
158/*
159 * HP's Remote Management Console. The Diva chip came in several
160 * different versions. N-class, L2000 and A500 have two Diva chips, each
161 * with 3 UARTs (the third UART on the second chip is unused). Superdome
162 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
163 * one Diva chip, but it has been expanded to 5 UARTs.
164 */
61a116ef 165static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 166{
167 int rc = 0;
168
169 switch (dev->subsystem_device) {
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
171 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
172 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
173 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
174 rc = 3;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
177 rc = 2;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
180 rc = 4;
181 break;
182 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 183 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 184 rc = 1;
185 break;
186 }
187
188 return rc;
189}
190
191/*
192 * HP's Diva chip puts the 4th/5th serial port further out, and
193 * some serial ports are supposed to be hidden on certain models.
194 */
195static int
975a1a7d
RK		 196pci_hp_diva_setup(struct serial_private *priv,
197 const struct pciserial_board *board,
2655a2c7 198 struct uart_8250_port *port, int idx)
1da177e4
LT		 199{
200 unsigned int offset = board->first_offset;
201 unsigned int bar = FL_GET_BASE(board->flags);
202
70db3d91 203 switch (priv->dev->subsystem_device) {
1da177e4
LT		 204 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 if (idx == 3)
206 idx++;
207 break;
208 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209 if (idx > 0)
210 idx++;
211 if (idx > 2)
212 idx++;
213 break;
214 }
215 if (idx > 2)
216 offset = 0x18;
217
218 offset += idx * board->uart_offset;
219
70db3d91 220 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 221}
222
223/*
224 * Added for EKF Intel i960 serial boards
225 */
61a116ef 226static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 227{
228 unsigned long oldval;
229
230 if (!(dev->subsystem_device & 0x1000))
231 return -ENODEV;
232
233 /* is firmware started? */
5756ee99
AC		 234 pci_read_config_dword(dev, 0x44, (void *)&oldval);
235 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 236 printk(KERN_DEBUG "Local i960 firmware missing");
237 return -ENODEV;
238 }
239 return 0;
240}
241
242/*
243 * Some PCI serial cards using the PLX 9050 PCI interface chip require
244 * that the card interrupt be explicitly enabled or disabled. This
245 * seems to be mainly needed on card using the PLX which also use I/O
246 * mapped memory.
247 */
61a116ef 248static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 249{
250 u8 irq_config;
251 void __iomem *p;
252
253 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
254 moan_device("no memory in bar 0", dev);
255 return 0;
256 }
257
258 irq_config = 0x41;
add7b58e 259 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 260 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 261 irq_config = 0x43;
5756ee99 262
1da177e4 263 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 264 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 265 /*
266 * As the megawolf cards have the int pins active
267 * high, and have 2 UART chips, both ints must be
268 * enabled on the 9050. Also, the UARTS are set in
269 * 16450 mode by default, so we have to enable the
270 * 16C950 'enhanced' mode so that we can use the
271 * deep FIFOs
272 */
273 irq_config = 0x5b;
1da177e4
LT		 274 /*
275 * enable/disable interrupts
276 */
6f441fe9 277 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 278 if (p == NULL)
279 return -ENOMEM;
280 writel(irq_config, p + 0x4c);
281
282 /*
283 * Read the register back to ensure that it took effect.
284 */
285 readl(p + 0x4c);
286 iounmap(p);
287
288 return 0;
289}
290
291static void __devexit pci_plx9050_exit(struct pci_dev *dev)
292{
293 u8 __iomem *p;
294
295 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
296 return;
297
298 /*
299 * disable interrupts
300 */
6f441fe9 301 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 302 if (p != NULL) {
303 writel(0, p + 0x4c);
304
305 /*
306 * Read the register back to ensure that it took effect.
307 */
308 readl(p + 0x4c);
309 iounmap(p);
310 }
311}
312
04bf7e74
WP		 313#define NI8420_INT_ENABLE_REG 0x38
314#define NI8420_INT_ENABLE_BIT 0x2000
315
316static void __devexit pci_ni8420_exit(struct pci_dev *dev)
317{
318 void __iomem *p;
319 unsigned long base, len;
320 unsigned int bar = 0;
321
322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
323 moan_device("no memory in bar", dev);
324 return;
325 }
326
327 base = pci_resource_start(dev, bar);
328 len = pci_resource_len(dev, bar);
329 p = ioremap_nocache(base, len);
330 if (p == NULL)
331 return;
332
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
336 iounmap(p);
337}
338
339
46a0fac9
SB		 340/* MITE registers */
341#define MITE_IOWBSR1 0xc4
342#define MITE_IOWCR1 0xf4
343#define MITE_LCIMR1 0x08
344#define MITE_LCIMR2 0x10
345
346#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
347
348static void __devexit pci_ni8430_exit(struct pci_dev *dev)
349{
350 void __iomem *p;
351 unsigned long base, len;
352 unsigned int bar = 0;
353
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
356 return;
357 }
358
359 base = pci_resource_start(dev, bar);
360 len = pci_resource_len(dev, bar);
361 p = ioremap_nocache(base, len);
362 if (p == NULL)
363 return;
364
365 /* Disable the CPU Interrupt */
366 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
367 iounmap(p);
368}
369
1da177e4
LT		 370/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
371static int
975a1a7d 372sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 373 struct uart_8250_port *port, int idx)
1da177e4
LT		 374{
375 unsigned int bar, offset = board->first_offset;
376
377 bar = 0;
378
379 if (idx < 4) {
380 /* first four channels map to 0, 0x100, 0x200, 0x300 */
381 offset += idx * board->uart_offset;
382 } else if (idx < 8) {
383 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
384 offset += idx * board->uart_offset + 0xC00;
385 } else /* we have only 8 ports on PMC-OCTALPRO */
386 return 1;
387
70db3d91 388 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 389}
390
391/*
392* This does initialization for PMC OCTALPRO cards:
393* maps the device memory, resets the UARTs (needed, bc
394* if the module is removed and inserted again, the card
395* is in the sleep mode) and enables global interrupt.
396*/
397
398/* global control register offset for SBS PMC-OctalPro */
399#define OCT_REG_CR_OFF 0x500
400
61a116ef 401static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 402{
403 u8 __iomem *p;
404
24ed3aba 405 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 406
407 if (p == NULL)
408 return -ENOMEM;
409 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 410 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 411 udelay(50);
5756ee99 412 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 413
414 /* Set bit-2 (INTENABLE) of Control Register */
415 writeb(0x4, p + OCT_REG_CR_OFF);
416 iounmap(p);
417
418 return 0;
419}
420
421/*
422 * Disables the global interrupt of PMC-OctalPro
423 */
424
425static void __devexit sbs_exit(struct pci_dev *dev)
426{
427 u8 __iomem *p;
428
24ed3aba 429 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 430 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
431 if (p != NULL)
1da177e4 432 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 433 iounmap(p);
434}
435
436/*
437 * SIIG serial cards have an PCI interface chip which also controls
438 * the UART clocking frequency. Each UART can be clocked independently
25985edc 439 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 440 * are stored in the EEPROM chip. It can cause problems because this
441 * version of serial driver doesn't support differently clocked UART's
442 * on single PCI card. To prevent this, initialization functions set
443 * high frequency clocking for all UART's on given card. It is safe (I
444 * hope) because it doesn't touch EEPROM settings to prevent conflicts
445 * with other OSes (like M$ DOS).
446 *
447 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 448 *
1da177e4
LT		 449 * There is two family of SIIG serial cards with different PCI
450 * interface chip and different configuration methods:
451 * - 10x cards have control registers in IO and/or memory space;
452 * - 20x cards have control registers in standard PCI configuration space.
453 *
67d74b87
RK		 454 * Note: all 10x cards have PCI device ids 0x10..
455 * all 20x cards have PCI device ids 0x20..
456 *
fbc0dc0d
AP		 457 * There are also Quartet Serial cards which use Oxford Semiconductor
458 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
459 *
1da177e4
LT		 460 * Note: some SIIG cards are probed by the parport_serial object.
461 */
462
463#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
464#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
465
466static int pci_siig10x_init(struct pci_dev *dev)
467{
468 u16 data;
469 void __iomem *p;
470
471 switch (dev->device & 0xfff8) {
472 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
473 data = 0xffdf;
474 break;
475 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
476 data = 0xf7ff;
477 break;
478 default: /* 1S1P, 4S */
479 data = 0xfffb;
480 break;
481 }
482
6f441fe9 483 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 484 if (p == NULL)
485 return -ENOMEM;
486
487 writew(readw(p + 0x28) & data, p + 0x28);
488 readw(p + 0x28);
489 iounmap(p);
490 return 0;
491}
492
493#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
494#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
495
496static int pci_siig20x_init(struct pci_dev *dev)
497{
498 u8 data;
499
500 /* Change clock frequency for the first UART. */
501 pci_read_config_byte(dev, 0x6f, &data);
502 pci_write_config_byte(dev, 0x6f, data & 0xef);
503
504 /* If this card has 2 UART, we have to do the same with second UART. */
505 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
506 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
507 pci_read_config_byte(dev, 0x73, &data);
508 pci_write_config_byte(dev, 0x73, data & 0xef);
509 }
510 return 0;
511}
512
67d74b87
RK		 513static int pci_siig_init(struct pci_dev *dev)
514{
515 unsigned int type = dev->device & 0xff00;
516
517 if (type == 0x1000)
518 return pci_siig10x_init(dev);
519 else if (type == 0x2000)
520 return pci_siig20x_init(dev);
521
522 moan_device("Unknown SIIG card", dev);
523 return -ENODEV;
524}
525
3ec9c594 526static int pci_siig_setup(struct serial_private *priv,
975a1a7d 527 const struct pciserial_board *board,
2655a2c7 528 struct uart_8250_port *port, int idx)
3ec9c594
AP		 529{
530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
531
532 if (idx > 3) {
533 bar = 4;
534 offset = (idx - 4) * 8;
535 }
536
537 return setup_port(priv, port, bar, offset, 0);
538}
539
1da177e4
LT		 540/*
541 * Timedia has an explosion of boards, and to avoid the PCI table from
542 * growing *huge*, we use this function to collapse some 70 entries
543 * in the PCI table into one, for sanity's and compactness's sake.
544 */
e9422e09 545static const unsigned short timedia_single_port[] = {
1da177e4
LT		 546 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
547};
548
e9422e09 549static const unsigned short timedia_dual_port[] = {
1da177e4 550 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 551 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
552 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 553 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
554 0xD079, 0
555};
556
e9422e09 557static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 558 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
559 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 560 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
561 0xB157, 0
562};
563
e9422e09 564static const unsigned short timedia_eight_port[] = {
5756ee99 565 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 566 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
567};
568
cb3592be 569static const struct timedia_struct {
1da177e4 570 int num;
e9422e09 571 const unsigned short *ids;
1da177e4
LT		 572} timedia_data[] = {
573 { 1, timedia_single_port },
574 { 2, timedia_dual_port },
575 { 4, timedia_quad_port },
e9422e09 576 { 8, timedia_eight_port }
1da177e4
LT		 577};
578
b9b24558
FB		 579/*
580 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
581 * listing them individually, this driver merely grabs them all with
582 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
583 * and should be left free to be claimed by parport_serial instead.
584 */
585static int pci_timedia_probe(struct pci_dev *dev)
586{
587 /*
588 * Check the third digit of the subdevice ID
589 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
590 */
591 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
592 dev_info(&dev->dev,
593 "ignoring Timedia subdevice %04x for parport_serial\n",
594 dev->subsystem_device);
595 return -ENODEV;
596 }
597
598 return 0;
599}
600
61a116ef 601static int pci_timedia_init(struct pci_dev *dev)
1da177e4 602{
e9422e09 603 const unsigned short *ids;
1da177e4
LT		 604 int i, j;
605
e9422e09 606 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 607 ids = timedia_data[i].ids;
608 for (j = 0; ids[j]; j++)
609 if (dev->subsystem_device == ids[j])
610 return timedia_data[i].num;
611 }
612 return 0;
613}
614
615/*
616 * Timedia/SUNIX uses a mixture of BARs and offsets
617 * Ugh, this is ugly as all hell --- TYT
618 */
619static int
975a1a7d
RK		 620pci_timedia_setup(struct serial_private *priv,
621 const struct pciserial_board *board,
2655a2c7 622 struct uart_8250_port *port, int idx)
1da177e4
LT		 623{
624 unsigned int bar = 0, offset = board->first_offset;
625
626 switch (idx) {
627 case 0:
628 bar = 0;
629 break;
630 case 1:
631 offset = board->uart_offset;
632 bar = 0;
633 break;
634 case 2:
635 bar = 1;
636 break;
637 case 3:
638 offset = board->uart_offset;
c2cd6d3c 639 /* FALLTHROUGH */
1da177e4
LT		 640 case 4: /* BAR 2 */
641 case 5: /* BAR 3 */
642 case 6: /* BAR 4 */
643 case 7: /* BAR 5 */
644 bar = idx - 2;
645 }
646
70db3d91 647 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 648}
649
650/*
651 * Some Titan cards are also a little weird
652 */
653static int
70db3d91 654titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 655 const struct pciserial_board *board,
2655a2c7 656 struct uart_8250_port *port, int idx)
1da177e4
LT		 657{
658 unsigned int bar, offset = board->first_offset;
659
660 switch (idx) {
661 case 0:
662 bar = 1;
663 break;
664 case 1:
665 bar = 2;
666 break;
667 default:
668 bar = 4;
669 offset = (idx - 2) * board->uart_offset;
670 }
671
70db3d91 672 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 673}
674
61a116ef 675static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 676{
677 msleep(100);
678 return 0;
679}
680
04bf7e74
WP		 681static int pci_ni8420_init(struct pci_dev *dev)
682{
683 void __iomem *p;
684 unsigned long base, len;
685 unsigned int bar = 0;
686
687 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
688 moan_device("no memory in bar", dev);
689 return 0;
690 }
691
692 base = pci_resource_start(dev, bar);
693 len = pci_resource_len(dev, bar);
694 p = ioremap_nocache(base, len);
695 if (p == NULL)
696 return -ENOMEM;
697
698 /* Enable CPU Interrupt */
699 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
700 p + NI8420_INT_ENABLE_REG);
701
702 iounmap(p);
703 return 0;
704}
705
46a0fac9
SB		 706#define MITE_IOWBSR1_WSIZE 0xa
707#define MITE_IOWBSR1_WIN_OFFSET 0x800
708#define MITE_IOWBSR1_WENAB (1 << 7)
709#define MITE_LCIMR1_IO_IE_0 (1 << 24)
710#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
711#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
712
713static int pci_ni8430_init(struct pci_dev *dev)
714{
715 void __iomem *p;
716 unsigned long base, len;
717 u32 device_window;
718 unsigned int bar = 0;
719
720 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
721 moan_device("no memory in bar", dev);
722 return 0;
723 }
724
725 base = pci_resource_start(dev, bar);
726 len = pci_resource_len(dev, bar);
727 p = ioremap_nocache(base, len);
728 if (p == NULL)
729 return -ENOMEM;
730
731 /* Set device window address and size in BAR0 */
732 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
733 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
734 writel(device_window, p + MITE_IOWBSR1);
735
736 /* Set window access to go to RAMSEL IO address space */
737 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
738 p + MITE_IOWCR1);
739
740 /* Enable IO Bus Interrupt 0 */
741 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
742
743 /* Enable CPU Interrupt */
744 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
745
746 iounmap(p);
747 return 0;
748}
749
750/* UART Port Control Register */
751#define NI8430_PORTCON 0x0f
752#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
753
754static int
bf538fe4
AC		 755pci_ni8430_setup(struct serial_private *priv,
756 const struct pciserial_board *board,
2655a2c7 757 struct uart_8250_port *port, int idx)
46a0fac9
SB		 758{
759 void __iomem *p;
760 unsigned long base, len;
761 unsigned int bar, offset = board->first_offset;
762
763 if (idx >= board->num_ports)
764 return 1;
765
766 bar = FL_GET_BASE(board->flags);
767 offset += idx * board->uart_offset;
768
769 base = pci_resource_start(priv->dev, bar);
770 len = pci_resource_len(priv->dev, bar);
771 p = ioremap_nocache(base, len);
772
7c9d440e 773 /* enable the transceiver */
46a0fac9
SB		 774 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
775 p + offset + NI8430_PORTCON);
776
777 iounmap(p);
778
779 return setup_port(priv, port, bar, offset, board->reg_shift);
780}
781
7808edcd
NG		 782static int pci_netmos_9900_setup(struct serial_private *priv,
783 const struct pciserial_board *board,
2655a2c7 784 struct uart_8250_port *port, int idx)
7808edcd
NG		 785{
786 unsigned int bar;
787
788 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
791 */
792 bar = 3 * idx;
793
794 return setup_port(priv, port, bar, 0, board->reg_shift);
795 } else {
796 return pci_default_setup(priv, board, port, idx);
797 }
798}
799
800/* the 99xx series comes with a range of device IDs and a variety
801 * of capabilities:
802 *
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
807 */
808static int pci_netmos_9900_numports(struct pci_dev *dev)
809{
810 unsigned int c = dev->class;
811 unsigned int pi;
812 unsigned short sub_serports;
813
814 pi = (c & 0xff);
815
816 if (pi == 2) {
817 return 1;
818 } else if ((pi == 0) &&
819 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
825 */
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0) {
828 return sub_serports;
829 } else {
830 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
831 return 0;
832 }
833 }
834
835 moan_device("unknown NetMos/Mostech program interface", dev);
836 return 0;
837}
46a0fac9 838
61a116ef 839static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 840{
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
843
ac6ec5b1
IS		 844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 846 return 0;
7808edcd 847
25cf9bc1
JS		 848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
850 return 0;
851
7808edcd
NG		 852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
858 break;
859
860 default:
861 if (num_serial == 0 ) {
862 moan_device("unknown NetMos/Mostech device", dev);
863 }
864 }
865
1da177e4
LT		 866 if (num_serial == 0)
867 return -ENODEV;
7808edcd 868
1da177e4
LT		 869 return num_serial;
870}
871
84f8c6fc 872/*
84f8c6fc
NV		 873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
875 *
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
878 *
879 * The region of the 32 I/O ports is configured in POSIO0R...
880 */
881
882/* registers */
883#define ITE_887x_MISCR 0x9c
884#define ITE_887x_INTCBAR 0x78
885#define ITE_887x_UARTBAR 0x7c
886#define ITE_887x_PS0BAR 0x10
887#define ITE_887x_POSIO0 0x60
888
889/* I/O space size */
890#define ITE_887x_IOSIZE 32
891/* I/O space size (bits 26-24; 8 bytes = 011b) */
892#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893/* I/O space size (bits 26-24; 32 bytes = 101b) */
894#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896#define ITE_887x_POSIO_SPEED (3 << 29)
897/* enable IO_Space bit */
898#define ITE_887x_POSIO_ENABLE (1 << 31)
899
f79abb82 900static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 901{
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904 0x200, 0x280, 0 };
905 int ret, i, type;
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
908
909 /* search for the base-ioport */
910 i = 0;
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913 "ite887x");
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
5756ee99
AC		 920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
921 inta_addr[i]);
84f8c6fc
NV		 922 ret = inb(inta_addr[i]);
923 if (ret != 0xff) {
924 /* ioport connected */
925 break;
926 }
927 release_region(iobase->start, ITE_887x_IOSIZE);
928 iobase = NULL;
929 }
930 i++;
931 }
932
933 if (!inta_addr[i]) {
934 printk(KERN_ERR "ite887x: could not find iobase\n");
935 return -ENODEV;
936 }
937
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
940
941 switch (type) {
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
944 ret = 0;
945 break;
946 case 0xe: /* ITE8872 (2S1P) */
947 ret = 2;
948 break;
949 case 0x6: /* ITE8873 (1S) */
950 ret = 1;
951 break;
952 case 0x8: /* ITE8874 (2S) */
953 ret = 2;
954 break;
955 default:
956 moan_device("Unknown ITE887x", dev);
957 ret = -ENODEV;
958 }
959
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964 &ioport);
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
969
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
984 }
985
986 if (ret <= 0) {
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
989 }
990
991 return ret;
992}
993
994static void __devexit pci_ite887x_exit(struct pci_dev *dev)
995{
996 u32 ioport;
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999 ioport &= 0xffff;
1000 release_region(ioport, ITE_887x_IOSIZE);
1001}
1002
9f2a036a
RK		 1003/*
1004 * Oxford Semiconductor Inc.
1005 * Check that device is part of the Tornado range of devices, then determine
1006 * the number of ports available on the device.
1007 */
1008static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009{
1010 u8 __iomem *p;
1011 unsigned long deviceID;
1012 unsigned int number_uarts = 0;
1013
1014 /* OxSemi Tornado devices are all 0xCxxx */
1015 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016 (dev->device & 0xF000) != 0xC000)
1017 return 0;
1018
1019 p = pci_iomap(dev, 0, 5);
1020 if (p == NULL)
1021 return -ENOMEM;
1022
1023 deviceID = ioread32(p);
1024 /* Tornado device */
1025 if (deviceID == 0x07000200) {
1026 number_uarts = ioread8(p + 4);
1027 printk(KERN_DEBUG
1028 "%d ports detected on Oxford PCI Express device\n",
1029 number_uarts);
1030 }
1031 pci_iounmap(dev, p);
1032 return number_uarts;
1033}
1034
1da177e4 1035static int
975a1a7d
RK		 1036pci_default_setup(struct serial_private *priv,
1037 const struct pciserial_board *board,
2655a2c7 1038 struct uart_8250_port *port, int idx)
1da177e4
LT		 1039{
1040 unsigned int bar, offset = board->first_offset, maxnr;
1041
1042 bar = FL_GET_BASE(board->flags);
1043 if (board->flags & FL_BASE_BARS)
1044 bar += idx;
1045 else
1046 offset += idx * board->uart_offset;
1047
2427ddd8
GKH		 1048 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1049 (board->reg_shift + 3);
1da177e4
LT		 1050
1051 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1052 return 1;
5756ee99 1053
70db3d91 1054 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1055}
1056
095e24b0
DB		 1057static int
1058ce4100_serial_setup(struct serial_private *priv,
1059 const struct pciserial_board *board,
2655a2c7 1060 struct uart_8250_port *port, int idx)
095e24b0
DB		 1061{
1062 int ret;
1063
1064 ret = setup_port(priv, port, 0, 0, board->reg_shift);
2655a2c7
AC		 1065 port->port.iotype = UPIO_MEM32;
1066 port->port.type = PORT_XSCALE;
1067 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1068 port->port.regshift = 2;
095e24b0
DB		 1069
1070 return ret;
1071}
1072
d9a0fbfd
AP		 1073static int
1074pci_omegapci_setup(struct serial_private *priv,
1798ca13 1075 const struct pciserial_board *board,
2655a2c7 1076 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1077{
1078 return setup_port(priv, port, 2, idx * 8, 0);
1079}
1080
b6adea33
MCC		 1081static int skip_tx_en_setup(struct serial_private *priv,
1082 const struct pciserial_board *board,
2655a2c7 1083 struct uart_8250_port *port, int idx)
b6adea33 1084{
2655a2c7 1085 port->port.flags |= UPF_NO_TXEN_TEST;
b6adea33
MCC		 1086 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1087 "[%04x:%04x] subsystem [%04x:%04x]\n",
1088 priv->dev->vendor,
1089 priv->dev->device,
1090 priv->dev->subsystem_vendor,
1091 priv->dev->subsystem_device);
1092
1093 return pci_default_setup(priv, board, port, idx);
1094}
1095
0ad372b9
SM		 1096static void kt_handle_break(struct uart_port *p)
1097{
1098 struct uart_8250_port *up =
1099 container_of(p, struct uart_8250_port, port);
1100 /*
1101 * On receipt of a BI, serial device in Intel ME (Intel
1102 * management engine) needs to have its fifos cleared for sane
1103 * SOL (Serial Over Lan) output.
1104 */
1105 serial8250_clear_and_reinit_fifos(up);
1106}
1107
1108static unsigned int kt_serial_in(struct uart_port *p, int offset)
1109{
1110 struct uart_8250_port *up =
1111 container_of(p, struct uart_8250_port, port);
1112 unsigned int val;
1113
1114 /*
1115 * When the Intel ME (management engine) gets reset its serial
1116 * port registers could return 0 momentarily. Functions like
1117 * serial8250_console_write, read and save the IER, perform
1118 * some operation and then restore it. In order to avoid
1119 * setting IER register inadvertently to 0, if the value read
1120 * is 0, double check with ier value in uart_8250_port and use
1121 * that instead. up->ier should be the same value as what is
1122 * currently configured.
1123 */
1124 val = inb(p->iobase + offset);
1125 if (offset == UART_IER) {
1126 if (val == 0)
1127 val = up->ier;
1128 }
1129 return val;
1130}
1131
bc02d15a
DW		 1132static int kt_serial_setup(struct serial_private *priv,
1133 const struct pciserial_board *board,
2655a2c7 1134 struct uart_8250_port *port, int idx)
bc02d15a 1135{
2655a2c7
AC		 1136 port->port.flags |= UPF_BUG_THRE;
1137 port->port.serial_in = kt_serial_in;
1138 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1139 return skip_tx_en_setup(priv, board, port, idx);
1140}
1141
eb7073db
TM		 1142static int pci_eg20t_init(struct pci_dev *dev)
1143{
1144#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1145 return -ENODEV;
1146#else
1147 return 0;
1148#endif
1149}
1150
06315348
SH		 1151static int
1152pci_xr17c154_setup(struct serial_private *priv,
1153 const struct pciserial_board *board,
2655a2c7 1154 struct uart_8250_port *port, int idx)
06315348 1155{
2655a2c7 1156 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1157 return pci_default_setup(priv, board, port, idx);
1158}
1159
1da177e4
LT		 1160#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1161#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1162#define PCI_DEVICE_ID_OCTPRO 0x0001
1163#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1164#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1165#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1166#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
78d70d48 1167#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1168#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1169#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1170#define PCI_DEVICE_ID_TITAN_200I 0x8028
1171#define PCI_DEVICE_ID_TITAN_400I 0x8048
1172#define PCI_DEVICE_ID_TITAN_800I 0x8088
1173#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1174#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1175#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1176#define PCI_DEVICE_ID_TITAN_100E 0xA010
1177#define PCI_DEVICE_ID_TITAN_200E 0xA012
1178#define PCI_DEVICE_ID_TITAN_400E 0xA013
1179#define PCI_DEVICE_ID_TITAN_800E 0xA014
1180#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1181#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1e9deb11
YY		 1182#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1183#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1184#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1185#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1186#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1187#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1188#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1189#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1da177e4 1190
b76c5a07
CB		 1191/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1192#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1193
1da177e4
LT		 1194/*
1195 * Master list of serial port init/setup/exit quirks.
1196 * This does not describe the general nature of the port.
1197 * (ie, baud base, number and location of ports, etc)
1198 *
1199 * This list is ordered alphabetically by vendor then device.
1200 * Specific entries must come before more generic entries.
1201 */
7a63ce5a 1202static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1203 /*
1204 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1205 */
1206 {
1207 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1208 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1209 .subvendor = PCI_ANY_ID,
1210 .subdevice = PCI_ANY_ID,
1211 .setup = addidata_apci7800_setup,
1212 },
1da177e4 1213 /*
61a116ef 1214 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1215 * It is not clear whether this applies to all products.
1216 */
1217 {
1218 .vendor = PCI_VENDOR_ID_AFAVLAB,
1219 .device = PCI_ANY_ID,
1220 .subvendor = PCI_ANY_ID,
1221 .subdevice = PCI_ANY_ID,
1222 .setup = afavlab_setup,
1223 },
1224 /*
1225 * HP Diva
1226 */
1227 {
1228 .vendor = PCI_VENDOR_ID_HP,
1229 .device = PCI_DEVICE_ID_HP_DIVA,
1230 .subvendor = PCI_ANY_ID,
1231 .subdevice = PCI_ANY_ID,
1232 .init = pci_hp_diva_init,
1233 .setup = pci_hp_diva_setup,
1234 },
1235 /*
1236 * Intel
1237 */
1238 {
1239 .vendor = PCI_VENDOR_ID_INTEL,
1240 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1241 .subvendor = 0xe4bf,
1242 .subdevice = PCI_ANY_ID,
1243 .init = pci_inteli960ni_init,
1244 .setup = pci_default_setup,
1245 },
b6adea33
MCC		 1246 {
1247 .vendor = PCI_VENDOR_ID_INTEL,
1248 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1249 .subvendor = PCI_ANY_ID,
1250 .subdevice = PCI_ANY_ID,
1251 .setup = skip_tx_en_setup,
1252 },
1253 {
1254 .vendor = PCI_VENDOR_ID_INTEL,
1255 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1256 .subvendor = PCI_ANY_ID,
1257 .subdevice = PCI_ANY_ID,
1258 .setup = skip_tx_en_setup,
1259 },
1260 {
1261 .vendor = PCI_VENDOR_ID_INTEL,
1262 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1263 .subvendor = PCI_ANY_ID,
1264 .subdevice = PCI_ANY_ID,
1265 .setup = skip_tx_en_setup,
1266 },
095e24b0
DB		 1267 {
1268 .vendor = PCI_VENDOR_ID_INTEL,
1269 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1270 .subvendor = PCI_ANY_ID,
1271 .subdevice = PCI_ANY_ID,
1272 .setup = ce4100_serial_setup,
1273 },
bc02d15a
DW		 1274 {
1275 .vendor = PCI_VENDOR_ID_INTEL,
1276 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1277 .subvendor = PCI_ANY_ID,
1278 .subdevice = PCI_ANY_ID,
1279 .setup = kt_serial_setup,
1280 },
84f8c6fc
NV		 1281 /*
1282 * ITE
1283 */
1284 {
1285 .vendor = PCI_VENDOR_ID_ITE,
1286 .device = PCI_DEVICE_ID_ITE_8872,
1287 .subvendor = PCI_ANY_ID,
1288 .subdevice = PCI_ANY_ID,
1289 .init = pci_ite887x_init,
1290 .setup = pci_default_setup,
1291 .exit = __devexit_p(pci_ite887x_exit),
1292 },
46a0fac9
SB		 1293 /*
1294 * National Instruments
1295 */
04bf7e74
WP		 1296 {
1297 .vendor = PCI_VENDOR_ID_NI,
1298 .device = PCI_DEVICE_ID_NI_PCI23216,
1299 .subvendor = PCI_ANY_ID,
1300 .subdevice = PCI_ANY_ID,
1301 .init = pci_ni8420_init,
1302 .setup = pci_default_setup,
1303 .exit = __devexit_p(pci_ni8420_exit),
1304 },
1305 {
1306 .vendor = PCI_VENDOR_ID_NI,
1307 .device = PCI_DEVICE_ID_NI_PCI2328,
1308 .subvendor = PCI_ANY_ID,
1309 .subdevice = PCI_ANY_ID,
1310 .init = pci_ni8420_init,
1311 .setup = pci_default_setup,
1312 .exit = __devexit_p(pci_ni8420_exit),
1313 },
1314 {
1315 .vendor = PCI_VENDOR_ID_NI,
1316 .device = PCI_DEVICE_ID_NI_PCI2324,
1317 .subvendor = PCI_ANY_ID,
1318 .subdevice = PCI_ANY_ID,
1319 .init = pci_ni8420_init,
1320 .setup = pci_default_setup,
1321 .exit = __devexit_p(pci_ni8420_exit),
1322 },
1323 {
1324 .vendor = PCI_VENDOR_ID_NI,
1325 .device = PCI_DEVICE_ID_NI_PCI2322,
1326 .subvendor = PCI_ANY_ID,
1327 .subdevice = PCI_ANY_ID,
1328 .init = pci_ni8420_init,
1329 .setup = pci_default_setup,
1330 .exit = __devexit_p(pci_ni8420_exit),
1331 },
1332 {
1333 .vendor = PCI_VENDOR_ID_NI,
1334 .device = PCI_DEVICE_ID_NI_PCI2324I,
1335 .subvendor = PCI_ANY_ID,
1336 .subdevice = PCI_ANY_ID,
1337 .init = pci_ni8420_init,
1338 .setup = pci_default_setup,
1339 .exit = __devexit_p(pci_ni8420_exit),
1340 },
1341 {
1342 .vendor = PCI_VENDOR_ID_NI,
1343 .device = PCI_DEVICE_ID_NI_PCI2322I,
1344 .subvendor = PCI_ANY_ID,
1345 .subdevice = PCI_ANY_ID,
1346 .init = pci_ni8420_init,
1347 .setup = pci_default_setup,
1348 .exit = __devexit_p(pci_ni8420_exit),
1349 },
1350 {
1351 .vendor = PCI_VENDOR_ID_NI,
1352 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1353 .subvendor = PCI_ANY_ID,
1354 .subdevice = PCI_ANY_ID,
1355 .init = pci_ni8420_init,
1356 .setup = pci_default_setup,
1357 .exit = __devexit_p(pci_ni8420_exit),
1358 },
1359 {
1360 .vendor = PCI_VENDOR_ID_NI,
1361 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1362 .subvendor = PCI_ANY_ID,
1363 .subdevice = PCI_ANY_ID,
1364 .init = pci_ni8420_init,
1365 .setup = pci_default_setup,
1366 .exit = __devexit_p(pci_ni8420_exit),
1367 },
1368 {
1369 .vendor = PCI_VENDOR_ID_NI,
1370 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1371 .subvendor = PCI_ANY_ID,
1372 .subdevice = PCI_ANY_ID,
1373 .init = pci_ni8420_init,
1374 .setup = pci_default_setup,
1375 .exit = __devexit_p(pci_ni8420_exit),
1376 },
1377 {
1378 .vendor = PCI_VENDOR_ID_NI,
1379 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1380 .subvendor = PCI_ANY_ID,
1381 .subdevice = PCI_ANY_ID,
1382 .init = pci_ni8420_init,
1383 .setup = pci_default_setup,
1384 .exit = __devexit_p(pci_ni8420_exit),
1385 },
1386 {
1387 .vendor = PCI_VENDOR_ID_NI,
1388 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1389 .subvendor = PCI_ANY_ID,
1390 .subdevice = PCI_ANY_ID,
1391 .init = pci_ni8420_init,
1392 .setup = pci_default_setup,
1393 .exit = __devexit_p(pci_ni8420_exit),
1394 },
1395 {
1396 .vendor = PCI_VENDOR_ID_NI,
1397 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1398 .subvendor = PCI_ANY_ID,
1399 .subdevice = PCI_ANY_ID,
1400 .init = pci_ni8420_init,
1401 .setup = pci_default_setup,
1402 .exit = __devexit_p(pci_ni8420_exit),
1403 },
46a0fac9
SB		 1404 {
1405 .vendor = PCI_VENDOR_ID_NI,
1406 .device = PCI_ANY_ID,
1407 .subvendor = PCI_ANY_ID,
1408 .subdevice = PCI_ANY_ID,
1409 .init = pci_ni8430_init,
1410 .setup = pci_ni8430_setup,
1411 .exit = __devexit_p(pci_ni8430_exit),
1412 },
1da177e4
LT		 1413 /*
1414 * Panacom
1415 */
1416 {
1417 .vendor = PCI_VENDOR_ID_PANACOM,
1418 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1419 .subvendor = PCI_ANY_ID,
1420 .subdevice = PCI_ANY_ID,
1421 .init = pci_plx9050_init,
1422 .setup = pci_default_setup,
1423 .exit = __devexit_p(pci_plx9050_exit),
5756ee99 1424 },
1da177e4
LT		 1425 {
1426 .vendor = PCI_VENDOR_ID_PANACOM,
1427 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1428 .subvendor = PCI_ANY_ID,
1429 .subdevice = PCI_ANY_ID,
1430 .init = pci_plx9050_init,
1431 .setup = pci_default_setup,
1432 .exit = __devexit_p(pci_plx9050_exit),
1433 },
1434 /*
1435 * PLX
1436 */
48212008
TH		 1437 {
1438 .vendor = PCI_VENDOR_ID_PLX,
1439 .device = PCI_DEVICE_ID_PLX_9030,
1440 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1441 .subdevice = PCI_ANY_ID,
1442 .setup = pci_default_setup,
1443 },
add7b58e
BH		 1444 {
1445 .vendor = PCI_VENDOR_ID_PLX,
1446 .device = PCI_DEVICE_ID_PLX_9050,
1447 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1448 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1449 .init = pci_plx9050_init,
1450 .setup = pci_default_setup,
1451 .exit = __devexit_p(pci_plx9050_exit),
1452 },
1da177e4
LT		 1453 {
1454 .vendor = PCI_VENDOR_ID_PLX,
1455 .device = PCI_DEVICE_ID_PLX_9050,
1456 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1457 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1458 .init = pci_plx9050_init,
1459 .setup = pci_default_setup,
1460 .exit = __devexit_p(pci_plx9050_exit),
1461 },
b76c5a07
CB		 1462 {
1463 .vendor = PCI_VENDOR_ID_PLX,
1464 .device = PCI_DEVICE_ID_PLX_9050,
1465 .subvendor = PCI_VENDOR_ID_PLX,
1466 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1467 .init = pci_plx9050_init,
1468 .setup = pci_default_setup,
1469 .exit = __devexit_p(pci_plx9050_exit),
1470 },
1da177e4
LT		 1471 {
1472 .vendor = PCI_VENDOR_ID_PLX,
1473 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1474 .subvendor = PCI_VENDOR_ID_PLX,
1475 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1476 .init = pci_plx9050_init,
1477 .setup = pci_default_setup,
1478 .exit = __devexit_p(pci_plx9050_exit),
1479 },
1480 /*
1481 * SBS Technologies, Inc., PMC-OCTALPRO 232
1482 */
1483 {
1484 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1485 .device = PCI_DEVICE_ID_OCTPRO,
1486 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1487 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1488 .init = sbs_init,
1489 .setup = sbs_setup,
1490 .exit = __devexit_p(sbs_exit),
1491 },
1492 /*
1493 * SBS Technologies, Inc., PMC-OCTALPRO 422
1494 */
1495 {
1496 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1497 .device = PCI_DEVICE_ID_OCTPRO,
1498 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1499 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1500 .init = sbs_init,
1501 .setup = sbs_setup,
1502 .exit = __devexit_p(sbs_exit),
1503 },
1504 /*
1505 * SBS Technologies, Inc., P-Octal 232
1506 */
1507 {
1508 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1509 .device = PCI_DEVICE_ID_OCTPRO,
1510 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1511 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1512 .init = sbs_init,
1513 .setup = sbs_setup,
1514 .exit = __devexit_p(sbs_exit),
1515 },
1516 /*
1517 * SBS Technologies, Inc., P-Octal 422
1518 */
1519 {
1520 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1521 .device = PCI_DEVICE_ID_OCTPRO,
1522 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1523 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1524 .init = sbs_init,
1525 .setup = sbs_setup,
1526 .exit = __devexit_p(sbs_exit),
1527 },
1da177e4 1528 /*
61a116ef 1529 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1530 */
1531 {
1532 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1533 .device = PCI_ANY_ID,
1da177e4
LT		 1534 .subvendor = PCI_ANY_ID,
1535 .subdevice = PCI_ANY_ID,
67d74b87 1536 .init = pci_siig_init,
3ec9c594 1537 .setup = pci_siig_setup,
1da177e4
LT		 1538 },
1539 /*
1540 * Titan cards
1541 */
1542 {
1543 .vendor = PCI_VENDOR_ID_TITAN,
1544 .device = PCI_DEVICE_ID_TITAN_400L,
1545 .subvendor = PCI_ANY_ID,
1546 .subdevice = PCI_ANY_ID,
1547 .setup = titan_400l_800l_setup,
1548 },
1549 {
1550 .vendor = PCI_VENDOR_ID_TITAN,
1551 .device = PCI_DEVICE_ID_TITAN_800L,
1552 .subvendor = PCI_ANY_ID,
1553 .subdevice = PCI_ANY_ID,
1554 .setup = titan_400l_800l_setup,
1555 },
1556 /*
1557 * Timedia cards
1558 */
1559 {
1560 .vendor = PCI_VENDOR_ID_TIMEDIA,
1561 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1562 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1563 .subdevice = PCI_ANY_ID,
b9b24558 1564 .probe = pci_timedia_probe,
1da177e4
LT		 1565 .init = pci_timedia_init,
1566 .setup = pci_timedia_setup,
1567 },
1568 {
1569 .vendor = PCI_VENDOR_ID_TIMEDIA,
1570 .device = PCI_ANY_ID,
1571 .subvendor = PCI_ANY_ID,
1572 .subdevice = PCI_ANY_ID,
1573 .setup = pci_timedia_setup,
1574 },
06315348
SH		 1575 /*
1576 * Exar cards
1577 */
1578 {
1579 .vendor = PCI_VENDOR_ID_EXAR,
1580 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1581 .subvendor = PCI_ANY_ID,
1582 .subdevice = PCI_ANY_ID,
1583 .setup = pci_xr17c154_setup,
1584 },
1585 {
1586 .vendor = PCI_VENDOR_ID_EXAR,
1587 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1588 .subvendor = PCI_ANY_ID,
1589 .subdevice = PCI_ANY_ID,
1590 .setup = pci_xr17c154_setup,
1591 },
1592 {
1593 .vendor = PCI_VENDOR_ID_EXAR,
1594 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1595 .subvendor = PCI_ANY_ID,
1596 .subdevice = PCI_ANY_ID,
1597 .setup = pci_xr17c154_setup,
1598 },
1da177e4
LT		 1599 /*
1600 * Xircom cards
1601 */
1602 {
1603 .vendor = PCI_VENDOR_ID_XIRCOM,
1604 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1605 .subvendor = PCI_ANY_ID,
1606 .subdevice = PCI_ANY_ID,
1607 .init = pci_xircom_init,
1608 .setup = pci_default_setup,
1609 },
1610 /*
61a116ef 1611 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1612 */
1613 {
1614 .vendor = PCI_VENDOR_ID_NETMOS,
1615 .device = PCI_ANY_ID,
1616 .subvendor = PCI_ANY_ID,
1617 .subdevice = PCI_ANY_ID,
1618 .init = pci_netmos_init,
7808edcd 1619 .setup = pci_netmos_9900_setup,
1da177e4 1620 },
9f2a036a 1621 /*
aa273ae5 1622 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 1623 */
1624 {
1625 .vendor = PCI_VENDOR_ID_OXSEMI,
1626 .device = PCI_ANY_ID,
1627 .subvendor = PCI_ANY_ID,
1628 .subdevice = PCI_ANY_ID,
1629 .init = pci_oxsemi_tornado_init,
1630 .setup = pci_default_setup,
1631 },
1632 {
1633 .vendor = PCI_VENDOR_ID_MAINPINE,
1634 .device = PCI_ANY_ID,
1635 .subvendor = PCI_ANY_ID,
1636 .subdevice = PCI_ANY_ID,
1637 .init = pci_oxsemi_tornado_init,
1638 .setup = pci_default_setup,
1639 },
aa273ae5
SK		 1640 {
1641 .vendor = PCI_VENDOR_ID_DIGI,
1642 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1643 .subvendor = PCI_SUBVENDOR_ID_IBM,
1644 .subdevice = PCI_ANY_ID,
1645 .init = pci_oxsemi_tornado_init,
1646 .setup = pci_default_setup,
1647 },
eb7073db
TM		 1648 {
1649 .vendor = PCI_VENDOR_ID_INTEL,
1650 .device = 0x8811,
aaa10eb1
AP		 1651 .subvendor = PCI_ANY_ID,
1652 .subdevice = PCI_ANY_ID,
eb7073db 1653 .init = pci_eg20t_init,
64d91cfa 1654 .setup = pci_default_setup,
eb7073db
TM		 1655 },
1656 {
1657 .vendor = PCI_VENDOR_ID_INTEL,
1658 .device = 0x8812,
aaa10eb1
AP		 1659 .subvendor = PCI_ANY_ID,
1660 .subdevice = PCI_ANY_ID,
eb7073db 1661 .init = pci_eg20t_init,
64d91cfa 1662 .setup = pci_default_setup,
eb7073db
TM		 1663 },
1664 {
1665 .vendor = PCI_VENDOR_ID_INTEL,
1666 .device = 0x8813,
aaa10eb1
AP		 1667 .subvendor = PCI_ANY_ID,
1668 .subdevice = PCI_ANY_ID,
eb7073db 1669 .init = pci_eg20t_init,
64d91cfa 1670 .setup = pci_default_setup,
eb7073db
TM		 1671 },
1672 {
1673 .vendor = PCI_VENDOR_ID_INTEL,
1674 .device = 0x8814,
aaa10eb1
AP		 1675 .subvendor = PCI_ANY_ID,
1676 .subdevice = PCI_ANY_ID,
eb7073db 1677 .init = pci_eg20t_init,
64d91cfa 1678 .setup = pci_default_setup,
eb7073db
TM		 1679 },
1680 {
1681 .vendor = 0x10DB,
1682 .device = 0x8027,
aaa10eb1
AP		 1683 .subvendor = PCI_ANY_ID,
1684 .subdevice = PCI_ANY_ID,
eb7073db 1685 .init = pci_eg20t_init,
64d91cfa 1686 .setup = pci_default_setup,
eb7073db
TM		 1687 },
1688 {
1689 .vendor = 0x10DB,
1690 .device = 0x8028,
aaa10eb1
AP		 1691 .subvendor = PCI_ANY_ID,
1692 .subdevice = PCI_ANY_ID,
eb7073db 1693 .init = pci_eg20t_init,
64d91cfa 1694 .setup = pci_default_setup,
eb7073db
TM		 1695 },
1696 {
1697 .vendor = 0x10DB,
1698 .device = 0x8029,
aaa10eb1
AP		 1699 .subvendor = PCI_ANY_ID,
1700 .subdevice = PCI_ANY_ID,
eb7073db 1701 .init = pci_eg20t_init,
64d91cfa 1702 .setup = pci_default_setup,
eb7073db
TM		 1703 },
1704 {
1705 .vendor = 0x10DB,
1706 .device = 0x800C,
aaa10eb1
AP		 1707 .subvendor = PCI_ANY_ID,
1708 .subdevice = PCI_ANY_ID,
eb7073db 1709 .init = pci_eg20t_init,
64d91cfa 1710 .setup = pci_default_setup,
eb7073db
TM		 1711 },
1712 {
1713 .vendor = 0x10DB,
1714 .device = 0x800D,
aaa10eb1
AP		 1715 .subvendor = PCI_ANY_ID,
1716 .subdevice = PCI_ANY_ID,
eb7073db 1717 .init = pci_eg20t_init,
64d91cfa 1718 .setup = pci_default_setup,
eb7073db 1719 },
d9a0fbfd
AP		 1720 /*
1721 * Cronyx Omega PCI (PLX-chip based)
1722 */
1723 {
1724 .vendor = PCI_VENDOR_ID_PLX,
1725 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1726 .subvendor = PCI_ANY_ID,
1727 .subdevice = PCI_ANY_ID,
1728 .setup = pci_omegapci_setup,
1729 },
1da177e4
LT		 1730 /*
1731 * Default "match everything" terminator entry
1732 */
1733 {
1734 .vendor = PCI_ANY_ID,
1735 .device = PCI_ANY_ID,
1736 .subvendor = PCI_ANY_ID,
1737 .subdevice = PCI_ANY_ID,
1738 .setup = pci_default_setup,
1739 }
1740};
1741
1742static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1743{
1744 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1745}
1746
1747static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1748{
1749 struct pci_serial_quirk *quirk;
1750
1751 for (quirk = pci_serial_quirks; ; quirk++)
1752 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1753 quirk_id_matches(quirk->device, dev->device) &&
1754 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1755 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1756 break;
1da177e4
LT		 1757 return quirk;
1758}
1759
dd68e88c 1760static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1761 const struct pciserial_board *board)
1da177e4
LT		 1762{
1763 if (board->flags & FL_NOIRQ)
1764 return 0;
1765 else
1766 return dev->irq;
1767}
1768
1769/*
1770 * This is the configuration table for all of the PCI serial boards
1771 * which we support. It is directly indexed by the pci_board_num_t enum
1772 * value, which is encoded in the pci_device_id PCI probe table's
1773 * driver_data member.
1774 *
1775 * The makeup of these names are:
26e92861 1776 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1777 *
26e92861
GH		 1778 * bn = PCI BAR number
1779 * bt = Index using PCI BARs
1780 * n = number of serial ports
1781 * baud = baud rate
1782 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1783 *
26e92861 1784 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1785 *
1da177e4
LT		 1786 * Please note: in theory if n = 1, _bt infix should make no difference.
1787 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1788 */
1789enum pci_board_num_t {
1790 pbn_default = 0,
1791
1792 pbn_b0_1_115200,
1793 pbn_b0_2_115200,
1794 pbn_b0_4_115200,
1795 pbn_b0_5_115200,
bf0df636 1796 pbn_b0_8_115200,
1da177e4
LT		 1797
1798 pbn_b0_1_921600,
1799 pbn_b0_2_921600,
1800 pbn_b0_4_921600,
1801
db1de159
DR		 1802 pbn_b0_2_1130000,
1803
fbc0dc0d
AP		 1804 pbn_b0_4_1152000,
1805
26e92861
GH		 1806 pbn_b0_2_1843200,
1807 pbn_b0_4_1843200,
1808
1809 pbn_b0_2_1843200_200,
1810 pbn_b0_4_1843200_200,
1811 pbn_b0_8_1843200_200,
1812
7106b4e3
LH		 1813 pbn_b0_1_4000000,
1814
1da177e4
LT		 1815 pbn_b0_bt_1_115200,
1816 pbn_b0_bt_2_115200,
ac6ec5b1 1817 pbn_b0_bt_4_115200,
1da177e4
LT		 1818 pbn_b0_bt_8_115200,
1819
1820 pbn_b0_bt_1_460800,
1821 pbn_b0_bt_2_460800,
1822 pbn_b0_bt_4_460800,
1823
1824 pbn_b0_bt_1_921600,
1825 pbn_b0_bt_2_921600,
1826 pbn_b0_bt_4_921600,
1827 pbn_b0_bt_8_921600,
1828
1829 pbn_b1_1_115200,
1830 pbn_b1_2_115200,
1831 pbn_b1_4_115200,
1832 pbn_b1_8_115200,
04bf7e74 1833 pbn_b1_16_115200,
1da177e4
LT		 1834
1835 pbn_b1_1_921600,
1836 pbn_b1_2_921600,
1837 pbn_b1_4_921600,
1838 pbn_b1_8_921600,
1839
26e92861
GH		 1840 pbn_b1_2_1250000,
1841
84f8c6fc 1842 pbn_b1_bt_1_115200,
04bf7e74
WP		 1843 pbn_b1_bt_2_115200,
1844 pbn_b1_bt_4_115200,
1845
1da177e4
LT		 1846 pbn_b1_bt_2_921600,
1847
1848 pbn_b1_1_1382400,
1849 pbn_b1_2_1382400,
1850 pbn_b1_4_1382400,
1851 pbn_b1_8_1382400,
1852
1853 pbn_b2_1_115200,
737c1756 1854 pbn_b2_2_115200,
a9cccd34 1855 pbn_b2_4_115200,
1da177e4
LT		 1856 pbn_b2_8_115200,
1857
1858 pbn_b2_1_460800,
1859 pbn_b2_4_460800,
1860 pbn_b2_8_460800,
1861 pbn_b2_16_460800,
1862
1863 pbn_b2_1_921600,
1864 pbn_b2_4_921600,
1865 pbn_b2_8_921600,
1866
e847003f
LB		 1867 pbn_b2_8_1152000,
1868
1da177e4
LT		 1869 pbn_b2_bt_1_115200,
1870 pbn_b2_bt_2_115200,
1871 pbn_b2_bt_4_115200,
1872
1873 pbn_b2_bt_2_921600,
1874 pbn_b2_bt_4_921600,
1875
d9004eb4 1876 pbn_b3_2_115200,
1da177e4
LT		 1877 pbn_b3_4_115200,
1878 pbn_b3_8_115200,
1879
66169ad1
YY		 1880 pbn_b4_bt_2_921600,
1881 pbn_b4_bt_4_921600,
1882 pbn_b4_bt_8_921600,
1883
1da177e4
LT		 1884 /*
1885 * Board-specific versions.
1886 */
1887 pbn_panacom,
1888 pbn_panacom2,
1889 pbn_panacom4,
1890 pbn_plx_romulus,
1891 pbn_oxsemi,
7106b4e3
LH		 1892 pbn_oxsemi_1_4000000,
1893 pbn_oxsemi_2_4000000,
1894 pbn_oxsemi_4_4000000,
1895 pbn_oxsemi_8_4000000,
1da177e4
LT		 1896 pbn_intel_i960,
1897 pbn_sgi_ioc3,
1da177e4
LT		 1898 pbn_computone_4,
1899 pbn_computone_6,
1900 pbn_computone_8,
1901 pbn_sbsxrsio,
1902 pbn_exar_XR17C152,
1903 pbn_exar_XR17C154,
1904 pbn_exar_XR17C158,
c68d2b15 1905 pbn_exar_ibm_saturn,
aa798505 1906 pbn_pasemi_1682M,
46a0fac9
SB		 1907 pbn_ni8430_2,
1908 pbn_ni8430_4,
1909 pbn_ni8430_8,
1910 pbn_ni8430_16,
1b62cbf2
KJ		 1911 pbn_ADDIDATA_PCIe_1_3906250,
1912 pbn_ADDIDATA_PCIe_2_3906250,
1913 pbn_ADDIDATA_PCIe_4_3906250,
1914 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 1915 pbn_ce4100_1_115200,
d9a0fbfd 1916 pbn_omegapci,
7808edcd 1917 pbn_NETMOS9900_2s_115200,
1da177e4
LT		 1918};
1919
1920/*
1921 * uart_offset - the space between channels
1922 * reg_shift - describes how the UART registers are mapped
1923 * to PCI memory by the card.
1924 * For example IER register on SBS, Inc. PMC-OctPro is located at
1925 * offset 0x10 from the UART base, while UART_IER is defined as 1
1926 * in include/linux/serial_reg.h,
1927 * see first lines of serial_in() and serial_out() in 8250.c
1928*/
1929
1c7c1fe5 1930static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1931 [pbn_default] = {
1932 .flags = FL_BASE0,
1933 .num_ports = 1,
1934 .base_baud = 115200,
1935 .uart_offset = 8,
1936 },
1937 [pbn_b0_1_115200] = {
1938 .flags = FL_BASE0,
1939 .num_ports = 1,
1940 .base_baud = 115200,
1941 .uart_offset = 8,
1942 },
1943 [pbn_b0_2_115200] = {
1944 .flags = FL_BASE0,
1945 .num_ports = 2,
1946 .base_baud = 115200,
1947 .uart_offset = 8,
1948 },
1949 [pbn_b0_4_115200] = {
1950 .flags = FL_BASE0,
1951 .num_ports = 4,
1952 .base_baud = 115200,
1953 .uart_offset = 8,
1954 },
1955 [pbn_b0_5_115200] = {
1956 .flags = FL_BASE0,
1957 .num_ports = 5,
1958 .base_baud = 115200,
1959 .uart_offset = 8,
1960 },
bf0df636
AC		 1961 [pbn_b0_8_115200] = {
1962 .flags = FL_BASE0,
1963 .num_ports = 8,
1964 .base_baud = 115200,
1965 .uart_offset = 8,
1966 },
1da177e4
LT		 1967 [pbn_b0_1_921600] = {
1968 .flags = FL_BASE0,
1969 .num_ports = 1,
1970 .base_baud = 921600,
1971 .uart_offset = 8,
1972 },
1973 [pbn_b0_2_921600] = {
1974 .flags = FL_BASE0,
1975 .num_ports = 2,
1976 .base_baud = 921600,
1977 .uart_offset = 8,
1978 },
1979 [pbn_b0_4_921600] = {
1980 .flags = FL_BASE0,
1981 .num_ports = 4,
1982 .base_baud = 921600,
1983 .uart_offset = 8,
1984 },
db1de159
DR		 1985
1986 [pbn_b0_2_1130000] = {
1987 .flags = FL_BASE0,
1988 .num_ports = 2,
1989 .base_baud = 1130000,
1990 .uart_offset = 8,
1991 },
1992
fbc0dc0d
AP		 1993 [pbn_b0_4_1152000] = {
1994 .flags = FL_BASE0,
1995 .num_ports = 4,
1996 .base_baud = 1152000,
1997 .uart_offset = 8,
1998 },
1da177e4 1999
26e92861
GH		 2000 [pbn_b0_2_1843200] = {
2001 .flags = FL_BASE0,
2002 .num_ports = 2,
2003 .base_baud = 1843200,
2004 .uart_offset = 8,
2005 },
2006 [pbn_b0_4_1843200] = {
2007 .flags = FL_BASE0,
2008 .num_ports = 4,
2009 .base_baud = 1843200,
2010 .uart_offset = 8,
2011 },
2012
2013 [pbn_b0_2_1843200_200] = {
2014 .flags = FL_BASE0,
2015 .num_ports = 2,
2016 .base_baud = 1843200,
2017 .uart_offset = 0x200,
2018 },
2019 [pbn_b0_4_1843200_200] = {
2020 .flags = FL_BASE0,
2021 .num_ports = 4,
2022 .base_baud = 1843200,
2023 .uart_offset = 0x200,
2024 },
2025 [pbn_b0_8_1843200_200] = {
2026 .flags = FL_BASE0,
2027 .num_ports = 8,
2028 .base_baud = 1843200,
2029 .uart_offset = 0x200,
2030 },
7106b4e3
LH		 2031 [pbn_b0_1_4000000] = {
2032 .flags = FL_BASE0,
2033 .num_ports = 1,
2034 .base_baud = 4000000,
2035 .uart_offset = 8,
2036 },
26e92861 2037
1da177e4
LT		 2038 [pbn_b0_bt_1_115200] = {
2039 .flags = FL_BASE0|FL_BASE_BARS,
2040 .num_ports = 1,
2041 .base_baud = 115200,
2042 .uart_offset = 8,
2043 },
2044 [pbn_b0_bt_2_115200] = {
2045 .flags = FL_BASE0|FL_BASE_BARS,
2046 .num_ports = 2,
2047 .base_baud = 115200,
2048 .uart_offset = 8,
2049 },
ac6ec5b1
IS		 2050 [pbn_b0_bt_4_115200] = {
2051 .flags = FL_BASE0|FL_BASE_BARS,
2052 .num_ports = 4,
2053 .base_baud = 115200,
2054 .uart_offset = 8,
2055 },
1da177e4
LT		 2056 [pbn_b0_bt_8_115200] = {
2057 .flags = FL_BASE0|FL_BASE_BARS,
2058 .num_ports = 8,
2059 .base_baud = 115200,
2060 .uart_offset = 8,
2061 },
2062
2063 [pbn_b0_bt_1_460800] = {
2064 .flags = FL_BASE0|FL_BASE_BARS,
2065 .num_ports = 1,
2066 .base_baud = 460800,
2067 .uart_offset = 8,
2068 },
2069 [pbn_b0_bt_2_460800] = {
2070 .flags = FL_BASE0|FL_BASE_BARS,
2071 .num_ports = 2,
2072 .base_baud = 460800,
2073 .uart_offset = 8,
2074 },
2075 [pbn_b0_bt_4_460800] = {
2076 .flags = FL_BASE0|FL_BASE_BARS,
2077 .num_ports = 4,
2078 .base_baud = 460800,
2079 .uart_offset = 8,
2080 },
2081
2082 [pbn_b0_bt_1_921600] = {
2083 .flags = FL_BASE0|FL_BASE_BARS,
2084 .num_ports = 1,
2085 .base_baud = 921600,
2086 .uart_offset = 8,
2087 },
2088 [pbn_b0_bt_2_921600] = {
2089 .flags = FL_BASE0|FL_BASE_BARS,
2090 .num_ports = 2,
2091 .base_baud = 921600,
2092 .uart_offset = 8,
2093 },
2094 [pbn_b0_bt_4_921600] = {
2095 .flags = FL_BASE0|FL_BASE_BARS,
2096 .num_ports = 4,
2097 .base_baud = 921600,
2098 .uart_offset = 8,
2099 },
2100 [pbn_b0_bt_8_921600] = {
2101 .flags = FL_BASE0|FL_BASE_BARS,
2102 .num_ports = 8,
2103 .base_baud = 921600,
2104 .uart_offset = 8,
2105 },
2106
2107 [pbn_b1_1_115200] = {
2108 .flags = FL_BASE1,
2109 .num_ports = 1,
2110 .base_baud = 115200,
2111 .uart_offset = 8,
2112 },
2113 [pbn_b1_2_115200] = {
2114 .flags = FL_BASE1,
2115 .num_ports = 2,
2116 .base_baud = 115200,
2117 .uart_offset = 8,
2118 },
2119 [pbn_b1_4_115200] = {
2120 .flags = FL_BASE1,
2121 .num_ports = 4,
2122 .base_baud = 115200,
2123 .uart_offset = 8,
2124 },
2125 [pbn_b1_8_115200] = {
2126 .flags = FL_BASE1,
2127 .num_ports = 8,
2128 .base_baud = 115200,
2129 .uart_offset = 8,
2130 },
04bf7e74
WP		 2131 [pbn_b1_16_115200] = {
2132 .flags = FL_BASE1,
2133 .num_ports = 16,
2134 .base_baud = 115200,
2135 .uart_offset = 8,
2136 },
1da177e4
LT		 2137
2138 [pbn_b1_1_921600] = {
2139 .flags = FL_BASE1,
2140 .num_ports = 1,
2141 .base_baud = 921600,
2142 .uart_offset = 8,
2143 },
2144 [pbn_b1_2_921600] = {
2145 .flags = FL_BASE1,
2146 .num_ports = 2,
2147 .base_baud = 921600,
2148 .uart_offset = 8,
2149 },
2150 [pbn_b1_4_921600] = {
2151 .flags = FL_BASE1,
2152 .num_ports = 4,
2153 .base_baud = 921600,
2154 .uart_offset = 8,
2155 },
2156 [pbn_b1_8_921600] = {
2157 .flags = FL_BASE1,
2158 .num_ports = 8,
2159 .base_baud = 921600,
2160 .uart_offset = 8,
2161 },
26e92861
GH		 2162 [pbn_b1_2_1250000] = {
2163 .flags = FL_BASE1,
2164 .num_ports = 2,
2165 .base_baud = 1250000,
2166 .uart_offset = 8,
2167 },
1da177e4 2168
84f8c6fc
NV		 2169 [pbn_b1_bt_1_115200] = {
2170 .flags = FL_BASE1|FL_BASE_BARS,
2171 .num_ports = 1,
2172 .base_baud = 115200,
2173 .uart_offset = 8,
2174 },
04bf7e74
WP		 2175 [pbn_b1_bt_2_115200] = {
2176 .flags = FL_BASE1|FL_BASE_BARS,
2177 .num_ports = 2,
2178 .base_baud = 115200,
2179 .uart_offset = 8,
2180 },
2181 [pbn_b1_bt_4_115200] = {
2182 .flags = FL_BASE1|FL_BASE_BARS,
2183 .num_ports = 4,
2184 .base_baud = 115200,
2185 .uart_offset = 8,
2186 },
84f8c6fc 2187
1da177e4
LT		 2188 [pbn_b1_bt_2_921600] = {
2189 .flags = FL_BASE1|FL_BASE_BARS,
2190 .num_ports = 2,
2191 .base_baud = 921600,
2192 .uart_offset = 8,
2193 },
2194
2195 [pbn_b1_1_1382400] = {
2196 .flags = FL_BASE1,
2197 .num_ports = 1,
2198 .base_baud = 1382400,
2199 .uart_offset = 8,
2200 },
2201 [pbn_b1_2_1382400] = {
2202 .flags = FL_BASE1,
2203 .num_ports = 2,
2204 .base_baud = 1382400,
2205 .uart_offset = 8,
2206 },
2207 [pbn_b1_4_1382400] = {
2208 .flags = FL_BASE1,
2209 .num_ports = 4,
2210 .base_baud = 1382400,
2211 .uart_offset = 8,
2212 },
2213 [pbn_b1_8_1382400] = {
2214 .flags = FL_BASE1,
2215 .num_ports = 8,
2216 .base_baud = 1382400,
2217 .uart_offset = 8,
2218 },
2219
2220 [pbn_b2_1_115200] = {
2221 .flags = FL_BASE2,
2222 .num_ports = 1,
2223 .base_baud = 115200,
2224 .uart_offset = 8,
2225 },
737c1756
PH		 2226 [pbn_b2_2_115200] = {
2227 .flags = FL_BASE2,
2228 .num_ports = 2,
2229 .base_baud = 115200,
2230 .uart_offset = 8,
2231 },
a9cccd34
MF		 2232 [pbn_b2_4_115200] = {
2233 .flags = FL_BASE2,
2234 .num_ports = 4,
2235 .base_baud = 115200,
2236 .uart_offset = 8,
2237 },
1da177e4
LT		 2238 [pbn_b2_8_115200] = {
2239 .flags = FL_BASE2,
2240 .num_ports = 8,
2241 .base_baud = 115200,
2242 .uart_offset = 8,
2243 },
2244
2245 [pbn_b2_1_460800] = {
2246 .flags = FL_BASE2,
2247 .num_ports = 1,
2248 .base_baud = 460800,
2249 .uart_offset = 8,
2250 },
2251 [pbn_b2_4_460800] = {
2252 .flags = FL_BASE2,
2253 .num_ports = 4,
2254 .base_baud = 460800,
2255 .uart_offset = 8,
2256 },
2257 [pbn_b2_8_460800] = {
2258 .flags = FL_BASE2,
2259 .num_ports = 8,
2260 .base_baud = 460800,
2261 .uart_offset = 8,
2262 },
2263 [pbn_b2_16_460800] = {
2264 .flags = FL_BASE2,
2265 .num_ports = 16,
2266 .base_baud = 460800,
2267 .uart_offset = 8,
2268 },
2269
2270 [pbn_b2_1_921600] = {
2271 .flags = FL_BASE2,
2272 .num_ports = 1,
2273 .base_baud = 921600,
2274 .uart_offset = 8,
2275 },
2276 [pbn_b2_4_921600] = {
2277 .flags = FL_BASE2,
2278 .num_ports = 4,
2279 .base_baud = 921600,
2280 .uart_offset = 8,
2281 },
2282 [pbn_b2_8_921600] = {
2283 .flags = FL_BASE2,
2284 .num_ports = 8,
2285 .base_baud = 921600,
2286 .uart_offset = 8,
2287 },
2288
e847003f
LB		 2289 [pbn_b2_8_1152000] = {
2290 .flags = FL_BASE2,
2291 .num_ports = 8,
2292 .base_baud = 1152000,
2293 .uart_offset = 8,
2294 },
2295
1da177e4
LT		 2296 [pbn_b2_bt_1_115200] = {
2297 .flags = FL_BASE2|FL_BASE_BARS,
2298 .num_ports = 1,
2299 .base_baud = 115200,
2300 .uart_offset = 8,
2301 },
2302 [pbn_b2_bt_2_115200] = {
2303 .flags = FL_BASE2|FL_BASE_BARS,
2304 .num_ports = 2,
2305 .base_baud = 115200,
2306 .uart_offset = 8,
2307 },
2308 [pbn_b2_bt_4_115200] = {
2309 .flags = FL_BASE2|FL_BASE_BARS,
2310 .num_ports = 4,
2311 .base_baud = 115200,
2312 .uart_offset = 8,
2313 },
2314
2315 [pbn_b2_bt_2_921600] = {
2316 .flags = FL_BASE2|FL_BASE_BARS,
2317 .num_ports = 2,
2318 .base_baud = 921600,
2319 .uart_offset = 8,
2320 },
2321 [pbn_b2_bt_4_921600] = {
2322 .flags = FL_BASE2|FL_BASE_BARS,
2323 .num_ports = 4,
2324 .base_baud = 921600,
2325 .uart_offset = 8,
2326 },
2327
d9004eb4
ABL		 2328 [pbn_b3_2_115200] = {
2329 .flags = FL_BASE3,
2330 .num_ports = 2,
2331 .base_baud = 115200,
2332 .uart_offset = 8,
2333 },
1da177e4
LT		 2334 [pbn_b3_4_115200] = {
2335 .flags = FL_BASE3,
2336 .num_ports = 4,
2337 .base_baud = 115200,
2338 .uart_offset = 8,
2339 },
2340 [pbn_b3_8_115200] = {
2341 .flags = FL_BASE3,
2342 .num_ports = 8,
2343 .base_baud = 115200,
2344 .uart_offset = 8,
2345 },
2346
66169ad1
YY		 2347 [pbn_b4_bt_2_921600] = {
2348 .flags = FL_BASE4,
2349 .num_ports = 2,
2350 .base_baud = 921600,
2351 .uart_offset = 8,
2352 },
2353 [pbn_b4_bt_4_921600] = {
2354 .flags = FL_BASE4,
2355 .num_ports = 4,
2356 .base_baud = 921600,
2357 .uart_offset = 8,
2358 },
2359 [pbn_b4_bt_8_921600] = {
2360 .flags = FL_BASE4,
2361 .num_ports = 8,
2362 .base_baud = 921600,
2363 .uart_offset = 8,
2364 },
2365
1da177e4
LT		 2366 /*
2367 * Entries following this are board-specific.
2368 */
2369
2370 /*
2371 * Panacom - IOMEM
2372 */
2373 [pbn_panacom] = {
2374 .flags = FL_BASE2,
2375 .num_ports = 2,
2376 .base_baud = 921600,
2377 .uart_offset = 0x400,
2378 .reg_shift = 7,
2379 },
2380 [pbn_panacom2] = {
2381 .flags = FL_BASE2|FL_BASE_BARS,
2382 .num_ports = 2,
2383 .base_baud = 921600,
2384 .uart_offset = 0x400,
2385 .reg_shift = 7,
2386 },
2387 [pbn_panacom4] = {
2388 .flags = FL_BASE2|FL_BASE_BARS,
2389 .num_ports = 4,
2390 .base_baud = 921600,
2391 .uart_offset = 0x400,
2392 .reg_shift = 7,
2393 },
2394
2395 /* I think this entry is broken - the first_offset looks wrong --rmk */
2396 [pbn_plx_romulus] = {
2397 .flags = FL_BASE2,
2398 .num_ports = 4,
2399 .base_baud = 921600,
2400 .uart_offset = 8 << 2,
2401 .reg_shift = 2,
2402 .first_offset = 0x03,
2403 },
2404
2405 /*
2406 * This board uses the size of PCI Base region 0 to
2407 * signal now many ports are available
2408 */
2409 [pbn_oxsemi] = {
2410 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2411 .num_ports = 32,
2412 .base_baud = 115200,
2413 .uart_offset = 8,
2414 },
7106b4e3
LH		 2415 [pbn_oxsemi_1_4000000] = {
2416 .flags = FL_BASE0,
2417 .num_ports = 1,
2418 .base_baud = 4000000,
2419 .uart_offset = 0x200,
2420 .first_offset = 0x1000,
2421 },
2422 [pbn_oxsemi_2_4000000] = {
2423 .flags = FL_BASE0,
2424 .num_ports = 2,
2425 .base_baud = 4000000,
2426 .uart_offset = 0x200,
2427 .first_offset = 0x1000,
2428 },
2429 [pbn_oxsemi_4_4000000] = {
2430 .flags = FL_BASE0,
2431 .num_ports = 4,
2432 .base_baud = 4000000,
2433 .uart_offset = 0x200,
2434 .first_offset = 0x1000,
2435 },
2436 [pbn_oxsemi_8_4000000] = {
2437 .flags = FL_BASE0,
2438 .num_ports = 8,
2439 .base_baud = 4000000,
2440 .uart_offset = 0x200,
2441 .first_offset = 0x1000,
2442 },
2443
1da177e4
LT		 2444
2445 /*
2446 * EKF addition for i960 Boards form EKF with serial port.
2447 * Max 256 ports.
2448 */
2449 [pbn_intel_i960] = {
2450 .flags = FL_BASE0,
2451 .num_ports = 32,
2452 .base_baud = 921600,
2453 .uart_offset = 8 << 2,
2454 .reg_shift = 2,
2455 .first_offset = 0x10000,
2456 },
2457 [pbn_sgi_ioc3] = {
2458 .flags = FL_BASE0|FL_NOIRQ,
2459 .num_ports = 1,
2460 .base_baud = 458333,
2461 .uart_offset = 8,
2462 .reg_shift = 0,
2463 .first_offset = 0x20178,
2464 },
2465
1da177e4
LT		 2466 /*
2467 * Computone - uses IOMEM.
2468 */
2469 [pbn_computone_4] = {
2470 .flags = FL_BASE0,
2471 .num_ports = 4,
2472 .base_baud = 921600,
2473 .uart_offset = 0x40,
2474 .reg_shift = 2,
2475 .first_offset = 0x200,
2476 },
2477 [pbn_computone_6] = {
2478 .flags = FL_BASE0,
2479 .num_ports = 6,
2480 .base_baud = 921600,
2481 .uart_offset = 0x40,
2482 .reg_shift = 2,
2483 .first_offset = 0x200,
2484 },
2485 [pbn_computone_8] = {
2486 .flags = FL_BASE0,
2487 .num_ports = 8,
2488 .base_baud = 921600,
2489 .uart_offset = 0x40,
2490 .reg_shift = 2,
2491 .first_offset = 0x200,
2492 },
2493 [pbn_sbsxrsio] = {
2494 .flags = FL_BASE0,
2495 .num_ports = 8,
2496 .base_baud = 460800,
2497 .uart_offset = 256,
2498 .reg_shift = 4,
2499 },
2500 /*
2501 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2502 * Only basic 16550A support.
2503 * XR17C15[24] are not tested, but they should work.
2504 */
2505 [pbn_exar_XR17C152] = {
2506 .flags = FL_BASE0,
2507 .num_ports = 2,
2508 .base_baud = 921600,
2509 .uart_offset = 0x200,
2510 },
2511 [pbn_exar_XR17C154] = {
2512 .flags = FL_BASE0,
2513 .num_ports = 4,
2514 .base_baud = 921600,
2515 .uart_offset = 0x200,
2516 },
2517 [pbn_exar_XR17C158] = {
2518 .flags = FL_BASE0,
2519 .num_ports = 8,
2520 .base_baud = 921600,
2521 .uart_offset = 0x200,
2522 },
c68d2b15
BH		 2523 [pbn_exar_ibm_saturn] = {
2524 .flags = FL_BASE0,
2525 .num_ports = 1,
2526 .base_baud = 921600,
2527 .uart_offset = 0x200,
2528 },
2529
aa798505
OJ		 2530 /*
2531 * PA Semi PWRficient PA6T-1682M on-chip UART
2532 */
2533 [pbn_pasemi_1682M] = {
2534 .flags = FL_BASE0,
2535 .num_ports = 1,
2536 .base_baud = 8333333,
2537 },
46a0fac9
SB		 2538 /*
2539 * National Instruments 843x
2540 */
2541 [pbn_ni8430_16] = {
2542 .flags = FL_BASE0,
2543 .num_ports = 16,
2544 .base_baud = 3686400,
2545 .uart_offset = 0x10,
2546 .first_offset = 0x800,
2547 },
2548 [pbn_ni8430_8] = {
2549 .flags = FL_BASE0,
2550 .num_ports = 8,
2551 .base_baud = 3686400,
2552 .uart_offset = 0x10,
2553 .first_offset = 0x800,
2554 },
2555 [pbn_ni8430_4] = {
2556 .flags = FL_BASE0,
2557 .num_ports = 4,
2558 .base_baud = 3686400,
2559 .uart_offset = 0x10,
2560 .first_offset = 0x800,
2561 },
2562 [pbn_ni8430_2] = {
2563 .flags = FL_BASE0,
2564 .num_ports = 2,
2565 .base_baud = 3686400,
2566 .uart_offset = 0x10,
2567 .first_offset = 0x800,
2568 },
1b62cbf2
KJ		 2569 /*
2570 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2571 */
2572 [pbn_ADDIDATA_PCIe_1_3906250] = {
2573 .flags = FL_BASE0,
2574 .num_ports = 1,
2575 .base_baud = 3906250,
2576 .uart_offset = 0x200,
2577 .first_offset = 0x1000,
2578 },
2579 [pbn_ADDIDATA_PCIe_2_3906250] = {
2580 .flags = FL_BASE0,
2581 .num_ports = 2,
2582 .base_baud = 3906250,
2583 .uart_offset = 0x200,
2584 .first_offset = 0x1000,
2585 },
2586 [pbn_ADDIDATA_PCIe_4_3906250] = {
2587 .flags = FL_BASE0,
2588 .num_ports = 4,
2589 .base_baud = 3906250,
2590 .uart_offset = 0x200,
2591 .first_offset = 0x1000,
2592 },
2593 [pbn_ADDIDATA_PCIe_8_3906250] = {
2594 .flags = FL_BASE0,
2595 .num_ports = 8,
2596 .base_baud = 3906250,
2597 .uart_offset = 0x200,
2598 .first_offset = 0x1000,
2599 },
095e24b0
DB		 2600 [pbn_ce4100_1_115200] = {
2601 .flags = FL_BASE0,
2602 .num_ports = 1,
2603 .base_baud = 921600,
2604 .reg_shift = 2,
2605 },
d9a0fbfd
AP		 2606 [pbn_omegapci] = {
2607 .flags = FL_BASE0,
2608 .num_ports = 8,
2609 .base_baud = 115200,
2610 .uart_offset = 0x200,
2611 },
7808edcd
NG		 2612 [pbn_NETMOS9900_2s_115200] = {
2613 .flags = FL_BASE0,
2614 .num_ports = 2,
2615 .base_baud = 115200,
2616 },
1da177e4
LT		 2617};
2618
436bbd43 2619static const struct pci_device_id softmodem_blacklist[] = {
5756ee99 2620 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 2621 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2622 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
436bbd43
CS		 2623};
2624
1da177e4
LT		 2625/*
2626 * Given a complete unknown PCI device, try to use some heuristics to
2627 * guess what the configuration might be, based on the pitiful PCI
2628 * serial specs. Returns 0 on success, 1 on failure.
2629 */
2630static int __devinit
1c7c1fe5 2631serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 2632{
436bbd43 2633 const struct pci_device_id *blacklist;
1da177e4 2634 int num_iomem, num_port, first_port = -1, i;
5756ee99 2635
1da177e4
LT		 2636 /*
2637 * If it is not a communications device or the programming
2638 * interface is greater than 6, give up.
2639 *
2640 * (Should we try to make guesses for multiport serial devices
5756ee99 2641 * later?)
1da177e4
LT		 2642 */
2643 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2644 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2645 (dev->class & 0xff) > 6)
2646 return -ENODEV;
2647
436bbd43
CS		 2648 /*
2649 * Do not access blacklisted devices that are known not to
2650 * feature serial ports.
2651 */
2652 for (blacklist = softmodem_blacklist;
2653 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2654 blacklist++) {
2655 if (dev->vendor == blacklist->vendor &&
2656 dev->device == blacklist->device)
2657 return -ENODEV;
2658 }
2659
1da177e4
LT		 2660 num_iomem = num_port = 0;
2661 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2662 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2663 num_port++;
2664 if (first_port == -1)
2665 first_port = i;
2666 }
2667 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2668 num_iomem++;
2669 }
2670
2671 /*
2672 * If there is 1 or 0 iomem regions, and exactly one port,
2673 * use it. We guess the number of ports based on the IO
2674 * region size.
2675 */
2676 if (num_iomem <= 1 && num_port == 1) {
2677 board->flags = first_port;
2678 board->num_ports = pci_resource_len(dev, first_port) / 8;
2679 return 0;
2680 }
2681
2682 /*
2683 * Now guess if we've got a board which indexes by BARs.
2684 * Each IO BAR should be 8 bytes, and they should follow
2685 * consecutively.
2686 */
2687 first_port = -1;
2688 num_port = 0;
2689 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2690 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2691 pci_resource_len(dev, i) == 8 &&
2692 (first_port == -1 || (first_port + num_port) == i)) {
2693 num_port++;
2694 if (first_port == -1)
2695 first_port = i;
2696 }
2697 }
2698
2699 if (num_port > 1) {
2700 board->flags = first_port | FL_BASE_BARS;
2701 board->num_ports = num_port;
2702 return 0;
2703 }
2704
2705 return -ENODEV;
2706}
2707
2708static inline int
975a1a7d
RK		 2709serial_pci_matches(const struct pciserial_board *board,
2710 const struct pciserial_board *guessed)
1da177e4
LT		 2711{
2712 return
2713 board->num_ports == guessed->num_ports &&
2714 board->base_baud == guessed->base_baud &&
2715 board->uart_offset == guessed->uart_offset &&
2716 board->reg_shift == guessed->reg_shift &&
2717 board->first_offset == guessed->first_offset;
2718}
2719
241fc436 2720struct serial_private *
975a1a7d 2721pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 2722{
2655a2c7 2723 struct uart_8250_port uart;
1da177e4 2724 struct serial_private *priv;
1da177e4
LT		 2725 struct pci_serial_quirk *quirk;
2726 int rc, nr_ports, i;
2727
1da177e4
LT		 2728 nr_ports = board->num_ports;
2729
2730 /*
2731 * Find an init and setup quirks.
2732 */
2733 quirk = find_quirk(dev);
2734
2735 /*
2736 * Run the new-style initialization function.
2737 * The initialization function returns:
2738 * <0 - error
2739 * 0 - use board->num_ports
2740 * >0 - number of ports
2741 */
2742 if (quirk->init) {
2743 rc = quirk->init(dev);
241fc436
RK		 2744 if (rc < 0) {
2745 priv = ERR_PTR(rc);
2746 goto err_out;
2747 }
1da177e4
LT		 2748 if (rc)
2749 nr_ports = rc;
2750 }
2751
8f31bb39 2752 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 2753 sizeof(unsigned int) * nr_ports,
2754 GFP_KERNEL);
2755 if (!priv) {
241fc436
RK		 2756 priv = ERR_PTR(-ENOMEM);
2757 goto err_deinit;
1da177e4
LT		 2758 }
2759
70db3d91 2760 priv->dev = dev;
1da177e4 2761 priv->quirk = quirk;
1da177e4 2762
2655a2c7
AC		 2763 memset(&uart, 0, sizeof(uart));
2764 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2765 uart.port.uartclk = board->base_baud * 16;
2766 uart.port.irq = get_pci_irq(dev, board);
2767 uart.port.dev = &dev->dev;
72ce9a83 2768
1da177e4 2769 for (i = 0; i < nr_ports; i++) {
2655a2c7 2770 if (quirk->setup(priv, board, &uart, i))
1da177e4 2771 break;
72ce9a83 2772
1da177e4 2773#ifdef SERIAL_DEBUG_PCI
80647b95 2774 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2655a2c7 2775 uart.port.iobase, uart.port.irq, uart.port.iotype);
1da177e4 2776#endif
5756ee99 2777
2655a2c7 2778 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4
LT		 2779 if (priv->line[i] < 0) {
2780 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2781 break;
2782 }
2783 }
1da177e4 2784 priv->nr = i;
241fc436 2785 return priv;
1da177e4 2786
5756ee99 2787err_deinit:
1da177e4
LT		 2788 if (quirk->exit)
2789 quirk->exit(dev);
5756ee99 2790err_out:
241fc436 2791 return priv;
1da177e4 2792}
241fc436 2793EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 2794
241fc436 2795void pciserial_remove_ports(struct serial_private *priv)
1da177e4 2796{
056a8763
RK		 2797 struct pci_serial_quirk *quirk;
2798 int i;
1da177e4 2799
056a8763
RK		 2800 for (i = 0; i < priv->nr; i++)
2801 serial8250_unregister_port(priv->line[i]);
1da177e4 2802
056a8763
RK		 2803 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2804 if (priv->remapped_bar[i])
2805 iounmap(priv->remapped_bar[i]);
2806 priv->remapped_bar[i] = NULL;
2807 }
1da177e4 2808
056a8763
RK		 2809 /*
2810 * Find the exit quirks.
2811 */
241fc436 2812 quirk = find_quirk(priv->dev);
056a8763 2813 if (quirk->exit)
241fc436
RK		 2814 quirk->exit(priv->dev);
2815
2816 kfree(priv);
2817}
2818EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2819
2820void pciserial_suspend_ports(struct serial_private *priv)
2821{
2822 int i;
2823
2824 for (i = 0; i < priv->nr; i++)
2825 if (priv->line[i] >= 0)
2826 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 2827
2828 /*
2829 * Ensure that every init quirk is properly torn down
2830 */
2831 if (priv->quirk->exit)
2832 priv->quirk->exit(priv->dev);
241fc436
RK		 2833}
2834EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2835
2836void pciserial_resume_ports(struct serial_private *priv)
2837{
2838 int i;
2839
2840 /*
2841 * Ensure that the board is correctly configured.
2842 */
2843 if (priv->quirk->init)
2844 priv->quirk->init(priv->dev);
2845
2846 for (i = 0; i < priv->nr; i++)
2847 if (priv->line[i] >= 0)
2848 serial8250_resume_port(priv->line[i]);
2849}
2850EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2851
2852/*
2853 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2854 * to the arrangement of serial ports on a PCI card.
2855 */
2856static int __devinit
2857pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2858{
5bf8f501 2859 struct pci_serial_quirk *quirk;
241fc436 2860 struct serial_private *priv;
975a1a7d
RK		 2861 const struct pciserial_board *board;
2862 struct pciserial_board tmp;
241fc436
RK		 2863 int rc;
2864
5bf8f501
FB		 2865 quirk = find_quirk(dev);
2866 if (quirk->probe) {
2867 rc = quirk->probe(dev);
2868 if (rc)
2869 return rc;
2870 }
2871
241fc436
RK		 2872 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2873 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2874 ent->driver_data);
2875 return -EINVAL;
2876 }
2877
2878 board = &pci_boards[ent->driver_data];
2879
2880 rc = pci_enable_device(dev);
2807190b 2881 pci_save_state(dev);
241fc436
RK		 2882 if (rc)
2883 return rc;
2884
2885 if (ent->driver_data == pbn_default) {
2886 /*
2887 * Use a copy of the pci_board entry for this;
2888 * avoid changing entries in the table.
2889 */
2890 memcpy(&tmp, board, sizeof(struct pciserial_board));
2891 board = &tmp;
2892
2893 /*
2894 * We matched one of our class entries. Try to
2895 * determine the parameters of this board.
2896 */
975a1a7d 2897 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 2898 if (rc)
2899 goto disable;
2900 } else {
2901 /*
2902 * We matched an explicit entry. If we are able to
2903 * detect this boards settings with our heuristic,
2904 * then we no longer need this entry.
2905 */
2906 memcpy(&tmp, &pci_boards[pbn_default],
2907 sizeof(struct pciserial_board));
2908 rc = serial_pci_guess_board(dev, &tmp);
2909 if (rc == 0 && serial_pci_matches(board, &tmp))
2910 moan_device("Redundant entry in serial pci_table.",
2911 dev);
2912 }
2913
2914 priv = pciserial_init_ports(dev, board);
2915 if (!IS_ERR(priv)) {
2916 pci_set_drvdata(dev, priv);
2917 return 0;
2918 }
2919
2920 rc = PTR_ERR(priv);
1da177e4 2921
241fc436 2922 disable:
056a8763 2923 pci_disable_device(dev);
241fc436
RK		 2924 return rc;
2925}
1da177e4 2926
241fc436
RK		 2927static void __devexit pciserial_remove_one(struct pci_dev *dev)
2928{
2929 struct serial_private *priv = pci_get_drvdata(dev);
2930
2931 pci_set_drvdata(dev, NULL);
2932
2933 pciserial_remove_ports(priv);
2934
2935 pci_disable_device(dev);
1da177e4
LT		 2936}
2937
1d5e7996 2938#ifdef CONFIG_PM
1da177e4
LT		 2939static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2940{
2941 struct serial_private *priv = pci_get_drvdata(dev);
2942
241fc436
RK		 2943 if (priv)
2944 pciserial_suspend_ports(priv);
1da177e4 2945
1da177e4
LT		 2946 pci_save_state(dev);
2947 pci_set_power_state(dev, pci_choose_state(dev, state));
2948 return 0;
2949}
2950
2951static int pciserial_resume_one(struct pci_dev *dev)
2952{
ccb9d59e 2953 int err;
1da177e4
LT		 2954 struct serial_private *priv = pci_get_drvdata(dev);
2955
2956 pci_set_power_state(dev, PCI_D0);
2957 pci_restore_state(dev);
2958
2959 if (priv) {
1da177e4
LT		 2960 /*
2961 * The device may have been disabled. Re-enable it.
2962 */
ccb9d59e 2963 err = pci_enable_device(dev);
40836c48 2964 /* FIXME: We cannot simply error out here */
ccb9d59e 2965 if (err)
40836c48 2966 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 2967 pciserial_resume_ports(priv);
1da177e4
LT		 2968 }
2969 return 0;
2970}
1d5e7996 2971#endif
1da177e4
LT		 2972
2973static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 2974 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2975 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2976 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2977 pbn_b2_8_921600 },
1da177e4
LT		 2978 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2979 PCI_SUBVENDOR_ID_CONNECT_TECH,
2980 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2981 pbn_b1_8_1382400 },
2982 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2983 PCI_SUBVENDOR_ID_CONNECT_TECH,
2984 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2985 pbn_b1_4_1382400 },
2986 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2987 PCI_SUBVENDOR_ID_CONNECT_TECH,
2988 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2989 pbn_b1_2_1382400 },
2990 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2991 PCI_SUBVENDOR_ID_CONNECT_TECH,
2992 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2993 pbn_b1_8_1382400 },
2994 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2995 PCI_SUBVENDOR_ID_CONNECT_TECH,
2996 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2997 pbn_b1_4_1382400 },
2998 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2999 PCI_SUBVENDOR_ID_CONNECT_TECH,
3000 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3001 pbn_b1_2_1382400 },
3002 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3003 PCI_SUBVENDOR_ID_CONNECT_TECH,
3004 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3005 pbn_b1_8_921600 },
3006 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3007 PCI_SUBVENDOR_ID_CONNECT_TECH,
3008 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3009 pbn_b1_8_921600 },
3010 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3011 PCI_SUBVENDOR_ID_CONNECT_TECH,
3012 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3013 pbn_b1_4_921600 },
3014 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3015 PCI_SUBVENDOR_ID_CONNECT_TECH,
3016 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3017 pbn_b1_4_921600 },
3018 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3019 PCI_SUBVENDOR_ID_CONNECT_TECH,
3020 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3021 pbn_b1_2_921600 },
3022 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3023 PCI_SUBVENDOR_ID_CONNECT_TECH,
3024 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3025 pbn_b1_8_921600 },
3026 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3027 PCI_SUBVENDOR_ID_CONNECT_TECH,
3028 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3029 pbn_b1_8_921600 },
3030 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3031 PCI_SUBVENDOR_ID_CONNECT_TECH,
3032 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3033 pbn_b1_4_921600 },
26e92861
GH		 3034 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3035 PCI_SUBVENDOR_ID_CONNECT_TECH,
3036 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3037 pbn_b1_2_1250000 },
3038 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3039 PCI_SUBVENDOR_ID_CONNECT_TECH,
3040 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3041 pbn_b0_2_1843200 },
3042 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3043 PCI_SUBVENDOR_ID_CONNECT_TECH,
3044 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3045 pbn_b0_4_1843200 },
85d1494e
YY		 3046 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3047 PCI_VENDOR_ID_AFAVLAB,
3048 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3049 pbn_b0_4_1152000 },
26e92861
GH		 3050 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3051 PCI_SUBVENDOR_ID_CONNECT_TECH,
3052 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3053 pbn_b0_2_1843200_200 },
3054 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3055 PCI_SUBVENDOR_ID_CONNECT_TECH,
3056 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3057 pbn_b0_4_1843200_200 },
3058 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3059 PCI_SUBVENDOR_ID_CONNECT_TECH,
3060 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3061 pbn_b0_8_1843200_200 },
3062 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3063 PCI_SUBVENDOR_ID_CONNECT_TECH,
3064 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3065 pbn_b0_2_1843200_200 },
3066 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3067 PCI_SUBVENDOR_ID_CONNECT_TECH,
3068 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3069 pbn_b0_4_1843200_200 },
3070 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3071 PCI_SUBVENDOR_ID_CONNECT_TECH,
3072 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3073 pbn_b0_8_1843200_200 },
3074 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3075 PCI_SUBVENDOR_ID_CONNECT_TECH,
3076 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3077 pbn_b0_2_1843200_200 },
3078 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3079 PCI_SUBVENDOR_ID_CONNECT_TECH,
3080 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3081 pbn_b0_4_1843200_200 },
3082 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3083 PCI_SUBVENDOR_ID_CONNECT_TECH,
3084 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3085 pbn_b0_8_1843200_200 },
3086 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3087 PCI_SUBVENDOR_ID_CONNECT_TECH,
3088 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3089 pbn_b0_2_1843200_200 },
3090 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3091 PCI_SUBVENDOR_ID_CONNECT_TECH,
3092 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3093 pbn_b0_4_1843200_200 },
3094 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3095 PCI_SUBVENDOR_ID_CONNECT_TECH,
3096 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3097 pbn_b0_8_1843200_200 },
c68d2b15
BH		 3098 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3099 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3100 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 3101
3102 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 3103 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3104 pbn_b2_bt_1_115200 },
3105 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 3106 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3107 pbn_b2_bt_2_115200 },
3108 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 3109 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3110 pbn_b2_bt_4_115200 },
3111 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 3112 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3113 pbn_b2_bt_2_115200 },
3114 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 3115 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3116 pbn_b2_bt_4_115200 },
3117 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 3118 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3119 pbn_b2_8_115200 },
e65f0f82
FL		 3120 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3122 pbn_b2_8_460800 },
1da177e4
LT		 3123 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3125 pbn_b2_8_115200 },
3126
3127 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3129 pbn_b2_bt_2_115200 },
3130 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3132 pbn_b2_bt_2_921600 },
3133 /*
3134 * VScom SPCOM800, from sl@s.pl
3135 */
5756ee99
AC		 3136 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3138 pbn_b2_8_921600 },
3139 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 3140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3141 pbn_b2_4_921600 },
b76c5a07
CB		 3142 /* Unknown card - subdevice 0x1584 */
3143 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3144 PCI_VENDOR_ID_PLX,
3145 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3146 pbn_b0_4_115200 },
1da177e4
LT		 3147 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3148 PCI_SUBVENDOR_ID_KEYSPAN,
3149 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3150 pbn_panacom },
3151 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3153 pbn_panacom4 },
3154 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3156 pbn_panacom2 },
a9cccd34
MF		 3157 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3158 PCI_VENDOR_ID_ESDGMBH,
3159 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3160 pbn_b2_4_115200 },
1da177e4
LT		 3161 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3162 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3163 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 3164 pbn_b2_4_460800 },
3165 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3166 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3167 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 3168 pbn_b2_8_460800 },
3169 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3170 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3171 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 3172 pbn_b2_16_460800 },
3173 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3174 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3175 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 3176 pbn_b2_16_460800 },
3177 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3178 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3179 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 3180 pbn_b2_4_460800 },
3181 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3182 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3183 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 3184 pbn_b2_8_460800 },
add7b58e
BH		 3185 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3186 PCI_SUBVENDOR_ID_EXSYS,
3187 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 3188 pbn_b2_4_115200 },
1da177e4
LT		 3189 /*
3190 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3191 * (Exoray@isys.ca)
3192 */
3193 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3194 0x10b5, 0x106a, 0, 0,
3195 pbn_plx_romulus },
3196 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3198 pbn_b1_4_115200 },
3199 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3201 pbn_b1_2_115200 },
3202 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3204 pbn_b1_8_115200 },
3205 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3207 pbn_b1_8_115200 },
3208 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3209 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3210 0, 0,
1da177e4 3211 pbn_b0_4_921600 },
fbc0dc0d 3212 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3213 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3214 0, 0,
fbc0dc0d 3215 pbn_b0_4_1152000 },
c9bd9d01
MP		 3216 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218 pbn_b0_bt_2_921600 },
db1de159
DR		 3219
3220 /*
3221 * The below card is a little controversial since it is the
3222 * subject of a PCI vendor/device ID clash. (See
3223 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3224 * For now just used the hex ID 0x950a.
3225 */
39aced68
NV		 3226 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3227 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3228 pbn_b0_2_115200 },
db1de159
DR		 3229 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3231 pbn_b0_2_1130000 },
70fd8fde
AP		 3232 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3233 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3234 pbn_b0_1_921600 },
1da177e4
LT		 3235 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3237 pbn_b0_4_115200 },
3238 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3240 pbn_b0_bt_2_921600 },
e847003f
LB		 3241 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3242 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3243 pbn_b2_8_1152000 },
1da177e4 3244
7106b4e3
LH		 3245 /*
3246 * Oxford Semiconductor Inc. Tornado PCI express device range.
3247 */
3248 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3250 pbn_b0_1_4000000 },
3251 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3253 pbn_b0_1_4000000 },
3254 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3256 pbn_oxsemi_1_4000000 },
3257 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3259 pbn_oxsemi_1_4000000 },
3260 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3262 pbn_b0_1_4000000 },
3263 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3265 pbn_b0_1_4000000 },
3266 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3268 pbn_oxsemi_1_4000000 },
3269 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271 pbn_oxsemi_1_4000000 },
3272 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3274 pbn_b0_1_4000000 },
3275 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3277 pbn_b0_1_4000000 },
3278 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3280 pbn_b0_1_4000000 },
3281 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3283 pbn_b0_1_4000000 },
3284 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3286 pbn_oxsemi_2_4000000 },
3287 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3289 pbn_oxsemi_2_4000000 },
3290 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3292 pbn_oxsemi_4_4000000 },
3293 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3295 pbn_oxsemi_4_4000000 },
3296 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3298 pbn_oxsemi_8_4000000 },
3299 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3301 pbn_oxsemi_8_4000000 },
3302 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3304 pbn_oxsemi_1_4000000 },
3305 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3307 pbn_oxsemi_1_4000000 },
3308 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3310 pbn_oxsemi_1_4000000 },
3311 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3313 pbn_oxsemi_1_4000000 },
3314 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3316 pbn_oxsemi_1_4000000 },
3317 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3319 pbn_oxsemi_1_4000000 },
3320 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3322 pbn_oxsemi_1_4000000 },
3323 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3325 pbn_oxsemi_1_4000000 },
3326 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3328 pbn_oxsemi_1_4000000 },
3329 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3331 pbn_oxsemi_1_4000000 },
3332 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3334 pbn_oxsemi_1_4000000 },
3335 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3336 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3337 pbn_oxsemi_1_4000000 },
3338 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3339 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3340 pbn_oxsemi_1_4000000 },
3341 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3342 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3343 pbn_oxsemi_1_4000000 },
3344 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3346 pbn_oxsemi_1_4000000 },
3347 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3348 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3349 pbn_oxsemi_1_4000000 },
3350 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3351 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3352 pbn_oxsemi_1_4000000 },
3353 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3355 pbn_oxsemi_1_4000000 },
3356 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3358 pbn_oxsemi_1_4000000 },
3359 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3361 pbn_oxsemi_1_4000000 },
3362 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3364 pbn_oxsemi_1_4000000 },
3365 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3367 pbn_oxsemi_1_4000000 },
3368 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3370 pbn_oxsemi_1_4000000 },
3371 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3373 pbn_oxsemi_1_4000000 },
3374 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3376 pbn_oxsemi_1_4000000 },
3377 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3378 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3379 pbn_oxsemi_1_4000000 },
b80de369
LH		 3380 /*
3381 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3382 */
3383 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3384 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3385 pbn_oxsemi_1_4000000 },
3386 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3387 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3388 pbn_oxsemi_2_4000000 },
3389 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3390 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3391 pbn_oxsemi_4_4000000 },
3392 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3393 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3394 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 3395
3396 /*
3397 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3398 */
3399 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3400 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3401 pbn_oxsemi_2_4000000 },
3402
1da177e4
LT		 3403 /*
3404 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3405 * from skokodyn@yahoo.com
3406 */
3407 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3408 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3409 pbn_sbsxrsio },
3410 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3411 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3412 pbn_sbsxrsio },
3413 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3414 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3415 pbn_sbsxrsio },
3416 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3417 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3418 pbn_sbsxrsio },
3419
3420 /*
3421 * Digitan DS560-558, from jimd@esoft.com
3422 */
3423 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 3424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3425 pbn_b1_1_115200 },
3426
3427 /*
3428 * Titan Electronic cards
3429 * The 400L and 800L have a custom setup quirk.
3430 */
3431 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 3432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3433 pbn_b0_1_921600 },
3434 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 3435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3436 pbn_b0_2_921600 },
3437 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 3438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3439 pbn_b0_4_921600 },
3440 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 3441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3442 pbn_b0_4_921600 },
3443 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3445 pbn_b1_1_921600 },
3446 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3448 pbn_b1_bt_2_921600 },
3449 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3451 pbn_b0_bt_4_921600 },
3452 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3454 pbn_b0_bt_8_921600 },
66169ad1
YY		 3455 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3457 pbn_b4_bt_2_921600 },
3458 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3460 pbn_b4_bt_4_921600 },
3461 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3463 pbn_b4_bt_8_921600 },
3464 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3466 pbn_b0_4_921600 },
3467 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3469 pbn_b0_4_921600 },
3470 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3472 pbn_b0_4_921600 },
3473 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3475 pbn_oxsemi_1_4000000 },
3476 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3478 pbn_oxsemi_2_4000000 },
3479 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3481 pbn_oxsemi_4_4000000 },
3482 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3484 pbn_oxsemi_8_4000000 },
3485 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3487 pbn_oxsemi_2_4000000 },
3488 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3490 pbn_oxsemi_2_4000000 },
1e9deb11
YY		 3491 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3493 pbn_b0_4_921600 },
3494 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3496 pbn_b0_4_921600 },
3497 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3499 pbn_b0_4_921600 },
3500 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3502 pbn_b0_4_921600 },
1da177e4
LT		 3503
3504 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3506 pbn_b2_1_460800 },
3507 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3509 pbn_b2_1_460800 },
3510 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3512 pbn_b2_1_460800 },
3513 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3515 pbn_b2_bt_2_921600 },
3516 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3518 pbn_b2_bt_2_921600 },
3519 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3521 pbn_b2_bt_2_921600 },
3522 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3524 pbn_b2_bt_4_921600 },
3525 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3527 pbn_b2_bt_4_921600 },
3528 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3530 pbn_b2_bt_4_921600 },
3531 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3533 pbn_b0_1_921600 },
3534 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3536 pbn_b0_1_921600 },
3537 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3539 pbn_b0_1_921600 },
3540 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3542 pbn_b0_bt_2_921600 },
3543 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3545 pbn_b0_bt_2_921600 },
3546 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3548 pbn_b0_bt_2_921600 },
3549 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3551 pbn_b0_bt_4_921600 },
3552 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3554 pbn_b0_bt_4_921600 },
3555 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3557 pbn_b0_bt_4_921600 },
3ec9c594
AP		 3558 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3560 pbn_b0_bt_8_921600 },
3561 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3563 pbn_b0_bt_8_921600 },
3564 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3566 pbn_b0_bt_8_921600 },
1da177e4
LT		 3567
3568 /*
3569 * Computone devices submitted by Doug McNash dmcnash@computone.com
3570 */
3571 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3572 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3573 0, 0, pbn_computone_4 },
3574 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3575 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3576 0, 0, pbn_computone_8 },
3577 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3578 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3579 0, 0, pbn_computone_6 },
3580
3581 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583 pbn_oxsemi },
3584 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3585 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3586 pbn_b0_bt_1_921600 },
3587
3588 /*
3589 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3590 */
3591 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3593 pbn_b0_bt_8_115200 },
3594 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3596 pbn_b0_bt_8_115200 },
3597
3598 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3600 pbn_b0_bt_2_115200 },
3601 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3603 pbn_b0_bt_2_115200 },
3604 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3606 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 3607 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3609 pbn_b0_bt_2_115200 },
3610 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3612 pbn_b0_bt_2_115200 },
1da177e4
LT		 3613 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3615 pbn_b0_bt_4_460800 },
3616 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3618 pbn_b0_bt_4_460800 },
3619 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3621 pbn_b0_bt_2_460800 },
3622 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3624 pbn_b0_bt_2_460800 },
3625 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3627 pbn_b0_bt_2_460800 },
3628 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3630 pbn_b0_bt_1_115200 },
3631 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3633 pbn_b0_bt_1_460800 },
3634
1fb8cacc
RK		 3635 /*
3636 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3637 * Cards are identified by their subsystem vendor IDs, which
3638 * (in hex) match the model number.
3639 *
3640 * Note that JC140x are RS422/485 cards which require ox950
3641 * ACR = 0x10, and as such are not currently fully supported.
3642 */
3643 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3644 0x1204, 0x0004, 0, 0,
3645 pbn_b0_4_921600 },
3646 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3647 0x1208, 0x0004, 0, 0,
3648 pbn_b0_4_921600 },
3649/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3650 0x1402, 0x0002, 0, 0,
3651 pbn_b0_2_921600 }, */
3652/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3653 0x1404, 0x0004, 0, 0,
3654 pbn_b0_4_921600 }, */
3655 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3656 0x1208, 0x0004, 0, 0,
3657 pbn_b0_4_921600 },
3658
2a52fcb5
KY		 3659 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3660 0x1204, 0x0004, 0, 0,
3661 pbn_b0_4_921600 },
3662 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3663 0x1208, 0x0004, 0, 0,
3664 pbn_b0_4_921600 },
3665 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3666 0x1208, 0x0004, 0, 0,
3667 pbn_b0_4_921600 },
1da177e4
LT		 3668 /*
3669 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3670 */
3671 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3673 pbn_b1_1_1382400 },
3674
3675 /*
3676 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3677 */
3678 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3680 pbn_b1_1_1382400 },
3681
3682 /*
3683 * RAStel 2 port modem, gerg@moreton.com.au
3684 */
3685 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3687 pbn_b2_bt_2_115200 },
3688
3689 /*
3690 * EKF addition for i960 Boards form EKF with serial port
3691 */
3692 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3693 0xE4BF, PCI_ANY_ID, 0, 0,
3694 pbn_intel_i960 },
3695
3696 /*
3697 * Xircom Cardbus/Ethernet combos
3698 */
3699 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3701 pbn_b0_1_115200 },
3702 /*
3703 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3704 */
3705 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3707 pbn_b0_1_115200 },
3708
3709 /*
3710 * Untested PCI modems, sent in from various folks...
3711 */
3712
3713 /*
3714 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3715 */
3716 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3717 0x1048, 0x1500, 0, 0,
3718 pbn_b1_1_115200 },
3719
3720 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3721 0xFF00, 0, 0, 0,
3722 pbn_sgi_ioc3 },
3723
3724 /*
3725 * HP Diva card
3726 */
3727 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3728 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3729 pbn_b1_1_115200 },
3730 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3732 pbn_b0_5_115200 },
3733 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3735 pbn_b2_1_115200 },
3736
d9004eb4
ABL		 3737 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3738 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3739 pbn_b3_2_115200 },
1da177e4
LT		 3740 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3741 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3742 pbn_b3_4_115200 },
3743 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3745 pbn_b3_8_115200 },
3746
3747 /*
3748 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3749 */
3750 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3751 PCI_ANY_ID, PCI_ANY_ID,
3752 0,
3753 0, pbn_exar_XR17C152 },
3754 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3755 PCI_ANY_ID, PCI_ANY_ID,
3756 0,
3757 0, pbn_exar_XR17C154 },
3758 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3759 PCI_ANY_ID, PCI_ANY_ID,
3760 0,
3761 0, pbn_exar_XR17C158 },
3762
3763 /*
3764 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3765 */
3766 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3768 pbn_b0_1_115200 },
84f8c6fc
NV		 3769 /*
3770 * ITE
3771 */
3772 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3773 PCI_ANY_ID, PCI_ANY_ID,
3774 0, 0,
3775 pbn_b1_bt_1_115200 },
1da177e4 3776
737c1756
PH		 3777 /*
3778 * IntaShield IS-200
3779 */
3780 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3781 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3782 pbn_b2_2_115200 },
4b6f6ce9
IGP		 3783 /*
3784 * IntaShield IS-400
3785 */
3786 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3787 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3788 pbn_b2_4_115200 },
48212008
TH		 3789 /*
3790 * Perle PCI-RAS cards
3791 */
3792 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3793 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3794 0, 0, pbn_b2_4_921600 },
3795 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3796 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3797 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 3798
3799 /*
3800 * Mainpine series cards: Fairly standard layout but fools
3801 * parts of the autodetect in some cases and uses otherwise
3802 * unmatched communications subclasses in the PCI Express case
3803 */
3804
3805 { /* RockForceDUO */
3806 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3807 PCI_VENDOR_ID_MAINPINE, 0x0200,
3808 0, 0, pbn_b0_2_115200 },
3809 { /* RockForceQUATRO */
3810 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3811 PCI_VENDOR_ID_MAINPINE, 0x0300,
3812 0, 0, pbn_b0_4_115200 },
3813 { /* RockForceDUO+ */
3814 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3815 PCI_VENDOR_ID_MAINPINE, 0x0400,
3816 0, 0, pbn_b0_2_115200 },
3817 { /* RockForceQUATRO+ */
3818 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3819 PCI_VENDOR_ID_MAINPINE, 0x0500,
3820 0, 0, pbn_b0_4_115200 },
3821 { /* RockForce+ */
3822 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3823 PCI_VENDOR_ID_MAINPINE, 0x0600,
3824 0, 0, pbn_b0_2_115200 },
3825 { /* RockForce+ */
3826 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3827 PCI_VENDOR_ID_MAINPINE, 0x0700,
3828 0, 0, pbn_b0_4_115200 },
3829 { /* RockForceOCTO+ */
3830 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3831 PCI_VENDOR_ID_MAINPINE, 0x0800,
3832 0, 0, pbn_b0_8_115200 },
3833 { /* RockForceDUO+ */
3834 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3835 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3836 0, 0, pbn_b0_2_115200 },
3837 { /* RockForceQUARTRO+ */
3838 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3839 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3840 0, 0, pbn_b0_4_115200 },
3841 { /* RockForceOCTO+ */
3842 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3843 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3844 0, 0, pbn_b0_8_115200 },
3845 { /* RockForceD1 */
3846 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3847 PCI_VENDOR_ID_MAINPINE, 0x2000,
3848 0, 0, pbn_b0_1_115200 },
3849 { /* RockForceF1 */
3850 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3851 PCI_VENDOR_ID_MAINPINE, 0x2100,
3852 0, 0, pbn_b0_1_115200 },
3853 { /* RockForceD2 */
3854 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3855 PCI_VENDOR_ID_MAINPINE, 0x2200,
3856 0, 0, pbn_b0_2_115200 },
3857 { /* RockForceF2 */
3858 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3859 PCI_VENDOR_ID_MAINPINE, 0x2300,
3860 0, 0, pbn_b0_2_115200 },
3861 { /* RockForceD4 */
3862 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3863 PCI_VENDOR_ID_MAINPINE, 0x2400,
3864 0, 0, pbn_b0_4_115200 },
3865 { /* RockForceF4 */
3866 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3867 PCI_VENDOR_ID_MAINPINE, 0x2500,
3868 0, 0, pbn_b0_4_115200 },
3869 { /* RockForceD8 */
3870 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3871 PCI_VENDOR_ID_MAINPINE, 0x2600,
3872 0, 0, pbn_b0_8_115200 },
3873 { /* RockForceF8 */
3874 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3875 PCI_VENDOR_ID_MAINPINE, 0x2700,
3876 0, 0, pbn_b0_8_115200 },
3877 { /* IQ Express D1 */
3878 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3879 PCI_VENDOR_ID_MAINPINE, 0x3000,
3880 0, 0, pbn_b0_1_115200 },
3881 { /* IQ Express F1 */
3882 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3883 PCI_VENDOR_ID_MAINPINE, 0x3100,
3884 0, 0, pbn_b0_1_115200 },
3885 { /* IQ Express D2 */
3886 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3887 PCI_VENDOR_ID_MAINPINE, 0x3200,
3888 0, 0, pbn_b0_2_115200 },
3889 { /* IQ Express F2 */
3890 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3891 PCI_VENDOR_ID_MAINPINE, 0x3300,
3892 0, 0, pbn_b0_2_115200 },
3893 { /* IQ Express D4 */
3894 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3895 PCI_VENDOR_ID_MAINPINE, 0x3400,
3896 0, 0, pbn_b0_4_115200 },
3897 { /* IQ Express F4 */
3898 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3899 PCI_VENDOR_ID_MAINPINE, 0x3500,
3900 0, 0, pbn_b0_4_115200 },
3901 { /* IQ Express D8 */
3902 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3903 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3904 0, 0, pbn_b0_8_115200 },
3905 { /* IQ Express F8 */
3906 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3907 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3908 0, 0, pbn_b0_8_115200 },
3909
3910
aa798505
OJ		 3911 /*
3912 * PA Semi PA6T-1682M on-chip UART
3913 */
3914 { PCI_VENDOR_ID_PASEMI, 0xa004,
3915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3916 pbn_pasemi_1682M },
3917
46a0fac9
SB		 3918 /*
3919 * National Instruments
3920 */
04bf7e74
WP		 3921 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3923 pbn_b1_16_115200 },
3924 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3926 pbn_b1_8_115200 },
3927 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3929 pbn_b1_bt_4_115200 },
3930 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3932 pbn_b1_bt_2_115200 },
3933 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3935 pbn_b1_bt_4_115200 },
3936 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3938 pbn_b1_bt_2_115200 },
3939 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3941 pbn_b1_16_115200 },
3942 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3944 pbn_b1_8_115200 },
3945 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3947 pbn_b1_bt_4_115200 },
3948 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3950 pbn_b1_bt_2_115200 },
3951 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3953 pbn_b1_bt_4_115200 },
3954 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3956 pbn_b1_bt_2_115200 },
46a0fac9
SB		 3957 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3959 pbn_ni8430_2 },
3960 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3962 pbn_ni8430_2 },
3963 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965 pbn_ni8430_4 },
3966 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3968 pbn_ni8430_4 },
3969 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3971 pbn_ni8430_8 },
3972 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3974 pbn_ni8430_8 },
3975 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3977 pbn_ni8430_16 },
3978 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3980 pbn_ni8430_16 },
3981 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983 pbn_ni8430_2 },
3984 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986 pbn_ni8430_2 },
3987 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3989 pbn_ni8430_4 },
3990 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992 pbn_ni8430_4 },
3993
02c9b5cf
KJ		 3994 /*
3995 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3996 */
3997 { PCI_VENDOR_ID_ADDIDATA,
3998 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3999 PCI_ANY_ID,
4000 PCI_ANY_ID,
4001 0,
4002 0,
4003 pbn_b0_4_115200 },
4004
4005 { PCI_VENDOR_ID_ADDIDATA,
4006 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4007 PCI_ANY_ID,
4008 PCI_ANY_ID,
4009 0,
4010 0,
4011 pbn_b0_2_115200 },
4012
4013 { PCI_VENDOR_ID_ADDIDATA,
4014 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4015 PCI_ANY_ID,
4016 PCI_ANY_ID,
4017 0,
4018 0,
4019 pbn_b0_1_115200 },
4020
4021 { PCI_VENDOR_ID_ADDIDATA_OLD,
4022 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4023 PCI_ANY_ID,
4024 PCI_ANY_ID,
4025 0,
4026 0,
4027 pbn_b1_8_115200 },
4028
4029 { PCI_VENDOR_ID_ADDIDATA,
4030 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4031 PCI_ANY_ID,
4032 PCI_ANY_ID,
4033 0,
4034 0,
4035 pbn_b0_4_115200 },
4036
4037 { PCI_VENDOR_ID_ADDIDATA,
4038 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4039 PCI_ANY_ID,
4040 PCI_ANY_ID,
4041 0,
4042 0,
4043 pbn_b0_2_115200 },
4044
4045 { PCI_VENDOR_ID_ADDIDATA,
4046 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4047 PCI_ANY_ID,
4048 PCI_ANY_ID,
4049 0,
4050 0,
4051 pbn_b0_1_115200 },
4052
4053 { PCI_VENDOR_ID_ADDIDATA,
4054 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4055 PCI_ANY_ID,
4056 PCI_ANY_ID,
4057 0,
4058 0,
4059 pbn_b0_4_115200 },
4060
4061 { PCI_VENDOR_ID_ADDIDATA,
4062 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4063 PCI_ANY_ID,
4064 PCI_ANY_ID,
4065 0,
4066 0,
4067 pbn_b0_2_115200 },
4068
4069 { PCI_VENDOR_ID_ADDIDATA,
4070 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4071 PCI_ANY_ID,
4072 PCI_ANY_ID,
4073 0,
4074 0,
4075 pbn_b0_1_115200 },
4076
4077 { PCI_VENDOR_ID_ADDIDATA,
4078 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4079 PCI_ANY_ID,
4080 PCI_ANY_ID,
4081 0,
4082 0,
4083 pbn_b0_8_115200 },
4084
1b62cbf2
KJ		 4085 { PCI_VENDOR_ID_ADDIDATA,
4086 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4087 PCI_ANY_ID,
4088 PCI_ANY_ID,
4089 0,
4090 0,
4091 pbn_ADDIDATA_PCIe_4_3906250 },
4092
4093 { PCI_VENDOR_ID_ADDIDATA,
4094 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4095 PCI_ANY_ID,
4096 PCI_ANY_ID,
4097 0,
4098 0,
4099 pbn_ADDIDATA_PCIe_2_3906250 },
4100
4101 { PCI_VENDOR_ID_ADDIDATA,
4102 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4103 PCI_ANY_ID,
4104 PCI_ANY_ID,
4105 0,
4106 0,
4107 pbn_ADDIDATA_PCIe_1_3906250 },
4108
4109 { PCI_VENDOR_ID_ADDIDATA,
4110 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4111 PCI_ANY_ID,
4112 PCI_ANY_ID,
4113 0,
4114 0,
4115 pbn_ADDIDATA_PCIe_8_3906250 },
4116
25cf9bc1
JS		 4117 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4118 PCI_VENDOR_ID_IBM, 0x0299,
4119 0, 0, pbn_b0_bt_2_115200 },
4120
c4285b47
MB		 4121 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4122 0xA000, 0x1000,
4123 0, 0, pbn_b0_1_115200 },
4124
7808edcd
NG		 4125 /* the 9901 is a rebranded 9912 */
4126 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4127 0xA000, 0x1000,
4128 0, 0, pbn_b0_1_115200 },
4129
4130 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4131 0xA000, 0x1000,
4132 0, 0, pbn_b0_1_115200 },
4133
4134 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4135 0xA000, 0x1000,
4136 0, 0, pbn_b0_1_115200 },
4137
4138 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4139 0xA000, 0x1000,
4140 0, 0, pbn_b0_1_115200 },
4141
4142 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4143 0xA000, 0x3002,
4144 0, 0, pbn_NETMOS9900_2s_115200 },
4145
ac6ec5b1 4146 /*
44178176 4147 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 4148 */
4149
4150 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4151 0xA000, 0x1000,
4152 0, 0, pbn_b0_1_115200 },
4153
44178176
ES		 4154 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4155 0xA000, 0x3002,
4156 0, 0, pbn_b0_bt_2_115200 },
4157
ac6ec5b1
IS		 4158 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4159 0xA000, 0x3004,
4160 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 4161 /* Intel CE4100 */
4162 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4164 pbn_ce4100_1_115200 },
4165
d9a0fbfd
AP		 4166 /*
4167 * Cronyx Omega PCI
4168 */
4169 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4171 pbn_omegapci },
ac6ec5b1 4172
1da177e4
LT		 4173 /*
4174 * These entries match devices with class COMMUNICATION_SERIAL,
4175 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4176 */
4177 { PCI_ANY_ID, PCI_ANY_ID,
4178 PCI_ANY_ID, PCI_ANY_ID,
4179 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4180 0xffff00, pbn_default },
4181 { PCI_ANY_ID, PCI_ANY_ID,
4182 PCI_ANY_ID, PCI_ANY_ID,
4183 PCI_CLASS_COMMUNICATION_MODEM << 8,
4184 0xffff00, pbn_default },
4185 { PCI_ANY_ID, PCI_ANY_ID,
4186 PCI_ANY_ID, PCI_ANY_ID,
4187 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4188 0xffff00, pbn_default },
4189 { 0, }
4190};
4191
2807190b
MR		 4192static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4193 pci_channel_state_t state)
4194{
4195 struct serial_private *priv = pci_get_drvdata(dev);
4196
4197 if (state == pci_channel_io_perm_failure)
4198 return PCI_ERS_RESULT_DISCONNECT;
4199
4200 if (priv)
4201 pciserial_suspend_ports(priv);
4202
4203 pci_disable_device(dev);
4204
4205 return PCI_ERS_RESULT_NEED_RESET;
4206}
4207
4208static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4209{
4210 int rc;
4211
4212 rc = pci_enable_device(dev);
4213
4214 if (rc)
4215 return PCI_ERS_RESULT_DISCONNECT;
4216
4217 pci_restore_state(dev);
4218 pci_save_state(dev);
4219
4220 return PCI_ERS_RESULT_RECOVERED;
4221}
4222
4223static void serial8250_io_resume(struct pci_dev *dev)
4224{
4225 struct serial_private *priv = pci_get_drvdata(dev);
4226
4227 if (priv)
4228 pciserial_resume_ports(priv);
4229}
4230
4231static struct pci_error_handlers serial8250_err_handler = {
4232 .error_detected = serial8250_io_error_detected,
4233 .slot_reset = serial8250_io_slot_reset,
4234 .resume = serial8250_io_resume,
4235};
4236
1da177e4
LT		 4237static struct pci_driver serial_pci_driver = {
4238 .name = "serial",
4239 .probe = pciserial_init_one,
4240 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 4241#ifdef CONFIG_PM
1da177e4
LT		 4242 .suspend = pciserial_suspend_one,
4243 .resume = pciserial_resume_one,
1d5e7996 4244#endif
1da177e4 4245 .id_table = serial_pci_tbl,
2807190b 4246 .err_handler = &serial8250_err_handler,
1da177e4
LT		 4247};
4248
4249static int __init serial8250_pci_init(void)
4250{
4251 return pci_register_driver(&serial_pci_driver);
4252}
4253
4254static void __exit serial8250_pci_exit(void)
4255{
4256 pci_unregister_driver(&serial_pci_driver);
4257}
4258
4259module_init(serial8250_pci_init);
4260module_exit(serial8250_pci_exit);
4261
4262MODULE_LICENSE("GPL");
4263MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4264MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
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