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[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / 8250 / 8250_port.c
CommitLineData
b6830f6d
PH		 1/*
2 * Base port operations for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * A note about mapbase / membase
13 *
14 * mapbase is the physical address of the IO port.
15 * membase is an 'ioremapped' cookie.
16 */
17
18#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
21
22#include <linux/module.h>
23#include <linux/moduleparam.h>
24#include <linux/ioport.h>
25#include <linux/init.h>
26#include <linux/console.h>
27#include <linux/sysrq.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/tty.h>
31#include <linux/ratelimit.h>
32#include <linux/tty_flip.h>
33#include <linux/serial.h>
34#include <linux/serial_8250.h>
35#include <linux/nmi.h>
36#include <linux/mutex.h>
37#include <linux/slab.h>
38#include <linux/uaccess.h>
39#include <linux/pm_runtime.h>
e490c914 40#include <linux/timer.h>
b6830f6d
PH		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
47/*
48 * Debugging.
49 */
50#if 0
51#define DEBUG_AUTOCONF(fmt...) printk(fmt)
52#else
53#define DEBUG_AUTOCONF(fmt...) do { } while (0)
54#endif
55
6d7c157f 56#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
b6830f6d
PH		 57
58/*
59 * Here we define the default xmit fifo size used for each type of UART.
60 */
61static const struct serial8250_config uart_config[] = {
62 [PORT_UNKNOWN] = {
63 .name = "unknown",
64 .fifo_size = 1,
65 .tx_loadsz = 1,
66 },
67 [PORT_8250] = {
68 .name = "8250",
69 .fifo_size = 1,
70 .tx_loadsz = 1,
71 },
72 [PORT_16450] = {
73 .name = "16450",
74 .fifo_size = 1,
75 .tx_loadsz = 1,
76 },
77 [PORT_16550] = {
78 .name = "16550",
79 .fifo_size = 1,
80 .tx_loadsz = 1,
81 },
82 [PORT_16550A] = {
83 .name = "16550A",
84 .fifo_size = 16,
85 .tx_loadsz = 16,
86 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
87 .rxtrig_bytes = {1, 4, 8, 14},
88 .flags = UART_CAP_FIFO,
89 },
90 [PORT_CIRRUS] = {
91 .name = "Cirrus",
92 .fifo_size = 1,
93 .tx_loadsz = 1,
94 },
95 [PORT_16650] = {
96 .name = "ST16650",
97 .fifo_size = 1,
98 .tx_loadsz = 1,
99 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
100 },
101 [PORT_16650V2] = {
102 .name = "ST16650V2",
103 .fifo_size = 32,
104 .tx_loadsz = 16,
105 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
106 UART_FCR_T_TRIG_00,
107 .rxtrig_bytes = {8, 16, 24, 28},
108 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
109 },
110 [PORT_16750] = {
111 .name = "TI16750",
112 .fifo_size = 64,
113 .tx_loadsz = 64,
114 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
115 UART_FCR7_64BYTE,
116 .rxtrig_bytes = {1, 16, 32, 56},
117 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
118 },
119 [PORT_STARTECH] = {
120 .name = "Startech",
121 .fifo_size = 1,
122 .tx_loadsz = 1,
123 },
124 [PORT_16C950] = {
125 .name = "16C950/954",
126 .fifo_size = 128,
127 .tx_loadsz = 128,
128 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
129 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
130 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
131 },
132 [PORT_16654] = {
133 .name = "ST16654",
134 .fifo_size = 64,
135 .tx_loadsz = 32,
136 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
137 UART_FCR_T_TRIG_10,
138 .rxtrig_bytes = {8, 16, 56, 60},
139 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
140 },
141 [PORT_16850] = {
142 .name = "XR16850",
143 .fifo_size = 128,
144 .tx_loadsz = 128,
145 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
146 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
147 },
148 [PORT_RSA] = {
149 .name = "RSA",
150 .fifo_size = 2048,
151 .tx_loadsz = 2048,
152 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
153 .flags = UART_CAP_FIFO,
154 },
155 [PORT_NS16550A] = {
156 .name = "NS16550A",
157 .fifo_size = 16,
158 .tx_loadsz = 16,
159 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
160 .flags = UART_CAP_FIFO | UART_NATSEMI,
161 },
162 [PORT_XSCALE] = {
163 .name = "XScale",
164 .fifo_size = 32,
165 .tx_loadsz = 32,
166 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
167 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
168 },
169 [PORT_OCTEON] = {
170 .name = "OCTEON",
171 .fifo_size = 64,
172 .tx_loadsz = 64,
173 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
174 .flags = UART_CAP_FIFO,
175 },
176 [PORT_AR7] = {
177 .name = "AR7",
178 .fifo_size = 16,
179 .tx_loadsz = 16,
180 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
181 .flags = UART_CAP_FIFO | UART_CAP_AFE,
182 },
183 [PORT_U6_16550A] = {
184 .name = "U6_16550A",
185 .fifo_size = 64,
186 .tx_loadsz = 64,
187 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
188 .flags = UART_CAP_FIFO | UART_CAP_AFE,
189 },
190 [PORT_TEGRA] = {
191 .name = "Tegra",
192 .fifo_size = 32,
193 .tx_loadsz = 8,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 UART_FCR_T_TRIG_01,
196 .rxtrig_bytes = {1, 4, 8, 14},
197 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
198 },
199 [PORT_XR17D15X] = {
200 .name = "XR17D15X",
201 .fifo_size = 64,
202 .tx_loadsz = 64,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
204 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
205 UART_CAP_SLEEP,
206 },
207 [PORT_XR17V35X] = {
208 .name = "XR17V35X",
209 .fifo_size = 256,
210 .tx_loadsz = 256,
211 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
212 UART_FCR_T_TRIG_11,
213 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
214 UART_CAP_SLEEP,
215 },
216 [PORT_LPC3220] = {
217 .name = "LPC3220",
218 .fifo_size = 64,
219 .tx_loadsz = 32,
220 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
221 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
222 .flags = UART_CAP_FIFO,
223 },
224 [PORT_BRCM_TRUMANAGE] = {
225 .name = "TruManage",
226 .fifo_size = 1,
227 .tx_loadsz = 1024,
228 .flags = UART_CAP_HFIFO,
229 },
230 [PORT_8250_CIR] = {
231 .name = "CIR port"
232 },
233 [PORT_ALTR_16550_F32] = {
234 .name = "Altera 16550 FIFO32",
235 .fifo_size = 32,
236 .tx_loadsz = 32,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
238 .flags = UART_CAP_FIFO | UART_CAP_AFE,
239 },
240 [PORT_ALTR_16550_F64] = {
241 .name = "Altera 16550 FIFO64",
242 .fifo_size = 64,
243 .tx_loadsz = 64,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 },
247 [PORT_ALTR_16550_F128] = {
248 .name = "Altera 16550 FIFO128",
249 .fifo_size = 128,
250 .tx_loadsz = 128,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 },
740dc2de
AW		 254 /*
255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 * workaround of errata A-008006 which states that tx_loadsz should
257 * be configured less than Maximum supported fifo bytes.
258 */
b6830f6d
PH		 259 [PORT_16550A_FSL64] = {
260 .name = "16550A_FSL64",
261 .fifo_size = 64,
262 .tx_loadsz = 63,
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
264 UART_FCR7_64BYTE,
265 .flags = UART_CAP_FIFO,
266 },
3c5a0357
MR		 267 [PORT_RT2880] = {
268 .name = "Palmchip BK-3103",
269 .fifo_size = 16,
270 .tx_loadsz = 16,
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 .rxtrig_bytes = {1, 4, 8, 14},
273 .flags = UART_CAP_FIFO,
274 },
b6830f6d
PH		 275};
276
277/* Uart divisor latch read */
278static int default_serial_dl_read(struct uart_8250_port *up)
279{
280 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
281}
282
283/* Uart divisor latch write */
284static void default_serial_dl_write(struct uart_8250_port *up, int value)
285{
286 serial_out(up, UART_DLL, value & 0xff);
287 serial_out(up, UART_DLM, value >> 8 & 0xff);
288}
289
9b2256c8 290#ifdef CONFIG_SERIAL_8250_RT288X
b6830f6d
PH		 291
292/* Au1x00/RT288x UART hardware has a weird register layout */
293static const s8 au_io_in_map[8] = {
294 0, /* UART_RX */
295 2, /* UART_IER */
296 3, /* UART_IIR */
297 5, /* UART_LCR */
298 6, /* UART_MCR */
299 7, /* UART_LSR */
300 8, /* UART_MSR */
301 -1, /* UART_SCR (unmapped) */
302};
303
304static const s8 au_io_out_map[8] = {
305 1, /* UART_TX */
306 2, /* UART_IER */
307 4, /* UART_FCR */
308 5, /* UART_LCR */
309 6, /* UART_MCR */
310 -1, /* UART_LSR (unmapped) */
311 -1, /* UART_MSR (unmapped) */
312 -1, /* UART_SCR (unmapped) */
313};
314
315static unsigned int au_serial_in(struct uart_port *p, int offset)
316{
317 if (offset >= ARRAY_SIZE(au_io_in_map))
318 return UINT_MAX;
319 offset = au_io_in_map[offset];
320 if (offset < 0)
321 return UINT_MAX;
322 return __raw_readl(p->membase + (offset << p->regshift));
323}
324
325static void au_serial_out(struct uart_port *p, int offset, int value)
326{
327 if (offset >= ARRAY_SIZE(au_io_out_map))
328 return;
329 offset = au_io_out_map[offset];
330 if (offset < 0)
331 return;
332 __raw_writel(value, p->membase + (offset << p->regshift));
333}
334
335/* Au1x00 haven't got a standard divisor latch */
336static int au_serial_dl_read(struct uart_8250_port *up)
337{
338 return __raw_readl(up->port.membase + 0x28);
339}
340
341static void au_serial_dl_write(struct uart_8250_port *up, int value)
342{
343 __raw_writel(value, up->port.membase + 0x28);
344}
345
346#endif
347
348static unsigned int hub6_serial_in(struct uart_port *p, int offset)
349{
350 offset = offset << p->regshift;
351 outb(p->hub6 - 1 + offset, p->iobase);
352 return inb(p->iobase + 1);
353}
354
355static void hub6_serial_out(struct uart_port *p, int offset, int value)
356{
357 offset = offset << p->regshift;
358 outb(p->hub6 - 1 + offset, p->iobase);
359 outb(value, p->iobase + 1);
360}
361
362static unsigned int mem_serial_in(struct uart_port *p, int offset)
363{
364 offset = offset << p->regshift;
365 return readb(p->membase + offset);
366}
367
368static void mem_serial_out(struct uart_port *p, int offset, int value)
369{
370 offset = offset << p->regshift;
371 writeb(value, p->membase + offset);
372}
373
bd94c407
MY		 374static void mem16_serial_out(struct uart_port *p, int offset, int value)
375{
376 offset = offset << p->regshift;
377 writew(value, p->membase + offset);
378}
379
380static unsigned int mem16_serial_in(struct uart_port *p, int offset)
381{
382 offset = offset << p->regshift;
383 return readw(p->membase + offset);
384}
385
b6830f6d
PH		 386static void mem32_serial_out(struct uart_port *p, int offset, int value)
387{
388 offset = offset << p->regshift;
389 writel(value, p->membase + offset);
390}
391
392static unsigned int mem32_serial_in(struct uart_port *p, int offset)
393{
394 offset = offset << p->regshift;
395 return readl(p->membase + offset);
396}
397
398static void mem32be_serial_out(struct uart_port *p, int offset, int value)
399{
400 offset = offset << p->regshift;
401 iowrite32be(value, p->membase + offset);
402}
403
404static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
405{
406 offset = offset << p->regshift;
407 return ioread32be(p->membase + offset);
408}
409
410static unsigned int io_serial_in(struct uart_port *p, int offset)
411{
412 offset = offset << p->regshift;
413 return inb(p->iobase + offset);
414}
415
416static void io_serial_out(struct uart_port *p, int offset, int value)
417{
418 offset = offset << p->regshift;
419 outb(value, p->iobase + offset);
420}
421
422static int serial8250_default_handle_irq(struct uart_port *port);
423static int exar_handle_irq(struct uart_port *port);
424
425static void set_io_from_upio(struct uart_port *p)
426{
427 struct uart_8250_port *up = up_to_u8250p(p);
428
429 up->dl_read = default_serial_dl_read;
430 up->dl_write = default_serial_dl_write;
431
432 switch (p->iotype) {
433 case UPIO_HUB6:
434 p->serial_in = hub6_serial_in;
435 p->serial_out = hub6_serial_out;
436 break;
437
438 case UPIO_MEM:
439 p->serial_in = mem_serial_in;
440 p->serial_out = mem_serial_out;
441 break;
442
bd94c407
MY		 443 case UPIO_MEM16:
444 p->serial_in = mem16_serial_in;
445 p->serial_out = mem16_serial_out;
446 break;
447
b6830f6d
PH		 448 case UPIO_MEM32:
449 p->serial_in = mem32_serial_in;
450 p->serial_out = mem32_serial_out;
451 break;
452
453 case UPIO_MEM32BE:
454 p->serial_in = mem32be_serial_in;
455 p->serial_out = mem32be_serial_out;
456 break;
457
9b2256c8 458#ifdef CONFIG_SERIAL_8250_RT288X
b6830f6d
PH		 459 case UPIO_AU:
460 p->serial_in = au_serial_in;
461 p->serial_out = au_serial_out;
462 up->dl_read = au_serial_dl_read;
463 up->dl_write = au_serial_dl_write;
464 break;
465#endif
466
467 default:
468 p->serial_in = io_serial_in;
469 p->serial_out = io_serial_out;
470 break;
471 }
472 /* Remember loaded iotype */
473 up->cur_iotype = p->iotype;
474 p->handle_irq = serial8250_default_handle_irq;
475}
476
477static void
478serial_port_out_sync(struct uart_port *p, int offset, int value)
479{
480 switch (p->iotype) {
481 case UPIO_MEM:
bd94c407 482 case UPIO_MEM16:
b6830f6d
PH		 483 case UPIO_MEM32:
484 case UPIO_MEM32BE:
485 case UPIO_AU:
486 p->serial_out(p, offset, value);
487 p->serial_in(p, UART_LCR); /* safe, no side-effects */
488 break;
489 default:
490 p->serial_out(p, offset, value);
491 }
492}
493
494/*
495 * For the 16C950
496 */
497static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
498{
499 serial_out(up, UART_SCR, offset);
500 serial_out(up, UART_ICR, value);
501}
502
503static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
504{
505 unsigned int value;
506
507 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
508 serial_out(up, UART_SCR, offset);
509 value = serial_in(up, UART_ICR);
510 serial_icr_write(up, UART_ACR, up->acr);
511
512 return value;
513}
514
515/*
516 * FIFO support.
517 */
518static void serial8250_clear_fifos(struct uart_8250_port *p)
519{
520 if (p->capabilities & UART_CAP_FIFO) {
521 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
522 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
523 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
524 serial_out(p, UART_FCR, 0);
525 }
526}
527
e490c914
MK		 528static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p)
529{
36fd95b1 530 unsigned char mcr = serial8250_in_MCR(p);
e490c914
MK		 531
532 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
533 mcr |= UART_MCR_RTS;
534 else
535 mcr &= ~UART_MCR_RTS;
36fd95b1 536 serial8250_out_MCR(p, mcr);
e490c914
MK		 537}
538
539static void serial8250_em485_handle_start_tx(unsigned long arg);
540static void serial8250_em485_handle_stop_tx(unsigned long arg);
541
b6830f6d
PH		 542void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
543{
544 serial8250_clear_fifos(p);
545 serial_out(p, UART_FCR, p->fcr);
546}
547EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
548
549void serial8250_rpm_get(struct uart_8250_port *p)
550{
551 if (!(p->capabilities & UART_CAP_RPM))
552 return;
553 pm_runtime_get_sync(p->port.dev);
554}
555EXPORT_SYMBOL_GPL(serial8250_rpm_get);
556
557void serial8250_rpm_put(struct uart_8250_port *p)
558{
559 if (!(p->capabilities & UART_CAP_RPM))
560 return;
561 pm_runtime_mark_last_busy(p->port.dev);
562 pm_runtime_put_autosuspend(p->port.dev);
563}
564EXPORT_SYMBOL_GPL(serial8250_rpm_put);
565
e490c914
MK		 566/**
567 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
568 * @p: uart_8250_port port instance
569 *
570 * The function is used to start rs485 software emulating on the
571 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
572 * transmission. The function is idempotent, so it is safe to call it
573 * multiple times.
574 *
575 * The caller MUST enable interrupt on empty shift register before
576 * calling serial8250_em485_init(). This interrupt is not a part of
577 * 8250 standard, but implementation defined.
578 *
579 * The function is supposed to be called from .rs485_config callback
580 * or from any other callback protected with p->port.lock spinlock.
581 *
582 * See also serial8250_em485_destroy()
583 *
584 * Return 0 - success, -errno - otherwise
585 */
586int serial8250_em485_init(struct uart_8250_port *p)
587{
588 if (p->em485 != NULL)
589 return 0;
590
b18a183e 591 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
e490c914
MK		 592 if (p->em485 == NULL)
593 return -ENOMEM;
594
595 setup_timer(&p->em485->stop_tx_timer,
596 serial8250_em485_handle_stop_tx, (unsigned long)p);
597 setup_timer(&p->em485->start_tx_timer,
598 serial8250_em485_handle_start_tx, (unsigned long)p);
599 p->em485->active_timer = NULL;
600
601 serial8250_em485_rts_after_send(p);
602
603 return 0;
604}
605EXPORT_SYMBOL_GPL(serial8250_em485_init);
606
607/**
608 * serial8250_em485_destroy() - put uart_8250_port into normal state
609 * @p: uart_8250_port port instance
610 *
611 * The function is used to stop rs485 software emulating on the
612 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
613 * call it multiple times.
614 *
615 * The function is supposed to be called from .rs485_config callback
616 * or from any other callback protected with p->port.lock spinlock.
617 *
618 * See also serial8250_em485_init()
619 */
620void serial8250_em485_destroy(struct uart_8250_port *p)
621{
622 if (p->em485 == NULL)
623 return;
624
625 del_timer(&p->em485->start_tx_timer);
626 del_timer(&p->em485->stop_tx_timer);
627
628 kfree(p->em485);
629 p->em485 = NULL;
630}
631EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
632
b6830f6d
PH		 633/*
634 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
635 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
636 * empty and the HW can idle again.
637 */
638static void serial8250_rpm_get_tx(struct uart_8250_port *p)
639{
640 unsigned char rpm_active;
641
642 if (!(p->capabilities & UART_CAP_RPM))
643 return;
644
645 rpm_active = xchg(&p->rpm_tx_active, 1);
646 if (rpm_active)
647 return;
648 pm_runtime_get_sync(p->port.dev);
649}
650
651static void serial8250_rpm_put_tx(struct uart_8250_port *p)
652{
653 unsigned char rpm_active;
654
655 if (!(p->capabilities & UART_CAP_RPM))
656 return;
657
658 rpm_active = xchg(&p->rpm_tx_active, 0);
659 if (!rpm_active)
660 return;
661 pm_runtime_mark_last_busy(p->port.dev);
662 pm_runtime_put_autosuspend(p->port.dev);
663}
664
665/*
666 * IER sleep support. UARTs which have EFRs need the "extended
667 * capability" bit enabled. Note that on XR16C850s, we need to
668 * reset LCR to write to IER.
669 */
670static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
671{
672 unsigned char lcr = 0, efr = 0;
673 /*
674 * Exar UARTs have a SLEEP register that enables or disables
675 * each UART to enter sleep mode separately. On the XR17V35x the
676 * register is accessible to each UART at the UART_EXAR_SLEEP
677 * offset but the UART channel may only write to the corresponding
678 * bit.
679 */
680 serial8250_rpm_get(p);
681 if ((p->port.type == PORT_XR17V35X) ||
682 (p->port.type == PORT_XR17D15X)) {
683 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
684 goto out;
685 }
686
687 if (p->capabilities & UART_CAP_SLEEP) {
688 if (p->capabilities & UART_CAP_EFR) {
689 lcr = serial_in(p, UART_LCR);
690 efr = serial_in(p, UART_EFR);
691 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
692 serial_out(p, UART_EFR, UART_EFR_ECB);
693 serial_out(p, UART_LCR, 0);
694 }
695 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
696 if (p->capabilities & UART_CAP_EFR) {
697 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
698 serial_out(p, UART_EFR, efr);
699 serial_out(p, UART_LCR, lcr);
700 }
701 }
702out:
703 serial8250_rpm_put(p);
704}
705
706#ifdef CONFIG_SERIAL_8250_RSA
707/*
708 * Attempts to turn on the RSA FIFO. Returns zero on failure.
709 * We set the port uart clock rate if we succeed.
710 */
711static int __enable_rsa(struct uart_8250_port *up)
712{
713 unsigned char mode;
714 int result;
715
716 mode = serial_in(up, UART_RSA_MSR);
717 result = mode & UART_RSA_MSR_FIFO;
718
719 if (!result) {
720 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
721 mode = serial_in(up, UART_RSA_MSR);
722 result = mode & UART_RSA_MSR_FIFO;
723 }
724
725 if (result)
726 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
727
728 return result;
729}
730
731static void enable_rsa(struct uart_8250_port *up)
732{
733 if (up->port.type == PORT_RSA) {
734 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
735 spin_lock_irq(&up->port.lock);
736 __enable_rsa(up);
737 spin_unlock_irq(&up->port.lock);
738 }
739 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
740 serial_out(up, UART_RSA_FRR, 0);
741 }
742}
743
744/*
745 * Attempts to turn off the RSA FIFO. Returns zero on failure.
746 * It is unknown why interrupts were disabled in here. However,
747 * the caller is expected to preserve this behaviour by grabbing
748 * the spinlock before calling this function.
749 */
750static void disable_rsa(struct uart_8250_port *up)
751{
752 unsigned char mode;
753 int result;
754
755 if (up->port.type == PORT_RSA &&
756 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
757 spin_lock_irq(&up->port.lock);
758
759 mode = serial_in(up, UART_RSA_MSR);
760 result = !(mode & UART_RSA_MSR_FIFO);
761
762 if (!result) {
763 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
764 mode = serial_in(up, UART_RSA_MSR);
765 result = !(mode & UART_RSA_MSR_FIFO);
766 }
767
768 if (result)
769 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
770 spin_unlock_irq(&up->port.lock);
771 }
772}
773#endif /* CONFIG_SERIAL_8250_RSA */
774
775/*
776 * This is a quickie test to see how big the FIFO is.
777 * It doesn't work at all the time, more's the pity.
778 */
779static int size_fifo(struct uart_8250_port *up)
780{
781 unsigned char old_fcr, old_mcr, old_lcr;
782 unsigned short old_dl;
783 int count;
784
785 old_lcr = serial_in(up, UART_LCR);
786 serial_out(up, UART_LCR, 0);
787 old_fcr = serial_in(up, UART_FCR);
36fd95b1 788 old_mcr = serial8250_in_MCR(up);
b6830f6d
PH		 789 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
790 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
36fd95b1 791 serial8250_out_MCR(up, UART_MCR_LOOP);
b6830f6d
PH		 792 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
793 old_dl = serial_dl_read(up);
794 serial_dl_write(up, 0x0001);
795 serial_out(up, UART_LCR, 0x03);
796 for (count = 0; count < 256; count++)
797 serial_out(up, UART_TX, count);
798 mdelay(20);/* FIXME - schedule_timeout */
799 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
800 (count < 256); count++)
801 serial_in(up, UART_RX);
802 serial_out(up, UART_FCR, old_fcr);
36fd95b1 803 serial8250_out_MCR(up, old_mcr);
b6830f6d
PH		 804 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
805 serial_dl_write(up, old_dl);
806 serial_out(up, UART_LCR, old_lcr);
807
808 return count;
809}
810
811/*
812 * Read UART ID using the divisor method - set DLL and DLM to zero
813 * and the revision will be in DLL and device type in DLM. We
814 * preserve the device state across this.
815 */
816static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
817{
0b41ce99
SF		 818 unsigned char old_lcr;
819 unsigned int id, old_dl;
b6830f6d
PH		 820
821 old_lcr = serial_in(p, UART_LCR);
822 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
0b41ce99
SF		 823 old_dl = serial_dl_read(p);
824 serial_dl_write(p, 0);
825 id = serial_dl_read(p);
826 serial_dl_write(p, old_dl);
b6830f6d 827
b6830f6d
PH		 828 serial_out(p, UART_LCR, old_lcr);
829
830 return id;
831}
832
833/*
834 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
835 * When this function is called we know it is at least a StarTech
836 * 16650 V2, but it might be one of several StarTech UARTs, or one of
837 * its clones. (We treat the broken original StarTech 16650 V1 as a
838 * 16550, and why not? Startech doesn't seem to even acknowledge its
839 * existence.)
840 *
841 * What evil have men's minds wrought...
842 */
843static void autoconfig_has_efr(struct uart_8250_port *up)
844{
845 unsigned int id1, id2, id3, rev;
846
847 /*
848 * Everything with an EFR has SLEEP
849 */
850 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
851
852 /*
853 * First we check to see if it's an Oxford Semiconductor UART.
854 *
855 * If we have to do this here because some non-National
856 * Semiconductor clone chips lock up if you try writing to the
857 * LSR register (which serial_icr_read does)
858 */
859
860 /*
861 * Check for Oxford Semiconductor 16C950.
862 *
863 * EFR [4] must be set else this test fails.
864 *
865 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
866 * claims that it's needed for 952 dual UART's (which are not
867 * recommended for new designs).
868 */
869 up->acr = 0;
870 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
871 serial_out(up, UART_EFR, UART_EFR_ECB);
872 serial_out(up, UART_LCR, 0x00);
873 id1 = serial_icr_read(up, UART_ID1);
874 id2 = serial_icr_read(up, UART_ID2);
875 id3 = serial_icr_read(up, UART_ID3);
876 rev = serial_icr_read(up, UART_REV);
877
878 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
879
880 if (id1 == 0x16 && id2 == 0xC9 &&
881 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
882 up->port.type = PORT_16C950;
883
884 /*
885 * Enable work around for the Oxford Semiconductor 952 rev B
886 * chip which causes it to seriously miscalculate baud rates
887 * when DLL is 0.
888 */
889 if (id3 == 0x52 && rev == 0x01)
890 up->bugs |= UART_BUG_QUOT;
891 return;
892 }
893
894 /*
895 * We check for a XR16C850 by setting DLL and DLM to 0, and then
896 * reading back DLL and DLM. The chip type depends on the DLM
897 * value read back:
898 * 0x10 - XR16C850 and the DLL contains the chip revision.
899 * 0x12 - XR16C2850.
900 * 0x14 - XR16C854.
901 */
902 id1 = autoconfig_read_divisor_id(up);
903 DEBUG_AUTOCONF("850id=%04x ", id1);
904
905 id2 = id1 >> 8;
906 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
907 up->port.type = PORT_16850;
908 return;
909 }
910
911 /*
912 * It wasn't an XR16C850.
913 *
914 * We distinguish between the '654 and the '650 by counting
915 * how many bytes are in the FIFO. I'm using this for now,
916 * since that's the technique that was sent to me in the
917 * serial driver update, but I'm not convinced this works.
918 * I've had problems doing this in the past. -TYT
919 */
920 if (size_fifo(up) == 64)
921 up->port.type = PORT_16654;
922 else
923 up->port.type = PORT_16650V2;
924}
925
926/*
927 * We detected a chip without a FIFO. Only two fall into
928 * this category - the original 8250 and the 16450. The
929 * 16450 has a scratch register (accessible with LCR=0)
930 */
931static void autoconfig_8250(struct uart_8250_port *up)
932{
933 unsigned char scratch, status1, status2;
934
935 up->port.type = PORT_8250;
936
937 scratch = serial_in(up, UART_SCR);
938 serial_out(up, UART_SCR, 0xa5);
939 status1 = serial_in(up, UART_SCR);
940 serial_out(up, UART_SCR, 0x5a);
941 status2 = serial_in(up, UART_SCR);
942 serial_out(up, UART_SCR, scratch);
943
944 if (status1 == 0xa5 && status2 == 0x5a)
945 up->port.type = PORT_16450;
946}
947
948static int broken_efr(struct uart_8250_port *up)
949{
950 /*
951 * Exar ST16C2550 "A2" devices incorrectly detect as
952 * having an EFR, and report an ID of 0x0201. See
953 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
954 */
955 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
956 return 1;
957
958 return 0;
959}
960
961/*
962 * We know that the chip has FIFOs. Does it have an EFR? The
963 * EFR is located in the same register position as the IIR and
964 * we know the top two bits of the IIR are currently set. The
965 * EFR should contain zero. Try to read the EFR.
966 */
967static void autoconfig_16550a(struct uart_8250_port *up)
968{
969 unsigned char status1, status2;
970 unsigned int iersave;
971
972 up->port.type = PORT_16550A;
973 up->capabilities |= UART_CAP_FIFO;
974
975 /*
976 * XR17V35x UARTs have an extra divisor register, DLD
977 * that gets enabled with when DLAB is set which will
978 * cause the device to incorrectly match and assign
979 * port type to PORT_16650. The EFR for this UART is
980 * found at offset 0x09. Instead check the Deice ID (DVID)
981 * register for a 2, 4 or 8 port UART.
982 */
983 if (up->port.flags & UPF_EXAR_EFR) {
984 status1 = serial_in(up, UART_EXAR_DVID);
985 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
986 DEBUG_AUTOCONF("Exar XR17V35x ");
987 up->port.type = PORT_XR17V35X;
988 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
989 UART_CAP_SLEEP;
990
991 return;
992 }
993
994 }
995
996 /*
997 * Check for presence of the EFR when DLAB is set.
998 * Only ST16C650V1 UARTs pass this test.
999 */
1000 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1001 if (serial_in(up, UART_EFR) == 0) {
1002 serial_out(up, UART_EFR, 0xA8);
1003 if (serial_in(up, UART_EFR) != 0) {
1004 DEBUG_AUTOCONF("EFRv1 ");
1005 up->port.type = PORT_16650;
1006 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1007 } else {
1008 serial_out(up, UART_LCR, 0);
1009 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1010 UART_FCR7_64BYTE);
1011 status1 = serial_in(up, UART_IIR) >> 5;
1012 serial_out(up, UART_FCR, 0);
1013 serial_out(up, UART_LCR, 0);
1014
1015 if (status1 == 7)
1016 up->port.type = PORT_16550A_FSL64;
1017 else
1018 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1019 }
1020 serial_out(up, UART_EFR, 0);
1021 return;
1022 }
1023
1024 /*
1025 * Maybe it requires 0xbf to be written to the LCR.
1026 * (other ST16C650V2 UARTs, TI16C752A, etc)
1027 */
1028 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1029 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1030 DEBUG_AUTOCONF("EFRv2 ");
1031 autoconfig_has_efr(up);
1032 return;
1033 }
1034
1035 /*
1036 * Check for a National Semiconductor SuperIO chip.
1037 * Attempt to switch to bank 2, read the value of the LOOP bit
1038 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1039 * switch back to bank 2, read it from EXCR1 again and check
1040 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1041 */
1042 serial_out(up, UART_LCR, 0);
36fd95b1 1043 status1 = serial8250_in_MCR(up);
b6830f6d
PH		 1044 serial_out(up, UART_LCR, 0xE0);
1045 status2 = serial_in(up, 0x02); /* EXCR1 */
1046
1047 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1048 serial_out(up, UART_LCR, 0);
36fd95b1 1049 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
b6830f6d
PH		 1050 serial_out(up, UART_LCR, 0xE0);
1051 status2 = serial_in(up, 0x02); /* EXCR1 */
1052 serial_out(up, UART_LCR, 0);
36fd95b1 1053 serial8250_out_MCR(up, status1);
b6830f6d
PH		 1054
1055 if ((status2 ^ status1) & UART_MCR_LOOP) {
1056 unsigned short quot;
1057
1058 serial_out(up, UART_LCR, 0xE0);
1059
1060 quot = serial_dl_read(up);
1061 quot <<= 3;
1062
1063 if (ns16550a_goto_highspeed(up))
1064 serial_dl_write(up, quot);
1065
1066 serial_out(up, UART_LCR, 0);
1067
1068 up->port.uartclk = 921600*16;
1069 up->port.type = PORT_NS16550A;
1070 up->capabilities |= UART_NATSEMI;
1071 return;
1072 }
1073 }
1074
1075 /*
1076 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1077 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1078 * Try setting it with and without DLAB set. Cheap clones
1079 * set bit 5 without DLAB set.
1080 */
1081 serial_out(up, UART_LCR, 0);
1082 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1083 status1 = serial_in(up, UART_IIR) >> 5;
1084 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1085 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1086 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1087 status2 = serial_in(up, UART_IIR) >> 5;
1088 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1089 serial_out(up, UART_LCR, 0);
1090
1091 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1092
1093 if (status1 == 6 && status2 == 7) {
1094 up->port.type = PORT_16750;
1095 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1096 return;
1097 }
1098
1099 /*
1100 * Try writing and reading the UART_IER_UUE bit (b6).
1101 * If it works, this is probably one of the Xscale platform's
1102 * internal UARTs.
1103 * We're going to explicitly set the UUE bit to 0 before
1104 * trying to write and read a 1 just to make sure it's not
1105 * already a 1 and maybe locked there before we even start start.
1106 */
1107 iersave = serial_in(up, UART_IER);
1108 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1109 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1110 /*
1111 * OK it's in a known zero state, try writing and reading
1112 * without disturbing the current state of the other bits.
1113 */
1114 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1115 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1116 /*
1117 * It's an Xscale.
1118 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1119 */
1120 DEBUG_AUTOCONF("Xscale ");
1121 up->port.type = PORT_XSCALE;
1122 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1123 return;
1124 }
1125 } else {
1126 /*
1127 * If we got here we couldn't force the IER_UUE bit to 0.
1128 * Log it and continue.
1129 */
1130 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1131 }
1132 serial_out(up, UART_IER, iersave);
1133
1134 /*
1135 * Exar uarts have EFR in a weird location
1136 */
1137 if (up->port.flags & UPF_EXAR_EFR) {
1138 DEBUG_AUTOCONF("Exar XR17D15x ");
1139 up->port.type = PORT_XR17D15X;
1140 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1141 UART_CAP_SLEEP;
1142
1143 return;
1144 }
1145
1146 /*
1147 * We distinguish between 16550A and U6 16550A by counting
1148 * how many bytes are in the FIFO.
1149 */
1150 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1151 up->port.type = PORT_U6_16550A;
1152 up->capabilities |= UART_CAP_AFE;
1153 }
1154}
1155
1156/*
1157 * This routine is called by rs_init() to initialize a specific serial
1158 * port. It determines what type of UART chip this serial port is
1159 * using: 8250, 16450, 16550, 16550A. The important question is
1160 * whether or not this UART is a 16550A or not, since this will
1161 * determine whether or not we can use its FIFO features or not.
1162 */
1163static void autoconfig(struct uart_8250_port *up)
1164{
1165 unsigned char status1, scratch, scratch2, scratch3;
1166 unsigned char save_lcr, save_mcr;
1167 struct uart_port *port = &up->port;
1168 unsigned long flags;
1169 unsigned int old_capabilities;
1170
1171 if (!port->iobase && !port->mapbase && !port->membase)
1172 return;
1173
1174 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1175 serial_index(port), port->iobase, port->membase);
1176
1177 /*
1178 * We really do need global IRQs disabled here - we're going to
1179 * be frobbing the chips IRQ enable register to see if it exists.
1180 */
1181 spin_lock_irqsave(&port->lock, flags);
1182
1183 up->capabilities = 0;
1184 up->bugs = 0;
1185
1186 if (!(port->flags & UPF_BUGGY_UART)) {
1187 /*
1188 * Do a simple existence test first; if we fail this,
1189 * there's no point trying anything else.
1190 *
1191 * 0x80 is used as a nonsense port to prevent against
1192 * false positives due to ISA bus float. The
1193 * assumption is that 0x80 is a non-existent port;
1194 * which should be safe since include/asm/io.h also
1195 * makes this assumption.
1196 *
1197 * Note: this is safe as long as MCR bit 4 is clear
1198 * and the device is in "PC" mode.
1199 */
1200 scratch = serial_in(up, UART_IER);
1201 serial_out(up, UART_IER, 0);
1202#ifdef __i386__
1203 outb(0xff, 0x080);
1204#endif
1205 /*
1206 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1207 * 16C754B) allow only to modify them if an EFR bit is set.
1208 */
1209 scratch2 = serial_in(up, UART_IER) & 0x0f;
1210 serial_out(up, UART_IER, 0x0F);
1211#ifdef __i386__
1212 outb(0, 0x080);
1213#endif
1214 scratch3 = serial_in(up, UART_IER) & 0x0f;
1215 serial_out(up, UART_IER, scratch);
1216 if (scratch2 != 0 || scratch3 != 0x0F) {
1217 /*
1218 * We failed; there's nothing here
1219 */
1220 spin_unlock_irqrestore(&port->lock, flags);
1221 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1222 scratch2, scratch3);
1223 goto out;
1224 }
1225 }
1226
36fd95b1 1227 save_mcr = serial8250_in_MCR(up);
b6830f6d
PH		 1228 save_lcr = serial_in(up, UART_LCR);
1229
1230 /*
1231 * Check to see if a UART is really there. Certain broken
1232 * internal modems based on the Rockwell chipset fail this
1233 * test, because they apparently don't implement the loopback
1234 * test mode. So this test is skipped on the COM 1 through
1235 * COM 4 ports. This *should* be safe, since no board
1236 * manufacturer would be stupid enough to design a board
1237 * that conflicts with COM 1-4 --- we hope!
1238 */
1239 if (!(port->flags & UPF_SKIP_TEST)) {
36fd95b1 1240 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
b6830f6d 1241 status1 = serial_in(up, UART_MSR) & 0xF0;
36fd95b1 1242 serial8250_out_MCR(up, save_mcr);
b6830f6d
PH		 1243 if (status1 != 0x90) {
1244 spin_unlock_irqrestore(&port->lock, flags);
1245 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1246 status1);
1247 goto out;
1248 }
1249 }
1250
1251 /*
1252 * We're pretty sure there's a port here. Lets find out what
1253 * type of port it is. The IIR top two bits allows us to find
1254 * out if it's 8250 or 16450, 16550, 16550A or later. This
1255 * determines what we test for next.
1256 *
1257 * We also initialise the EFR (if any) to zero for later. The
1258 * EFR occupies the same register location as the FCR and IIR.
1259 */
1260 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1261 serial_out(up, UART_EFR, 0);
1262 serial_out(up, UART_LCR, 0);
1263
1264 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1265 scratch = serial_in(up, UART_IIR) >> 6;
1266
1267 switch (scratch) {
1268 case 0:
1269 autoconfig_8250(up);
1270 break;
1271 case 1:
1272 port->type = PORT_UNKNOWN;
1273 break;
1274 case 2:
1275 port->type = PORT_16550;
1276 break;
1277 case 3:
1278 autoconfig_16550a(up);
1279 break;
1280 }
1281
1282#ifdef CONFIG_SERIAL_8250_RSA
1283 /*
1284 * Only probe for RSA ports if we got the region.
1285 */
1286 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1287 __enable_rsa(up))
1288 port->type = PORT_RSA;
1289#endif
1290
1291 serial_out(up, UART_LCR, save_lcr);
1292
1293 port->fifosize = uart_config[up->port.type].fifo_size;
1294 old_capabilities = up->capabilities;
1295 up->capabilities = uart_config[port->type].flags;
1296 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1297
1298 if (port->type == PORT_UNKNOWN)
1299 goto out_lock;
1300
1301 /*
1302 * Reset the UART.
1303 */
1304#ifdef CONFIG_SERIAL_8250_RSA
1305 if (port->type == PORT_RSA)
1306 serial_out(up, UART_RSA_FRR, 0);
1307#endif
36fd95b1 1308 serial8250_out_MCR(up, save_mcr);
b6830f6d
PH		 1309 serial8250_clear_fifos(up);
1310 serial_in(up, UART_RX);
1311 if (up->capabilities & UART_CAP_UUE)
1312 serial_out(up, UART_IER, UART_IER_UUE);
1313 else
1314 serial_out(up, UART_IER, 0);
1315
1316out_lock:
1317 spin_unlock_irqrestore(&port->lock, flags);
fa01e2ca
RRD		 1318
1319 /*
1320 * Check if the device is a Fintek F81216A
1321 */
1322 if (port->type == PORT_16550A)
1323 fintek_8250_probe(up);
1324
b6830f6d 1325 if (up->capabilities != old_capabilities) {
9f59fbf0 1326 pr_warn("ttyS%d: detected caps %08x should be %08x\n",
b6830f6d
PH		 1327 serial_index(port), old_capabilities,
1328 up->capabilities);
1329 }
1330out:
1331 DEBUG_AUTOCONF("iir=%d ", scratch);
1332 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1333}
1334
1335static void autoconfig_irq(struct uart_8250_port *up)
1336{
1337 struct uart_port *port = &up->port;
1338 unsigned char save_mcr, save_ier;
1339 unsigned char save_ICP = 0;
1340 unsigned int ICP = 0;
1341 unsigned long irqs;
1342 int irq;
1343
1344 if (port->flags & UPF_FOURPORT) {
1345 ICP = (port->iobase & 0xfe0) | 0x1f;
1346 save_ICP = inb_p(ICP);
1347 outb_p(0x80, ICP);
1348 inb_p(ICP);
1349 }
1350
9a23a1d1
TK		 1351 if (uart_console(port))
1352 console_lock();
1353
b6830f6d
PH		 1354 /* forget possible initially masked and pending IRQ */
1355 probe_irq_off(probe_irq_on());
36fd95b1 1356 save_mcr = serial8250_in_MCR(up);
b6830f6d 1357 save_ier = serial_in(up, UART_IER);
36fd95b1 1358 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
b6830f6d
PH		 1359
1360 irqs = probe_irq_on();
36fd95b1 1361 serial8250_out_MCR(up, 0);
b6830f6d
PH		 1362 udelay(10);
1363 if (port->flags & UPF_FOURPORT) {
36fd95b1 1364 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
b6830f6d 1365 } else {
36fd95b1
YY		 1366 serial8250_out_MCR(up,
1367 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
b6830f6d
PH		 1368 }
1369 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1370 serial_in(up, UART_LSR);
1371 serial_in(up, UART_RX);
1372 serial_in(up, UART_IIR);
1373 serial_in(up, UART_MSR);
1374 serial_out(up, UART_TX, 0xFF);
1375 udelay(20);
1376 irq = probe_irq_off(irqs);
1377
36fd95b1 1378 serial8250_out_MCR(up, save_mcr);
b6830f6d
PH		 1379 serial_out(up, UART_IER, save_ier);
1380
1381 if (port->flags & UPF_FOURPORT)
1382 outb_p(save_ICP, ICP);
1383
9a23a1d1
TK		 1384 if (uart_console(port))
1385 console_unlock();
1386
b6830f6d
PH		 1387 port->irq = (irq > 0) ? irq : 0;
1388}
1389
a07a70bc
MK		 1390static void serial8250_stop_rx(struct uart_port *port)
1391{
1392 struct uart_8250_port *up = up_to_u8250p(port);
1393
1394 serial8250_rpm_get(up);
1395
1396 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1397 up->port.read_status_mask &= ~UART_LSR_DR;
1398 serial_port_out(port, UART_IER, up->ier);
1399
1400 serial8250_rpm_put(up);
1401}
1402
e490c914
MK		 1403static void __do_stop_tx_rs485(struct uart_8250_port *p)
1404{
1405 if (!p->em485)
1406 return;
1407
1408 serial8250_em485_rts_after_send(p);
1409 /*
1410 * Empty the RX FIFO, we are not interested in anything
1411 * received during the half-duplex transmission.
0c66940d 1412 * Enable previously disabled RX interrupts.
e490c914 1413 */
0c66940d 1414 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
e490c914 1415 serial8250_clear_fifos(p);
0c66940d
YY		 1416
1417 serial8250_rpm_get(p);
1418
1419 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1420 serial_port_out(&p->port, UART_IER, p->ier);
1421
1422 serial8250_rpm_put(p);
1423 }
e490c914
MK		 1424}
1425
1426static void serial8250_em485_handle_stop_tx(unsigned long arg)
1427{
1428 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1429 struct uart_8250_em485 *em485 = p->em485;
1430 unsigned long flags;
1431
1432 spin_lock_irqsave(&p->port.lock, flags);
1433 if (em485 &&
1434 em485->active_timer == &em485->stop_tx_timer) {
1435 __do_stop_tx_rs485(p);
1436 em485->active_timer = NULL;
1437 }
1438 spin_unlock_irqrestore(&p->port.lock, flags);
1439}
1440
1441static void __stop_tx_rs485(struct uart_8250_port *p)
1442{
1443 struct uart_8250_em485 *em485 = p->em485;
1444
1445 if (!em485)
1446 return;
1447
1448 /*
1449 * __do_stop_tx_rs485 is going to set RTS according to config
1450 * AND flush RX FIFO if required.
1451 */
1452 if (p->port.rs485.delay_rts_after_send > 0) {
1453 em485->active_timer = &em485->stop_tx_timer;
1454 mod_timer(&em485->stop_tx_timer, jiffies +
1455 p->port.rs485.delay_rts_after_send * HZ / 1000);
1456 } else {
1457 __do_stop_tx_rs485(p);
1458 }
1459}
1460
1461static inline void __do_stop_tx(struct uart_8250_port *p)
b6830f6d
PH		 1462{
1463 if (p->ier & UART_IER_THRI) {
1464 p->ier &= ~UART_IER_THRI;
1465 serial_out(p, UART_IER, p->ier);
1466 serial8250_rpm_put_tx(p);
1467 }
1468}
1469
e490c914
MK		 1470static inline void __stop_tx(struct uart_8250_port *p)
1471{
1472 struct uart_8250_em485 *em485 = p->em485;
1473
1474 if (em485) {
1475 unsigned char lsr = serial_in(p, UART_LSR);
1476 /*
1477 * To provide required timeing and allow FIFO transfer,
1478 * __stop_tx_rs485 must be called only when both FIFO and
1479 * shift register are empty. It is for device driver to enable
1480 * interrupt on TEMT.
1481 */
1482 if ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
1483 return;
1484
1485 del_timer(&em485->start_tx_timer);
1486 em485->active_timer = NULL;
1487 }
1488 __do_stop_tx(p);
1489 __stop_tx_rs485(p);
1490}
1491
b6830f6d
PH		 1492static void serial8250_stop_tx(struct uart_port *port)
1493{
1494 struct uart_8250_port *up = up_to_u8250p(port);
1495
1496 serial8250_rpm_get(up);
1497 __stop_tx(up);
1498
1499 /*
1500 * We really want to stop the transmitter from sending.
1501 */
1502 if (port->type == PORT_16C950) {
1503 up->acr |= UART_ACR_TXDIS;
1504 serial_icr_write(up, UART_ACR, up->acr);
1505 }
1506 serial8250_rpm_put(up);
1507}
1508
e490c914 1509static inline void __start_tx(struct uart_port *port)
b6830f6d
PH		 1510{
1511 struct uart_8250_port *up = up_to_u8250p(port);
1512
b6830f6d
PH		 1513 if (up->dma && !up->dma->tx_dma(up))
1514 return;
1515
1516 if (!(up->ier & UART_IER_THRI)) {
1517 up->ier |= UART_IER_THRI;
1518 serial_port_out(port, UART_IER, up->ier);
1519
1520 if (up->bugs & UART_BUG_TXEN) {
1521 unsigned char lsr;
1a33e342 1522
b6830f6d
PH		 1523 lsr = serial_in(up, UART_LSR);
1524 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1525 if (lsr & UART_LSR_THRE)
1526 serial8250_tx_chars(up);
1527 }
1528 }
1529
1530 /*
1531 * Re-enable the transmitter if we disabled it.
1532 */
1533 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1534 up->acr &= ~UART_ACR_TXDIS;
1535 serial_icr_write(up, UART_ACR, up->acr);
1536 }
1537}
1538
e490c914
MK		 1539static inline void start_tx_rs485(struct uart_port *port)
1540{
1541 struct uart_8250_port *up = up_to_u8250p(port);
1542 struct uart_8250_em485 *em485 = up->em485;
1543 unsigned char mcr;
1544
1545 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1546 serial8250_stop_rx(&up->port);
1547
1548 del_timer(&em485->stop_tx_timer);
1549 em485->active_timer = NULL;
1550
36fd95b1 1551 mcr = serial8250_in_MCR(up);
e490c914
MK		 1552 if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) !=
1553 !!(mcr & UART_MCR_RTS)) {
1554 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1555 mcr |= UART_MCR_RTS;
1556 else
1557 mcr &= ~UART_MCR_RTS;
36fd95b1 1558 serial8250_out_MCR(up, mcr);
e490c914
MK		 1559
1560 if (up->port.rs485.delay_rts_before_send > 0) {
1561 em485->active_timer = &em485->start_tx_timer;
1562 mod_timer(&em485->start_tx_timer, jiffies +
1563 up->port.rs485.delay_rts_before_send * HZ / 1000);
1564 return;
1565 }
1566 }
1567
1568 __start_tx(port);
1569}
1570
1571static void serial8250_em485_handle_start_tx(unsigned long arg)
1572{
1573 struct uart_8250_port *p = (struct uart_8250_port *)arg;
1574 struct uart_8250_em485 *em485 = p->em485;
1575 unsigned long flags;
1576
1577 spin_lock_irqsave(&p->port.lock, flags);
1578 if (em485 &&
1579 em485->active_timer == &em485->start_tx_timer) {
1580 __start_tx(&p->port);
1581 em485->active_timer = NULL;
1582 }
1583 spin_unlock_irqrestore(&p->port.lock, flags);
1584}
1585
1586static void serial8250_start_tx(struct uart_port *port)
1587{
1588 struct uart_8250_port *up = up_to_u8250p(port);
1589 struct uart_8250_em485 *em485 = up->em485;
1590
1591 serial8250_rpm_get_tx(up);
1592
1593 if (em485 &&
1594 em485->active_timer == &em485->start_tx_timer)
1595 return;
1596
1597 if (em485)
1598 start_tx_rs485(port);
1599 else
1600 __start_tx(port);
1601}
1602
b6830f6d
PH		 1603static void serial8250_throttle(struct uart_port *port)
1604{
1605 port->throttle(port);
1606}
1607
1608static void serial8250_unthrottle(struct uart_port *port)
1609{
1610 port->unthrottle(port);
1611}
1612
b6830f6d
PH		 1613static void serial8250_disable_ms(struct uart_port *port)
1614{
013e3586 1615 struct uart_8250_port *up = up_to_u8250p(port);
b6830f6d
PH		 1616
1617 /* no MSR capabilities */
1618 if (up->bugs & UART_BUG_NOMSR)
1619 return;
1620
1621 up->ier &= ~UART_IER_MSI;
1622 serial_port_out(port, UART_IER, up->ier);
1623}
1624
1625static void serial8250_enable_ms(struct uart_port *port)
1626{
1627 struct uart_8250_port *up = up_to_u8250p(port);
1628
1629 /* no MSR capabilities */
1630 if (up->bugs & UART_BUG_NOMSR)
1631 return;
1632
1633 up->ier |= UART_IER_MSI;
1634
1635 serial8250_rpm_get(up);
1636 serial_port_out(port, UART_IER, up->ier);
1637 serial8250_rpm_put(up);
1638}
1639
3f6b3ce0
PH		 1640static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr)
1641{
1642 struct uart_port *port = &up->port;
1643 unsigned char ch;
1644 char flag = TTY_NORMAL;
1645
1646 if (likely(lsr & UART_LSR_DR))
1647 ch = serial_in(up, UART_RX);
1648 else
1649 /*
1650 * Intel 82571 has a Serial Over Lan device that will
1651 * set UART_LSR_BI without setting UART_LSR_DR when
1652 * it receives a break. To avoid reading from the
1653 * receive buffer without UART_LSR_DR bit set, we
1654 * just force the read character to be 0
1655 */
1656 ch = 0;
1657
1658 port->icount.rx++;
1659
1660 lsr |= up->lsr_saved_flags;
1661 up->lsr_saved_flags = 0;
1662
1663 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1664 if (lsr & UART_LSR_BI) {
1665 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1666 port->icount.brk++;
1667 /*
1668 * We do the SysRQ and SAK checking
1669 * here because otherwise the break
1670 * may get masked by ignore_status_mask
1671 * or read_status_mask.
1672 */
1673 if (uart_handle_break(port))
1674 return;
1675 } else if (lsr & UART_LSR_PE)
1676 port->icount.parity++;
1677 else if (lsr & UART_LSR_FE)
1678 port->icount.frame++;
1679 if (lsr & UART_LSR_OE)
1680 port->icount.overrun++;
1681
1682 /*
1683 * Mask off conditions which should be ignored.
1684 */
1685 lsr &= port->read_status_mask;
1686
1687 if (lsr & UART_LSR_BI) {
934014d5 1688 pr_debug("%s: handling break\n", __func__);
3f6b3ce0
PH		 1689 flag = TTY_BREAK;
1690 } else if (lsr & UART_LSR_PE)
1691 flag = TTY_PARITY;
1692 else if (lsr & UART_LSR_FE)
1693 flag = TTY_FRAME;
1694 }
1695 if (uart_handle_sysrq_char(port, ch))
1696 return;
1697
1698 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1699}
1700
b6830f6d
PH		 1701/*
1702 * serial8250_rx_chars: processes according to the passed in LSR
1703 * value, and returns the remaining LSR bits not handled
1704 * by this Rx routine.
1705 */
d22f8f10 1706unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
b6830f6d
PH		 1707{
1708 struct uart_port *port = &up->port;
b6830f6d 1709 int max_count = 256;
b6830f6d
PH		 1710
1711 do {
3f6b3ce0 1712 serial8250_read_char(up, lsr);
d22f8f10
PH		 1713 if (--max_count == 0)
1714 break;
b6830f6d 1715 lsr = serial_in(up, UART_LSR);
d22f8f10 1716 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
6a597a38 1717
b6830f6d 1718 tty_flip_buffer_push(&port->state->port);
b6830f6d
PH		 1719 return lsr;
1720}
1721EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1722
1723void serial8250_tx_chars(struct uart_8250_port *up)
1724{
1725 struct uart_port *port = &up->port;
1726 struct circ_buf *xmit = &port->state->xmit;
1727 int count;
1728
1729 if (port->x_char) {
1730 serial_out(up, UART_TX, port->x_char);
1731 port->icount.tx++;
1732 port->x_char = 0;
1733 return;
1734 }
1735 if (uart_tx_stopped(port)) {
1736 serial8250_stop_tx(port);
1737 return;
1738 }
1739 if (uart_circ_empty(xmit)) {
1740 __stop_tx(up);
1741 return;
1742 }
1743
1744 count = up->tx_loadsz;
1745 do {
1746 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1747 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1748 port->icount.tx++;
1749 if (uart_circ_empty(xmit))
1750 break;
cee10c8c
PH		 1751 if ((up->capabilities & UART_CAP_HFIFO) &&
1752 (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY)
1753 break;
b6830f6d
PH		 1754 } while (--count > 0);
1755
1756 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1757 uart_write_wakeup(port);
1758
934014d5 1759 pr_debug("%s: THRE\n", __func__);
b6830f6d
PH		 1760
1761 /*
1762 * With RPM enabled, we have to wait until the FIFO is empty before the
1763 * HW can go idle. So we get here once again with empty FIFO and disable
1764 * the interrupt and RPM in __stop_tx()
1765 */
1766 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1767 __stop_tx(up);
1768}
1769EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1770
1771/* Caller holds uart port lock */
1772unsigned int serial8250_modem_status(struct uart_8250_port *up)
1773{
1774 struct uart_port *port = &up->port;
1775 unsigned int status = serial_in(up, UART_MSR);
1776
1777 status |= up->msr_saved_flags;
1778 up->msr_saved_flags = 0;
1779 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1780 port->state != NULL) {
1781 if (status & UART_MSR_TERI)
1782 port->icount.rng++;
1783 if (status & UART_MSR_DDSR)
1784 port->icount.dsr++;
1785 if (status & UART_MSR_DDCD)
1786 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1787 if (status & UART_MSR_DCTS)
1788 uart_handle_cts_change(port, status & UART_MSR_CTS);
1789
1790 wake_up_interruptible(&port->state->port.delta_msr_wait);
1791 }
1792
1793 return status;
1794}
1795EXPORT_SYMBOL_GPL(serial8250_modem_status);
1796
33d9b8b2
PH		 1797static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1798{
1799 switch (iir & 0x3f) {
1800 case UART_IIR_RX_TIMEOUT:
1801 serial8250_rx_dma_flush(up);
1802 /* fall-through */
1803 case UART_IIR_RLSI:
1804 return true;
1805 }
1806 return up->dma->rx_dma(up);
1807}
1808
b6830f6d
PH		 1809/*
1810 * This handles the interrupt from one port.
1811 */
1812int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1813{
1814 unsigned char status;
1815 unsigned long flags;
1816 struct uart_8250_port *up = up_to_u8250p(port);
b6830f6d
PH		 1817
1818 if (iir & UART_IIR_NO_INT)
1819 return 0;
1820
1821 spin_lock_irqsave(&port->lock, flags);
1822
1823 status = serial_port_in(port, UART_LSR);
1824
934014d5 1825 pr_debug("%s: status = %x\n", __func__, status);
b6830f6d
PH		 1826
1827 if (status & (UART_LSR_DR | UART_LSR_BI)) {
33d9b8b2 1828 if (!up->dma || handle_rx_dma(up, iir))
b6830f6d
PH		 1829 status = serial8250_rx_chars(up, status);
1830 }
1831 serial8250_modem_status(up);
d601744d 1832 if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE))
b6830f6d
PH		 1833 serial8250_tx_chars(up);
1834
1835 spin_unlock_irqrestore(&port->lock, flags);
1836 return 1;
1837}
1838EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1839
1840static int serial8250_default_handle_irq(struct uart_port *port)
1841{
1842 struct uart_8250_port *up = up_to_u8250p(port);
1843 unsigned int iir;
1844 int ret;
1845
1846 serial8250_rpm_get(up);
1847
1848 iir = serial_port_in(port, UART_IIR);
1849 ret = serial8250_handle_irq(port, iir);
1850
1851 serial8250_rpm_put(up);
1852 return ret;
1853}
1854
1855/*
1856 * These Exar UARTs have an extra interrupt indicator that could
1857 * fire for a few unimplemented interrupts. One of which is a
1858 * wakeup event when coming out of sleep. Put this here just
1859 * to be on the safe side that these interrupts don't go unhandled.
1860 */
1861static int exar_handle_irq(struct uart_port *port)
1862{
b6830f6d
PH		 1863 unsigned int iir = serial_port_in(port, UART_IIR);
1864 int ret;
1865
1866 ret = serial8250_handle_irq(port, iir);
1867
1868 if ((port->type == PORT_XR17V35X) ||
1869 (port->type == PORT_XR17D15X)) {
17b2720b
JS		 1870 serial_port_in(port, 0x80);
1871 serial_port_in(port, 0x81);
1872 serial_port_in(port, 0x82);
1873 serial_port_in(port, 0x83);
b6830f6d
PH		 1874 }
1875
1876 return ret;
1877}
1878
1879static unsigned int serial8250_tx_empty(struct uart_port *port)
1880{
1881 struct uart_8250_port *up = up_to_u8250p(port);
1882 unsigned long flags;
1883 unsigned int lsr;
1884
1885 serial8250_rpm_get(up);
1886
1887 spin_lock_irqsave(&port->lock, flags);
1888 lsr = serial_port_in(port, UART_LSR);
1889 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1890 spin_unlock_irqrestore(&port->lock, flags);
1891
1892 serial8250_rpm_put(up);
1893
1894 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1895}
1896
144ef5c2 1897unsigned int serial8250_do_get_mctrl(struct uart_port *port)
b6830f6d
PH		 1898{
1899 struct uart_8250_port *up = up_to_u8250p(port);
1900 unsigned int status;
1901 unsigned int ret;
1902
1903 serial8250_rpm_get(up);
1904 status = serial8250_modem_status(up);
1905 serial8250_rpm_put(up);
1906
1907 ret = 0;
1908 if (status & UART_MSR_DCD)
1909 ret |= TIOCM_CAR;
1910 if (status & UART_MSR_RI)
1911 ret |= TIOCM_RNG;
1912 if (status & UART_MSR_DSR)
1913 ret |= TIOCM_DSR;
1914 if (status & UART_MSR_CTS)
1915 ret |= TIOCM_CTS;
5db4f7f8 1916 return ret;
b6830f6d 1917}
144ef5c2
WAZ		 1918EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1919
1920static unsigned int serial8250_get_mctrl(struct uart_port *port)
1921{
1922 if (port->get_mctrl)
1923 return port->get_mctrl(port);
1924 return serial8250_do_get_mctrl(port);
1925}
b6830f6d
PH		 1926
1927void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1928{
1929 struct uart_8250_port *up = up_to_u8250p(port);
1930 unsigned char mcr = 0;
1931
1932 if (mctrl & TIOCM_RTS)
1933 mcr |= UART_MCR_RTS;
1934 if (mctrl & TIOCM_DTR)
1935 mcr |= UART_MCR_DTR;
1936 if (mctrl & TIOCM_OUT1)
1937 mcr |= UART_MCR_OUT1;
1938 if (mctrl & TIOCM_OUT2)
1939 mcr |= UART_MCR_OUT2;
1940 if (mctrl & TIOCM_LOOP)
1941 mcr |= UART_MCR_LOOP;
1942
1943 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1944
36fd95b1 1945 serial8250_out_MCR(up, mcr);
b6830f6d
PH		 1946}
1947EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
1948
1949static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1950{
1951 if (port->set_mctrl)
1952 port->set_mctrl(port, mctrl);
1953 else
1954 serial8250_do_set_mctrl(port, mctrl);
1955}
1956
1957static void serial8250_break_ctl(struct uart_port *port, int break_state)
1958{
1959 struct uart_8250_port *up = up_to_u8250p(port);
1960 unsigned long flags;
1961
1962 serial8250_rpm_get(up);
1963 spin_lock_irqsave(&port->lock, flags);
1964 if (break_state == -1)
1965 up->lcr |= UART_LCR_SBC;
1966 else
1967 up->lcr &= ~UART_LCR_SBC;
1968 serial_port_out(port, UART_LCR, up->lcr);
1969 spin_unlock_irqrestore(&port->lock, flags);
1970 serial8250_rpm_put(up);
1971}
1972
1973/*
1974 * Wait for transmitter & holding register to empty
1975 */
1976static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1977{
1978 unsigned int status, tmout = 10000;
1979
1980 /* Wait up to 10ms for the character(s) to be sent. */
1981 for (;;) {
1982 status = serial_in(up, UART_LSR);
1983
1984 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1985
1986 if ((status & bits) == bits)
1987 break;
1988 if (--tmout == 0)
1989 break;
1990 udelay(1);
1991 }
1992
1993 /* Wait up to 1s for flow control if necessary */
1994 if (up->port.flags & UPF_CONS_FLOW) {
b6830f6d
PH		 1995 for (tmout = 1000000; tmout; tmout--) {
1996 unsigned int msr = serial_in(up, UART_MSR);
1997 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1998 if (msr & UART_MSR_CTS)
1999 break;
2000 udelay(1);
2001 touch_nmi_watchdog();
2002 }
2003 }
2004}
2005
2006#ifdef CONFIG_CONSOLE_POLL
2007/*
2008 * Console polling routines for writing and reading from the uart while
2009 * in an interrupt or debug context.
2010 */
2011
2012static int serial8250_get_poll_char(struct uart_port *port)
2013{
2014 struct uart_8250_port *up = up_to_u8250p(port);
2015 unsigned char lsr;
2016 int status;
2017
2018 serial8250_rpm_get(up);
2019
2020 lsr = serial_port_in(port, UART_LSR);
2021
2022 if (!(lsr & UART_LSR_DR)) {
2023 status = NO_POLL_CHAR;
2024 goto out;
2025 }
2026
2027 status = serial_port_in(port, UART_RX);
2028out:
2029 serial8250_rpm_put(up);
2030 return status;
2031}
2032
2033
2034static void serial8250_put_poll_char(struct uart_port *port,
2035 unsigned char c)
2036{
2037 unsigned int ier;
2038 struct uart_8250_port *up = up_to_u8250p(port);
2039
2040 serial8250_rpm_get(up);
2041 /*
2042 * First save the IER then disable the interrupts
2043 */
2044 ier = serial_port_in(port, UART_IER);
2045 if (up->capabilities & UART_CAP_UUE)
2046 serial_port_out(port, UART_IER, UART_IER_UUE);
2047 else
2048 serial_port_out(port, UART_IER, 0);
2049
2050 wait_for_xmitr(up, BOTH_EMPTY);
2051 /*
2052 * Send the character out.
2053 */
2054 serial_port_out(port, UART_TX, c);
2055
2056 /*
2057 * Finally, wait for transmitter to become empty
2058 * and restore the IER
2059 */
2060 wait_for_xmitr(up, BOTH_EMPTY);
2061 serial_port_out(port, UART_IER, ier);
2062 serial8250_rpm_put(up);
2063}
2064
2065#endif /* CONFIG_CONSOLE_POLL */
2066
2067int serial8250_do_startup(struct uart_port *port)
2068{
2069 struct uart_8250_port *up = up_to_u8250p(port);
2070 unsigned long flags;
2071 unsigned char lsr, iir;
2072 int retval;
2073
b6830f6d
PH		 2074 if (!port->fifosize)
2075 port->fifosize = uart_config[port->type].fifo_size;
2076 if (!up->tx_loadsz)
2077 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2078 if (!up->capabilities)
2079 up->capabilities = uart_config[port->type].flags;
2080 up->mcr = 0;
2081
2082 if (port->iotype != up->cur_iotype)
2083 set_io_from_upio(port);
2084
2085 serial8250_rpm_get(up);
2086 if (port->type == PORT_16C950) {
2087 /* Wake up and initialize UART */
2088 up->acr = 0;
2089 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2090 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2091 serial_port_out(port, UART_IER, 0);
2092 serial_port_out(port, UART_LCR, 0);
2093 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2094 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2095 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2096 serial_port_out(port, UART_LCR, 0);
2097 }
2098
2099#ifdef CONFIG_SERIAL_8250_RSA
2100 /*
2101 * If this is an RSA port, see if we can kick it up to the
2102 * higher speed clock.
2103 */
2104 enable_rsa(up);
2105#endif
da891641
JR		 2106
2107 if (port->type == PORT_XR17V35X) {
2108 /*
2109 * First enable access to IER [7:5], ISR [5:4], FCR [5:4],
2110 * MCR [7:5] and MSR [7:0]
2111 */
2112 serial_port_out(port, UART_XR_EFR, UART_EFR_ECB);
2113
2114 /*
2115 * Make sure all interrups are masked until initialization is
2116 * complete and the FIFOs are cleared
2117 */
2118 serial_port_out(port, UART_IER, 0);
2119 }
2120
b6830f6d
PH		 2121 /*
2122 * Clear the FIFO buffers and disable them.
2123 * (they will be reenabled in set_termios())
2124 */
2125 serial8250_clear_fifos(up);
2126
2127 /*
2128 * Clear the interrupt registers.
2129 */
2130 serial_port_in(port, UART_LSR);
2131 serial_port_in(port, UART_RX);
2132 serial_port_in(port, UART_IIR);
2133 serial_port_in(port, UART_MSR);
2134
2135 /*
2136 * At this point, there's no way the LSR could still be 0xff;
2137 * if it is, then bail out, because there's likely no UART
2138 * here.
2139 */
2140 if (!(port->flags & UPF_BUGGY_UART) &&
2141 (serial_port_in(port, UART_LSR) == 0xff)) {
2142 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2143 serial_index(port));
2144 retval = -ENODEV;
2145 goto out;
2146 }
2147
2148 /*
2149 * For a XR16C850, we need to set the trigger levels
2150 */
2151 if (port->type == PORT_16850) {
2152 unsigned char fctr;
2153
2154 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2155
2156 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2157 serial_port_out(port, UART_FCTR,
2158 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2159 serial_port_out(port, UART_TRG, UART_TRG_96);
2160 serial_port_out(port, UART_FCTR,
2161 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2162 serial_port_out(port, UART_TRG, UART_TRG_96);
2163
2164 serial_port_out(port, UART_LCR, 0);
2165 }
2166
2167 if (port->irq) {
2168 unsigned char iir1;
2169 /*
2170 * Test for UARTs that do not reassert THRE when the
2171 * transmitter is idle and the interrupt has already
2172 * been cleared. Real 16550s should always reassert
2173 * this interrupt whenever the transmitter is idle and
2174 * the interrupt is enabled. Delays are necessary to
2175 * allow register changes to become visible.
2176 */
2177 spin_lock_irqsave(&port->lock, flags);
2178 if (up->port.irqflags & IRQF_SHARED)
2179 disable_irq_nosync(port->irq);
2180
2181 wait_for_xmitr(up, UART_LSR_THRE);
2182 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2183 udelay(1); /* allow THRE to set */
2184 iir1 = serial_port_in(port, UART_IIR);
2185 serial_port_out(port, UART_IER, 0);
2186 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2187 udelay(1); /* allow a working UART time to re-assert THRE */
2188 iir = serial_port_in(port, UART_IIR);
2189 serial_port_out(port, UART_IER, 0);
2190
2191 if (port->irqflags & IRQF_SHARED)
2192 enable_irq(port->irq);
2193 spin_unlock_irqrestore(&port->lock, flags);
2194
2195 /*
2196 * If the interrupt is not reasserted, or we otherwise
2197 * don't trust the iir, setup a timer to kick the UART
2198 * on a regular basis.
2199 */
2200 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2201 up->port.flags & UPF_BUG_THRE) {
2202 up->bugs |= UART_BUG_THRE;
2203 }
2204 }
2205
2206 retval = up->ops->setup_irq(up);
2207 if (retval)
2208 goto out;
2209
2210 /*
2211 * Now, initialize the UART
2212 */
2213 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2214
2215 spin_lock_irqsave(&port->lock, flags);
2216 if (up->port.flags & UPF_FOURPORT) {
2217 if (!up->port.irq)
2218 up->port.mctrl |= TIOCM_OUT1;
2219 } else
2220 /*
2221 * Most PC uarts need OUT2 raised to enable interrupts.
2222 */
2223 if (port->irq)
2224 up->port.mctrl |= TIOCM_OUT2;
2225
2226 serial8250_set_mctrl(port, port->mctrl);
2227
740dc2de
AW		 2228 /*
2229 * Serial over Lan (SoL) hack:
2230 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2231 * used for Serial Over Lan. Those chips take a longer time than a
2232 * normal serial device to signalize that a transmission data was
2233 * queued. Due to that, the above test generally fails. One solution
2234 * would be to delay the reading of iir. However, this is not
2235 * reliable, since the timeout is variable. So, let's just don't
2236 * test if we receive TX irq. This way, we'll never enable
2237 * UART_BUG_TXEN.
b6830f6d
PH		 2238 */
2239 if (up->port.flags & UPF_NO_TXEN_TEST)
2240 goto dont_test_tx_en;
2241
2242 /*
740dc2de
AW		 2243 * Do a quick test to see if we receive an interrupt when we enable
2244 * the TX irq.
b6830f6d
PH		 2245 */
2246 serial_port_out(port, UART_IER, UART_IER_THRI);
2247 lsr = serial_port_in(port, UART_LSR);
2248 iir = serial_port_in(port, UART_IIR);
2249 serial_port_out(port, UART_IER, 0);
2250
2251 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2252 if (!(up->bugs & UART_BUG_TXEN)) {
2253 up->bugs |= UART_BUG_TXEN;
2254 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2255 serial_index(port));
2256 }
2257 } else {
2258 up->bugs &= ~UART_BUG_TXEN;
2259 }
2260
2261dont_test_tx_en:
2262 spin_unlock_irqrestore(&port->lock, flags);
2263
2264 /*
2265 * Clear the interrupt registers again for luck, and clear the
2266 * saved flags to avoid getting false values from polling
2267 * routines or the previous session.
2268 */
2269 serial_port_in(port, UART_LSR);
2270 serial_port_in(port, UART_RX);
2271 serial_port_in(port, UART_IIR);
2272 serial_port_in(port, UART_MSR);
2273 up->lsr_saved_flags = 0;
2274 up->msr_saved_flags = 0;
2275
2276 /*
2277 * Request DMA channels for both RX and TX.
2278 */
2279 if (up->dma) {
2280 retval = serial8250_request_dma(up);
2281 if (retval) {
2282 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2283 serial_index(port));
2284 up->dma = NULL;
2285 }
2286 }
2287
2288 /*
ee3ad90b
PH		 2289 * Set the IER shadow for rx interrupts but defer actual interrupt
2290 * enable until after the FIFOs are enabled; otherwise, an already-
2291 * active sender can swamp the interrupt handler with "too much work".
b6830f6d
PH		 2292 */
2293 up->ier = UART_IER_RLSI | UART_IER_RDI;
b6830f6d
PH		 2294
2295 if (port->flags & UPF_FOURPORT) {
2296 unsigned int icp;
2297 /*
2298 * Enable interrupts on the AST Fourport board
2299 */
2300 icp = (port->iobase & 0xfe0) | 0x01f;
2301 outb_p(0x80, icp);
2302 inb_p(icp);
2303 }
2304 retval = 0;
2305out:
2306 serial8250_rpm_put(up);
2307 return retval;
2308}
2309EXPORT_SYMBOL_GPL(serial8250_do_startup);
2310
2311static int serial8250_startup(struct uart_port *port)
2312{
2313 if (port->startup)
2314 return port->startup(port);
2315 return serial8250_do_startup(port);
2316}
2317
2318void serial8250_do_shutdown(struct uart_port *port)
2319{
2320 struct uart_8250_port *up = up_to_u8250p(port);
2321 unsigned long flags;
2322
2323 serial8250_rpm_get(up);
2324 /*
2325 * Disable interrupts from this port
2326 */
611e0d83 2327 spin_lock_irqsave(&port->lock, flags);
b6830f6d
PH		 2328 up->ier = 0;
2329 serial_port_out(port, UART_IER, 0);
611e0d83
PH		 2330 spin_unlock_irqrestore(&port->lock, flags);
2331
2332 synchronize_irq(port->irq);
b6830f6d
PH		 2333
2334 if (up->dma)
2335 serial8250_release_dma(up);
2336
2337 spin_lock_irqsave(&port->lock, flags);
2338 if (port->flags & UPF_FOURPORT) {
2339 /* reset interrupts on the AST Fourport board */
2340 inb((port->iobase & 0xfe0) | 0x1f);
2341 port->mctrl |= TIOCM_OUT1;
2342 } else
2343 port->mctrl &= ~TIOCM_OUT2;
2344
2345 serial8250_set_mctrl(port, port->mctrl);
2346 spin_unlock_irqrestore(&port->lock, flags);
2347
2348 /*
2349 * Disable break condition and FIFOs
2350 */
2351 serial_port_out(port, UART_LCR,
2352 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2353 serial8250_clear_fifos(up);
2354
2355#ifdef CONFIG_SERIAL_8250_RSA
2356 /*
2357 * Reset the RSA board back to 115kbps compat mode.
2358 */
2359 disable_rsa(up);
2360#endif
2361
2362 /*
2363 * Read data port to reset things, and then unlink from
2364 * the IRQ chain.
2365 */
2366 serial_port_in(port, UART_RX);
2367 serial8250_rpm_put(up);
2368
2369 up->ops->release_irq(up);
2370}
2371EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2372
2373static void serial8250_shutdown(struct uart_port *port)
2374{
2375 if (port->shutdown)
2376 port->shutdown(port);
2377 else
2378 serial8250_do_shutdown(port);
2379}
2380
2381/*
2382 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2383 * Calculate divisor with extra 4-bit fractional portion
2384 */
2385static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2386 unsigned int baud,
2387 unsigned int *frac)
2388{
2389 struct uart_port *port = &up->port;
2390 unsigned int quot_16;
2391
2392 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2393 *frac = quot_16 & 0x0f;
2394
2395 return quot_16 >> 4;
2396}
2397
2398static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2399 unsigned int baud,
2400 unsigned int *frac)
2401{
2402 struct uart_port *port = &up->port;
2403 unsigned int quot;
2404
2405 /*
2406 * Handle magic divisors for baud rates above baud_base on
2407 * SMSC SuperIO chips.
2408 *
2409 */
2410 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2411 baud == (port->uartclk/4))
2412 quot = 0x8001;
2413 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2414 baud == (port->uartclk/8))
2415 quot = 0x8002;
2416 else if (up->port.type == PORT_XR17V35X)
2417 quot = xr17v35x_get_divisor(up, baud, frac);
2418 else
2419 quot = uart_get_divisor(port, baud);
2420
2421 /*
2422 * Oxford Semi 952 rev B workaround
2423 */
2424 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2425 quot++;
2426
2427 return quot;
2428}
2429
2430static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2431 tcflag_t c_cflag)
2432{
2433 unsigned char cval;
2434
2435 switch (c_cflag & CSIZE) {
2436 case CS5:
2437 cval = UART_LCR_WLEN5;
2438 break;
2439 case CS6:
2440 cval = UART_LCR_WLEN6;
2441 break;
2442 case CS7:
2443 cval = UART_LCR_WLEN7;
2444 break;
2445 default:
2446 case CS8:
2447 cval = UART_LCR_WLEN8;
2448 break;
2449 }
2450
2451 if (c_cflag & CSTOPB)
2452 cval |= UART_LCR_STOP;
2453 if (c_cflag & PARENB) {
2454 cval |= UART_LCR_PARITY;
2455 if (up->bugs & UART_BUG_PARITY)
2456 up->fifo_bug = true;
2457 }
2458 if (!(c_cflag & PARODD))
2459 cval |= UART_LCR_EPAR;
2460#ifdef CMSPAR
2461 if (c_cflag & CMSPAR)
2462 cval |= UART_LCR_SPAR;
2463#endif
2464
2465 return cval;
2466}
2467
2468static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2469 unsigned int quot, unsigned int quot_frac)
2470{
2471 struct uart_8250_port *up = up_to_u8250p(port);
2472
2473 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2474 if (is_omap1510_8250(up)) {
2475 if (baud == 115200) {
2476 quot = 1;
2477 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2478 } else
2479 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2480 }
2481
2482 /*
2483 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2484 * otherwise just set DLAB
2485 */
2486 if (up->capabilities & UART_NATSEMI)
2487 serial_port_out(port, UART_LCR, 0xe0);
2488 else
2489 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2490
2491 serial_dl_write(up, quot);
2492
2493 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2494 if (up->port.type == PORT_XR17V35X)
2495 serial_port_out(port, 0x2, quot_frac);
2496}
2497
b3d67936
AW		 2498static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2499 struct ktermios *termios,
2500 struct ktermios *old)
4f56f3fd
JH		 2501{
2502 unsigned int tolerance = port->uartclk / 100;
2503
2504 /*
2505 * Ask the core to calculate the divisor for us.
2506 * Allow 1% tolerance at the upper limit so uart clks marginally
2507 * slower than nominal still match standard baud rates without
2508 * causing transmission errors.
2509 */
2510 return uart_get_baud_rate(port, termios, old,
2511 port->uartclk / 16 / 0xffff,
2512 (port->uartclk + tolerance) / 16);
2513}
2514
b6830f6d
PH		 2515void
2516serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
6d7c157f 2517 struct ktermios *old)
b6830f6d
PH		 2518{
2519 struct uart_8250_port *up = up_to_u8250p(port);
2520 unsigned char cval;
2521 unsigned long flags;
2522 unsigned int baud, quot, frac = 0;
2523
2524 cval = serial8250_compute_lcr(up, termios->c_cflag);
2525
4f56f3fd 2526 baud = serial8250_get_baud_rate(port, termios, old);
b6830f6d
PH		 2527 quot = serial8250_get_divisor(up, baud, &frac);
2528
2529 /*
2530 * Ok, we're now changing the port state. Do it with
2531 * interrupts disabled.
2532 */
2533 serial8250_rpm_get(up);
2534 spin_lock_irqsave(&port->lock, flags);
2535
2536 up->lcr = cval; /* Save computed LCR */
2537
2538 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2539 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2540 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2541 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2542 up->fcr |= UART_FCR_TRIGGER_1;
2543 }
2544 }
2545
2546 /*
2547 * MCR-based auto flow control. When AFE is enabled, RTS will be
2548 * deasserted when the receive FIFO contains more characters than
2549 * the trigger, or the MCR RTS bit is cleared. In the case where
2550 * the remote UART is not using CTS auto flow control, we must
2551 * have sufficient FIFO entries for the latency of the remote
2552 * UART to respond. IOW, at least 32 bytes of FIFO.
2553 */
2554 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2555 up->mcr &= ~UART_MCR_AFE;
2556 if (termios->c_cflag & CRTSCTS)
2557 up->mcr |= UART_MCR_AFE;
2558 }
2559
2560 /*
2561 * Update the per-port timeout.
2562 */
2563 uart_update_timeout(port, termios->c_cflag, baud);
2564
2565 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2566 if (termios->c_iflag & INPCK)
2567 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2568 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2569 port->read_status_mask |= UART_LSR_BI;
2570
2571 /*
2572 * Characteres to ignore
2573 */
2574 port->ignore_status_mask = 0;
2575 if (termios->c_iflag & IGNPAR)
2576 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2577 if (termios->c_iflag & IGNBRK) {
2578 port->ignore_status_mask |= UART_LSR_BI;
2579 /*
2580 * If we're ignoring parity and break indicators,
2581 * ignore overruns too (for real raw support).
2582 */
2583 if (termios->c_iflag & IGNPAR)
2584 port->ignore_status_mask |= UART_LSR_OE;
2585 }
2586
2587 /*
2588 * ignore all characters if CREAD is not set
2589 */
2590 if ((termios->c_cflag & CREAD) == 0)
2591 port->ignore_status_mask |= UART_LSR_DR;
2592
2593 /*
2594 * CTS flow control flag and modem status interrupts
2595 */
2596 up->ier &= ~UART_IER_MSI;
2597 if (!(up->bugs & UART_BUG_NOMSR) &&
2598 UART_ENABLE_MS(&up->port, termios->c_cflag))
2599 up->ier |= UART_IER_MSI;
2600 if (up->capabilities & UART_CAP_UUE)
2601 up->ier |= UART_IER_UUE;
2602 if (up->capabilities & UART_CAP_RTOIE)
2603 up->ier |= UART_IER_RTOIE;
2604
2605 serial_port_out(port, UART_IER, up->ier);
2606
2607 if (up->capabilities & UART_CAP_EFR) {
2608 unsigned char efr = 0;
2609 /*
2610 * TI16C752/Startech hardware flow control. FIXME:
2611 * - TI16C752 requires control thresholds to be set.
2612 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2613 */
2614 if (termios->c_cflag & CRTSCTS)
2615 efr |= UART_EFR_CTS;
2616
2617 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2618 if (port->flags & UPF_EXAR_EFR)
2619 serial_port_out(port, UART_XR_EFR, efr);
2620 else
2621 serial_port_out(port, UART_EFR, efr);
2622 }
2623
2624 serial8250_set_divisor(port, baud, quot, frac);
2625
2626 /*
2627 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2628 * is written without DLAB set, this mode will be disabled.
2629 */
2630 if (port->type == PORT_16750)
2631 serial_port_out(port, UART_FCR, up->fcr);
2632
2633 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2634 if (port->type != PORT_16750) {
2635 /* emulated UARTs (Lucent Venus 167x) need two steps */
2636 if (up->fcr & UART_FCR_ENABLE_FIFO)
2637 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2638 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2639 }
2640 serial8250_set_mctrl(port, port->mctrl);
2641 spin_unlock_irqrestore(&port->lock, flags);
2642 serial8250_rpm_put(up);
2643
2644 /* Don't rewrite B0 */
2645 if (tty_termios_baud_rate(termios))
2646 tty_termios_encode_baud_rate(termios, baud, baud);
2647}
2648EXPORT_SYMBOL(serial8250_do_set_termios);
2649
2650static void
2651serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2652 struct ktermios *old)
2653{
2654 if (port->set_termios)
2655 port->set_termios(port, termios, old);
2656 else
2657 serial8250_do_set_termios(port, termios, old);
2658}
2659
2660static void
2661serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2662{
2663 if (termios->c_line == N_PPS) {
2664 port->flags |= UPF_HARDPPS_CD;
2665 spin_lock_irq(&port->lock);
2666 serial8250_enable_ms(port);
2667 spin_unlock_irq(&port->lock);
2668 } else {
2669 port->flags &= ~UPF_HARDPPS_CD;
2670 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2671 spin_lock_irq(&port->lock);
2672 serial8250_disable_ms(port);
2673 spin_unlock_irq(&port->lock);
2674 }
2675 }
2676}
2677
2678
2679void serial8250_do_pm(struct uart_port *port, unsigned int state,
2680 unsigned int oldstate)
2681{
2682 struct uart_8250_port *p = up_to_u8250p(port);
2683
2684 serial8250_set_sleep(p, state != 0);
2685}
2686EXPORT_SYMBOL(serial8250_do_pm);
2687
2688static void
2689serial8250_pm(struct uart_port *port, unsigned int state,
2690 unsigned int oldstate)
2691{
2692 if (port->pm)
2693 port->pm(port, state, oldstate);
2694 else
2695 serial8250_do_pm(port, state, oldstate);
2696}
2697
2698static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2699{
2700 if (pt->port.mapsize)
2701 return pt->port.mapsize;
2702 if (pt->port.iotype == UPIO_AU) {
2703 if (pt->port.type == PORT_RT2880)
2704 return 0x100;
2705 return 0x1000;
2706 }
2707 if (is_omap1_8250(pt))
2708 return 0x16 << pt->port.regshift;
2709
2710 return 8 << pt->port.regshift;
2711}
2712
2713/*
2714 * Resource handling.
2715 */
2716static int serial8250_request_std_resource(struct uart_8250_port *up)
2717{
2718 unsigned int size = serial8250_port_size(up);
2719 struct uart_port *port = &up->port;
2720 int ret = 0;
2721
2722 switch (port->iotype) {
2723 case UPIO_AU:
2724 case UPIO_TSI:
2725 case UPIO_MEM32:
2726 case UPIO_MEM32BE:
bd94c407 2727 case UPIO_MEM16:
b6830f6d
PH		 2728 case UPIO_MEM:
2729 if (!port->mapbase)
2730 break;
2731
2732 if (!request_mem_region(port->mapbase, size, "serial")) {
2733 ret = -EBUSY;
2734 break;
2735 }
2736
2737 if (port->flags & UPF_IOREMAP) {
2738 port->membase = ioremap_nocache(port->mapbase, size);
2739 if (!port->membase) {
2740 release_mem_region(port->mapbase, size);
2741 ret = -ENOMEM;
2742 }
2743 }
2744 break;
2745
2746 case UPIO_HUB6:
2747 case UPIO_PORT:
2748 if (!request_region(port->iobase, size, "serial"))
2749 ret = -EBUSY;
2750 break;
2751 }
2752 return ret;
2753}
2754
2755static void serial8250_release_std_resource(struct uart_8250_port *up)
2756{
2757 unsigned int size = serial8250_port_size(up);
2758 struct uart_port *port = &up->port;
2759
2760 switch (port->iotype) {
2761 case UPIO_AU:
2762 case UPIO_TSI:
2763 case UPIO_MEM32:
2764 case UPIO_MEM32BE:
bd94c407 2765 case UPIO_MEM16:
b6830f6d
PH		 2766 case UPIO_MEM:
2767 if (!port->mapbase)
2768 break;
2769
2770 if (port->flags & UPF_IOREMAP) {
2771 iounmap(port->membase);
2772 port->membase = NULL;
2773 }
2774
2775 release_mem_region(port->mapbase, size);
2776 break;
2777
2778 case UPIO_HUB6:
2779 case UPIO_PORT:
2780 release_region(port->iobase, size);
2781 break;
2782 }
2783}
2784
2785static void serial8250_release_port(struct uart_port *port)
2786{
2787 struct uart_8250_port *up = up_to_u8250p(port);
2788
2789 serial8250_release_std_resource(up);
2790}
2791
2792static int serial8250_request_port(struct uart_port *port)
2793{
2794 struct uart_8250_port *up = up_to_u8250p(port);
b6830f6d 2795
e4fda3a0 2796 return serial8250_request_std_resource(up);
b6830f6d
PH		 2797}
2798
2799static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2800{
2801 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2802 unsigned char bytes;
2803
2804 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2805
2806 return bytes ? bytes : -EOPNOTSUPP;
2807}
2808
2809static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2810{
2811 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2812 int i;
2813
2814 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2815 return -EOPNOTSUPP;
2816
2817 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2818 if (bytes < conf_type->rxtrig_bytes[i])
2819 /* Use the nearest lower value */
2820 return (--i) << UART_FCR_R_TRIG_SHIFT;
2821 }
2822
2823 return UART_FCR_R_TRIG_11;
2824}
2825
2826static int do_get_rxtrig(struct tty_port *port)
2827{
2828 struct uart_state *state = container_of(port, struct uart_state, port);
2829 struct uart_port *uport = state->uart_port;
013e3586 2830 struct uart_8250_port *up = up_to_u8250p(uport);
b6830f6d
PH		 2831
2832 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2833 return -EINVAL;
2834
2835 return fcr_get_rxtrig_bytes(up);
2836}
2837
2838static int do_serial8250_get_rxtrig(struct tty_port *port)
2839{
2840 int rxtrig_bytes;
2841
2842 mutex_lock(&port->mutex);
2843 rxtrig_bytes = do_get_rxtrig(port);
2844 mutex_unlock(&port->mutex);
2845
2846 return rxtrig_bytes;
2847}
2848
2849static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2850 struct device_attribute *attr, char *buf)
2851{
2852 struct tty_port *port = dev_get_drvdata(dev);
2853 int rxtrig_bytes;
2854
2855 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2856 if (rxtrig_bytes < 0)
2857 return rxtrig_bytes;
2858
2859 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2860}
2861
2862static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2863{
2864 struct uart_state *state = container_of(port, struct uart_state, port);
2865 struct uart_port *uport = state->uart_port;
013e3586 2866 struct uart_8250_port *up = up_to_u8250p(uport);
b6830f6d
PH		 2867 int rxtrig;
2868
2869 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2870 up->fifo_bug)
2871 return -EINVAL;
2872
2873 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2874 if (rxtrig < 0)
2875 return rxtrig;
2876
2877 serial8250_clear_fifos(up);
2878 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2879 up->fcr |= (unsigned char)rxtrig;
2880 serial_out(up, UART_FCR, up->fcr);
2881 return 0;
2882}
2883
2884static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2885{
2886 int ret;
2887
2888 mutex_lock(&port->mutex);
2889 ret = do_set_rxtrig(port, bytes);
2890 mutex_unlock(&port->mutex);
2891
2892 return ret;
2893}
2894
2895static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2896 struct device_attribute *attr, const char *buf, size_t count)
2897{
2898 struct tty_port *port = dev_get_drvdata(dev);
2899 unsigned char bytes;
2900 int ret;
2901
2902 if (!count)
2903 return -EINVAL;
2904
2905 ret = kstrtou8(buf, 10, &bytes);
2906 if (ret < 0)
2907 return ret;
2908
2909 ret = do_serial8250_set_rxtrig(port, bytes);
2910 if (ret < 0)
2911 return ret;
2912
2913 return count;
2914}
2915
2916static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2917 serial8250_get_attr_rx_trig_bytes,
2918 serial8250_set_attr_rx_trig_bytes);
2919
2920static struct attribute *serial8250_dev_attrs[] = {
2921 &dev_attr_rx_trig_bytes.attr,
2922 NULL,
2923 };
2924
2925static struct attribute_group serial8250_dev_attr_group = {
2926 .attrs = serial8250_dev_attrs,
2927 };
2928
2929static void register_dev_spec_attr_grp(struct uart_8250_port *up)
2930{
2931 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2932
2933 if (conf_type->rxtrig_bytes[0])
2934 up->port.attr_group = &serial8250_dev_attr_group;
2935}
2936
2937static void serial8250_config_port(struct uart_port *port, int flags)
2938{
2939 struct uart_8250_port *up = up_to_u8250p(port);
2940 int ret;
2941
b6830f6d
PH		 2942 /*
2943 * Find the region that we can probe for. This in turn
2944 * tells us whether we can probe for the type of port.
2945 */
2946 ret = serial8250_request_std_resource(up);
2947 if (ret < 0)
2948 return;
2949
2950 if (port->iotype != up->cur_iotype)
2951 set_io_from_upio(port);
2952
2953 if (flags & UART_CONFIG_TYPE)
2954 autoconfig(up);
2955
2956 /* if access method is AU, it is a 16550 with a quirk */
2957 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2958 up->bugs |= UART_BUG_NOMSR;
2959
2960 /* HW bugs may trigger IRQ while IIR == NO_INT */
2961 if (port->type == PORT_TEGRA)
2962 up->bugs |= UART_BUG_NOMSR;
2963
2964 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2965 autoconfig_irq(up);
2966
2967 if (port->type == PORT_UNKNOWN)
2968 serial8250_release_std_resource(up);
2969
2970 /* Fixme: probably not the best place for this */
2971 if ((port->type == PORT_XR17V35X) ||
2972 (port->type == PORT_XR17D15X))
2973 port->handle_irq = exar_handle_irq;
2974
2975 register_dev_spec_attr_grp(up);
2976 up->fcr = uart_config[up->port.type].fcr;
2977}
2978
2979static int
2980serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2981{
2982 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2983 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2984 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2985 ser->type == PORT_STARTECH)
2986 return -EINVAL;
2987 return 0;
2988}
2989
cee10c8c 2990static const char *serial8250_type(struct uart_port *port)
b6830f6d
PH		 2991{
2992 int type = port->type;
2993
2994 if (type >= ARRAY_SIZE(uart_config))
2995 type = 0;
2996 return uart_config[type].name;
2997}
2998
2999static const struct uart_ops serial8250_pops = {
3000 .tx_empty = serial8250_tx_empty,
3001 .set_mctrl = serial8250_set_mctrl,
3002 .get_mctrl = serial8250_get_mctrl,
3003 .stop_tx = serial8250_stop_tx,
3004 .start_tx = serial8250_start_tx,
3005 .throttle = serial8250_throttle,
3006 .unthrottle = serial8250_unthrottle,
3007 .stop_rx = serial8250_stop_rx,
3008 .enable_ms = serial8250_enable_ms,
3009 .break_ctl = serial8250_break_ctl,
3010 .startup = serial8250_startup,
3011 .shutdown = serial8250_shutdown,
3012 .set_termios = serial8250_set_termios,
3013 .set_ldisc = serial8250_set_ldisc,
3014 .pm = serial8250_pm,
3015 .type = serial8250_type,
3016 .release_port = serial8250_release_port,
3017 .request_port = serial8250_request_port,
3018 .config_port = serial8250_config_port,
3019 .verify_port = serial8250_verify_port,
3020#ifdef CONFIG_CONSOLE_POLL
3021 .poll_get_char = serial8250_get_poll_char,
3022 .poll_put_char = serial8250_put_poll_char,
3023#endif
3024};
3025
3026void serial8250_init_port(struct uart_8250_port *up)
3027{
3028 struct uart_port *port = &up->port;
3029
3030 spin_lock_init(&port->lock);
3031 port->ops = &serial8250_pops;
3032
3033 up->cur_iotype = 0xFF;
3034}
3035EXPORT_SYMBOL_GPL(serial8250_init_port);
3036
3037void serial8250_set_defaults(struct uart_8250_port *up)
3038{
3039 struct uart_port *port = &up->port;
3040
3041 if (up->port.flags & UPF_FIXED_TYPE) {
3042 unsigned int type = up->port.type;
3043
3044 if (!up->port.fifosize)
3045 up->port.fifosize = uart_config[type].fifo_size;
3046 if (!up->tx_loadsz)
3047 up->tx_loadsz = uart_config[type].tx_loadsz;
3048 if (!up->capabilities)
3049 up->capabilities = uart_config[type].flags;
3050 }
3051
3052 set_io_from_upio(port);
3053
3054 /* default dma handlers */
3055 if (up->dma) {
3056 if (!up->dma->tx_dma)
3057 up->dma->tx_dma = serial8250_tx_dma;
3058 if (!up->dma->rx_dma)
3059 up->dma->rx_dma = serial8250_rx_dma;
3060 }
3061}
3062EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3063
3064#ifdef CONFIG_SERIAL_8250_CONSOLE
3065
3066static void serial8250_console_putchar(struct uart_port *port, int ch)
3067{
3068 struct uart_8250_port *up = up_to_u8250p(port);
3069
3070 wait_for_xmitr(up, UART_LSR_THRE);
3071 serial_port_out(port, UART_TX, ch);
3072}
3073
10791233
PH		 3074/*
3075 * Restore serial console when h/w power-off detected
3076 */
3077static void serial8250_console_restore(struct uart_8250_port *up)
3078{
3079 struct uart_port *port = &up->port;
3080 struct ktermios termios;
3081 unsigned int baud, quot, frac = 0;
3082
3083 termios.c_cflag = port->cons->cflag;
3084 if (port->state->port.tty && termios.c_cflag == 0)
3085 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3086
3087 baud = serial8250_get_baud_rate(port, &termios, NULL);
3088 quot = serial8250_get_divisor(up, baud, &frac);
3089
3090 serial8250_set_divisor(port, baud, quot, frac);
3091 serial_port_out(port, UART_LCR, up->lcr);
36fd95b1 3092 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
10791233
PH		 3093}
3094
b6830f6d
PH		 3095/*
3096 * Print a string to the serial port trying not to disturb
3097 * any possible real use of the port...
3098 *
3099 * The console_lock must be held when we get here.
3100 */
3101void serial8250_console_write(struct uart_8250_port *up, const char *s,
3102 unsigned int count)
3103{
3104 struct uart_port *port = &up->port;
3105 unsigned long flags;
3106 unsigned int ier;
3107 int locked = 1;
3108
3109 touch_nmi_watchdog();
3110
3111 serial8250_rpm_get(up);
3112
3113 if (port->sysrq)
3114 locked = 0;
3115 else if (oops_in_progress)
3116 locked = spin_trylock_irqsave(&port->lock, flags);
3117 else
3118 spin_lock_irqsave(&port->lock, flags);
3119
3120 /*
3121 * First save the IER then disable the interrupts
3122 */
3123 ier = serial_port_in(port, UART_IER);
3124
3125 if (up->capabilities & UART_CAP_UUE)
3126 serial_port_out(port, UART_IER, UART_IER_UUE);
3127 else
3128 serial_port_out(port, UART_IER, 0);
3129
3130 /* check scratch reg to see if port powered off during system sleep */
3131 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
10791233 3132 serial8250_console_restore(up);
b6830f6d
PH		 3133 up->canary = 0;
3134 }
3135
3136 uart_console_write(port, s, count, serial8250_console_putchar);
3137
3138 /*
3139 * Finally, wait for transmitter to become empty
3140 * and restore the IER
3141 */
3142 wait_for_xmitr(up, BOTH_EMPTY);
3143 serial_port_out(port, UART_IER, ier);
3144
3145 /*
3146 * The receive handling will happen properly because the
3147 * receive ready bit will still be set; it is not cleared
3148 * on read. However, modem control will not, we must
3149 * call it if we have saved something in the saved flags
3150 * while processing with interrupts off.
3151 */
3152 if (up->msr_saved_flags)
3153 serial8250_modem_status(up);
3154
3155 if (locked)
3156 spin_unlock_irqrestore(&port->lock, flags);
3157 serial8250_rpm_put(up);
3158}
3159
3160static unsigned int probe_baud(struct uart_port *port)
3161{
3162 unsigned char lcr, dll, dlm;
3163 unsigned int quot;
3164
3165 lcr = serial_port_in(port, UART_LCR);
3166 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3167 dll = serial_port_in(port, UART_DLL);
3168 dlm = serial_port_in(port, UART_DLM);
3169 serial_port_out(port, UART_LCR, lcr);
3170
3171 quot = (dlm << 8) | dll;
3172 return (port->uartclk / 16) / quot;
3173}
3174
3175int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3176{
3177 int baud = 9600;
3178 int bits = 8;
3179 int parity = 'n';
3180 int flow = 'n';
3181
3182 if (!port->iobase && !port->membase)
3183 return -ENODEV;
3184
3185 if (options)
3186 uart_parse_options(options, &baud, &parity, &bits, &flow);
3187 else if (probe)
3188 baud = probe_baud(port);
3189
3190 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3191}
3192
3193#endif /* CONFIG_SERIAL_8250_CONSOLE */
f7a7651f
JM		 3194
3195MODULE_LICENSE("GPL");
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