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b6830f6d PH |
1 | /* |
2 | * Base port operations for 8250/16550-type serial ports | |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * Split from 8250_core.c, Copyright (C) 2001 Russell King. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * A note about mapbase / membase | |
13 | * | |
14 | * mapbase is the physical address of the IO port. | |
15 | * membase is an 'ioremapped' cookie. | |
16 | */ | |
17 | ||
18 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
19 | #define SUPPORT_SYSRQ | |
20 | #endif | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/moduleparam.h> | |
24 | #include <linux/ioport.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/console.h> | |
27 | #include <linux/sysrq.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/tty.h> | |
31 | #include <linux/ratelimit.h> | |
32 | #include <linux/tty_flip.h> | |
33 | #include <linux/serial.h> | |
34 | #include <linux/serial_8250.h> | |
35 | #include <linux/nmi.h> | |
36 | #include <linux/mutex.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/uaccess.h> | |
39 | #include <linux/pm_runtime.h> | |
e490c914 | 40 | #include <linux/timer.h> |
b6830f6d PH |
41 | |
42 | #include <asm/io.h> | |
43 | #include <asm/irq.h> | |
44 | ||
45 | #include "8250.h" | |
46 | ||
7e12357e JK |
47 | /* |
48 | * These are definitions for the Exar XR17V35X and XR17(C|D)15X | |
49 | */ | |
2c0ac5b4 | 50 | #define UART_EXAR_INT0 0x80 |
7e12357e JK |
51 | #define UART_EXAR_SLEEP 0x8b /* Sleep mode */ |
52 | #define UART_EXAR_DVID 0x8d /* Device identification */ | |
53 | ||
b6830f6d PH |
54 | /* |
55 | * Debugging. | |
56 | */ | |
57 | #if 0 | |
58 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) | |
59 | #else | |
60 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) | |
61 | #endif | |
62 | ||
6d7c157f | 63 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
b6830f6d PH |
64 | |
65 | /* | |
66 | * Here we define the default xmit fifo size used for each type of UART. | |
67 | */ | |
68 | static const struct serial8250_config uart_config[] = { | |
69 | [PORT_UNKNOWN] = { | |
70 | .name = "unknown", | |
71 | .fifo_size = 1, | |
72 | .tx_loadsz = 1, | |
73 | }, | |
74 | [PORT_8250] = { | |
75 | .name = "8250", | |
76 | .fifo_size = 1, | |
77 | .tx_loadsz = 1, | |
78 | }, | |
79 | [PORT_16450] = { | |
80 | .name = "16450", | |
81 | .fifo_size = 1, | |
82 | .tx_loadsz = 1, | |
83 | }, | |
84 | [PORT_16550] = { | |
85 | .name = "16550", | |
86 | .fifo_size = 1, | |
87 | .tx_loadsz = 1, | |
88 | }, | |
89 | [PORT_16550A] = { | |
90 | .name = "16550A", | |
91 | .fifo_size = 16, | |
92 | .tx_loadsz = 16, | |
ecb988a3 SS |
93 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | |
94 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, | |
b6830f6d PH |
95 | .rxtrig_bytes = {1, 4, 8, 14}, |
96 | .flags = UART_CAP_FIFO, | |
97 | }, | |
98 | [PORT_CIRRUS] = { | |
99 | .name = "Cirrus", | |
100 | .fifo_size = 1, | |
101 | .tx_loadsz = 1, | |
102 | }, | |
103 | [PORT_16650] = { | |
104 | .name = "ST16650", | |
105 | .fifo_size = 1, | |
106 | .tx_loadsz = 1, | |
107 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
108 | }, | |
109 | [PORT_16650V2] = { | |
110 | .name = "ST16650V2", | |
111 | .fifo_size = 32, | |
112 | .tx_loadsz = 16, | |
113 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
114 | UART_FCR_T_TRIG_00, | |
115 | .rxtrig_bytes = {8, 16, 24, 28}, | |
116 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
117 | }, | |
118 | [PORT_16750] = { | |
119 | .name = "TI16750", | |
120 | .fifo_size = 64, | |
121 | .tx_loadsz = 64, | |
122 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | | |
123 | UART_FCR7_64BYTE, | |
124 | .rxtrig_bytes = {1, 16, 32, 56}, | |
125 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, | |
126 | }, | |
127 | [PORT_STARTECH] = { | |
128 | .name = "Startech", | |
129 | .fifo_size = 1, | |
130 | .tx_loadsz = 1, | |
131 | }, | |
132 | [PORT_16C950] = { | |
133 | .name = "16C950/954", | |
134 | .fifo_size = 128, | |
135 | .tx_loadsz = 128, | |
136 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
137 | /* UART_CAP_EFR breaks billionon CF bluetooth card. */ | |
138 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP, | |
139 | }, | |
140 | [PORT_16654] = { | |
141 | .name = "ST16654", | |
142 | .fifo_size = 64, | |
143 | .tx_loadsz = 32, | |
144 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
145 | UART_FCR_T_TRIG_10, | |
146 | .rxtrig_bytes = {8, 16, 56, 60}, | |
147 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
148 | }, | |
149 | [PORT_16850] = { | |
150 | .name = "XR16850", | |
151 | .fifo_size = 128, | |
152 | .tx_loadsz = 128, | |
153 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
154 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
155 | }, | |
156 | [PORT_RSA] = { | |
157 | .name = "RSA", | |
158 | .fifo_size = 2048, | |
159 | .tx_loadsz = 2048, | |
160 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, | |
161 | .flags = UART_CAP_FIFO, | |
162 | }, | |
163 | [PORT_NS16550A] = { | |
164 | .name = "NS16550A", | |
165 | .fifo_size = 16, | |
166 | .tx_loadsz = 16, | |
167 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
168 | .flags = UART_CAP_FIFO | UART_NATSEMI, | |
169 | }, | |
170 | [PORT_XSCALE] = { | |
171 | .name = "XScale", | |
172 | .fifo_size = 32, | |
173 | .tx_loadsz = 32, | |
174 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
175 | .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE, | |
176 | }, | |
177 | [PORT_OCTEON] = { | |
178 | .name = "OCTEON", | |
179 | .fifo_size = 64, | |
180 | .tx_loadsz = 64, | |
181 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
182 | .flags = UART_CAP_FIFO, | |
183 | }, | |
184 | [PORT_AR7] = { | |
185 | .name = "AR7", | |
186 | .fifo_size = 16, | |
187 | .tx_loadsz = 16, | |
188 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, | |
68af490b | 189 | .flags = UART_CAP_FIFO /* | UART_CAP_AFE */, |
b6830f6d PH |
190 | }, |
191 | [PORT_U6_16550A] = { | |
192 | .name = "U6_16550A", | |
193 | .fifo_size = 64, | |
194 | .tx_loadsz = 64, | |
195 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
196 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
197 | }, | |
198 | [PORT_TEGRA] = { | |
199 | .name = "Tegra", | |
200 | .fifo_size = 32, | |
201 | .tx_loadsz = 8, | |
202 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
203 | UART_FCR_T_TRIG_01, | |
204 | .rxtrig_bytes = {1, 4, 8, 14}, | |
205 | .flags = UART_CAP_FIFO | UART_CAP_RTOIE, | |
206 | }, | |
207 | [PORT_XR17D15X] = { | |
208 | .name = "XR17D15X", | |
209 | .fifo_size = 64, | |
210 | .tx_loadsz = 64, | |
211 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
212 | .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | | |
213 | UART_CAP_SLEEP, | |
214 | }, | |
215 | [PORT_XR17V35X] = { | |
216 | .name = "XR17V35X", | |
217 | .fifo_size = 256, | |
218 | .tx_loadsz = 256, | |
219 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 | | |
220 | UART_FCR_T_TRIG_11, | |
221 | .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | | |
222 | UART_CAP_SLEEP, | |
223 | }, | |
224 | [PORT_LPC3220] = { | |
225 | .name = "LPC3220", | |
226 | .fifo_size = 64, | |
227 | .tx_loadsz = 32, | |
228 | .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO | | |
229 | UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00, | |
230 | .flags = UART_CAP_FIFO, | |
231 | }, | |
232 | [PORT_BRCM_TRUMANAGE] = { | |
233 | .name = "TruManage", | |
234 | .fifo_size = 1, | |
235 | .tx_loadsz = 1024, | |
236 | .flags = UART_CAP_HFIFO, | |
237 | }, | |
238 | [PORT_8250_CIR] = { | |
239 | .name = "CIR port" | |
240 | }, | |
241 | [PORT_ALTR_16550_F32] = { | |
242 | .name = "Altera 16550 FIFO32", | |
243 | .fifo_size = 32, | |
244 | .tx_loadsz = 32, | |
245 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
246 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
247 | }, | |
248 | [PORT_ALTR_16550_F64] = { | |
249 | .name = "Altera 16550 FIFO64", | |
250 | .fifo_size = 64, | |
251 | .tx_loadsz = 64, | |
252 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
253 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
254 | }, | |
255 | [PORT_ALTR_16550_F128] = { | |
256 | .name = "Altera 16550 FIFO128", | |
257 | .fifo_size = 128, | |
258 | .tx_loadsz = 128, | |
259 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
260 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
261 | }, | |
740dc2de AW |
262 | /* |
263 | * tx_loadsz is set to 63-bytes instead of 64-bytes to implement | |
264 | * workaround of errata A-008006 which states that tx_loadsz should | |
265 | * be configured less than Maximum supported fifo bytes. | |
266 | */ | |
b6830f6d PH |
267 | [PORT_16550A_FSL64] = { |
268 | .name = "16550A_FSL64", | |
269 | .fifo_size = 64, | |
270 | .tx_loadsz = 63, | |
271 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | | |
272 | UART_FCR7_64BYTE, | |
273 | .flags = UART_CAP_FIFO, | |
274 | }, | |
3c5a0357 MR |
275 | [PORT_RT2880] = { |
276 | .name = "Palmchip BK-3103", | |
277 | .fifo_size = 16, | |
278 | .tx_loadsz = 16, | |
279 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
280 | .rxtrig_bytes = {1, 4, 8, 14}, | |
281 | .flags = UART_CAP_FIFO, | |
282 | }, | |
a2d6a987 DL |
283 | [PORT_DA830] = { |
284 | .name = "TI DA8xx/66AK2x", | |
285 | .fifo_size = 16, | |
286 | .tx_loadsz = 16, | |
287 | .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO | | |
288 | UART_FCR_R_TRIG_10, | |
289 | .rxtrig_bytes = {1, 4, 8, 14}, | |
290 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
291 | }, | |
b6830f6d PH |
292 | }; |
293 | ||
294 | /* Uart divisor latch read */ | |
295 | static int default_serial_dl_read(struct uart_8250_port *up) | |
296 | { | |
297 | return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8; | |
298 | } | |
299 | ||
300 | /* Uart divisor latch write */ | |
301 | static void default_serial_dl_write(struct uart_8250_port *up, int value) | |
302 | { | |
303 | serial_out(up, UART_DLL, value & 0xff); | |
304 | serial_out(up, UART_DLM, value >> 8 & 0xff); | |
305 | } | |
306 | ||
9b2256c8 | 307 | #ifdef CONFIG_SERIAL_8250_RT288X |
b6830f6d PH |
308 | |
309 | /* Au1x00/RT288x UART hardware has a weird register layout */ | |
310 | static const s8 au_io_in_map[8] = { | |
311 | 0, /* UART_RX */ | |
312 | 2, /* UART_IER */ | |
313 | 3, /* UART_IIR */ | |
314 | 5, /* UART_LCR */ | |
315 | 6, /* UART_MCR */ | |
316 | 7, /* UART_LSR */ | |
317 | 8, /* UART_MSR */ | |
318 | -1, /* UART_SCR (unmapped) */ | |
319 | }; | |
320 | ||
321 | static const s8 au_io_out_map[8] = { | |
322 | 1, /* UART_TX */ | |
323 | 2, /* UART_IER */ | |
324 | 4, /* UART_FCR */ | |
325 | 5, /* UART_LCR */ | |
326 | 6, /* UART_MCR */ | |
327 | -1, /* UART_LSR (unmapped) */ | |
328 | -1, /* UART_MSR (unmapped) */ | |
329 | -1, /* UART_SCR (unmapped) */ | |
330 | }; | |
331 | ||
72f1b85a | 332 | unsigned int au_serial_in(struct uart_port *p, int offset) |
b6830f6d PH |
333 | { |
334 | if (offset >= ARRAY_SIZE(au_io_in_map)) | |
335 | return UINT_MAX; | |
336 | offset = au_io_in_map[offset]; | |
337 | if (offset < 0) | |
338 | return UINT_MAX; | |
339 | return __raw_readl(p->membase + (offset << p->regshift)); | |
340 | } | |
341 | ||
72f1b85a | 342 | void au_serial_out(struct uart_port *p, int offset, int value) |
b6830f6d PH |
343 | { |
344 | if (offset >= ARRAY_SIZE(au_io_out_map)) | |
345 | return; | |
346 | offset = au_io_out_map[offset]; | |
347 | if (offset < 0) | |
348 | return; | |
349 | __raw_writel(value, p->membase + (offset << p->regshift)); | |
350 | } | |
351 | ||
352 | /* Au1x00 haven't got a standard divisor latch */ | |
353 | static int au_serial_dl_read(struct uart_8250_port *up) | |
354 | { | |
355 | return __raw_readl(up->port.membase + 0x28); | |
356 | } | |
357 | ||
358 | static void au_serial_dl_write(struct uart_8250_port *up, int value) | |
359 | { | |
360 | __raw_writel(value, up->port.membase + 0x28); | |
361 | } | |
362 | ||
363 | #endif | |
364 | ||
365 | static unsigned int hub6_serial_in(struct uart_port *p, int offset) | |
366 | { | |
367 | offset = offset << p->regshift; | |
368 | outb(p->hub6 - 1 + offset, p->iobase); | |
369 | return inb(p->iobase + 1); | |
370 | } | |
371 | ||
372 | static void hub6_serial_out(struct uart_port *p, int offset, int value) | |
373 | { | |
374 | offset = offset << p->regshift; | |
375 | outb(p->hub6 - 1 + offset, p->iobase); | |
376 | outb(value, p->iobase + 1); | |
377 | } | |
378 | ||
379 | static unsigned int mem_serial_in(struct uart_port *p, int offset) | |
380 | { | |
381 | offset = offset << p->regshift; | |
382 | return readb(p->membase + offset); | |
383 | } | |
384 | ||
385 | static void mem_serial_out(struct uart_port *p, int offset, int value) | |
386 | { | |
387 | offset = offset << p->regshift; | |
388 | writeb(value, p->membase + offset); | |
389 | } | |
390 | ||
bd94c407 MY |
391 | static void mem16_serial_out(struct uart_port *p, int offset, int value) |
392 | { | |
393 | offset = offset << p->regshift; | |
394 | writew(value, p->membase + offset); | |
395 | } | |
396 | ||
397 | static unsigned int mem16_serial_in(struct uart_port *p, int offset) | |
398 | { | |
399 | offset = offset << p->regshift; | |
400 | return readw(p->membase + offset); | |
401 | } | |
402 | ||
b6830f6d PH |
403 | static void mem32_serial_out(struct uart_port *p, int offset, int value) |
404 | { | |
405 | offset = offset << p->regshift; | |
406 | writel(value, p->membase + offset); | |
407 | } | |
408 | ||
409 | static unsigned int mem32_serial_in(struct uart_port *p, int offset) | |
410 | { | |
411 | offset = offset << p->regshift; | |
412 | return readl(p->membase + offset); | |
413 | } | |
414 | ||
415 | static void mem32be_serial_out(struct uart_port *p, int offset, int value) | |
416 | { | |
417 | offset = offset << p->regshift; | |
418 | iowrite32be(value, p->membase + offset); | |
419 | } | |
420 | ||
421 | static unsigned int mem32be_serial_in(struct uart_port *p, int offset) | |
422 | { | |
423 | offset = offset << p->regshift; | |
424 | return ioread32be(p->membase + offset); | |
425 | } | |
426 | ||
427 | static unsigned int io_serial_in(struct uart_port *p, int offset) | |
428 | { | |
429 | offset = offset << p->regshift; | |
430 | return inb(p->iobase + offset); | |
431 | } | |
432 | ||
433 | static void io_serial_out(struct uart_port *p, int offset, int value) | |
434 | { | |
435 | offset = offset << p->regshift; | |
436 | outb(value, p->iobase + offset); | |
437 | } | |
438 | ||
439 | static int serial8250_default_handle_irq(struct uart_port *port); | |
440 | static int exar_handle_irq(struct uart_port *port); | |
441 | ||
442 | static void set_io_from_upio(struct uart_port *p) | |
443 | { | |
444 | struct uart_8250_port *up = up_to_u8250p(p); | |
445 | ||
446 | up->dl_read = default_serial_dl_read; | |
447 | up->dl_write = default_serial_dl_write; | |
448 | ||
449 | switch (p->iotype) { | |
450 | case UPIO_HUB6: | |
451 | p->serial_in = hub6_serial_in; | |
452 | p->serial_out = hub6_serial_out; | |
453 | break; | |
454 | ||
455 | case UPIO_MEM: | |
456 | p->serial_in = mem_serial_in; | |
457 | p->serial_out = mem_serial_out; | |
458 | break; | |
459 | ||
bd94c407 MY |
460 | case UPIO_MEM16: |
461 | p->serial_in = mem16_serial_in; | |
462 | p->serial_out = mem16_serial_out; | |
463 | break; | |
464 | ||
b6830f6d PH |
465 | case UPIO_MEM32: |
466 | p->serial_in = mem32_serial_in; | |
467 | p->serial_out = mem32_serial_out; | |
468 | break; | |
469 | ||
470 | case UPIO_MEM32BE: | |
471 | p->serial_in = mem32be_serial_in; | |
472 | p->serial_out = mem32be_serial_out; | |
473 | break; | |
474 | ||
9b2256c8 | 475 | #ifdef CONFIG_SERIAL_8250_RT288X |
b6830f6d PH |
476 | case UPIO_AU: |
477 | p->serial_in = au_serial_in; | |
478 | p->serial_out = au_serial_out; | |
479 | up->dl_read = au_serial_dl_read; | |
480 | up->dl_write = au_serial_dl_write; | |
481 | break; | |
482 | #endif | |
483 | ||
484 | default: | |
485 | p->serial_in = io_serial_in; | |
486 | p->serial_out = io_serial_out; | |
487 | break; | |
488 | } | |
489 | /* Remember loaded iotype */ | |
490 | up->cur_iotype = p->iotype; | |
491 | p->handle_irq = serial8250_default_handle_irq; | |
492 | } | |
493 | ||
494 | static void | |
495 | serial_port_out_sync(struct uart_port *p, int offset, int value) | |
496 | { | |
497 | switch (p->iotype) { | |
498 | case UPIO_MEM: | |
bd94c407 | 499 | case UPIO_MEM16: |
b6830f6d PH |
500 | case UPIO_MEM32: |
501 | case UPIO_MEM32BE: | |
502 | case UPIO_AU: | |
503 | p->serial_out(p, offset, value); | |
504 | p->serial_in(p, UART_LCR); /* safe, no side-effects */ | |
505 | break; | |
506 | default: | |
507 | p->serial_out(p, offset, value); | |
508 | } | |
509 | } | |
510 | ||
511 | /* | |
512 | * For the 16C950 | |
513 | */ | |
514 | static void serial_icr_write(struct uart_8250_port *up, int offset, int value) | |
515 | { | |
516 | serial_out(up, UART_SCR, offset); | |
517 | serial_out(up, UART_ICR, value); | |
518 | } | |
519 | ||
520 | static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) | |
521 | { | |
522 | unsigned int value; | |
523 | ||
524 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); | |
525 | serial_out(up, UART_SCR, offset); | |
526 | value = serial_in(up, UART_ICR); | |
527 | serial_icr_write(up, UART_ACR, up->acr); | |
528 | ||
529 | return value; | |
530 | } | |
531 | ||
532 | /* | |
533 | * FIFO support. | |
534 | */ | |
535 | static void serial8250_clear_fifos(struct uart_8250_port *p) | |
536 | { | |
537 | if (p->capabilities & UART_CAP_FIFO) { | |
538 | serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO); | |
539 | serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO | | |
540 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
541 | serial_out(p, UART_FCR, 0); | |
542 | } | |
543 | } | |
544 | ||
e490c914 MK |
545 | static inline void serial8250_em485_rts_after_send(struct uart_8250_port *p) |
546 | { | |
36fd95b1 | 547 | unsigned char mcr = serial8250_in_MCR(p); |
e490c914 MK |
548 | |
549 | if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND) | |
550 | mcr |= UART_MCR_RTS; | |
551 | else | |
552 | mcr &= ~UART_MCR_RTS; | |
36fd95b1 | 553 | serial8250_out_MCR(p, mcr); |
e490c914 MK |
554 | } |
555 | ||
556 | static void serial8250_em485_handle_start_tx(unsigned long arg); | |
557 | static void serial8250_em485_handle_stop_tx(unsigned long arg); | |
558 | ||
b6830f6d PH |
559 | void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p) |
560 | { | |
561 | serial8250_clear_fifos(p); | |
562 | serial_out(p, UART_FCR, p->fcr); | |
563 | } | |
564 | EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos); | |
565 | ||
566 | void serial8250_rpm_get(struct uart_8250_port *p) | |
567 | { | |
568 | if (!(p->capabilities & UART_CAP_RPM)) | |
569 | return; | |
570 | pm_runtime_get_sync(p->port.dev); | |
571 | } | |
572 | EXPORT_SYMBOL_GPL(serial8250_rpm_get); | |
573 | ||
574 | void serial8250_rpm_put(struct uart_8250_port *p) | |
575 | { | |
576 | if (!(p->capabilities & UART_CAP_RPM)) | |
577 | return; | |
578 | pm_runtime_mark_last_busy(p->port.dev); | |
579 | pm_runtime_put_autosuspend(p->port.dev); | |
580 | } | |
581 | EXPORT_SYMBOL_GPL(serial8250_rpm_put); | |
582 | ||
e490c914 MK |
583 | /** |
584 | * serial8250_em485_init() - put uart_8250_port into rs485 emulating | |
585 | * @p: uart_8250_port port instance | |
586 | * | |
587 | * The function is used to start rs485 software emulating on the | |
588 | * &struct uart_8250_port* @p. Namely, RTS is switched before/after | |
589 | * transmission. The function is idempotent, so it is safe to call it | |
590 | * multiple times. | |
591 | * | |
592 | * The caller MUST enable interrupt on empty shift register before | |
593 | * calling serial8250_em485_init(). This interrupt is not a part of | |
594 | * 8250 standard, but implementation defined. | |
595 | * | |
596 | * The function is supposed to be called from .rs485_config callback | |
597 | * or from any other callback protected with p->port.lock spinlock. | |
598 | * | |
599 | * See also serial8250_em485_destroy() | |
600 | * | |
601 | * Return 0 - success, -errno - otherwise | |
602 | */ | |
603 | int serial8250_em485_init(struct uart_8250_port *p) | |
604 | { | |
f3bf2632 | 605 | if (p->em485) |
e490c914 MK |
606 | return 0; |
607 | ||
b18a183e | 608 | p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC); |
f3bf2632 | 609 | if (!p->em485) |
e490c914 MK |
610 | return -ENOMEM; |
611 | ||
612 | setup_timer(&p->em485->stop_tx_timer, | |
613 | serial8250_em485_handle_stop_tx, (unsigned long)p); | |
614 | setup_timer(&p->em485->start_tx_timer, | |
615 | serial8250_em485_handle_start_tx, (unsigned long)p); | |
616 | p->em485->active_timer = NULL; | |
617 | ||
618 | serial8250_em485_rts_after_send(p); | |
619 | ||
620 | return 0; | |
621 | } | |
622 | EXPORT_SYMBOL_GPL(serial8250_em485_init); | |
623 | ||
624 | /** | |
625 | * serial8250_em485_destroy() - put uart_8250_port into normal state | |
626 | * @p: uart_8250_port port instance | |
627 | * | |
628 | * The function is used to stop rs485 software emulating on the | |
629 | * &struct uart_8250_port* @p. The function is idempotent, so it is safe to | |
630 | * call it multiple times. | |
631 | * | |
632 | * The function is supposed to be called from .rs485_config callback | |
633 | * or from any other callback protected with p->port.lock spinlock. | |
634 | * | |
635 | * See also serial8250_em485_init() | |
636 | */ | |
637 | void serial8250_em485_destroy(struct uart_8250_port *p) | |
638 | { | |
f3bf2632 | 639 | if (!p->em485) |
e490c914 MK |
640 | return; |
641 | ||
642 | del_timer(&p->em485->start_tx_timer); | |
643 | del_timer(&p->em485->stop_tx_timer); | |
644 | ||
645 | kfree(p->em485); | |
646 | p->em485 = NULL; | |
647 | } | |
648 | EXPORT_SYMBOL_GPL(serial8250_em485_destroy); | |
649 | ||
b6830f6d PH |
650 | /* |
651 | * These two wrappers ensure that enable_runtime_pm_tx() can be called more than | |
652 | * once and disable_runtime_pm_tx() will still disable RPM because the fifo is | |
653 | * empty and the HW can idle again. | |
654 | */ | |
7d4e00c6 | 655 | void serial8250_rpm_get_tx(struct uart_8250_port *p) |
b6830f6d PH |
656 | { |
657 | unsigned char rpm_active; | |
658 | ||
659 | if (!(p->capabilities & UART_CAP_RPM)) | |
660 | return; | |
661 | ||
662 | rpm_active = xchg(&p->rpm_tx_active, 1); | |
663 | if (rpm_active) | |
664 | return; | |
665 | pm_runtime_get_sync(p->port.dev); | |
666 | } | |
7d4e00c6 | 667 | EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx); |
b6830f6d | 668 | |
7d4e00c6 | 669 | void serial8250_rpm_put_tx(struct uart_8250_port *p) |
b6830f6d PH |
670 | { |
671 | unsigned char rpm_active; | |
672 | ||
673 | if (!(p->capabilities & UART_CAP_RPM)) | |
674 | return; | |
675 | ||
676 | rpm_active = xchg(&p->rpm_tx_active, 0); | |
677 | if (!rpm_active) | |
678 | return; | |
679 | pm_runtime_mark_last_busy(p->port.dev); | |
680 | pm_runtime_put_autosuspend(p->port.dev); | |
681 | } | |
7d4e00c6 | 682 | EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx); |
b6830f6d PH |
683 | |
684 | /* | |
685 | * IER sleep support. UARTs which have EFRs need the "extended | |
686 | * capability" bit enabled. Note that on XR16C850s, we need to | |
687 | * reset LCR to write to IER. | |
688 | */ | |
689 | static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) | |
690 | { | |
691 | unsigned char lcr = 0, efr = 0; | |
692 | /* | |
693 | * Exar UARTs have a SLEEP register that enables or disables | |
694 | * each UART to enter sleep mode separately. On the XR17V35x the | |
695 | * register is accessible to each UART at the UART_EXAR_SLEEP | |
696 | * offset but the UART channel may only write to the corresponding | |
697 | * bit. | |
698 | */ | |
699 | serial8250_rpm_get(p); | |
700 | if ((p->port.type == PORT_XR17V35X) || | |
701 | (p->port.type == PORT_XR17D15X)) { | |
702 | serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0); | |
703 | goto out; | |
704 | } | |
705 | ||
706 | if (p->capabilities & UART_CAP_SLEEP) { | |
707 | if (p->capabilities & UART_CAP_EFR) { | |
708 | lcr = serial_in(p, UART_LCR); | |
709 | efr = serial_in(p, UART_EFR); | |
710 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); | |
711 | serial_out(p, UART_EFR, UART_EFR_ECB); | |
712 | serial_out(p, UART_LCR, 0); | |
713 | } | |
714 | serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); | |
715 | if (p->capabilities & UART_CAP_EFR) { | |
716 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); | |
717 | serial_out(p, UART_EFR, efr); | |
718 | serial_out(p, UART_LCR, lcr); | |
719 | } | |
720 | } | |
721 | out: | |
722 | serial8250_rpm_put(p); | |
723 | } | |
724 | ||
725 | #ifdef CONFIG_SERIAL_8250_RSA | |
726 | /* | |
727 | * Attempts to turn on the RSA FIFO. Returns zero on failure. | |
728 | * We set the port uart clock rate if we succeed. | |
729 | */ | |
730 | static int __enable_rsa(struct uart_8250_port *up) | |
731 | { | |
732 | unsigned char mode; | |
733 | int result; | |
734 | ||
735 | mode = serial_in(up, UART_RSA_MSR); | |
736 | result = mode & UART_RSA_MSR_FIFO; | |
737 | ||
738 | if (!result) { | |
739 | serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); | |
740 | mode = serial_in(up, UART_RSA_MSR); | |
741 | result = mode & UART_RSA_MSR_FIFO; | |
742 | } | |
743 | ||
744 | if (result) | |
745 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; | |
746 | ||
747 | return result; | |
748 | } | |
749 | ||
750 | static void enable_rsa(struct uart_8250_port *up) | |
751 | { | |
752 | if (up->port.type == PORT_RSA) { | |
753 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { | |
754 | spin_lock_irq(&up->port.lock); | |
755 | __enable_rsa(up); | |
756 | spin_unlock_irq(&up->port.lock); | |
757 | } | |
758 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) | |
759 | serial_out(up, UART_RSA_FRR, 0); | |
760 | } | |
761 | } | |
762 | ||
763 | /* | |
764 | * Attempts to turn off the RSA FIFO. Returns zero on failure. | |
765 | * It is unknown why interrupts were disabled in here. However, | |
766 | * the caller is expected to preserve this behaviour by grabbing | |
767 | * the spinlock before calling this function. | |
768 | */ | |
769 | static void disable_rsa(struct uart_8250_port *up) | |
770 | { | |
771 | unsigned char mode; | |
772 | int result; | |
773 | ||
774 | if (up->port.type == PORT_RSA && | |
775 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { | |
776 | spin_lock_irq(&up->port.lock); | |
777 | ||
778 | mode = serial_in(up, UART_RSA_MSR); | |
779 | result = !(mode & UART_RSA_MSR_FIFO); | |
780 | ||
781 | if (!result) { | |
782 | serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); | |
783 | mode = serial_in(up, UART_RSA_MSR); | |
784 | result = !(mode & UART_RSA_MSR_FIFO); | |
785 | } | |
786 | ||
787 | if (result) | |
788 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; | |
789 | spin_unlock_irq(&up->port.lock); | |
790 | } | |
791 | } | |
792 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
793 | ||
794 | /* | |
795 | * This is a quickie test to see how big the FIFO is. | |
796 | * It doesn't work at all the time, more's the pity. | |
797 | */ | |
798 | static int size_fifo(struct uart_8250_port *up) | |
799 | { | |
800 | unsigned char old_fcr, old_mcr, old_lcr; | |
801 | unsigned short old_dl; | |
802 | int count; | |
803 | ||
804 | old_lcr = serial_in(up, UART_LCR); | |
805 | serial_out(up, UART_LCR, 0); | |
806 | old_fcr = serial_in(up, UART_FCR); | |
36fd95b1 | 807 | old_mcr = serial8250_in_MCR(up); |
b6830f6d PH |
808 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | |
809 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
36fd95b1 | 810 | serial8250_out_MCR(up, UART_MCR_LOOP); |
b6830f6d PH |
811 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
812 | old_dl = serial_dl_read(up); | |
813 | serial_dl_write(up, 0x0001); | |
814 | serial_out(up, UART_LCR, 0x03); | |
815 | for (count = 0; count < 256; count++) | |
816 | serial_out(up, UART_TX, count); | |
817 | mdelay(20);/* FIXME - schedule_timeout */ | |
818 | for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) && | |
819 | (count < 256); count++) | |
820 | serial_in(up, UART_RX); | |
821 | serial_out(up, UART_FCR, old_fcr); | |
36fd95b1 | 822 | serial8250_out_MCR(up, old_mcr); |
b6830f6d PH |
823 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
824 | serial_dl_write(up, old_dl); | |
825 | serial_out(up, UART_LCR, old_lcr); | |
826 | ||
827 | return count; | |
828 | } | |
829 | ||
830 | /* | |
831 | * Read UART ID using the divisor method - set DLL and DLM to zero | |
832 | * and the revision will be in DLL and device type in DLM. We | |
833 | * preserve the device state across this. | |
834 | */ | |
835 | static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) | |
836 | { | |
0b41ce99 SF |
837 | unsigned char old_lcr; |
838 | unsigned int id, old_dl; | |
b6830f6d PH |
839 | |
840 | old_lcr = serial_in(p, UART_LCR); | |
841 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A); | |
0b41ce99 SF |
842 | old_dl = serial_dl_read(p); |
843 | serial_dl_write(p, 0); | |
844 | id = serial_dl_read(p); | |
845 | serial_dl_write(p, old_dl); | |
b6830f6d | 846 | |
b6830f6d PH |
847 | serial_out(p, UART_LCR, old_lcr); |
848 | ||
849 | return id; | |
850 | } | |
851 | ||
852 | /* | |
853 | * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. | |
854 | * When this function is called we know it is at least a StarTech | |
855 | * 16650 V2, but it might be one of several StarTech UARTs, or one of | |
856 | * its clones. (We treat the broken original StarTech 16650 V1 as a | |
857 | * 16550, and why not? Startech doesn't seem to even acknowledge its | |
858 | * existence.) | |
859 | * | |
860 | * What evil have men's minds wrought... | |
861 | */ | |
862 | static void autoconfig_has_efr(struct uart_8250_port *up) | |
863 | { | |
864 | unsigned int id1, id2, id3, rev; | |
865 | ||
866 | /* | |
867 | * Everything with an EFR has SLEEP | |
868 | */ | |
869 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
870 | ||
871 | /* | |
872 | * First we check to see if it's an Oxford Semiconductor UART. | |
873 | * | |
874 | * If we have to do this here because some non-National | |
875 | * Semiconductor clone chips lock up if you try writing to the | |
876 | * LSR register (which serial_icr_read does) | |
877 | */ | |
878 | ||
879 | /* | |
880 | * Check for Oxford Semiconductor 16C950. | |
881 | * | |
882 | * EFR [4] must be set else this test fails. | |
883 | * | |
884 | * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) | |
885 | * claims that it's needed for 952 dual UART's (which are not | |
886 | * recommended for new designs). | |
887 | */ | |
888 | up->acr = 0; | |
889 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
890 | serial_out(up, UART_EFR, UART_EFR_ECB); | |
891 | serial_out(up, UART_LCR, 0x00); | |
892 | id1 = serial_icr_read(up, UART_ID1); | |
893 | id2 = serial_icr_read(up, UART_ID2); | |
894 | id3 = serial_icr_read(up, UART_ID3); | |
895 | rev = serial_icr_read(up, UART_REV); | |
896 | ||
897 | DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); | |
898 | ||
899 | if (id1 == 0x16 && id2 == 0xC9 && | |
900 | (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { | |
901 | up->port.type = PORT_16C950; | |
902 | ||
903 | /* | |
904 | * Enable work around for the Oxford Semiconductor 952 rev B | |
905 | * chip which causes it to seriously miscalculate baud rates | |
906 | * when DLL is 0. | |
907 | */ | |
908 | if (id3 == 0x52 && rev == 0x01) | |
909 | up->bugs |= UART_BUG_QUOT; | |
910 | return; | |
911 | } | |
912 | ||
913 | /* | |
914 | * We check for a XR16C850 by setting DLL and DLM to 0, and then | |
915 | * reading back DLL and DLM. The chip type depends on the DLM | |
916 | * value read back: | |
917 | * 0x10 - XR16C850 and the DLL contains the chip revision. | |
918 | * 0x12 - XR16C2850. | |
919 | * 0x14 - XR16C854. | |
920 | */ | |
921 | id1 = autoconfig_read_divisor_id(up); | |
922 | DEBUG_AUTOCONF("850id=%04x ", id1); | |
923 | ||
924 | id2 = id1 >> 8; | |
925 | if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { | |
926 | up->port.type = PORT_16850; | |
927 | return; | |
928 | } | |
929 | ||
930 | /* | |
931 | * It wasn't an XR16C850. | |
932 | * | |
933 | * We distinguish between the '654 and the '650 by counting | |
934 | * how many bytes are in the FIFO. I'm using this for now, | |
935 | * since that's the technique that was sent to me in the | |
936 | * serial driver update, but I'm not convinced this works. | |
937 | * I've had problems doing this in the past. -TYT | |
938 | */ | |
939 | if (size_fifo(up) == 64) | |
940 | up->port.type = PORT_16654; | |
941 | else | |
942 | up->port.type = PORT_16650V2; | |
943 | } | |
944 | ||
945 | /* | |
946 | * We detected a chip without a FIFO. Only two fall into | |
947 | * this category - the original 8250 and the 16450. The | |
948 | * 16450 has a scratch register (accessible with LCR=0) | |
949 | */ | |
950 | static void autoconfig_8250(struct uart_8250_port *up) | |
951 | { | |
952 | unsigned char scratch, status1, status2; | |
953 | ||
954 | up->port.type = PORT_8250; | |
955 | ||
956 | scratch = serial_in(up, UART_SCR); | |
957 | serial_out(up, UART_SCR, 0xa5); | |
958 | status1 = serial_in(up, UART_SCR); | |
959 | serial_out(up, UART_SCR, 0x5a); | |
960 | status2 = serial_in(up, UART_SCR); | |
961 | serial_out(up, UART_SCR, scratch); | |
962 | ||
963 | if (status1 == 0xa5 && status2 == 0x5a) | |
964 | up->port.type = PORT_16450; | |
965 | } | |
966 | ||
967 | static int broken_efr(struct uart_8250_port *up) | |
968 | { | |
969 | /* | |
970 | * Exar ST16C2550 "A2" devices incorrectly detect as | |
971 | * having an EFR, and report an ID of 0x0201. See | |
972 | * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html | |
973 | */ | |
974 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) | |
975 | return 1; | |
976 | ||
977 | return 0; | |
978 | } | |
979 | ||
980 | /* | |
981 | * We know that the chip has FIFOs. Does it have an EFR? The | |
982 | * EFR is located in the same register position as the IIR and | |
983 | * we know the top two bits of the IIR are currently set. The | |
984 | * EFR should contain zero. Try to read the EFR. | |
985 | */ | |
986 | static void autoconfig_16550a(struct uart_8250_port *up) | |
987 | { | |
988 | unsigned char status1, status2; | |
989 | unsigned int iersave; | |
990 | ||
991 | up->port.type = PORT_16550A; | |
992 | up->capabilities |= UART_CAP_FIFO; | |
993 | ||
994 | /* | |
995 | * XR17V35x UARTs have an extra divisor register, DLD | |
996 | * that gets enabled with when DLAB is set which will | |
997 | * cause the device to incorrectly match and assign | |
998 | * port type to PORT_16650. The EFR for this UART is | |
999 | * found at offset 0x09. Instead check the Deice ID (DVID) | |
1000 | * register for a 2, 4 or 8 port UART. | |
1001 | */ | |
1002 | if (up->port.flags & UPF_EXAR_EFR) { | |
1003 | status1 = serial_in(up, UART_EXAR_DVID); | |
1004 | if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) { | |
1005 | DEBUG_AUTOCONF("Exar XR17V35x "); | |
1006 | up->port.type = PORT_XR17V35X; | |
1007 | up->capabilities |= UART_CAP_AFE | UART_CAP_EFR | | |
1008 | UART_CAP_SLEEP; | |
1009 | ||
1010 | return; | |
1011 | } | |
1012 | ||
1013 | } | |
1014 | ||
1015 | /* | |
1016 | * Check for presence of the EFR when DLAB is set. | |
1017 | * Only ST16C650V1 UARTs pass this test. | |
1018 | */ | |
1019 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
1020 | if (serial_in(up, UART_EFR) == 0) { | |
1021 | serial_out(up, UART_EFR, 0xA8); | |
1022 | if (serial_in(up, UART_EFR) != 0) { | |
1023 | DEBUG_AUTOCONF("EFRv1 "); | |
1024 | up->port.type = PORT_16650; | |
1025 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
1026 | } else { | |
1027 | serial_out(up, UART_LCR, 0); | |
1028 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
1029 | UART_FCR7_64BYTE); | |
1030 | status1 = serial_in(up, UART_IIR) >> 5; | |
1031 | serial_out(up, UART_FCR, 0); | |
1032 | serial_out(up, UART_LCR, 0); | |
1033 | ||
1034 | if (status1 == 7) | |
1035 | up->port.type = PORT_16550A_FSL64; | |
1036 | else | |
1037 | DEBUG_AUTOCONF("Motorola 8xxx DUART "); | |
1038 | } | |
1039 | serial_out(up, UART_EFR, 0); | |
1040 | return; | |
1041 | } | |
1042 | ||
1043 | /* | |
1044 | * Maybe it requires 0xbf to be written to the LCR. | |
1045 | * (other ST16C650V2 UARTs, TI16C752A, etc) | |
1046 | */ | |
1047 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
1048 | if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { | |
1049 | DEBUG_AUTOCONF("EFRv2 "); | |
1050 | autoconfig_has_efr(up); | |
1051 | return; | |
1052 | } | |
1053 | ||
1054 | /* | |
1055 | * Check for a National Semiconductor SuperIO chip. | |
1056 | * Attempt to switch to bank 2, read the value of the LOOP bit | |
1057 | * from EXCR1. Switch back to bank 0, change it in MCR. Then | |
1058 | * switch back to bank 2, read it from EXCR1 again and check | |
1059 | * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 | |
1060 | */ | |
1061 | serial_out(up, UART_LCR, 0); | |
36fd95b1 | 1062 | status1 = serial8250_in_MCR(up); |
b6830f6d PH |
1063 | serial_out(up, UART_LCR, 0xE0); |
1064 | status2 = serial_in(up, 0x02); /* EXCR1 */ | |
1065 | ||
1066 | if (!((status2 ^ status1) & UART_MCR_LOOP)) { | |
1067 | serial_out(up, UART_LCR, 0); | |
36fd95b1 | 1068 | serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP); |
b6830f6d PH |
1069 | serial_out(up, UART_LCR, 0xE0); |
1070 | status2 = serial_in(up, 0x02); /* EXCR1 */ | |
1071 | serial_out(up, UART_LCR, 0); | |
36fd95b1 | 1072 | serial8250_out_MCR(up, status1); |
b6830f6d PH |
1073 | |
1074 | if ((status2 ^ status1) & UART_MCR_LOOP) { | |
1075 | unsigned short quot; | |
1076 | ||
1077 | serial_out(up, UART_LCR, 0xE0); | |
1078 | ||
1079 | quot = serial_dl_read(up); | |
1080 | quot <<= 3; | |
1081 | ||
1082 | if (ns16550a_goto_highspeed(up)) | |
1083 | serial_dl_write(up, quot); | |
1084 | ||
1085 | serial_out(up, UART_LCR, 0); | |
1086 | ||
1087 | up->port.uartclk = 921600*16; | |
1088 | up->port.type = PORT_NS16550A; | |
1089 | up->capabilities |= UART_NATSEMI; | |
1090 | return; | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | /* | |
1095 | * No EFR. Try to detect a TI16750, which only sets bit 5 of | |
1096 | * the IIR when 64 byte FIFO mode is enabled when DLAB is set. | |
1097 | * Try setting it with and without DLAB set. Cheap clones | |
1098 | * set bit 5 without DLAB set. | |
1099 | */ | |
1100 | serial_out(up, UART_LCR, 0); | |
1101 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1102 | status1 = serial_in(up, UART_IIR) >> 5; | |
1103 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1104 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
1105 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1106 | status2 = serial_in(up, UART_IIR) >> 5; | |
1107 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1108 | serial_out(up, UART_LCR, 0); | |
1109 | ||
1110 | DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); | |
1111 | ||
1112 | if (status1 == 6 && status2 == 7) { | |
1113 | up->port.type = PORT_16750; | |
1114 | up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; | |
1115 | return; | |
1116 | } | |
1117 | ||
1118 | /* | |
1119 | * Try writing and reading the UART_IER_UUE bit (b6). | |
1120 | * If it works, this is probably one of the Xscale platform's | |
1121 | * internal UARTs. | |
1122 | * We're going to explicitly set the UUE bit to 0 before | |
1123 | * trying to write and read a 1 just to make sure it's not | |
1124 | * already a 1 and maybe locked there before we even start start. | |
1125 | */ | |
1126 | iersave = serial_in(up, UART_IER); | |
1127 | serial_out(up, UART_IER, iersave & ~UART_IER_UUE); | |
1128 | if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { | |
1129 | /* | |
1130 | * OK it's in a known zero state, try writing and reading | |
1131 | * without disturbing the current state of the other bits. | |
1132 | */ | |
1133 | serial_out(up, UART_IER, iersave | UART_IER_UUE); | |
1134 | if (serial_in(up, UART_IER) & UART_IER_UUE) { | |
1135 | /* | |
1136 | * It's an Xscale. | |
1137 | * We'll leave the UART_IER_UUE bit set to 1 (enabled). | |
1138 | */ | |
1139 | DEBUG_AUTOCONF("Xscale "); | |
1140 | up->port.type = PORT_XSCALE; | |
1141 | up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE; | |
1142 | return; | |
1143 | } | |
1144 | } else { | |
1145 | /* | |
1146 | * If we got here we couldn't force the IER_UUE bit to 0. | |
1147 | * Log it and continue. | |
1148 | */ | |
1149 | DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); | |
1150 | } | |
1151 | serial_out(up, UART_IER, iersave); | |
1152 | ||
1153 | /* | |
1154 | * Exar uarts have EFR in a weird location | |
1155 | */ | |
1156 | if (up->port.flags & UPF_EXAR_EFR) { | |
1157 | DEBUG_AUTOCONF("Exar XR17D15x "); | |
1158 | up->port.type = PORT_XR17D15X; | |
1159 | up->capabilities |= UART_CAP_AFE | UART_CAP_EFR | | |
1160 | UART_CAP_SLEEP; | |
1161 | ||
1162 | return; | |
1163 | } | |
1164 | ||
1165 | /* | |
1166 | * We distinguish between 16550A and U6 16550A by counting | |
1167 | * how many bytes are in the FIFO. | |
1168 | */ | |
1169 | if (up->port.type == PORT_16550A && size_fifo(up) == 64) { | |
1170 | up->port.type = PORT_U6_16550A; | |
1171 | up->capabilities |= UART_CAP_AFE; | |
1172 | } | |
1173 | } | |
1174 | ||
1175 | /* | |
1176 | * This routine is called by rs_init() to initialize a specific serial | |
1177 | * port. It determines what type of UART chip this serial port is | |
1178 | * using: 8250, 16450, 16550, 16550A. The important question is | |
1179 | * whether or not this UART is a 16550A or not, since this will | |
1180 | * determine whether or not we can use its FIFO features or not. | |
1181 | */ | |
1182 | static void autoconfig(struct uart_8250_port *up) | |
1183 | { | |
1184 | unsigned char status1, scratch, scratch2, scratch3; | |
1185 | unsigned char save_lcr, save_mcr; | |
1186 | struct uart_port *port = &up->port; | |
1187 | unsigned long flags; | |
1188 | unsigned int old_capabilities; | |
1189 | ||
1190 | if (!port->iobase && !port->mapbase && !port->membase) | |
1191 | return; | |
1192 | ||
1193 | DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ", | |
1194 | serial_index(port), port->iobase, port->membase); | |
1195 | ||
1196 | /* | |
1197 | * We really do need global IRQs disabled here - we're going to | |
1198 | * be frobbing the chips IRQ enable register to see if it exists. | |
1199 | */ | |
1200 | spin_lock_irqsave(&port->lock, flags); | |
1201 | ||
1202 | up->capabilities = 0; | |
1203 | up->bugs = 0; | |
1204 | ||
1205 | if (!(port->flags & UPF_BUGGY_UART)) { | |
1206 | /* | |
1207 | * Do a simple existence test first; if we fail this, | |
1208 | * there's no point trying anything else. | |
1209 | * | |
1210 | * 0x80 is used as a nonsense port to prevent against | |
1211 | * false positives due to ISA bus float. The | |
1212 | * assumption is that 0x80 is a non-existent port; | |
1213 | * which should be safe since include/asm/io.h also | |
1214 | * makes this assumption. | |
1215 | * | |
1216 | * Note: this is safe as long as MCR bit 4 is clear | |
1217 | * and the device is in "PC" mode. | |
1218 | */ | |
1219 | scratch = serial_in(up, UART_IER); | |
1220 | serial_out(up, UART_IER, 0); | |
1221 | #ifdef __i386__ | |
1222 | outb(0xff, 0x080); | |
1223 | #endif | |
1224 | /* | |
1225 | * Mask out IER[7:4] bits for test as some UARTs (e.g. TL | |
1226 | * 16C754B) allow only to modify them if an EFR bit is set. | |
1227 | */ | |
1228 | scratch2 = serial_in(up, UART_IER) & 0x0f; | |
1229 | serial_out(up, UART_IER, 0x0F); | |
1230 | #ifdef __i386__ | |
1231 | outb(0, 0x080); | |
1232 | #endif | |
1233 | scratch3 = serial_in(up, UART_IER) & 0x0f; | |
1234 | serial_out(up, UART_IER, scratch); | |
1235 | if (scratch2 != 0 || scratch3 != 0x0F) { | |
1236 | /* | |
1237 | * We failed; there's nothing here | |
1238 | */ | |
1239 | spin_unlock_irqrestore(&port->lock, flags); | |
1240 | DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", | |
1241 | scratch2, scratch3); | |
1242 | goto out; | |
1243 | } | |
1244 | } | |
1245 | ||
36fd95b1 | 1246 | save_mcr = serial8250_in_MCR(up); |
b6830f6d PH |
1247 | save_lcr = serial_in(up, UART_LCR); |
1248 | ||
1249 | /* | |
1250 | * Check to see if a UART is really there. Certain broken | |
1251 | * internal modems based on the Rockwell chipset fail this | |
1252 | * test, because they apparently don't implement the loopback | |
1253 | * test mode. So this test is skipped on the COM 1 through | |
1254 | * COM 4 ports. This *should* be safe, since no board | |
1255 | * manufacturer would be stupid enough to design a board | |
1256 | * that conflicts with COM 1-4 --- we hope! | |
1257 | */ | |
1258 | if (!(port->flags & UPF_SKIP_TEST)) { | |
36fd95b1 | 1259 | serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A); |
b6830f6d | 1260 | status1 = serial_in(up, UART_MSR) & 0xF0; |
36fd95b1 | 1261 | serial8250_out_MCR(up, save_mcr); |
b6830f6d PH |
1262 | if (status1 != 0x90) { |
1263 | spin_unlock_irqrestore(&port->lock, flags); | |
1264 | DEBUG_AUTOCONF("LOOP test failed (%02x) ", | |
1265 | status1); | |
1266 | goto out; | |
1267 | } | |
1268 | } | |
1269 | ||
1270 | /* | |
1271 | * We're pretty sure there's a port here. Lets find out what | |
1272 | * type of port it is. The IIR top two bits allows us to find | |
1273 | * out if it's 8250 or 16450, 16550, 16550A or later. This | |
1274 | * determines what we test for next. | |
1275 | * | |
1276 | * We also initialise the EFR (if any) to zero for later. The | |
1277 | * EFR occupies the same register location as the FCR and IIR. | |
1278 | */ | |
1279 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
1280 | serial_out(up, UART_EFR, 0); | |
1281 | serial_out(up, UART_LCR, 0); | |
1282 | ||
1283 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
1284 | scratch = serial_in(up, UART_IIR) >> 6; | |
1285 | ||
1286 | switch (scratch) { | |
1287 | case 0: | |
1288 | autoconfig_8250(up); | |
1289 | break; | |
1290 | case 1: | |
1291 | port->type = PORT_UNKNOWN; | |
1292 | break; | |
1293 | case 2: | |
1294 | port->type = PORT_16550; | |
1295 | break; | |
1296 | case 3: | |
1297 | autoconfig_16550a(up); | |
1298 | break; | |
1299 | } | |
1300 | ||
1301 | #ifdef CONFIG_SERIAL_8250_RSA | |
1302 | /* | |
1303 | * Only probe for RSA ports if we got the region. | |
1304 | */ | |
1305 | if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA && | |
1306 | __enable_rsa(up)) | |
1307 | port->type = PORT_RSA; | |
1308 | #endif | |
1309 | ||
1310 | serial_out(up, UART_LCR, save_lcr); | |
1311 | ||
1312 | port->fifosize = uart_config[up->port.type].fifo_size; | |
1313 | old_capabilities = up->capabilities; | |
1314 | up->capabilities = uart_config[port->type].flags; | |
1315 | up->tx_loadsz = uart_config[port->type].tx_loadsz; | |
1316 | ||
1317 | if (port->type == PORT_UNKNOWN) | |
1318 | goto out_lock; | |
1319 | ||
1320 | /* | |
1321 | * Reset the UART. | |
1322 | */ | |
1323 | #ifdef CONFIG_SERIAL_8250_RSA | |
1324 | if (port->type == PORT_RSA) | |
1325 | serial_out(up, UART_RSA_FRR, 0); | |
1326 | #endif | |
36fd95b1 | 1327 | serial8250_out_MCR(up, save_mcr); |
b6830f6d PH |
1328 | serial8250_clear_fifos(up); |
1329 | serial_in(up, UART_RX); | |
1330 | if (up->capabilities & UART_CAP_UUE) | |
1331 | serial_out(up, UART_IER, UART_IER_UUE); | |
1332 | else | |
1333 | serial_out(up, UART_IER, 0); | |
1334 | ||
1335 | out_lock: | |
1336 | spin_unlock_irqrestore(&port->lock, flags); | |
fa01e2ca RRD |
1337 | |
1338 | /* | |
1339 | * Check if the device is a Fintek F81216A | |
1340 | */ | |
4c4fc909 | 1341 | if (port->type == PORT_16550A && port->iotype == UPIO_PORT) |
fa01e2ca RRD |
1342 | fintek_8250_probe(up); |
1343 | ||
b6830f6d | 1344 | if (up->capabilities != old_capabilities) { |
9f59fbf0 | 1345 | pr_warn("ttyS%d: detected caps %08x should be %08x\n", |
b6830f6d PH |
1346 | serial_index(port), old_capabilities, |
1347 | up->capabilities); | |
1348 | } | |
1349 | out: | |
1350 | DEBUG_AUTOCONF("iir=%d ", scratch); | |
1351 | DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name); | |
1352 | } | |
1353 | ||
1354 | static void autoconfig_irq(struct uart_8250_port *up) | |
1355 | { | |
1356 | struct uart_port *port = &up->port; | |
1357 | unsigned char save_mcr, save_ier; | |
1358 | unsigned char save_ICP = 0; | |
1359 | unsigned int ICP = 0; | |
1360 | unsigned long irqs; | |
1361 | int irq; | |
1362 | ||
1363 | if (port->flags & UPF_FOURPORT) { | |
1364 | ICP = (port->iobase & 0xfe0) | 0x1f; | |
1365 | save_ICP = inb_p(ICP); | |
1366 | outb_p(0x80, ICP); | |
1367 | inb_p(ICP); | |
1368 | } | |
1369 | ||
9a23a1d1 TK |
1370 | if (uart_console(port)) |
1371 | console_lock(); | |
1372 | ||
b6830f6d PH |
1373 | /* forget possible initially masked and pending IRQ */ |
1374 | probe_irq_off(probe_irq_on()); | |
36fd95b1 | 1375 | save_mcr = serial8250_in_MCR(up); |
b6830f6d | 1376 | save_ier = serial_in(up, UART_IER); |
36fd95b1 | 1377 | serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2); |
b6830f6d PH |
1378 | |
1379 | irqs = probe_irq_on(); | |
36fd95b1 | 1380 | serial8250_out_MCR(up, 0); |
b6830f6d PH |
1381 | udelay(10); |
1382 | if (port->flags & UPF_FOURPORT) { | |
36fd95b1 | 1383 | serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS); |
b6830f6d | 1384 | } else { |
36fd95b1 YY |
1385 | serial8250_out_MCR(up, |
1386 | UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); | |
b6830f6d PH |
1387 | } |
1388 | serial_out(up, UART_IER, 0x0f); /* enable all intrs */ | |
1389 | serial_in(up, UART_LSR); | |
1390 | serial_in(up, UART_RX); | |
1391 | serial_in(up, UART_IIR); | |
1392 | serial_in(up, UART_MSR); | |
1393 | serial_out(up, UART_TX, 0xFF); | |
1394 | udelay(20); | |
1395 | irq = probe_irq_off(irqs); | |
1396 | ||
36fd95b1 | 1397 | serial8250_out_MCR(up, save_mcr); |
b6830f6d PH |
1398 | serial_out(up, UART_IER, save_ier); |
1399 | ||
1400 | if (port->flags & UPF_FOURPORT) | |
1401 | outb_p(save_ICP, ICP); | |
1402 | ||
9a23a1d1 TK |
1403 | if (uart_console(port)) |
1404 | console_unlock(); | |
1405 | ||
b6830f6d PH |
1406 | port->irq = (irq > 0) ? irq : 0; |
1407 | } | |
1408 | ||
a07a70bc MK |
1409 | static void serial8250_stop_rx(struct uart_port *port) |
1410 | { | |
1411 | struct uart_8250_port *up = up_to_u8250p(port); | |
1412 | ||
1413 | serial8250_rpm_get(up); | |
1414 | ||
1415 | up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); | |
1416 | up->port.read_status_mask &= ~UART_LSR_DR; | |
1417 | serial_port_out(port, UART_IER, up->ier); | |
1418 | ||
1419 | serial8250_rpm_put(up); | |
1420 | } | |
1421 | ||
e490c914 MK |
1422 | static void __do_stop_tx_rs485(struct uart_8250_port *p) |
1423 | { | |
e490c914 | 1424 | serial8250_em485_rts_after_send(p); |
f3bf2632 | 1425 | |
e490c914 MK |
1426 | /* |
1427 | * Empty the RX FIFO, we are not interested in anything | |
1428 | * received during the half-duplex transmission. | |
0c66940d | 1429 | * Enable previously disabled RX interrupts. |
e490c914 | 1430 | */ |
0c66940d | 1431 | if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) { |
2bed8a8e | 1432 | serial8250_clear_and_reinit_fifos(p); |
0c66940d | 1433 | |
0c66940d YY |
1434 | p->ier |= UART_IER_RLSI | UART_IER_RDI; |
1435 | serial_port_out(&p->port, UART_IER, p->ier); | |
0c66940d | 1436 | } |
e490c914 MK |
1437 | } |
1438 | ||
1439 | static void serial8250_em485_handle_stop_tx(unsigned long arg) | |
1440 | { | |
1441 | struct uart_8250_port *p = (struct uart_8250_port *)arg; | |
1442 | struct uart_8250_em485 *em485 = p->em485; | |
1443 | unsigned long flags; | |
1444 | ||
b3965767 | 1445 | serial8250_rpm_get(p); |
e490c914 MK |
1446 | spin_lock_irqsave(&p->port.lock, flags); |
1447 | if (em485 && | |
1448 | em485->active_timer == &em485->stop_tx_timer) { | |
1449 | __do_stop_tx_rs485(p); | |
1450 | em485->active_timer = NULL; | |
1451 | } | |
1452 | spin_unlock_irqrestore(&p->port.lock, flags); | |
b3965767 | 1453 | serial8250_rpm_put(p); |
e490c914 MK |
1454 | } |
1455 | ||
1456 | static void __stop_tx_rs485(struct uart_8250_port *p) | |
1457 | { | |
1458 | struct uart_8250_em485 *em485 = p->em485; | |
1459 | ||
e490c914 MK |
1460 | /* |
1461 | * __do_stop_tx_rs485 is going to set RTS according to config | |
1462 | * AND flush RX FIFO if required. | |
1463 | */ | |
1464 | if (p->port.rs485.delay_rts_after_send > 0) { | |
1465 | em485->active_timer = &em485->stop_tx_timer; | |
1466 | mod_timer(&em485->stop_tx_timer, jiffies + | |
1467 | p->port.rs485.delay_rts_after_send * HZ / 1000); | |
1468 | } else { | |
1469 | __do_stop_tx_rs485(p); | |
1470 | } | |
1471 | } | |
1472 | ||
1473 | static inline void __do_stop_tx(struct uart_8250_port *p) | |
b6830f6d PH |
1474 | { |
1475 | if (p->ier & UART_IER_THRI) { | |
1476 | p->ier &= ~UART_IER_THRI; | |
1477 | serial_out(p, UART_IER, p->ier); | |
1478 | serial8250_rpm_put_tx(p); | |
1479 | } | |
1480 | } | |
1481 | ||
e490c914 MK |
1482 | static inline void __stop_tx(struct uart_8250_port *p) |
1483 | { | |
1484 | struct uart_8250_em485 *em485 = p->em485; | |
1485 | ||
1486 | if (em485) { | |
1487 | unsigned char lsr = serial_in(p, UART_LSR); | |
1488 | /* | |
1489 | * To provide required timeing and allow FIFO transfer, | |
b3965767 | 1490 | * __stop_tx_rs485() must be called only when both FIFO and |
e490c914 MK |
1491 | * shift register are empty. It is for device driver to enable |
1492 | * interrupt on TEMT. | |
1493 | */ | |
1494 | if ((lsr & BOTH_EMPTY) != BOTH_EMPTY) | |
1495 | return; | |
1496 | ||
1497 | del_timer(&em485->start_tx_timer); | |
1498 | em485->active_timer = NULL; | |
b3965767 AS |
1499 | |
1500 | __stop_tx_rs485(p); | |
e490c914 MK |
1501 | } |
1502 | __do_stop_tx(p); | |
e490c914 MK |
1503 | } |
1504 | ||
b6830f6d PH |
1505 | static void serial8250_stop_tx(struct uart_port *port) |
1506 | { | |
1507 | struct uart_8250_port *up = up_to_u8250p(port); | |
1508 | ||
1509 | serial8250_rpm_get(up); | |
1510 | __stop_tx(up); | |
1511 | ||
1512 | /* | |
1513 | * We really want to stop the transmitter from sending. | |
1514 | */ | |
1515 | if (port->type == PORT_16C950) { | |
1516 | up->acr |= UART_ACR_TXDIS; | |
1517 | serial_icr_write(up, UART_ACR, up->acr); | |
1518 | } | |
1519 | serial8250_rpm_put(up); | |
1520 | } | |
1521 | ||
e490c914 | 1522 | static inline void __start_tx(struct uart_port *port) |
b6830f6d PH |
1523 | { |
1524 | struct uart_8250_port *up = up_to_u8250p(port); | |
1525 | ||
b6830f6d PH |
1526 | if (up->dma && !up->dma->tx_dma(up)) |
1527 | return; | |
1528 | ||
1529 | if (!(up->ier & UART_IER_THRI)) { | |
1530 | up->ier |= UART_IER_THRI; | |
1531 | serial_port_out(port, UART_IER, up->ier); | |
1532 | ||
1533 | if (up->bugs & UART_BUG_TXEN) { | |
1534 | unsigned char lsr; | |
1a33e342 | 1535 | |
b6830f6d PH |
1536 | lsr = serial_in(up, UART_LSR); |
1537 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; | |
1538 | if (lsr & UART_LSR_THRE) | |
1539 | serial8250_tx_chars(up); | |
1540 | } | |
1541 | } | |
1542 | ||
1543 | /* | |
1544 | * Re-enable the transmitter if we disabled it. | |
1545 | */ | |
1546 | if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { | |
1547 | up->acr &= ~UART_ACR_TXDIS; | |
1548 | serial_icr_write(up, UART_ACR, up->acr); | |
1549 | } | |
1550 | } | |
1551 | ||
e490c914 MK |
1552 | static inline void start_tx_rs485(struct uart_port *port) |
1553 | { | |
1554 | struct uart_8250_port *up = up_to_u8250p(port); | |
1555 | struct uart_8250_em485 *em485 = up->em485; | |
1556 | unsigned char mcr; | |
1557 | ||
1558 | if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) | |
1559 | serial8250_stop_rx(&up->port); | |
1560 | ||
1561 | del_timer(&em485->stop_tx_timer); | |
1562 | em485->active_timer = NULL; | |
1563 | ||
36fd95b1 | 1564 | mcr = serial8250_in_MCR(up); |
e490c914 MK |
1565 | if (!!(up->port.rs485.flags & SER_RS485_RTS_ON_SEND) != |
1566 | !!(mcr & UART_MCR_RTS)) { | |
1567 | if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND) | |
1568 | mcr |= UART_MCR_RTS; | |
1569 | else | |
1570 | mcr &= ~UART_MCR_RTS; | |
36fd95b1 | 1571 | serial8250_out_MCR(up, mcr); |
e490c914 MK |
1572 | |
1573 | if (up->port.rs485.delay_rts_before_send > 0) { | |
1574 | em485->active_timer = &em485->start_tx_timer; | |
1575 | mod_timer(&em485->start_tx_timer, jiffies + | |
1576 | up->port.rs485.delay_rts_before_send * HZ / 1000); | |
1577 | return; | |
1578 | } | |
1579 | } | |
1580 | ||
1581 | __start_tx(port); | |
1582 | } | |
1583 | ||
1584 | static void serial8250_em485_handle_start_tx(unsigned long arg) | |
1585 | { | |
1586 | struct uart_8250_port *p = (struct uart_8250_port *)arg; | |
1587 | struct uart_8250_em485 *em485 = p->em485; | |
1588 | unsigned long flags; | |
1589 | ||
1590 | spin_lock_irqsave(&p->port.lock, flags); | |
1591 | if (em485 && | |
1592 | em485->active_timer == &em485->start_tx_timer) { | |
1593 | __start_tx(&p->port); | |
1594 | em485->active_timer = NULL; | |
1595 | } | |
1596 | spin_unlock_irqrestore(&p->port.lock, flags); | |
1597 | } | |
1598 | ||
1599 | static void serial8250_start_tx(struct uart_port *port) | |
1600 | { | |
1601 | struct uart_8250_port *up = up_to_u8250p(port); | |
1602 | struct uart_8250_em485 *em485 = up->em485; | |
1603 | ||
1604 | serial8250_rpm_get_tx(up); | |
1605 | ||
1606 | if (em485 && | |
1607 | em485->active_timer == &em485->start_tx_timer) | |
1608 | return; | |
1609 | ||
1610 | if (em485) | |
1611 | start_tx_rs485(port); | |
1612 | else | |
1613 | __start_tx(port); | |
1614 | } | |
1615 | ||
b6830f6d PH |
1616 | static void serial8250_throttle(struct uart_port *port) |
1617 | { | |
1618 | port->throttle(port); | |
1619 | } | |
1620 | ||
1621 | static void serial8250_unthrottle(struct uart_port *port) | |
1622 | { | |
1623 | port->unthrottle(port); | |
1624 | } | |
1625 | ||
b6830f6d PH |
1626 | static void serial8250_disable_ms(struct uart_port *port) |
1627 | { | |
013e3586 | 1628 | struct uart_8250_port *up = up_to_u8250p(port); |
b6830f6d PH |
1629 | |
1630 | /* no MSR capabilities */ | |
1631 | if (up->bugs & UART_BUG_NOMSR) | |
1632 | return; | |
1633 | ||
1634 | up->ier &= ~UART_IER_MSI; | |
1635 | serial_port_out(port, UART_IER, up->ier); | |
1636 | } | |
1637 | ||
1638 | static void serial8250_enable_ms(struct uart_port *port) | |
1639 | { | |
1640 | struct uart_8250_port *up = up_to_u8250p(port); | |
1641 | ||
1642 | /* no MSR capabilities */ | |
1643 | if (up->bugs & UART_BUG_NOMSR) | |
1644 | return; | |
1645 | ||
1646 | up->ier |= UART_IER_MSI; | |
1647 | ||
1648 | serial8250_rpm_get(up); | |
1649 | serial_port_out(port, UART_IER, up->ier); | |
1650 | serial8250_rpm_put(up); | |
1651 | } | |
1652 | ||
3f6b3ce0 PH |
1653 | static void serial8250_read_char(struct uart_8250_port *up, unsigned char lsr) |
1654 | { | |
1655 | struct uart_port *port = &up->port; | |
1656 | unsigned char ch; | |
1657 | char flag = TTY_NORMAL; | |
1658 | ||
1659 | if (likely(lsr & UART_LSR_DR)) | |
1660 | ch = serial_in(up, UART_RX); | |
1661 | else | |
1662 | /* | |
1663 | * Intel 82571 has a Serial Over Lan device that will | |
1664 | * set UART_LSR_BI without setting UART_LSR_DR when | |
1665 | * it receives a break. To avoid reading from the | |
1666 | * receive buffer without UART_LSR_DR bit set, we | |
1667 | * just force the read character to be 0 | |
1668 | */ | |
1669 | ch = 0; | |
1670 | ||
1671 | port->icount.rx++; | |
1672 | ||
1673 | lsr |= up->lsr_saved_flags; | |
1674 | up->lsr_saved_flags = 0; | |
1675 | ||
1676 | if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { | |
1677 | if (lsr & UART_LSR_BI) { | |
1678 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
1679 | port->icount.brk++; | |
1680 | /* | |
1681 | * We do the SysRQ and SAK checking | |
1682 | * here because otherwise the break | |
1683 | * may get masked by ignore_status_mask | |
1684 | * or read_status_mask. | |
1685 | */ | |
1686 | if (uart_handle_break(port)) | |
1687 | return; | |
1688 | } else if (lsr & UART_LSR_PE) | |
1689 | port->icount.parity++; | |
1690 | else if (lsr & UART_LSR_FE) | |
1691 | port->icount.frame++; | |
1692 | if (lsr & UART_LSR_OE) | |
1693 | port->icount.overrun++; | |
1694 | ||
1695 | /* | |
1696 | * Mask off conditions which should be ignored. | |
1697 | */ | |
1698 | lsr &= port->read_status_mask; | |
1699 | ||
1700 | if (lsr & UART_LSR_BI) { | |
934014d5 | 1701 | pr_debug("%s: handling break\n", __func__); |
3f6b3ce0 PH |
1702 | flag = TTY_BREAK; |
1703 | } else if (lsr & UART_LSR_PE) | |
1704 | flag = TTY_PARITY; | |
1705 | else if (lsr & UART_LSR_FE) | |
1706 | flag = TTY_FRAME; | |
1707 | } | |
1708 | if (uart_handle_sysrq_char(port, ch)) | |
1709 | return; | |
1710 | ||
1711 | uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); | |
1712 | } | |
1713 | ||
b6830f6d PH |
1714 | /* |
1715 | * serial8250_rx_chars: processes according to the passed in LSR | |
1716 | * value, and returns the remaining LSR bits not handled | |
1717 | * by this Rx routine. | |
1718 | */ | |
d22f8f10 | 1719 | unsigned char serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr) |
b6830f6d PH |
1720 | { |
1721 | struct uart_port *port = &up->port; | |
b6830f6d | 1722 | int max_count = 256; |
b6830f6d PH |
1723 | |
1724 | do { | |
3f6b3ce0 | 1725 | serial8250_read_char(up, lsr); |
d22f8f10 PH |
1726 | if (--max_count == 0) |
1727 | break; | |
b6830f6d | 1728 | lsr = serial_in(up, UART_LSR); |
d22f8f10 | 1729 | } while (lsr & (UART_LSR_DR | UART_LSR_BI)); |
6a597a38 | 1730 | |
b6830f6d | 1731 | tty_flip_buffer_push(&port->state->port); |
b6830f6d PH |
1732 | return lsr; |
1733 | } | |
1734 | EXPORT_SYMBOL_GPL(serial8250_rx_chars); | |
1735 | ||
1736 | void serial8250_tx_chars(struct uart_8250_port *up) | |
1737 | { | |
1738 | struct uart_port *port = &up->port; | |
1739 | struct circ_buf *xmit = &port->state->xmit; | |
1740 | int count; | |
1741 | ||
1742 | if (port->x_char) { | |
1743 | serial_out(up, UART_TX, port->x_char); | |
1744 | port->icount.tx++; | |
1745 | port->x_char = 0; | |
1746 | return; | |
1747 | } | |
1748 | if (uart_tx_stopped(port)) { | |
1749 | serial8250_stop_tx(port); | |
1750 | return; | |
1751 | } | |
1752 | if (uart_circ_empty(xmit)) { | |
1753 | __stop_tx(up); | |
1754 | return; | |
1755 | } | |
1756 | ||
1757 | count = up->tx_loadsz; | |
1758 | do { | |
1759 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
1760 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1761 | port->icount.tx++; | |
1762 | if (uart_circ_empty(xmit)) | |
1763 | break; | |
cee10c8c PH |
1764 | if ((up->capabilities & UART_CAP_HFIFO) && |
1765 | (serial_in(up, UART_LSR) & BOTH_EMPTY) != BOTH_EMPTY) | |
1766 | break; | |
b6830f6d PH |
1767 | } while (--count > 0); |
1768 | ||
1769 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1770 | uart_write_wakeup(port); | |
1771 | ||
b6830f6d PH |
1772 | /* |
1773 | * With RPM enabled, we have to wait until the FIFO is empty before the | |
1774 | * HW can go idle. So we get here once again with empty FIFO and disable | |
1775 | * the interrupt and RPM in __stop_tx() | |
1776 | */ | |
1777 | if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM)) | |
1778 | __stop_tx(up); | |
1779 | } | |
1780 | EXPORT_SYMBOL_GPL(serial8250_tx_chars); | |
1781 | ||
1782 | /* Caller holds uart port lock */ | |
1783 | unsigned int serial8250_modem_status(struct uart_8250_port *up) | |
1784 | { | |
1785 | struct uart_port *port = &up->port; | |
1786 | unsigned int status = serial_in(up, UART_MSR); | |
1787 | ||
1788 | status |= up->msr_saved_flags; | |
1789 | up->msr_saved_flags = 0; | |
1790 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && | |
1791 | port->state != NULL) { | |
1792 | if (status & UART_MSR_TERI) | |
1793 | port->icount.rng++; | |
1794 | if (status & UART_MSR_DDSR) | |
1795 | port->icount.dsr++; | |
1796 | if (status & UART_MSR_DDCD) | |
1797 | uart_handle_dcd_change(port, status & UART_MSR_DCD); | |
1798 | if (status & UART_MSR_DCTS) | |
1799 | uart_handle_cts_change(port, status & UART_MSR_CTS); | |
1800 | ||
1801 | wake_up_interruptible(&port->state->port.delta_msr_wait); | |
1802 | } | |
1803 | ||
1804 | return status; | |
1805 | } | |
1806 | EXPORT_SYMBOL_GPL(serial8250_modem_status); | |
1807 | ||
33d9b8b2 PH |
1808 | static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir) |
1809 | { | |
1810 | switch (iir & 0x3f) { | |
1811 | case UART_IIR_RX_TIMEOUT: | |
1812 | serial8250_rx_dma_flush(up); | |
1813 | /* fall-through */ | |
1814 | case UART_IIR_RLSI: | |
1815 | return true; | |
1816 | } | |
1817 | return up->dma->rx_dma(up); | |
1818 | } | |
1819 | ||
b6830f6d PH |
1820 | /* |
1821 | * This handles the interrupt from one port. | |
1822 | */ | |
1823 | int serial8250_handle_irq(struct uart_port *port, unsigned int iir) | |
1824 | { | |
1825 | unsigned char status; | |
1826 | unsigned long flags; | |
1827 | struct uart_8250_port *up = up_to_u8250p(port); | |
b6830f6d PH |
1828 | |
1829 | if (iir & UART_IIR_NO_INT) | |
1830 | return 0; | |
1831 | ||
1832 | spin_lock_irqsave(&port->lock, flags); | |
1833 | ||
1834 | status = serial_port_in(port, UART_LSR); | |
1835 | ||
b6830f6d | 1836 | if (status & (UART_LSR_DR | UART_LSR_BI)) { |
33d9b8b2 | 1837 | if (!up->dma || handle_rx_dma(up, iir)) |
b6830f6d PH |
1838 | status = serial8250_rx_chars(up, status); |
1839 | } | |
1840 | serial8250_modem_status(up); | |
d601744d | 1841 | if ((!up->dma || up->dma->tx_err) && (status & UART_LSR_THRE)) |
b6830f6d PH |
1842 | serial8250_tx_chars(up); |
1843 | ||
1844 | spin_unlock_irqrestore(&port->lock, flags); | |
1845 | return 1; | |
1846 | } | |
1847 | EXPORT_SYMBOL_GPL(serial8250_handle_irq); | |
1848 | ||
1849 | static int serial8250_default_handle_irq(struct uart_port *port) | |
1850 | { | |
1851 | struct uart_8250_port *up = up_to_u8250p(port); | |
1852 | unsigned int iir; | |
1853 | int ret; | |
1854 | ||
1855 | serial8250_rpm_get(up); | |
1856 | ||
1857 | iir = serial_port_in(port, UART_IIR); | |
1858 | ret = serial8250_handle_irq(port, iir); | |
1859 | ||
1860 | serial8250_rpm_put(up); | |
1861 | return ret; | |
1862 | } | |
1863 | ||
1864 | /* | |
1865 | * These Exar UARTs have an extra interrupt indicator that could | |
1866 | * fire for a few unimplemented interrupts. One of which is a | |
1867 | * wakeup event when coming out of sleep. Put this here just | |
1868 | * to be on the safe side that these interrupts don't go unhandled. | |
1869 | */ | |
1870 | static int exar_handle_irq(struct uart_port *port) | |
1871 | { | |
b6830f6d | 1872 | unsigned int iir = serial_port_in(port, UART_IIR); |
2c0ac5b4 | 1873 | int ret = 0; |
b6830f6d | 1874 | |
2c0ac5b4 JK |
1875 | if (((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X)) && |
1876 | serial_port_in(port, UART_EXAR_INT0) != 0) | |
1877 | ret = 1; | |
b6830f6d | 1878 | |
2c0ac5b4 | 1879 | ret |= serial8250_handle_irq(port, iir); |
b6830f6d PH |
1880 | |
1881 | return ret; | |
1882 | } | |
1883 | ||
8e5470c9 TT |
1884 | /* |
1885 | * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP | |
1886 | * have a programmable TX threshold that triggers the THRE interrupt in | |
1887 | * the IIR register. In this case, the THRE interrupt indicates the FIFO | |
1888 | * has space available. Load it up with tx_loadsz bytes. | |
1889 | */ | |
1890 | static int serial8250_tx_threshold_handle_irq(struct uart_port *port) | |
1891 | { | |
1892 | unsigned long flags; | |
1893 | unsigned int iir = serial_port_in(port, UART_IIR); | |
1894 | ||
1895 | /* TX Threshold IRQ triggered so load up FIFO */ | |
1896 | if ((iir & UART_IIR_ID) == UART_IIR_THRI) { | |
1897 | struct uart_8250_port *up = up_to_u8250p(port); | |
1898 | ||
1899 | spin_lock_irqsave(&port->lock, flags); | |
1900 | serial8250_tx_chars(up); | |
1901 | spin_unlock_irqrestore(&port->lock, flags); | |
1902 | } | |
1903 | ||
1904 | iir = serial_port_in(port, UART_IIR); | |
1905 | return serial8250_handle_irq(port, iir); | |
1906 | } | |
1907 | ||
b6830f6d PH |
1908 | static unsigned int serial8250_tx_empty(struct uart_port *port) |
1909 | { | |
1910 | struct uart_8250_port *up = up_to_u8250p(port); | |
1911 | unsigned long flags; | |
1912 | unsigned int lsr; | |
1913 | ||
1914 | serial8250_rpm_get(up); | |
1915 | ||
1916 | spin_lock_irqsave(&port->lock, flags); | |
1917 | lsr = serial_port_in(port, UART_LSR); | |
1918 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; | |
1919 | spin_unlock_irqrestore(&port->lock, flags); | |
1920 | ||
1921 | serial8250_rpm_put(up); | |
1922 | ||
1923 | return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; | |
1924 | } | |
1925 | ||
144ef5c2 | 1926 | unsigned int serial8250_do_get_mctrl(struct uart_port *port) |
b6830f6d PH |
1927 | { |
1928 | struct uart_8250_port *up = up_to_u8250p(port); | |
1929 | unsigned int status; | |
1930 | unsigned int ret; | |
1931 | ||
1932 | serial8250_rpm_get(up); | |
1933 | status = serial8250_modem_status(up); | |
1934 | serial8250_rpm_put(up); | |
1935 | ||
1936 | ret = 0; | |
1937 | if (status & UART_MSR_DCD) | |
1938 | ret |= TIOCM_CAR; | |
1939 | if (status & UART_MSR_RI) | |
1940 | ret |= TIOCM_RNG; | |
1941 | if (status & UART_MSR_DSR) | |
1942 | ret |= TIOCM_DSR; | |
1943 | if (status & UART_MSR_CTS) | |
1944 | ret |= TIOCM_CTS; | |
5db4f7f8 | 1945 | return ret; |
b6830f6d | 1946 | } |
144ef5c2 WAZ |
1947 | EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl); |
1948 | ||
1949 | static unsigned int serial8250_get_mctrl(struct uart_port *port) | |
1950 | { | |
1951 | if (port->get_mctrl) | |
1952 | return port->get_mctrl(port); | |
1953 | return serial8250_do_get_mctrl(port); | |
1954 | } | |
b6830f6d PH |
1955 | |
1956 | void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1957 | { | |
1958 | struct uart_8250_port *up = up_to_u8250p(port); | |
1959 | unsigned char mcr = 0; | |
1960 | ||
1961 | if (mctrl & TIOCM_RTS) | |
1962 | mcr |= UART_MCR_RTS; | |
1963 | if (mctrl & TIOCM_DTR) | |
1964 | mcr |= UART_MCR_DTR; | |
1965 | if (mctrl & TIOCM_OUT1) | |
1966 | mcr |= UART_MCR_OUT1; | |
1967 | if (mctrl & TIOCM_OUT2) | |
1968 | mcr |= UART_MCR_OUT2; | |
1969 | if (mctrl & TIOCM_LOOP) | |
1970 | mcr |= UART_MCR_LOOP; | |
1971 | ||
1972 | mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; | |
1973 | ||
36fd95b1 | 1974 | serial8250_out_MCR(up, mcr); |
b6830f6d PH |
1975 | } |
1976 | EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl); | |
1977 | ||
1978 | static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1979 | { | |
1980 | if (port->set_mctrl) | |
1981 | port->set_mctrl(port, mctrl); | |
1982 | else | |
1983 | serial8250_do_set_mctrl(port, mctrl); | |
1984 | } | |
1985 | ||
1986 | static void serial8250_break_ctl(struct uart_port *port, int break_state) | |
1987 | { | |
1988 | struct uart_8250_port *up = up_to_u8250p(port); | |
1989 | unsigned long flags; | |
1990 | ||
1991 | serial8250_rpm_get(up); | |
1992 | spin_lock_irqsave(&port->lock, flags); | |
1993 | if (break_state == -1) | |
1994 | up->lcr |= UART_LCR_SBC; | |
1995 | else | |
1996 | up->lcr &= ~UART_LCR_SBC; | |
1997 | serial_port_out(port, UART_LCR, up->lcr); | |
1998 | spin_unlock_irqrestore(&port->lock, flags); | |
1999 | serial8250_rpm_put(up); | |
2000 | } | |
2001 | ||
2002 | /* | |
2003 | * Wait for transmitter & holding register to empty | |
2004 | */ | |
2005 | static void wait_for_xmitr(struct uart_8250_port *up, int bits) | |
2006 | { | |
2007 | unsigned int status, tmout = 10000; | |
2008 | ||
2009 | /* Wait up to 10ms for the character(s) to be sent. */ | |
2010 | for (;;) { | |
2011 | status = serial_in(up, UART_LSR); | |
2012 | ||
2013 | up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; | |
2014 | ||
2015 | if ((status & bits) == bits) | |
2016 | break; | |
2017 | if (--tmout == 0) | |
2018 | break; | |
2019 | udelay(1); | |
54f19b4a | 2020 | touch_nmi_watchdog(); |
b6830f6d PH |
2021 | } |
2022 | ||
2023 | /* Wait up to 1s for flow control if necessary */ | |
2024 | if (up->port.flags & UPF_CONS_FLOW) { | |
b6830f6d PH |
2025 | for (tmout = 1000000; tmout; tmout--) { |
2026 | unsigned int msr = serial_in(up, UART_MSR); | |
2027 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
2028 | if (msr & UART_MSR_CTS) | |
2029 | break; | |
2030 | udelay(1); | |
2031 | touch_nmi_watchdog(); | |
2032 | } | |
2033 | } | |
2034 | } | |
2035 | ||
2036 | #ifdef CONFIG_CONSOLE_POLL | |
2037 | /* | |
2038 | * Console polling routines for writing and reading from the uart while | |
2039 | * in an interrupt or debug context. | |
2040 | */ | |
2041 | ||
2042 | static int serial8250_get_poll_char(struct uart_port *port) | |
2043 | { | |
2044 | struct uart_8250_port *up = up_to_u8250p(port); | |
2045 | unsigned char lsr; | |
2046 | int status; | |
2047 | ||
2048 | serial8250_rpm_get(up); | |
2049 | ||
2050 | lsr = serial_port_in(port, UART_LSR); | |
2051 | ||
2052 | if (!(lsr & UART_LSR_DR)) { | |
2053 | status = NO_POLL_CHAR; | |
2054 | goto out; | |
2055 | } | |
2056 | ||
2057 | status = serial_port_in(port, UART_RX); | |
2058 | out: | |
2059 | serial8250_rpm_put(up); | |
2060 | return status; | |
2061 | } | |
2062 | ||
2063 | ||
2064 | static void serial8250_put_poll_char(struct uart_port *port, | |
2065 | unsigned char c) | |
2066 | { | |
2067 | unsigned int ier; | |
2068 | struct uart_8250_port *up = up_to_u8250p(port); | |
2069 | ||
2070 | serial8250_rpm_get(up); | |
2071 | /* | |
2072 | * First save the IER then disable the interrupts | |
2073 | */ | |
2074 | ier = serial_port_in(port, UART_IER); | |
2075 | if (up->capabilities & UART_CAP_UUE) | |
2076 | serial_port_out(port, UART_IER, UART_IER_UUE); | |
2077 | else | |
2078 | serial_port_out(port, UART_IER, 0); | |
2079 | ||
2080 | wait_for_xmitr(up, BOTH_EMPTY); | |
2081 | /* | |
2082 | * Send the character out. | |
2083 | */ | |
2084 | serial_port_out(port, UART_TX, c); | |
2085 | ||
2086 | /* | |
2087 | * Finally, wait for transmitter to become empty | |
2088 | * and restore the IER | |
2089 | */ | |
2090 | wait_for_xmitr(up, BOTH_EMPTY); | |
2091 | serial_port_out(port, UART_IER, ier); | |
2092 | serial8250_rpm_put(up); | |
2093 | } | |
2094 | ||
2095 | #endif /* CONFIG_CONSOLE_POLL */ | |
2096 | ||
2097 | int serial8250_do_startup(struct uart_port *port) | |
2098 | { | |
2099 | struct uart_8250_port *up = up_to_u8250p(port); | |
2100 | unsigned long flags; | |
2101 | unsigned char lsr, iir; | |
2102 | int retval; | |
2103 | ||
b6830f6d PH |
2104 | if (!port->fifosize) |
2105 | port->fifosize = uart_config[port->type].fifo_size; | |
2106 | if (!up->tx_loadsz) | |
2107 | up->tx_loadsz = uart_config[port->type].tx_loadsz; | |
2108 | if (!up->capabilities) | |
2109 | up->capabilities = uart_config[port->type].flags; | |
2110 | up->mcr = 0; | |
2111 | ||
2112 | if (port->iotype != up->cur_iotype) | |
2113 | set_io_from_upio(port); | |
2114 | ||
2115 | serial8250_rpm_get(up); | |
2116 | if (port->type == PORT_16C950) { | |
2117 | /* Wake up and initialize UART */ | |
2118 | up->acr = 0; | |
2119 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); | |
2120 | serial_port_out(port, UART_EFR, UART_EFR_ECB); | |
2121 | serial_port_out(port, UART_IER, 0); | |
2122 | serial_port_out(port, UART_LCR, 0); | |
2123 | serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ | |
2124 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); | |
2125 | serial_port_out(port, UART_EFR, UART_EFR_ECB); | |
2126 | serial_port_out(port, UART_LCR, 0); | |
2127 | } | |
2128 | ||
a2d6a987 DL |
2129 | if (port->type == PORT_DA830) { |
2130 | /* Reset the port */ | |
2131 | serial_port_out(port, UART_IER, 0); | |
2132 | serial_port_out(port, UART_DA830_PWREMU_MGMT, 0); | |
2133 | mdelay(10); | |
2134 | ||
2135 | /* Enable Tx, Rx and free run mode */ | |
2136 | serial_port_out(port, UART_DA830_PWREMU_MGMT, | |
2137 | UART_DA830_PWREMU_MGMT_UTRST | | |
2138 | UART_DA830_PWREMU_MGMT_URRST | | |
2139 | UART_DA830_PWREMU_MGMT_FREE); | |
2140 | } | |
2141 | ||
b6830f6d PH |
2142 | #ifdef CONFIG_SERIAL_8250_RSA |
2143 | /* | |
2144 | * If this is an RSA port, see if we can kick it up to the | |
2145 | * higher speed clock. | |
2146 | */ | |
2147 | enable_rsa(up); | |
2148 | #endif | |
da891641 JR |
2149 | |
2150 | if (port->type == PORT_XR17V35X) { | |
2151 | /* | |
2152 | * First enable access to IER [7:5], ISR [5:4], FCR [5:4], | |
2153 | * MCR [7:5] and MSR [7:0] | |
2154 | */ | |
2155 | serial_port_out(port, UART_XR_EFR, UART_EFR_ECB); | |
2156 | ||
2157 | /* | |
2158 | * Make sure all interrups are masked until initialization is | |
2159 | * complete and the FIFOs are cleared | |
2160 | */ | |
2161 | serial_port_out(port, UART_IER, 0); | |
2162 | } | |
2163 | ||
b6830f6d PH |
2164 | /* |
2165 | * Clear the FIFO buffers and disable them. | |
2166 | * (they will be reenabled in set_termios()) | |
2167 | */ | |
2168 | serial8250_clear_fifos(up); | |
2169 | ||
2170 | /* | |
2171 | * Clear the interrupt registers. | |
2172 | */ | |
2173 | serial_port_in(port, UART_LSR); | |
2174 | serial_port_in(port, UART_RX); | |
2175 | serial_port_in(port, UART_IIR); | |
2176 | serial_port_in(port, UART_MSR); | |
2c0ac5b4 JK |
2177 | if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X)) |
2178 | serial_port_in(port, UART_EXAR_INT0); | |
b6830f6d PH |
2179 | |
2180 | /* | |
2181 | * At this point, there's no way the LSR could still be 0xff; | |
2182 | * if it is, then bail out, because there's likely no UART | |
2183 | * here. | |
2184 | */ | |
2185 | if (!(port->flags & UPF_BUGGY_UART) && | |
2186 | (serial_port_in(port, UART_LSR) == 0xff)) { | |
2187 | printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n", | |
2188 | serial_index(port)); | |
2189 | retval = -ENODEV; | |
2190 | goto out; | |
2191 | } | |
2192 | ||
2193 | /* | |
2194 | * For a XR16C850, we need to set the trigger levels | |
2195 | */ | |
2196 | if (port->type == PORT_16850) { | |
2197 | unsigned char fctr; | |
2198 | ||
2199 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
2200 | ||
2201 | fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); | |
2202 | serial_port_out(port, UART_FCTR, | |
2203 | fctr | UART_FCTR_TRGD | UART_FCTR_RX); | |
2204 | serial_port_out(port, UART_TRG, UART_TRG_96); | |
2205 | serial_port_out(port, UART_FCTR, | |
2206 | fctr | UART_FCTR_TRGD | UART_FCTR_TX); | |
2207 | serial_port_out(port, UART_TRG, UART_TRG_96); | |
2208 | ||
2209 | serial_port_out(port, UART_LCR, 0); | |
2210 | } | |
2211 | ||
8e5470c9 TT |
2212 | /* |
2213 | * For the Altera 16550 variants, set TX threshold trigger level. | |
2214 | */ | |
2215 | if (((port->type == PORT_ALTR_16550_F32) || | |
2216 | (port->type == PORT_ALTR_16550_F64) || | |
2217 | (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) { | |
2218 | /* Bounds checking of TX threshold (valid 0 to fifosize-2) */ | |
2219 | if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) { | |
2220 | pr_err("ttyS%d TX FIFO Threshold errors, skipping\n", | |
2221 | serial_index(port)); | |
2222 | } else { | |
2223 | serial_port_out(port, UART_ALTR_AFR, | |
2224 | UART_ALTR_EN_TXFIFO_LW); | |
2225 | serial_port_out(port, UART_ALTR_TX_LOW, | |
2226 | port->fifosize - up->tx_loadsz); | |
2227 | port->handle_irq = serial8250_tx_threshold_handle_irq; | |
2228 | } | |
2229 | } | |
2230 | ||
b6830f6d PH |
2231 | if (port->irq) { |
2232 | unsigned char iir1; | |
2233 | /* | |
2234 | * Test for UARTs that do not reassert THRE when the | |
2235 | * transmitter is idle and the interrupt has already | |
2236 | * been cleared. Real 16550s should always reassert | |
2237 | * this interrupt whenever the transmitter is idle and | |
2238 | * the interrupt is enabled. Delays are necessary to | |
2239 | * allow register changes to become visible. | |
2240 | */ | |
2241 | spin_lock_irqsave(&port->lock, flags); | |
2242 | if (up->port.irqflags & IRQF_SHARED) | |
2243 | disable_irq_nosync(port->irq); | |
2244 | ||
2245 | wait_for_xmitr(up, UART_LSR_THRE); | |
2246 | serial_port_out_sync(port, UART_IER, UART_IER_THRI); | |
2247 | udelay(1); /* allow THRE to set */ | |
2248 | iir1 = serial_port_in(port, UART_IIR); | |
2249 | serial_port_out(port, UART_IER, 0); | |
2250 | serial_port_out_sync(port, UART_IER, UART_IER_THRI); | |
2251 | udelay(1); /* allow a working UART time to re-assert THRE */ | |
2252 | iir = serial_port_in(port, UART_IIR); | |
2253 | serial_port_out(port, UART_IER, 0); | |
2254 | ||
2255 | if (port->irqflags & IRQF_SHARED) | |
2256 | enable_irq(port->irq); | |
2257 | spin_unlock_irqrestore(&port->lock, flags); | |
2258 | ||
2259 | /* | |
2260 | * If the interrupt is not reasserted, or we otherwise | |
2261 | * don't trust the iir, setup a timer to kick the UART | |
2262 | * on a regular basis. | |
2263 | */ | |
2264 | if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) || | |
2265 | up->port.flags & UPF_BUG_THRE) { | |
2266 | up->bugs |= UART_BUG_THRE; | |
2267 | } | |
2268 | } | |
2269 | ||
2270 | retval = up->ops->setup_irq(up); | |
2271 | if (retval) | |
2272 | goto out; | |
2273 | ||
2274 | /* | |
2275 | * Now, initialize the UART | |
2276 | */ | |
2277 | serial_port_out(port, UART_LCR, UART_LCR_WLEN8); | |
2278 | ||
2279 | spin_lock_irqsave(&port->lock, flags); | |
2280 | if (up->port.flags & UPF_FOURPORT) { | |
2281 | if (!up->port.irq) | |
2282 | up->port.mctrl |= TIOCM_OUT1; | |
2283 | } else | |
2284 | /* | |
2285 | * Most PC uarts need OUT2 raised to enable interrupts. | |
2286 | */ | |
2287 | if (port->irq) | |
2288 | up->port.mctrl |= TIOCM_OUT2; | |
2289 | ||
2290 | serial8250_set_mctrl(port, port->mctrl); | |
2291 | ||
740dc2de AW |
2292 | /* |
2293 | * Serial over Lan (SoL) hack: | |
2294 | * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be | |
2295 | * used for Serial Over Lan. Those chips take a longer time than a | |
2296 | * normal serial device to signalize that a transmission data was | |
2297 | * queued. Due to that, the above test generally fails. One solution | |
2298 | * would be to delay the reading of iir. However, this is not | |
2299 | * reliable, since the timeout is variable. So, let's just don't | |
2300 | * test if we receive TX irq. This way, we'll never enable | |
2301 | * UART_BUG_TXEN. | |
b6830f6d PH |
2302 | */ |
2303 | if (up->port.flags & UPF_NO_TXEN_TEST) | |
2304 | goto dont_test_tx_en; | |
2305 | ||
2306 | /* | |
740dc2de AW |
2307 | * Do a quick test to see if we receive an interrupt when we enable |
2308 | * the TX irq. | |
b6830f6d PH |
2309 | */ |
2310 | serial_port_out(port, UART_IER, UART_IER_THRI); | |
2311 | lsr = serial_port_in(port, UART_LSR); | |
2312 | iir = serial_port_in(port, UART_IIR); | |
2313 | serial_port_out(port, UART_IER, 0); | |
2314 | ||
2315 | if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { | |
2316 | if (!(up->bugs & UART_BUG_TXEN)) { | |
2317 | up->bugs |= UART_BUG_TXEN; | |
2318 | pr_debug("ttyS%d - enabling bad tx status workarounds\n", | |
2319 | serial_index(port)); | |
2320 | } | |
2321 | } else { | |
2322 | up->bugs &= ~UART_BUG_TXEN; | |
2323 | } | |
2324 | ||
2325 | dont_test_tx_en: | |
2326 | spin_unlock_irqrestore(&port->lock, flags); | |
2327 | ||
2328 | /* | |
2329 | * Clear the interrupt registers again for luck, and clear the | |
2330 | * saved flags to avoid getting false values from polling | |
2331 | * routines or the previous session. | |
2332 | */ | |
2333 | serial_port_in(port, UART_LSR); | |
2334 | serial_port_in(port, UART_RX); | |
2335 | serial_port_in(port, UART_IIR); | |
2336 | serial_port_in(port, UART_MSR); | |
2c0ac5b4 JK |
2337 | if ((port->type == PORT_XR17V35X) || (port->type == PORT_XR17D15X)) |
2338 | serial_port_in(port, UART_EXAR_INT0); | |
b6830f6d PH |
2339 | up->lsr_saved_flags = 0; |
2340 | up->msr_saved_flags = 0; | |
2341 | ||
2342 | /* | |
2343 | * Request DMA channels for both RX and TX. | |
2344 | */ | |
2345 | if (up->dma) { | |
2346 | retval = serial8250_request_dma(up); | |
2347 | if (retval) { | |
2348 | pr_warn_ratelimited("ttyS%d - failed to request DMA\n", | |
2349 | serial_index(port)); | |
2350 | up->dma = NULL; | |
2351 | } | |
2352 | } | |
2353 | ||
2354 | /* | |
ee3ad90b PH |
2355 | * Set the IER shadow for rx interrupts but defer actual interrupt |
2356 | * enable until after the FIFOs are enabled; otherwise, an already- | |
2357 | * active sender can swamp the interrupt handler with "too much work". | |
b6830f6d PH |
2358 | */ |
2359 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
b6830f6d PH |
2360 | |
2361 | if (port->flags & UPF_FOURPORT) { | |
2362 | unsigned int icp; | |
2363 | /* | |
2364 | * Enable interrupts on the AST Fourport board | |
2365 | */ | |
2366 | icp = (port->iobase & 0xfe0) | 0x01f; | |
2367 | outb_p(0x80, icp); | |
2368 | inb_p(icp); | |
2369 | } | |
2370 | retval = 0; | |
2371 | out: | |
2372 | serial8250_rpm_put(up); | |
2373 | return retval; | |
2374 | } | |
2375 | EXPORT_SYMBOL_GPL(serial8250_do_startup); | |
2376 | ||
2377 | static int serial8250_startup(struct uart_port *port) | |
2378 | { | |
2379 | if (port->startup) | |
2380 | return port->startup(port); | |
2381 | return serial8250_do_startup(port); | |
2382 | } | |
2383 | ||
2384 | void serial8250_do_shutdown(struct uart_port *port) | |
2385 | { | |
2386 | struct uart_8250_port *up = up_to_u8250p(port); | |
2387 | unsigned long flags; | |
2388 | ||
2389 | serial8250_rpm_get(up); | |
2390 | /* | |
2391 | * Disable interrupts from this port | |
2392 | */ | |
611e0d83 | 2393 | spin_lock_irqsave(&port->lock, flags); |
b6830f6d PH |
2394 | up->ier = 0; |
2395 | serial_port_out(port, UART_IER, 0); | |
611e0d83 PH |
2396 | spin_unlock_irqrestore(&port->lock, flags); |
2397 | ||
2398 | synchronize_irq(port->irq); | |
b6830f6d PH |
2399 | |
2400 | if (up->dma) | |
2401 | serial8250_release_dma(up); | |
2402 | ||
2403 | spin_lock_irqsave(&port->lock, flags); | |
2404 | if (port->flags & UPF_FOURPORT) { | |
2405 | /* reset interrupts on the AST Fourport board */ | |
2406 | inb((port->iobase & 0xfe0) | 0x1f); | |
2407 | port->mctrl |= TIOCM_OUT1; | |
2408 | } else | |
2409 | port->mctrl &= ~TIOCM_OUT2; | |
2410 | ||
2411 | serial8250_set_mctrl(port, port->mctrl); | |
2412 | spin_unlock_irqrestore(&port->lock, flags); | |
2413 | ||
2414 | /* | |
2415 | * Disable break condition and FIFOs | |
2416 | */ | |
2417 | serial_port_out(port, UART_LCR, | |
2418 | serial_port_in(port, UART_LCR) & ~UART_LCR_SBC); | |
2419 | serial8250_clear_fifos(up); | |
2420 | ||
2421 | #ifdef CONFIG_SERIAL_8250_RSA | |
2422 | /* | |
2423 | * Reset the RSA board back to 115kbps compat mode. | |
2424 | */ | |
2425 | disable_rsa(up); | |
2426 | #endif | |
2427 | ||
2428 | /* | |
2429 | * Read data port to reset things, and then unlink from | |
2430 | * the IRQ chain. | |
2431 | */ | |
2432 | serial_port_in(port, UART_RX); | |
2433 | serial8250_rpm_put(up); | |
2434 | ||
2435 | up->ops->release_irq(up); | |
2436 | } | |
2437 | EXPORT_SYMBOL_GPL(serial8250_do_shutdown); | |
2438 | ||
2439 | static void serial8250_shutdown(struct uart_port *port) | |
2440 | { | |
2441 | if (port->shutdown) | |
2442 | port->shutdown(port); | |
2443 | else | |
2444 | serial8250_do_shutdown(port); | |
2445 | } | |
2446 | ||
2447 | /* | |
2448 | * XR17V35x UARTs have an extra fractional divisor register (DLD) | |
2449 | * Calculate divisor with extra 4-bit fractional portion | |
2450 | */ | |
2451 | static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up, | |
2452 | unsigned int baud, | |
2453 | unsigned int *frac) | |
2454 | { | |
2455 | struct uart_port *port = &up->port; | |
2456 | unsigned int quot_16; | |
2457 | ||
2458 | quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud); | |
2459 | *frac = quot_16 & 0x0f; | |
2460 | ||
2461 | return quot_16 >> 4; | |
2462 | } | |
2463 | ||
2464 | static unsigned int serial8250_get_divisor(struct uart_8250_port *up, | |
2465 | unsigned int baud, | |
2466 | unsigned int *frac) | |
2467 | { | |
2468 | struct uart_port *port = &up->port; | |
2469 | unsigned int quot; | |
2470 | ||
2471 | /* | |
2472 | * Handle magic divisors for baud rates above baud_base on | |
2473 | * SMSC SuperIO chips. | |
2474 | * | |
2475 | */ | |
2476 | if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2477 | baud == (port->uartclk/4)) | |
2478 | quot = 0x8001; | |
2479 | else if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2480 | baud == (port->uartclk/8)) | |
2481 | quot = 0x8002; | |
2482 | else if (up->port.type == PORT_XR17V35X) | |
2483 | quot = xr17v35x_get_divisor(up, baud, frac); | |
2484 | else | |
2485 | quot = uart_get_divisor(port, baud); | |
2486 | ||
2487 | /* | |
2488 | * Oxford Semi 952 rev B workaround | |
2489 | */ | |
2490 | if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) | |
2491 | quot++; | |
2492 | ||
2493 | return quot; | |
2494 | } | |
2495 | ||
2496 | static unsigned char serial8250_compute_lcr(struct uart_8250_port *up, | |
2497 | tcflag_t c_cflag) | |
2498 | { | |
2499 | unsigned char cval; | |
2500 | ||
2501 | switch (c_cflag & CSIZE) { | |
2502 | case CS5: | |
2503 | cval = UART_LCR_WLEN5; | |
2504 | break; | |
2505 | case CS6: | |
2506 | cval = UART_LCR_WLEN6; | |
2507 | break; | |
2508 | case CS7: | |
2509 | cval = UART_LCR_WLEN7; | |
2510 | break; | |
2511 | default: | |
2512 | case CS8: | |
2513 | cval = UART_LCR_WLEN8; | |
2514 | break; | |
2515 | } | |
2516 | ||
2517 | if (c_cflag & CSTOPB) | |
2518 | cval |= UART_LCR_STOP; | |
2519 | if (c_cflag & PARENB) { | |
2520 | cval |= UART_LCR_PARITY; | |
2521 | if (up->bugs & UART_BUG_PARITY) | |
2522 | up->fifo_bug = true; | |
2523 | } | |
2524 | if (!(c_cflag & PARODD)) | |
2525 | cval |= UART_LCR_EPAR; | |
2526 | #ifdef CMSPAR | |
2527 | if (c_cflag & CMSPAR) | |
2528 | cval |= UART_LCR_SPAR; | |
2529 | #endif | |
2530 | ||
2531 | return cval; | |
2532 | } | |
2533 | ||
2534 | static void serial8250_set_divisor(struct uart_port *port, unsigned int baud, | |
2535 | unsigned int quot, unsigned int quot_frac) | |
2536 | { | |
2537 | struct uart_8250_port *up = up_to_u8250p(port); | |
2538 | ||
2539 | /* Workaround to enable 115200 baud on OMAP1510 internal ports */ | |
2540 | if (is_omap1510_8250(up)) { | |
2541 | if (baud == 115200) { | |
2542 | quot = 1; | |
2543 | serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1); | |
2544 | } else | |
2545 | serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0); | |
2546 | } | |
2547 | ||
2548 | /* | |
2549 | * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2, | |
2550 | * otherwise just set DLAB | |
2551 | */ | |
2552 | if (up->capabilities & UART_NATSEMI) | |
2553 | serial_port_out(port, UART_LCR, 0xe0); | |
2554 | else | |
2555 | serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB); | |
2556 | ||
2557 | serial_dl_write(up, quot); | |
2558 | ||
2559 | /* XR17V35x UARTs have an extra fractional divisor register (DLD) */ | |
2560 | if (up->port.type == PORT_XR17V35X) | |
2561 | serial_port_out(port, 0x2, quot_frac); | |
2562 | } | |
2563 | ||
b3d67936 AW |
2564 | static unsigned int serial8250_get_baud_rate(struct uart_port *port, |
2565 | struct ktermios *termios, | |
2566 | struct ktermios *old) | |
4f56f3fd | 2567 | { |
4f56f3fd JH |
2568 | /* |
2569 | * Ask the core to calculate the divisor for us. | |
2570 | * Allow 1% tolerance at the upper limit so uart clks marginally | |
2571 | * slower than nominal still match standard baud rates without | |
2572 | * causing transmission errors. | |
2573 | */ | |
2574 | return uart_get_baud_rate(port, termios, old, | |
2575 | port->uartclk / 16 / 0xffff, | |
81bb549f | 2576 | port->uartclk); |
4f56f3fd JH |
2577 | } |
2578 | ||
b6830f6d PH |
2579 | void |
2580 | serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, | |
6d7c157f | 2581 | struct ktermios *old) |
b6830f6d PH |
2582 | { |
2583 | struct uart_8250_port *up = up_to_u8250p(port); | |
2584 | unsigned char cval; | |
2585 | unsigned long flags; | |
2586 | unsigned int baud, quot, frac = 0; | |
2587 | ||
2588 | cval = serial8250_compute_lcr(up, termios->c_cflag); | |
2589 | ||
4f56f3fd | 2590 | baud = serial8250_get_baud_rate(port, termios, old); |
b6830f6d PH |
2591 | quot = serial8250_get_divisor(up, baud, &frac); |
2592 | ||
2593 | /* | |
2594 | * Ok, we're now changing the port state. Do it with | |
2595 | * interrupts disabled. | |
2596 | */ | |
2597 | serial8250_rpm_get(up); | |
2598 | spin_lock_irqsave(&port->lock, flags); | |
2599 | ||
2600 | up->lcr = cval; /* Save computed LCR */ | |
2601 | ||
2602 | if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { | |
2603 | /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */ | |
2604 | if ((baud < 2400 && !up->dma) || up->fifo_bug) { | |
2605 | up->fcr &= ~UART_FCR_TRIGGER_MASK; | |
2606 | up->fcr |= UART_FCR_TRIGGER_1; | |
2607 | } | |
2608 | } | |
2609 | ||
2610 | /* | |
2611 | * MCR-based auto flow control. When AFE is enabled, RTS will be | |
2612 | * deasserted when the receive FIFO contains more characters than | |
68af490b | 2613 | * the trigger, or the MCR RTS bit is cleared. |
b6830f6d | 2614 | */ |
68af490b | 2615 | if (up->capabilities & UART_CAP_AFE) { |
b6830f6d PH |
2616 | up->mcr &= ~UART_MCR_AFE; |
2617 | if (termios->c_cflag & CRTSCTS) | |
2618 | up->mcr |= UART_MCR_AFE; | |
2619 | } | |
2620 | ||
2621 | /* | |
2622 | * Update the per-port timeout. | |
2623 | */ | |
2624 | uart_update_timeout(port, termios->c_cflag, baud); | |
2625 | ||
2626 | port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
2627 | if (termios->c_iflag & INPCK) | |
2628 | port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
2629 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) | |
2630 | port->read_status_mask |= UART_LSR_BI; | |
2631 | ||
2632 | /* | |
2633 | * Characteres to ignore | |
2634 | */ | |
2635 | port->ignore_status_mask = 0; | |
2636 | if (termios->c_iflag & IGNPAR) | |
2637 | port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
2638 | if (termios->c_iflag & IGNBRK) { | |
2639 | port->ignore_status_mask |= UART_LSR_BI; | |
2640 | /* | |
2641 | * If we're ignoring parity and break indicators, | |
2642 | * ignore overruns too (for real raw support). | |
2643 | */ | |
2644 | if (termios->c_iflag & IGNPAR) | |
2645 | port->ignore_status_mask |= UART_LSR_OE; | |
2646 | } | |
2647 | ||
2648 | /* | |
2649 | * ignore all characters if CREAD is not set | |
2650 | */ | |
2651 | if ((termios->c_cflag & CREAD) == 0) | |
2652 | port->ignore_status_mask |= UART_LSR_DR; | |
2653 | ||
2654 | /* | |
2655 | * CTS flow control flag and modem status interrupts | |
2656 | */ | |
2657 | up->ier &= ~UART_IER_MSI; | |
2658 | if (!(up->bugs & UART_BUG_NOMSR) && | |
2659 | UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
2660 | up->ier |= UART_IER_MSI; | |
2661 | if (up->capabilities & UART_CAP_UUE) | |
2662 | up->ier |= UART_IER_UUE; | |
2663 | if (up->capabilities & UART_CAP_RTOIE) | |
2664 | up->ier |= UART_IER_RTOIE; | |
2665 | ||
2666 | serial_port_out(port, UART_IER, up->ier); | |
2667 | ||
2668 | if (up->capabilities & UART_CAP_EFR) { | |
2669 | unsigned char efr = 0; | |
2670 | /* | |
2671 | * TI16C752/Startech hardware flow control. FIXME: | |
2672 | * - TI16C752 requires control thresholds to be set. | |
2673 | * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. | |
2674 | */ | |
2675 | if (termios->c_cflag & CRTSCTS) | |
2676 | efr |= UART_EFR_CTS; | |
2677 | ||
2678 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); | |
2679 | if (port->flags & UPF_EXAR_EFR) | |
2680 | serial_port_out(port, UART_XR_EFR, efr); | |
2681 | else | |
2682 | serial_port_out(port, UART_EFR, efr); | |
2683 | } | |
2684 | ||
2685 | serial8250_set_divisor(port, baud, quot, frac); | |
2686 | ||
2687 | /* | |
2688 | * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR | |
2689 | * is written without DLAB set, this mode will be disabled. | |
2690 | */ | |
2691 | if (port->type == PORT_16750) | |
2692 | serial_port_out(port, UART_FCR, up->fcr); | |
2693 | ||
2694 | serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */ | |
2695 | if (port->type != PORT_16750) { | |
2696 | /* emulated UARTs (Lucent Venus 167x) need two steps */ | |
2697 | if (up->fcr & UART_FCR_ENABLE_FIFO) | |
2698 | serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO); | |
2699 | serial_port_out(port, UART_FCR, up->fcr); /* set fcr */ | |
2700 | } | |
2701 | serial8250_set_mctrl(port, port->mctrl); | |
2702 | spin_unlock_irqrestore(&port->lock, flags); | |
2703 | serial8250_rpm_put(up); | |
2704 | ||
2705 | /* Don't rewrite B0 */ | |
2706 | if (tty_termios_baud_rate(termios)) | |
2707 | tty_termios_encode_baud_rate(termios, baud, baud); | |
2708 | } | |
2709 | EXPORT_SYMBOL(serial8250_do_set_termios); | |
2710 | ||
2711 | static void | |
2712 | serial8250_set_termios(struct uart_port *port, struct ktermios *termios, | |
2713 | struct ktermios *old) | |
2714 | { | |
2715 | if (port->set_termios) | |
2716 | port->set_termios(port, termios, old); | |
2717 | else | |
2718 | serial8250_do_set_termios(port, termios, old); | |
2719 | } | |
2720 | ||
db405a8f | 2721 | void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios) |
b6830f6d PH |
2722 | { |
2723 | if (termios->c_line == N_PPS) { | |
2724 | port->flags |= UPF_HARDPPS_CD; | |
2725 | spin_lock_irq(&port->lock); | |
2726 | serial8250_enable_ms(port); | |
2727 | spin_unlock_irq(&port->lock); | |
2728 | } else { | |
2729 | port->flags &= ~UPF_HARDPPS_CD; | |
2730 | if (!UART_ENABLE_MS(port, termios->c_cflag)) { | |
2731 | spin_lock_irq(&port->lock); | |
2732 | serial8250_disable_ms(port); | |
2733 | spin_unlock_irq(&port->lock); | |
2734 | } | |
2735 | } | |
2736 | } | |
db405a8f | 2737 | EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc); |
b6830f6d | 2738 | |
db405a8f EB |
2739 | static void |
2740 | serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios) | |
2741 | { | |
2742 | if (port->set_ldisc) | |
2743 | port->set_ldisc(port, termios); | |
2744 | else | |
2745 | serial8250_do_set_ldisc(port, termios); | |
2746 | } | |
b6830f6d PH |
2747 | |
2748 | void serial8250_do_pm(struct uart_port *port, unsigned int state, | |
2749 | unsigned int oldstate) | |
2750 | { | |
2751 | struct uart_8250_port *p = up_to_u8250p(port); | |
2752 | ||
2753 | serial8250_set_sleep(p, state != 0); | |
2754 | } | |
2755 | EXPORT_SYMBOL(serial8250_do_pm); | |
2756 | ||
2757 | static void | |
2758 | serial8250_pm(struct uart_port *port, unsigned int state, | |
2759 | unsigned int oldstate) | |
2760 | { | |
2761 | if (port->pm) | |
2762 | port->pm(port, state, oldstate); | |
2763 | else | |
2764 | serial8250_do_pm(port, state, oldstate); | |
2765 | } | |
2766 | ||
2767 | static unsigned int serial8250_port_size(struct uart_8250_port *pt) | |
2768 | { | |
2769 | if (pt->port.mapsize) | |
2770 | return pt->port.mapsize; | |
2771 | if (pt->port.iotype == UPIO_AU) { | |
2772 | if (pt->port.type == PORT_RT2880) | |
2773 | return 0x100; | |
2774 | return 0x1000; | |
2775 | } | |
2776 | if (is_omap1_8250(pt)) | |
2777 | return 0x16 << pt->port.regshift; | |
2778 | ||
2779 | return 8 << pt->port.regshift; | |
2780 | } | |
2781 | ||
2782 | /* | |
2783 | * Resource handling. | |
2784 | */ | |
2785 | static int serial8250_request_std_resource(struct uart_8250_port *up) | |
2786 | { | |
2787 | unsigned int size = serial8250_port_size(up); | |
2788 | struct uart_port *port = &up->port; | |
2789 | int ret = 0; | |
2790 | ||
2791 | switch (port->iotype) { | |
2792 | case UPIO_AU: | |
2793 | case UPIO_TSI: | |
2794 | case UPIO_MEM32: | |
2795 | case UPIO_MEM32BE: | |
bd94c407 | 2796 | case UPIO_MEM16: |
b6830f6d PH |
2797 | case UPIO_MEM: |
2798 | if (!port->mapbase) | |
2799 | break; | |
2800 | ||
2801 | if (!request_mem_region(port->mapbase, size, "serial")) { | |
2802 | ret = -EBUSY; | |
2803 | break; | |
2804 | } | |
2805 | ||
2806 | if (port->flags & UPF_IOREMAP) { | |
2807 | port->membase = ioremap_nocache(port->mapbase, size); | |
2808 | if (!port->membase) { | |
2809 | release_mem_region(port->mapbase, size); | |
2810 | ret = -ENOMEM; | |
2811 | } | |
2812 | } | |
2813 | break; | |
2814 | ||
2815 | case UPIO_HUB6: | |
2816 | case UPIO_PORT: | |
2817 | if (!request_region(port->iobase, size, "serial")) | |
2818 | ret = -EBUSY; | |
2819 | break; | |
2820 | } | |
2821 | return ret; | |
2822 | } | |
2823 | ||
2824 | static void serial8250_release_std_resource(struct uart_8250_port *up) | |
2825 | { | |
2826 | unsigned int size = serial8250_port_size(up); | |
2827 | struct uart_port *port = &up->port; | |
2828 | ||
2829 | switch (port->iotype) { | |
2830 | case UPIO_AU: | |
2831 | case UPIO_TSI: | |
2832 | case UPIO_MEM32: | |
2833 | case UPIO_MEM32BE: | |
bd94c407 | 2834 | case UPIO_MEM16: |
b6830f6d PH |
2835 | case UPIO_MEM: |
2836 | if (!port->mapbase) | |
2837 | break; | |
2838 | ||
2839 | if (port->flags & UPF_IOREMAP) { | |
2840 | iounmap(port->membase); | |
2841 | port->membase = NULL; | |
2842 | } | |
2843 | ||
2844 | release_mem_region(port->mapbase, size); | |
2845 | break; | |
2846 | ||
2847 | case UPIO_HUB6: | |
2848 | case UPIO_PORT: | |
2849 | release_region(port->iobase, size); | |
2850 | break; | |
2851 | } | |
2852 | } | |
2853 | ||
2854 | static void serial8250_release_port(struct uart_port *port) | |
2855 | { | |
2856 | struct uart_8250_port *up = up_to_u8250p(port); | |
2857 | ||
2858 | serial8250_release_std_resource(up); | |
2859 | } | |
2860 | ||
2861 | static int serial8250_request_port(struct uart_port *port) | |
2862 | { | |
2863 | struct uart_8250_port *up = up_to_u8250p(port); | |
b6830f6d | 2864 | |
e4fda3a0 | 2865 | return serial8250_request_std_resource(up); |
b6830f6d PH |
2866 | } |
2867 | ||
2868 | static int fcr_get_rxtrig_bytes(struct uart_8250_port *up) | |
2869 | { | |
2870 | const struct serial8250_config *conf_type = &uart_config[up->port.type]; | |
2871 | unsigned char bytes; | |
2872 | ||
2873 | bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)]; | |
2874 | ||
2875 | return bytes ? bytes : -EOPNOTSUPP; | |
2876 | } | |
2877 | ||
2878 | static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes) | |
2879 | { | |
2880 | const struct serial8250_config *conf_type = &uart_config[up->port.type]; | |
2881 | int i; | |
2882 | ||
2883 | if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)]) | |
2884 | return -EOPNOTSUPP; | |
2885 | ||
2886 | for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) { | |
2887 | if (bytes < conf_type->rxtrig_bytes[i]) | |
2888 | /* Use the nearest lower value */ | |
2889 | return (--i) << UART_FCR_R_TRIG_SHIFT; | |
2890 | } | |
2891 | ||
2892 | return UART_FCR_R_TRIG_11; | |
2893 | } | |
2894 | ||
2895 | static int do_get_rxtrig(struct tty_port *port) | |
2896 | { | |
2897 | struct uart_state *state = container_of(port, struct uart_state, port); | |
2898 | struct uart_port *uport = state->uart_port; | |
013e3586 | 2899 | struct uart_8250_port *up = up_to_u8250p(uport); |
b6830f6d PH |
2900 | |
2901 | if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) | |
2902 | return -EINVAL; | |
2903 | ||
2904 | return fcr_get_rxtrig_bytes(up); | |
2905 | } | |
2906 | ||
2907 | static int do_serial8250_get_rxtrig(struct tty_port *port) | |
2908 | { | |
2909 | int rxtrig_bytes; | |
2910 | ||
2911 | mutex_lock(&port->mutex); | |
2912 | rxtrig_bytes = do_get_rxtrig(port); | |
2913 | mutex_unlock(&port->mutex); | |
2914 | ||
2915 | return rxtrig_bytes; | |
2916 | } | |
2917 | ||
2918 | static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev, | |
2919 | struct device_attribute *attr, char *buf) | |
2920 | { | |
2921 | struct tty_port *port = dev_get_drvdata(dev); | |
2922 | int rxtrig_bytes; | |
2923 | ||
2924 | rxtrig_bytes = do_serial8250_get_rxtrig(port); | |
2925 | if (rxtrig_bytes < 0) | |
2926 | return rxtrig_bytes; | |
2927 | ||
2928 | return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes); | |
2929 | } | |
2930 | ||
2931 | static int do_set_rxtrig(struct tty_port *port, unsigned char bytes) | |
2932 | { | |
2933 | struct uart_state *state = container_of(port, struct uart_state, port); | |
2934 | struct uart_port *uport = state->uart_port; | |
013e3586 | 2935 | struct uart_8250_port *up = up_to_u8250p(uport); |
b6830f6d PH |
2936 | int rxtrig; |
2937 | ||
2938 | if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 || | |
2939 | up->fifo_bug) | |
2940 | return -EINVAL; | |
2941 | ||
2942 | rxtrig = bytes_to_fcr_rxtrig(up, bytes); | |
2943 | if (rxtrig < 0) | |
2944 | return rxtrig; | |
2945 | ||
2946 | serial8250_clear_fifos(up); | |
2947 | up->fcr &= ~UART_FCR_TRIGGER_MASK; | |
2948 | up->fcr |= (unsigned char)rxtrig; | |
2949 | serial_out(up, UART_FCR, up->fcr); | |
2950 | return 0; | |
2951 | } | |
2952 | ||
2953 | static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes) | |
2954 | { | |
2955 | int ret; | |
2956 | ||
2957 | mutex_lock(&port->mutex); | |
2958 | ret = do_set_rxtrig(port, bytes); | |
2959 | mutex_unlock(&port->mutex); | |
2960 | ||
2961 | return ret; | |
2962 | } | |
2963 | ||
2964 | static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev, | |
2965 | struct device_attribute *attr, const char *buf, size_t count) | |
2966 | { | |
2967 | struct tty_port *port = dev_get_drvdata(dev); | |
2968 | unsigned char bytes; | |
2969 | int ret; | |
2970 | ||
2971 | if (!count) | |
2972 | return -EINVAL; | |
2973 | ||
2974 | ret = kstrtou8(buf, 10, &bytes); | |
2975 | if (ret < 0) | |
2976 | return ret; | |
2977 | ||
2978 | ret = do_serial8250_set_rxtrig(port, bytes); | |
2979 | if (ret < 0) | |
2980 | return ret; | |
2981 | ||
2982 | return count; | |
2983 | } | |
2984 | ||
2985 | static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP, | |
2986 | serial8250_get_attr_rx_trig_bytes, | |
2987 | serial8250_set_attr_rx_trig_bytes); | |
2988 | ||
2989 | static struct attribute *serial8250_dev_attrs[] = { | |
2990 | &dev_attr_rx_trig_bytes.attr, | |
2991 | NULL, | |
2992 | }; | |
2993 | ||
2994 | static struct attribute_group serial8250_dev_attr_group = { | |
2995 | .attrs = serial8250_dev_attrs, | |
2996 | }; | |
2997 | ||
2998 | static void register_dev_spec_attr_grp(struct uart_8250_port *up) | |
2999 | { | |
3000 | const struct serial8250_config *conf_type = &uart_config[up->port.type]; | |
3001 | ||
3002 | if (conf_type->rxtrig_bytes[0]) | |
3003 | up->port.attr_group = &serial8250_dev_attr_group; | |
3004 | } | |
3005 | ||
3006 | static void serial8250_config_port(struct uart_port *port, int flags) | |
3007 | { | |
3008 | struct uart_8250_port *up = up_to_u8250p(port); | |
3009 | int ret; | |
3010 | ||
b6830f6d PH |
3011 | /* |
3012 | * Find the region that we can probe for. This in turn | |
3013 | * tells us whether we can probe for the type of port. | |
3014 | */ | |
3015 | ret = serial8250_request_std_resource(up); | |
3016 | if (ret < 0) | |
3017 | return; | |
3018 | ||
3019 | if (port->iotype != up->cur_iotype) | |
3020 | set_io_from_upio(port); | |
3021 | ||
3022 | if (flags & UART_CONFIG_TYPE) | |
3023 | autoconfig(up); | |
3024 | ||
3025 | /* if access method is AU, it is a 16550 with a quirk */ | |
3026 | if (port->type == PORT_16550A && port->iotype == UPIO_AU) | |
3027 | up->bugs |= UART_BUG_NOMSR; | |
3028 | ||
3029 | /* HW bugs may trigger IRQ while IIR == NO_INT */ | |
3030 | if (port->type == PORT_TEGRA) | |
3031 | up->bugs |= UART_BUG_NOMSR; | |
3032 | ||
3033 | if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) | |
3034 | autoconfig_irq(up); | |
3035 | ||
3036 | if (port->type == PORT_UNKNOWN) | |
3037 | serial8250_release_std_resource(up); | |
3038 | ||
3039 | /* Fixme: probably not the best place for this */ | |
3040 | if ((port->type == PORT_XR17V35X) || | |
3041 | (port->type == PORT_XR17D15X)) | |
3042 | port->handle_irq = exar_handle_irq; | |
3043 | ||
3044 | register_dev_spec_attr_grp(up); | |
3045 | up->fcr = uart_config[up->port.type].fcr; | |
3046 | } | |
3047 | ||
3048 | static int | |
3049 | serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) | |
3050 | { | |
3051 | if (ser->irq >= nr_irqs || ser->irq < 0 || | |
3052 | ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || | |
3053 | ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || | |
3054 | ser->type == PORT_STARTECH) | |
3055 | return -EINVAL; | |
3056 | return 0; | |
3057 | } | |
3058 | ||
cee10c8c | 3059 | static const char *serial8250_type(struct uart_port *port) |
b6830f6d PH |
3060 | { |
3061 | int type = port->type; | |
3062 | ||
3063 | if (type >= ARRAY_SIZE(uart_config)) | |
3064 | type = 0; | |
3065 | return uart_config[type].name; | |
3066 | } | |
3067 | ||
3068 | static const struct uart_ops serial8250_pops = { | |
3069 | .tx_empty = serial8250_tx_empty, | |
3070 | .set_mctrl = serial8250_set_mctrl, | |
3071 | .get_mctrl = serial8250_get_mctrl, | |
3072 | .stop_tx = serial8250_stop_tx, | |
3073 | .start_tx = serial8250_start_tx, | |
3074 | .throttle = serial8250_throttle, | |
3075 | .unthrottle = serial8250_unthrottle, | |
3076 | .stop_rx = serial8250_stop_rx, | |
3077 | .enable_ms = serial8250_enable_ms, | |
3078 | .break_ctl = serial8250_break_ctl, | |
3079 | .startup = serial8250_startup, | |
3080 | .shutdown = serial8250_shutdown, | |
3081 | .set_termios = serial8250_set_termios, | |
3082 | .set_ldisc = serial8250_set_ldisc, | |
3083 | .pm = serial8250_pm, | |
3084 | .type = serial8250_type, | |
3085 | .release_port = serial8250_release_port, | |
3086 | .request_port = serial8250_request_port, | |
3087 | .config_port = serial8250_config_port, | |
3088 | .verify_port = serial8250_verify_port, | |
3089 | #ifdef CONFIG_CONSOLE_POLL | |
3090 | .poll_get_char = serial8250_get_poll_char, | |
3091 | .poll_put_char = serial8250_put_poll_char, | |
3092 | #endif | |
3093 | }; | |
3094 | ||
3095 | void serial8250_init_port(struct uart_8250_port *up) | |
3096 | { | |
3097 | struct uart_port *port = &up->port; | |
3098 | ||
3099 | spin_lock_init(&port->lock); | |
3100 | port->ops = &serial8250_pops; | |
3101 | ||
3102 | up->cur_iotype = 0xFF; | |
3103 | } | |
3104 | EXPORT_SYMBOL_GPL(serial8250_init_port); | |
3105 | ||
3106 | void serial8250_set_defaults(struct uart_8250_port *up) | |
3107 | { | |
3108 | struct uart_port *port = &up->port; | |
3109 | ||
3110 | if (up->port.flags & UPF_FIXED_TYPE) { | |
3111 | unsigned int type = up->port.type; | |
3112 | ||
3113 | if (!up->port.fifosize) | |
3114 | up->port.fifosize = uart_config[type].fifo_size; | |
3115 | if (!up->tx_loadsz) | |
3116 | up->tx_loadsz = uart_config[type].tx_loadsz; | |
3117 | if (!up->capabilities) | |
3118 | up->capabilities = uart_config[type].flags; | |
3119 | } | |
3120 | ||
3121 | set_io_from_upio(port); | |
3122 | ||
3123 | /* default dma handlers */ | |
3124 | if (up->dma) { | |
3125 | if (!up->dma->tx_dma) | |
3126 | up->dma->tx_dma = serial8250_tx_dma; | |
3127 | if (!up->dma->rx_dma) | |
3128 | up->dma->rx_dma = serial8250_rx_dma; | |
3129 | } | |
3130 | } | |
3131 | EXPORT_SYMBOL_GPL(serial8250_set_defaults); | |
3132 | ||
3133 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
3134 | ||
3135 | static void serial8250_console_putchar(struct uart_port *port, int ch) | |
3136 | { | |
3137 | struct uart_8250_port *up = up_to_u8250p(port); | |
3138 | ||
3139 | wait_for_xmitr(up, UART_LSR_THRE); | |
3140 | serial_port_out(port, UART_TX, ch); | |
3141 | } | |
3142 | ||
10791233 PH |
3143 | /* |
3144 | * Restore serial console when h/w power-off detected | |
3145 | */ | |
3146 | static void serial8250_console_restore(struct uart_8250_port *up) | |
3147 | { | |
3148 | struct uart_port *port = &up->port; | |
3149 | struct ktermios termios; | |
3150 | unsigned int baud, quot, frac = 0; | |
3151 | ||
3152 | termios.c_cflag = port->cons->cflag; | |
3153 | if (port->state->port.tty && termios.c_cflag == 0) | |
3154 | termios.c_cflag = port->state->port.tty->termios.c_cflag; | |
3155 | ||
3156 | baud = serial8250_get_baud_rate(port, &termios, NULL); | |
3157 | quot = serial8250_get_divisor(up, baud, &frac); | |
3158 | ||
3159 | serial8250_set_divisor(port, baud, quot, frac); | |
3160 | serial_port_out(port, UART_LCR, up->lcr); | |
36fd95b1 | 3161 | serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS); |
10791233 PH |
3162 | } |
3163 | ||
b6830f6d PH |
3164 | /* |
3165 | * Print a string to the serial port trying not to disturb | |
3166 | * any possible real use of the port... | |
3167 | * | |
3168 | * The console_lock must be held when we get here. | |
3169 | */ | |
3170 | void serial8250_console_write(struct uart_8250_port *up, const char *s, | |
3171 | unsigned int count) | |
3172 | { | |
3173 | struct uart_port *port = &up->port; | |
3174 | unsigned long flags; | |
3175 | unsigned int ier; | |
3176 | int locked = 1; | |
3177 | ||
3178 | touch_nmi_watchdog(); | |
3179 | ||
3180 | serial8250_rpm_get(up); | |
3181 | ||
3182 | if (port->sysrq) | |
3183 | locked = 0; | |
3184 | else if (oops_in_progress) | |
3185 | locked = spin_trylock_irqsave(&port->lock, flags); | |
3186 | else | |
3187 | spin_lock_irqsave(&port->lock, flags); | |
3188 | ||
3189 | /* | |
3190 | * First save the IER then disable the interrupts | |
3191 | */ | |
3192 | ier = serial_port_in(port, UART_IER); | |
3193 | ||
3194 | if (up->capabilities & UART_CAP_UUE) | |
3195 | serial_port_out(port, UART_IER, UART_IER_UUE); | |
3196 | else | |
3197 | serial_port_out(port, UART_IER, 0); | |
3198 | ||
3199 | /* check scratch reg to see if port powered off during system sleep */ | |
3200 | if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) { | |
10791233 | 3201 | serial8250_console_restore(up); |
b6830f6d PH |
3202 | up->canary = 0; |
3203 | } | |
3204 | ||
3205 | uart_console_write(port, s, count, serial8250_console_putchar); | |
3206 | ||
3207 | /* | |
3208 | * Finally, wait for transmitter to become empty | |
3209 | * and restore the IER | |
3210 | */ | |
3211 | wait_for_xmitr(up, BOTH_EMPTY); | |
3212 | serial_port_out(port, UART_IER, ier); | |
3213 | ||
3214 | /* | |
3215 | * The receive handling will happen properly because the | |
3216 | * receive ready bit will still be set; it is not cleared | |
3217 | * on read. However, modem control will not, we must | |
3218 | * call it if we have saved something in the saved flags | |
3219 | * while processing with interrupts off. | |
3220 | */ | |
3221 | if (up->msr_saved_flags) | |
3222 | serial8250_modem_status(up); | |
3223 | ||
3224 | if (locked) | |
3225 | spin_unlock_irqrestore(&port->lock, flags); | |
3226 | serial8250_rpm_put(up); | |
3227 | } | |
3228 | ||
3229 | static unsigned int probe_baud(struct uart_port *port) | |
3230 | { | |
3231 | unsigned char lcr, dll, dlm; | |
3232 | unsigned int quot; | |
3233 | ||
3234 | lcr = serial_port_in(port, UART_LCR); | |
3235 | serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB); | |
3236 | dll = serial_port_in(port, UART_DLL); | |
3237 | dlm = serial_port_in(port, UART_DLM); | |
3238 | serial_port_out(port, UART_LCR, lcr); | |
3239 | ||
3240 | quot = (dlm << 8) | dll; | |
3241 | return (port->uartclk / 16) / quot; | |
3242 | } | |
3243 | ||
3244 | int serial8250_console_setup(struct uart_port *port, char *options, bool probe) | |
3245 | { | |
3246 | int baud = 9600; | |
3247 | int bits = 8; | |
3248 | int parity = 'n'; | |
3249 | int flow = 'n'; | |
3250 | ||
3251 | if (!port->iobase && !port->membase) | |
3252 | return -ENODEV; | |
3253 | ||
3254 | if (options) | |
3255 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
3256 | else if (probe) | |
3257 | baud = probe_baud(port); | |
3258 | ||
3259 | return uart_set_options(port, port->cons, baud, parity, bits, flow); | |
3260 | } | |
3261 | ||
3262 | #endif /* CONFIG_SERIAL_8250_CONSOLE */ | |
f7a7651f JM |
3263 | |
3264 | MODULE_LICENSE("GPL"); |