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1/*
2 * altera_uart.c -- Altera UART driver
3 *
4 * Based on mcf.c -- Freescale ColdFire UART driver
5 *
6 * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
7 * (C) Copyright 2008, Thomas Chou <thomas@wytron.com.tw>
8 * (C) Copyright 2010, Tobias Klauser <tklauser@distanz.ch>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
2f8b9c15 18#include <linux/timer.h>
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19#include <linux/interrupt.h>
20#include <linux/module.h>
21#include <linux/console.h>
22#include <linux/tty.h>
23#include <linux/tty_flip.h>
24#include <linux/serial.h>
25#include <linux/serial_core.h>
26#include <linux/platform_device.h>
7c9325d7 27#include <linux/of.h>
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28#include <linux/io.h>
29#include <linux/altera_uart.h>
30
31#define DRV_NAME "altera_uart"
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32#define SERIAL_ALTERA_MAJOR 204
33#define SERIAL_ALTERA_MINOR 213
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34
35/*
36 * Altera UART register definitions according to the Nios UART datasheet:
37 * http://www.altera.com/literature/ds/ds_nios_uart.pdf
38 */
39
40#define ALTERA_UART_SIZE 32
41
42#define ALTERA_UART_RXDATA_REG 0
43#define ALTERA_UART_TXDATA_REG 4
44#define ALTERA_UART_STATUS_REG 8
45#define ALTERA_UART_CONTROL_REG 12
46#define ALTERA_UART_DIVISOR_REG 16
47#define ALTERA_UART_EOP_REG 20
48
49#define ALTERA_UART_STATUS_PE_MSK 0x0001 /* parity error */
50#define ALTERA_UART_STATUS_FE_MSK 0x0002 /* framing error */
51#define ALTERA_UART_STATUS_BRK_MSK 0x0004 /* break */
52#define ALTERA_UART_STATUS_ROE_MSK 0x0008 /* RX overrun error */
53#define ALTERA_UART_STATUS_TOE_MSK 0x0010 /* TX overrun error */
54#define ALTERA_UART_STATUS_TMT_MSK 0x0020 /* TX shift register state */
55#define ALTERA_UART_STATUS_TRDY_MSK 0x0040 /* TX ready */
56#define ALTERA_UART_STATUS_RRDY_MSK 0x0080 /* RX ready */
57#define ALTERA_UART_STATUS_E_MSK 0x0100 /* exception condition */
58#define ALTERA_UART_STATUS_DCTS_MSK 0x0400 /* CTS logic-level change */
59#define ALTERA_UART_STATUS_CTS_MSK 0x0800 /* CTS logic state */
60#define ALTERA_UART_STATUS_EOP_MSK 0x1000 /* EOP written/read */
61
62 /* Enable interrupt on... */
63#define ALTERA_UART_CONTROL_PE_MSK 0x0001 /* ...parity error */
64#define ALTERA_UART_CONTROL_FE_MSK 0x0002 /* ...framing error */
65#define ALTERA_UART_CONTROL_BRK_MSK 0x0004 /* ...break */
66#define ALTERA_UART_CONTROL_ROE_MSK 0x0008 /* ...RX overrun */
67#define ALTERA_UART_CONTROL_TOE_MSK 0x0010 /* ...TX overrun */
68#define ALTERA_UART_CONTROL_TMT_MSK 0x0020 /* ...TX shift register empty */
69#define ALTERA_UART_CONTROL_TRDY_MSK 0x0040 /* ...TX ready */
70#define ALTERA_UART_CONTROL_RRDY_MSK 0x0080 /* ...RX ready */
71#define ALTERA_UART_CONTROL_E_MSK 0x0100 /* ...exception*/
72
73#define ALTERA_UART_CONTROL_TRBK_MSK 0x0200 /* TX break */
74#define ALTERA_UART_CONTROL_DCTS_MSK 0x0400 /* Interrupt on CTS change */
75#define ALTERA_UART_CONTROL_RTS_MSK 0x0800 /* RTS signal */
76#define ALTERA_UART_CONTROL_EOP_MSK 0x1000 /* Interrupt on EOP */
77
78/*
79 * Local per-uart structure.
80 */
81struct altera_uart {
82 struct uart_port port;
2f8b9c15 83 struct timer_list tmr;
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84 unsigned int sigs; /* Local copy of line sigs */
85 unsigned short imr; /* Local IMR mirror */
86};
87
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88static u32 altera_uart_readl(struct uart_port *port, int reg)
89{
2780ad42 90 return readl(port->membase + (reg << port->regshift));
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91}
92
93static void altera_uart_writel(struct uart_port *port, u32 dat, int reg)
94{
2780ad42 95 writel(dat, port->membase + (reg << port->regshift));
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96}
97
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98static unsigned int altera_uart_tx_empty(struct uart_port *port)
99{
0d426eda 100 return (altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
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101 ALTERA_UART_STATUS_TMT_MSK) ? TIOCSER_TEMT : 0;
102}
103
104static unsigned int altera_uart_get_mctrl(struct uart_port *port)
105{
106 struct altera_uart *pp = container_of(port, struct altera_uart, port);
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107 unsigned int sigs;
108
0d426eda 109 sigs = (altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
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110 ALTERA_UART_STATUS_CTS_MSK) ? TIOCM_CTS : 0;
111 sigs |= (pp->sigs & TIOCM_RTS);
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112
113 return sigs;
114}
115
116static void altera_uart_set_mctrl(struct uart_port *port, unsigned int sigs)
117{
118 struct altera_uart *pp = container_of(port, struct altera_uart, port);
6b7d8f8b 119
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120 pp->sigs = sigs;
121 if (sigs & TIOCM_RTS)
122 pp->imr |= ALTERA_UART_CONTROL_RTS_MSK;
123 else
124 pp->imr &= ~ALTERA_UART_CONTROL_RTS_MSK;
0d426eda 125 altera_uart_writel(port, pp->imr, ALTERA_UART_CONTROL_REG);
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126}
127
128static void altera_uart_start_tx(struct uart_port *port)
129{
130 struct altera_uart *pp = container_of(port, struct altera_uart, port);
6b7d8f8b 131
6b7d8f8b 132 pp->imr |= ALTERA_UART_CONTROL_TRDY_MSK;
0d426eda 133 altera_uart_writel(port, pp->imr, ALTERA_UART_CONTROL_REG);
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134}
135
136static void altera_uart_stop_tx(struct uart_port *port)
137{
138 struct altera_uart *pp = container_of(port, struct altera_uart, port);
6b7d8f8b 139
6b7d8f8b 140 pp->imr &= ~ALTERA_UART_CONTROL_TRDY_MSK;
0d426eda 141 altera_uart_writel(port, pp->imr, ALTERA_UART_CONTROL_REG);
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142}
143
144static void altera_uart_stop_rx(struct uart_port *port)
145{
146 struct altera_uart *pp = container_of(port, struct altera_uart, port);
6b7d8f8b 147
6b7d8f8b 148 pp->imr &= ~ALTERA_UART_CONTROL_RRDY_MSK;
0d426eda 149 altera_uart_writel(port, pp->imr, ALTERA_UART_CONTROL_REG);
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150}
151
152static void altera_uart_break_ctl(struct uart_port *port, int break_state)
153{
154 struct altera_uart *pp = container_of(port, struct altera_uart, port);
155 unsigned long flags;
156
157 spin_lock_irqsave(&port->lock, flags);
158 if (break_state == -1)
159 pp->imr |= ALTERA_UART_CONTROL_TRBK_MSK;
160 else
161 pp->imr &= ~ALTERA_UART_CONTROL_TRBK_MSK;
0d426eda 162 altera_uart_writel(port, pp->imr, ALTERA_UART_CONTROL_REG);
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163 spin_unlock_irqrestore(&port->lock, flags);
164}
165
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166static void altera_uart_set_termios(struct uart_port *port,
167 struct ktermios *termios,
168 struct ktermios *old)
169{
170 unsigned long flags;
171 unsigned int baud, baudclk;
172
173 baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
174 baudclk = port->uartclk / baud;
175
176 if (old)
177 tty_termios_copy_hw(termios, old);
178 tty_termios_encode_baud_rate(termios, baud, baud);
179
180 spin_lock_irqsave(&port->lock, flags);
2f8b9c15 181 uart_update_timeout(port, termios->c_cflag, baud);
0d426eda 182 altera_uart_writel(port, baudclk, ALTERA_UART_DIVISOR_REG);
6b7d8f8b 183 spin_unlock_irqrestore(&port->lock, flags);
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184
185 /*
186 * FIXME: port->read_status_mask and port->ignore_status_mask
187 * need to be initialized based on termios settings for
188 * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT
189 */
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190}
191
192static void altera_uart_rx_chars(struct altera_uart *pp)
193{
194 struct uart_port *port = &pp->port;
195 unsigned char ch, flag;
196 unsigned short status;
197
0d426eda 198 while ((status = altera_uart_readl(port, ALTERA_UART_STATUS_REG)) &
6b7d8f8b 199 ALTERA_UART_STATUS_RRDY_MSK) {
0d426eda 200 ch = altera_uart_readl(port, ALTERA_UART_RXDATA_REG);
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201 flag = TTY_NORMAL;
202 port->icount.rx++;
203
204 if (status & ALTERA_UART_STATUS_E_MSK) {
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205 altera_uart_writel(port, status,
206 ALTERA_UART_STATUS_REG);
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207
208 if (status & ALTERA_UART_STATUS_BRK_MSK) {
209 port->icount.brk++;
210 if (uart_handle_break(port))
211 continue;
212 } else if (status & ALTERA_UART_STATUS_PE_MSK) {
213 port->icount.parity++;
214 } else if (status & ALTERA_UART_STATUS_ROE_MSK) {
215 port->icount.overrun++;
216 } else if (status & ALTERA_UART_STATUS_FE_MSK) {
217 port->icount.frame++;
218 }
219
220 status &= port->read_status_mask;
221
222 if (status & ALTERA_UART_STATUS_BRK_MSK)
223 flag = TTY_BREAK;
224 else if (status & ALTERA_UART_STATUS_PE_MSK)
225 flag = TTY_PARITY;
226 else if (status & ALTERA_UART_STATUS_FE_MSK)
227 flag = TTY_FRAME;
228 }
229
230 if (uart_handle_sysrq_char(port, ch))
231 continue;
232 uart_insert_char(port, status, ALTERA_UART_STATUS_ROE_MSK, ch,
233 flag);
234 }
235
dd085ed8 236 spin_unlock(&port->lock);
2e124b4a 237 tty_flip_buffer_push(&port->state->port);
dd085ed8 238 spin_lock(&port->lock);
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239}
240
241static void altera_uart_tx_chars(struct altera_uart *pp)
242{
243 struct uart_port *port = &pp->port;
244 struct circ_buf *xmit = &port->state->xmit;
245
246 if (port->x_char) {
247 /* Send special char - probably flow control */
0d426eda 248 altera_uart_writel(port, port->x_char, ALTERA_UART_TXDATA_REG);
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249 port->x_char = 0;
250 port->icount.tx++;
251 return;
252 }
253
0d426eda 254 while (altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
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255 ALTERA_UART_STATUS_TRDY_MSK) {
256 if (xmit->head == xmit->tail)
257 break;
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258 altera_uart_writel(port, xmit->buf[xmit->tail],
259 ALTERA_UART_TXDATA_REG);
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260 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
261 port->icount.tx++;
262 }
263
264 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
265 uart_write_wakeup(port);
266
267 if (xmit->head == xmit->tail) {
268 pp->imr &= ~ALTERA_UART_CONTROL_TRDY_MSK;
0d426eda 269 altera_uart_writel(port, pp->imr, ALTERA_UART_CONTROL_REG);
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270 }
271}
272
273static irqreturn_t altera_uart_interrupt(int irq, void *data)
274{
275 struct uart_port *port = data;
276 struct altera_uart *pp = container_of(port, struct altera_uart, port);
277 unsigned int isr;
278
0d426eda 279 isr = altera_uart_readl(port, ALTERA_UART_STATUS_REG) & pp->imr;
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280
281 spin_lock(&port->lock);
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282 if (isr & ALTERA_UART_STATUS_RRDY_MSK)
283 altera_uart_rx_chars(pp);
284 if (isr & ALTERA_UART_STATUS_TRDY_MSK)
285 altera_uart_tx_chars(pp);
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286 spin_unlock(&port->lock);
287
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288 return IRQ_RETVAL(isr);
289}
290
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291static void altera_uart_timer(unsigned long data)
292{
293 struct uart_port *port = (void *)data;
294 struct altera_uart *pp = container_of(port, struct altera_uart, port);
295
296 altera_uart_interrupt(0, port);
297 mod_timer(&pp->tmr, jiffies + uart_poll_timeout(port));
298}
299
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300static void altera_uart_config_port(struct uart_port *port, int flags)
301{
302 port->type = PORT_ALTERA_UART;
303
304 /* Clear mask, so no surprise interrupts. */
0d426eda 305 altera_uart_writel(port, 0, ALTERA_UART_CONTROL_REG);
6b7d8f8b 306 /* Clear status register */
0d426eda 307 altera_uart_writel(port, 0, ALTERA_UART_STATUS_REG);
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308}
309
310static int altera_uart_startup(struct uart_port *port)
311{
312 struct altera_uart *pp = container_of(port, struct altera_uart, port);
313 unsigned long flags;
314 int ret;
315
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316 if (!port->irq) {
317 setup_timer(&pp->tmr, altera_uart_timer, (unsigned long)port);
318 mod_timer(&pp->tmr, jiffies + uart_poll_timeout(port));
319 return 0;
320 }
321
9cfb5c05 322 ret = request_irq(port->irq, altera_uart_interrupt, 0,
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323 DRV_NAME, port);
324 if (ret) {
325 pr_err(DRV_NAME ": unable to attach Altera UART %d "
326 "interrupt vector=%d\n", port->line, port->irq);
327 return ret;
328 }
329
330 spin_lock_irqsave(&port->lock, flags);
331
332 /* Enable RX interrupts now */
333 pp->imr = ALTERA_UART_CONTROL_RRDY_MSK;
334 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG);
335
336 spin_unlock_irqrestore(&port->lock, flags);
337
338 return 0;
339}
340
341static void altera_uart_shutdown(struct uart_port *port)
342{
343 struct altera_uart *pp = container_of(port, struct altera_uart, port);
344 unsigned long flags;
345
346 spin_lock_irqsave(&port->lock, flags);
347
348 /* Disable all interrupts now */
349 pp->imr = 0;
350 writel(pp->imr, port->membase + ALTERA_UART_CONTROL_REG);
351
352 spin_unlock_irqrestore(&port->lock, flags);
353
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354 if (port->irq)
355 free_irq(port->irq, port);
356 else
357 del_timer_sync(&pp->tmr);
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358}
359
360static const char *altera_uart_type(struct uart_port *port)
361{
362 return (port->type == PORT_ALTERA_UART) ? "Altera UART" : NULL;
363}
364
365static int altera_uart_request_port(struct uart_port *port)
366{
367 /* UARTs always present */
368 return 0;
369}
370
371static void altera_uart_release_port(struct uart_port *port)
372{
373 /* Nothing to release... */
374}
375
376static int altera_uart_verify_port(struct uart_port *port,
377 struct serial_struct *ser)
378{
379 if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_ALTERA_UART))
380 return -EINVAL;
381 return 0;
382}
383
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384#ifdef CONFIG_CONSOLE_POLL
385static int altera_uart_poll_get_char(struct uart_port *port)
386{
387 while (!(altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
388 ALTERA_UART_STATUS_RRDY_MSK))
389 cpu_relax();
390
391 return altera_uart_readl(port, ALTERA_UART_RXDATA_REG);
392}
393
394static void altera_uart_poll_put_char(struct uart_port *port, unsigned char c)
395{
396 while (!(altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
397 ALTERA_UART_STATUS_TRDY_MSK))
398 cpu_relax();
399
400 altera_uart_writel(port, c, ALTERA_UART_TXDATA_REG);
401}
402#endif
403
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404/*
405 * Define the basic serial functions we support.
406 */
03bd797f 407static const struct uart_ops altera_uart_ops = {
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408 .tx_empty = altera_uart_tx_empty,
409 .get_mctrl = altera_uart_get_mctrl,
410 .set_mctrl = altera_uart_set_mctrl,
411 .start_tx = altera_uart_start_tx,
412 .stop_tx = altera_uart_stop_tx,
413 .stop_rx = altera_uart_stop_rx,
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414 .break_ctl = altera_uart_break_ctl,
415 .startup = altera_uart_startup,
416 .shutdown = altera_uart_shutdown,
417 .set_termios = altera_uart_set_termios,
418 .type = altera_uart_type,
419 .request_port = altera_uart_request_port,
420 .release_port = altera_uart_release_port,
421 .config_port = altera_uart_config_port,
422 .verify_port = altera_uart_verify_port,
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423#ifdef CONFIG_CONSOLE_POLL
424 .poll_get_char = altera_uart_poll_get_char,
425 .poll_put_char = altera_uart_poll_put_char,
426#endif
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427};
428
429static struct altera_uart altera_uart_ports[CONFIG_SERIAL_ALTERA_UART_MAXPORTS];
430
431#if defined(CONFIG_SERIAL_ALTERA_UART_CONSOLE)
432
2970b7f5 433static void altera_uart_console_putc(struct uart_port *port, int c)
6b7d8f8b 434{
0d426eda 435 while (!(altera_uart_readl(port, ALTERA_UART_STATUS_REG) &
e8dd4757 436 ALTERA_UART_STATUS_TRDY_MSK))
fadf34f0 437 cpu_relax();
6b7d8f8b 438
6b7d8f8b 439 writel(c, port->membase + ALTERA_UART_TXDATA_REG);
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440}
441
442static void altera_uart_console_write(struct console *co, const char *s,
443 unsigned int count)
444{
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445 struct uart_port *port = &(altera_uart_ports + co->index)->port;
446
2970b7f5 447 uart_console_write(port, s, count, altera_uart_console_putc);
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448}
449
450static int __init altera_uart_console_setup(struct console *co, char *options)
451{
452 struct uart_port *port;
453 int baud = CONFIG_SERIAL_ALTERA_UART_BAUDRATE;
454 int bits = 8;
455 int parity = 'n';
456 int flow = 'n';
457
458 if (co->index < 0 || co->index >= CONFIG_SERIAL_ALTERA_UART_MAXPORTS)
459 return -EINVAL;
460 port = &altera_uart_ports[co->index].port;
70eebd0b 461 if (!port->membase)
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462 return -ENODEV;
463
464 if (options)
465 uart_parse_options(options, &baud, &parity, &bits, &flow);
466
467 return uart_set_options(port, co, baud, parity, bits, flow);
468}
469
470static struct uart_driver altera_uart_driver;
471
472static struct console altera_uart_console = {
99793c66 473 .name = "ttyAL",
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474 .write = altera_uart_console_write,
475 .device = uart_console_device,
476 .setup = altera_uart_console_setup,
477 .flags = CON_PRINTBUFFER,
478 .index = -1,
479 .data = &altera_uart_driver,
480};
481
482static int __init altera_uart_console_init(void)
483{
484 register_console(&altera_uart_console);
485 return 0;
486}
487
488console_initcall(altera_uart_console_init);
489
490#define ALTERA_UART_CONSOLE (&altera_uart_console)
491
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492static void altera_uart_earlycon_write(struct console *co, const char *s,
493 unsigned int count)
494{
495 struct earlycon_device *dev = co->data;
496
497 uart_console_write(&dev->port, s, count, altera_uart_console_putc);
498}
499
500static int __init altera_uart_earlycon_setup(struct earlycon_device *dev,
501 const char *options)
502{
503 struct uart_port *port = &dev->port;
504
505 if (!port->membase)
506 return -ENODEV;
507
508 /* Enable RX interrupts now */
509 writel(ALTERA_UART_CONTROL_RRDY_MSK,
510 port->membase + ALTERA_UART_CONTROL_REG);
511
512 if (dev->baud) {
513 unsigned int baudclk = port->uartclk / dev->baud;
514
515 writel(baudclk, port->membase + ALTERA_UART_DIVISOR_REG);
516 }
517
518 dev->con->write = altera_uart_earlycon_write;
519 return 0;
520}
521
522OF_EARLYCON_DECLARE(uart, "altr,uart-1.0", altera_uart_earlycon_setup);
523
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524#else
525
526#define ALTERA_UART_CONSOLE NULL
527
0656b1a9 528#endif /* CONFIG_SERIAL_ALTERA_UART_CONSOLE */
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529
530/*
531 * Define the altera_uart UART driver structure.
532 */
533static struct uart_driver altera_uart_driver = {
534 .owner = THIS_MODULE,
535 .driver_name = DRV_NAME,
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536 .dev_name = "ttyAL",
537 .major = SERIAL_ALTERA_MAJOR,
538 .minor = SERIAL_ALTERA_MINOR,
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539 .nr = CONFIG_SERIAL_ALTERA_UART_MAXPORTS,
540 .cons = ALTERA_UART_CONSOLE,
541};
542
9671f099 543static int altera_uart_probe(struct platform_device *pdev)
6b7d8f8b 544{
574de559 545 struct altera_uart_platform_uart *platp = dev_get_platdata(&pdev->dev);
6b7d8f8b 546 struct uart_port *port;
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547 struct resource *res_mem;
548 struct resource *res_irq;
549 int i = pdev->id;
7c9325d7 550 int ret;
6b7d8f8b 551
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552 /* if id is -1 scan for a free id and use that one */
553 if (i == -1) {
554 for (i = 0; i < CONFIG_SERIAL_ALTERA_UART_MAXPORTS; i++)
555 if (altera_uart_ports[i].port.mapbase == 0)
556 break;
557 }
6b7d8f8b 558
a664ec96 559 if (i < 0 || i >= CONFIG_SERIAL_ALTERA_UART_MAXPORTS)
6b5756f1 560 return -EINVAL;
6b7d8f8b 561
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562 port = &altera_uart_ports[i].port;
563
564 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
565 if (res_mem)
566 port->mapbase = res_mem->start;
acede70d 567 else if (platp)
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568 port->mapbase = platp->mapbase;
569 else
570 return -EINVAL;
571
572 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
573 if (res_irq)
574 port->irq = res_irq->start;
acede70d 575 else if (platp)
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576 port->irq = platp->irq;
577
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578 /* Check platform data first so we can override device node data */
579 if (platp)
580 port->uartclk = platp->uartclk;
581 else {
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582 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency",
583 &port->uartclk);
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584 if (ret)
585 return ret;
586 }
587
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588 port->membase = ioremap(port->mapbase, ALTERA_UART_SIZE);
589 if (!port->membase)
590 return -ENOMEM;
591
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592 if (platp)
593 port->regshift = platp->bus_shift;
594 else
595 port->regshift = 0;
596
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597 port->line = i;
598 port->type = PORT_ALTERA_UART;
599 port->iotype = SERIAL_IO_MEM;
6b5756f1 600 port->ops = &altera_uart_ops;
288e9feb 601 port->flags = UPF_BOOT_AUTOCONF;
b820cd76 602 port->dev = &pdev->dev;
6b5756f1 603
1a16afa2 604 platform_set_drvdata(pdev, port);
a664ec96 605
6b5756f1 606 uart_add_one_port(&altera_uart_driver, port);
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607
608 return 0;
609}
610
ae8d8a14 611static int altera_uart_remove(struct platform_device *pdev)
6b7d8f8b 612{
1a16afa2 613 struct uart_port *port = platform_get_drvdata(pdev);
6b7d8f8b 614
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TK
615 if (port) {
616 uart_remove_one_port(&altera_uart_driver, port);
a664ec96 617 port->mapbase = 0;
59fe2cc8 618 iounmap(port->membase);
a664ec96 619 }
e96fabd8 620
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621 return 0;
622}
623
7c9325d7 624#ifdef CONFIG_OF
4d199a55 625static const struct of_device_id altera_uart_match[] = {
7c9325d7 626 { .compatible = "ALTR,uart-1.0", },
13960b47 627 { .compatible = "altr,uart-1.0", },
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628 {},
629};
630MODULE_DEVICE_TABLE(of, altera_uart_match);
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631#endif /* CONFIG_OF */
632
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633static struct platform_driver altera_uart_platform_driver = {
634 .probe = altera_uart_probe,
2d47b716 635 .remove = altera_uart_remove,
6b7d8f8b 636 .driver = {
7c9325d7 637 .name = DRV_NAME,
85888069 638 .of_match_table = of_match_ptr(altera_uart_match),
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639 },
640};
641
642static int __init altera_uart_init(void)
643{
644 int rc;
645
646 rc = uart_register_driver(&altera_uart_driver);
647 if (rc)
648 return rc;
649 rc = platform_driver_register(&altera_uart_platform_driver);
61bc6559 650 if (rc)
6b7d8f8b 651 uart_unregister_driver(&altera_uart_driver);
61bc6559 652 return rc;
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TK
653}
654
655static void __exit altera_uart_exit(void)
656{
657 platform_driver_unregister(&altera_uart_platform_driver);
658 uart_unregister_driver(&altera_uart_driver);
659}
660
661module_init(altera_uart_init);
662module_exit(altera_uart_exit);
663
664MODULE_DESCRIPTION("Altera UART driver");
665MODULE_AUTHOR("Thomas Chou <thomas@wytron.com.tw>");
666MODULE_LICENSE("GPL");
667MODULE_ALIAS("platform:" DRV_NAME);
99793c66 668MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_ALTERA_MAJOR);