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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for AMBA serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 8 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
1da177e4 LT |
24 | * This is a generic driver for ARM AMBA-type serial ports. They |
25 | * have a lot of 16550-like features, but are not register compatible. | |
26 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
27 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
28 | * required, these have to be supplied via some other means (eg, GPIO) | |
29 | * and hooked into this driver. | |
30 | */ | |
1da177e4 | 31 | |
cb06ff10 | 32 | |
1da177e4 LT |
33 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
34 | #define SUPPORT_SYSRQ | |
35 | #endif | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/console.h> | |
41 | #include <linux/sysrq.h> | |
42 | #include <linux/device.h> | |
43 | #include <linux/tty.h> | |
44 | #include <linux/tty_flip.h> | |
45 | #include <linux/serial_core.h> | |
46 | #include <linux/serial.h> | |
a62c80e5 RK |
47 | #include <linux/amba/bus.h> |
48 | #include <linux/amba/serial.h> | |
f8ce2547 | 49 | #include <linux/clk.h> |
5a0e3ad6 | 50 | #include <linux/slab.h> |
68b65f73 RK |
51 | #include <linux/dmaengine.h> |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/scatterlist.h> | |
c16d51a3 | 54 | #include <linux/delay.h> |
258aea76 | 55 | #include <linux/types.h> |
32614aad ML |
56 | #include <linux/of.h> |
57 | #include <linux/of_device.h> | |
258e0551 | 58 | #include <linux/pinctrl/consumer.h> |
cb70706c | 59 | #include <linux/sizes.h> |
de609582 | 60 | #include <linux/io.h> |
3db9ab0b | 61 | #include <linux/acpi.h> |
1da177e4 | 62 | |
9f25bc51 RK |
63 | #include "amba-pl011.h" |
64 | ||
1da177e4 LT |
65 | #define UART_NR 14 |
66 | ||
67 | #define SERIAL_AMBA_MAJOR 204 | |
68 | #define SERIAL_AMBA_MINOR 64 | |
69 | #define SERIAL_AMBA_NR UART_NR | |
70 | ||
71 | #define AMBA_ISR_PASS_LIMIT 256 | |
72 | ||
b63d4f0f RK |
73 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
74 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 75 | |
debb7f64 RK |
76 | static u16 pl011_std_offsets[REG_ARRAY_SIZE] = { |
77 | [REG_DR] = UART01x_DR, | |
debb7f64 | 78 | [REG_FR] = UART01x_FR, |
e4df9a80 RK |
79 | [REG_LCRH_RX] = UART011_LCRH, |
80 | [REG_LCRH_TX] = UART011_LCRH, | |
debb7f64 RK |
81 | [REG_IBRD] = UART011_IBRD, |
82 | [REG_FBRD] = UART011_FBRD, | |
debb7f64 RK |
83 | [REG_CR] = UART011_CR, |
84 | [REG_IFLS] = UART011_IFLS, | |
85 | [REG_IMSC] = UART011_IMSC, | |
86 | [REG_RIS] = UART011_RIS, | |
87 | [REG_MIS] = UART011_MIS, | |
88 | [REG_ICR] = UART011_ICR, | |
89 | [REG_DMACR] = UART011_DMACR, | |
debb7f64 RK |
90 | }; |
91 | ||
5926a295 AR |
92 | /* There is by now at least one vendor with differing details, so handle it */ |
93 | struct vendor_data { | |
439403bd | 94 | const u16 *reg_offset; |
5926a295 | 95 | unsigned int ifls; |
ac3e3fb4 | 96 | bool oversampling; |
38d62436 | 97 | bool dma_threshold; |
4fd0690b | 98 | bool cts_event_workaround; |
71eec483 | 99 | bool always_enabled; |
cefc2d1d | 100 | bool fixed_options; |
78506f22 | 101 | |
ea33640a | 102 | unsigned int (*get_fifosize)(struct amba_device *dev); |
5926a295 AR |
103 | }; |
104 | ||
ea33640a | 105 | static unsigned int get_fifosize_arm(struct amba_device *dev) |
78506f22 | 106 | { |
ea33640a | 107 | return amba_rev(dev) < 3 ? 16 : 32; |
78506f22 JK |
108 | } |
109 | ||
5926a295 | 110 | static struct vendor_data vendor_arm = { |
439403bd | 111 | .reg_offset = pl011_std_offsets, |
5926a295 | 112 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, |
ac3e3fb4 | 113 | .oversampling = false, |
38d62436 | 114 | .dma_threshold = false, |
4fd0690b | 115 | .cts_event_workaround = false, |
71eec483 | 116 | .always_enabled = false, |
cefc2d1d | 117 | .fixed_options = false, |
78506f22 | 118 | .get_fifosize = get_fifosize_arm, |
5926a295 AR |
119 | }; |
120 | ||
0dd1e247 | 121 | static struct vendor_data vendor_sbsa = { |
439403bd | 122 | .reg_offset = pl011_std_offsets, |
0dd1e247 AP |
123 | .oversampling = false, |
124 | .dma_threshold = false, | |
125 | .cts_event_workaround = false, | |
126 | .always_enabled = true, | |
127 | .fixed_options = true, | |
128 | }; | |
129 | ||
bf69ff8a RK |
130 | static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { |
131 | [REG_DR] = UART01x_DR, | |
132 | [REG_ST_DMAWM] = ST_UART011_DMAWM, | |
133 | [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, | |
134 | [REG_FR] = UART01x_FR, | |
e4df9a80 RK |
135 | [REG_LCRH_RX] = ST_UART011_LCRH_RX, |
136 | [REG_LCRH_TX] = ST_UART011_LCRH_TX, | |
bf69ff8a RK |
137 | [REG_IBRD] = UART011_IBRD, |
138 | [REG_FBRD] = UART011_FBRD, | |
bf69ff8a RK |
139 | [REG_CR] = UART011_CR, |
140 | [REG_IFLS] = UART011_IFLS, | |
141 | [REG_IMSC] = UART011_IMSC, | |
142 | [REG_RIS] = UART011_RIS, | |
143 | [REG_MIS] = UART011_MIS, | |
144 | [REG_ICR] = UART011_ICR, | |
145 | [REG_DMACR] = UART011_DMACR, | |
146 | [REG_ST_XFCR] = ST_UART011_XFCR, | |
147 | [REG_ST_XON1] = ST_UART011_XON1, | |
148 | [REG_ST_XON2] = ST_UART011_XON2, | |
149 | [REG_ST_XOFF1] = ST_UART011_XOFF1, | |
150 | [REG_ST_XOFF2] = ST_UART011_XOFF2, | |
151 | [REG_ST_ITCR] = ST_UART011_ITCR, | |
152 | [REG_ST_ITIP] = ST_UART011_ITIP, | |
153 | [REG_ST_ABCR] = ST_UART011_ABCR, | |
154 | [REG_ST_ABIMSC] = ST_UART011_ABIMSC, | |
155 | }; | |
156 | ||
ea33640a | 157 | static unsigned int get_fifosize_st(struct amba_device *dev) |
78506f22 JK |
158 | { |
159 | return 64; | |
160 | } | |
161 | ||
5926a295 | 162 | static struct vendor_data vendor_st = { |
bf69ff8a | 163 | .reg_offset = pl011_st_offsets, |
5926a295 | 164 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, |
ac3e3fb4 | 165 | .oversampling = true, |
38d62436 | 166 | .dma_threshold = true, |
4fd0690b | 167 | .cts_event_workaround = true, |
71eec483 | 168 | .always_enabled = false, |
cefc2d1d | 169 | .fixed_options = false, |
78506f22 | 170 | .get_fifosize = get_fifosize_st, |
1da177e4 LT |
171 | }; |
172 | ||
68b65f73 | 173 | /* Deals with DMA transactions */ |
ead76f32 LW |
174 | |
175 | struct pl011_sgbuf { | |
176 | struct scatterlist sg; | |
177 | char *buf; | |
178 | }; | |
179 | ||
180 | struct pl011_dmarx_data { | |
181 | struct dma_chan *chan; | |
182 | struct completion complete; | |
183 | bool use_buf_b; | |
184 | struct pl011_sgbuf sgbuf_a; | |
185 | struct pl011_sgbuf sgbuf_b; | |
186 | dma_cookie_t cookie; | |
187 | bool running; | |
cb06ff10 CM |
188 | struct timer_list timer; |
189 | unsigned int last_residue; | |
190 | unsigned long last_jiffies; | |
191 | bool auto_poll_rate; | |
192 | unsigned int poll_rate; | |
193 | unsigned int poll_timeout; | |
ead76f32 LW |
194 | }; |
195 | ||
68b65f73 RK |
196 | struct pl011_dmatx_data { |
197 | struct dma_chan *chan; | |
198 | struct scatterlist sg; | |
199 | char *buf; | |
200 | bool queued; | |
201 | }; | |
202 | ||
c19f12b5 RK |
203 | /* |
204 | * We wrap our port structure around the generic uart_port. | |
205 | */ | |
206 | struct uart_amba_port { | |
207 | struct uart_port port; | |
debb7f64 | 208 | const u16 *reg_offset; |
c19f12b5 RK |
209 | struct clk *clk; |
210 | const struct vendor_data *vendor; | |
68b65f73 | 211 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
212 | unsigned int im; /* interrupt mask */ |
213 | unsigned int old_status; | |
ffca2b11 | 214 | unsigned int fifosize; /* vendor-specific */ |
d8d8ffa4 | 215 | unsigned int old_cr; /* state during shutdown */ |
c19f12b5 | 216 | bool autorts; |
cefc2d1d | 217 | unsigned int fixed_baud; /* vendor-set fixed baud rate */ |
c19f12b5 | 218 | char type[12]; |
68b65f73 RK |
219 | #ifdef CONFIG_DMA_ENGINE |
220 | /* DMA stuff */ | |
ead76f32 LW |
221 | bool using_tx_dma; |
222 | bool using_rx_dma; | |
223 | struct pl011_dmarx_data dmarx; | |
68b65f73 | 224 | struct pl011_dmatx_data dmatx; |
1c9be310 | 225 | bool dma_probed; |
68b65f73 RK |
226 | #endif |
227 | }; | |
228 | ||
9f25bc51 RK |
229 | static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap, |
230 | unsigned int reg) | |
231 | { | |
debb7f64 | 232 | return uap->reg_offset[reg]; |
9f25bc51 RK |
233 | } |
234 | ||
b2a4e24c RK |
235 | static unsigned int pl011_read(const struct uart_amba_port *uap, |
236 | unsigned int reg) | |
75836339 | 237 | { |
9f25bc51 | 238 | return readw(uap->port.membase + pl011_reg_to_offset(uap, reg)); |
75836339 RK |
239 | } |
240 | ||
b2a4e24c RK |
241 | static void pl011_write(unsigned int val, const struct uart_amba_port *uap, |
242 | unsigned int reg) | |
75836339 | 243 | { |
9f25bc51 | 244 | writew(val, uap->port.membase + pl011_reg_to_offset(uap, reg)); |
75836339 RK |
245 | } |
246 | ||
29772c4e LW |
247 | /* |
248 | * Reads up to 256 characters from the FIFO or until it's empty and | |
249 | * inserts them into the TTY layer. Returns the number of characters | |
250 | * read from the FIFO. | |
251 | */ | |
252 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
253 | { | |
71a5cd8a TT |
254 | u16 status; |
255 | unsigned int ch, flag, max_count = 256; | |
29772c4e LW |
256 | int fifotaken = 0; |
257 | ||
258 | while (max_count--) { | |
9f25bc51 | 259 | status = pl011_read(uap, REG_FR); |
29772c4e LW |
260 | if (status & UART01x_FR_RXFE) |
261 | break; | |
262 | ||
263 | /* Take chars from the FIFO and update status */ | |
9f25bc51 | 264 | ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX; |
29772c4e LW |
265 | flag = TTY_NORMAL; |
266 | uap->port.icount.rx++; | |
267 | fifotaken++; | |
268 | ||
269 | if (unlikely(ch & UART_DR_ERROR)) { | |
270 | if (ch & UART011_DR_BE) { | |
271 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
272 | uap->port.icount.brk++; | |
273 | if (uart_handle_break(&uap->port)) | |
274 | continue; | |
275 | } else if (ch & UART011_DR_PE) | |
276 | uap->port.icount.parity++; | |
277 | else if (ch & UART011_DR_FE) | |
278 | uap->port.icount.frame++; | |
279 | if (ch & UART011_DR_OE) | |
280 | uap->port.icount.overrun++; | |
281 | ||
282 | ch &= uap->port.read_status_mask; | |
283 | ||
284 | if (ch & UART011_DR_BE) | |
285 | flag = TTY_BREAK; | |
286 | else if (ch & UART011_DR_PE) | |
287 | flag = TTY_PARITY; | |
288 | else if (ch & UART011_DR_FE) | |
289 | flag = TTY_FRAME; | |
290 | } | |
291 | ||
292 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
293 | continue; | |
294 | ||
295 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
296 | } | |
297 | ||
298 | return fifotaken; | |
299 | } | |
300 | ||
301 | ||
68b65f73 RK |
302 | /* |
303 | * All the DMA operation mode stuff goes inside this ifdef. | |
304 | * This assumes that you have a generic DMA device interface, | |
305 | * no custom DMA interfaces are supported. | |
306 | */ | |
307 | #ifdef CONFIG_DMA_ENGINE | |
308 | ||
309 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
310 | ||
ead76f32 LW |
311 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
312 | enum dma_data_direction dir) | |
313 | { | |
cb06ff10 CM |
314 | dma_addr_t dma_addr; |
315 | ||
316 | sg->buf = dma_alloc_coherent(chan->device->dev, | |
317 | PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); | |
ead76f32 LW |
318 | if (!sg->buf) |
319 | return -ENOMEM; | |
320 | ||
cb06ff10 CM |
321 | sg_init_table(&sg->sg, 1); |
322 | sg_set_page(&sg->sg, phys_to_page(dma_addr), | |
323 | PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); | |
324 | sg_dma_address(&sg->sg) = dma_addr; | |
c64be923 | 325 | sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE; |
ead76f32 | 326 | |
ead76f32 LW |
327 | return 0; |
328 | } | |
329 | ||
330 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
331 | enum dma_data_direction dir) | |
332 | { | |
333 | if (sg->buf) { | |
cb06ff10 CM |
334 | dma_free_coherent(chan->device->dev, |
335 | PL011_DMA_BUFFER_SIZE, sg->buf, | |
336 | sg_dma_address(&sg->sg)); | |
ead76f32 LW |
337 | } |
338 | } | |
339 | ||
1c9be310 | 340 | static void pl011_dma_probe(struct uart_amba_port *uap) |
68b65f73 RK |
341 | { |
342 | /* DMA is the sole user of the platform data right now */ | |
574de559 | 343 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); |
1c9be310 | 344 | struct device *dev = uap->port.dev; |
68b65f73 | 345 | struct dma_slave_config tx_conf = { |
9f25bc51 RK |
346 | .dst_addr = uap->port.mapbase + |
347 | pl011_reg_to_offset(uap, REG_DR), | |
68b65f73 | 348 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, |
a485df4b | 349 | .direction = DMA_MEM_TO_DEV, |
68b65f73 | 350 | .dst_maxburst = uap->fifosize >> 1, |
258aea76 | 351 | .device_fc = false, |
68b65f73 RK |
352 | }; |
353 | struct dma_chan *chan; | |
354 | dma_cap_mask_t mask; | |
355 | ||
1c9be310 JRO |
356 | uap->dma_probed = true; |
357 | chan = dma_request_slave_channel_reason(dev, "tx"); | |
358 | if (IS_ERR(chan)) { | |
359 | if (PTR_ERR(chan) == -EPROBE_DEFER) { | |
1c9be310 JRO |
360 | uap->dma_probed = false; |
361 | return; | |
362 | } | |
68b65f73 | 363 | |
787b0c1f AB |
364 | /* We need platform data */ |
365 | if (!plat || !plat->dma_filter) { | |
366 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
367 | return; | |
368 | } | |
369 | ||
370 | /* Try to acquire a generic DMA engine slave TX channel */ | |
371 | dma_cap_zero(mask); | |
372 | dma_cap_set(DMA_SLAVE, mask); | |
373 | ||
374 | chan = dma_request_channel(mask, plat->dma_filter, | |
375 | plat->dma_tx_param); | |
376 | if (!chan) { | |
377 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
378 | return; | |
379 | } | |
68b65f73 RK |
380 | } |
381 | ||
382 | dmaengine_slave_config(chan, &tx_conf); | |
383 | uap->dmatx.chan = chan; | |
384 | ||
385 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
386 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
387 | |
388 | /* Optionally make use of an RX channel as well */ | |
787b0c1f | 389 | chan = dma_request_slave_channel(dev, "rx"); |
0d3c673e | 390 | |
787b0c1f AB |
391 | if (!chan && plat->dma_rx_param) { |
392 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); | |
393 | ||
394 | if (!chan) { | |
395 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
396 | return; | |
397 | } | |
398 | } | |
399 | ||
400 | if (chan) { | |
ead76f32 | 401 | struct dma_slave_config rx_conf = { |
9f25bc51 RK |
402 | .src_addr = uap->port.mapbase + |
403 | pl011_reg_to_offset(uap, REG_DR), | |
ead76f32 | 404 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, |
a485df4b | 405 | .direction = DMA_DEV_TO_MEM, |
b2aeb775 | 406 | .src_maxburst = uap->fifosize >> 2, |
258aea76 | 407 | .device_fc = false, |
ead76f32 | 408 | }; |
2d3b7d6e AJ |
409 | struct dma_slave_caps caps; |
410 | ||
411 | /* | |
412 | * Some DMA controllers provide information on their capabilities. | |
413 | * If the controller does, check for suitable residue processing | |
414 | * otherwise assime all is well. | |
415 | */ | |
416 | if (0 == dma_get_slave_caps(chan, &caps)) { | |
417 | if (caps.residue_granularity == | |
418 | DMA_RESIDUE_GRANULARITY_DESCRIPTOR) { | |
419 | dma_release_channel(chan); | |
420 | dev_info(uap->port.dev, | |
421 | "RX DMA disabled - no residue processing\n"); | |
422 | return; | |
423 | } | |
424 | } | |
ead76f32 LW |
425 | dmaengine_slave_config(chan, &rx_conf); |
426 | uap->dmarx.chan = chan; | |
427 | ||
98267d33 | 428 | uap->dmarx.auto_poll_rate = false; |
8f898bfd | 429 | if (plat && plat->dma_rx_poll_enable) { |
cb06ff10 CM |
430 | /* Set poll rate if specified. */ |
431 | if (plat->dma_rx_poll_rate) { | |
432 | uap->dmarx.auto_poll_rate = false; | |
433 | uap->dmarx.poll_rate = plat->dma_rx_poll_rate; | |
434 | } else { | |
435 | /* | |
436 | * 100 ms defaults to poll rate if not | |
437 | * specified. This will be adjusted with | |
438 | * the baud rate at set_termios. | |
439 | */ | |
440 | uap->dmarx.auto_poll_rate = true; | |
441 | uap->dmarx.poll_rate = 100; | |
442 | } | |
443 | /* 3 secs defaults poll_timeout if not specified. */ | |
444 | if (plat->dma_rx_poll_timeout) | |
445 | uap->dmarx.poll_timeout = | |
446 | plat->dma_rx_poll_timeout; | |
447 | else | |
448 | uap->dmarx.poll_timeout = 3000; | |
98267d33 AJ |
449 | } else if (!plat && dev->of_node) { |
450 | uap->dmarx.auto_poll_rate = of_property_read_bool( | |
451 | dev->of_node, "auto-poll"); | |
452 | if (uap->dmarx.auto_poll_rate) { | |
453 | u32 x; | |
454 | ||
455 | if (0 == of_property_read_u32(dev->of_node, | |
456 | "poll-rate-ms", &x)) | |
457 | uap->dmarx.poll_rate = x; | |
458 | else | |
459 | uap->dmarx.poll_rate = 100; | |
460 | if (0 == of_property_read_u32(dev->of_node, | |
461 | "poll-timeout-ms", &x)) | |
462 | uap->dmarx.poll_timeout = x; | |
463 | else | |
464 | uap->dmarx.poll_timeout = 3000; | |
465 | } | |
466 | } | |
ead76f32 LW |
467 | dev_info(uap->port.dev, "DMA channel RX %s\n", |
468 | dma_chan_name(uap->dmarx.chan)); | |
469 | } | |
68b65f73 RK |
470 | } |
471 | ||
68b65f73 RK |
472 | static void pl011_dma_remove(struct uart_amba_port *uap) |
473 | { | |
68b65f73 RK |
474 | if (uap->dmatx.chan) |
475 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
476 | if (uap->dmarx.chan) |
477 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
478 | } |
479 | ||
734745ca | 480 | /* Forward declare these for the refill routine */ |
68b65f73 | 481 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); |
734745ca | 482 | static void pl011_start_tx_pio(struct uart_amba_port *uap); |
68b65f73 RK |
483 | |
484 | /* | |
485 | * The current DMA TX buffer has been sent. | |
486 | * Try to queue up another DMA buffer. | |
487 | */ | |
488 | static void pl011_dma_tx_callback(void *data) | |
489 | { | |
490 | struct uart_amba_port *uap = data; | |
491 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
492 | unsigned long flags; | |
493 | u16 dmacr; | |
494 | ||
495 | spin_lock_irqsave(&uap->port.lock, flags); | |
496 | if (uap->dmatx.queued) | |
497 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
498 | DMA_TO_DEVICE); | |
499 | ||
500 | dmacr = uap->dmacr; | |
501 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
9f25bc51 | 502 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
503 | |
504 | /* | |
505 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
506 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
507 | * | |
508 | * Note: we need to be careful here of a potential race between DMA | |
509 | * and the rest of the driver - if the driver disables TX DMA while | |
510 | * a TX buffer completing, we must update the tx queued status to | |
511 | * get further refills (hence we check dmacr). | |
512 | */ | |
513 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
514 | uart_circ_empty(&uap->port.state->xmit)) { | |
515 | uap->dmatx.queued = false; | |
516 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
517 | return; | |
518 | } | |
519 | ||
734745ca | 520 | if (pl011_dma_tx_refill(uap) <= 0) |
68b65f73 RK |
521 | /* |
522 | * We didn't queue a DMA buffer for some reason, but we | |
523 | * have data pending to be sent. Re-enable the TX IRQ. | |
524 | */ | |
734745ca DM |
525 | pl011_start_tx_pio(uap); |
526 | ||
68b65f73 RK |
527 | spin_unlock_irqrestore(&uap->port.lock, flags); |
528 | } | |
529 | ||
530 | /* | |
531 | * Try to refill the TX DMA buffer. | |
532 | * Locking: called with port lock held and IRQs disabled. | |
533 | * Returns: | |
534 | * 1 if we queued up a TX DMA buffer. | |
535 | * 0 if we didn't want to handle this by DMA | |
536 | * <0 on error | |
537 | */ | |
538 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
539 | { | |
540 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
541 | struct dma_chan *chan = dmatx->chan; | |
542 | struct dma_device *dma_dev = chan->device; | |
543 | struct dma_async_tx_descriptor *desc; | |
544 | struct circ_buf *xmit = &uap->port.state->xmit; | |
545 | unsigned int count; | |
546 | ||
547 | /* | |
548 | * Try to avoid the overhead involved in using DMA if the | |
549 | * transaction fits in the first half of the FIFO, by using | |
550 | * the standard interrupt handling. This ensures that we | |
551 | * issue a uart_write_wakeup() at the appropriate time. | |
552 | */ | |
553 | count = uart_circ_chars_pending(xmit); | |
554 | if (count < (uap->fifosize >> 1)) { | |
555 | uap->dmatx.queued = false; | |
556 | return 0; | |
557 | } | |
558 | ||
559 | /* | |
560 | * Bodge: don't send the last character by DMA, as this | |
561 | * will prevent XON from notifying us to restart DMA. | |
562 | */ | |
563 | count -= 1; | |
564 | ||
565 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
566 | if (count > PL011_DMA_BUFFER_SIZE) | |
567 | count = PL011_DMA_BUFFER_SIZE; | |
568 | ||
569 | if (xmit->tail < xmit->head) | |
570 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
571 | else { | |
572 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
e2a545a6 AJ |
573 | size_t second; |
574 | ||
575 | if (first > count) | |
576 | first = count; | |
577 | second = count - first; | |
68b65f73 RK |
578 | |
579 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
580 | if (second) | |
581 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
582 | } | |
583 | ||
584 | dmatx->sg.length = count; | |
585 | ||
586 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
587 | uap->dmatx.queued = false; | |
588 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
589 | return -EBUSY; | |
590 | } | |
591 | ||
16052827 | 592 | desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, |
68b65f73 RK |
593 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
594 | if (!desc) { | |
595 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
596 | uap->dmatx.queued = false; | |
597 | /* | |
598 | * If DMA cannot be used right now, we complete this | |
599 | * transaction via IRQ and let the TTY layer retry. | |
600 | */ | |
601 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
602 | return -EBUSY; | |
603 | } | |
604 | ||
605 | /* Some data to go along to the callback */ | |
606 | desc->callback = pl011_dma_tx_callback; | |
607 | desc->callback_param = uap; | |
608 | ||
609 | /* All errors should happen at prepare time */ | |
610 | dmaengine_submit(desc); | |
611 | ||
612 | /* Fire the DMA transaction */ | |
613 | dma_dev->device_issue_pending(chan); | |
614 | ||
615 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 616 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
617 | uap->dmatx.queued = true; |
618 | ||
619 | /* | |
620 | * Now we know that DMA will fire, so advance the ring buffer | |
621 | * with the stuff we just dispatched. | |
622 | */ | |
623 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
624 | uap->port.icount.tx += count; | |
625 | ||
626 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
627 | uart_write_wakeup(&uap->port); | |
628 | ||
629 | return 1; | |
630 | } | |
631 | ||
632 | /* | |
633 | * We received a transmit interrupt without a pending X-char but with | |
634 | * pending characters. | |
635 | * Locking: called with port lock held and IRQs disabled. | |
636 | * Returns: | |
637 | * false if we want to use PIO to transmit | |
638 | * true if we queued a DMA buffer | |
639 | */ | |
640 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
641 | { | |
ead76f32 | 642 | if (!uap->using_tx_dma) |
68b65f73 RK |
643 | return false; |
644 | ||
645 | /* | |
646 | * If we already have a TX buffer queued, but received a | |
647 | * TX interrupt, it will be because we've just sent an X-char. | |
648 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
649 | */ | |
650 | if (uap->dmatx.queued) { | |
651 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 652 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 | 653 | uap->im &= ~UART011_TXIM; |
9f25bc51 | 654 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 RK |
655 | return true; |
656 | } | |
657 | ||
658 | /* | |
659 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 660 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
661 | */ |
662 | if (pl011_dma_tx_refill(uap) > 0) { | |
663 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 664 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 RK |
665 | return true; |
666 | } | |
667 | return false; | |
668 | } | |
669 | ||
670 | /* | |
671 | * Stop the DMA transmit (eg, due to received XOFF). | |
672 | * Locking: called with port lock held and IRQs disabled. | |
673 | */ | |
674 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
675 | { | |
676 | if (uap->dmatx.queued) { | |
677 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 678 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
679 | } |
680 | } | |
681 | ||
682 | /* | |
683 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
684 | * character queued for send, try to get that character out ASAP. | |
685 | * Locking: called with port lock held and IRQs disabled. | |
686 | * Returns: | |
687 | * false if we want the TX IRQ to be enabled | |
688 | * true if we have a buffer queued | |
689 | */ | |
690 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
691 | { | |
692 | u16 dmacr; | |
693 | ||
ead76f32 | 694 | if (!uap->using_tx_dma) |
68b65f73 RK |
695 | return false; |
696 | ||
697 | if (!uap->port.x_char) { | |
698 | /* no X-char, try to push chars out in DMA mode */ | |
699 | bool ret = true; | |
700 | ||
701 | if (!uap->dmatx.queued) { | |
702 | if (pl011_dma_tx_refill(uap) > 0) { | |
703 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 704 | pl011_write(uap->im, uap, REG_IMSC); |
734745ca | 705 | } else |
68b65f73 | 706 | ret = false; |
68b65f73 RK |
707 | } else if (!(uap->dmacr & UART011_TXDMAE)) { |
708 | uap->dmacr |= UART011_TXDMAE; | |
9f25bc51 | 709 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
710 | } |
711 | return ret; | |
712 | } | |
713 | ||
714 | /* | |
715 | * We have an X-char to send. Disable DMA to prevent it loading | |
716 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
717 | */ | |
718 | dmacr = uap->dmacr; | |
719 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 720 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 | 721 | |
9f25bc51 | 722 | if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) { |
68b65f73 RK |
723 | /* |
724 | * No space in the FIFO, so enable the transmit interrupt | |
725 | * so we know when there is space. Note that once we've | |
726 | * loaded the character, we should just re-enable DMA. | |
727 | */ | |
728 | return false; | |
729 | } | |
730 | ||
9f25bc51 | 731 | pl011_write(uap->port.x_char, uap, REG_DR); |
68b65f73 RK |
732 | uap->port.icount.tx++; |
733 | uap->port.x_char = 0; | |
734 | ||
735 | /* Success - restore the DMA state */ | |
736 | uap->dmacr = dmacr; | |
9f25bc51 | 737 | pl011_write(dmacr, uap, REG_DMACR); |
68b65f73 RK |
738 | |
739 | return true; | |
740 | } | |
741 | ||
742 | /* | |
743 | * Flush the transmit buffer. | |
744 | * Locking: called with port lock held and IRQs disabled. | |
745 | */ | |
746 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
b83286bf FE |
747 | __releases(&uap->port.lock) |
748 | __acquires(&uap->port.lock) | |
68b65f73 | 749 | { |
a5820c24 DT |
750 | struct uart_amba_port *uap = |
751 | container_of(port, struct uart_amba_port, port); | |
68b65f73 | 752 | |
ead76f32 | 753 | if (!uap->using_tx_dma) |
68b65f73 RK |
754 | return; |
755 | ||
756 | /* Avoid deadlock with the DMA engine callback */ | |
757 | spin_unlock(&uap->port.lock); | |
758 | dmaengine_terminate_all(uap->dmatx.chan); | |
759 | spin_lock(&uap->port.lock); | |
760 | if (uap->dmatx.queued) { | |
761 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
762 | DMA_TO_DEVICE); | |
763 | uap->dmatx.queued = false; | |
764 | uap->dmacr &= ~UART011_TXDMAE; | |
9f25bc51 | 765 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
766 | } |
767 | } | |
768 | ||
ead76f32 LW |
769 | static void pl011_dma_rx_callback(void *data); |
770 | ||
771 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
772 | { | |
773 | struct dma_chan *rxchan = uap->dmarx.chan; | |
ead76f32 LW |
774 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
775 | struct dma_async_tx_descriptor *desc; | |
776 | struct pl011_sgbuf *sgbuf; | |
777 | ||
778 | if (!rxchan) | |
779 | return -EIO; | |
780 | ||
781 | /* Start the RX DMA job */ | |
782 | sgbuf = uap->dmarx.use_buf_b ? | |
783 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
16052827 | 784 | desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, |
a485df4b | 785 | DMA_DEV_TO_MEM, |
ead76f32 LW |
786 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
787 | /* | |
788 | * If the DMA engine is busy and cannot prepare a | |
789 | * channel, no big deal, the driver will fall back | |
790 | * to interrupt mode as a result of this error code. | |
791 | */ | |
792 | if (!desc) { | |
793 | uap->dmarx.running = false; | |
794 | dmaengine_terminate_all(rxchan); | |
795 | return -EBUSY; | |
796 | } | |
797 | ||
798 | /* Some data to go along to the callback */ | |
799 | desc->callback = pl011_dma_rx_callback; | |
800 | desc->callback_param = uap; | |
801 | dmarx->cookie = dmaengine_submit(desc); | |
802 | dma_async_issue_pending(rxchan); | |
803 | ||
804 | uap->dmacr |= UART011_RXDMAE; | |
9f25bc51 | 805 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 LW |
806 | uap->dmarx.running = true; |
807 | ||
808 | uap->im &= ~UART011_RXIM; | |
9f25bc51 | 809 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
810 | |
811 | return 0; | |
812 | } | |
813 | ||
814 | /* | |
815 | * This is called when either the DMA job is complete, or | |
816 | * the FIFO timeout interrupt occurred. This must be called | |
817 | * with the port spinlock uap->port.lock held. | |
818 | */ | |
819 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
820 | u32 pending, bool use_buf_b, | |
821 | bool readfifo) | |
822 | { | |
05c7cd39 | 823 | struct tty_port *port = &uap->port.state->port; |
ead76f32 LW |
824 | struct pl011_sgbuf *sgbuf = use_buf_b ? |
825 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
ead76f32 LW |
826 | int dma_count = 0; |
827 | u32 fifotaken = 0; /* only used for vdbg() */ | |
828 | ||
cb06ff10 CM |
829 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
830 | int dmataken = 0; | |
831 | ||
832 | if (uap->dmarx.poll_rate) { | |
833 | /* The data can be taken by polling */ | |
834 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
835 | /* Recalculate the pending size */ | |
836 | if (pending >= dmataken) | |
837 | pending -= dmataken; | |
838 | } | |
839 | ||
840 | /* Pick the remain data from the DMA */ | |
ead76f32 | 841 | if (pending) { |
ead76f32 LW |
842 | |
843 | /* | |
844 | * First take all chars in the DMA pipe, then look in the FIFO. | |
845 | * Note that tty_insert_flip_buf() tries to take as many chars | |
846 | * as it can. | |
847 | */ | |
cb06ff10 CM |
848 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, |
849 | pending); | |
ead76f32 LW |
850 | |
851 | uap->port.icount.rx += dma_count; | |
852 | if (dma_count < pending) | |
853 | dev_warn(uap->port.dev, | |
854 | "couldn't insert all characters (TTY is full?)\n"); | |
855 | } | |
856 | ||
cb06ff10 CM |
857 | /* Reset the last_residue for Rx DMA poll */ |
858 | if (uap->dmarx.poll_rate) | |
859 | dmarx->last_residue = sgbuf->sg.length; | |
860 | ||
ead76f32 LW |
861 | /* |
862 | * Only continue with trying to read the FIFO if all DMA chars have | |
863 | * been taken first. | |
864 | */ | |
865 | if (dma_count == pending && readfifo) { | |
866 | /* Clear any error flags */ | |
75836339 | 867 | pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | |
9f25bc51 | 868 | UART011_FEIS, uap, REG_ICR); |
ead76f32 LW |
869 | |
870 | /* | |
871 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
872 | * incomplete buffer, that could be due to an rx error, or |
873 | * maybe we just timed out. Read any pending chars and check | |
874 | * the error status. | |
875 | * | |
876 | * Error conditions will only occur in the FIFO, these will | |
877 | * trigger an immediate interrupt and stop the DMA job, so we | |
878 | * will always find the error in the FIFO, never in the DMA | |
879 | * buffer. | |
ead76f32 | 880 | */ |
29772c4e | 881 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
882 | } |
883 | ||
884 | spin_unlock(&uap->port.lock); | |
885 | dev_vdbg(uap->port.dev, | |
886 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
887 | dma_count, fifotaken); | |
2e124b4a | 888 | tty_flip_buffer_push(port); |
ead76f32 LW |
889 | spin_lock(&uap->port.lock); |
890 | } | |
891 | ||
892 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
893 | { | |
894 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
895 | struct dma_chan *rxchan = dmarx->chan; | |
896 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
897 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
898 | size_t pending; | |
899 | struct dma_tx_state state; | |
900 | enum dma_status dmastat; | |
901 | ||
902 | /* | |
903 | * Pause the transfer so we can trust the current counter, | |
904 | * do this before we pause the PL011 block, else we may | |
905 | * overflow the FIFO. | |
906 | */ | |
907 | if (dmaengine_pause(rxchan)) | |
908 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
909 | dmastat = rxchan->device->device_tx_status(rxchan, | |
910 | dmarx->cookie, &state); | |
911 | if (dmastat != DMA_PAUSED) | |
912 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
913 | ||
914 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
915 | uap->dmacr &= ~UART011_RXDMAE; | |
9f25bc51 | 916 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 LW |
917 | uap->dmarx.running = false; |
918 | ||
919 | pending = sgbuf->sg.length - state.residue; | |
920 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
921 | /* Then we terminate the transfer - we now know our residue */ | |
922 | dmaengine_terminate_all(rxchan); | |
923 | ||
924 | /* | |
925 | * This will take the chars we have so far and insert | |
926 | * into the framework. | |
927 | */ | |
928 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
929 | ||
930 | /* Switch buffer & re-trigger DMA job */ | |
931 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
932 | if (pl011_dma_rx_trigger_dma(uap)) { | |
933 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
934 | "fall back to interrupt mode\n"); | |
935 | uap->im |= UART011_RXIM; | |
9f25bc51 | 936 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
937 | } |
938 | } | |
939 | ||
940 | static void pl011_dma_rx_callback(void *data) | |
941 | { | |
942 | struct uart_amba_port *uap = data; | |
943 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
6dc01aa6 | 944 | struct dma_chan *rxchan = dmarx->chan; |
ead76f32 | 945 | bool lastbuf = dmarx->use_buf_b; |
6dc01aa6 CM |
946 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? |
947 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
948 | size_t pending; | |
949 | struct dma_tx_state state; | |
ead76f32 LW |
950 | int ret; |
951 | ||
952 | /* | |
953 | * This completion interrupt occurs typically when the | |
954 | * RX buffer is totally stuffed but no timeout has yet | |
955 | * occurred. When that happens, we just want the RX | |
956 | * routine to flush out the secondary DMA buffer while | |
957 | * we immediately trigger the next DMA job. | |
958 | */ | |
959 | spin_lock_irq(&uap->port.lock); | |
6dc01aa6 CM |
960 | /* |
961 | * Rx data can be taken by the UART interrupts during | |
962 | * the DMA irq handler. So we check the residue here. | |
963 | */ | |
964 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
965 | pending = sgbuf->sg.length - state.residue; | |
966 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
967 | /* Then we terminate the transfer - we now know our residue */ | |
968 | dmaengine_terminate_all(rxchan); | |
969 | ||
ead76f32 LW |
970 | uap->dmarx.running = false; |
971 | dmarx->use_buf_b = !lastbuf; | |
972 | ret = pl011_dma_rx_trigger_dma(uap); | |
973 | ||
6dc01aa6 | 974 | pl011_dma_rx_chars(uap, pending, lastbuf, false); |
ead76f32 LW |
975 | spin_unlock_irq(&uap->port.lock); |
976 | /* | |
977 | * Do this check after we picked the DMA chars so we don't | |
978 | * get some IRQ immediately from RX. | |
979 | */ | |
980 | if (ret) { | |
981 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
982 | "fall back to interrupt mode\n"); | |
983 | uap->im |= UART011_RXIM; | |
9f25bc51 | 984 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
985 | } |
986 | } | |
987 | ||
988 | /* | |
989 | * Stop accepting received characters, when we're shutting down or | |
990 | * suspending this port. | |
991 | * Locking: called with port lock held and IRQs disabled. | |
992 | */ | |
993 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
994 | { | |
995 | /* FIXME. Just disable the DMA enable */ | |
996 | uap->dmacr &= ~UART011_RXDMAE; | |
9f25bc51 | 997 | pl011_write(uap->dmacr, uap, REG_DMACR); |
ead76f32 | 998 | } |
68b65f73 | 999 | |
cb06ff10 CM |
1000 | /* |
1001 | * Timer handler for Rx DMA polling. | |
1002 | * Every polling, It checks the residue in the dma buffer and transfer | |
1003 | * data to the tty. Also, last_residue is updated for the next polling. | |
1004 | */ | |
1005 | static void pl011_dma_rx_poll(unsigned long args) | |
1006 | { | |
1007 | struct uart_amba_port *uap = (struct uart_amba_port *)args; | |
1008 | struct tty_port *port = &uap->port.state->port; | |
1009 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
1010 | struct dma_chan *rxchan = uap->dmarx.chan; | |
1011 | unsigned long flags = 0; | |
1012 | unsigned int dmataken = 0; | |
1013 | unsigned int size = 0; | |
1014 | struct pl011_sgbuf *sgbuf; | |
1015 | int dma_count; | |
1016 | struct dma_tx_state state; | |
1017 | ||
1018 | sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
1019 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
1020 | if (likely(state.residue < dmarx->last_residue)) { | |
1021 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
1022 | size = dmarx->last_residue - state.residue; | |
1023 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, | |
1024 | size); | |
1025 | if (dma_count == size) | |
1026 | dmarx->last_residue = state.residue; | |
1027 | dmarx->last_jiffies = jiffies; | |
1028 | } | |
1029 | tty_flip_buffer_push(port); | |
1030 | ||
1031 | /* | |
1032 | * If no data is received in poll_timeout, the driver will fall back | |
1033 | * to interrupt mode. We will retrigger DMA at the first interrupt. | |
1034 | */ | |
1035 | if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) | |
1036 | > uap->dmarx.poll_timeout) { | |
1037 | ||
1038 | spin_lock_irqsave(&uap->port.lock, flags); | |
1039 | pl011_dma_rx_stop(uap); | |
c25a1ad7 | 1040 | uap->im |= UART011_RXIM; |
9f25bc51 | 1041 | pl011_write(uap->im, uap, REG_IMSC); |
cb06ff10 CM |
1042 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1043 | ||
1044 | uap->dmarx.running = false; | |
1045 | dmaengine_terminate_all(rxchan); | |
1046 | del_timer(&uap->dmarx.timer); | |
1047 | } else { | |
1048 | mod_timer(&uap->dmarx.timer, | |
1049 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1050 | } | |
1051 | } | |
1052 | ||
68b65f73 RK |
1053 | static void pl011_dma_startup(struct uart_amba_port *uap) |
1054 | { | |
ead76f32 LW |
1055 | int ret; |
1056 | ||
1c9be310 JRO |
1057 | if (!uap->dma_probed) |
1058 | pl011_dma_probe(uap); | |
1059 | ||
68b65f73 RK |
1060 | if (!uap->dmatx.chan) |
1061 | return; | |
1062 | ||
4c0be45b | 1063 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA); |
68b65f73 RK |
1064 | if (!uap->dmatx.buf) { |
1065 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
1066 | uap->port.fifosize = uap->fifosize; | |
1067 | return; | |
1068 | } | |
1069 | ||
1070 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
1071 | ||
1072 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
1073 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
1074 | uap->using_tx_dma = true; |
1075 | ||
1076 | if (!uap->dmarx.chan) | |
1077 | goto skip_rx; | |
1078 | ||
1079 | /* Allocate and map DMA RX buffers */ | |
1080 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1081 | DMA_FROM_DEVICE); | |
1082 | if (ret) { | |
1083 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1084 | "RX buffer A", ret); | |
1085 | goto skip_rx; | |
1086 | } | |
68b65f73 | 1087 | |
ead76f32 LW |
1088 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
1089 | DMA_FROM_DEVICE); | |
1090 | if (ret) { | |
1091 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1092 | "RX buffer B", ret); | |
1093 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1094 | DMA_FROM_DEVICE); | |
1095 | goto skip_rx; | |
1096 | } | |
1097 | ||
1098 | uap->using_rx_dma = true; | |
68b65f73 | 1099 | |
ead76f32 | 1100 | skip_rx: |
68b65f73 RK |
1101 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
1102 | uap->dmacr |= UART011_DMAONERR; | |
9f25bc51 | 1103 | pl011_write(uap->dmacr, uap, REG_DMACR); |
38d62436 RK |
1104 | |
1105 | /* | |
1106 | * ST Micro variants has some specific dma burst threshold | |
1107 | * compensation. Set this to 16 bytes, so burst will only | |
1108 | * be issued above/below 16 bytes. | |
1109 | */ | |
1110 | if (uap->vendor->dma_threshold) | |
75836339 | 1111 | pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, |
9f25bc51 | 1112 | uap, REG_ST_DMAWM); |
ead76f32 LW |
1113 | |
1114 | if (uap->using_rx_dma) { | |
1115 | if (pl011_dma_rx_trigger_dma(uap)) | |
1116 | dev_dbg(uap->port.dev, "could not trigger initial " | |
1117 | "RX DMA job, fall back to interrupt mode\n"); | |
cb06ff10 CM |
1118 | if (uap->dmarx.poll_rate) { |
1119 | init_timer(&(uap->dmarx.timer)); | |
1120 | uap->dmarx.timer.function = pl011_dma_rx_poll; | |
1121 | uap->dmarx.timer.data = (unsigned long)uap; | |
1122 | mod_timer(&uap->dmarx.timer, | |
1123 | jiffies + | |
1124 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1125 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1126 | uap->dmarx.last_jiffies = jiffies; | |
1127 | } | |
ead76f32 | 1128 | } |
68b65f73 RK |
1129 | } |
1130 | ||
1131 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1132 | { | |
ead76f32 | 1133 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
1134 | return; |
1135 | ||
1136 | /* Disable RX and TX DMA */ | |
9f25bc51 | 1137 | while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY) |
68b65f73 RK |
1138 | barrier(); |
1139 | ||
1140 | spin_lock_irq(&uap->port.lock); | |
1141 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
9f25bc51 | 1142 | pl011_write(uap->dmacr, uap, REG_DMACR); |
68b65f73 RK |
1143 | spin_unlock_irq(&uap->port.lock); |
1144 | ||
ead76f32 LW |
1145 | if (uap->using_tx_dma) { |
1146 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
1147 | dmaengine_terminate_all(uap->dmatx.chan); | |
1148 | if (uap->dmatx.queued) { | |
1149 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
1150 | DMA_TO_DEVICE); | |
1151 | uap->dmatx.queued = false; | |
1152 | } | |
1153 | ||
1154 | kfree(uap->dmatx.buf); | |
1155 | uap->using_tx_dma = false; | |
68b65f73 RK |
1156 | } |
1157 | ||
ead76f32 LW |
1158 | if (uap->using_rx_dma) { |
1159 | dmaengine_terminate_all(uap->dmarx.chan); | |
1160 | /* Clean up the RX DMA */ | |
1161 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
1162 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
cb06ff10 CM |
1163 | if (uap->dmarx.poll_rate) |
1164 | del_timer_sync(&uap->dmarx.timer); | |
ead76f32 LW |
1165 | uap->using_rx_dma = false; |
1166 | } | |
1167 | } | |
68b65f73 | 1168 | |
ead76f32 LW |
1169 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
1170 | { | |
1171 | return uap->using_rx_dma; | |
68b65f73 RK |
1172 | } |
1173 | ||
ead76f32 LW |
1174 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
1175 | { | |
1176 | return uap->using_rx_dma && uap->dmarx.running; | |
1177 | } | |
1178 | ||
68b65f73 RK |
1179 | #else |
1180 | /* Blank functions if the DMA engine is not available */ | |
1c9be310 | 1181 | static inline void pl011_dma_probe(struct uart_amba_port *uap) |
68b65f73 RK |
1182 | { |
1183 | } | |
1184 | ||
1185 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
1186 | { | |
1187 | } | |
1188 | ||
1189 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
1190 | { | |
1191 | } | |
1192 | ||
1193 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1194 | { | |
1195 | } | |
1196 | ||
1197 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
1198 | { | |
1199 | return false; | |
1200 | } | |
1201 | ||
1202 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
1203 | { | |
1204 | } | |
1205 | ||
1206 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
1207 | { | |
1208 | return false; | |
1209 | } | |
1210 | ||
ead76f32 LW |
1211 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
1212 | { | |
1213 | } | |
1214 | ||
1215 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1216 | { | |
1217 | } | |
1218 | ||
1219 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
1220 | { | |
1221 | return -EIO; | |
1222 | } | |
1223 | ||
1224 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1225 | { | |
1226 | return false; | |
1227 | } | |
1228 | ||
1229 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1230 | { | |
1231 | return false; | |
1232 | } | |
1233 | ||
68b65f73 RK |
1234 | #define pl011_dma_flush_buffer NULL |
1235 | #endif | |
1236 | ||
b129a8cc | 1237 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 | 1238 | { |
a5820c24 DT |
1239 | struct uart_amba_port *uap = |
1240 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1241 | |
1242 | uap->im &= ~UART011_TXIM; | |
9f25bc51 | 1243 | pl011_write(uap->im, uap, REG_IMSC); |
68b65f73 | 1244 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1245 | } |
1246 | ||
1e84d223 | 1247 | static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq); |
734745ca DM |
1248 | |
1249 | /* Start TX with programmed I/O only (no DMA) */ | |
1250 | static void pl011_start_tx_pio(struct uart_amba_port *uap) | |
1251 | { | |
1252 | uap->im |= UART011_TXIM; | |
9f25bc51 | 1253 | pl011_write(uap->im, uap, REG_IMSC); |
1e84d223 | 1254 | pl011_tx_chars(uap, false); |
734745ca DM |
1255 | } |
1256 | ||
b129a8cc | 1257 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 | 1258 | { |
a5820c24 DT |
1259 | struct uart_amba_port *uap = |
1260 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1261 | |
734745ca DM |
1262 | if (!pl011_dma_tx_start(uap)) |
1263 | pl011_start_tx_pio(uap); | |
1da177e4 LT |
1264 | } |
1265 | ||
1266 | static void pl011_stop_rx(struct uart_port *port) | |
1267 | { | |
a5820c24 DT |
1268 | struct uart_amba_port *uap = |
1269 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1270 | |
1271 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1272 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
9f25bc51 | 1273 | pl011_write(uap->im, uap, REG_IMSC); |
ead76f32 LW |
1274 | |
1275 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1276 | } |
1277 | ||
1278 | static void pl011_enable_ms(struct uart_port *port) | |
1279 | { | |
a5820c24 DT |
1280 | struct uart_amba_port *uap = |
1281 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1282 | |
1283 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
9f25bc51 | 1284 | pl011_write(uap->im, uap, REG_IMSC); |
1da177e4 LT |
1285 | } |
1286 | ||
7d12e780 | 1287 | static void pl011_rx_chars(struct uart_amba_port *uap) |
b83286bf FE |
1288 | __releases(&uap->port.lock) |
1289 | __acquires(&uap->port.lock) | |
1da177e4 | 1290 | { |
29772c4e | 1291 | pl011_fifo_to_tty(uap); |
1da177e4 | 1292 | |
2389b272 | 1293 | spin_unlock(&uap->port.lock); |
2e124b4a | 1294 | tty_flip_buffer_push(&uap->port.state->port); |
ead76f32 LW |
1295 | /* |
1296 | * If we were temporarily out of DMA mode for a while, | |
1297 | * attempt to switch back to DMA mode again. | |
1298 | */ | |
1299 | if (pl011_dma_rx_available(uap)) { | |
1300 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1301 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1302 | "fall back to interrupt mode again\n"); | |
1303 | uap->im |= UART011_RXIM; | |
9f25bc51 | 1304 | pl011_write(uap->im, uap, REG_IMSC); |
cb06ff10 | 1305 | } else { |
89fa28db | 1306 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1307 | /* Start Rx DMA poll */ |
1308 | if (uap->dmarx.poll_rate) { | |
1309 | uap->dmarx.last_jiffies = jiffies; | |
1310 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1311 | mod_timer(&uap->dmarx.timer, | |
1312 | jiffies + | |
1313 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1314 | } | |
89fa28db | 1315 | #endif |
cb06ff10 | 1316 | } |
ead76f32 | 1317 | } |
2389b272 | 1318 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1319 | } |
1320 | ||
1e84d223 DM |
1321 | static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, |
1322 | bool from_irq) | |
734745ca | 1323 | { |
1e84d223 | 1324 | if (unlikely(!from_irq) && |
9f25bc51 | 1325 | pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
1e84d223 DM |
1326 | return false; /* unable to transmit character */ |
1327 | ||
9f25bc51 | 1328 | pl011_write(c, uap, REG_DR); |
734745ca DM |
1329 | uap->port.icount.tx++; |
1330 | ||
1e84d223 | 1331 | return true; |
734745ca DM |
1332 | } |
1333 | ||
1e84d223 | 1334 | static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq) |
1da177e4 | 1335 | { |
ebd2c8f6 | 1336 | struct circ_buf *xmit = &uap->port.state->xmit; |
1e84d223 | 1337 | int count = uap->fifosize >> 1; |
734745ca | 1338 | |
1da177e4 | 1339 | if (uap->port.x_char) { |
1e84d223 DM |
1340 | if (!pl011_tx_char(uap, uap->port.x_char, from_irq)) |
1341 | return; | |
1da177e4 | 1342 | uap->port.x_char = 0; |
734745ca | 1343 | --count; |
1da177e4 LT |
1344 | } |
1345 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1346 | pl011_stop_tx(&uap->port); |
1e84d223 | 1347 | return; |
1da177e4 LT |
1348 | } |
1349 | ||
68b65f73 RK |
1350 | /* If we are using DMA mode, try to send some characters. */ |
1351 | if (pl011_dma_tx_irq(uap)) | |
1e84d223 | 1352 | return; |
68b65f73 | 1353 | |
1e84d223 DM |
1354 | do { |
1355 | if (likely(from_irq) && count-- == 0) | |
1da177e4 | 1356 | break; |
1e84d223 DM |
1357 | |
1358 | if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq)) | |
1359 | break; | |
1360 | ||
1361 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1362 | } while (!uart_circ_empty(xmit)); | |
1da177e4 LT |
1363 | |
1364 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1365 | uart_write_wakeup(&uap->port); | |
1366 | ||
1e84d223 | 1367 | if (uart_circ_empty(xmit)) |
b129a8cc | 1368 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1369 | } |
1370 | ||
1371 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1372 | { | |
1373 | unsigned int status, delta; | |
1374 | ||
9f25bc51 | 1375 | status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 LT |
1376 | |
1377 | delta = status ^ uap->old_status; | |
1378 | uap->old_status = status; | |
1379 | ||
1380 | if (!delta) | |
1381 | return; | |
1382 | ||
1383 | if (delta & UART01x_FR_DCD) | |
1384 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1385 | ||
062a68a5 | 1386 | if (delta & UART01x_FR_DSR) |
1da177e4 LT |
1387 | uap->port.icount.dsr++; |
1388 | ||
062a68a5 GKH |
1389 | if (delta & UART01x_FR_CTS) |
1390 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1da177e4 | 1391 | |
bdc04e31 | 1392 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1393 | } |
1394 | ||
9c4ef4b0 AP |
1395 | static void check_apply_cts_event_workaround(struct uart_amba_port *uap) |
1396 | { | |
1397 | unsigned int dummy_read; | |
1398 | ||
1399 | if (!uap->vendor->cts_event_workaround) | |
1400 | return; | |
1401 | ||
1402 | /* workaround to make sure that all bits are unlocked.. */ | |
9f25bc51 | 1403 | pl011_write(0x00, uap, REG_ICR); |
9c4ef4b0 AP |
1404 | |
1405 | /* | |
1406 | * WA: introduce 26ns(1 uart clk) delay before W1C; | |
1407 | * single apb access will incur 2 pclk(133.12Mhz) delay, | |
1408 | * so add 2 dummy reads | |
1409 | */ | |
9f25bc51 RK |
1410 | dummy_read = pl011_read(uap, REG_ICR); |
1411 | dummy_read = pl011_read(uap, REG_ICR); | |
9c4ef4b0 AP |
1412 | } |
1413 | ||
7d12e780 | 1414 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1415 | { |
1416 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1417 | unsigned long flags; |
1da177e4 | 1418 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
075167ed | 1419 | u16 imsc; |
1da177e4 LT |
1420 | int handled = 0; |
1421 | ||
963cc981 | 1422 | spin_lock_irqsave(&uap->port.lock, flags); |
9f25bc51 RK |
1423 | imsc = pl011_read(uap, REG_IMSC); |
1424 | status = pl011_read(uap, REG_RIS) & imsc; | |
1da177e4 LT |
1425 | if (status) { |
1426 | do { | |
9c4ef4b0 | 1427 | check_apply_cts_event_workaround(uap); |
f11c9841 | 1428 | |
75836339 RK |
1429 | pl011_write(status & ~(UART011_TXIS|UART011_RTIS| |
1430 | UART011_RXIS), | |
9f25bc51 | 1431 | uap, REG_ICR); |
1da177e4 | 1432 | |
ead76f32 LW |
1433 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1434 | if (pl011_dma_rx_running(uap)) | |
1435 | pl011_dma_rx_irq(uap); | |
1436 | else | |
1437 | pl011_rx_chars(uap); | |
1438 | } | |
1da177e4 LT |
1439 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1440 | UART011_CTSMIS|UART011_RIMIS)) | |
1441 | pl011_modem_status(uap); | |
1e84d223 DM |
1442 | if (status & UART011_TXIS) |
1443 | pl011_tx_chars(uap, true); | |
1da177e4 | 1444 | |
4fd0690b | 1445 | if (pass_counter-- == 0) |
1da177e4 LT |
1446 | break; |
1447 | ||
9f25bc51 | 1448 | status = pl011_read(uap, REG_RIS) & imsc; |
1da177e4 LT |
1449 | } while (status != 0); |
1450 | handled = 1; | |
1451 | } | |
1452 | ||
963cc981 | 1453 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1454 | |
1455 | return IRQ_RETVAL(handled); | |
1456 | } | |
1457 | ||
e643f87f | 1458 | static unsigned int pl011_tx_empty(struct uart_port *port) |
1da177e4 | 1459 | { |
a5820c24 DT |
1460 | struct uart_amba_port *uap = |
1461 | container_of(port, struct uart_amba_port, port); | |
9f25bc51 | 1462 | unsigned int status = pl011_read(uap, REG_FR); |
062a68a5 | 1463 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; |
1da177e4 LT |
1464 | } |
1465 | ||
e643f87f | 1466 | static unsigned int pl011_get_mctrl(struct uart_port *port) |
1da177e4 | 1467 | { |
a5820c24 DT |
1468 | struct uart_amba_port *uap = |
1469 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1470 | unsigned int result = 0; |
9f25bc51 | 1471 | unsigned int status = pl011_read(uap, REG_FR); |
1da177e4 | 1472 | |
5159f407 | 1473 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1474 | if (status & uartbit) \ |
1475 | result |= tiocmbit | |
1476 | ||
5159f407 | 1477 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
062a68a5 GKH |
1478 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); |
1479 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1480 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
5159f407 | 1481 | #undef TIOCMBIT |
1da177e4 LT |
1482 | return result; |
1483 | } | |
1484 | ||
1485 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1486 | { | |
a5820c24 DT |
1487 | struct uart_amba_port *uap = |
1488 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1489 | unsigned int cr; |
1490 | ||
9f25bc51 | 1491 | cr = pl011_read(uap, REG_CR); |
1da177e4 | 1492 | |
5159f407 | 1493 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1494 | if (mctrl & tiocmbit) \ |
1495 | cr |= uartbit; \ | |
1496 | else \ | |
1497 | cr &= ~uartbit | |
1498 | ||
5159f407 JS |
1499 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1500 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1501 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1502 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1503 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1504 | |
1505 | if (uap->autorts) { | |
1506 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1507 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1508 | } | |
5159f407 | 1509 | #undef TIOCMBIT |
1da177e4 | 1510 | |
9f25bc51 | 1511 | pl011_write(cr, uap, REG_CR); |
1da177e4 LT |
1512 | } |
1513 | ||
1514 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1515 | { | |
a5820c24 DT |
1516 | struct uart_amba_port *uap = |
1517 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1518 | unsigned long flags; |
1519 | unsigned int lcr_h; | |
1520 | ||
1521 | spin_lock_irqsave(&uap->port.lock, flags); | |
e4df9a80 | 1522 | lcr_h = pl011_read(uap, REG_LCRH_TX); |
1da177e4 LT |
1523 | if (break_state == -1) |
1524 | lcr_h |= UART01x_LCRH_BRK; | |
1525 | else | |
1526 | lcr_h &= ~UART01x_LCRH_BRK; | |
e4df9a80 | 1527 | pl011_write(lcr_h, uap, REG_LCRH_TX); |
1da177e4 LT |
1528 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1529 | } | |
1530 | ||
84b5ae15 | 1531 | #ifdef CONFIG_CONSOLE_POLL |
5c8124a0 AV |
1532 | |
1533 | static void pl011_quiesce_irqs(struct uart_port *port) | |
1534 | { | |
a5820c24 DT |
1535 | struct uart_amba_port *uap = |
1536 | container_of(port, struct uart_amba_port, port); | |
5c8124a0 | 1537 | |
9f25bc51 | 1538 | pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR); |
5c8124a0 AV |
1539 | /* |
1540 | * There is no way to clear TXIM as this is "ready to transmit IRQ", so | |
1541 | * we simply mask it. start_tx() will unmask it. | |
1542 | * | |
1543 | * Note we can race with start_tx(), and if the race happens, the | |
1544 | * polling user might get another interrupt just after we clear it. | |
1545 | * But it should be OK and can happen even w/o the race, e.g. | |
1546 | * controller immediately got some new data and raised the IRQ. | |
1547 | * | |
1548 | * And whoever uses polling routines assumes that it manages the device | |
1549 | * (including tx queue), so we're also fine with start_tx()'s caller | |
1550 | * side. | |
1551 | */ | |
9f25bc51 RK |
1552 | pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap, |
1553 | REG_IMSC); | |
5c8124a0 AV |
1554 | } |
1555 | ||
e643f87f | 1556 | static int pl011_get_poll_char(struct uart_port *port) |
84b5ae15 | 1557 | { |
a5820c24 DT |
1558 | struct uart_amba_port *uap = |
1559 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1560 | unsigned int status; |
1561 | ||
5c8124a0 AV |
1562 | /* |
1563 | * The caller might need IRQs lowered, e.g. if used with KDB NMI | |
1564 | * debugger. | |
1565 | */ | |
1566 | pl011_quiesce_irqs(port); | |
1567 | ||
9f25bc51 | 1568 | status = pl011_read(uap, REG_FR); |
f5316b4a JW |
1569 | if (status & UART01x_FR_RXFE) |
1570 | return NO_POLL_CHAR; | |
84b5ae15 | 1571 | |
9f25bc51 | 1572 | return pl011_read(uap, REG_DR); |
84b5ae15 JW |
1573 | } |
1574 | ||
e643f87f | 1575 | static void pl011_put_poll_char(struct uart_port *port, |
84b5ae15 JW |
1576 | unsigned char ch) |
1577 | { | |
a5820c24 DT |
1578 | struct uart_amba_port *uap = |
1579 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 | 1580 | |
9f25bc51 | 1581 | while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
84b5ae15 JW |
1582 | barrier(); |
1583 | ||
9f25bc51 | 1584 | pl011_write(ch, uap, REG_DR); |
84b5ae15 JW |
1585 | } |
1586 | ||
1587 | #endif /* CONFIG_CONSOLE_POLL */ | |
1588 | ||
b3564c2c | 1589 | static int pl011_hwinit(struct uart_port *port) |
1da177e4 | 1590 | { |
a5820c24 DT |
1591 | struct uart_amba_port *uap = |
1592 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1593 | int retval; |
1594 | ||
78d80c5a | 1595 | /* Optionaly enable pins to be muxed in and configured */ |
2b996fc5 | 1596 | pinctrl_pm_select_default_state(port->dev); |
78d80c5a | 1597 | |
1da177e4 LT |
1598 | /* |
1599 | * Try to enable the clock producer. | |
1600 | */ | |
1c4c4394 | 1601 | retval = clk_prepare_enable(uap->clk); |
1da177e4 | 1602 | if (retval) |
7f6d942a | 1603 | return retval; |
1da177e4 LT |
1604 | |
1605 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1606 | ||
9b96fbac | 1607 | /* Clear pending error and receive interrupts */ |
75836339 RK |
1608 | pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS | |
1609 | UART011_FEIS | UART011_RTIS | UART011_RXIS, | |
9f25bc51 | 1610 | uap, REG_ICR); |
9b96fbac | 1611 | |
b3564c2c AV |
1612 | /* |
1613 | * Save interrupts enable mask, and enable RX interrupts in case if | |
1614 | * the interrupt is used for NMI entry. | |
1615 | */ | |
9f25bc51 RK |
1616 | uap->im = pl011_read(uap, REG_IMSC); |
1617 | pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC); | |
b3564c2c | 1618 | |
574de559 | 1619 | if (dev_get_platdata(uap->port.dev)) { |
b3564c2c AV |
1620 | struct amba_pl011_data *plat; |
1621 | ||
574de559 | 1622 | plat = dev_get_platdata(uap->port.dev); |
b3564c2c AV |
1623 | if (plat->init) |
1624 | plat->init(); | |
1625 | } | |
1626 | return 0; | |
b3564c2c AV |
1627 | } |
1628 | ||
7fe9a5a9 RK |
1629 | static bool pl011_split_lcrh(const struct uart_amba_port *uap) |
1630 | { | |
e4df9a80 RK |
1631 | return pl011_reg_to_offset(uap, REG_LCRH_RX) != |
1632 | pl011_reg_to_offset(uap, REG_LCRH_TX); | |
7fe9a5a9 RK |
1633 | } |
1634 | ||
b60f2f66 JM |
1635 | static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) |
1636 | { | |
e4df9a80 | 1637 | pl011_write(lcr_h, uap, REG_LCRH_RX); |
7fe9a5a9 | 1638 | if (pl011_split_lcrh(uap)) { |
b60f2f66 JM |
1639 | int i; |
1640 | /* | |
1641 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1642 | * to get this delay write read only register 10 times | |
1643 | */ | |
1644 | for (i = 0; i < 10; ++i) | |
9f25bc51 | 1645 | pl011_write(0xff, uap, REG_MIS); |
e4df9a80 | 1646 | pl011_write(lcr_h, uap, REG_LCRH_TX); |
b60f2f66 JM |
1647 | } |
1648 | } | |
1649 | ||
867b8e8e AP |
1650 | static int pl011_allocate_irq(struct uart_amba_port *uap) |
1651 | { | |
9f25bc51 | 1652 | pl011_write(uap->im, uap, REG_IMSC); |
867b8e8e AP |
1653 | |
1654 | return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1655 | } | |
1656 | ||
1657 | /* | |
1658 | * Enable interrupts, only timeouts when using DMA | |
1659 | * if initial RX DMA job failed, start in interrupt mode | |
1660 | * as well. | |
1661 | */ | |
1662 | static void pl011_enable_interrupts(struct uart_amba_port *uap) | |
1663 | { | |
1664 | spin_lock_irq(&uap->port.lock); | |
1665 | ||
1666 | /* Clear out any spuriously appearing RX interrupts */ | |
9f25bc51 | 1667 | pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); |
867b8e8e AP |
1668 | uap->im = UART011_RTIM; |
1669 | if (!pl011_dma_rx_running(uap)) | |
1670 | uap->im |= UART011_RXIM; | |
9f25bc51 | 1671 | pl011_write(uap->im, uap, REG_IMSC); |
867b8e8e AP |
1672 | spin_unlock_irq(&uap->port.lock); |
1673 | } | |
1674 | ||
b3564c2c AV |
1675 | static int pl011_startup(struct uart_port *port) |
1676 | { | |
a5820c24 DT |
1677 | struct uart_amba_port *uap = |
1678 | container_of(port, struct uart_amba_port, port); | |
734745ca | 1679 | unsigned int cr; |
b3564c2c AV |
1680 | int retval; |
1681 | ||
1682 | retval = pl011_hwinit(port); | |
1683 | if (retval) | |
1684 | goto clk_dis; | |
1685 | ||
867b8e8e | 1686 | retval = pl011_allocate_irq(uap); |
1da177e4 LT |
1687 | if (retval) |
1688 | goto clk_dis; | |
1689 | ||
9f25bc51 | 1690 | pl011_write(uap->vendor->ifls, uap, REG_IFLS); |
1da177e4 | 1691 | |
734745ca | 1692 | spin_lock_irq(&uap->port.lock); |
570d2910 | 1693 | |
d8d8ffa4 SKS |
1694 | /* restore RTS and DTR */ |
1695 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); | |
1696 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
9f25bc51 | 1697 | pl011_write(cr, uap, REG_CR); |
1da177e4 | 1698 | |
fe433907 JM |
1699 | spin_unlock_irq(&uap->port.lock); |
1700 | ||
1da177e4 LT |
1701 | /* |
1702 | * initialise the old status of the modem signals | |
1703 | */ | |
9f25bc51 | 1704 | uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 | 1705 | |
68b65f73 RK |
1706 | /* Startup DMA */ |
1707 | pl011_dma_startup(uap); | |
1708 | ||
867b8e8e | 1709 | pl011_enable_interrupts(uap); |
1da177e4 LT |
1710 | |
1711 | return 0; | |
1712 | ||
1713 | clk_dis: | |
1c4c4394 | 1714 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
1715 | return retval; |
1716 | } | |
1717 | ||
0dd1e247 AP |
1718 | static int sbsa_uart_startup(struct uart_port *port) |
1719 | { | |
1720 | struct uart_amba_port *uap = | |
1721 | container_of(port, struct uart_amba_port, port); | |
1722 | int retval; | |
1723 | ||
1724 | retval = pl011_hwinit(port); | |
1725 | if (retval) | |
1726 | return retval; | |
1727 | ||
1728 | retval = pl011_allocate_irq(uap); | |
1729 | if (retval) | |
1730 | return retval; | |
1731 | ||
1732 | /* The SBSA UART does not support any modem status lines. */ | |
1733 | uap->old_status = 0; | |
1734 | ||
1735 | pl011_enable_interrupts(uap); | |
1736 | ||
1737 | return 0; | |
1738 | } | |
1739 | ||
ec489aa8 LW |
1740 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1741 | unsigned int lcrh) | |
1742 | { | |
f11c9841 | 1743 | unsigned long val; |
ec489aa8 | 1744 | |
b2a4e24c | 1745 | val = pl011_read(uap, lcrh); |
f11c9841 | 1746 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); |
b2a4e24c | 1747 | pl011_write(val, uap, lcrh); |
ec489aa8 LW |
1748 | } |
1749 | ||
95166a3f AP |
1750 | /* |
1751 | * disable the port. It should not disable RTS and DTR. | |
1752 | * Also RTS and DTR state should be preserved to restore | |
1753 | * it during startup(). | |
1754 | */ | |
1755 | static void pl011_disable_uart(struct uart_amba_port *uap) | |
1da177e4 | 1756 | { |
d8d8ffa4 | 1757 | unsigned int cr; |
1da177e4 | 1758 | |
3b43816f | 1759 | uap->autorts = false; |
fe433907 | 1760 | spin_lock_irq(&uap->port.lock); |
9f25bc51 | 1761 | cr = pl011_read(uap, REG_CR); |
d8d8ffa4 SKS |
1762 | uap->old_cr = cr; |
1763 | cr &= UART011_CR_RTS | UART011_CR_DTR; | |
1764 | cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
9f25bc51 | 1765 | pl011_write(cr, uap, REG_CR); |
fe433907 | 1766 | spin_unlock_irq(&uap->port.lock); |
1da177e4 LT |
1767 | |
1768 | /* | |
1769 | * disable break condition and fifos | |
1770 | */ | |
e4df9a80 | 1771 | pl011_shutdown_channel(uap, REG_LCRH_RX); |
7fe9a5a9 | 1772 | if (pl011_split_lcrh(uap)) |
e4df9a80 | 1773 | pl011_shutdown_channel(uap, REG_LCRH_TX); |
95166a3f AP |
1774 | } |
1775 | ||
1776 | static void pl011_disable_interrupts(struct uart_amba_port *uap) | |
1777 | { | |
1778 | spin_lock_irq(&uap->port.lock); | |
1779 | ||
1780 | /* mask all interrupts and clear all pending ones */ | |
1781 | uap->im = 0; | |
9f25bc51 RK |
1782 | pl011_write(uap->im, uap, REG_IMSC); |
1783 | pl011_write(0xffff, uap, REG_ICR); | |
95166a3f AP |
1784 | |
1785 | spin_unlock_irq(&uap->port.lock); | |
1786 | } | |
1787 | ||
1788 | static void pl011_shutdown(struct uart_port *port) | |
1789 | { | |
1790 | struct uart_amba_port *uap = | |
1791 | container_of(port, struct uart_amba_port, port); | |
1792 | ||
1793 | pl011_disable_interrupts(uap); | |
1794 | ||
1795 | pl011_dma_shutdown(uap); | |
1796 | ||
1797 | free_irq(uap->port.irq, uap); | |
1798 | ||
1799 | pl011_disable_uart(uap); | |
1da177e4 LT |
1800 | |
1801 | /* | |
1802 | * Shut down the clock producer | |
1803 | */ | |
1c4c4394 | 1804 | clk_disable_unprepare(uap->clk); |
78d80c5a | 1805 | /* Optionally let pins go into sleep states */ |
2b996fc5 | 1806 | pinctrl_pm_select_sleep_state(port->dev); |
c16d51a3 | 1807 | |
574de559 | 1808 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
1809 | struct amba_pl011_data *plat; |
1810 | ||
574de559 | 1811 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
1812 | if (plat->exit) |
1813 | plat->exit(); | |
1814 | } | |
1815 | ||
36f339d1 PH |
1816 | if (uap->port.ops->flush_buffer) |
1817 | uap->port.ops->flush_buffer(port); | |
1da177e4 LT |
1818 | } |
1819 | ||
0dd1e247 AP |
1820 | static void sbsa_uart_shutdown(struct uart_port *port) |
1821 | { | |
1822 | struct uart_amba_port *uap = | |
1823 | container_of(port, struct uart_amba_port, port); | |
1824 | ||
1825 | pl011_disable_interrupts(uap); | |
1826 | ||
1827 | free_irq(uap->port.irq, uap); | |
1828 | ||
1829 | if (uap->port.ops->flush_buffer) | |
1830 | uap->port.ops->flush_buffer(port); | |
1831 | } | |
1832 | ||
ef5a9358 AP |
1833 | static void |
1834 | pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios) | |
1835 | { | |
1836 | port->read_status_mask = UART011_DR_OE | 255; | |
1837 | if (termios->c_iflag & INPCK) | |
1838 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; | |
1839 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) | |
1840 | port->read_status_mask |= UART011_DR_BE; | |
1841 | ||
1842 | /* | |
1843 | * Characters to ignore | |
1844 | */ | |
1845 | port->ignore_status_mask = 0; | |
1846 | if (termios->c_iflag & IGNPAR) | |
1847 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; | |
1848 | if (termios->c_iflag & IGNBRK) { | |
1849 | port->ignore_status_mask |= UART011_DR_BE; | |
1850 | /* | |
1851 | * If we're ignoring parity and break indicators, | |
1852 | * ignore overruns too (for real raw support). | |
1853 | */ | |
1854 | if (termios->c_iflag & IGNPAR) | |
1855 | port->ignore_status_mask |= UART011_DR_OE; | |
1856 | } | |
1857 | ||
1858 | /* | |
1859 | * Ignore all characters if CREAD is not set. | |
1860 | */ | |
1861 | if ((termios->c_cflag & CREAD) == 0) | |
1862 | port->ignore_status_mask |= UART_DUMMY_DR_RX; | |
1863 | } | |
1864 | ||
1da177e4 | 1865 | static void |
606d099c AC |
1866 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1867 | struct ktermios *old) | |
1da177e4 | 1868 | { |
a5820c24 DT |
1869 | struct uart_amba_port *uap = |
1870 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1871 | unsigned int lcr_h, old_cr; |
1872 | unsigned long flags; | |
c19f12b5 RK |
1873 | unsigned int baud, quot, clkdiv; |
1874 | ||
1875 | if (uap->vendor->oversampling) | |
1876 | clkdiv = 8; | |
1877 | else | |
1878 | clkdiv = 16; | |
1da177e4 LT |
1879 | |
1880 | /* | |
1881 | * Ask the core to calculate the divisor for us. | |
1882 | */ | |
ac3e3fb4 | 1883 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1884 | port->uartclk / clkdiv); |
89fa28db | 1885 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1886 | /* |
1887 | * Adjust RX DMA polling rate with baud rate if not specified. | |
1888 | */ | |
1889 | if (uap->dmarx.auto_poll_rate) | |
1890 | uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); | |
89fa28db | 1891 | #endif |
ac3e3fb4 LW |
1892 | |
1893 | if (baud > port->uartclk/16) | |
1894 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1895 | else | |
1896 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1897 | |
1898 | switch (termios->c_cflag & CSIZE) { | |
1899 | case CS5: | |
1900 | lcr_h = UART01x_LCRH_WLEN_5; | |
1901 | break; | |
1902 | case CS6: | |
1903 | lcr_h = UART01x_LCRH_WLEN_6; | |
1904 | break; | |
1905 | case CS7: | |
1906 | lcr_h = UART01x_LCRH_WLEN_7; | |
1907 | break; | |
1908 | default: // CS8 | |
1909 | lcr_h = UART01x_LCRH_WLEN_8; | |
1910 | break; | |
1911 | } | |
1912 | if (termios->c_cflag & CSTOPB) | |
1913 | lcr_h |= UART01x_LCRH_STP2; | |
1914 | if (termios->c_cflag & PARENB) { | |
1915 | lcr_h |= UART01x_LCRH_PEN; | |
1916 | if (!(termios->c_cflag & PARODD)) | |
1917 | lcr_h |= UART01x_LCRH_EPS; | |
1918 | } | |
ffca2b11 | 1919 | if (uap->fifosize > 1) |
1da177e4 LT |
1920 | lcr_h |= UART01x_LCRH_FEN; |
1921 | ||
1922 | spin_lock_irqsave(&port->lock, flags); | |
1923 | ||
1924 | /* | |
1925 | * Update the per-port timeout. | |
1926 | */ | |
1927 | uart_update_timeout(port, termios->c_cflag, baud); | |
1928 | ||
ef5a9358 | 1929 | pl011_setup_status_masks(port, termios); |
1da177e4 LT |
1930 | |
1931 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1932 | pl011_enable_ms(port); | |
1933 | ||
1934 | /* first, disable everything */ | |
9f25bc51 RK |
1935 | old_cr = pl011_read(uap, REG_CR); |
1936 | pl011_write(0, uap, REG_CR); | |
1da177e4 | 1937 | |
3b43816f RV |
1938 | if (termios->c_cflag & CRTSCTS) { |
1939 | if (old_cr & UART011_CR_RTS) | |
1940 | old_cr |= UART011_CR_RTSEN; | |
1941 | ||
1942 | old_cr |= UART011_CR_CTSEN; | |
1943 | uap->autorts = true; | |
1944 | } else { | |
1945 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1946 | uap->autorts = false; | |
1947 | } | |
1948 | ||
c19f12b5 RK |
1949 | if (uap->vendor->oversampling) { |
1950 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1951 | old_cr |= ST_UART011_CR_OVSFACT; |
1952 | else | |
1953 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1954 | } | |
1955 | ||
c5dd553b LW |
1956 | /* |
1957 | * Workaround for the ST Micro oversampling variants to | |
1958 | * increase the bitrate slightly, by lowering the divisor, | |
1959 | * to avoid delayed sampling of start bit at high speeds, | |
1960 | * else we see data corruption. | |
1961 | */ | |
1962 | if (uap->vendor->oversampling) { | |
1963 | if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) | |
1964 | quot -= 1; | |
1965 | else if ((baud > 3250000) && (quot > 2)) | |
1966 | quot -= 2; | |
1967 | } | |
1da177e4 | 1968 | /* Set baud rate */ |
9f25bc51 RK |
1969 | pl011_write(quot & 0x3f, uap, REG_FBRD); |
1970 | pl011_write(quot >> 6, uap, REG_IBRD); | |
1da177e4 LT |
1971 | |
1972 | /* | |
1973 | * ----------v----------v----------v----------v----- | |
e4df9a80 | 1974 | * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER |
9f25bc51 | 1975 | * REG_FBRD & REG_IBRD. |
1da177e4 LT |
1976 | * ----------^----------^----------^----------^----- |
1977 | */ | |
b60f2f66 | 1978 | pl011_write_lcr_h(uap, lcr_h); |
9f25bc51 | 1979 | pl011_write(old_cr, uap, REG_CR); |
1da177e4 LT |
1980 | |
1981 | spin_unlock_irqrestore(&port->lock, flags); | |
1982 | } | |
1983 | ||
0dd1e247 AP |
1984 | static void |
1985 | sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios, | |
1986 | struct ktermios *old) | |
1987 | { | |
1988 | struct uart_amba_port *uap = | |
1989 | container_of(port, struct uart_amba_port, port); | |
1990 | unsigned long flags; | |
1991 | ||
1992 | tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud); | |
1993 | ||
1994 | /* The SBSA UART only supports 8n1 without hardware flow control. */ | |
1995 | termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); | |
1996 | termios->c_cflag &= ~(CMSPAR | CRTSCTS); | |
1997 | termios->c_cflag |= CS8 | CLOCAL; | |
1998 | ||
1999 | spin_lock_irqsave(&port->lock, flags); | |
2000 | uart_update_timeout(port, CS8, uap->fixed_baud); | |
2001 | pl011_setup_status_masks(port, termios); | |
2002 | spin_unlock_irqrestore(&port->lock, flags); | |
2003 | } | |
2004 | ||
1da177e4 LT |
2005 | static const char *pl011_type(struct uart_port *port) |
2006 | { | |
a5820c24 DT |
2007 | struct uart_amba_port *uap = |
2008 | container_of(port, struct uart_amba_port, port); | |
e8a7ba86 | 2009 | return uap->port.type == PORT_AMBA ? uap->type : NULL; |
1da177e4 LT |
2010 | } |
2011 | ||
2012 | /* | |
2013 | * Release the memory region(s) being used by 'port' | |
2014 | */ | |
e643f87f | 2015 | static void pl011_release_port(struct uart_port *port) |
1da177e4 LT |
2016 | { |
2017 | release_mem_region(port->mapbase, SZ_4K); | |
2018 | } | |
2019 | ||
2020 | /* | |
2021 | * Request the memory region(s) being used by 'port' | |
2022 | */ | |
e643f87f | 2023 | static int pl011_request_port(struct uart_port *port) |
1da177e4 LT |
2024 | { |
2025 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
2026 | != NULL ? 0 : -EBUSY; | |
2027 | } | |
2028 | ||
2029 | /* | |
2030 | * Configure/autoconfigure the port. | |
2031 | */ | |
e643f87f | 2032 | static void pl011_config_port(struct uart_port *port, int flags) |
1da177e4 LT |
2033 | { |
2034 | if (flags & UART_CONFIG_TYPE) { | |
2035 | port->type = PORT_AMBA; | |
e643f87f | 2036 | pl011_request_port(port); |
1da177e4 LT |
2037 | } |
2038 | } | |
2039 | ||
2040 | /* | |
2041 | * verify the new serial_struct (for TIOCSSERIAL). | |
2042 | */ | |
e643f87f | 2043 | static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) |
1da177e4 LT |
2044 | { |
2045 | int ret = 0; | |
2046 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
2047 | ret = -EINVAL; | |
a62c4133 | 2048 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
2049 | ret = -EINVAL; |
2050 | if (ser->baud_base < 9600) | |
2051 | ret = -EINVAL; | |
2052 | return ret; | |
2053 | } | |
2054 | ||
2055 | static struct uart_ops amba_pl011_pops = { | |
e643f87f | 2056 | .tx_empty = pl011_tx_empty, |
1da177e4 | 2057 | .set_mctrl = pl011_set_mctrl, |
e643f87f | 2058 | .get_mctrl = pl011_get_mctrl, |
1da177e4 LT |
2059 | .stop_tx = pl011_stop_tx, |
2060 | .start_tx = pl011_start_tx, | |
2061 | .stop_rx = pl011_stop_rx, | |
2062 | .enable_ms = pl011_enable_ms, | |
2063 | .break_ctl = pl011_break_ctl, | |
2064 | .startup = pl011_startup, | |
2065 | .shutdown = pl011_shutdown, | |
68b65f73 | 2066 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
2067 | .set_termios = pl011_set_termios, |
2068 | .type = pl011_type, | |
e643f87f LW |
2069 | .release_port = pl011_release_port, |
2070 | .request_port = pl011_request_port, | |
2071 | .config_port = pl011_config_port, | |
2072 | .verify_port = pl011_verify_port, | |
84b5ae15 | 2073 | #ifdef CONFIG_CONSOLE_POLL |
b3564c2c | 2074 | .poll_init = pl011_hwinit, |
e643f87f LW |
2075 | .poll_get_char = pl011_get_poll_char, |
2076 | .poll_put_char = pl011_put_poll_char, | |
84b5ae15 | 2077 | #endif |
1da177e4 LT |
2078 | }; |
2079 | ||
0dd1e247 AP |
2080 | static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
2081 | { | |
2082 | } | |
2083 | ||
2084 | static unsigned int sbsa_uart_get_mctrl(struct uart_port *port) | |
2085 | { | |
2086 | return 0; | |
2087 | } | |
2088 | ||
2089 | static const struct uart_ops sbsa_uart_pops = { | |
2090 | .tx_empty = pl011_tx_empty, | |
2091 | .set_mctrl = sbsa_uart_set_mctrl, | |
2092 | .get_mctrl = sbsa_uart_get_mctrl, | |
2093 | .stop_tx = pl011_stop_tx, | |
2094 | .start_tx = pl011_start_tx, | |
2095 | .stop_rx = pl011_stop_rx, | |
2096 | .startup = sbsa_uart_startup, | |
2097 | .shutdown = sbsa_uart_shutdown, | |
2098 | .set_termios = sbsa_uart_set_termios, | |
2099 | .type = pl011_type, | |
2100 | .release_port = pl011_release_port, | |
2101 | .request_port = pl011_request_port, | |
2102 | .config_port = pl011_config_port, | |
2103 | .verify_port = pl011_verify_port, | |
2104 | #ifdef CONFIG_CONSOLE_POLL | |
2105 | .poll_init = pl011_hwinit, | |
2106 | .poll_get_char = pl011_get_poll_char, | |
2107 | .poll_put_char = pl011_put_poll_char, | |
2108 | #endif | |
2109 | }; | |
2110 | ||
1da177e4 LT |
2111 | static struct uart_amba_port *amba_ports[UART_NR]; |
2112 | ||
2113 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
2114 | ||
d358788f | 2115 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 2116 | { |
a5820c24 DT |
2117 | struct uart_amba_port *uap = |
2118 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 2119 | |
9f25bc51 | 2120 | while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) |
d358788f | 2121 | barrier(); |
9f25bc51 | 2122 | pl011_write(ch, uap, REG_DR); |
1da177e4 LT |
2123 | } |
2124 | ||
2125 | static void | |
2126 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
2127 | { | |
2128 | struct uart_amba_port *uap = amba_ports[co->index]; | |
71eec483 | 2129 | unsigned int status, old_cr = 0, new_cr; |
ef605fdb RV |
2130 | unsigned long flags; |
2131 | int locked = 1; | |
1da177e4 LT |
2132 | |
2133 | clk_enable(uap->clk); | |
2134 | ||
ef605fdb RV |
2135 | local_irq_save(flags); |
2136 | if (uap->port.sysrq) | |
2137 | locked = 0; | |
2138 | else if (oops_in_progress) | |
2139 | locked = spin_trylock(&uap->port.lock); | |
2140 | else | |
2141 | spin_lock(&uap->port.lock); | |
2142 | ||
1da177e4 LT |
2143 | /* |
2144 | * First save the CR then disable the interrupts | |
2145 | */ | |
71eec483 | 2146 | if (!uap->vendor->always_enabled) { |
9f25bc51 | 2147 | old_cr = pl011_read(uap, REG_CR); |
71eec483 AP |
2148 | new_cr = old_cr & ~UART011_CR_CTSEN; |
2149 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
9f25bc51 | 2150 | pl011_write(new_cr, uap, REG_CR); |
71eec483 | 2151 | } |
1da177e4 | 2152 | |
d358788f | 2153 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
2154 | |
2155 | /* | |
2156 | * Finally, wait for transmitter to become empty | |
2157 | * and restore the TCR | |
2158 | */ | |
2159 | do { | |
9f25bc51 | 2160 | status = pl011_read(uap, REG_FR); |
062a68a5 | 2161 | } while (status & UART01x_FR_BUSY); |
71eec483 | 2162 | if (!uap->vendor->always_enabled) |
9f25bc51 | 2163 | pl011_write(old_cr, uap, REG_CR); |
1da177e4 | 2164 | |
ef605fdb RV |
2165 | if (locked) |
2166 | spin_unlock(&uap->port.lock); | |
2167 | local_irq_restore(flags); | |
2168 | ||
1da177e4 LT |
2169 | clk_disable(uap->clk); |
2170 | } | |
2171 | ||
2172 | static void __init | |
2173 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
2174 | int *parity, int *bits) | |
2175 | { | |
9f25bc51 | 2176 | if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) { |
1da177e4 LT |
2177 | unsigned int lcr_h, ibrd, fbrd; |
2178 | ||
e4df9a80 | 2179 | lcr_h = pl011_read(uap, REG_LCRH_TX); |
1da177e4 LT |
2180 | |
2181 | *parity = 'n'; | |
2182 | if (lcr_h & UART01x_LCRH_PEN) { | |
2183 | if (lcr_h & UART01x_LCRH_EPS) | |
2184 | *parity = 'e'; | |
2185 | else | |
2186 | *parity = 'o'; | |
2187 | } | |
2188 | ||
2189 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
2190 | *bits = 7; | |
2191 | else | |
2192 | *bits = 8; | |
2193 | ||
9f25bc51 RK |
2194 | ibrd = pl011_read(uap, REG_IBRD); |
2195 | fbrd = pl011_read(uap, REG_FBRD); | |
1da177e4 LT |
2196 | |
2197 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 2198 | |
c19f12b5 | 2199 | if (uap->vendor->oversampling) { |
9f25bc51 | 2200 | if (pl011_read(uap, REG_CR) |
ac3e3fb4 LW |
2201 | & ST_UART011_CR_OVSFACT) |
2202 | *baud *= 2; | |
2203 | } | |
1da177e4 LT |
2204 | } |
2205 | } | |
2206 | ||
2207 | static int __init pl011_console_setup(struct console *co, char *options) | |
2208 | { | |
2209 | struct uart_amba_port *uap; | |
2210 | int baud = 38400; | |
2211 | int bits = 8; | |
2212 | int parity = 'n'; | |
2213 | int flow = 'n'; | |
4b4851c6 | 2214 | int ret; |
1da177e4 LT |
2215 | |
2216 | /* | |
2217 | * Check whether an invalid uart number has been specified, and | |
2218 | * if so, search for the first available port that does have | |
2219 | * console support. | |
2220 | */ | |
2221 | if (co->index >= UART_NR) | |
2222 | co->index = 0; | |
2223 | uap = amba_ports[co->index]; | |
d28122a5 RK |
2224 | if (!uap) |
2225 | return -ENODEV; | |
1da177e4 | 2226 | |
78d80c5a | 2227 | /* Allow pins to be muxed in and configured */ |
2b996fc5 | 2228 | pinctrl_pm_select_default_state(uap->port.dev); |
78d80c5a | 2229 | |
4b4851c6 RK |
2230 | ret = clk_prepare(uap->clk); |
2231 | if (ret) | |
2232 | return ret; | |
2233 | ||
574de559 | 2234 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
2235 | struct amba_pl011_data *plat; |
2236 | ||
574de559 | 2237 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
2238 | if (plat->init) |
2239 | plat->init(); | |
2240 | } | |
2241 | ||
1da177e4 LT |
2242 | uap->port.uartclk = clk_get_rate(uap->clk); |
2243 | ||
cefc2d1d AP |
2244 | if (uap->vendor->fixed_options) { |
2245 | baud = uap->fixed_baud; | |
2246 | } else { | |
2247 | if (options) | |
2248 | uart_parse_options(options, | |
2249 | &baud, &parity, &bits, &flow); | |
2250 | else | |
2251 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
2252 | } | |
1da177e4 LT |
2253 | |
2254 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
2255 | } | |
2256 | ||
2d93486c | 2257 | static struct uart_driver amba_reg; |
1da177e4 LT |
2258 | static struct console amba_console = { |
2259 | .name = "ttyAMA", | |
2260 | .write = pl011_console_write, | |
2261 | .device = uart_console_device, | |
2262 | .setup = pl011_console_setup, | |
2263 | .flags = CON_PRINTBUFFER, | |
2264 | .index = -1, | |
2265 | .data = &amba_reg, | |
2266 | }; | |
2267 | ||
2268 | #define AMBA_CONSOLE (&amba_console) | |
0d3c673e RH |
2269 | |
2270 | static void pl011_putc(struct uart_port *port, int c) | |
2271 | { | |
9f25bc51 | 2272 | while (readl(port->membase + REG_FR) & UART01x_FR_TXFF) |
0d3c673e | 2273 | ; |
9f25bc51 RK |
2274 | writeb(c, port->membase + REG_DR); |
2275 | while (readl(port->membase + REG_FR) & UART01x_FR_BUSY) | |
0d3c673e RH |
2276 | ; |
2277 | } | |
2278 | ||
2279 | static void pl011_early_write(struct console *con, const char *s, unsigned n) | |
2280 | { | |
2281 | struct earlycon_device *dev = con->data; | |
2282 | ||
2283 | uart_console_write(&dev->port, s, n, pl011_putc); | |
2284 | } | |
2285 | ||
2286 | static int __init pl011_early_console_setup(struct earlycon_device *device, | |
2287 | const char *opt) | |
2288 | { | |
2289 | if (!device->port.membase) | |
2290 | return -ENODEV; | |
2291 | ||
2292 | device->con->write = pl011_early_write; | |
2293 | return 0; | |
2294 | } | |
2295 | EARLYCON_DECLARE(pl011, pl011_early_console_setup); | |
45e0f0f5 | 2296 | OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); |
0d3c673e | 2297 | |
1da177e4 LT |
2298 | #else |
2299 | #define AMBA_CONSOLE NULL | |
2300 | #endif | |
2301 | ||
2302 | static struct uart_driver amba_reg = { | |
2303 | .owner = THIS_MODULE, | |
2304 | .driver_name = "ttyAMA", | |
2305 | .dev_name = "ttyAMA", | |
2306 | .major = SERIAL_AMBA_MAJOR, | |
2307 | .minor = SERIAL_AMBA_MINOR, | |
2308 | .nr = UART_NR, | |
2309 | .cons = AMBA_CONSOLE, | |
2310 | }; | |
2311 | ||
32614aad ML |
2312 | static int pl011_probe_dt_alias(int index, struct device *dev) |
2313 | { | |
2314 | struct device_node *np; | |
2315 | static bool seen_dev_with_alias = false; | |
2316 | static bool seen_dev_without_alias = false; | |
2317 | int ret = index; | |
2318 | ||
2319 | if (!IS_ENABLED(CONFIG_OF)) | |
2320 | return ret; | |
2321 | ||
2322 | np = dev->of_node; | |
2323 | if (!np) | |
2324 | return ret; | |
2325 | ||
2326 | ret = of_alias_get_id(np, "serial"); | |
2327 | if (IS_ERR_VALUE(ret)) { | |
2328 | seen_dev_without_alias = true; | |
2329 | ret = index; | |
2330 | } else { | |
2331 | seen_dev_with_alias = true; | |
2332 | if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { | |
2333 | dev_warn(dev, "requested serial port %d not available.\n", ret); | |
2334 | ret = index; | |
2335 | } | |
2336 | } | |
2337 | ||
2338 | if (seen_dev_with_alias && seen_dev_without_alias) | |
2339 | dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); | |
2340 | ||
2341 | return ret; | |
2342 | } | |
2343 | ||
49bb3c86 AP |
2344 | /* unregisters the driver also if no more ports are left */ |
2345 | static void pl011_unregister_port(struct uart_amba_port *uap) | |
2346 | { | |
2347 | int i; | |
2348 | bool busy = false; | |
2349 | ||
2350 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) { | |
2351 | if (amba_ports[i] == uap) | |
2352 | amba_ports[i] = NULL; | |
2353 | else if (amba_ports[i]) | |
2354 | busy = true; | |
2355 | } | |
2356 | pl011_dma_remove(uap); | |
2357 | if (!busy) | |
2358 | uart_unregister_driver(&amba_reg); | |
2359 | } | |
2360 | ||
3873e2d7 | 2361 | static int pl011_find_free_port(void) |
1da177e4 | 2362 | { |
3873e2d7 | 2363 | int i; |
1da177e4 LT |
2364 | |
2365 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2366 | if (amba_ports[i] == NULL) | |
3873e2d7 | 2367 | return i; |
1da177e4 | 2368 | |
3873e2d7 AP |
2369 | return -EBUSY; |
2370 | } | |
1da177e4 | 2371 | |
3873e2d7 AP |
2372 | static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap, |
2373 | struct resource *mmiobase, int index) | |
2374 | { | |
2375 | void __iomem *base; | |
32614aad | 2376 | |
3873e2d7 | 2377 | base = devm_ioremap_resource(dev, mmiobase); |
97a60eac KK |
2378 | if (IS_ERR(base)) |
2379 | return PTR_ERR(base); | |
1da177e4 | 2380 | |
3873e2d7 | 2381 | index = pl011_probe_dt_alias(index, dev); |
1da177e4 | 2382 | |
d8d8ffa4 | 2383 | uap->old_cr = 0; |
3873e2d7 AP |
2384 | uap->port.dev = dev; |
2385 | uap->port.mapbase = mmiobase->start; | |
1da177e4 LT |
2386 | uap->port.membase = base; |
2387 | uap->port.iotype = UPIO_MEM; | |
ffca2b11 | 2388 | uap->port.fifosize = uap->fifosize; |
1da177e4 | 2389 | uap->port.flags = UPF_BOOT_AUTOCONF; |
3873e2d7 | 2390 | uap->port.line = index; |
1da177e4 | 2391 | |
3873e2d7 | 2392 | amba_ports[index] = uap; |
c3d8b76f | 2393 | |
3873e2d7 AP |
2394 | return 0; |
2395 | } | |
e8a7ba86 | 2396 | |
3873e2d7 AP |
2397 | static int pl011_register_port(struct uart_amba_port *uap) |
2398 | { | |
2399 | int ret; | |
1da177e4 | 2400 | |
3873e2d7 | 2401 | /* Ensure interrupts from this UART are masked and cleared */ |
9f25bc51 RK |
2402 | pl011_write(0, uap, REG_IMSC); |
2403 | pl011_write(0xffff, uap, REG_ICR); | |
ef2889f7 TB |
2404 | |
2405 | if (!amba_reg.state) { | |
2406 | ret = uart_register_driver(&amba_reg); | |
2407 | if (ret < 0) { | |
3873e2d7 | 2408 | dev_err(uap->port.dev, |
1c9be310 | 2409 | "Failed to register AMBA-PL011 driver\n"); |
ef2889f7 TB |
2410 | return ret; |
2411 | } | |
2412 | } | |
2413 | ||
1da177e4 | 2414 | ret = uart_add_one_port(&amba_reg, &uap->port); |
49bb3c86 AP |
2415 | if (ret) |
2416 | pl011_unregister_port(uap); | |
7f6d942a | 2417 | |
1da177e4 LT |
2418 | return ret; |
2419 | } | |
2420 | ||
3873e2d7 AP |
2421 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
2422 | { | |
2423 | struct uart_amba_port *uap; | |
2424 | struct vendor_data *vendor = id->data; | |
2425 | int portnr, ret; | |
2426 | ||
2427 | portnr = pl011_find_free_port(); | |
2428 | if (portnr < 0) | |
2429 | return portnr; | |
2430 | ||
2431 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), | |
2432 | GFP_KERNEL); | |
2433 | if (!uap) | |
2434 | return -ENOMEM; | |
2435 | ||
2436 | uap->clk = devm_clk_get(&dev->dev, NULL); | |
2437 | if (IS_ERR(uap->clk)) | |
2438 | return PTR_ERR(uap->clk); | |
2439 | ||
439403bd | 2440 | uap->reg_offset = vendor->reg_offset; |
3873e2d7 | 2441 | uap->vendor = vendor; |
3873e2d7 AP |
2442 | uap->fifosize = vendor->get_fifosize(dev); |
2443 | uap->port.irq = dev->irq[0]; | |
2444 | uap->port.ops = &amba_pl011_pops; | |
2445 | ||
2446 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); | |
2447 | ||
2448 | ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr); | |
2449 | if (ret) | |
2450 | return ret; | |
2451 | ||
2452 | amba_set_drvdata(dev, uap); | |
2453 | ||
2454 | return pl011_register_port(uap); | |
2455 | } | |
2456 | ||
1da177e4 LT |
2457 | static int pl011_remove(struct amba_device *dev) |
2458 | { | |
2459 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1da177e4 | 2460 | |
1da177e4 | 2461 | uart_remove_one_port(&amba_reg, &uap->port); |
49bb3c86 | 2462 | pl011_unregister_port(uap); |
1da177e4 LT |
2463 | return 0; |
2464 | } | |
2465 | ||
d0ce850d UH |
2466 | #ifdef CONFIG_PM_SLEEP |
2467 | static int pl011_suspend(struct device *dev) | |
b736b89f | 2468 | { |
d0ce850d | 2469 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2470 | |
2471 | if (!uap) | |
2472 | return -EINVAL; | |
2473 | ||
2474 | return uart_suspend_port(&amba_reg, &uap->port); | |
2475 | } | |
2476 | ||
d0ce850d | 2477 | static int pl011_resume(struct device *dev) |
b736b89f | 2478 | { |
d0ce850d | 2479 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2480 | |
2481 | if (!uap) | |
2482 | return -EINVAL; | |
2483 | ||
2484 | return uart_resume_port(&amba_reg, &uap->port); | |
2485 | } | |
2486 | #endif | |
2487 | ||
d0ce850d UH |
2488 | static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); |
2489 | ||
0dd1e247 AP |
2490 | static int sbsa_uart_probe(struct platform_device *pdev) |
2491 | { | |
2492 | struct uart_amba_port *uap; | |
2493 | struct resource *r; | |
2494 | int portnr, ret; | |
2495 | int baudrate; | |
2496 | ||
2497 | /* | |
2498 | * Check the mandatory baud rate parameter in the DT node early | |
2499 | * so that we can easily exit with the error. | |
2500 | */ | |
2501 | if (pdev->dev.of_node) { | |
2502 | struct device_node *np = pdev->dev.of_node; | |
2503 | ||
2504 | ret = of_property_read_u32(np, "current-speed", &baudrate); | |
2505 | if (ret) | |
2506 | return ret; | |
2507 | } else { | |
2508 | baudrate = 115200; | |
2509 | } | |
2510 | ||
2511 | portnr = pl011_find_free_port(); | |
2512 | if (portnr < 0) | |
2513 | return portnr; | |
2514 | ||
2515 | uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port), | |
2516 | GFP_KERNEL); | |
2517 | if (!uap) | |
2518 | return -ENOMEM; | |
2519 | ||
439403bd | 2520 | uap->reg_offset = vendor_sbsa.reg_offset; |
0dd1e247 AP |
2521 | uap->vendor = &vendor_sbsa; |
2522 | uap->fifosize = 32; | |
2523 | uap->port.irq = platform_get_irq(pdev, 0); | |
2524 | uap->port.ops = &sbsa_uart_pops; | |
2525 | uap->fixed_baud = baudrate; | |
2526 | ||
2527 | snprintf(uap->type, sizeof(uap->type), "SBSA"); | |
2528 | ||
2529 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2530 | ||
2531 | ret = pl011_setup_port(&pdev->dev, uap, r, portnr); | |
2532 | if (ret) | |
2533 | return ret; | |
2534 | ||
2535 | platform_set_drvdata(pdev, uap); | |
2536 | ||
2537 | return pl011_register_port(uap); | |
2538 | } | |
2539 | ||
2540 | static int sbsa_uart_remove(struct platform_device *pdev) | |
2541 | { | |
2542 | struct uart_amba_port *uap = platform_get_drvdata(pdev); | |
2543 | ||
2544 | uart_remove_one_port(&amba_reg, &uap->port); | |
2545 | pl011_unregister_port(uap); | |
2546 | return 0; | |
2547 | } | |
2548 | ||
2549 | static const struct of_device_id sbsa_uart_of_match[] = { | |
2550 | { .compatible = "arm,sbsa-uart", }, | |
2551 | {}, | |
2552 | }; | |
2553 | MODULE_DEVICE_TABLE(of, sbsa_uart_of_match); | |
2554 | ||
3db9ab0b GG |
2555 | static const struct acpi_device_id sbsa_uart_acpi_match[] = { |
2556 | { "ARMH0011", 0 }, | |
2557 | {}, | |
2558 | }; | |
2559 | MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match); | |
2560 | ||
0dd1e247 AP |
2561 | static struct platform_driver arm_sbsa_uart_platform_driver = { |
2562 | .probe = sbsa_uart_probe, | |
2563 | .remove = sbsa_uart_remove, | |
2564 | .driver = { | |
2565 | .name = "sbsa-uart", | |
2566 | .of_match_table = of_match_ptr(sbsa_uart_of_match), | |
3db9ab0b | 2567 | .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match), |
0dd1e247 AP |
2568 | }, |
2569 | }; | |
2570 | ||
2c39c9e1 | 2571 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
2572 | { |
2573 | .id = 0x00041011, | |
2574 | .mask = 0x000fffff, | |
5926a295 AR |
2575 | .data = &vendor_arm, |
2576 | }, | |
2577 | { | |
2578 | .id = 0x00380802, | |
2579 | .mask = 0x00ffffff, | |
2580 | .data = &vendor_st, | |
1da177e4 LT |
2581 | }, |
2582 | { 0, 0 }, | |
2583 | }; | |
2584 | ||
60f7a33b DM |
2585 | MODULE_DEVICE_TABLE(amba, pl011_ids); |
2586 | ||
1da177e4 LT |
2587 | static struct amba_driver pl011_driver = { |
2588 | .drv = { | |
2589 | .name = "uart-pl011", | |
d0ce850d | 2590 | .pm = &pl011_dev_pm_ops, |
1da177e4 LT |
2591 | }, |
2592 | .id_table = pl011_ids, | |
2593 | .probe = pl011_probe, | |
2594 | .remove = pl011_remove, | |
2595 | }; | |
2596 | ||
2597 | static int __init pl011_init(void) | |
2598 | { | |
1da177e4 LT |
2599 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); |
2600 | ||
0dd1e247 AP |
2601 | if (platform_driver_register(&arm_sbsa_uart_platform_driver)) |
2602 | pr_warn("could not register SBSA UART platform driver\n"); | |
062a68a5 | 2603 | return amba_driver_register(&pl011_driver); |
1da177e4 LT |
2604 | } |
2605 | ||
2606 | static void __exit pl011_exit(void) | |
2607 | { | |
0dd1e247 | 2608 | platform_driver_unregister(&arm_sbsa_uart_platform_driver); |
1da177e4 | 2609 | amba_driver_unregister(&pl011_driver); |
1da177e4 LT |
2610 | } |
2611 | ||
4dd9e742 AR |
2612 | /* |
2613 | * While this can be a module, if builtin it's most likely the console | |
2614 | * So let's leave module_exit but move module_init to an earlier place | |
2615 | */ | |
2616 | arch_initcall(pl011_init); | |
1da177e4 LT |
2617 | module_exit(pl011_exit); |
2618 | ||
2619 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
2620 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
2621 | MODULE_LICENSE("GPL"); |