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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for AMBA serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
68b65f73 | 8 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
1da177e4 LT |
24 | * This is a generic driver for ARM AMBA-type serial ports. They |
25 | * have a lot of 16550-like features, but are not register compatible. | |
26 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
27 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
28 | * required, these have to be supplied via some other means (eg, GPIO) | |
29 | * and hooked into this driver. | |
30 | */ | |
1da177e4 | 31 | |
cb06ff10 | 32 | |
1da177e4 LT |
33 | #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
34 | #define SUPPORT_SYSRQ | |
35 | #endif | |
36 | ||
37 | #include <linux/module.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/console.h> | |
41 | #include <linux/sysrq.h> | |
42 | #include <linux/device.h> | |
43 | #include <linux/tty.h> | |
44 | #include <linux/tty_flip.h> | |
45 | #include <linux/serial_core.h> | |
46 | #include <linux/serial.h> | |
a62c80e5 RK |
47 | #include <linux/amba/bus.h> |
48 | #include <linux/amba/serial.h> | |
f8ce2547 | 49 | #include <linux/clk.h> |
5a0e3ad6 | 50 | #include <linux/slab.h> |
68b65f73 RK |
51 | #include <linux/dmaengine.h> |
52 | #include <linux/dma-mapping.h> | |
53 | #include <linux/scatterlist.h> | |
c16d51a3 | 54 | #include <linux/delay.h> |
258aea76 | 55 | #include <linux/types.h> |
32614aad ML |
56 | #include <linux/of.h> |
57 | #include <linux/of_device.h> | |
258e0551 | 58 | #include <linux/pinctrl/consumer.h> |
cb70706c | 59 | #include <linux/sizes.h> |
de609582 | 60 | #include <linux/io.h> |
1da177e4 LT |
61 | |
62 | #define UART_NR 14 | |
63 | ||
64 | #define SERIAL_AMBA_MAJOR 204 | |
65 | #define SERIAL_AMBA_MINOR 64 | |
66 | #define SERIAL_AMBA_NR UART_NR | |
67 | ||
68 | #define AMBA_ISR_PASS_LIMIT 256 | |
69 | ||
b63d4f0f RK |
70 | #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE) |
71 | #define UART_DUMMY_DR_RX (1 << 16) | |
1da177e4 | 72 | |
5926a295 AR |
73 | /* There is by now at least one vendor with differing details, so handle it */ |
74 | struct vendor_data { | |
75 | unsigned int ifls; | |
ec489aa8 LW |
76 | unsigned int lcrh_tx; |
77 | unsigned int lcrh_rx; | |
ac3e3fb4 | 78 | bool oversampling; |
38d62436 | 79 | bool dma_threshold; |
4fd0690b | 80 | bool cts_event_workaround; |
78506f22 | 81 | |
ea33640a | 82 | unsigned int (*get_fifosize)(struct amba_device *dev); |
5926a295 AR |
83 | }; |
84 | ||
ea33640a | 85 | static unsigned int get_fifosize_arm(struct amba_device *dev) |
78506f22 | 86 | { |
ea33640a | 87 | return amba_rev(dev) < 3 ? 16 : 32; |
78506f22 JK |
88 | } |
89 | ||
5926a295 AR |
90 | static struct vendor_data vendor_arm = { |
91 | .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8, | |
ec489aa8 LW |
92 | .lcrh_tx = UART011_LCRH, |
93 | .lcrh_rx = UART011_LCRH, | |
ac3e3fb4 | 94 | .oversampling = false, |
38d62436 | 95 | .dma_threshold = false, |
4fd0690b | 96 | .cts_event_workaround = false, |
78506f22 | 97 | .get_fifosize = get_fifosize_arm, |
5926a295 AR |
98 | }; |
99 | ||
ea33640a | 100 | static unsigned int get_fifosize_st(struct amba_device *dev) |
78506f22 JK |
101 | { |
102 | return 64; | |
103 | } | |
104 | ||
5926a295 AR |
105 | static struct vendor_data vendor_st = { |
106 | .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF, | |
ec489aa8 LW |
107 | .lcrh_tx = ST_UART011_LCRH_TX, |
108 | .lcrh_rx = ST_UART011_LCRH_RX, | |
ac3e3fb4 | 109 | .oversampling = true, |
38d62436 | 110 | .dma_threshold = true, |
4fd0690b | 111 | .cts_event_workaround = true, |
78506f22 | 112 | .get_fifosize = get_fifosize_st, |
1da177e4 LT |
113 | }; |
114 | ||
68b65f73 | 115 | /* Deals with DMA transactions */ |
ead76f32 LW |
116 | |
117 | struct pl011_sgbuf { | |
118 | struct scatterlist sg; | |
119 | char *buf; | |
120 | }; | |
121 | ||
122 | struct pl011_dmarx_data { | |
123 | struct dma_chan *chan; | |
124 | struct completion complete; | |
125 | bool use_buf_b; | |
126 | struct pl011_sgbuf sgbuf_a; | |
127 | struct pl011_sgbuf sgbuf_b; | |
128 | dma_cookie_t cookie; | |
129 | bool running; | |
cb06ff10 CM |
130 | struct timer_list timer; |
131 | unsigned int last_residue; | |
132 | unsigned long last_jiffies; | |
133 | bool auto_poll_rate; | |
134 | unsigned int poll_rate; | |
135 | unsigned int poll_timeout; | |
ead76f32 LW |
136 | }; |
137 | ||
68b65f73 RK |
138 | struct pl011_dmatx_data { |
139 | struct dma_chan *chan; | |
140 | struct scatterlist sg; | |
141 | char *buf; | |
142 | bool queued; | |
143 | }; | |
144 | ||
c19f12b5 RK |
145 | /* |
146 | * We wrap our port structure around the generic uart_port. | |
147 | */ | |
148 | struct uart_amba_port { | |
149 | struct uart_port port; | |
150 | struct clk *clk; | |
151 | const struct vendor_data *vendor; | |
68b65f73 | 152 | unsigned int dmacr; /* dma control reg */ |
c19f12b5 RK |
153 | unsigned int im; /* interrupt mask */ |
154 | unsigned int old_status; | |
ffca2b11 | 155 | unsigned int fifosize; /* vendor-specific */ |
c19f12b5 RK |
156 | unsigned int lcrh_tx; /* vendor-specific */ |
157 | unsigned int lcrh_rx; /* vendor-specific */ | |
d8d8ffa4 | 158 | unsigned int old_cr; /* state during shutdown */ |
c19f12b5 RK |
159 | bool autorts; |
160 | char type[12]; | |
68b65f73 RK |
161 | #ifdef CONFIG_DMA_ENGINE |
162 | /* DMA stuff */ | |
ead76f32 LW |
163 | bool using_tx_dma; |
164 | bool using_rx_dma; | |
165 | struct pl011_dmarx_data dmarx; | |
68b65f73 RK |
166 | struct pl011_dmatx_data dmatx; |
167 | #endif | |
168 | }; | |
169 | ||
29772c4e LW |
170 | /* |
171 | * Reads up to 256 characters from the FIFO or until it's empty and | |
172 | * inserts them into the TTY layer. Returns the number of characters | |
173 | * read from the FIFO. | |
174 | */ | |
175 | static int pl011_fifo_to_tty(struct uart_amba_port *uap) | |
176 | { | |
177 | u16 status, ch; | |
178 | unsigned int flag, max_count = 256; | |
179 | int fifotaken = 0; | |
180 | ||
181 | while (max_count--) { | |
182 | status = readw(uap->port.membase + UART01x_FR); | |
183 | if (status & UART01x_FR_RXFE) | |
184 | break; | |
185 | ||
186 | /* Take chars from the FIFO and update status */ | |
187 | ch = readw(uap->port.membase + UART01x_DR) | | |
188 | UART_DUMMY_DR_RX; | |
189 | flag = TTY_NORMAL; | |
190 | uap->port.icount.rx++; | |
191 | fifotaken++; | |
192 | ||
193 | if (unlikely(ch & UART_DR_ERROR)) { | |
194 | if (ch & UART011_DR_BE) { | |
195 | ch &= ~(UART011_DR_FE | UART011_DR_PE); | |
196 | uap->port.icount.brk++; | |
197 | if (uart_handle_break(&uap->port)) | |
198 | continue; | |
199 | } else if (ch & UART011_DR_PE) | |
200 | uap->port.icount.parity++; | |
201 | else if (ch & UART011_DR_FE) | |
202 | uap->port.icount.frame++; | |
203 | if (ch & UART011_DR_OE) | |
204 | uap->port.icount.overrun++; | |
205 | ||
206 | ch &= uap->port.read_status_mask; | |
207 | ||
208 | if (ch & UART011_DR_BE) | |
209 | flag = TTY_BREAK; | |
210 | else if (ch & UART011_DR_PE) | |
211 | flag = TTY_PARITY; | |
212 | else if (ch & UART011_DR_FE) | |
213 | flag = TTY_FRAME; | |
214 | } | |
215 | ||
216 | if (uart_handle_sysrq_char(&uap->port, ch & 255)) | |
217 | continue; | |
218 | ||
219 | uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); | |
220 | } | |
221 | ||
222 | return fifotaken; | |
223 | } | |
224 | ||
225 | ||
68b65f73 RK |
226 | /* |
227 | * All the DMA operation mode stuff goes inside this ifdef. | |
228 | * This assumes that you have a generic DMA device interface, | |
229 | * no custom DMA interfaces are supported. | |
230 | */ | |
231 | #ifdef CONFIG_DMA_ENGINE | |
232 | ||
233 | #define PL011_DMA_BUFFER_SIZE PAGE_SIZE | |
234 | ||
ead76f32 LW |
235 | static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg, |
236 | enum dma_data_direction dir) | |
237 | { | |
cb06ff10 CM |
238 | dma_addr_t dma_addr; |
239 | ||
240 | sg->buf = dma_alloc_coherent(chan->device->dev, | |
241 | PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL); | |
ead76f32 LW |
242 | if (!sg->buf) |
243 | return -ENOMEM; | |
244 | ||
cb06ff10 CM |
245 | sg_init_table(&sg->sg, 1); |
246 | sg_set_page(&sg->sg, phys_to_page(dma_addr), | |
247 | PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr)); | |
248 | sg_dma_address(&sg->sg) = dma_addr; | |
ead76f32 | 249 | |
ead76f32 LW |
250 | return 0; |
251 | } | |
252 | ||
253 | static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg, | |
254 | enum dma_data_direction dir) | |
255 | { | |
256 | if (sg->buf) { | |
cb06ff10 CM |
257 | dma_free_coherent(chan->device->dev, |
258 | PL011_DMA_BUFFER_SIZE, sg->buf, | |
259 | sg_dma_address(&sg->sg)); | |
ead76f32 LW |
260 | } |
261 | } | |
262 | ||
787b0c1f | 263 | static void pl011_dma_probe_initcall(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
264 | { |
265 | /* DMA is the sole user of the platform data right now */ | |
574de559 | 266 | struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev); |
68b65f73 RK |
267 | struct dma_slave_config tx_conf = { |
268 | .dst_addr = uap->port.mapbase + UART01x_DR, | |
269 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 270 | .direction = DMA_MEM_TO_DEV, |
68b65f73 | 271 | .dst_maxburst = uap->fifosize >> 1, |
258aea76 | 272 | .device_fc = false, |
68b65f73 RK |
273 | }; |
274 | struct dma_chan *chan; | |
275 | dma_cap_mask_t mask; | |
276 | ||
787b0c1f | 277 | chan = dma_request_slave_channel(dev, "tx"); |
68b65f73 | 278 | |
68b65f73 | 279 | if (!chan) { |
787b0c1f AB |
280 | /* We need platform data */ |
281 | if (!plat || !plat->dma_filter) { | |
282 | dev_info(uap->port.dev, "no DMA platform data\n"); | |
283 | return; | |
284 | } | |
285 | ||
286 | /* Try to acquire a generic DMA engine slave TX channel */ | |
287 | dma_cap_zero(mask); | |
288 | dma_cap_set(DMA_SLAVE, mask); | |
289 | ||
290 | chan = dma_request_channel(mask, plat->dma_filter, | |
291 | plat->dma_tx_param); | |
292 | if (!chan) { | |
293 | dev_err(uap->port.dev, "no TX DMA channel!\n"); | |
294 | return; | |
295 | } | |
68b65f73 RK |
296 | } |
297 | ||
298 | dmaengine_slave_config(chan, &tx_conf); | |
299 | uap->dmatx.chan = chan; | |
300 | ||
301 | dev_info(uap->port.dev, "DMA channel TX %s\n", | |
302 | dma_chan_name(uap->dmatx.chan)); | |
ead76f32 LW |
303 | |
304 | /* Optionally make use of an RX channel as well */ | |
787b0c1f | 305 | chan = dma_request_slave_channel(dev, "rx"); |
0d3c673e | 306 | |
787b0c1f AB |
307 | if (!chan && plat->dma_rx_param) { |
308 | chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param); | |
309 | ||
310 | if (!chan) { | |
311 | dev_err(uap->port.dev, "no RX DMA channel!\n"); | |
312 | return; | |
313 | } | |
314 | } | |
315 | ||
316 | if (chan) { | |
ead76f32 LW |
317 | struct dma_slave_config rx_conf = { |
318 | .src_addr = uap->port.mapbase + UART01x_DR, | |
319 | .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE, | |
a485df4b | 320 | .direction = DMA_DEV_TO_MEM, |
b2aeb775 | 321 | .src_maxburst = uap->fifosize >> 2, |
258aea76 | 322 | .device_fc = false, |
ead76f32 LW |
323 | }; |
324 | ||
ead76f32 LW |
325 | dmaengine_slave_config(chan, &rx_conf); |
326 | uap->dmarx.chan = chan; | |
327 | ||
8f898bfd | 328 | if (plat && plat->dma_rx_poll_enable) { |
cb06ff10 CM |
329 | /* Set poll rate if specified. */ |
330 | if (plat->dma_rx_poll_rate) { | |
331 | uap->dmarx.auto_poll_rate = false; | |
332 | uap->dmarx.poll_rate = plat->dma_rx_poll_rate; | |
333 | } else { | |
334 | /* | |
335 | * 100 ms defaults to poll rate if not | |
336 | * specified. This will be adjusted with | |
337 | * the baud rate at set_termios. | |
338 | */ | |
339 | uap->dmarx.auto_poll_rate = true; | |
340 | uap->dmarx.poll_rate = 100; | |
341 | } | |
342 | /* 3 secs defaults poll_timeout if not specified. */ | |
343 | if (plat->dma_rx_poll_timeout) | |
344 | uap->dmarx.poll_timeout = | |
345 | plat->dma_rx_poll_timeout; | |
346 | else | |
347 | uap->dmarx.poll_timeout = 3000; | |
348 | } else | |
349 | uap->dmarx.auto_poll_rate = false; | |
350 | ||
ead76f32 LW |
351 | dev_info(uap->port.dev, "DMA channel RX %s\n", |
352 | dma_chan_name(uap->dmarx.chan)); | |
353 | } | |
68b65f73 RK |
354 | } |
355 | ||
356 | #ifndef MODULE | |
357 | /* | |
358 | * Stack up the UARTs and let the above initcall be done at device | |
359 | * initcall time, because the serial driver is called as an arch | |
360 | * initcall, and at this time the DMA subsystem is not yet registered. | |
361 | * At this point the driver will switch over to using DMA where desired. | |
362 | */ | |
363 | struct dma_uap { | |
364 | struct list_head node; | |
365 | struct uart_amba_port *uap; | |
787b0c1f | 366 | struct device *dev; |
c19f12b5 RK |
367 | }; |
368 | ||
68b65f73 RK |
369 | static LIST_HEAD(pl011_dma_uarts); |
370 | ||
371 | static int __init pl011_dma_initcall(void) | |
372 | { | |
373 | struct list_head *node, *tmp; | |
374 | ||
375 | list_for_each_safe(node, tmp, &pl011_dma_uarts) { | |
376 | struct dma_uap *dmau = list_entry(node, struct dma_uap, node); | |
787b0c1f | 377 | pl011_dma_probe_initcall(dmau->dev, dmau->uap); |
68b65f73 RK |
378 | list_del(node); |
379 | kfree(dmau); | |
380 | } | |
381 | return 0; | |
382 | } | |
383 | ||
384 | device_initcall(pl011_dma_initcall); | |
385 | ||
787b0c1f | 386 | static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
387 | { |
388 | struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL); | |
389 | if (dmau) { | |
390 | dmau->uap = uap; | |
787b0c1f | 391 | dmau->dev = dev; |
68b65f73 RK |
392 | list_add_tail(&dmau->node, &pl011_dma_uarts); |
393 | } | |
394 | } | |
395 | #else | |
787b0c1f | 396 | static void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 | 397 | { |
787b0c1f | 398 | pl011_dma_probe_initcall(dev, uap); |
68b65f73 RK |
399 | } |
400 | #endif | |
401 | ||
402 | static void pl011_dma_remove(struct uart_amba_port *uap) | |
403 | { | |
404 | /* TODO: remove the initcall if it has not yet executed */ | |
405 | if (uap->dmatx.chan) | |
406 | dma_release_channel(uap->dmatx.chan); | |
ead76f32 LW |
407 | if (uap->dmarx.chan) |
408 | dma_release_channel(uap->dmarx.chan); | |
68b65f73 RK |
409 | } |
410 | ||
68b65f73 RK |
411 | /* Forward declare this for the refill routine */ |
412 | static int pl011_dma_tx_refill(struct uart_amba_port *uap); | |
413 | ||
414 | /* | |
415 | * The current DMA TX buffer has been sent. | |
416 | * Try to queue up another DMA buffer. | |
417 | */ | |
418 | static void pl011_dma_tx_callback(void *data) | |
419 | { | |
420 | struct uart_amba_port *uap = data; | |
421 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
422 | unsigned long flags; | |
423 | u16 dmacr; | |
424 | ||
425 | spin_lock_irqsave(&uap->port.lock, flags); | |
426 | if (uap->dmatx.queued) | |
427 | dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, | |
428 | DMA_TO_DEVICE); | |
429 | ||
430 | dmacr = uap->dmacr; | |
431 | uap->dmacr = dmacr & ~UART011_TXDMAE; | |
432 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
433 | ||
434 | /* | |
435 | * If TX DMA was disabled, it means that we've stopped the DMA for | |
436 | * some reason (eg, XOFF received, or we want to send an X-char.) | |
437 | * | |
438 | * Note: we need to be careful here of a potential race between DMA | |
439 | * and the rest of the driver - if the driver disables TX DMA while | |
440 | * a TX buffer completing, we must update the tx queued status to | |
441 | * get further refills (hence we check dmacr). | |
442 | */ | |
443 | if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || | |
444 | uart_circ_empty(&uap->port.state->xmit)) { | |
445 | uap->dmatx.queued = false; | |
446 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
447 | return; | |
448 | } | |
449 | ||
450 | if (pl011_dma_tx_refill(uap) <= 0) { | |
451 | /* | |
452 | * We didn't queue a DMA buffer for some reason, but we | |
453 | * have data pending to be sent. Re-enable the TX IRQ. | |
454 | */ | |
455 | uap->im |= UART011_TXIM; | |
456 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
457 | } | |
458 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
459 | } | |
460 | ||
461 | /* | |
462 | * Try to refill the TX DMA buffer. | |
463 | * Locking: called with port lock held and IRQs disabled. | |
464 | * Returns: | |
465 | * 1 if we queued up a TX DMA buffer. | |
466 | * 0 if we didn't want to handle this by DMA | |
467 | * <0 on error | |
468 | */ | |
469 | static int pl011_dma_tx_refill(struct uart_amba_port *uap) | |
470 | { | |
471 | struct pl011_dmatx_data *dmatx = &uap->dmatx; | |
472 | struct dma_chan *chan = dmatx->chan; | |
473 | struct dma_device *dma_dev = chan->device; | |
474 | struct dma_async_tx_descriptor *desc; | |
475 | struct circ_buf *xmit = &uap->port.state->xmit; | |
476 | unsigned int count; | |
477 | ||
478 | /* | |
479 | * Try to avoid the overhead involved in using DMA if the | |
480 | * transaction fits in the first half of the FIFO, by using | |
481 | * the standard interrupt handling. This ensures that we | |
482 | * issue a uart_write_wakeup() at the appropriate time. | |
483 | */ | |
484 | count = uart_circ_chars_pending(xmit); | |
485 | if (count < (uap->fifosize >> 1)) { | |
486 | uap->dmatx.queued = false; | |
487 | return 0; | |
488 | } | |
489 | ||
490 | /* | |
491 | * Bodge: don't send the last character by DMA, as this | |
492 | * will prevent XON from notifying us to restart DMA. | |
493 | */ | |
494 | count -= 1; | |
495 | ||
496 | /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */ | |
497 | if (count > PL011_DMA_BUFFER_SIZE) | |
498 | count = PL011_DMA_BUFFER_SIZE; | |
499 | ||
500 | if (xmit->tail < xmit->head) | |
501 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count); | |
502 | else { | |
503 | size_t first = UART_XMIT_SIZE - xmit->tail; | |
504 | size_t second = xmit->head; | |
505 | ||
506 | memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first); | |
507 | if (second) | |
508 | memcpy(&dmatx->buf[first], &xmit->buf[0], second); | |
509 | } | |
510 | ||
511 | dmatx->sg.length = count; | |
512 | ||
513 | if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) { | |
514 | uap->dmatx.queued = false; | |
515 | dev_dbg(uap->port.dev, "unable to map TX DMA\n"); | |
516 | return -EBUSY; | |
517 | } | |
518 | ||
16052827 | 519 | desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV, |
68b65f73 RK |
520 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
521 | if (!desc) { | |
522 | dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE); | |
523 | uap->dmatx.queued = false; | |
524 | /* | |
525 | * If DMA cannot be used right now, we complete this | |
526 | * transaction via IRQ and let the TTY layer retry. | |
527 | */ | |
528 | dev_dbg(uap->port.dev, "TX DMA busy\n"); | |
529 | return -EBUSY; | |
530 | } | |
531 | ||
532 | /* Some data to go along to the callback */ | |
533 | desc->callback = pl011_dma_tx_callback; | |
534 | desc->callback_param = uap; | |
535 | ||
536 | /* All errors should happen at prepare time */ | |
537 | dmaengine_submit(desc); | |
538 | ||
539 | /* Fire the DMA transaction */ | |
540 | dma_dev->device_issue_pending(chan); | |
541 | ||
542 | uap->dmacr |= UART011_TXDMAE; | |
543 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
544 | uap->dmatx.queued = true; | |
545 | ||
546 | /* | |
547 | * Now we know that DMA will fire, so advance the ring buffer | |
548 | * with the stuff we just dispatched. | |
549 | */ | |
550 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
551 | uap->port.icount.tx += count; | |
552 | ||
553 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
554 | uart_write_wakeup(&uap->port); | |
555 | ||
556 | return 1; | |
557 | } | |
558 | ||
559 | /* | |
560 | * We received a transmit interrupt without a pending X-char but with | |
561 | * pending characters. | |
562 | * Locking: called with port lock held and IRQs disabled. | |
563 | * Returns: | |
564 | * false if we want to use PIO to transmit | |
565 | * true if we queued a DMA buffer | |
566 | */ | |
567 | static bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
568 | { | |
ead76f32 | 569 | if (!uap->using_tx_dma) |
68b65f73 RK |
570 | return false; |
571 | ||
572 | /* | |
573 | * If we already have a TX buffer queued, but received a | |
574 | * TX interrupt, it will be because we've just sent an X-char. | |
575 | * Ensure the TX DMA is enabled and the TX IRQ is disabled. | |
576 | */ | |
577 | if (uap->dmatx.queued) { | |
578 | uap->dmacr |= UART011_TXDMAE; | |
579 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
580 | uap->im &= ~UART011_TXIM; | |
581 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
582 | return true; | |
583 | } | |
584 | ||
585 | /* | |
586 | * We don't have a TX buffer queued, so try to queue one. | |
25985edc | 587 | * If we successfully queued a buffer, mask the TX IRQ. |
68b65f73 RK |
588 | */ |
589 | if (pl011_dma_tx_refill(uap) > 0) { | |
590 | uap->im &= ~UART011_TXIM; | |
591 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
592 | return true; | |
593 | } | |
594 | return false; | |
595 | } | |
596 | ||
597 | /* | |
598 | * Stop the DMA transmit (eg, due to received XOFF). | |
599 | * Locking: called with port lock held and IRQs disabled. | |
600 | */ | |
601 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
602 | { | |
603 | if (uap->dmatx.queued) { | |
604 | uap->dmacr &= ~UART011_TXDMAE; | |
605 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
606 | } | |
607 | } | |
608 | ||
609 | /* | |
610 | * Try to start a DMA transmit, or in the case of an XON/OFF | |
611 | * character queued for send, try to get that character out ASAP. | |
612 | * Locking: called with port lock held and IRQs disabled. | |
613 | * Returns: | |
614 | * false if we want the TX IRQ to be enabled | |
615 | * true if we have a buffer queued | |
616 | */ | |
617 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
618 | { | |
619 | u16 dmacr; | |
620 | ||
ead76f32 | 621 | if (!uap->using_tx_dma) |
68b65f73 RK |
622 | return false; |
623 | ||
624 | if (!uap->port.x_char) { | |
625 | /* no X-char, try to push chars out in DMA mode */ | |
626 | bool ret = true; | |
627 | ||
628 | if (!uap->dmatx.queued) { | |
629 | if (pl011_dma_tx_refill(uap) > 0) { | |
630 | uap->im &= ~UART011_TXIM; | |
631 | ret = true; | |
632 | } else { | |
633 | uap->im |= UART011_TXIM; | |
634 | ret = false; | |
635 | } | |
636 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
637 | } else if (!(uap->dmacr & UART011_TXDMAE)) { | |
638 | uap->dmacr |= UART011_TXDMAE; | |
639 | writew(uap->dmacr, | |
640 | uap->port.membase + UART011_DMACR); | |
641 | } | |
642 | return ret; | |
643 | } | |
644 | ||
645 | /* | |
646 | * We have an X-char to send. Disable DMA to prevent it loading | |
647 | * the TX fifo, and then see if we can stuff it into the FIFO. | |
648 | */ | |
649 | dmacr = uap->dmacr; | |
650 | uap->dmacr &= ~UART011_TXDMAE; | |
651 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
652 | ||
653 | if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) { | |
654 | /* | |
655 | * No space in the FIFO, so enable the transmit interrupt | |
656 | * so we know when there is space. Note that once we've | |
657 | * loaded the character, we should just re-enable DMA. | |
658 | */ | |
659 | return false; | |
660 | } | |
661 | ||
662 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
663 | uap->port.icount.tx++; | |
664 | uap->port.x_char = 0; | |
665 | ||
666 | /* Success - restore the DMA state */ | |
667 | uap->dmacr = dmacr; | |
668 | writew(dmacr, uap->port.membase + UART011_DMACR); | |
669 | ||
670 | return true; | |
671 | } | |
672 | ||
673 | /* | |
674 | * Flush the transmit buffer. | |
675 | * Locking: called with port lock held and IRQs disabled. | |
676 | */ | |
677 | static void pl011_dma_flush_buffer(struct uart_port *port) | |
b83286bf FE |
678 | __releases(&uap->port.lock) |
679 | __acquires(&uap->port.lock) | |
68b65f73 | 680 | { |
a5820c24 DT |
681 | struct uart_amba_port *uap = |
682 | container_of(port, struct uart_amba_port, port); | |
68b65f73 | 683 | |
ead76f32 | 684 | if (!uap->using_tx_dma) |
68b65f73 RK |
685 | return; |
686 | ||
687 | /* Avoid deadlock with the DMA engine callback */ | |
688 | spin_unlock(&uap->port.lock); | |
689 | dmaengine_terminate_all(uap->dmatx.chan); | |
690 | spin_lock(&uap->port.lock); | |
691 | if (uap->dmatx.queued) { | |
692 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
693 | DMA_TO_DEVICE); | |
694 | uap->dmatx.queued = false; | |
695 | uap->dmacr &= ~UART011_TXDMAE; | |
696 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
697 | } | |
698 | } | |
699 | ||
ead76f32 LW |
700 | static void pl011_dma_rx_callback(void *data); |
701 | ||
702 | static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
703 | { | |
704 | struct dma_chan *rxchan = uap->dmarx.chan; | |
ead76f32 LW |
705 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
706 | struct dma_async_tx_descriptor *desc; | |
707 | struct pl011_sgbuf *sgbuf; | |
708 | ||
709 | if (!rxchan) | |
710 | return -EIO; | |
711 | ||
712 | /* Start the RX DMA job */ | |
713 | sgbuf = uap->dmarx.use_buf_b ? | |
714 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
16052827 | 715 | desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1, |
a485df4b | 716 | DMA_DEV_TO_MEM, |
ead76f32 LW |
717 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
718 | /* | |
719 | * If the DMA engine is busy and cannot prepare a | |
720 | * channel, no big deal, the driver will fall back | |
721 | * to interrupt mode as a result of this error code. | |
722 | */ | |
723 | if (!desc) { | |
724 | uap->dmarx.running = false; | |
725 | dmaengine_terminate_all(rxchan); | |
726 | return -EBUSY; | |
727 | } | |
728 | ||
729 | /* Some data to go along to the callback */ | |
730 | desc->callback = pl011_dma_rx_callback; | |
731 | desc->callback_param = uap; | |
732 | dmarx->cookie = dmaengine_submit(desc); | |
733 | dma_async_issue_pending(rxchan); | |
734 | ||
735 | uap->dmacr |= UART011_RXDMAE; | |
736 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
737 | uap->dmarx.running = true; | |
738 | ||
739 | uap->im &= ~UART011_RXIM; | |
740 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
745 | /* | |
746 | * This is called when either the DMA job is complete, or | |
747 | * the FIFO timeout interrupt occurred. This must be called | |
748 | * with the port spinlock uap->port.lock held. | |
749 | */ | |
750 | static void pl011_dma_rx_chars(struct uart_amba_port *uap, | |
751 | u32 pending, bool use_buf_b, | |
752 | bool readfifo) | |
753 | { | |
05c7cd39 | 754 | struct tty_port *port = &uap->port.state->port; |
ead76f32 LW |
755 | struct pl011_sgbuf *sgbuf = use_buf_b ? |
756 | &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
ead76f32 LW |
757 | int dma_count = 0; |
758 | u32 fifotaken = 0; /* only used for vdbg() */ | |
759 | ||
cb06ff10 CM |
760 | struct pl011_dmarx_data *dmarx = &uap->dmarx; |
761 | int dmataken = 0; | |
762 | ||
763 | if (uap->dmarx.poll_rate) { | |
764 | /* The data can be taken by polling */ | |
765 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
766 | /* Recalculate the pending size */ | |
767 | if (pending >= dmataken) | |
768 | pending -= dmataken; | |
769 | } | |
770 | ||
771 | /* Pick the remain data from the DMA */ | |
ead76f32 | 772 | if (pending) { |
ead76f32 LW |
773 | |
774 | /* | |
775 | * First take all chars in the DMA pipe, then look in the FIFO. | |
776 | * Note that tty_insert_flip_buf() tries to take as many chars | |
777 | * as it can. | |
778 | */ | |
cb06ff10 CM |
779 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, |
780 | pending); | |
ead76f32 LW |
781 | |
782 | uap->port.icount.rx += dma_count; | |
783 | if (dma_count < pending) | |
784 | dev_warn(uap->port.dev, | |
785 | "couldn't insert all characters (TTY is full?)\n"); | |
786 | } | |
787 | ||
cb06ff10 CM |
788 | /* Reset the last_residue for Rx DMA poll */ |
789 | if (uap->dmarx.poll_rate) | |
790 | dmarx->last_residue = sgbuf->sg.length; | |
791 | ||
ead76f32 LW |
792 | /* |
793 | * Only continue with trying to read the FIFO if all DMA chars have | |
794 | * been taken first. | |
795 | */ | |
796 | if (dma_count == pending && readfifo) { | |
797 | /* Clear any error flags */ | |
798 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS, | |
799 | uap->port.membase + UART011_ICR); | |
800 | ||
801 | /* | |
802 | * If we read all the DMA'd characters, and we had an | |
29772c4e LW |
803 | * incomplete buffer, that could be due to an rx error, or |
804 | * maybe we just timed out. Read any pending chars and check | |
805 | * the error status. | |
806 | * | |
807 | * Error conditions will only occur in the FIFO, these will | |
808 | * trigger an immediate interrupt and stop the DMA job, so we | |
809 | * will always find the error in the FIFO, never in the DMA | |
810 | * buffer. | |
ead76f32 | 811 | */ |
29772c4e | 812 | fifotaken = pl011_fifo_to_tty(uap); |
ead76f32 LW |
813 | } |
814 | ||
815 | spin_unlock(&uap->port.lock); | |
816 | dev_vdbg(uap->port.dev, | |
817 | "Took %d chars from DMA buffer and %d chars from the FIFO\n", | |
818 | dma_count, fifotaken); | |
2e124b4a | 819 | tty_flip_buffer_push(port); |
ead76f32 LW |
820 | spin_lock(&uap->port.lock); |
821 | } | |
822 | ||
823 | static void pl011_dma_rx_irq(struct uart_amba_port *uap) | |
824 | { | |
825 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
826 | struct dma_chan *rxchan = dmarx->chan; | |
827 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? | |
828 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
829 | size_t pending; | |
830 | struct dma_tx_state state; | |
831 | enum dma_status dmastat; | |
832 | ||
833 | /* | |
834 | * Pause the transfer so we can trust the current counter, | |
835 | * do this before we pause the PL011 block, else we may | |
836 | * overflow the FIFO. | |
837 | */ | |
838 | if (dmaengine_pause(rxchan)) | |
839 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
840 | dmastat = rxchan->device->device_tx_status(rxchan, | |
841 | dmarx->cookie, &state); | |
842 | if (dmastat != DMA_PAUSED) | |
843 | dev_err(uap->port.dev, "unable to pause DMA transfer\n"); | |
844 | ||
845 | /* Disable RX DMA - incoming data will wait in the FIFO */ | |
846 | uap->dmacr &= ~UART011_RXDMAE; | |
847 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
848 | uap->dmarx.running = false; | |
849 | ||
850 | pending = sgbuf->sg.length - state.residue; | |
851 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
852 | /* Then we terminate the transfer - we now know our residue */ | |
853 | dmaengine_terminate_all(rxchan); | |
854 | ||
855 | /* | |
856 | * This will take the chars we have so far and insert | |
857 | * into the framework. | |
858 | */ | |
859 | pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true); | |
860 | ||
861 | /* Switch buffer & re-trigger DMA job */ | |
862 | dmarx->use_buf_b = !dmarx->use_buf_b; | |
863 | if (pl011_dma_rx_trigger_dma(uap)) { | |
864 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
865 | "fall back to interrupt mode\n"); | |
866 | uap->im |= UART011_RXIM; | |
867 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
868 | } | |
869 | } | |
870 | ||
871 | static void pl011_dma_rx_callback(void *data) | |
872 | { | |
873 | struct uart_amba_port *uap = data; | |
874 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
6dc01aa6 | 875 | struct dma_chan *rxchan = dmarx->chan; |
ead76f32 | 876 | bool lastbuf = dmarx->use_buf_b; |
6dc01aa6 CM |
877 | struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ? |
878 | &dmarx->sgbuf_b : &dmarx->sgbuf_a; | |
879 | size_t pending; | |
880 | struct dma_tx_state state; | |
ead76f32 LW |
881 | int ret; |
882 | ||
883 | /* | |
884 | * This completion interrupt occurs typically when the | |
885 | * RX buffer is totally stuffed but no timeout has yet | |
886 | * occurred. When that happens, we just want the RX | |
887 | * routine to flush out the secondary DMA buffer while | |
888 | * we immediately trigger the next DMA job. | |
889 | */ | |
890 | spin_lock_irq(&uap->port.lock); | |
6dc01aa6 CM |
891 | /* |
892 | * Rx data can be taken by the UART interrupts during | |
893 | * the DMA irq handler. So we check the residue here. | |
894 | */ | |
895 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
896 | pending = sgbuf->sg.length - state.residue; | |
897 | BUG_ON(pending > PL011_DMA_BUFFER_SIZE); | |
898 | /* Then we terminate the transfer - we now know our residue */ | |
899 | dmaengine_terminate_all(rxchan); | |
900 | ||
ead76f32 LW |
901 | uap->dmarx.running = false; |
902 | dmarx->use_buf_b = !lastbuf; | |
903 | ret = pl011_dma_rx_trigger_dma(uap); | |
904 | ||
6dc01aa6 | 905 | pl011_dma_rx_chars(uap, pending, lastbuf, false); |
ead76f32 LW |
906 | spin_unlock_irq(&uap->port.lock); |
907 | /* | |
908 | * Do this check after we picked the DMA chars so we don't | |
909 | * get some IRQ immediately from RX. | |
910 | */ | |
911 | if (ret) { | |
912 | dev_dbg(uap->port.dev, "could not retrigger RX DMA job " | |
913 | "fall back to interrupt mode\n"); | |
914 | uap->im |= UART011_RXIM; | |
915 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
916 | } | |
917 | } | |
918 | ||
919 | /* | |
920 | * Stop accepting received characters, when we're shutting down or | |
921 | * suspending this port. | |
922 | * Locking: called with port lock held and IRQs disabled. | |
923 | */ | |
924 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
925 | { | |
926 | /* FIXME. Just disable the DMA enable */ | |
927 | uap->dmacr &= ~UART011_RXDMAE; | |
928 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
929 | } | |
68b65f73 | 930 | |
cb06ff10 CM |
931 | /* |
932 | * Timer handler for Rx DMA polling. | |
933 | * Every polling, It checks the residue in the dma buffer and transfer | |
934 | * data to the tty. Also, last_residue is updated for the next polling. | |
935 | */ | |
936 | static void pl011_dma_rx_poll(unsigned long args) | |
937 | { | |
938 | struct uart_amba_port *uap = (struct uart_amba_port *)args; | |
939 | struct tty_port *port = &uap->port.state->port; | |
940 | struct pl011_dmarx_data *dmarx = &uap->dmarx; | |
941 | struct dma_chan *rxchan = uap->dmarx.chan; | |
942 | unsigned long flags = 0; | |
943 | unsigned int dmataken = 0; | |
944 | unsigned int size = 0; | |
945 | struct pl011_sgbuf *sgbuf; | |
946 | int dma_count; | |
947 | struct dma_tx_state state; | |
948 | ||
949 | sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a; | |
950 | rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state); | |
951 | if (likely(state.residue < dmarx->last_residue)) { | |
952 | dmataken = sgbuf->sg.length - dmarx->last_residue; | |
953 | size = dmarx->last_residue - state.residue; | |
954 | dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken, | |
955 | size); | |
956 | if (dma_count == size) | |
957 | dmarx->last_residue = state.residue; | |
958 | dmarx->last_jiffies = jiffies; | |
959 | } | |
960 | tty_flip_buffer_push(port); | |
961 | ||
962 | /* | |
963 | * If no data is received in poll_timeout, the driver will fall back | |
964 | * to interrupt mode. We will retrigger DMA at the first interrupt. | |
965 | */ | |
966 | if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) | |
967 | > uap->dmarx.poll_timeout) { | |
968 | ||
969 | spin_lock_irqsave(&uap->port.lock, flags); | |
970 | pl011_dma_rx_stop(uap); | |
c25a1ad7 GL |
971 | uap->im |= UART011_RXIM; |
972 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
cb06ff10 CM |
973 | spin_unlock_irqrestore(&uap->port.lock, flags); |
974 | ||
975 | uap->dmarx.running = false; | |
976 | dmaengine_terminate_all(rxchan); | |
977 | del_timer(&uap->dmarx.timer); | |
978 | } else { | |
979 | mod_timer(&uap->dmarx.timer, | |
980 | jiffies + msecs_to_jiffies(uap->dmarx.poll_rate)); | |
981 | } | |
982 | } | |
983 | ||
68b65f73 RK |
984 | static void pl011_dma_startup(struct uart_amba_port *uap) |
985 | { | |
ead76f32 LW |
986 | int ret; |
987 | ||
68b65f73 RK |
988 | if (!uap->dmatx.chan) |
989 | return; | |
990 | ||
991 | uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL); | |
992 | if (!uap->dmatx.buf) { | |
993 | dev_err(uap->port.dev, "no memory for DMA TX buffer\n"); | |
994 | uap->port.fifosize = uap->fifosize; | |
995 | return; | |
996 | } | |
997 | ||
998 | sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE); | |
999 | ||
1000 | /* The DMA buffer is now the FIFO the TTY subsystem can use */ | |
1001 | uap->port.fifosize = PL011_DMA_BUFFER_SIZE; | |
ead76f32 LW |
1002 | uap->using_tx_dma = true; |
1003 | ||
1004 | if (!uap->dmarx.chan) | |
1005 | goto skip_rx; | |
1006 | ||
1007 | /* Allocate and map DMA RX buffers */ | |
1008 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1009 | DMA_FROM_DEVICE); | |
1010 | if (ret) { | |
1011 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1012 | "RX buffer A", ret); | |
1013 | goto skip_rx; | |
1014 | } | |
68b65f73 | 1015 | |
ead76f32 LW |
1016 | ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b, |
1017 | DMA_FROM_DEVICE); | |
1018 | if (ret) { | |
1019 | dev_err(uap->port.dev, "failed to init DMA %s: %d\n", | |
1020 | "RX buffer B", ret); | |
1021 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, | |
1022 | DMA_FROM_DEVICE); | |
1023 | goto skip_rx; | |
1024 | } | |
1025 | ||
1026 | uap->using_rx_dma = true; | |
68b65f73 | 1027 | |
ead76f32 | 1028 | skip_rx: |
68b65f73 RK |
1029 | /* Turn on DMA error (RX/TX will be enabled on demand) */ |
1030 | uap->dmacr |= UART011_DMAONERR; | |
1031 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
38d62436 RK |
1032 | |
1033 | /* | |
1034 | * ST Micro variants has some specific dma burst threshold | |
1035 | * compensation. Set this to 16 bytes, so burst will only | |
1036 | * be issued above/below 16 bytes. | |
1037 | */ | |
1038 | if (uap->vendor->dma_threshold) | |
1039 | writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16, | |
1040 | uap->port.membase + ST_UART011_DMAWM); | |
ead76f32 LW |
1041 | |
1042 | if (uap->using_rx_dma) { | |
1043 | if (pl011_dma_rx_trigger_dma(uap)) | |
1044 | dev_dbg(uap->port.dev, "could not trigger initial " | |
1045 | "RX DMA job, fall back to interrupt mode\n"); | |
cb06ff10 CM |
1046 | if (uap->dmarx.poll_rate) { |
1047 | init_timer(&(uap->dmarx.timer)); | |
1048 | uap->dmarx.timer.function = pl011_dma_rx_poll; | |
1049 | uap->dmarx.timer.data = (unsigned long)uap; | |
1050 | mod_timer(&uap->dmarx.timer, | |
1051 | jiffies + | |
1052 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1053 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1054 | uap->dmarx.last_jiffies = jiffies; | |
1055 | } | |
ead76f32 | 1056 | } |
68b65f73 RK |
1057 | } |
1058 | ||
1059 | static void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1060 | { | |
ead76f32 | 1061 | if (!(uap->using_tx_dma || uap->using_rx_dma)) |
68b65f73 RK |
1062 | return; |
1063 | ||
1064 | /* Disable RX and TX DMA */ | |
1065 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1066 | barrier(); | |
1067 | ||
1068 | spin_lock_irq(&uap->port.lock); | |
1069 | uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); | |
1070 | writew(uap->dmacr, uap->port.membase + UART011_DMACR); | |
1071 | spin_unlock_irq(&uap->port.lock); | |
1072 | ||
ead76f32 LW |
1073 | if (uap->using_tx_dma) { |
1074 | /* In theory, this should already be done by pl011_dma_flush_buffer */ | |
1075 | dmaengine_terminate_all(uap->dmatx.chan); | |
1076 | if (uap->dmatx.queued) { | |
1077 | dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1, | |
1078 | DMA_TO_DEVICE); | |
1079 | uap->dmatx.queued = false; | |
1080 | } | |
1081 | ||
1082 | kfree(uap->dmatx.buf); | |
1083 | uap->using_tx_dma = false; | |
68b65f73 RK |
1084 | } |
1085 | ||
ead76f32 LW |
1086 | if (uap->using_rx_dma) { |
1087 | dmaengine_terminate_all(uap->dmarx.chan); | |
1088 | /* Clean up the RX DMA */ | |
1089 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE); | |
1090 | pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE); | |
cb06ff10 CM |
1091 | if (uap->dmarx.poll_rate) |
1092 | del_timer_sync(&uap->dmarx.timer); | |
ead76f32 LW |
1093 | uap->using_rx_dma = false; |
1094 | } | |
1095 | } | |
68b65f73 | 1096 | |
ead76f32 LW |
1097 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) |
1098 | { | |
1099 | return uap->using_rx_dma; | |
68b65f73 RK |
1100 | } |
1101 | ||
ead76f32 LW |
1102 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) |
1103 | { | |
1104 | return uap->using_rx_dma && uap->dmarx.running; | |
1105 | } | |
1106 | ||
68b65f73 RK |
1107 | #else |
1108 | /* Blank functions if the DMA engine is not available */ | |
aabdd290 | 1109 | static inline void pl011_dma_probe(struct device *dev, struct uart_amba_port *uap) |
68b65f73 RK |
1110 | { |
1111 | } | |
1112 | ||
1113 | static inline void pl011_dma_remove(struct uart_amba_port *uap) | |
1114 | { | |
1115 | } | |
1116 | ||
1117 | static inline void pl011_dma_startup(struct uart_amba_port *uap) | |
1118 | { | |
1119 | } | |
1120 | ||
1121 | static inline void pl011_dma_shutdown(struct uart_amba_port *uap) | |
1122 | { | |
1123 | } | |
1124 | ||
1125 | static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap) | |
1126 | { | |
1127 | return false; | |
1128 | } | |
1129 | ||
1130 | static inline void pl011_dma_tx_stop(struct uart_amba_port *uap) | |
1131 | { | |
1132 | } | |
1133 | ||
1134 | static inline bool pl011_dma_tx_start(struct uart_amba_port *uap) | |
1135 | { | |
1136 | return false; | |
1137 | } | |
1138 | ||
ead76f32 LW |
1139 | static inline void pl011_dma_rx_irq(struct uart_amba_port *uap) |
1140 | { | |
1141 | } | |
1142 | ||
1143 | static inline void pl011_dma_rx_stop(struct uart_amba_port *uap) | |
1144 | { | |
1145 | } | |
1146 | ||
1147 | static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap) | |
1148 | { | |
1149 | return -EIO; | |
1150 | } | |
1151 | ||
1152 | static inline bool pl011_dma_rx_available(struct uart_amba_port *uap) | |
1153 | { | |
1154 | return false; | |
1155 | } | |
1156 | ||
1157 | static inline bool pl011_dma_rx_running(struct uart_amba_port *uap) | |
1158 | { | |
1159 | return false; | |
1160 | } | |
1161 | ||
68b65f73 RK |
1162 | #define pl011_dma_flush_buffer NULL |
1163 | #endif | |
1164 | ||
b129a8cc | 1165 | static void pl011_stop_tx(struct uart_port *port) |
1da177e4 | 1166 | { |
a5820c24 DT |
1167 | struct uart_amba_port *uap = |
1168 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1169 | |
1170 | uap->im &= ~UART011_TXIM; | |
1171 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
68b65f73 | 1172 | pl011_dma_tx_stop(uap); |
1da177e4 LT |
1173 | } |
1174 | ||
b129a8cc | 1175 | static void pl011_start_tx(struct uart_port *port) |
1da177e4 | 1176 | { |
a5820c24 DT |
1177 | struct uart_amba_port *uap = |
1178 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1179 | |
68b65f73 RK |
1180 | if (!pl011_dma_tx_start(uap)) { |
1181 | uap->im |= UART011_TXIM; | |
1182 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1183 | } | |
1da177e4 LT |
1184 | } |
1185 | ||
1186 | static void pl011_stop_rx(struct uart_port *port) | |
1187 | { | |
a5820c24 DT |
1188 | struct uart_amba_port *uap = |
1189 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1190 | |
1191 | uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM| | |
1192 | UART011_PEIM|UART011_BEIM|UART011_OEIM); | |
1193 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
ead76f32 LW |
1194 | |
1195 | pl011_dma_rx_stop(uap); | |
1da177e4 LT |
1196 | } |
1197 | ||
1198 | static void pl011_enable_ms(struct uart_port *port) | |
1199 | { | |
a5820c24 DT |
1200 | struct uart_amba_port *uap = |
1201 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1202 | |
1203 | uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM; | |
1204 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1205 | } | |
1206 | ||
7d12e780 | 1207 | static void pl011_rx_chars(struct uart_amba_port *uap) |
b83286bf FE |
1208 | __releases(&uap->port.lock) |
1209 | __acquires(&uap->port.lock) | |
1da177e4 | 1210 | { |
29772c4e | 1211 | pl011_fifo_to_tty(uap); |
1da177e4 | 1212 | |
2389b272 | 1213 | spin_unlock(&uap->port.lock); |
2e124b4a | 1214 | tty_flip_buffer_push(&uap->port.state->port); |
ead76f32 LW |
1215 | /* |
1216 | * If we were temporarily out of DMA mode for a while, | |
1217 | * attempt to switch back to DMA mode again. | |
1218 | */ | |
1219 | if (pl011_dma_rx_available(uap)) { | |
1220 | if (pl011_dma_rx_trigger_dma(uap)) { | |
1221 | dev_dbg(uap->port.dev, "could not trigger RX DMA job " | |
1222 | "fall back to interrupt mode again\n"); | |
1223 | uap->im |= UART011_RXIM; | |
30ae5859 | 1224 | writew(uap->im, uap->port.membase + UART011_IMSC); |
cb06ff10 | 1225 | } else { |
89fa28db | 1226 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1227 | /* Start Rx DMA poll */ |
1228 | if (uap->dmarx.poll_rate) { | |
1229 | uap->dmarx.last_jiffies = jiffies; | |
1230 | uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE; | |
1231 | mod_timer(&uap->dmarx.timer, | |
1232 | jiffies + | |
1233 | msecs_to_jiffies(uap->dmarx.poll_rate)); | |
1234 | } | |
89fa28db | 1235 | #endif |
cb06ff10 | 1236 | } |
ead76f32 | 1237 | } |
2389b272 | 1238 | spin_lock(&uap->port.lock); |
1da177e4 LT |
1239 | } |
1240 | ||
1241 | static void pl011_tx_chars(struct uart_amba_port *uap) | |
1242 | { | |
ebd2c8f6 | 1243 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
1244 | int count; |
1245 | ||
1246 | if (uap->port.x_char) { | |
1247 | writew(uap->port.x_char, uap->port.membase + UART01x_DR); | |
1248 | uap->port.icount.tx++; | |
1249 | uap->port.x_char = 0; | |
1250 | return; | |
1251 | } | |
1252 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { | |
b129a8cc | 1253 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1254 | return; |
1255 | } | |
1256 | ||
68b65f73 RK |
1257 | /* If we are using DMA mode, try to send some characters. */ |
1258 | if (pl011_dma_tx_irq(uap)) | |
1259 | return; | |
1260 | ||
ffca2b11 | 1261 | count = uap->fifosize >> 1; |
1da177e4 LT |
1262 | do { |
1263 | writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); | |
1264 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
1265 | uap->port.icount.tx++; | |
1266 | if (uart_circ_empty(xmit)) | |
1267 | break; | |
1268 | } while (--count > 0); | |
1269 | ||
1270 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1271 | uart_write_wakeup(&uap->port); | |
1272 | ||
1273 | if (uart_circ_empty(xmit)) | |
b129a8cc | 1274 | pl011_stop_tx(&uap->port); |
1da177e4 LT |
1275 | } |
1276 | ||
1277 | static void pl011_modem_status(struct uart_amba_port *uap) | |
1278 | { | |
1279 | unsigned int status, delta; | |
1280 | ||
1281 | status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1282 | ||
1283 | delta = status ^ uap->old_status; | |
1284 | uap->old_status = status; | |
1285 | ||
1286 | if (!delta) | |
1287 | return; | |
1288 | ||
1289 | if (delta & UART01x_FR_DCD) | |
1290 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
1291 | ||
1292 | if (delta & UART01x_FR_DSR) | |
1293 | uap->port.icount.dsr++; | |
1294 | ||
1295 | if (delta & UART01x_FR_CTS) | |
1296 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
1297 | ||
bdc04e31 | 1298 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
1299 | } |
1300 | ||
7d12e780 | 1301 | static irqreturn_t pl011_int(int irq, void *dev_id) |
1da177e4 LT |
1302 | { |
1303 | struct uart_amba_port *uap = dev_id; | |
963cc981 | 1304 | unsigned long flags; |
1da177e4 LT |
1305 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
1306 | int handled = 0; | |
4fd0690b | 1307 | unsigned int dummy_read; |
1da177e4 | 1308 | |
963cc981 | 1309 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
1310 | status = readw(uap->port.membase + UART011_MIS); |
1311 | if (status) { | |
1312 | do { | |
4fd0690b R |
1313 | if (uap->vendor->cts_event_workaround) { |
1314 | /* workaround to make sure that all bits are unlocked.. */ | |
1315 | writew(0x00, uap->port.membase + UART011_ICR); | |
1316 | ||
1317 | /* | |
1318 | * WA: introduce 26ns(1 uart clk) delay before W1C; | |
1319 | * single apb access will incur 2 pclk(133.12Mhz) delay, | |
1320 | * so add 2 dummy reads | |
1321 | */ | |
1322 | dummy_read = readw(uap->port.membase + UART011_ICR); | |
1323 | dummy_read = readw(uap->port.membase + UART011_ICR); | |
1324 | } | |
1325 | ||
1da177e4 LT |
1326 | writew(status & ~(UART011_TXIS|UART011_RTIS| |
1327 | UART011_RXIS), | |
1328 | uap->port.membase + UART011_ICR); | |
1329 | ||
ead76f32 LW |
1330 | if (status & (UART011_RTIS|UART011_RXIS)) { |
1331 | if (pl011_dma_rx_running(uap)) | |
1332 | pl011_dma_rx_irq(uap); | |
1333 | else | |
1334 | pl011_rx_chars(uap); | |
1335 | } | |
1da177e4 LT |
1336 | if (status & (UART011_DSRMIS|UART011_DCDMIS| |
1337 | UART011_CTSMIS|UART011_RIMIS)) | |
1338 | pl011_modem_status(uap); | |
1339 | if (status & UART011_TXIS) | |
1340 | pl011_tx_chars(uap); | |
1341 | ||
4fd0690b | 1342 | if (pass_counter-- == 0) |
1da177e4 LT |
1343 | break; |
1344 | ||
1345 | status = readw(uap->port.membase + UART011_MIS); | |
1346 | } while (status != 0); | |
1347 | handled = 1; | |
1348 | } | |
1349 | ||
963cc981 | 1350 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
1351 | |
1352 | return IRQ_RETVAL(handled); | |
1353 | } | |
1354 | ||
e643f87f | 1355 | static unsigned int pl011_tx_empty(struct uart_port *port) |
1da177e4 | 1356 | { |
a5820c24 DT |
1357 | struct uart_amba_port *uap = |
1358 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1359 | unsigned int status = readw(uap->port.membase + UART01x_FR); |
1360 | return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT; | |
1361 | } | |
1362 | ||
e643f87f | 1363 | static unsigned int pl011_get_mctrl(struct uart_port *port) |
1da177e4 | 1364 | { |
a5820c24 DT |
1365 | struct uart_amba_port *uap = |
1366 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1367 | unsigned int result = 0; |
1368 | unsigned int status = readw(uap->port.membase + UART01x_FR); | |
1369 | ||
5159f407 | 1370 | #define TIOCMBIT(uartbit, tiocmbit) \ |
1da177e4 LT |
1371 | if (status & uartbit) \ |
1372 | result |= tiocmbit | |
1373 | ||
5159f407 JS |
1374 | TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR); |
1375 | TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR); | |
1376 | TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS); | |
1377 | TIOCMBIT(UART011_FR_RI, TIOCM_RNG); | |
1378 | #undef TIOCMBIT | |
1da177e4 LT |
1379 | return result; |
1380 | } | |
1381 | ||
1382 | static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1383 | { | |
a5820c24 DT |
1384 | struct uart_amba_port *uap = |
1385 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1386 | unsigned int cr; |
1387 | ||
1388 | cr = readw(uap->port.membase + UART011_CR); | |
1389 | ||
5159f407 | 1390 | #define TIOCMBIT(tiocmbit, uartbit) \ |
1da177e4 LT |
1391 | if (mctrl & tiocmbit) \ |
1392 | cr |= uartbit; \ | |
1393 | else \ | |
1394 | cr &= ~uartbit | |
1395 | ||
5159f407 JS |
1396 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTS); |
1397 | TIOCMBIT(TIOCM_DTR, UART011_CR_DTR); | |
1398 | TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1); | |
1399 | TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2); | |
1400 | TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE); | |
3b43816f RV |
1401 | |
1402 | if (uap->autorts) { | |
1403 | /* We need to disable auto-RTS if we want to turn RTS off */ | |
1404 | TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN); | |
1405 | } | |
5159f407 | 1406 | #undef TIOCMBIT |
1da177e4 LT |
1407 | |
1408 | writew(cr, uap->port.membase + UART011_CR); | |
1409 | } | |
1410 | ||
1411 | static void pl011_break_ctl(struct uart_port *port, int break_state) | |
1412 | { | |
a5820c24 DT |
1413 | struct uart_amba_port *uap = |
1414 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1415 | unsigned long flags; |
1416 | unsigned int lcr_h; | |
1417 | ||
1418 | spin_lock_irqsave(&uap->port.lock, flags); | |
ec489aa8 | 1419 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1420 | if (break_state == -1) |
1421 | lcr_h |= UART01x_LCRH_BRK; | |
1422 | else | |
1423 | lcr_h &= ~UART01x_LCRH_BRK; | |
ec489aa8 | 1424 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1425 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1426 | } | |
1427 | ||
84b5ae15 | 1428 | #ifdef CONFIG_CONSOLE_POLL |
5c8124a0 AV |
1429 | |
1430 | static void pl011_quiesce_irqs(struct uart_port *port) | |
1431 | { | |
a5820c24 DT |
1432 | struct uart_amba_port *uap = |
1433 | container_of(port, struct uart_amba_port, port); | |
5c8124a0 AV |
1434 | unsigned char __iomem *regs = uap->port.membase; |
1435 | ||
1436 | writew(readw(regs + UART011_MIS), regs + UART011_ICR); | |
1437 | /* | |
1438 | * There is no way to clear TXIM as this is "ready to transmit IRQ", so | |
1439 | * we simply mask it. start_tx() will unmask it. | |
1440 | * | |
1441 | * Note we can race with start_tx(), and if the race happens, the | |
1442 | * polling user might get another interrupt just after we clear it. | |
1443 | * But it should be OK and can happen even w/o the race, e.g. | |
1444 | * controller immediately got some new data and raised the IRQ. | |
1445 | * | |
1446 | * And whoever uses polling routines assumes that it manages the device | |
1447 | * (including tx queue), so we're also fine with start_tx()'s caller | |
1448 | * side. | |
1449 | */ | |
1450 | writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC); | |
1451 | } | |
1452 | ||
e643f87f | 1453 | static int pl011_get_poll_char(struct uart_port *port) |
84b5ae15 | 1454 | { |
a5820c24 DT |
1455 | struct uart_amba_port *uap = |
1456 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1457 | unsigned int status; |
1458 | ||
5c8124a0 AV |
1459 | /* |
1460 | * The caller might need IRQs lowered, e.g. if used with KDB NMI | |
1461 | * debugger. | |
1462 | */ | |
1463 | pl011_quiesce_irqs(port); | |
1464 | ||
f5316b4a JW |
1465 | status = readw(uap->port.membase + UART01x_FR); |
1466 | if (status & UART01x_FR_RXFE) | |
1467 | return NO_POLL_CHAR; | |
84b5ae15 JW |
1468 | |
1469 | return readw(uap->port.membase + UART01x_DR); | |
1470 | } | |
1471 | ||
e643f87f | 1472 | static void pl011_put_poll_char(struct uart_port *port, |
84b5ae15 JW |
1473 | unsigned char ch) |
1474 | { | |
a5820c24 DT |
1475 | struct uart_amba_port *uap = |
1476 | container_of(port, struct uart_amba_port, port); | |
84b5ae15 JW |
1477 | |
1478 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) | |
1479 | barrier(); | |
1480 | ||
1481 | writew(ch, uap->port.membase + UART01x_DR); | |
1482 | } | |
1483 | ||
1484 | #endif /* CONFIG_CONSOLE_POLL */ | |
1485 | ||
b3564c2c | 1486 | static int pl011_hwinit(struct uart_port *port) |
1da177e4 | 1487 | { |
a5820c24 DT |
1488 | struct uart_amba_port *uap = |
1489 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1490 | int retval; |
1491 | ||
78d80c5a | 1492 | /* Optionaly enable pins to be muxed in and configured */ |
2b996fc5 | 1493 | pinctrl_pm_select_default_state(port->dev); |
78d80c5a | 1494 | |
1da177e4 LT |
1495 | /* |
1496 | * Try to enable the clock producer. | |
1497 | */ | |
1c4c4394 | 1498 | retval = clk_prepare_enable(uap->clk); |
1da177e4 | 1499 | if (retval) |
7f6d942a | 1500 | return retval; |
1da177e4 LT |
1501 | |
1502 | uap->port.uartclk = clk_get_rate(uap->clk); | |
1503 | ||
9b96fbac LW |
1504 | /* Clear pending error and receive interrupts */ |
1505 | writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS | | |
1506 | UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR); | |
1507 | ||
b3564c2c AV |
1508 | /* |
1509 | * Save interrupts enable mask, and enable RX interrupts in case if | |
1510 | * the interrupt is used for NMI entry. | |
1511 | */ | |
1512 | uap->im = readw(uap->port.membase + UART011_IMSC); | |
1513 | writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC); | |
1514 | ||
574de559 | 1515 | if (dev_get_platdata(uap->port.dev)) { |
b3564c2c AV |
1516 | struct amba_pl011_data *plat; |
1517 | ||
574de559 | 1518 | plat = dev_get_platdata(uap->port.dev); |
b3564c2c AV |
1519 | if (plat->init) |
1520 | plat->init(); | |
1521 | } | |
1522 | return 0; | |
b3564c2c AV |
1523 | } |
1524 | ||
b60f2f66 JM |
1525 | static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h) |
1526 | { | |
1527 | writew(lcr_h, uap->port.membase + uap->lcrh_rx); | |
1528 | if (uap->lcrh_rx != uap->lcrh_tx) { | |
1529 | int i; | |
1530 | /* | |
1531 | * Wait 10 PCLKs before writing LCRH_TX register, | |
1532 | * to get this delay write read only register 10 times | |
1533 | */ | |
1534 | for (i = 0; i < 10; ++i) | |
1535 | writew(0xff, uap->port.membase + UART011_MIS); | |
1536 | writew(lcr_h, uap->port.membase + uap->lcrh_tx); | |
1537 | } | |
1538 | } | |
1539 | ||
b3564c2c AV |
1540 | static int pl011_startup(struct uart_port *port) |
1541 | { | |
a5820c24 DT |
1542 | struct uart_amba_port *uap = |
1543 | container_of(port, struct uart_amba_port, port); | |
570d2910 | 1544 | unsigned int cr, lcr_h, fbrd, ibrd; |
b3564c2c AV |
1545 | int retval; |
1546 | ||
1547 | retval = pl011_hwinit(port); | |
1548 | if (retval) | |
1549 | goto clk_dis; | |
1550 | ||
1551 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1552 | ||
1da177e4 LT |
1553 | /* |
1554 | * Allocate the IRQ | |
1555 | */ | |
1556 | retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap); | |
1557 | if (retval) | |
1558 | goto clk_dis; | |
1559 | ||
c19f12b5 | 1560 | writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); |
1da177e4 LT |
1561 | |
1562 | /* | |
570d2910 JM |
1563 | * Provoke TX FIFO interrupt into asserting. Taking care to preserve |
1564 | * baud rate and data format specified by FBRD, IBRD and LCRH as the | |
1565 | * UART may already be in use as a console. | |
1da177e4 | 1566 | */ |
fe433907 JM |
1567 | spin_lock_irq(&uap->port.lock); |
1568 | ||
570d2910 JM |
1569 | fbrd = readw(uap->port.membase + UART011_FBRD); |
1570 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
1571 | lcr_h = readw(uap->port.membase + uap->lcrh_rx); | |
1572 | ||
1da177e4 LT |
1573 | cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; |
1574 | writew(cr, uap->port.membase + UART011_CR); | |
1575 | writew(0, uap->port.membase + UART011_FBRD); | |
1576 | writew(1, uap->port.membase + UART011_IBRD); | |
b60f2f66 | 1577 | pl011_write_lcr_h(uap, 0); |
1da177e4 LT |
1578 | writew(0, uap->port.membase + UART01x_DR); |
1579 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) | |
1580 | barrier(); | |
1581 | ||
570d2910 JM |
1582 | writew(fbrd, uap->port.membase + UART011_FBRD); |
1583 | writew(ibrd, uap->port.membase + UART011_IBRD); | |
1584 | pl011_write_lcr_h(uap, lcr_h); | |
1585 | ||
d8d8ffa4 SKS |
1586 | /* restore RTS and DTR */ |
1587 | cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR); | |
1588 | cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; | |
1da177e4 LT |
1589 | writew(cr, uap->port.membase + UART011_CR); |
1590 | ||
fe433907 JM |
1591 | spin_unlock_irq(&uap->port.lock); |
1592 | ||
1da177e4 LT |
1593 | /* |
1594 | * initialise the old status of the modem signals | |
1595 | */ | |
1596 | uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; | |
1597 | ||
68b65f73 RK |
1598 | /* Startup DMA */ |
1599 | pl011_dma_startup(uap); | |
1600 | ||
1da177e4 | 1601 | /* |
ead76f32 LW |
1602 | * Finally, enable interrupts, only timeouts when using DMA |
1603 | * if initial RX DMA job failed, start in interrupt mode | |
1604 | * as well. | |
1da177e4 LT |
1605 | */ |
1606 | spin_lock_irq(&uap->port.lock); | |
9b96fbac LW |
1607 | /* Clear out any spuriously appearing RX interrupts */ |
1608 | writew(UART011_RTIS | UART011_RXIS, | |
1609 | uap->port.membase + UART011_ICR); | |
ead76f32 LW |
1610 | uap->im = UART011_RTIM; |
1611 | if (!pl011_dma_rx_running(uap)) | |
1612 | uap->im |= UART011_RXIM; | |
1da177e4 LT |
1613 | writew(uap->im, uap->port.membase + UART011_IMSC); |
1614 | spin_unlock_irq(&uap->port.lock); | |
1615 | ||
1616 | return 0; | |
1617 | ||
1618 | clk_dis: | |
1c4c4394 | 1619 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
1620 | return retval; |
1621 | } | |
1622 | ||
ec489aa8 LW |
1623 | static void pl011_shutdown_channel(struct uart_amba_port *uap, |
1624 | unsigned int lcrh) | |
1625 | { | |
1626 | unsigned long val; | |
1627 | ||
1628 | val = readw(uap->port.membase + lcrh); | |
1629 | val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN); | |
1630 | writew(val, uap->port.membase + lcrh); | |
1631 | } | |
1632 | ||
1da177e4 LT |
1633 | static void pl011_shutdown(struct uart_port *port) |
1634 | { | |
a5820c24 DT |
1635 | struct uart_amba_port *uap = |
1636 | container_of(port, struct uart_amba_port, port); | |
d8d8ffa4 | 1637 | unsigned int cr; |
1da177e4 LT |
1638 | |
1639 | /* | |
1640 | * disable all interrupts | |
1641 | */ | |
1642 | spin_lock_irq(&uap->port.lock); | |
1643 | uap->im = 0; | |
1644 | writew(uap->im, uap->port.membase + UART011_IMSC); | |
1645 | writew(0xffff, uap->port.membase + UART011_ICR); | |
1646 | spin_unlock_irq(&uap->port.lock); | |
1647 | ||
68b65f73 RK |
1648 | pl011_dma_shutdown(uap); |
1649 | ||
1da177e4 LT |
1650 | /* |
1651 | * Free the interrupt | |
1652 | */ | |
1653 | free_irq(uap->port.irq, uap); | |
1654 | ||
1655 | /* | |
1656 | * disable the port | |
d8d8ffa4 SKS |
1657 | * disable the port. It should not disable RTS and DTR. |
1658 | * Also RTS and DTR state should be preserved to restore | |
1659 | * it during startup(). | |
1da177e4 | 1660 | */ |
3b43816f | 1661 | uap->autorts = false; |
fe433907 | 1662 | spin_lock_irq(&uap->port.lock); |
d8d8ffa4 SKS |
1663 | cr = readw(uap->port.membase + UART011_CR); |
1664 | uap->old_cr = cr; | |
1665 | cr &= UART011_CR_RTS | UART011_CR_DTR; | |
1666 | cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1667 | writew(cr, uap->port.membase + UART011_CR); | |
fe433907 | 1668 | spin_unlock_irq(&uap->port.lock); |
1da177e4 LT |
1669 | |
1670 | /* | |
1671 | * disable break condition and fifos | |
1672 | */ | |
ec489aa8 LW |
1673 | pl011_shutdown_channel(uap, uap->lcrh_rx); |
1674 | if (uap->lcrh_rx != uap->lcrh_tx) | |
1675 | pl011_shutdown_channel(uap, uap->lcrh_tx); | |
1da177e4 LT |
1676 | |
1677 | /* | |
1678 | * Shut down the clock producer | |
1679 | */ | |
1c4c4394 | 1680 | clk_disable_unprepare(uap->clk); |
78d80c5a | 1681 | /* Optionally let pins go into sleep states */ |
2b996fc5 | 1682 | pinctrl_pm_select_sleep_state(port->dev); |
c16d51a3 | 1683 | |
574de559 | 1684 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
1685 | struct amba_pl011_data *plat; |
1686 | ||
574de559 | 1687 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
1688 | if (plat->exit) |
1689 | plat->exit(); | |
1690 | } | |
1691 | ||
36f339d1 PH |
1692 | if (uap->port.ops->flush_buffer) |
1693 | uap->port.ops->flush_buffer(port); | |
1da177e4 LT |
1694 | } |
1695 | ||
1696 | static void | |
606d099c AC |
1697 | pl011_set_termios(struct uart_port *port, struct ktermios *termios, |
1698 | struct ktermios *old) | |
1da177e4 | 1699 | { |
a5820c24 DT |
1700 | struct uart_amba_port *uap = |
1701 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
1702 | unsigned int lcr_h, old_cr; |
1703 | unsigned long flags; | |
c19f12b5 RK |
1704 | unsigned int baud, quot, clkdiv; |
1705 | ||
1706 | if (uap->vendor->oversampling) | |
1707 | clkdiv = 8; | |
1708 | else | |
1709 | clkdiv = 16; | |
1da177e4 LT |
1710 | |
1711 | /* | |
1712 | * Ask the core to calculate the divisor for us. | |
1713 | */ | |
ac3e3fb4 | 1714 | baud = uart_get_baud_rate(port, termios, old, 0, |
c19f12b5 | 1715 | port->uartclk / clkdiv); |
89fa28db | 1716 | #ifdef CONFIG_DMA_ENGINE |
cb06ff10 CM |
1717 | /* |
1718 | * Adjust RX DMA polling rate with baud rate if not specified. | |
1719 | */ | |
1720 | if (uap->dmarx.auto_poll_rate) | |
1721 | uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud); | |
89fa28db | 1722 | #endif |
ac3e3fb4 LW |
1723 | |
1724 | if (baud > port->uartclk/16) | |
1725 | quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud); | |
1726 | else | |
1727 | quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud); | |
1da177e4 LT |
1728 | |
1729 | switch (termios->c_cflag & CSIZE) { | |
1730 | case CS5: | |
1731 | lcr_h = UART01x_LCRH_WLEN_5; | |
1732 | break; | |
1733 | case CS6: | |
1734 | lcr_h = UART01x_LCRH_WLEN_6; | |
1735 | break; | |
1736 | case CS7: | |
1737 | lcr_h = UART01x_LCRH_WLEN_7; | |
1738 | break; | |
1739 | default: // CS8 | |
1740 | lcr_h = UART01x_LCRH_WLEN_8; | |
1741 | break; | |
1742 | } | |
1743 | if (termios->c_cflag & CSTOPB) | |
1744 | lcr_h |= UART01x_LCRH_STP2; | |
1745 | if (termios->c_cflag & PARENB) { | |
1746 | lcr_h |= UART01x_LCRH_PEN; | |
1747 | if (!(termios->c_cflag & PARODD)) | |
1748 | lcr_h |= UART01x_LCRH_EPS; | |
1749 | } | |
ffca2b11 | 1750 | if (uap->fifosize > 1) |
1da177e4 LT |
1751 | lcr_h |= UART01x_LCRH_FEN; |
1752 | ||
1753 | spin_lock_irqsave(&port->lock, flags); | |
1754 | ||
1755 | /* | |
1756 | * Update the per-port timeout. | |
1757 | */ | |
1758 | uart_update_timeout(port, termios->c_cflag, baud); | |
1759 | ||
b63d4f0f | 1760 | port->read_status_mask = UART011_DR_OE | 255; |
1da177e4 | 1761 | if (termios->c_iflag & INPCK) |
b63d4f0f | 1762 | port->read_status_mask |= UART011_DR_FE | UART011_DR_PE; |
ef8b9ddc | 1763 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
b63d4f0f | 1764 | port->read_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1765 | |
1766 | /* | |
1767 | * Characters to ignore | |
1768 | */ | |
1769 | port->ignore_status_mask = 0; | |
1770 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1771 | port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE; |
1da177e4 | 1772 | if (termios->c_iflag & IGNBRK) { |
b63d4f0f | 1773 | port->ignore_status_mask |= UART011_DR_BE; |
1da177e4 LT |
1774 | /* |
1775 | * If we're ignoring parity and break indicators, | |
1776 | * ignore overruns too (for real raw support). | |
1777 | */ | |
1778 | if (termios->c_iflag & IGNPAR) | |
b63d4f0f | 1779 | port->ignore_status_mask |= UART011_DR_OE; |
1da177e4 LT |
1780 | } |
1781 | ||
1782 | /* | |
1783 | * Ignore all characters if CREAD is not set. | |
1784 | */ | |
1785 | if ((termios->c_cflag & CREAD) == 0) | |
b63d4f0f | 1786 | port->ignore_status_mask |= UART_DUMMY_DR_RX; |
1da177e4 LT |
1787 | |
1788 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
1789 | pl011_enable_ms(port); | |
1790 | ||
1791 | /* first, disable everything */ | |
1792 | old_cr = readw(port->membase + UART011_CR); | |
1793 | writew(0, port->membase + UART011_CR); | |
1794 | ||
3b43816f RV |
1795 | if (termios->c_cflag & CRTSCTS) { |
1796 | if (old_cr & UART011_CR_RTS) | |
1797 | old_cr |= UART011_CR_RTSEN; | |
1798 | ||
1799 | old_cr |= UART011_CR_CTSEN; | |
1800 | uap->autorts = true; | |
1801 | } else { | |
1802 | old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN); | |
1803 | uap->autorts = false; | |
1804 | } | |
1805 | ||
c19f12b5 RK |
1806 | if (uap->vendor->oversampling) { |
1807 | if (baud > port->uartclk / 16) | |
ac3e3fb4 LW |
1808 | old_cr |= ST_UART011_CR_OVSFACT; |
1809 | else | |
1810 | old_cr &= ~ST_UART011_CR_OVSFACT; | |
1811 | } | |
1812 | ||
c5dd553b LW |
1813 | /* |
1814 | * Workaround for the ST Micro oversampling variants to | |
1815 | * increase the bitrate slightly, by lowering the divisor, | |
1816 | * to avoid delayed sampling of start bit at high speeds, | |
1817 | * else we see data corruption. | |
1818 | */ | |
1819 | if (uap->vendor->oversampling) { | |
1820 | if ((baud >= 3000000) && (baud < 3250000) && (quot > 1)) | |
1821 | quot -= 1; | |
1822 | else if ((baud > 3250000) && (quot > 2)) | |
1823 | quot -= 2; | |
1824 | } | |
1da177e4 LT |
1825 | /* Set baud rate */ |
1826 | writew(quot & 0x3f, port->membase + UART011_FBRD); | |
1827 | writew(quot >> 6, port->membase + UART011_IBRD); | |
1828 | ||
1829 | /* | |
1830 | * ----------v----------v----------v----------v----- | |
c5dd553b LW |
1831 | * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER |
1832 | * UART011_FBRD & UART011_IBRD. | |
1da177e4 LT |
1833 | * ----------^----------^----------^----------^----- |
1834 | */ | |
b60f2f66 | 1835 | pl011_write_lcr_h(uap, lcr_h); |
1da177e4 LT |
1836 | writew(old_cr, port->membase + UART011_CR); |
1837 | ||
1838 | spin_unlock_irqrestore(&port->lock, flags); | |
1839 | } | |
1840 | ||
1841 | static const char *pl011_type(struct uart_port *port) | |
1842 | { | |
a5820c24 DT |
1843 | struct uart_amba_port *uap = |
1844 | container_of(port, struct uart_amba_port, port); | |
e8a7ba86 | 1845 | return uap->port.type == PORT_AMBA ? uap->type : NULL; |
1da177e4 LT |
1846 | } |
1847 | ||
1848 | /* | |
1849 | * Release the memory region(s) being used by 'port' | |
1850 | */ | |
e643f87f | 1851 | static void pl011_release_port(struct uart_port *port) |
1da177e4 LT |
1852 | { |
1853 | release_mem_region(port->mapbase, SZ_4K); | |
1854 | } | |
1855 | ||
1856 | /* | |
1857 | * Request the memory region(s) being used by 'port' | |
1858 | */ | |
e643f87f | 1859 | static int pl011_request_port(struct uart_port *port) |
1da177e4 LT |
1860 | { |
1861 | return request_mem_region(port->mapbase, SZ_4K, "uart-pl011") | |
1862 | != NULL ? 0 : -EBUSY; | |
1863 | } | |
1864 | ||
1865 | /* | |
1866 | * Configure/autoconfigure the port. | |
1867 | */ | |
e643f87f | 1868 | static void pl011_config_port(struct uart_port *port, int flags) |
1da177e4 LT |
1869 | { |
1870 | if (flags & UART_CONFIG_TYPE) { | |
1871 | port->type = PORT_AMBA; | |
e643f87f | 1872 | pl011_request_port(port); |
1da177e4 LT |
1873 | } |
1874 | } | |
1875 | ||
1876 | /* | |
1877 | * verify the new serial_struct (for TIOCSSERIAL). | |
1878 | */ | |
e643f87f | 1879 | static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser) |
1da177e4 LT |
1880 | { |
1881 | int ret = 0; | |
1882 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
1883 | ret = -EINVAL; | |
a62c4133 | 1884 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
1885 | ret = -EINVAL; |
1886 | if (ser->baud_base < 9600) | |
1887 | ret = -EINVAL; | |
1888 | return ret; | |
1889 | } | |
1890 | ||
1891 | static struct uart_ops amba_pl011_pops = { | |
e643f87f | 1892 | .tx_empty = pl011_tx_empty, |
1da177e4 | 1893 | .set_mctrl = pl011_set_mctrl, |
e643f87f | 1894 | .get_mctrl = pl011_get_mctrl, |
1da177e4 LT |
1895 | .stop_tx = pl011_stop_tx, |
1896 | .start_tx = pl011_start_tx, | |
1897 | .stop_rx = pl011_stop_rx, | |
1898 | .enable_ms = pl011_enable_ms, | |
1899 | .break_ctl = pl011_break_ctl, | |
1900 | .startup = pl011_startup, | |
1901 | .shutdown = pl011_shutdown, | |
68b65f73 | 1902 | .flush_buffer = pl011_dma_flush_buffer, |
1da177e4 LT |
1903 | .set_termios = pl011_set_termios, |
1904 | .type = pl011_type, | |
e643f87f LW |
1905 | .release_port = pl011_release_port, |
1906 | .request_port = pl011_request_port, | |
1907 | .config_port = pl011_config_port, | |
1908 | .verify_port = pl011_verify_port, | |
84b5ae15 | 1909 | #ifdef CONFIG_CONSOLE_POLL |
b3564c2c | 1910 | .poll_init = pl011_hwinit, |
e643f87f LW |
1911 | .poll_get_char = pl011_get_poll_char, |
1912 | .poll_put_char = pl011_put_poll_char, | |
84b5ae15 | 1913 | #endif |
1da177e4 LT |
1914 | }; |
1915 | ||
1916 | static struct uart_amba_port *amba_ports[UART_NR]; | |
1917 | ||
1918 | #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE | |
1919 | ||
d358788f | 1920 | static void pl011_console_putchar(struct uart_port *port, int ch) |
1da177e4 | 1921 | { |
a5820c24 DT |
1922 | struct uart_amba_port *uap = |
1923 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 1924 | |
d358788f RK |
1925 | while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) |
1926 | barrier(); | |
1da177e4 LT |
1927 | writew(ch, uap->port.membase + UART01x_DR); |
1928 | } | |
1929 | ||
1930 | static void | |
1931 | pl011_console_write(struct console *co, const char *s, unsigned int count) | |
1932 | { | |
1933 | struct uart_amba_port *uap = amba_ports[co->index]; | |
1934 | unsigned int status, old_cr, new_cr; | |
ef605fdb RV |
1935 | unsigned long flags; |
1936 | int locked = 1; | |
1da177e4 LT |
1937 | |
1938 | clk_enable(uap->clk); | |
1939 | ||
ef605fdb RV |
1940 | local_irq_save(flags); |
1941 | if (uap->port.sysrq) | |
1942 | locked = 0; | |
1943 | else if (oops_in_progress) | |
1944 | locked = spin_trylock(&uap->port.lock); | |
1945 | else | |
1946 | spin_lock(&uap->port.lock); | |
1947 | ||
1da177e4 LT |
1948 | /* |
1949 | * First save the CR then disable the interrupts | |
1950 | */ | |
1951 | old_cr = readw(uap->port.membase + UART011_CR); | |
1952 | new_cr = old_cr & ~UART011_CR_CTSEN; | |
1953 | new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE; | |
1954 | writew(new_cr, uap->port.membase + UART011_CR); | |
1955 | ||
d358788f | 1956 | uart_console_write(&uap->port, s, count, pl011_console_putchar); |
1da177e4 LT |
1957 | |
1958 | /* | |
1959 | * Finally, wait for transmitter to become empty | |
1960 | * and restore the TCR | |
1961 | */ | |
1962 | do { | |
1963 | status = readw(uap->port.membase + UART01x_FR); | |
1964 | } while (status & UART01x_FR_BUSY); | |
1965 | writew(old_cr, uap->port.membase + UART011_CR); | |
1966 | ||
ef605fdb RV |
1967 | if (locked) |
1968 | spin_unlock(&uap->port.lock); | |
1969 | local_irq_restore(flags); | |
1970 | ||
1da177e4 LT |
1971 | clk_disable(uap->clk); |
1972 | } | |
1973 | ||
1974 | static void __init | |
1975 | pl011_console_get_options(struct uart_amba_port *uap, int *baud, | |
1976 | int *parity, int *bits) | |
1977 | { | |
1978 | if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) { | |
1979 | unsigned int lcr_h, ibrd, fbrd; | |
1980 | ||
ec489aa8 | 1981 | lcr_h = readw(uap->port.membase + uap->lcrh_tx); |
1da177e4 LT |
1982 | |
1983 | *parity = 'n'; | |
1984 | if (lcr_h & UART01x_LCRH_PEN) { | |
1985 | if (lcr_h & UART01x_LCRH_EPS) | |
1986 | *parity = 'e'; | |
1987 | else | |
1988 | *parity = 'o'; | |
1989 | } | |
1990 | ||
1991 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
1992 | *bits = 7; | |
1993 | else | |
1994 | *bits = 8; | |
1995 | ||
1996 | ibrd = readw(uap->port.membase + UART011_IBRD); | |
1997 | fbrd = readw(uap->port.membase + UART011_FBRD); | |
1998 | ||
1999 | *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd); | |
ac3e3fb4 | 2000 | |
c19f12b5 | 2001 | if (uap->vendor->oversampling) { |
ac3e3fb4 LW |
2002 | if (readw(uap->port.membase + UART011_CR) |
2003 | & ST_UART011_CR_OVSFACT) | |
2004 | *baud *= 2; | |
2005 | } | |
1da177e4 LT |
2006 | } |
2007 | } | |
2008 | ||
2009 | static int __init pl011_console_setup(struct console *co, char *options) | |
2010 | { | |
2011 | struct uart_amba_port *uap; | |
2012 | int baud = 38400; | |
2013 | int bits = 8; | |
2014 | int parity = 'n'; | |
2015 | int flow = 'n'; | |
4b4851c6 | 2016 | int ret; |
1da177e4 LT |
2017 | |
2018 | /* | |
2019 | * Check whether an invalid uart number has been specified, and | |
2020 | * if so, search for the first available port that does have | |
2021 | * console support. | |
2022 | */ | |
2023 | if (co->index >= UART_NR) | |
2024 | co->index = 0; | |
2025 | uap = amba_ports[co->index]; | |
d28122a5 RK |
2026 | if (!uap) |
2027 | return -ENODEV; | |
1da177e4 | 2028 | |
78d80c5a | 2029 | /* Allow pins to be muxed in and configured */ |
2b996fc5 | 2030 | pinctrl_pm_select_default_state(uap->port.dev); |
78d80c5a | 2031 | |
4b4851c6 RK |
2032 | ret = clk_prepare(uap->clk); |
2033 | if (ret) | |
2034 | return ret; | |
2035 | ||
574de559 | 2036 | if (dev_get_platdata(uap->port.dev)) { |
c16d51a3 SKS |
2037 | struct amba_pl011_data *plat; |
2038 | ||
574de559 | 2039 | plat = dev_get_platdata(uap->port.dev); |
c16d51a3 SKS |
2040 | if (plat->init) |
2041 | plat->init(); | |
2042 | } | |
2043 | ||
1da177e4 LT |
2044 | uap->port.uartclk = clk_get_rate(uap->clk); |
2045 | ||
2046 | if (options) | |
2047 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2048 | else | |
2049 | pl011_console_get_options(uap, &baud, &parity, &bits); | |
2050 | ||
2051 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); | |
2052 | } | |
2053 | ||
2d93486c | 2054 | static struct uart_driver amba_reg; |
1da177e4 LT |
2055 | static struct console amba_console = { |
2056 | .name = "ttyAMA", | |
2057 | .write = pl011_console_write, | |
2058 | .device = uart_console_device, | |
2059 | .setup = pl011_console_setup, | |
2060 | .flags = CON_PRINTBUFFER, | |
2061 | .index = -1, | |
2062 | .data = &amba_reg, | |
2063 | }; | |
2064 | ||
2065 | #define AMBA_CONSOLE (&amba_console) | |
0d3c673e RH |
2066 | |
2067 | static void pl011_putc(struct uart_port *port, int c) | |
2068 | { | |
2069 | while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF) | |
2070 | ; | |
2071 | writeb(c, port->membase + UART01x_DR); | |
2072 | while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY) | |
2073 | ; | |
2074 | } | |
2075 | ||
2076 | static void pl011_early_write(struct console *con, const char *s, unsigned n) | |
2077 | { | |
2078 | struct earlycon_device *dev = con->data; | |
2079 | ||
2080 | uart_console_write(&dev->port, s, n, pl011_putc); | |
2081 | } | |
2082 | ||
2083 | static int __init pl011_early_console_setup(struct earlycon_device *device, | |
2084 | const char *opt) | |
2085 | { | |
2086 | if (!device->port.membase) | |
2087 | return -ENODEV; | |
2088 | ||
2089 | device->con->write = pl011_early_write; | |
2090 | return 0; | |
2091 | } | |
2092 | EARLYCON_DECLARE(pl011, pl011_early_console_setup); | |
45e0f0f5 | 2093 | OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup); |
0d3c673e | 2094 | |
1da177e4 LT |
2095 | #else |
2096 | #define AMBA_CONSOLE NULL | |
2097 | #endif | |
2098 | ||
2099 | static struct uart_driver amba_reg = { | |
2100 | .owner = THIS_MODULE, | |
2101 | .driver_name = "ttyAMA", | |
2102 | .dev_name = "ttyAMA", | |
2103 | .major = SERIAL_AMBA_MAJOR, | |
2104 | .minor = SERIAL_AMBA_MINOR, | |
2105 | .nr = UART_NR, | |
2106 | .cons = AMBA_CONSOLE, | |
2107 | }; | |
2108 | ||
32614aad ML |
2109 | static int pl011_probe_dt_alias(int index, struct device *dev) |
2110 | { | |
2111 | struct device_node *np; | |
2112 | static bool seen_dev_with_alias = false; | |
2113 | static bool seen_dev_without_alias = false; | |
2114 | int ret = index; | |
2115 | ||
2116 | if (!IS_ENABLED(CONFIG_OF)) | |
2117 | return ret; | |
2118 | ||
2119 | np = dev->of_node; | |
2120 | if (!np) | |
2121 | return ret; | |
2122 | ||
2123 | ret = of_alias_get_id(np, "serial"); | |
2124 | if (IS_ERR_VALUE(ret)) { | |
2125 | seen_dev_without_alias = true; | |
2126 | ret = index; | |
2127 | } else { | |
2128 | seen_dev_with_alias = true; | |
2129 | if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) { | |
2130 | dev_warn(dev, "requested serial port %d not available.\n", ret); | |
2131 | ret = index; | |
2132 | } | |
2133 | } | |
2134 | ||
2135 | if (seen_dev_with_alias && seen_dev_without_alias) | |
2136 | dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n"); | |
2137 | ||
2138 | return ret; | |
2139 | } | |
2140 | ||
aa25afad | 2141 | static int pl011_probe(struct amba_device *dev, const struct amba_id *id) |
1da177e4 LT |
2142 | { |
2143 | struct uart_amba_port *uap; | |
5926a295 | 2144 | struct vendor_data *vendor = id->data; |
1da177e4 LT |
2145 | void __iomem *base; |
2146 | int i, ret; | |
2147 | ||
2148 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2149 | if (amba_ports[i] == NULL) | |
2150 | break; | |
2151 | ||
7f6d942a TB |
2152 | if (i == ARRAY_SIZE(amba_ports)) |
2153 | return -EBUSY; | |
1da177e4 | 2154 | |
de609582 LW |
2155 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), |
2156 | GFP_KERNEL); | |
7f6d942a TB |
2157 | if (uap == NULL) |
2158 | return -ENOMEM; | |
1da177e4 | 2159 | |
32614aad ML |
2160 | i = pl011_probe_dt_alias(i, &dev->dev); |
2161 | ||
de609582 LW |
2162 | base = devm_ioremap(&dev->dev, dev->res.start, |
2163 | resource_size(&dev->res)); | |
7f6d942a TB |
2164 | if (!base) |
2165 | return -ENOMEM; | |
1da177e4 | 2166 | |
de609582 | 2167 | uap->clk = devm_clk_get(&dev->dev, NULL); |
7f6d942a TB |
2168 | if (IS_ERR(uap->clk)) |
2169 | return PTR_ERR(uap->clk); | |
1da177e4 | 2170 | |
c19f12b5 | 2171 | uap->vendor = vendor; |
ec489aa8 LW |
2172 | uap->lcrh_rx = vendor->lcrh_rx; |
2173 | uap->lcrh_tx = vendor->lcrh_tx; | |
d8d8ffa4 | 2174 | uap->old_cr = 0; |
ea33640a | 2175 | uap->fifosize = vendor->get_fifosize(dev); |
1da177e4 LT |
2176 | uap->port.dev = &dev->dev; |
2177 | uap->port.mapbase = dev->res.start; | |
2178 | uap->port.membase = base; | |
2179 | uap->port.iotype = UPIO_MEM; | |
2180 | uap->port.irq = dev->irq[0]; | |
ffca2b11 | 2181 | uap->port.fifosize = uap->fifosize; |
1da177e4 LT |
2182 | uap->port.ops = &amba_pl011_pops; |
2183 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
2184 | uap->port.line = i; | |
787b0c1f | 2185 | pl011_dma_probe(&dev->dev, uap); |
1da177e4 | 2186 | |
c3d8b76f LW |
2187 | /* Ensure interrupts from this UART are masked and cleared */ |
2188 | writew(0, uap->port.membase + UART011_IMSC); | |
2189 | writew(0xffff, uap->port.membase + UART011_ICR); | |
2190 | ||
e8a7ba86 RK |
2191 | snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev)); |
2192 | ||
1da177e4 LT |
2193 | amba_ports[i] = uap; |
2194 | ||
2195 | amba_set_drvdata(dev, uap); | |
ef2889f7 TB |
2196 | |
2197 | if (!amba_reg.state) { | |
2198 | ret = uart_register_driver(&amba_reg); | |
2199 | if (ret < 0) { | |
2200 | pr_err("Failed to register AMBA-PL011 driver\n"); | |
2201 | return ret; | |
2202 | } | |
2203 | } | |
2204 | ||
1da177e4 LT |
2205 | ret = uart_add_one_port(&amba_reg, &uap->port); |
2206 | if (ret) { | |
1da177e4 | 2207 | amba_ports[i] = NULL; |
ef2889f7 | 2208 | uart_unregister_driver(&amba_reg); |
68b65f73 | 2209 | pl011_dma_remove(uap); |
1da177e4 | 2210 | } |
7f6d942a | 2211 | |
1da177e4 LT |
2212 | return ret; |
2213 | } | |
2214 | ||
2215 | static int pl011_remove(struct amba_device *dev) | |
2216 | { | |
2217 | struct uart_amba_port *uap = amba_get_drvdata(dev); | |
1e7da053 | 2218 | bool busy = false; |
1da177e4 LT |
2219 | int i; |
2220 | ||
1da177e4 LT |
2221 | uart_remove_one_port(&amba_reg, &uap->port); |
2222 | ||
2223 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
2224 | if (amba_ports[i] == uap) | |
2225 | amba_ports[i] = NULL; | |
1e7da053 GL |
2226 | else if (amba_ports[i]) |
2227 | busy = true; | |
1da177e4 | 2228 | |
68b65f73 | 2229 | pl011_dma_remove(uap); |
1e7da053 GL |
2230 | if (!busy) |
2231 | uart_unregister_driver(&amba_reg); | |
1da177e4 LT |
2232 | return 0; |
2233 | } | |
2234 | ||
d0ce850d UH |
2235 | #ifdef CONFIG_PM_SLEEP |
2236 | static int pl011_suspend(struct device *dev) | |
b736b89f | 2237 | { |
d0ce850d | 2238 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2239 | |
2240 | if (!uap) | |
2241 | return -EINVAL; | |
2242 | ||
2243 | return uart_suspend_port(&amba_reg, &uap->port); | |
2244 | } | |
2245 | ||
d0ce850d | 2246 | static int pl011_resume(struct device *dev) |
b736b89f | 2247 | { |
d0ce850d | 2248 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
b736b89f LC |
2249 | |
2250 | if (!uap) | |
2251 | return -EINVAL; | |
2252 | ||
2253 | return uart_resume_port(&amba_reg, &uap->port); | |
2254 | } | |
2255 | #endif | |
2256 | ||
d0ce850d UH |
2257 | static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume); |
2258 | ||
2c39c9e1 | 2259 | static struct amba_id pl011_ids[] = { |
1da177e4 LT |
2260 | { |
2261 | .id = 0x00041011, | |
2262 | .mask = 0x000fffff, | |
5926a295 AR |
2263 | .data = &vendor_arm, |
2264 | }, | |
2265 | { | |
2266 | .id = 0x00380802, | |
2267 | .mask = 0x00ffffff, | |
2268 | .data = &vendor_st, | |
1da177e4 LT |
2269 | }, |
2270 | { 0, 0 }, | |
2271 | }; | |
2272 | ||
60f7a33b DM |
2273 | MODULE_DEVICE_TABLE(amba, pl011_ids); |
2274 | ||
1da177e4 LT |
2275 | static struct amba_driver pl011_driver = { |
2276 | .drv = { | |
2277 | .name = "uart-pl011", | |
d0ce850d | 2278 | .pm = &pl011_dev_pm_ops, |
1da177e4 LT |
2279 | }, |
2280 | .id_table = pl011_ids, | |
2281 | .probe = pl011_probe, | |
2282 | .remove = pl011_remove, | |
2283 | }; | |
2284 | ||
2285 | static int __init pl011_init(void) | |
2286 | { | |
1da177e4 LT |
2287 | printk(KERN_INFO "Serial: AMBA PL011 UART driver\n"); |
2288 | ||
ef2889f7 | 2289 | return amba_driver_register(&pl011_driver); |
1da177e4 LT |
2290 | } |
2291 | ||
2292 | static void __exit pl011_exit(void) | |
2293 | { | |
2294 | amba_driver_unregister(&pl011_driver); | |
1da177e4 LT |
2295 | } |
2296 | ||
4dd9e742 AR |
2297 | /* |
2298 | * While this can be a module, if builtin it's most likely the console | |
2299 | * So let's leave module_exit but move module_init to an earlier place | |
2300 | */ | |
2301 | arch_initcall(pl011_init); | |
1da177e4 LT |
2302 | module_exit(pl011_exit); |
2303 | ||
2304 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
2305 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); | |
2306 | MODULE_LICENSE("GPL"); |