]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/tty/serial/amba-pl011.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge 4.11-rc7 into tty-next
[mirror_ubuntu-artful-kernel.git] / drivers / tty / serial / amba-pl011.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
68b65f73 8 * Copyright (C) 2010 ST-Ericsson SA
1da177e4
LT		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
1da177e4
LT		 24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
1da177e4 31
cb06ff10 32
1da177e4
LT		 33#if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34#define SUPPORT_SYSRQ
35#endif
36
37#include <linux/module.h>
38#include <linux/ioport.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/sysrq.h>
42#include <linux/device.h>
43#include <linux/tty.h>
44#include <linux/tty_flip.h>
45#include <linux/serial_core.h>
46#include <linux/serial.h>
a62c80e5
RK		 47#include <linux/amba/bus.h>
48#include <linux/amba/serial.h>
f8ce2547 49#include <linux/clk.h>
5a0e3ad6 50#include <linux/slab.h>
68b65f73
RK		 51#include <linux/dmaengine.h>
52#include <linux/dma-mapping.h>
53#include <linux/scatterlist.h>
c16d51a3 54#include <linux/delay.h>
258aea76 55#include <linux/types.h>
32614aad
ML		 56#include <linux/of.h>
57#include <linux/of_device.h>
258e0551 58#include <linux/pinctrl/consumer.h>
cb70706c 59#include <linux/sizes.h>
de609582 60#include <linux/io.h>
3db9ab0b 61#include <linux/acpi.h>
1da177e4 62
9f25bc51
RK		 63#include "amba-pl011.h"
64
1da177e4
LT		 65#define UART_NR 14
66
67#define SERIAL_AMBA_MAJOR 204
68#define SERIAL_AMBA_MINOR 64
69#define SERIAL_AMBA_NR UART_NR
70
71#define AMBA_ISR_PASS_LIMIT 256
72
b63d4f0f
RK		 73#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
74#define UART_DUMMY_DR_RX (1 << 16)
1da177e4 75
debb7f64
RK		 76static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
77 [REG_DR] = UART01x_DR,
debb7f64 78 [REG_FR] = UART01x_FR,
e4df9a80
RK		 79 [REG_LCRH_RX] = UART011_LCRH,
80 [REG_LCRH_TX] = UART011_LCRH,
debb7f64
RK		 81 [REG_IBRD] = UART011_IBRD,
82 [REG_FBRD] = UART011_FBRD,
debb7f64
RK		 83 [REG_CR] = UART011_CR,
84 [REG_IFLS] = UART011_IFLS,
85 [REG_IMSC] = UART011_IMSC,
86 [REG_RIS] = UART011_RIS,
87 [REG_MIS] = UART011_MIS,
88 [REG_ICR] = UART011_ICR,
89 [REG_DMACR] = UART011_DMACR,
debb7f64
RK		 90};
91
5926a295
AR		 92/* There is by now at least one vendor with differing details, so handle it */
93struct vendor_data {
439403bd 94 const u16 *reg_offset;
5926a295 95 unsigned int ifls;
0e125a5f
SG		 96 unsigned int fr_busy;
97 unsigned int fr_dsr;
98 unsigned int fr_cts;
99 unsigned int fr_ri;
d8a4995b 100 unsigned int inv_fr;
84c3e03b 101 bool access_32b;
ac3e3fb4 102 bool oversampling;
38d62436 103 bool dma_threshold;
4fd0690b 104 bool cts_event_workaround;
71eec483 105 bool always_enabled;
cefc2d1d 106 bool fixed_options;
78506f22 107
ea33640a 108 unsigned int (*get_fifosize)(struct amba_device *dev);
5926a295
AR		 109};
110
ea33640a 111static unsigned int get_fifosize_arm(struct amba_device *dev)
78506f22 112{
ea33640a 113 return amba_rev(dev) < 3 ? 16 : 32;
78506f22
JK		 114}
115
5926a295 116static struct vendor_data vendor_arm = {
439403bd 117 .reg_offset = pl011_std_offsets,
5926a295 118 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 119 .fr_busy = UART01x_FR_BUSY,
120 .fr_dsr = UART01x_FR_DSR,
121 .fr_cts = UART01x_FR_CTS,
122 .fr_ri = UART011_FR_RI,
ac3e3fb4 123 .oversampling = false,
38d62436 124 .dma_threshold = false,
4fd0690b 125 .cts_event_workaround = false,
71eec483 126 .always_enabled = false,
cefc2d1d 127 .fixed_options = false,
78506f22 128 .get_fifosize = get_fifosize_arm,
5926a295
AR		 129};
130
0dd1e247 131static struct vendor_data vendor_sbsa = {
439403bd 132 .reg_offset = pl011_std_offsets,
0e125a5f
SG		 133 .fr_busy = UART01x_FR_BUSY,
134 .fr_dsr = UART01x_FR_DSR,
135 .fr_cts = UART01x_FR_CTS,
136 .fr_ri = UART011_FR_RI,
1aabf523 137 .access_32b = true,
0dd1e247
AP		 138 .oversampling = false,
139 .dma_threshold = false,
140 .cts_event_workaround = false,
141 .always_enabled = true,
142 .fixed_options = true,
143};
144
d8a4995b
CC		 145/*
146 * Erratum 44 for QDF2432v1 and QDF2400v1 SoCs describes the BUSY bit as
147 * occasionally getting stuck as 1. To avoid the potential for a hang, check
148 * TXFE == 0 instead of BUSY == 1. This may not be suitable for all UART
149 * implementations, so only do so if an affected platform is detected in
150 * parse_spcr().
151 */
152static bool qdf2400_e44_present = false;
153
154static struct vendor_data vendor_qdt_qdf2400_e44 = {
155 .reg_offset = pl011_std_offsets,
156 .fr_busy = UART011_FR_TXFE,
157 .fr_dsr = UART01x_FR_DSR,
158 .fr_cts = UART01x_FR_CTS,
159 .fr_ri = UART011_FR_RI,
160 .inv_fr = UART011_FR_TXFE,
161 .access_32b = true,
162 .oversampling = false,
163 .dma_threshold = false,
164 .cts_event_workaround = false,
165 .always_enabled = true,
166 .fixed_options = true,
167};
168
bf69ff8a
RK		 169static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
170 [REG_DR] = UART01x_DR,
171 [REG_ST_DMAWM] = ST_UART011_DMAWM,
172 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
173 [REG_FR] = UART01x_FR,
e4df9a80
RK		 174 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
175 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
bf69ff8a
RK		 176 [REG_IBRD] = UART011_IBRD,
177 [REG_FBRD] = UART011_FBRD,
bf69ff8a
RK		 178 [REG_CR] = UART011_CR,
179 [REG_IFLS] = UART011_IFLS,
180 [REG_IMSC] = UART011_IMSC,
181 [REG_RIS] = UART011_RIS,
182 [REG_MIS] = UART011_MIS,
183 [REG_ICR] = UART011_ICR,
184 [REG_DMACR] = UART011_DMACR,
185 [REG_ST_XFCR] = ST_UART011_XFCR,
186 [REG_ST_XON1] = ST_UART011_XON1,
187 [REG_ST_XON2] = ST_UART011_XON2,
188 [REG_ST_XOFF1] = ST_UART011_XOFF1,
189 [REG_ST_XOFF2] = ST_UART011_XOFF2,
190 [REG_ST_ITCR] = ST_UART011_ITCR,
191 [REG_ST_ITIP] = ST_UART011_ITIP,
192 [REG_ST_ABCR] = ST_UART011_ABCR,
193 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
194};
195
ea33640a 196static unsigned int get_fifosize_st(struct amba_device *dev)
78506f22
JK		 197{
198 return 64;
199}
200
5926a295 201static struct vendor_data vendor_st = {
bf69ff8a 202 .reg_offset = pl011_st_offsets,
5926a295 203 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
0e125a5f
SG		 204 .fr_busy = UART01x_FR_BUSY,
205 .fr_dsr = UART01x_FR_DSR,
206 .fr_cts = UART01x_FR_CTS,
207 .fr_ri = UART011_FR_RI,
ac3e3fb4 208 .oversampling = true,
38d62436 209 .dma_threshold = true,
4fd0690b 210 .cts_event_workaround = true,
71eec483 211 .always_enabled = false,
cefc2d1d 212 .fixed_options = false,
78506f22 213 .get_fifosize = get_fifosize_st,
1da177e4
LT		 214};
215
7ec75871
RK		 216static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
217 [REG_DR] = ZX_UART011_DR,
218 [REG_FR] = ZX_UART011_FR,
219 [REG_LCRH_RX] = ZX_UART011_LCRH,
220 [REG_LCRH_TX] = ZX_UART011_LCRH,
221 [REG_IBRD] = ZX_UART011_IBRD,
222 [REG_FBRD] = ZX_UART011_FBRD,
223 [REG_CR] = ZX_UART011_CR,
224 [REG_IFLS] = ZX_UART011_IFLS,
225 [REG_IMSC] = ZX_UART011_IMSC,
226 [REG_RIS] = ZX_UART011_RIS,
227 [REG_MIS] = ZX_UART011_MIS,
228 [REG_ICR] = ZX_UART011_ICR,
229 [REG_DMACR] = ZX_UART011_DMACR,
230};
231
9c267ddb
SG		 232static unsigned int get_fifosize_zte(struct amba_device *dev)
233{
234 return 16;
235}
236
2426fbc7 237static struct vendor_data vendor_zte = {
7ec75871
RK		 238 .reg_offset = pl011_zte_offsets,
239 .access_32b = true,
240 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
0e125a5f
SG		 241 .fr_busy = ZX_UART01x_FR_BUSY,
242 .fr_dsr = ZX_UART01x_FR_DSR,
243 .fr_cts = ZX_UART01x_FR_CTS,
244 .fr_ri = ZX_UART011_FR_RI,
9c267ddb 245 .get_fifosize = get_fifosize_zte,
7ec75871
RK		 246};
247
68b65f73 248/* Deals with DMA transactions */
ead76f32
LW		 249
250struct pl011_sgbuf {
251 struct scatterlist sg;
252 char *buf;
253};
254
255struct pl011_dmarx_data {
256 struct dma_chan *chan;
257 struct completion complete;
258 bool use_buf_b;
259 struct pl011_sgbuf sgbuf_a;
260 struct pl011_sgbuf sgbuf_b;
261 dma_cookie_t cookie;
262 bool running;
cb06ff10
CM		 263 struct timer_list timer;
264 unsigned int last_residue;
265 unsigned long last_jiffies;
266 bool auto_poll_rate;
267 unsigned int poll_rate;
268 unsigned int poll_timeout;
ead76f32
LW		 269};
270
68b65f73
RK		 271struct pl011_dmatx_data {
272 struct dma_chan *chan;
273 struct scatterlist sg;
274 char *buf;
275 bool queued;
276};
277
c19f12b5
RK		 278/*
279 * We wrap our port structure around the generic uart_port.
280 */
281struct uart_amba_port {
282 struct uart_port port;
debb7f64 283 const u16 *reg_offset;
c19f12b5
RK		 284 struct clk *clk;
285 const struct vendor_data *vendor;
68b65f73 286 unsigned int dmacr; /* dma control reg */
c19f12b5
RK		 287 unsigned int im; /* interrupt mask */
288 unsigned int old_status;
ffca2b11 289 unsigned int fifosize; /* vendor-specific */
d8d8ffa4 290 unsigned int old_cr; /* state during shutdown */
c19f12b5 291 bool autorts;
cefc2d1d 292 unsigned int fixed_baud; /* vendor-set fixed baud rate */
c19f12b5 293 char type[12];
68b65f73
RK		 294#ifdef CONFIG_DMA_ENGINE
295 /* DMA stuff */
ead76f32
LW		 296 bool using_tx_dma;
297 bool using_rx_dma;
298 struct pl011_dmarx_data dmarx;
68b65f73 299 struct pl011_dmatx_data dmatx;
1c9be310 300 bool dma_probed;
68b65f73
RK		 301#endif
302};
303
9f25bc51
RK		 304static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
305 unsigned int reg)
306{
debb7f64 307 return uap->reg_offset[reg];
9f25bc51
RK		 308}
309
b2a4e24c
RK		 310static unsigned int pl011_read(const struct uart_amba_port *uap,
311 unsigned int reg)
75836339 312{
84c3e03b
RK		 313 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
314
3b78fae7
TT		 315 return (uap->port.iotype == UPIO_MEM32) ?
316 readl_relaxed(addr) : readw_relaxed(addr);
75836339
RK		 317}
318
b2a4e24c
RK		 319static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
320 unsigned int reg)
75836339 321{
84c3e03b
RK		 322 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
323
3b78fae7 324 if (uap->port.iotype == UPIO_MEM32)
f5ce6edd 325 writel_relaxed(val, addr);
84c3e03b 326 else
f5ce6edd 327 writew_relaxed(val, addr);
75836339
RK		 328}
329
29772c4e
LW		 330/*
331 * Reads up to 256 characters from the FIFO or until it's empty and
332 * inserts them into the TTY layer. Returns the number of characters
333 * read from the FIFO.
334 */
335static int pl011_fifo_to_tty(struct uart_amba_port *uap)
336{
71a5cd8a
TT		 337 u16 status;
338 unsigned int ch, flag, max_count = 256;
29772c4e
LW		 339 int fifotaken = 0;
340
341 while (max_count--) {
9f25bc51 342 status = pl011_read(uap, REG_FR);
29772c4e
LW		 343 if (status & UART01x_FR_RXFE)
344 break;
345
346 /* Take chars from the FIFO and update status */
9f25bc51 347 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
29772c4e
LW		 348 flag = TTY_NORMAL;
349 uap->port.icount.rx++;
350 fifotaken++;
351
352 if (unlikely(ch & UART_DR_ERROR)) {
353 if (ch & UART011_DR_BE) {
354 ch &= ~(UART011_DR_FE | UART011_DR_PE);
355 uap->port.icount.brk++;
356 if (uart_handle_break(&uap->port))
357 continue;
358 } else if (ch & UART011_DR_PE)
359 uap->port.icount.parity++;
360 else if (ch & UART011_DR_FE)
361 uap->port.icount.frame++;
362 if (ch & UART011_DR_OE)
363 uap->port.icount.overrun++;
364
365 ch &= uap->port.read_status_mask;
366
367 if (ch & UART011_DR_BE)
368 flag = TTY_BREAK;
369 else if (ch & UART011_DR_PE)
370 flag = TTY_PARITY;
371 else if (ch & UART011_DR_FE)
372 flag = TTY_FRAME;
373 }
374
375 if (uart_handle_sysrq_char(&uap->port, ch & 255))
376 continue;
377
378 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
379 }
380
381 return fifotaken;
382}
383
384
68b65f73
RK		 385/*
386 * All the DMA operation mode stuff goes inside this ifdef.
387 * This assumes that you have a generic DMA device interface,
388 * no custom DMA interfaces are supported.
389 */
390#ifdef CONFIG_DMA_ENGINE
391
392#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
393
ead76f32
LW		 394static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
395 enum dma_data_direction dir)
396{
cb06ff10
CM		 397 dma_addr_t dma_addr;
398
399 sg->buf = dma_alloc_coherent(chan->device->dev,
400 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
ead76f32
LW		 401 if (!sg->buf)
402 return -ENOMEM;
403
cb06ff10
CM		 404 sg_init_table(&sg->sg, 1);
405 sg_set_page(&sg->sg, phys_to_page(dma_addr),
406 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
407 sg_dma_address(&sg->sg) = dma_addr;
c64be923 408 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
ead76f32 409
ead76f32
LW		 410 return 0;
411}
412
413static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
414 enum dma_data_direction dir)
415{
416 if (sg->buf) {
cb06ff10
CM		 417 dma_free_coherent(chan->device->dev,
418 PL011_DMA_BUFFER_SIZE, sg->buf,
419 sg_dma_address(&sg->sg));
ead76f32
LW		 420 }
421}
422
1c9be310 423static void pl011_dma_probe(struct uart_amba_port *uap)
68b65f73
RK		 424{
425 /* DMA is the sole user of the platform data right now */
574de559 426 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
1c9be310 427 struct device *dev = uap->port.dev;
68b65f73 428 struct dma_slave_config tx_conf = {
9f25bc51
RK		 429 .dst_addr = uap->port.mapbase +
430 pl011_reg_to_offset(uap, REG_DR),
68b65f73 431 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 432 .direction = DMA_MEM_TO_DEV,
68b65f73 433 .dst_maxburst = uap->fifosize >> 1,
258aea76 434 .device_fc = false,
68b65f73
RK		 435 };
436 struct dma_chan *chan;
437 dma_cap_mask_t mask;
438
1c9be310
JRO		 439 uap->dma_probed = true;
440 chan = dma_request_slave_channel_reason(dev, "tx");
441 if (IS_ERR(chan)) {
442 if (PTR_ERR(chan) == -EPROBE_DEFER) {
1c9be310
JRO		 443 uap->dma_probed = false;
444 return;
445 }
68b65f73 446
787b0c1f
AB		 447 /* We need platform data */
448 if (!plat || !plat->dma_filter) {
449 dev_info(uap->port.dev, "no DMA platform data\n");
450 return;
451 }
452
453 /* Try to acquire a generic DMA engine slave TX channel */
454 dma_cap_zero(mask);
455 dma_cap_set(DMA_SLAVE, mask);
456
457 chan = dma_request_channel(mask, plat->dma_filter,
458 plat->dma_tx_param);
459 if (!chan) {
460 dev_err(uap->port.dev, "no TX DMA channel!\n");
461 return;
462 }
68b65f73
RK		 463 }
464
465 dmaengine_slave_config(chan, &tx_conf);
466 uap->dmatx.chan = chan;
467
468 dev_info(uap->port.dev, "DMA channel TX %s\n",
469 dma_chan_name(uap->dmatx.chan));
ead76f32
LW		 470
471 /* Optionally make use of an RX channel as well */
787b0c1f 472 chan = dma_request_slave_channel(dev, "rx");
0d3c673e 473
d9e105ca 474 if (!chan && plat && plat->dma_rx_param) {
787b0c1f
AB		 475 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
476
477 if (!chan) {
478 dev_err(uap->port.dev, "no RX DMA channel!\n");
479 return;
480 }
481 }
482
483 if (chan) {
ead76f32 484 struct dma_slave_config rx_conf = {
9f25bc51
RK		 485 .src_addr = uap->port.mapbase +
486 pl011_reg_to_offset(uap, REG_DR),
ead76f32 487 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
a485df4b 488 .direction = DMA_DEV_TO_MEM,
b2aeb775 489 .src_maxburst = uap->fifosize >> 2,
258aea76 490 .device_fc = false,
ead76f32 491 };
2d3b7d6e
AJ		 492 struct dma_slave_caps caps;
493
494 /*
495 * Some DMA controllers provide information on their capabilities.
496 * If the controller does, check for suitable residue processing
497 * otherwise assime all is well.
498 */
499 if (0 == dma_get_slave_caps(chan, &caps)) {
500 if (caps.residue_granularity ==
501 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
502 dma_release_channel(chan);
503 dev_info(uap->port.dev,
504 "RX DMA disabled - no residue processing\n");
505 return;
506 }
507 }
ead76f32
LW		 508 dmaengine_slave_config(chan, &rx_conf);
509 uap->dmarx.chan = chan;
510
98267d33 511 uap->dmarx.auto_poll_rate = false;
8f898bfd 512 if (plat && plat->dma_rx_poll_enable) {
cb06ff10
CM		 513 /* Set poll rate if specified. */
514 if (plat->dma_rx_poll_rate) {
515 uap->dmarx.auto_poll_rate = false;
516 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
517 } else {
518 /*
519 * 100 ms defaults to poll rate if not
520 * specified. This will be adjusted with
521 * the baud rate at set_termios.
522 */
523 uap->dmarx.auto_poll_rate = true;
524 uap->dmarx.poll_rate = 100;
525 }
526 /* 3 secs defaults poll_timeout if not specified. */
527 if (plat->dma_rx_poll_timeout)
528 uap->dmarx.poll_timeout =
529 plat->dma_rx_poll_timeout;
530 else
531 uap->dmarx.poll_timeout = 3000;
98267d33
AJ		 532 } else if (!plat && dev->of_node) {
533 uap->dmarx.auto_poll_rate = of_property_read_bool(
534 dev->of_node, "auto-poll");
535 if (uap->dmarx.auto_poll_rate) {
536 u32 x;
537
538 if (0 == of_property_read_u32(dev->of_node,
539 "poll-rate-ms", &x))
540 uap->dmarx.poll_rate = x;
541 else
542 uap->dmarx.poll_rate = 100;
543 if (0 == of_property_read_u32(dev->of_node,
544 "poll-timeout-ms", &x))
545 uap->dmarx.poll_timeout = x;
546 else
547 uap->dmarx.poll_timeout = 3000;
548 }
549 }
ead76f32
LW		 550 dev_info(uap->port.dev, "DMA channel RX %s\n",
551 dma_chan_name(uap->dmarx.chan));
552 }
68b65f73
RK		 553}
554
68b65f73
RK		 555static void pl011_dma_remove(struct uart_amba_port *uap)
556{
68b65f73
RK		 557 if (uap->dmatx.chan)
558 dma_release_channel(uap->dmatx.chan);
ead76f32
LW		 559 if (uap->dmarx.chan)
560 dma_release_channel(uap->dmarx.chan);
68b65f73
RK		 561}
562
734745ca 563/* Forward declare these for the refill routine */
68b65f73 564static int pl011_dma_tx_refill(struct uart_amba_port *uap);
734745ca 565static void pl011_start_tx_pio(struct uart_amba_port *uap);
68b65f73
RK		 566
567/*
568 * The current DMA TX buffer has been sent.
569 * Try to queue up another DMA buffer.
570 */
571static void pl011_dma_tx_callback(void *data)
572{
573 struct uart_amba_port *uap = data;
574 struct pl011_dmatx_data *dmatx = &uap->dmatx;
575 unsigned long flags;
576 u16 dmacr;
577
578 spin_lock_irqsave(&uap->port.lock, flags);
579 if (uap->dmatx.queued)
580 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
581 DMA_TO_DEVICE);
582
583 dmacr = uap->dmacr;
584 uap->dmacr = dmacr & ~UART011_TXDMAE;
9f25bc51 585 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 586
587 /*
588 * If TX DMA was disabled, it means that we've stopped the DMA for
589 * some reason (eg, XOFF received, or we want to send an X-char.)
590 *
591 * Note: we need to be careful here of a potential race between DMA
592 * and the rest of the driver - if the driver disables TX DMA while
593 * a TX buffer completing, we must update the tx queued status to
594 * get further refills (hence we check dmacr).
595 */
596 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
597 uart_circ_empty(&uap->port.state->xmit)) {
598 uap->dmatx.queued = false;
599 spin_unlock_irqrestore(&uap->port.lock, flags);
600 return;
601 }
602
734745ca 603 if (pl011_dma_tx_refill(uap) <= 0)
68b65f73
RK		 604 /*
605 * We didn't queue a DMA buffer for some reason, but we
606 * have data pending to be sent. Re-enable the TX IRQ.
607 */
734745ca
DM		 608 pl011_start_tx_pio(uap);
609
68b65f73
RK		 610 spin_unlock_irqrestore(&uap->port.lock, flags);
611}
612
613/*
614 * Try to refill the TX DMA buffer.
615 * Locking: called with port lock held and IRQs disabled.
616 * Returns:
617 * 1 if we queued up a TX DMA buffer.
618 * 0 if we didn't want to handle this by DMA
619 * <0 on error
620 */
621static int pl011_dma_tx_refill(struct uart_amba_port *uap)
622{
623 struct pl011_dmatx_data *dmatx = &uap->dmatx;
624 struct dma_chan *chan = dmatx->chan;
625 struct dma_device *dma_dev = chan->device;
626 struct dma_async_tx_descriptor *desc;
627 struct circ_buf *xmit = &uap->port.state->xmit;
628 unsigned int count;
629
630 /*
631 * Try to avoid the overhead involved in using DMA if the
632 * transaction fits in the first half of the FIFO, by using
633 * the standard interrupt handling. This ensures that we
634 * issue a uart_write_wakeup() at the appropriate time.
635 */
636 count = uart_circ_chars_pending(xmit);
637 if (count < (uap->fifosize >> 1)) {
638 uap->dmatx.queued = false;
639 return 0;
640 }
641
642 /*
643 * Bodge: don't send the last character by DMA, as this
644 * will prevent XON from notifying us to restart DMA.
645 */
646 count -= 1;
647
648 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
649 if (count > PL011_DMA_BUFFER_SIZE)
650 count = PL011_DMA_BUFFER_SIZE;
651
652 if (xmit->tail < xmit->head)
653 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
654 else {
655 size_t first = UART_XMIT_SIZE - xmit->tail;
e2a545a6
AJ		 656 size_t second;
657
658 if (first > count)
659 first = count;
660 second = count - first;
68b65f73
RK		 661
662 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
663 if (second)
664 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
665 }
666
667 dmatx->sg.length = count;
668
669 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
670 uap->dmatx.queued = false;
671 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
672 return -EBUSY;
673 }
674
16052827 675 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
68b65f73
RK		 676 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
677 if (!desc) {
678 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
679 uap->dmatx.queued = false;
680 /*
681 * If DMA cannot be used right now, we complete this
682 * transaction via IRQ and let the TTY layer retry.
683 */
684 dev_dbg(uap->port.dev, "TX DMA busy\n");
685 return -EBUSY;
686 }
687
688 /* Some data to go along to the callback */
689 desc->callback = pl011_dma_tx_callback;
690 desc->callback_param = uap;
691
692 /* All errors should happen at prepare time */
693 dmaengine_submit(desc);
694
695 /* Fire the DMA transaction */
696 dma_dev->device_issue_pending(chan);
697
698 uap->dmacr |= UART011_TXDMAE;
9f25bc51 699 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 700 uap->dmatx.queued = true;
701
702 /*
703 * Now we know that DMA will fire, so advance the ring buffer
704 * with the stuff we just dispatched.
705 */
706 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
707 uap->port.icount.tx += count;
708
709 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
710 uart_write_wakeup(&uap->port);
711
712 return 1;
713}
714
715/*
716 * We received a transmit interrupt without a pending X-char but with
717 * pending characters.
718 * Locking: called with port lock held and IRQs disabled.
719 * Returns:
720 * false if we want to use PIO to transmit
721 * true if we queued a DMA buffer
722 */
723static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
724{
ead76f32 725 if (!uap->using_tx_dma)
68b65f73
RK		 726 return false;
727
728 /*
729 * If we already have a TX buffer queued, but received a
730 * TX interrupt, it will be because we've just sent an X-char.
731 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
732 */
733 if (uap->dmatx.queued) {
734 uap->dmacr |= UART011_TXDMAE;
9f25bc51 735 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 736 uap->im &= ~UART011_TXIM;
9f25bc51 737 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 738 return true;
739 }
740
741 /*
742 * We don't have a TX buffer queued, so try to queue one.
25985edc 743 * If we successfully queued a buffer, mask the TX IRQ.
68b65f73
RK		 744 */
745 if (pl011_dma_tx_refill(uap) > 0) {
746 uap->im &= ~UART011_TXIM;
9f25bc51 747 pl011_write(uap->im, uap, REG_IMSC);
68b65f73
RK		 748 return true;
749 }
750 return false;
751}
752
753/*
754 * Stop the DMA transmit (eg, due to received XOFF).
755 * Locking: called with port lock held and IRQs disabled.
756 */
757static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
758{
759 if (uap->dmatx.queued) {
760 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 761 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 762 }
763}
764
765/*
766 * Try to start a DMA transmit, or in the case of an XON/OFF
767 * character queued for send, try to get that character out ASAP.
768 * Locking: called with port lock held and IRQs disabled.
769 * Returns:
770 * false if we want the TX IRQ to be enabled
771 * true if we have a buffer queued
772 */
773static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
774{
775 u16 dmacr;
776
ead76f32 777 if (!uap->using_tx_dma)
68b65f73
RK		 778 return false;
779
780 if (!uap->port.x_char) {
781 /* no X-char, try to push chars out in DMA mode */
782 bool ret = true;
783
784 if (!uap->dmatx.queued) {
785 if (pl011_dma_tx_refill(uap) > 0) {
786 uap->im &= ~UART011_TXIM;
9f25bc51 787 pl011_write(uap->im, uap, REG_IMSC);
734745ca 788 } else
68b65f73 789 ret = false;
68b65f73
RK		 790 } else if (!(uap->dmacr & UART011_TXDMAE)) {
791 uap->dmacr |= UART011_TXDMAE;
9f25bc51 792 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 793 }
794 return ret;
795 }
796
797 /*
798 * We have an X-char to send. Disable DMA to prevent it loading
799 * the TX fifo, and then see if we can stuff it into the FIFO.
800 */
801 dmacr = uap->dmacr;
802 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 803 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73 804
9f25bc51 805 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
68b65f73
RK		 806 /*
807 * No space in the FIFO, so enable the transmit interrupt
808 * so we know when there is space. Note that once we've
809 * loaded the character, we should just re-enable DMA.
810 */
811 return false;
812 }
813
9f25bc51 814 pl011_write(uap->port.x_char, uap, REG_DR);
68b65f73
RK		 815 uap->port.icount.tx++;
816 uap->port.x_char = 0;
817
818 /* Success - restore the DMA state */
819 uap->dmacr = dmacr;
9f25bc51 820 pl011_write(dmacr, uap, REG_DMACR);
68b65f73
RK		 821
822 return true;
823}
824
825/*
826 * Flush the transmit buffer.
827 * Locking: called with port lock held and IRQs disabled.
828 */
829static void pl011_dma_flush_buffer(struct uart_port *port)
b83286bf
FE		 830__releases(&uap->port.lock)
831__acquires(&uap->port.lock)
68b65f73 832{
a5820c24
DT		 833 struct uart_amba_port *uap =
834 container_of(port, struct uart_amba_port, port);
68b65f73 835
ead76f32 836 if (!uap->using_tx_dma)
68b65f73
RK		 837 return;
838
839 /* Avoid deadlock with the DMA engine callback */
840 spin_unlock(&uap->port.lock);
841 dmaengine_terminate_all(uap->dmatx.chan);
842 spin_lock(&uap->port.lock);
843 if (uap->dmatx.queued) {
844 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
845 DMA_TO_DEVICE);
846 uap->dmatx.queued = false;
847 uap->dmacr &= ~UART011_TXDMAE;
9f25bc51 848 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 849 }
850}
851
ead76f32
LW		 852static void pl011_dma_rx_callback(void *data);
853
854static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
855{
856 struct dma_chan *rxchan = uap->dmarx.chan;
ead76f32
LW		 857 struct pl011_dmarx_data *dmarx = &uap->dmarx;
858 struct dma_async_tx_descriptor *desc;
859 struct pl011_sgbuf *sgbuf;
860
861 if (!rxchan)
862 return -EIO;
863
864 /* Start the RX DMA job */
865 sgbuf = uap->dmarx.use_buf_b ?
866 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
16052827 867 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
a485df4b 868 DMA_DEV_TO_MEM,
ead76f32
LW		 869 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
870 /*
871 * If the DMA engine is busy and cannot prepare a
872 * channel, no big deal, the driver will fall back
873 * to interrupt mode as a result of this error code.
874 */
875 if (!desc) {
876 uap->dmarx.running = false;
877 dmaengine_terminate_all(rxchan);
878 return -EBUSY;
879 }
880
881 /* Some data to go along to the callback */
882 desc->callback = pl011_dma_rx_callback;
883 desc->callback_param = uap;
884 dmarx->cookie = dmaengine_submit(desc);
885 dma_async_issue_pending(rxchan);
886
887 uap->dmacr |= UART011_RXDMAE;
9f25bc51 888 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 889 uap->dmarx.running = true;
890
891 uap->im &= ~UART011_RXIM;
9f25bc51 892 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 893
894 return 0;
895}
896
897/*
898 * This is called when either the DMA job is complete, or
899 * the FIFO timeout interrupt occurred. This must be called
900 * with the port spinlock uap->port.lock held.
901 */
902static void pl011_dma_rx_chars(struct uart_amba_port *uap,
903 u32 pending, bool use_buf_b,
904 bool readfifo)
905{
05c7cd39 906 struct tty_port *port = &uap->port.state->port;
ead76f32
LW		 907 struct pl011_sgbuf *sgbuf = use_buf_b ?
908 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
ead76f32
LW		 909 int dma_count = 0;
910 u32 fifotaken = 0; /* only used for vdbg() */
911
cb06ff10
CM		 912 struct pl011_dmarx_data *dmarx = &uap->dmarx;
913 int dmataken = 0;
914
915 if (uap->dmarx.poll_rate) {
916 /* The data can be taken by polling */
917 dmataken = sgbuf->sg.length - dmarx->last_residue;
918 /* Recalculate the pending size */
919 if (pending >= dmataken)
920 pending -= dmataken;
921 }
922
923 /* Pick the remain data from the DMA */
ead76f32 924 if (pending) {
ead76f32
LW		 925
926 /*
927 * First take all chars in the DMA pipe, then look in the FIFO.
928 * Note that tty_insert_flip_buf() tries to take as many chars
929 * as it can.
930 */
cb06ff10
CM		 931 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
932 pending);
ead76f32
LW		 933
934 uap->port.icount.rx += dma_count;
935 if (dma_count < pending)
936 dev_warn(uap->port.dev,
937 "couldn't insert all characters (TTY is full?)\n");
938 }
939
cb06ff10
CM		 940 /* Reset the last_residue for Rx DMA poll */
941 if (uap->dmarx.poll_rate)
942 dmarx->last_residue = sgbuf->sg.length;
943
ead76f32
LW		 944 /*
945 * Only continue with trying to read the FIFO if all DMA chars have
946 * been taken first.
947 */
948 if (dma_count == pending && readfifo) {
949 /* Clear any error flags */
75836339 950 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
9f25bc51 951 UART011_FEIS, uap, REG_ICR);
ead76f32
LW		 952
953 /*
954 * If we read all the DMA'd characters, and we had an
29772c4e
LW		 955 * incomplete buffer, that could be due to an rx error, or
956 * maybe we just timed out. Read any pending chars and check
957 * the error status.
958 *
959 * Error conditions will only occur in the FIFO, these will
960 * trigger an immediate interrupt and stop the DMA job, so we
961 * will always find the error in the FIFO, never in the DMA
962 * buffer.
ead76f32 963 */
29772c4e 964 fifotaken = pl011_fifo_to_tty(uap);
ead76f32
LW		 965 }
966
967 spin_unlock(&uap->port.lock);
968 dev_vdbg(uap->port.dev,
969 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
970 dma_count, fifotaken);
2e124b4a 971 tty_flip_buffer_push(port);
ead76f32
LW		 972 spin_lock(&uap->port.lock);
973}
974
975static void pl011_dma_rx_irq(struct uart_amba_port *uap)
976{
977 struct pl011_dmarx_data *dmarx = &uap->dmarx;
978 struct dma_chan *rxchan = dmarx->chan;
979 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
980 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
981 size_t pending;
982 struct dma_tx_state state;
983 enum dma_status dmastat;
984
985 /*
986 * Pause the transfer so we can trust the current counter,
987 * do this before we pause the PL011 block, else we may
988 * overflow the FIFO.
989 */
990 if (dmaengine_pause(rxchan))
991 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
992 dmastat = rxchan->device->device_tx_status(rxchan,
993 dmarx->cookie, &state);
994 if (dmastat != DMA_PAUSED)
995 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
996
997 /* Disable RX DMA - incoming data will wait in the FIFO */
998 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 999 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32
LW		 1000 uap->dmarx.running = false;
1001
1002 pending = sgbuf->sg.length - state.residue;
1003 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1004 /* Then we terminate the transfer - we now know our residue */
1005 dmaengine_terminate_all(rxchan);
1006
1007 /*
1008 * This will take the chars we have so far and insert
1009 * into the framework.
1010 */
1011 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
1012
1013 /* Switch buffer & re-trigger DMA job */
1014 dmarx->use_buf_b = !dmarx->use_buf_b;
1015 if (pl011_dma_rx_trigger_dma(uap)) {
1016 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1017 "fall back to interrupt mode\n");
1018 uap->im |= UART011_RXIM;
9f25bc51 1019 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1020 }
1021}
1022
1023static void pl011_dma_rx_callback(void *data)
1024{
1025 struct uart_amba_port *uap = data;
1026 struct pl011_dmarx_data *dmarx = &uap->dmarx;
6dc01aa6 1027 struct dma_chan *rxchan = dmarx->chan;
ead76f32 1028 bool lastbuf = dmarx->use_buf_b;
6dc01aa6
CM		 1029 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1030 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1031 size_t pending;
1032 struct dma_tx_state state;
ead76f32
LW		 1033 int ret;
1034
1035 /*
1036 * This completion interrupt occurs typically when the
1037 * RX buffer is totally stuffed but no timeout has yet
1038 * occurred. When that happens, we just want the RX
1039 * routine to flush out the secondary DMA buffer while
1040 * we immediately trigger the next DMA job.
1041 */
1042 spin_lock_irq(&uap->port.lock);
6dc01aa6
CM		 1043 /*
1044 * Rx data can be taken by the UART interrupts during
1045 * the DMA irq handler. So we check the residue here.
1046 */
1047 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1048 pending = sgbuf->sg.length - state.residue;
1049 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1050 /* Then we terminate the transfer - we now know our residue */
1051 dmaengine_terminate_all(rxchan);
1052
ead76f32
LW		 1053 uap->dmarx.running = false;
1054 dmarx->use_buf_b = !lastbuf;
1055 ret = pl011_dma_rx_trigger_dma(uap);
1056
6dc01aa6 1057 pl011_dma_rx_chars(uap, pending, lastbuf, false);
ead76f32
LW		 1058 spin_unlock_irq(&uap->port.lock);
1059 /*
1060 * Do this check after we picked the DMA chars so we don't
1061 * get some IRQ immediately from RX.
1062 */
1063 if (ret) {
1064 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1065 "fall back to interrupt mode\n");
1066 uap->im |= UART011_RXIM;
9f25bc51 1067 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1068 }
1069}
1070
1071/*
1072 * Stop accepting received characters, when we're shutting down or
1073 * suspending this port.
1074 * Locking: called with port lock held and IRQs disabled.
1075 */
1076static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1077{
1078 /* FIXME. Just disable the DMA enable */
1079 uap->dmacr &= ~UART011_RXDMAE;
9f25bc51 1080 pl011_write(uap->dmacr, uap, REG_DMACR);
ead76f32 1081}
68b65f73 1082
cb06ff10
CM		 1083/*
1084 * Timer handler for Rx DMA polling.
1085 * Every polling, It checks the residue in the dma buffer and transfer
1086 * data to the tty. Also, last_residue is updated for the next polling.
1087 */
1088static void pl011_dma_rx_poll(unsigned long args)
1089{
1090 struct uart_amba_port *uap = (struct uart_amba_port *)args;
1091 struct tty_port *port = &uap->port.state->port;
1092 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1093 struct dma_chan *rxchan = uap->dmarx.chan;
1094 unsigned long flags = 0;
1095 unsigned int dmataken = 0;
1096 unsigned int size = 0;
1097 struct pl011_sgbuf *sgbuf;
1098 int dma_count;
1099 struct dma_tx_state state;
1100
1101 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1102 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1103 if (likely(state.residue < dmarx->last_residue)) {
1104 dmataken = sgbuf->sg.length - dmarx->last_residue;
1105 size = dmarx->last_residue - state.residue;
1106 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1107 size);
1108 if (dma_count == size)
1109 dmarx->last_residue = state.residue;
1110 dmarx->last_jiffies = jiffies;
1111 }
1112 tty_flip_buffer_push(port);
1113
1114 /*
1115 * If no data is received in poll_timeout, the driver will fall back
1116 * to interrupt mode. We will retrigger DMA at the first interrupt.
1117 */
1118 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1119 > uap->dmarx.poll_timeout) {
1120
1121 spin_lock_irqsave(&uap->port.lock, flags);
1122 pl011_dma_rx_stop(uap);
c25a1ad7 1123 uap->im |= UART011_RXIM;
9f25bc51 1124 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10
CM		 1125 spin_unlock_irqrestore(&uap->port.lock, flags);
1126
1127 uap->dmarx.running = false;
1128 dmaengine_terminate_all(rxchan);
1129 del_timer(&uap->dmarx.timer);
1130 } else {
1131 mod_timer(&uap->dmarx.timer,
1132 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1133 }
1134}
1135
68b65f73
RK		 1136static void pl011_dma_startup(struct uart_amba_port *uap)
1137{
ead76f32
LW		 1138 int ret;
1139
1c9be310
JRO		 1140 if (!uap->dma_probed)
1141 pl011_dma_probe(uap);
1142
68b65f73
RK		 1143 if (!uap->dmatx.chan)
1144 return;
1145
4c0be45b 1146 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
68b65f73
RK		 1147 if (!uap->dmatx.buf) {
1148 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1149 uap->port.fifosize = uap->fifosize;
1150 return;
1151 }
1152
1153 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1154
1155 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1156 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
ead76f32
LW		 1157 uap->using_tx_dma = true;
1158
1159 if (!uap->dmarx.chan)
1160 goto skip_rx;
1161
1162 /* Allocate and map DMA RX buffers */
1163 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1164 DMA_FROM_DEVICE);
1165 if (ret) {
1166 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1167 "RX buffer A", ret);
1168 goto skip_rx;
1169 }
68b65f73 1170
ead76f32
LW		 1171 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1172 DMA_FROM_DEVICE);
1173 if (ret) {
1174 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1175 "RX buffer B", ret);
1176 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1177 DMA_FROM_DEVICE);
1178 goto skip_rx;
1179 }
1180
1181 uap->using_rx_dma = true;
68b65f73 1182
ead76f32 1183skip_rx:
68b65f73
RK		 1184 /* Turn on DMA error (RX/TX will be enabled on demand) */
1185 uap->dmacr |= UART011_DMAONERR;
9f25bc51 1186 pl011_write(uap->dmacr, uap, REG_DMACR);
38d62436
RK		 1187
1188 /*
1189 * ST Micro variants has some specific dma burst threshold
1190 * compensation. Set this to 16 bytes, so burst will only
1191 * be issued above/below 16 bytes.
1192 */
1193 if (uap->vendor->dma_threshold)
75836339 1194 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
9f25bc51 1195 uap, REG_ST_DMAWM);
ead76f32
LW		 1196
1197 if (uap->using_rx_dma) {
1198 if (pl011_dma_rx_trigger_dma(uap))
1199 dev_dbg(uap->port.dev, "could not trigger initial "
1200 "RX DMA job, fall back to interrupt mode\n");
cb06ff10
CM		 1201 if (uap->dmarx.poll_rate) {
1202 init_timer(&(uap->dmarx.timer));
1203 uap->dmarx.timer.function = pl011_dma_rx_poll;
1204 uap->dmarx.timer.data = (unsigned long)uap;
1205 mod_timer(&uap->dmarx.timer,
1206 jiffies +
1207 msecs_to_jiffies(uap->dmarx.poll_rate));
1208 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1209 uap->dmarx.last_jiffies = jiffies;
1210 }
ead76f32 1211 }
68b65f73
RK		 1212}
1213
1214static void pl011_dma_shutdown(struct uart_amba_port *uap)
1215{
ead76f32 1216 if (!(uap->using_tx_dma || uap->using_rx_dma))
68b65f73
RK		 1217 return;
1218
1219 /* Disable RX and TX DMA */
0e125a5f 1220 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
2f2fd089 1221 cpu_relax();
68b65f73
RK		 1222
1223 spin_lock_irq(&uap->port.lock);
1224 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
9f25bc51 1225 pl011_write(uap->dmacr, uap, REG_DMACR);
68b65f73
RK		 1226 spin_unlock_irq(&uap->port.lock);
1227
ead76f32
LW		 1228 if (uap->using_tx_dma) {
1229 /* In theory, this should already be done by pl011_dma_flush_buffer */
1230 dmaengine_terminate_all(uap->dmatx.chan);
1231 if (uap->dmatx.queued) {
1232 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1233 DMA_TO_DEVICE);
1234 uap->dmatx.queued = false;
1235 }
1236
1237 kfree(uap->dmatx.buf);
1238 uap->using_tx_dma = false;
68b65f73
RK		 1239 }
1240
ead76f32
LW		 1241 if (uap->using_rx_dma) {
1242 dmaengine_terminate_all(uap->dmarx.chan);
1243 /* Clean up the RX DMA */
1244 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1245 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
cb06ff10
CM		 1246 if (uap->dmarx.poll_rate)
1247 del_timer_sync(&uap->dmarx.timer);
ead76f32
LW		 1248 uap->using_rx_dma = false;
1249 }
1250}
68b65f73 1251
ead76f32
LW		 1252static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1253{
1254 return uap->using_rx_dma;
68b65f73
RK		 1255}
1256
ead76f32
LW		 1257static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1258{
1259 return uap->using_rx_dma && uap->dmarx.running;
1260}
1261
68b65f73
RK		 1262#else
1263/* Blank functions if the DMA engine is not available */
1c9be310 1264static inline void pl011_dma_probe(struct uart_amba_port *uap)
68b65f73
RK		 1265{
1266}
1267
1268static inline void pl011_dma_remove(struct uart_amba_port *uap)
1269{
1270}
1271
1272static inline void pl011_dma_startup(struct uart_amba_port *uap)
1273{
1274}
1275
1276static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1277{
1278}
1279
1280static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1281{
1282 return false;
1283}
1284
1285static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1286{
1287}
1288
1289static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1290{
1291 return false;
1292}
1293
ead76f32
LW		 1294static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1295{
1296}
1297
1298static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1299{
1300}
1301
1302static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1303{
1304 return -EIO;
1305}
1306
1307static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1308{
1309 return false;
1310}
1311
1312static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1313{
1314 return false;
1315}
1316
68b65f73
RK		 1317#define pl011_dma_flush_buffer NULL
1318#endif
1319
b129a8cc 1320static void pl011_stop_tx(struct uart_port *port)
1da177e4 1321{
a5820c24
DT		 1322 struct uart_amba_port *uap =
1323 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1324
1325 uap->im &= ~UART011_TXIM;
9f25bc51 1326 pl011_write(uap->im, uap, REG_IMSC);
68b65f73 1327 pl011_dma_tx_stop(uap);
1da177e4
LT		 1328}
1329
7d05587c 1330static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
734745ca
DM		 1331
1332/* Start TX with programmed I/O only (no DMA) */
1333static void pl011_start_tx_pio(struct uart_amba_port *uap)
1334{
7d05587c
J		 1335 if (pl011_tx_chars(uap, false)) {
1336 uap->im |= UART011_TXIM;
1337 pl011_write(uap->im, uap, REG_IMSC);
1338 }
734745ca
DM		 1339}
1340
b129a8cc 1341static void pl011_start_tx(struct uart_port *port)
1da177e4 1342{
a5820c24
DT		 1343 struct uart_amba_port *uap =
1344 container_of(port, struct uart_amba_port, port);
1da177e4 1345
734745ca
DM		 1346 if (!pl011_dma_tx_start(uap))
1347 pl011_start_tx_pio(uap);
1da177e4
LT		 1348}
1349
1350static void pl011_stop_rx(struct uart_port *port)
1351{
a5820c24
DT		 1352 struct uart_amba_port *uap =
1353 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1354
1355 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1356 UART011_PEIM|UART011_BEIM|UART011_OEIM);
9f25bc51 1357 pl011_write(uap->im, uap, REG_IMSC);
ead76f32
LW		 1358
1359 pl011_dma_rx_stop(uap);
1da177e4
LT		 1360}
1361
1362static void pl011_enable_ms(struct uart_port *port)
1363{
a5820c24
DT		 1364 struct uart_amba_port *uap =
1365 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1366
1367 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
9f25bc51 1368 pl011_write(uap->im, uap, REG_IMSC);
1da177e4
LT		 1369}
1370
7d12e780 1371static void pl011_rx_chars(struct uart_amba_port *uap)
b83286bf
FE		 1372__releases(&uap->port.lock)
1373__acquires(&uap->port.lock)
1da177e4 1374{
29772c4e 1375 pl011_fifo_to_tty(uap);
1da177e4 1376
2389b272 1377 spin_unlock(&uap->port.lock);
2e124b4a 1378 tty_flip_buffer_push(&uap->port.state->port);
ead76f32
LW		 1379 /*
1380 * If we were temporarily out of DMA mode for a while,
1381 * attempt to switch back to DMA mode again.
1382 */
1383 if (pl011_dma_rx_available(uap)) {
1384 if (pl011_dma_rx_trigger_dma(uap)) {
1385 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1386 "fall back to interrupt mode again\n");
1387 uap->im |= UART011_RXIM;
9f25bc51 1388 pl011_write(uap->im, uap, REG_IMSC);
cb06ff10 1389 } else {
89fa28db 1390#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 1391 /* Start Rx DMA poll */
1392 if (uap->dmarx.poll_rate) {
1393 uap->dmarx.last_jiffies = jiffies;
1394 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1395 mod_timer(&uap->dmarx.timer,
1396 jiffies +
1397 msecs_to_jiffies(uap->dmarx.poll_rate));
1398 }
89fa28db 1399#endif
cb06ff10 1400 }
ead76f32 1401 }
2389b272 1402 spin_lock(&uap->port.lock);
1da177e4
LT		 1403}
1404
1e84d223
DM		 1405static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1406 bool from_irq)
734745ca 1407{
1e84d223 1408 if (unlikely(!from_irq) &&
9f25bc51 1409 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1e84d223
DM		 1410 return false; /* unable to transmit character */
1411
9f25bc51 1412 pl011_write(c, uap, REG_DR);
734745ca
DM		 1413 uap->port.icount.tx++;
1414
1e84d223 1415 return true;
734745ca
DM		 1416}
1417
7d05587c
J		 1418/* Returns true if tx interrupts have to be (kept) enabled */
1419static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1da177e4 1420{
ebd2c8f6 1421 struct circ_buf *xmit = &uap->port.state->xmit;
1e84d223 1422 int count = uap->fifosize >> 1;
734745ca 1423
1da177e4 1424 if (uap->port.x_char) {
1e84d223 1425 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
7d05587c 1426 return true;
1da177e4 1427 uap->port.x_char = 0;
734745ca 1428 --count;
1da177e4
LT		 1429 }
1430 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
b129a8cc 1431 pl011_stop_tx(&uap->port);
7d05587c 1432 return false;
1da177e4
LT		 1433 }
1434
68b65f73
RK		 1435 /* If we are using DMA mode, try to send some characters. */
1436 if (pl011_dma_tx_irq(uap))
7d05587c 1437 return true;
68b65f73 1438
1e84d223
DM		 1439 do {
1440 if (likely(from_irq) && count-- == 0)
1da177e4 1441 break;
1e84d223
DM		 1442
1443 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1444 break;
1445
1446 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1447 } while (!uart_circ_empty(xmit));
1da177e4
LT		 1448
1449 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1450 uart_write_wakeup(&uap->port);
1451
7d05587c 1452 if (uart_circ_empty(xmit)) {
b129a8cc 1453 pl011_stop_tx(&uap->port);
7d05587c
J		 1454 return false;
1455 }
1456 return true;
1da177e4
LT		 1457}
1458
1459static void pl011_modem_status(struct uart_amba_port *uap)
1460{
1461 unsigned int status, delta;
1462
9f25bc51 1463 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4
LT		 1464
1465 delta = status ^ uap->old_status;
1466 uap->old_status = status;
1467
1468 if (!delta)
1469 return;
1470
1471 if (delta & UART01x_FR_DCD)
1472 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1473
0e125a5f 1474 if (delta & uap->vendor->fr_dsr)
1da177e4
LT		 1475 uap->port.icount.dsr++;
1476
0e125a5f
SG		 1477 if (delta & uap->vendor->fr_cts)
1478 uart_handle_cts_change(&uap->port,
1479 status & uap->vendor->fr_cts);
1da177e4 1480
bdc04e31 1481 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1da177e4
LT		 1482}
1483
9c4ef4b0
AP		 1484static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1485{
1486 unsigned int dummy_read;
1487
1488 if (!uap->vendor->cts_event_workaround)
1489 return;
1490
1491 /* workaround to make sure that all bits are unlocked.. */
9f25bc51 1492 pl011_write(0x00, uap, REG_ICR);
9c4ef4b0
AP		 1493
1494 /*
1495 * WA: introduce 26ns(1 uart clk) delay before W1C;
1496 * single apb access will incur 2 pclk(133.12Mhz) delay,
1497 * so add 2 dummy reads
1498 */
9f25bc51
RK		 1499 dummy_read = pl011_read(uap, REG_ICR);
1500 dummy_read = pl011_read(uap, REG_ICR);
9c4ef4b0
AP		 1501}
1502
7d12e780 1503static irqreturn_t pl011_int(int irq, void *dev_id)
1da177e4
LT		 1504{
1505 struct uart_amba_port *uap = dev_id;
963cc981 1506 unsigned long flags;
1da177e4 1507 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
075167ed 1508 u16 imsc;
1da177e4
LT		 1509 int handled = 0;
1510
963cc981 1511 spin_lock_irqsave(&uap->port.lock, flags);
9f25bc51
RK		 1512 imsc = pl011_read(uap, REG_IMSC);
1513 status = pl011_read(uap, REG_RIS) & imsc;
1da177e4
LT		 1514 if (status) {
1515 do {
9c4ef4b0 1516 check_apply_cts_event_workaround(uap);
f11c9841 1517
75836339
RK		 1518 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1519 UART011_RXIS),
9f25bc51 1520 uap, REG_ICR);
1da177e4 1521
ead76f32
LW		 1522 if (status & (UART011_RTIS|UART011_RXIS)) {
1523 if (pl011_dma_rx_running(uap))
1524 pl011_dma_rx_irq(uap);
1525 else
1526 pl011_rx_chars(uap);
1527 }
1da177e4
LT		 1528 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1529 UART011_CTSMIS|UART011_RIMIS))
1530 pl011_modem_status(uap);
1e84d223
DM		 1531 if (status & UART011_TXIS)
1532 pl011_tx_chars(uap, true);
1da177e4 1533
4fd0690b 1534 if (pass_counter-- == 0)
1da177e4
LT		 1535 break;
1536
9f25bc51 1537 status = pl011_read(uap, REG_RIS) & imsc;
1da177e4
LT		 1538 } while (status != 0);
1539 handled = 1;
1540 }
1541
963cc981 1542 spin_unlock_irqrestore(&uap->port.lock, flags);
1da177e4
LT		 1543
1544 return IRQ_RETVAL(handled);
1545}
1546
e643f87f 1547static unsigned int pl011_tx_empty(struct uart_port *port)
1da177e4 1548{
a5820c24
DT		 1549 struct uart_amba_port *uap =
1550 container_of(port, struct uart_amba_port, port);
d8a4995b
CC		 1551
1552 /* Allow feature register bits to be inverted to work around errata */
1553 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1554
0e125a5f
SG		 1555 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1556 0 : TIOCSER_TEMT;
1da177e4
LT		 1557}
1558
e643f87f 1559static unsigned int pl011_get_mctrl(struct uart_port *port)
1da177e4 1560{
a5820c24
DT		 1561 struct uart_amba_port *uap =
1562 container_of(port, struct uart_amba_port, port);
1da177e4 1563 unsigned int result = 0;
9f25bc51 1564 unsigned int status = pl011_read(uap, REG_FR);
1da177e4 1565
5159f407 1566#define TIOCMBIT(uartbit, tiocmbit) \
1da177e4
LT		 1567 if (status & uartbit) \
1568 result |= tiocmbit
1569
5159f407 1570 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
0e125a5f
SG		 1571 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1572 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1573 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
5159f407 1574#undef TIOCMBIT
1da177e4
LT		 1575 return result;
1576}
1577
1578static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1579{
a5820c24
DT		 1580 struct uart_amba_port *uap =
1581 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1582 unsigned int cr;
1583
9f25bc51 1584 cr = pl011_read(uap, REG_CR);
1da177e4 1585
5159f407 1586#define TIOCMBIT(tiocmbit, uartbit) \
1da177e4
LT		 1587 if (mctrl & tiocmbit) \
1588 cr |= uartbit; \
1589 else \
1590 cr &= ~uartbit
1591
5159f407
JS		 1592 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1593 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1594 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1595 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1596 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
3b43816f
RV		 1597
1598 if (uap->autorts) {
1599 /* We need to disable auto-RTS if we want to turn RTS off */
1600 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1601 }
5159f407 1602#undef TIOCMBIT
1da177e4 1603
9f25bc51 1604 pl011_write(cr, uap, REG_CR);
1da177e4
LT		 1605}
1606
1607static void pl011_break_ctl(struct uart_port *port, int break_state)
1608{
a5820c24
DT		 1609 struct uart_amba_port *uap =
1610 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1611 unsigned long flags;
1612 unsigned int lcr_h;
1613
1614 spin_lock_irqsave(&uap->port.lock, flags);
e4df9a80 1615 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 1616 if (break_state == -1)
1617 lcr_h |= UART01x_LCRH_BRK;
1618 else
1619 lcr_h &= ~UART01x_LCRH_BRK;
e4df9a80 1620 pl011_write(lcr_h, uap, REG_LCRH_TX);
1da177e4
LT		 1621 spin_unlock_irqrestore(&uap->port.lock, flags);
1622}
1623
84b5ae15 1624#ifdef CONFIG_CONSOLE_POLL
5c8124a0
AV		 1625
1626static void pl011_quiesce_irqs(struct uart_port *port)
1627{
a5820c24
DT		 1628 struct uart_amba_port *uap =
1629 container_of(port, struct uart_amba_port, port);
5c8124a0 1630
9f25bc51 1631 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
5c8124a0
AV		 1632 /*
1633 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1634 * we simply mask it. start_tx() will unmask it.
1635 *
1636 * Note we can race with start_tx(), and if the race happens, the
1637 * polling user might get another interrupt just after we clear it.
1638 * But it should be OK and can happen even w/o the race, e.g.
1639 * controller immediately got some new data and raised the IRQ.
1640 *
1641 * And whoever uses polling routines assumes that it manages the device
1642 * (including tx queue), so we're also fine with start_tx()'s caller
1643 * side.
1644 */
9f25bc51
RK		 1645 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1646 REG_IMSC);
5c8124a0
AV		 1647}
1648
e643f87f 1649static int pl011_get_poll_char(struct uart_port *port)
84b5ae15 1650{
a5820c24
DT		 1651 struct uart_amba_port *uap =
1652 container_of(port, struct uart_amba_port, port);
84b5ae15
JW		 1653 unsigned int status;
1654
5c8124a0
AV		 1655 /*
1656 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1657 * debugger.
1658 */
1659 pl011_quiesce_irqs(port);
1660
9f25bc51 1661 status = pl011_read(uap, REG_FR);
f5316b4a
JW		 1662 if (status & UART01x_FR_RXFE)
1663 return NO_POLL_CHAR;
84b5ae15 1664
9f25bc51 1665 return pl011_read(uap, REG_DR);
84b5ae15
JW		 1666}
1667
e643f87f 1668static void pl011_put_poll_char(struct uart_port *port,
84b5ae15
JW		 1669 unsigned char ch)
1670{
a5820c24
DT		 1671 struct uart_amba_port *uap =
1672 container_of(port, struct uart_amba_port, port);
84b5ae15 1673
9f25bc51 1674 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 1675 cpu_relax();
84b5ae15 1676
9f25bc51 1677 pl011_write(ch, uap, REG_DR);
84b5ae15
JW		 1678}
1679
1680#endif /* CONFIG_CONSOLE_POLL */
1681
b3564c2c 1682static int pl011_hwinit(struct uart_port *port)
1da177e4 1683{
a5820c24
DT		 1684 struct uart_amba_port *uap =
1685 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1686 int retval;
1687
78d80c5a 1688 /* Optionaly enable pins to be muxed in and configured */
2b996fc5 1689 pinctrl_pm_select_default_state(port->dev);
78d80c5a 1690
1da177e4
LT		 1691 /*
1692 * Try to enable the clock producer.
1693 */
1c4c4394 1694 retval = clk_prepare_enable(uap->clk);
1da177e4 1695 if (retval)
7f6d942a 1696 return retval;
1da177e4
LT		 1697
1698 uap->port.uartclk = clk_get_rate(uap->clk);
1699
9b96fbac 1700 /* Clear pending error and receive interrupts */
75836339
RK		 1701 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1702 UART011_FEIS | UART011_RTIS | UART011_RXIS,
9f25bc51 1703 uap, REG_ICR);
9b96fbac 1704
b3564c2c
AV		 1705 /*
1706 * Save interrupts enable mask, and enable RX interrupts in case if
1707 * the interrupt is used for NMI entry.
1708 */
9f25bc51
RK		 1709 uap->im = pl011_read(uap, REG_IMSC);
1710 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
b3564c2c 1711
574de559 1712 if (dev_get_platdata(uap->port.dev)) {
b3564c2c
AV		 1713 struct amba_pl011_data *plat;
1714
574de559 1715 plat = dev_get_platdata(uap->port.dev);
b3564c2c
AV		 1716 if (plat->init)
1717 plat->init();
1718 }
1719 return 0;
b3564c2c
AV		 1720}
1721
7fe9a5a9
RK		 1722static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1723{
e4df9a80
RK		 1724 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1725 pl011_reg_to_offset(uap, REG_LCRH_TX);
7fe9a5a9
RK		 1726}
1727
b60f2f66
JM		 1728static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1729{
e4df9a80 1730 pl011_write(lcr_h, uap, REG_LCRH_RX);
7fe9a5a9 1731 if (pl011_split_lcrh(uap)) {
b60f2f66
JM		 1732 int i;
1733 /*
1734 * Wait 10 PCLKs before writing LCRH_TX register,
1735 * to get this delay write read only register 10 times
1736 */
1737 for (i = 0; i < 10; ++i)
9f25bc51 1738 pl011_write(0xff, uap, REG_MIS);
e4df9a80 1739 pl011_write(lcr_h, uap, REG_LCRH_TX);
b60f2f66
JM		 1740 }
1741}
1742
867b8e8e
AP		 1743static int pl011_allocate_irq(struct uart_amba_port *uap)
1744{
9f25bc51 1745 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e
AP		 1746
1747 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1748}
1749
1750/*
1751 * Enable interrupts, only timeouts when using DMA
1752 * if initial RX DMA job failed, start in interrupt mode
1753 * as well.
1754 */
1755static void pl011_enable_interrupts(struct uart_amba_port *uap)
1756{
1757 spin_lock_irq(&uap->port.lock);
1758
1759 /* Clear out any spuriously appearing RX interrupts */
9f25bc51 1760 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
867b8e8e
AP		 1761 uap->im = UART011_RTIM;
1762 if (!pl011_dma_rx_running(uap))
1763 uap->im |= UART011_RXIM;
9f25bc51 1764 pl011_write(uap->im, uap, REG_IMSC);
867b8e8e
AP		 1765 spin_unlock_irq(&uap->port.lock);
1766}
1767
b3564c2c
AV		 1768static int pl011_startup(struct uart_port *port)
1769{
a5820c24
DT		 1770 struct uart_amba_port *uap =
1771 container_of(port, struct uart_amba_port, port);
734745ca 1772 unsigned int cr;
b3564c2c
AV		 1773 int retval;
1774
1775 retval = pl011_hwinit(port);
1776 if (retval)
1777 goto clk_dis;
1778
867b8e8e 1779 retval = pl011_allocate_irq(uap);
1da177e4
LT		 1780 if (retval)
1781 goto clk_dis;
1782
9f25bc51 1783 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1da177e4 1784
734745ca 1785 spin_lock_irq(&uap->port.lock);
570d2910 1786
d8d8ffa4
SKS		 1787 /* restore RTS and DTR */
1788 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1789 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
9f25bc51 1790 pl011_write(cr, uap, REG_CR);
1da177e4 1791
fe433907
JM		 1792 spin_unlock_irq(&uap->port.lock);
1793
1da177e4
LT		 1794 /*
1795 * initialise the old status of the modem signals
1796 */
9f25bc51 1797 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1da177e4 1798
68b65f73
RK		 1799 /* Startup DMA */
1800 pl011_dma_startup(uap);
1801
867b8e8e 1802 pl011_enable_interrupts(uap);
1da177e4
LT		 1803
1804 return 0;
1805
1806 clk_dis:
1c4c4394 1807 clk_disable_unprepare(uap->clk);
1da177e4
LT		 1808 return retval;
1809}
1810
0dd1e247
AP		 1811static int sbsa_uart_startup(struct uart_port *port)
1812{
1813 struct uart_amba_port *uap =
1814 container_of(port, struct uart_amba_port, port);
1815 int retval;
1816
1817 retval = pl011_hwinit(port);
1818 if (retval)
1819 return retval;
1820
1821 retval = pl011_allocate_irq(uap);
1822 if (retval)
1823 return retval;
1824
1825 /* The SBSA UART does not support any modem status lines. */
1826 uap->old_status = 0;
1827
1828 pl011_enable_interrupts(uap);
1829
1830 return 0;
1831}
1832
ec489aa8
LW		 1833static void pl011_shutdown_channel(struct uart_amba_port *uap,
1834 unsigned int lcrh)
1835{
f11c9841 1836 unsigned long val;
ec489aa8 1837
b2a4e24c 1838 val = pl011_read(uap, lcrh);
f11c9841 1839 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
b2a4e24c 1840 pl011_write(val, uap, lcrh);
ec489aa8
LW		 1841}
1842
95166a3f
AP		 1843/*
1844 * disable the port. It should not disable RTS and DTR.
1845 * Also RTS and DTR state should be preserved to restore
1846 * it during startup().
1847 */
1848static void pl011_disable_uart(struct uart_amba_port *uap)
1da177e4 1849{
d8d8ffa4 1850 unsigned int cr;
1da177e4 1851
3b43816f 1852 uap->autorts = false;
fe433907 1853 spin_lock_irq(&uap->port.lock);
9f25bc51 1854 cr = pl011_read(uap, REG_CR);
d8d8ffa4
SKS		 1855 uap->old_cr = cr;
1856 cr &= UART011_CR_RTS | UART011_CR_DTR;
1857 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 1858 pl011_write(cr, uap, REG_CR);
fe433907 1859 spin_unlock_irq(&uap->port.lock);
1da177e4
LT		 1860
1861 /*
1862 * disable break condition and fifos
1863 */
e4df9a80 1864 pl011_shutdown_channel(uap, REG_LCRH_RX);
7fe9a5a9 1865 if (pl011_split_lcrh(uap))
e4df9a80 1866 pl011_shutdown_channel(uap, REG_LCRH_TX);
95166a3f
AP		 1867}
1868
1869static void pl011_disable_interrupts(struct uart_amba_port *uap)
1870{
1871 spin_lock_irq(&uap->port.lock);
1872
1873 /* mask all interrupts and clear all pending ones */
1874 uap->im = 0;
9f25bc51
RK		 1875 pl011_write(uap->im, uap, REG_IMSC);
1876 pl011_write(0xffff, uap, REG_ICR);
95166a3f
AP		 1877
1878 spin_unlock_irq(&uap->port.lock);
1879}
1880
1881static void pl011_shutdown(struct uart_port *port)
1882{
1883 struct uart_amba_port *uap =
1884 container_of(port, struct uart_amba_port, port);
1885
1886 pl011_disable_interrupts(uap);
1887
1888 pl011_dma_shutdown(uap);
1889
1890 free_irq(uap->port.irq, uap);
1891
1892 pl011_disable_uart(uap);
1da177e4
LT		 1893
1894 /*
1895 * Shut down the clock producer
1896 */
1c4c4394 1897 clk_disable_unprepare(uap->clk);
78d80c5a 1898 /* Optionally let pins go into sleep states */
2b996fc5 1899 pinctrl_pm_select_sleep_state(port->dev);
c16d51a3 1900
574de559 1901 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 1902 struct amba_pl011_data *plat;
1903
574de559 1904 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 1905 if (plat->exit)
1906 plat->exit();
1907 }
1908
36f339d1
PH		 1909 if (uap->port.ops->flush_buffer)
1910 uap->port.ops->flush_buffer(port);
1da177e4
LT		 1911}
1912
0dd1e247
AP		 1913static void sbsa_uart_shutdown(struct uart_port *port)
1914{
1915 struct uart_amba_port *uap =
1916 container_of(port, struct uart_amba_port, port);
1917
1918 pl011_disable_interrupts(uap);
1919
1920 free_irq(uap->port.irq, uap);
1921
1922 if (uap->port.ops->flush_buffer)
1923 uap->port.ops->flush_buffer(port);
1924}
1925
ef5a9358
AP		 1926static void
1927pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1928{
1929 port->read_status_mask = UART011_DR_OE | 255;
1930 if (termios->c_iflag & INPCK)
1931 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1932 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1933 port->read_status_mask |= UART011_DR_BE;
1934
1935 /*
1936 * Characters to ignore
1937 */
1938 port->ignore_status_mask = 0;
1939 if (termios->c_iflag & IGNPAR)
1940 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1941 if (termios->c_iflag & IGNBRK) {
1942 port->ignore_status_mask |= UART011_DR_BE;
1943 /*
1944 * If we're ignoring parity and break indicators,
1945 * ignore overruns too (for real raw support).
1946 */
1947 if (termios->c_iflag & IGNPAR)
1948 port->ignore_status_mask |= UART011_DR_OE;
1949 }
1950
1951 /*
1952 * Ignore all characters if CREAD is not set.
1953 */
1954 if ((termios->c_cflag & CREAD) == 0)
1955 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1956}
1957
1da177e4 1958static void
606d099c
AC		 1959pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1960 struct ktermios *old)
1da177e4 1961{
a5820c24
DT		 1962 struct uart_amba_port *uap =
1963 container_of(port, struct uart_amba_port, port);
1da177e4
LT		 1964 unsigned int lcr_h, old_cr;
1965 unsigned long flags;
c19f12b5
RK		 1966 unsigned int baud, quot, clkdiv;
1967
1968 if (uap->vendor->oversampling)
1969 clkdiv = 8;
1970 else
1971 clkdiv = 16;
1da177e4
LT		 1972
1973 /*
1974 * Ask the core to calculate the divisor for us.
1975 */
ac3e3fb4 1976 baud = uart_get_baud_rate(port, termios, old, 0,
c19f12b5 1977 port->uartclk / clkdiv);
89fa28db 1978#ifdef CONFIG_DMA_ENGINE
cb06ff10
CM		 1979 /*
1980 * Adjust RX DMA polling rate with baud rate if not specified.
1981 */
1982 if (uap->dmarx.auto_poll_rate)
1983 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
89fa28db 1984#endif
ac3e3fb4
LW		 1985
1986 if (baud > port->uartclk/16)
1987 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1988 else
1989 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1da177e4
LT		 1990
1991 switch (termios->c_cflag & CSIZE) {
1992 case CS5:
1993 lcr_h = UART01x_LCRH_WLEN_5;
1994 break;
1995 case CS6:
1996 lcr_h = UART01x_LCRH_WLEN_6;
1997 break;
1998 case CS7:
1999 lcr_h = UART01x_LCRH_WLEN_7;
2000 break;
2001 default: // CS8
2002 lcr_h = UART01x_LCRH_WLEN_8;
2003 break;
2004 }
2005 if (termios->c_cflag & CSTOPB)
2006 lcr_h |= UART01x_LCRH_STP2;
2007 if (termios->c_cflag & PARENB) {
2008 lcr_h |= UART01x_LCRH_PEN;
2009 if (!(termios->c_cflag & PARODD))
2010 lcr_h |= UART01x_LCRH_EPS;
bb70002c
ES		 2011 if (termios->c_cflag & CMSPAR)
2012 lcr_h |= UART011_LCRH_SPS;
1da177e4 2013 }
ffca2b11 2014 if (uap->fifosize > 1)
1da177e4
LT		 2015 lcr_h |= UART01x_LCRH_FEN;
2016
2017 spin_lock_irqsave(&port->lock, flags);
2018
2019 /*
2020 * Update the per-port timeout.
2021 */
2022 uart_update_timeout(port, termios->c_cflag, baud);
2023
ef5a9358 2024 pl011_setup_status_masks(port, termios);
1da177e4
LT		 2025
2026 if (UART_ENABLE_MS(port, termios->c_cflag))
2027 pl011_enable_ms(port);
2028
2029 /* first, disable everything */
9f25bc51
RK		 2030 old_cr = pl011_read(uap, REG_CR);
2031 pl011_write(0, uap, REG_CR);
1da177e4 2032
3b43816f
RV		 2033 if (termios->c_cflag & CRTSCTS) {
2034 if (old_cr & UART011_CR_RTS)
2035 old_cr |= UART011_CR_RTSEN;
2036
2037 old_cr |= UART011_CR_CTSEN;
2038 uap->autorts = true;
2039 } else {
2040 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2041 uap->autorts = false;
2042 }
2043
c19f12b5
RK		 2044 if (uap->vendor->oversampling) {
2045 if (baud > port->uartclk / 16)
ac3e3fb4
LW		 2046 old_cr |= ST_UART011_CR_OVSFACT;
2047 else
2048 old_cr &= ~ST_UART011_CR_OVSFACT;
2049 }
2050
c5dd553b
LW		 2051 /*
2052 * Workaround for the ST Micro oversampling variants to
2053 * increase the bitrate slightly, by lowering the divisor,
2054 * to avoid delayed sampling of start bit at high speeds,
2055 * else we see data corruption.
2056 */
2057 if (uap->vendor->oversampling) {
2058 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2059 quot -= 1;
2060 else if ((baud > 3250000) && (quot > 2))
2061 quot -= 2;
2062 }
1da177e4 2063 /* Set baud rate */
9f25bc51
RK		 2064 pl011_write(quot & 0x3f, uap, REG_FBRD);
2065 pl011_write(quot >> 6, uap, REG_IBRD);
1da177e4
LT		 2066
2067 /*
2068 * ----------v----------v----------v----------v-----
e4df9a80 2069 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
9f25bc51 2070 * REG_FBRD & REG_IBRD.
1da177e4
LT		 2071 * ----------^----------^----------^----------^-----
2072 */
b60f2f66 2073 pl011_write_lcr_h(uap, lcr_h);
9f25bc51 2074 pl011_write(old_cr, uap, REG_CR);
1da177e4
LT		 2075
2076 spin_unlock_irqrestore(&port->lock, flags);
2077}
2078
0dd1e247
AP		 2079static void
2080sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2081 struct ktermios *old)
2082{
2083 struct uart_amba_port *uap =
2084 container_of(port, struct uart_amba_port, port);
2085 unsigned long flags;
2086
2087 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2088
2089 /* The SBSA UART only supports 8n1 without hardware flow control. */
2090 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2091 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2092 termios->c_cflag |= CS8 | CLOCAL;
2093
2094 spin_lock_irqsave(&port->lock, flags);
2095 uart_update_timeout(port, CS8, uap->fixed_baud);
2096 pl011_setup_status_masks(port, termios);
2097 spin_unlock_irqrestore(&port->lock, flags);
2098}
2099
1da177e4
LT		 2100static const char *pl011_type(struct uart_port *port)
2101{
a5820c24
DT		 2102 struct uart_amba_port *uap =
2103 container_of(port, struct uart_amba_port, port);
e8a7ba86 2104 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1da177e4
LT		 2105}
2106
2107/*
2108 * Release the memory region(s) being used by 'port'
2109 */
e643f87f 2110static void pl011_release_port(struct uart_port *port)
1da177e4
LT		 2111{
2112 release_mem_region(port->mapbase, SZ_4K);
2113}
2114
2115/*
2116 * Request the memory region(s) being used by 'port'
2117 */
e643f87f 2118static int pl011_request_port(struct uart_port *port)
1da177e4
LT		 2119{
2120 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2121 != NULL ? 0 : -EBUSY;
2122}
2123
2124/*
2125 * Configure/autoconfigure the port.
2126 */
e643f87f 2127static void pl011_config_port(struct uart_port *port, int flags)
1da177e4
LT		 2128{
2129 if (flags & UART_CONFIG_TYPE) {
2130 port->type = PORT_AMBA;
e643f87f 2131 pl011_request_port(port);
1da177e4
LT		 2132 }
2133}
2134
2135/*
2136 * verify the new serial_struct (for TIOCSSERIAL).
2137 */
e643f87f 2138static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1da177e4
LT		 2139{
2140 int ret = 0;
2141 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2142 ret = -EINVAL;
a62c4133 2143 if (ser->irq < 0 || ser->irq >= nr_irqs)
1da177e4
LT		 2144 ret = -EINVAL;
2145 if (ser->baud_base < 9600)
2146 ret = -EINVAL;
2147 return ret;
2148}
2149
2331e068 2150static const struct uart_ops amba_pl011_pops = {
e643f87f 2151 .tx_empty = pl011_tx_empty,
1da177e4 2152 .set_mctrl = pl011_set_mctrl,
e643f87f 2153 .get_mctrl = pl011_get_mctrl,
1da177e4
LT		 2154 .stop_tx = pl011_stop_tx,
2155 .start_tx = pl011_start_tx,
2156 .stop_rx = pl011_stop_rx,
2157 .enable_ms = pl011_enable_ms,
2158 .break_ctl = pl011_break_ctl,
2159 .startup = pl011_startup,
2160 .shutdown = pl011_shutdown,
68b65f73 2161 .flush_buffer = pl011_dma_flush_buffer,
1da177e4
LT		 2162 .set_termios = pl011_set_termios,
2163 .type = pl011_type,
e643f87f
LW		 2164 .release_port = pl011_release_port,
2165 .request_port = pl011_request_port,
2166 .config_port = pl011_config_port,
2167 .verify_port = pl011_verify_port,
84b5ae15 2168#ifdef CONFIG_CONSOLE_POLL
b3564c2c 2169 .poll_init = pl011_hwinit,
e643f87f
LW		 2170 .poll_get_char = pl011_get_poll_char,
2171 .poll_put_char = pl011_put_poll_char,
84b5ae15 2172#endif
1da177e4
LT		 2173};
2174
0dd1e247
AP		 2175static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2176{
2177}
2178
2179static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2180{
2181 return 0;
2182}
2183
2184static const struct uart_ops sbsa_uart_pops = {
2185 .tx_empty = pl011_tx_empty,
2186 .set_mctrl = sbsa_uart_set_mctrl,
2187 .get_mctrl = sbsa_uart_get_mctrl,
2188 .stop_tx = pl011_stop_tx,
2189 .start_tx = pl011_start_tx,
2190 .stop_rx = pl011_stop_rx,
2191 .startup = sbsa_uart_startup,
2192 .shutdown = sbsa_uart_shutdown,
2193 .set_termios = sbsa_uart_set_termios,
2194 .type = pl011_type,
2195 .release_port = pl011_release_port,
2196 .request_port = pl011_request_port,
2197 .config_port = pl011_config_port,
2198 .verify_port = pl011_verify_port,
2199#ifdef CONFIG_CONSOLE_POLL
2200 .poll_init = pl011_hwinit,
2201 .poll_get_char = pl011_get_poll_char,
2202 .poll_put_char = pl011_put_poll_char,
2203#endif
2204};
2205
1da177e4
LT		 2206static struct uart_amba_port *amba_ports[UART_NR];
2207
2208#ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2209
d358788f 2210static void pl011_console_putchar(struct uart_port *port, int ch)
1da177e4 2211{
a5820c24
DT		 2212 struct uart_amba_port *uap =
2213 container_of(port, struct uart_amba_port, port);
1da177e4 2214
9f25bc51 2215 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2f2fd089 2216 cpu_relax();
9f25bc51 2217 pl011_write(ch, uap, REG_DR);
1da177e4
LT		 2218}
2219
2220static void
2221pl011_console_write(struct console *co, const char *s, unsigned int count)
2222{
2223 struct uart_amba_port *uap = amba_ports[co->index];
2f2fd089 2224 unsigned int old_cr = 0, new_cr;
ef605fdb
RV		 2225 unsigned long flags;
2226 int locked = 1;
1da177e4
LT		 2227
2228 clk_enable(uap->clk);
2229
ef605fdb
RV		 2230 local_irq_save(flags);
2231 if (uap->port.sysrq)
2232 locked = 0;
2233 else if (oops_in_progress)
2234 locked = spin_trylock(&uap->port.lock);
2235 else
2236 spin_lock(&uap->port.lock);
2237
1da177e4
LT		 2238 /*
2239 * First save the CR then disable the interrupts
2240 */
71eec483 2241 if (!uap->vendor->always_enabled) {
9f25bc51 2242 old_cr = pl011_read(uap, REG_CR);
71eec483
AP		 2243 new_cr = old_cr & ~UART011_CR_CTSEN;
2244 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
9f25bc51 2245 pl011_write(new_cr, uap, REG_CR);
71eec483 2246 }
1da177e4 2247
d358788f 2248 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1da177e4
LT		 2249
2250 /*
d8a4995b
CC		 2251 * Finally, wait for transmitter to become empty and restore the
2252 * TCR. Allow feature register bits to be inverted to work around
2253 * errata.
1da177e4 2254 */
d8a4995b
CC		 2255 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2256 & uap->vendor->fr_busy)
2f2fd089 2257 cpu_relax();
71eec483 2258 if (!uap->vendor->always_enabled)
9f25bc51 2259 pl011_write(old_cr, uap, REG_CR);
1da177e4 2260
ef605fdb
RV		 2261 if (locked)
2262 spin_unlock(&uap->port.lock);
2263 local_irq_restore(flags);
2264
1da177e4
LT		 2265 clk_disable(uap->clk);
2266}
2267
2268static void __init
2269pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2270 int *parity, int *bits)
2271{
9f25bc51 2272 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
1da177e4
LT		 2273 unsigned int lcr_h, ibrd, fbrd;
2274
e4df9a80 2275 lcr_h = pl011_read(uap, REG_LCRH_TX);
1da177e4
LT		 2276
2277 *parity = 'n';
2278 if (lcr_h & UART01x_LCRH_PEN) {
2279 if (lcr_h & UART01x_LCRH_EPS)
2280 *parity = 'e';
2281 else
2282 *parity = 'o';
2283 }
2284
2285 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2286 *bits = 7;
2287 else
2288 *bits = 8;
2289
9f25bc51
RK		 2290 ibrd = pl011_read(uap, REG_IBRD);
2291 fbrd = pl011_read(uap, REG_FBRD);
1da177e4
LT		 2292
2293 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
ac3e3fb4 2294
c19f12b5 2295 if (uap->vendor->oversampling) {
9f25bc51 2296 if (pl011_read(uap, REG_CR)
ac3e3fb4
LW		 2297 & ST_UART011_CR_OVSFACT)
2298 *baud *= 2;
2299 }
1da177e4
LT		 2300 }
2301}
2302
2303static int __init pl011_console_setup(struct console *co, char *options)
2304{
2305 struct uart_amba_port *uap;
2306 int baud = 38400;
2307 int bits = 8;
2308 int parity = 'n';
2309 int flow = 'n';
4b4851c6 2310 int ret;
1da177e4
LT		 2311
2312 /*
2313 * Check whether an invalid uart number has been specified, and
2314 * if so, search for the first available port that does have
2315 * console support.
2316 */
2317 if (co->index >= UART_NR)
2318 co->index = 0;
2319 uap = amba_ports[co->index];
d28122a5
RK		 2320 if (!uap)
2321 return -ENODEV;
1da177e4 2322
78d80c5a 2323 /* Allow pins to be muxed in and configured */
2b996fc5 2324 pinctrl_pm_select_default_state(uap->port.dev);
78d80c5a 2325
4b4851c6
RK		 2326 ret = clk_prepare(uap->clk);
2327 if (ret)
2328 return ret;
2329
574de559 2330 if (dev_get_platdata(uap->port.dev)) {
c16d51a3
SKS		 2331 struct amba_pl011_data *plat;
2332
574de559 2333 plat = dev_get_platdata(uap->port.dev);
c16d51a3
SKS		 2334 if (plat->init)
2335 plat->init();
2336 }
2337
1da177e4
LT		 2338 uap->port.uartclk = clk_get_rate(uap->clk);
2339
cefc2d1d
AP		 2340 if (uap->vendor->fixed_options) {
2341 baud = uap->fixed_baud;
2342 } else {
2343 if (options)
2344 uart_parse_options(options,
2345 &baud, &parity, &bits, &flow);
2346 else
2347 pl011_console_get_options(uap, &baud, &parity, &bits);
2348 }
1da177e4
LT		 2349
2350 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2351}
2352
10879ae5
AM		 2353/**
2354 * pl011_console_match - non-standard console matching
2355 * @co: registering console
2356 * @name: name from console command line
2357 * @idx: index from console command line
2358 * @options: ptr to option string from console command line
2359 *
2360 * Only attempts to match console command lines of the form:
2361 * console=pl011,mmio|mmio32,<addr>[,<options>]
2362 * console=pl011,0x<addr>[,<options>]
2363 * This form is used to register an initial earlycon boot console and
2364 * replace it with the amba_console at pl011 driver init.
2365 *
2366 * Performs console setup for a match (as required by interface)
2367 * If no <options> are specified, then assume the h/w is already setup.
2368 *
2369 * Returns 0 if console matches; otherwise non-zero to use default matching
2370 */
2371static int __init pl011_console_match(struct console *co, char *name, int idx,
2372 char *options)
2373{
2374 unsigned char iotype;
2375 resource_size_t addr;
2376 int i;
2377
d8a4995b
CC		 2378 if (strcmp(name, "qdf2400_e44") == 0) {
2379 pr_info_once("UART: Working around QDF2400 SoC erratum 44");
2380 qdf2400_e44_present = true;
b767ad72 2381 } else if (strcmp(name, "pl011") != 0) {
10879ae5 2382 return -ENODEV;
d8a4995b 2383 }
10879ae5
AM		 2384
2385 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2386 return -ENODEV;
2387
2388 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2389 return -ENODEV;
2390
2391 /* try to match the port specified on the command line */
2392 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2393 struct uart_port *port;
2394
2395 if (!amba_ports[i])
2396 continue;
2397
2398 port = &amba_ports[i]->port;
2399
2400 if (port->mapbase != addr)
2401 continue;
2402
2403 co->index = i;
2404 port->cons = co;
2405 return pl011_console_setup(co, options);
2406 }
2407
2408 return -ENODEV;
2409}
2410
2d93486c 2411static struct uart_driver amba_reg;
1da177e4
LT		 2412static struct console amba_console = {
2413 .name = "ttyAMA",
2414 .write = pl011_console_write,
2415 .device = uart_console_device,
2416 .setup = pl011_console_setup,
10879ae5 2417 .match = pl011_console_match,
7951ffc9 2418 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2419 .index = -1,
2420 .data = &amba_reg,
2421};
2422
2423#define AMBA_CONSOLE (&amba_console)
0d3c673e 2424
d8a4995b
CC		 2425static void qdf2400_e44_putc(struct uart_port *port, int c)
2426{
2427 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2428 cpu_relax();
2429 writel(c, port->membase + UART01x_DR);
2430 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2431 cpu_relax();
2432}
2433
2434static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2435{
2436 struct earlycon_device *dev = con->data;
2437
2438 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2439}
2440
0d3c673e
RH		 2441static void pl011_putc(struct uart_port *port, int c)
2442{
cdf091ca 2443 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2f2fd089 2444 cpu_relax();
3b78fae7
TT		 2445 if (port->iotype == UPIO_MEM32)
2446 writel(c, port->membase + UART01x_DR);
2447 else
2448 writeb(c, port->membase + UART01x_DR);
e06690bf 2449 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2f2fd089 2450 cpu_relax();
0d3c673e
RH		 2451}
2452
2453static void pl011_early_write(struct console *con, const char *s, unsigned n)
2454{
2455 struct earlycon_device *dev = con->data;
2456
2457 uart_console_write(&dev->port, s, n, pl011_putc);
2458}
2459
e53e597f
TT		 2460/*
2461 * On non-ACPI systems, earlycon is enabled by specifying
2462 * "earlycon=pl011,<address>" on the kernel command line.
2463 *
2464 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2465 * by specifying only "earlycon" on the command line. Because it requires
2466 * SPCR, the console starts after ACPI is parsed, which is later than a
2467 * traditional early console.
2468 *
2469 * To get the traditional early console that starts before ACPI is parsed,
2470 * specify the full "earlycon=pl011,<address>" option.
2471 */
0d3c673e
RH		 2472static int __init pl011_early_console_setup(struct earlycon_device *device,
2473 const char *opt)
2474{
2475 if (!device->port.membase)
2476 return -ENODEV;
2477
e53e597f
TT		 2478 /* On QDF2400 SOCs affected by Erratum 44, the "qdf2400_e44" must
2479 * also be specified, e.g. "earlycon=pl011,<address>,qdf2400_e44".
2480 */
2481 if (!strcmp(device->options, "qdf2400_e44"))
2482 device->con->write = qdf2400_e44_early_write;
2483 else
2484 device->con->write = pl011_early_write;
2485
0d3c673e
RH		 2486 return 0;
2487}
45e0f0f5 2488OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
fcb32159 2489OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
e53e597f 2490EARLYCON_DECLARE(qdf2400_e44, pl011_early_console_setup);
0d3c673e 2491
1da177e4
LT		 2492#else
2493#define AMBA_CONSOLE NULL
2494#endif
2495
2496static struct uart_driver amba_reg = {
2497 .owner = THIS_MODULE,
2498 .driver_name = "ttyAMA",
2499 .dev_name = "ttyAMA",
2500 .major = SERIAL_AMBA_MAJOR,
2501 .minor = SERIAL_AMBA_MINOR,
2502 .nr = UART_NR,
2503 .cons = AMBA_CONSOLE,
2504};
2505
32614aad
ML		 2506static int pl011_probe_dt_alias(int index, struct device *dev)
2507{
2508 struct device_node *np;
2509 static bool seen_dev_with_alias = false;
2510 static bool seen_dev_without_alias = false;
2511 int ret = index;
2512
2513 if (!IS_ENABLED(CONFIG_OF))
2514 return ret;
2515
2516 np = dev->of_node;
2517 if (!np)
2518 return ret;
2519
2520 ret = of_alias_get_id(np, "serial");
287980e4 2521 if (ret < 0) {
32614aad
ML		 2522 seen_dev_without_alias = true;
2523 ret = index;
2524 } else {
2525 seen_dev_with_alias = true;
2526 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2527 dev_warn(dev, "requested serial port %d not available.\n", ret);
2528 ret = index;
2529 }
2530 }
2531
2532 if (seen_dev_with_alias && seen_dev_without_alias)
2533 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2534
2535 return ret;
2536}
2537
49bb3c86
AP		 2538/* unregisters the driver also if no more ports are left */
2539static void pl011_unregister_port(struct uart_amba_port *uap)
2540{
2541 int i;
2542 bool busy = false;
2543
2544 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2545 if (amba_ports[i] == uap)
2546 amba_ports[i] = NULL;
2547 else if (amba_ports[i])
2548 busy = true;
2549 }
2550 pl011_dma_remove(uap);
2551 if (!busy)
2552 uart_unregister_driver(&amba_reg);
2553}
2554
3873e2d7 2555static int pl011_find_free_port(void)
1da177e4 2556{
3873e2d7 2557 int i;
1da177e4
LT		 2558
2559 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2560 if (amba_ports[i] == NULL)
3873e2d7 2561 return i;
1da177e4 2562
3873e2d7
AP		 2563 return -EBUSY;
2564}
1da177e4 2565
3873e2d7
AP		 2566static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2567 struct resource *mmiobase, int index)
2568{
2569 void __iomem *base;
32614aad 2570
3873e2d7 2571 base = devm_ioremap_resource(dev, mmiobase);
97a60eac
KK		 2572 if (IS_ERR(base))
2573 return PTR_ERR(base);
1da177e4 2574
3873e2d7 2575 index = pl011_probe_dt_alias(index, dev);
1da177e4 2576
d8d8ffa4 2577 uap->old_cr = 0;
3873e2d7
AP		 2578 uap->port.dev = dev;
2579 uap->port.mapbase = mmiobase->start;
1da177e4 2580 uap->port.membase = base;
ffca2b11 2581 uap->port.fifosize = uap->fifosize;
1da177e4 2582 uap->port.flags = UPF_BOOT_AUTOCONF;
3873e2d7 2583 uap->port.line = index;
1da177e4 2584
3873e2d7 2585 amba_ports[index] = uap;
c3d8b76f 2586
3873e2d7
AP		 2587 return 0;
2588}
e8a7ba86 2589
3873e2d7
AP		 2590static int pl011_register_port(struct uart_amba_port *uap)
2591{
2592 int ret;
1da177e4 2593
3873e2d7 2594 /* Ensure interrupts from this UART are masked and cleared */
9f25bc51
RK		 2595 pl011_write(0, uap, REG_IMSC);
2596 pl011_write(0xffff, uap, REG_ICR);
ef2889f7
TB		 2597
2598 if (!amba_reg.state) {
2599 ret = uart_register_driver(&amba_reg);
2600 if (ret < 0) {
3873e2d7 2601 dev_err(uap->port.dev,
1c9be310 2602 "Failed to register AMBA-PL011 driver\n");
ef2889f7
TB		 2603 return ret;
2604 }
2605 }
2606
1da177e4 2607 ret = uart_add_one_port(&amba_reg, &uap->port);
49bb3c86
AP		 2608 if (ret)
2609 pl011_unregister_port(uap);
7f6d942a 2610
1da177e4
LT		 2611 return ret;
2612}
2613
3873e2d7
AP		 2614static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2615{
2616 struct uart_amba_port *uap;
2617 struct vendor_data *vendor = id->data;
2618 int portnr, ret;
2619
2620 portnr = pl011_find_free_port();
2621 if (portnr < 0)
2622 return portnr;
2623
2624 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2625 GFP_KERNEL);
2626 if (!uap)
2627 return -ENOMEM;
2628
2629 uap->clk = devm_clk_get(&dev->dev, NULL);
2630 if (IS_ERR(uap->clk))
2631 return PTR_ERR(uap->clk);
2632
439403bd 2633 uap->reg_offset = vendor->reg_offset;
3873e2d7 2634 uap->vendor = vendor;
3873e2d7 2635 uap->fifosize = vendor->get_fifosize(dev);
3b78fae7 2636 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
3873e2d7
AP		 2637 uap->port.irq = dev->irq[0];
2638 uap->port.ops = &amba_pl011_pops;
2639
2640 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2641
2642 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2643 if (ret)
2644 return ret;
2645
2646 amba_set_drvdata(dev, uap);
2647
2648 return pl011_register_port(uap);
2649}
2650
1da177e4
LT		 2651static int pl011_remove(struct amba_device *dev)
2652{
2653 struct uart_amba_port *uap = amba_get_drvdata(dev);
1da177e4 2654
1da177e4 2655 uart_remove_one_port(&amba_reg, &uap->port);
49bb3c86 2656 pl011_unregister_port(uap);
1da177e4
LT		 2657 return 0;
2658}
2659
d0ce850d
UH		 2660#ifdef CONFIG_PM_SLEEP
2661static int pl011_suspend(struct device *dev)
b736b89f 2662{
d0ce850d 2663 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2664
2665 if (!uap)
2666 return -EINVAL;
2667
2668 return uart_suspend_port(&amba_reg, &uap->port);
2669}
2670
d0ce850d 2671static int pl011_resume(struct device *dev)
b736b89f 2672{
d0ce850d 2673 struct uart_amba_port *uap = dev_get_drvdata(dev);
b736b89f
LC		 2674
2675 if (!uap)
2676 return -EINVAL;
2677
2678 return uart_resume_port(&amba_reg, &uap->port);
2679}
2680#endif
2681
d0ce850d
UH		 2682static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2683
0dd1e247
AP		 2684static int sbsa_uart_probe(struct platform_device *pdev)
2685{
2686 struct uart_amba_port *uap;
2687 struct resource *r;
2688 int portnr, ret;
2689 int baudrate;
2690
2691 /*
2692 * Check the mandatory baud rate parameter in the DT node early
2693 * so that we can easily exit with the error.
2694 */
2695 if (pdev->dev.of_node) {
2696 struct device_node *np = pdev->dev.of_node;
2697
2698 ret = of_property_read_u32(np, "current-speed", &baudrate);
2699 if (ret)
2700 return ret;
2701 } else {
2702 baudrate = 115200;
2703 }
2704
2705 portnr = pl011_find_free_port();
2706 if (portnr < 0)
2707 return portnr;
2708
2709 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2710 GFP_KERNEL);
2711 if (!uap)
2712 return -ENOMEM;
2713
394a9e2c
JS		 2714 ret = platform_get_irq(pdev, 0);
2715 if (ret < 0) {
35aa33cf
KW		 2716 if (ret != -EPROBE_DEFER)
2717 dev_err(&pdev->dev, "cannot obtain irq\n");
394a9e2c
JS		 2718 return ret;
2719 }
2720 uap->port.irq = ret;
2721
439403bd 2722 uap->reg_offset = vendor_sbsa.reg_offset;
d8a4995b
CC		 2723 uap->vendor = qdf2400_e44_present ?
2724 &vendor_qdt_qdf2400_e44 : &vendor_sbsa;
0dd1e247 2725 uap->fifosize = 32;
3b78fae7 2726 uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM;
0dd1e247
AP		 2727 uap->port.ops = &sbsa_uart_pops;
2728 uap->fixed_baud = baudrate;
2729
2730 snprintf(uap->type, sizeof(uap->type), "SBSA");
2731
2732 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2733
2734 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2735 if (ret)
2736 return ret;
2737
2738 platform_set_drvdata(pdev, uap);
2739
2740 return pl011_register_port(uap);
2741}
2742
2743static int sbsa_uart_remove(struct platform_device *pdev)
2744{
2745 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2746
2747 uart_remove_one_port(&amba_reg, &uap->port);
2748 pl011_unregister_port(uap);
2749 return 0;
2750}
2751
2752static const struct of_device_id sbsa_uart_of_match[] = {
2753 { .compatible = "arm,sbsa-uart", },
2754 {},
2755};
2756MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2757
3db9ab0b
GG		 2758static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2759 { "ARMH0011", 0 },
2760 {},
2761};
2762MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2763
0dd1e247
AP		 2764static struct platform_driver arm_sbsa_uart_platform_driver = {
2765 .probe = sbsa_uart_probe,
2766 .remove = sbsa_uart_remove,
2767 .driver = {
2768 .name = "sbsa-uart",
2769 .of_match_table = of_match_ptr(sbsa_uart_of_match),
3db9ab0b 2770 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
0dd1e247
AP		 2771 },
2772};
2773
2c39c9e1 2774static struct amba_id pl011_ids[] = {
1da177e4
LT		 2775 {
2776 .id = 0x00041011,
2777 .mask = 0x000fffff,
5926a295
AR		 2778 .data = &vendor_arm,
2779 },
2780 {
2781 .id = 0x00380802,
2782 .mask = 0x00ffffff,
2783 .data = &vendor_st,
1da177e4 2784 },
2426fbc7
SG		 2785 {
2786 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2787 .mask = 0x00ffffff,
2788 .data = &vendor_zte,
2789 },
1da177e4
LT		 2790 { 0, 0 },
2791};
2792
60f7a33b
DM		 2793MODULE_DEVICE_TABLE(amba, pl011_ids);
2794
1da177e4
LT		 2795static struct amba_driver pl011_driver = {
2796 .drv = {
2797 .name = "uart-pl011",
d0ce850d 2798 .pm = &pl011_dev_pm_ops,
1da177e4
LT		 2799 },
2800 .id_table = pl011_ids,
2801 .probe = pl011_probe,
2802 .remove = pl011_remove,
2803};
2804
2805static int __init pl011_init(void)
2806{
1da177e4
LT		 2807 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2808
0dd1e247
AP		 2809 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2810 pr_warn("could not register SBSA UART platform driver\n");
062a68a5 2811 return amba_driver_register(&pl011_driver);
1da177e4
LT		 2812}
2813
2814static void __exit pl011_exit(void)
2815{
0dd1e247 2816 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
1da177e4 2817 amba_driver_unregister(&pl011_driver);
1da177e4
LT		 2818}
2819
4dd9e742
AR		 2820/*
2821 * While this can be a module, if builtin it's most likely the console
2822 * So let's leave module_exit but move module_init to an earlier place
2823 */
2824arch_initcall(pl011_init);
1da177e4
LT		 2825module_exit(pl011_exit);
2826
2827MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2828MODULE_DESCRIPTION("ARM AMBA serial port driver");
2829MODULE_LICENSE("GPL");
Ubuntu Artful kernel mirror